LTC3776EGN

LTC3776 Dual 2-Phase, No RSENSETM, Synchronous Controller for DDR/QDR Memory Termination U FEATURES DESCRIPTIO ■ The LTC®3776 is a 2-phase dual output synchronous stepdown switching regulator controller for DDR/QDR memory termination applications. The second controller regulates its output voltage to 1/2 VREF while providing symmetrical source and sink output current capability. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ No Current Sense Resistors Required Out-of-Phase Controllers Reduce Required Input Capacitance VOUT2 Tracks 1/2 VREF Symmetrical Source/Sink Output Current Capability (VOUT2) Spread Spectrum Operation (When Enabled) Wide VIN Range: 2.75V to 9.8V Constant Frequency Current Mode Operation 0.6V ±1.5% Voltage Reference (VOUT1) Low Dropout Operation: 100% Duty Cycle True PLL for Frequency Locking or Adjustment Internal Soft-Start Circuitry Power Good Output Voltage Monitor Output Overvoltage Protection Micropower Shutdown: IQ = 9μA Tiny Low Profile (4mm × 4mm) QFN and Narrow SSOP Packages The No RSENSE constant frequency current mode architecture eliminates the need for sense resistors and improves efficiency. Power loss and noise due to the ESR of the input capacitance are minimized by operating the two controllers out of phase. The switching frequency can be programmed up to 750kHz, allowing the use of small surface mount inductors and capacitors. For noise sensitive applications, the LTC3776 switching frequency can be externally synchronized from 250kHz to 850kHz, or can be enabled for spread spectrum operation. Forced continuous operation reduces noise and RF interference. Soft-start for VOUT1 is provided internally and can be extended using an external capacitor. U APPLICATIO S ■ ■ ■ DDR, DDR II and QDR Memory SSTL, HSTL Termination Supplies Servers, RAID Systems Distributed DC Power Systems , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Burst Mode is a registered trademark of Linear Technology Corporation. No RSENSE is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5481178, 5929620, 6144194, 6580258, 6304066, 6611131, 6498466, patent pending on Spread Spectrum. U ■ The LTC3776 is available in the tiny thermally enhanced (4mm × 4mm) QFN package or 24-lead SSOP narrow package. TYPICAL APPLICATIO High Efficiency, 2-Phase, DDR Memory (VDDQ and VTT) Supplies Efficiency vs Load Current VIN 3.3V 10μF ×2 VIN SENSE1+ SENSE2+ TG2 SW1 SW2 90 80 70 EFFICIENCY (%) 1.5μH TG1 100 1.5μH LTC3776 BG1 BG2 PGND (VDDQ)VOUT1 2.5V 4A PGND VFB1 47μF 59k ITH2 SGND 15k VOUT2 (VTT) 1.25V ±4A VFB2 ITH1 470pF 50 40 30 VREF 187k 60 2200pF 47μF 6.2k FIGURE 14 CIRCUIT CHANNEL 2 (VIN = 3.3V) CHANNEL 1 (VIN = 5V) CHANNEL 1 (VIN = 3.3V) CHANNEL 2 (VIN = 5V) 20 10 0 10 100 1000 LOAD CURRENT (mA) 10000 3776 TA01b 3776 TA01a 3776fa 1 LTC3776 W W W AXI U U ABSOLUTE RATI GS (Note 1) Input Supply Voltage (VIN) ........................ – 0.3V to 10V PLLLPF, RUN/SS, SYNC/SSEN, VREF, SENSE1+, SENSE2+, VFB2 IPRG1, IPRG2 Voltages ................. – 0.3V to (VIN + 0.3V) VFB1, ITH1, ITH2 Voltages ........................... – 0.3V to 2.4V SW1, SW2 Voltages .............. –2V to VIN + 1V (10V Max) PGOOD ..................................................... – 0.3V to 10V TG1, TG2, BG1, BG2 Peak Output Current ( fSYNC/FCB fOSC < fSYNC/FCB –4 4 μA μA PGOOD Voltage Low IPGOOD Sinking 1mA 125 mV PGOOD Trip Level VFB with Respect to Set Output Voltage VFB < Regulated Feedback Voltage, Ramping Positive VFB < Regulated Feedback Voltage, Ramping Negative VFB > Regulated Feedback Voltage, Ramping Negative VFB > Regulated Feedback Voltage, Ramping Positive PGOOD Output Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3776E is guaranteed to meet specified performance from 0°C to 70°C. Specifications over the –40°C to 85°C operating range are assured by design, characterization and correlation with statistical process controls. –13 –16 7 10 –10.0 –13.3 10.0 13.3 –7 –10 13 16 % % % % Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: TJ = TA + (PD • θJA°C/W) Note 4: Dynamic supply current is higher due to gate charge being delivered at the switching frequency. Note 5: The LTC3776 is tested in a feedback loop that servos ITH to a specified voltage and measures the resultant VFB voltage. Note 6: Peak current sense voltage is reduced dependent on duty cycle to a percentage of value as shown in Figure 2. 3776fa 3 LTC3776 U W TYPICAL PERFOR A CE CHARACTERISTICS TA = 25°C unless otherwise noted. Step from Sinking to Sourcing Load Current (CH2) Efficiency vs Load Current 100 90 VOUT2 100mV/DIV AC-COUPLED 80 EFFICIENCY (%) 70 60 50 LOAD CURRENT 500mA/DIV 40 30 FIGURE 14 CIRCUIT CHANNEL 2 (VIN = 3.3V) CHANNEL 1 (VIN = 5V) CHANNEL 1 (VIN = 3.3V) CHANNEL 2 (VIN = 5V) 20 10 0 10 100 1000 LOAD CURRENT (mA) 20μs/DIV VIN = 3.3V FIGURE 14 CIRCUIT 3776 G02 10000 3776 G01 Tracking Start-Up with Internal Soft-Start (CSS = 0μF) Load Step (Load Connected Between VOUT1 and VOUT2) VOUT1 100mV/DIV AC-COUPLED VOUT1 = 2.5V 500mV/DIV VOUT2 100mV/DIV AC-COUPLED VOUT2 = 1.25V LOAD CURRENT 1A/DIV 3776 G03 20μs/DIV VIN = 3.3V FIGURE 14 CIRCUIT VOUT1 SOURCING VOUT2 SINKING 500μs/DIV VIN = 3.3V FIGURE 14 CIRCUIT Tracking Start-Up with External Soft-Start (CSS = 0.15μF) Oscillator Frequency vs Input Voltage Maximum Current Sense Voltage vs ITH1 Pin Voltage (CH1) 4ms/DIV VIN = 3.3V FIGURE 14 CIRCUIT 3776 G05 100 4 80 3 CURRENT LIMIT (%) 500mV/DIV VOUT2 = 1.25V NORMALIZED FREQUENCY SHIFT (%) 5 VOUT1 = 2.5V 3776 G04 2 1 0 –1 –2 –3 60 40 20 0 –4 –5 2 3 4 8 6 5 7 INPUT VOLTAGE (V) 9 –20 10 3736 G06 0.5 1 1.5 ITH VOLTAGE (V) 2 3776 G07 3776fa 4 LTC3776 U W TYPICAL PERFOR A CE CHARACTERISTICS Regulated Feedback Voltage (CH2) vs Temperature Maximum Current Sense Voltage vs ITH2 Pin Voltage (CH2) 1.2625 80 1.2600 Regulated Feedback Voltage (CH1) vs Temperature 0.612 VREF = 2.500V FEEDBACK VOLTAGE (VFB1) (V) FEEDBACK VOLTAGE (VFB2) (V) 100 1.2575 60 CURRENT LIMIT (%) TA = 25°C unless otherwise noted. 1.2550 40 1.2525 20 1.2500 0 1.2475 –20 1.2450 –40 1.2425 –60 –100 0 2.0 1.5 1.0 ITH2 VOLTAGE (V) 1.2375 –60 –40 –20 0 20 40 60 TEMPERATURE (°C) 80 0.596 0.592 100 1.0 RUN/SS PULL-UP CURRENT (μA) 0.7 0.6 0.5 0.4 0.3 0.2 0.9 0.8 0.7 0.6 0.5 0.1 80 0.4 –60 –40 –20 0 20 40 60 TEMPERATURE (°C) 100 80 100 Maximum Current Sense Threshold (CH2) vs Temperature 2.45 6 4 2 0 –2 –4 –6 80 100 3776 G14 –10 –60 –40 –20 0 20 40 60 TEMPERATURE (°C) 80 100 VIN RISING 2.40 2.35 2.30 VIN FALLING 2.25 2.20 2.15 –8 125 20 40 60 –60 –40 –20 0 TEMPERATURE (°C) 115 –60 –40 –20 0 20 40 60 TEMPERATURE (°C) 2.50 INPUT (VIN) VOLTAGE (V) NROMALIZED FREQUENCY (%) 130 120 Undervoltage Lockout Threshold vs Temperature 8 135 125 3736 G13 10 140 IPRG1 = FLOAT 130 Oscillator Frequency vs Temperature IPRG2 = FLOAT 145 135 3736 G12 3736 G11 100 Maximum Current Sense Threshold (CH1) vs Temperature 1.0 0.8 80 3776 G10 RUN/SS Pull-Up Current vs Temperature 0.9 0 –60 –40 –20 0 20 40 60 TEMPERATURE (°C) 0.588 –60 –40 –20 0 20 40 60 TEMPERATURE (°C) MAXIMUM CURRENT SENSE THRESHOLD (mV) Shutdown (RUN) Threshold vs Temperature RUN/SS VOLTAGE (V) 0.600 3776 G09 3776 G08 MAXIMUM CURRENT SENSE THRESHOLD (mV) 0.604 1.2400 –80 150 0.608 80 100 3736 G15 2.10 20 40 60 –60 –40 –20 0 TEMPERATURE (°C) 80 100 3736 G16 3776fa 5 LTC3776 U W TYPICAL PERFOR A CE CHARACTERISTICS Shutdown Quiescent Current vs Input Voltage SHUTDOWN CURRENT (μA) RUN/SS Start-Up Current vs Input Voltage 0.9 RUN/SS = 0V RUN/SS PIN PULL-UP CURRENT (μA) 20 18 16 14 12 10 8 6 4 2 0 2 3 4 8 6 5 7 INPUT VOLTAGE (V) 9 10 3736 G17 U U U PI FU CTIO S TA = 25°C unless otherwise noted. RUN/SS = 0V 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 2 3 4 6 7 5 8 INPUT VOLTAGE (V) 9 10 3736 G18 (UF/GN Package) ITH1/ITH2 (Pins 1, 8/ Pins 4, 11): Current Threshold and Error Amplifier Compensation Point. Nominal operating range on these pins is from 0.7V to 2V. The voltage on these pins determines the threshold of the main current comparator. PLLLPF (Pin 3/Pin 6): Frequency Set/PLL Lowpass Filter. When synchronizing to an external clock, this pin serves as the lowpass filter point for the phase-locked loop. Normally a series RC is connected between this pin and ground. When SYNC/SSEN is tied to GND, this pin serves as the frequency select input. Tying this pin to GND selects 300kHz operation; tying this pin to VIN selects 750kHz operation. Floating this pin selects 550kHz operation. When SYNC/ SSEN is tied to VIN to enable spread spectrum operation, a capacitor (1nF to 4.7nF) should be connected from this pin to SGND to filter and smooth the changes in frequency of the LTC3776’s internal oscillator. SGND (Pin 4/Pin 7): Small-Signal Ground. This pin serves as the ground connection for most internal circuits. VIN (Pin 5/Pin 8): Chip Signal Power Supply. This pin powers the entire chip except for the gate drivers. Externally filtering this pin with a lowpass RC network (e.g., R = 10Ω, C = 1μF) is suggested to minimize noise pickup, especially in high load current applications. VREF (Pin 6/Pin 9): Reference voltage input for channel 2. The positive input of the error amplifier for channel 2 senses one half of the voltage on this pin through an internal resistor divider. PGOOD (Pin 9/Pin 12): Power Good Output Voltage Monitor Open-Drain Logic Output. This pin is pulled to ground when the voltage on either feedback pin (VFB1, VFB2) is not within ±13.3% of its nominal set point. PGND (Pins 12, 16, 20, 25/ Pins 15, 19, 23): Power Ground. These pins serve as the ground connection for the gate drivers and the negative input to the reverse current comparators. The Exposed Pad (UF package) must be soldered to PCB ground. RUN/SS (Pin 14/Pin 17): Run Control Input and Optional External Soft-Start Input. Forcing this pin below 0.65V shuts down the chip (both channels). Driving this pin to VIN or releasing this pin enables the chip, using the chip’s internal soft-start. An external soft-start can be programmed by connecting a capacitor between this pin and ground. TG1/TG2 (Pins 17, 15/Pins 20, 18): Top (PMOS) Gate Drive Output. These pins drive the gates of the external P-channel MOSFETs. These pins have an output swing from PGND to SENSE+. SYNC/SSEN (Pin 18/Pin 21): Synchronization Input and Spread Spectrum Modulation Enable Input. To synchronize the LTC3776’s switching frequency to an external clock 3776fa 6 LTC3776 U U U PI FU CTIO S (UF/GN Package) using the phase-locked loop, apply a CMOS compatible clock with a frequency between 250kHz and 850kHz to this pin. Tie this pin to GND to enable constant frequency operation (300kHz, 550kHz or 750kHz as determined by the state of the PLLLPF pin). Tie this pin to VIN to enable spread spectrum operation. In spread spectrum mode, the LTC3776’s frequency is randomly varied between 450kHz and 580kHz. BG1/BG2 (Pins 19, 13/Pins 22, 16): Bottom (NMOS) Gate Drive Output. These pins drive the gates of the external Nchannel MOSFETs. These pins have an output swing from PGND to SENSE+. SENSE1+/SENSE2+ (Pins 21, 11/Pins 24, 14): Positive Input to Differential Current Comparator. Also powers the gate drivers. Normally connected to the source of the external P-channel MOSFET. SW1/SW2 (Pins 22, 10/Pins 1, 13): Switch Node Connection to Inductor. Also the negative input to differential peak current comparator and an input to the reverse current comparator. Normally connected to the drain of the external P-channel MOSFETs, the drain of the external N-channel MOSFET and the inductor. IPRG1/IPRG2 (Pins 23, 2/Pins 2, 5): Three-State Pins to Select Maximum Peak Sense Voltage Threshold. These pins select the maximum allowed voltage drop between the SENSE+ and SW pins (i.e., the maximum allowed drop across the external P-channel MOSFET) for each channel. Tie to VIN, GND or float to select one of three discrete levels. VFB1/VFB2 (Pins 24, 7/Pins 3, 10): Feedback Pins. Receives the remotely sensed feedback voltage for its controller. Exposed Pad (Pin 25/NA): The Exposed Pad (UF Package) must be soldered to the PCB ground. W FU CTIO AL DIAGRA (Common Circuitry) U RVIN VIN UNDERVOLTAGE LOCKOUT CVIN VOLTAGE REFERENCE VIN (TO CONTROLLER 1, 2) 0.6V VREF 0.7μA SHDN RUN/SS EXTSS tSEC = 1ms + INTSS – SYNC/SSEN PLLLPF SYNC DETECT/ SPREAD SPECTRUM ENABLE VOLTAGE CONTROLLED OSCILLATOR PHASE DETECTOR CLK1 CLK2 SLOPE1 SLOPE COMP VFB1 SLOPE2 – UV1 0.54V + PGOOD OV1 SHDN IPRG1 IPRG2 VOLTAGE MAXIMUM CONTROLLED SENSE VOLTAGE OSCILLATOR SELECT IPROG1 IPROG2 0.9 • VREF/2 + VFB2 – UV2 OV2 3776 FD 3776fa 7 U LTC3776 W FU CTIO AL DIAGRA U (Controller 1) U VIN SENSE1+ CIN RS1 CLK1 S TG1 MP1 Q R SWITCHING LOGIC AND BLANKING CIRCUIT OV1 SC1 PGND SW1 ANTISHOOT THROUGH L1 VOUT1 SENSE1+ COUT1 BG1 MN1 PGND SLOPE1 SW1 – ICMP SENSE1+ + IPROG1 SHDN – + VFB1 R1B EAMP + R1A – 0.6V ITH1 EXTSS INTSS RITH1 + OV1 VFB1 SC1 OVP – 0.68V + 0.12V – VFB1 CITH1 SCP 3776fa 8 LTC3776 W FU CTIO AL DIAGRA U (Controller 2) U SENSE2+ RS2 CLK2 TG2 MP2 Q S VIN R SWITCHING LOGIC AND BLANKING CIRCUIT OV2 SC2 PGND SW2 ANTISHOOT THROUGH L2 SENSE2+ VOUT2 COUT2 BG2 MN2 PGND SLOPE2 SW2 – ICMP SENSE2+ SHDN + VFB2 – + 40k EAMP + VREF 40k – 120k 40k ITH2 RITH2 + OV2 VFB2 SC2 OVP – VREF/8 – VFB2/2 CITH2 SCP 1.1 • VREF/2 SHORT1 U OPERATIO + 3776 CONT2 (Refer to Functional Diagram) Main Control Loop The LTC3776 uses a constant frequency, current mode architecture with the two controllers operating 180 degrees out of phase. During normal operation, the top external P-channel power MOSFET is turned on when the clock for that channel sets the RS latch, and turned off when the current comparator (ICMP) resets the latch. The peak inductor current at which ICMP resets the RS latch is determined by the voltage on the ITH pin, which is driven by the output of the error amplifier (EAMP). The VFB pin receives the output voltage feedback signal from an external resistor divider. This feedback signal is compared to a reference (either the internal 0.6V reference for controller 1 or the divided down VREF pin for CH2) by the EAMP. 3776fa 9 LTC3776 U OPERATIO (Refer to Functional Diagram) When the load current increases, it causes a slight decrease in VFB relative to the reference, which in turn causes the ITH voltage to increase until the average inductor current matches the new load current. While the top P-channel MOSFET is off, the bottom N-channel MOSFET is turned on until the beginning of the next cycle. Shutdown, Soft-Start and Tracking Start-Up (RUN/SS and TRACK Pins) The LTC3776 is shut down by pulling the RUN/SS pin low. In shutdown, all controller functions are disabled and the chip draws only 9μA. The TG outputs are held high (off) and the BG outputs low (off) in shutdown. Releasing RUN/SS allows an internal 0.7μA current source to charge up the RUN/SS pin. When the RUN/SS pin reaches 0.65V, the LTC3776’s two controllers are enabled. The start-up of VOUT1 is controlled by the LTC3776’s internal soft-start. During soft-start, the error amplifier EAMP compares the feedback signal VFB1 to the internal soft-start ramp (instead of the 0.6V reference), which rises linearly from 0V to 0.6V in about 1ms. This allows the output voltage to rise smoothly from 0V to its final value, while maintaining control of the inductor current. The 1ms soft-start time can be increased by connecting the optional external soft-start capacitor CSS between the RUN/SS and SGND pins. As the RUN/SS pin continues to rise linearly from approximately 0.65V to 1.25V (being charged by the internal 0.7μA current source), the EAMP regulates the VFB1 proportionally linearly from 0V to 0.6V. The start-up of VOUT2 is controlled by the voltage on the VREF pin. Typically, VOUT1 is connected to the VREF pin to allow the start-up of VOUT2 to “track” that of 1/2 VOUT1. Note that if either VOUT1 or VOUT2 is less than 90% (lower PGOOD threshold) of its regulation point (in either a startup or short-circuit condition), then channel one’s inductor current is not allowed to reverse (i.e., discontinuous operation is forced). This is to prevent a minimum ontime condition during startup. Short-Circuit Protection When an output is shorted to ground, the switching frequency of that controller is reduced to 1/5 of the normal operating frequency. The short-circuit threshold on VFB2 is based on the smaller of 0.12V and a fraction of the voltage on the VREF pin. This also allows VOUT2 to start up and track VOUT1 more easily. Note that if VOUT1 is truly short-circuited (VOUT1 = VFB1 = 0V), then the LTC3776 will try to regulate VOUT2 to 0V if VOUT1 is connected to the VREF pin. Output Overvoltage Protection As further protection, the overvoltage comparator (OV) guards against transient overshoots, as well as other more serious conditions that may overvoltage the output. When the feedback voltage on the VFB pin has risen 13.33% above its resolution point, the external P-channel MOSFET is turned off and the N-channel MOSFET is turned on until the overvoltage is cleared. Frequency Selection and Phase-Locked Loop (PLLLPF and SYNC/SSEN Pins) The selection of switching frequency is a tradeoff between efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. The switching frequency of the LTC3776’s controllers can be selected using the PLLLPF pin. If the SYNC/SSEN pin is tied to ground, the PLLLPF pin can be floated, tied to VIN, or tied to SGND to select 550kHz, 750kHz, or 300kHz constant frequency operation, respectively. A phase-locked loop (PLL) is available on the LTC3776 to synchronize the internal oscillator to an external clock source that connected to the SYNC/SSEN pin. In this case, a series RC should be connected between the PLLLPF pin and SGND to serve as the PLL’s loop filter. The LTC3776 3776fa 10 LTC3776 U OPERATIO (Refer to Functional Diagram) phase detector adjusts the voltage on the PLLLPF pin to align the turn-on of controller 1’s external P-channel MOSFET to the rising edge of the synchronizing signal. Thus, the turn-on of controller 2’s external P-channel MOSFET is 180 degrees out of phase with the rising edge of the external clock source. The typical capture range of the LTC3776’s phase-locked loop is from approximately 200kHz to 1MHz, with a guarantee over all process variations and temperature to be between 250kHz and 850kHz. In other words, the LTC3776’s PLL is guaranteed to lock to an external clock source whose frequency is between 250kHz and 850kHz. Alternatively, the SYNC/SSEN pin may be tied to VIN to –10 Spread Spectrum Operation Switching regulators can be particularly troublesome in applications where electromagnetic interference (EMI) is a concern. Switching regulators operate on a cycle-bycycle basis to transfer power to an output. In most cases, the frequency of operation is either fixed or is a constant based on the output load. This method of conversion creates large components of noise at the frequency of operation (fundamental) and multiples of the operating frequency (harmonics). Figures 1a and 1b depict the –10 RBW = 3kHz –20 –20 –30 –30 –40 –40 AMPLITUDE (dBm) AMPLITUDE (dBm) enable spread spectrum operation (see Spread Spectrum Operation section). –50 –60 –70 –80 –50 –60 –70 –80 –90 –90 –100 –100 –110 0 6 12 18 FREQUENCY (MHz) 24 30 –10 –20 –30 –40 –40 AMPLITUDE (dBm) –30 –50 –60 –70 –80 24 30 37361 F01c Figure 1c. Output Noise Spectrum of the LTC3776 Spread Spectrum Buck Switching Converter. Note the Reduction in Fundamental and Harmonic Peak Spectral Amplitude Compared to Figure 1a. RBW = 30Hz –70 –90 12 18 FREQUENCY (MHz) 610 37361 F01b –80 –100 6 570 –60 –90 –110 490 530 FREQUENCY (kHz) –50 –100 0 450 Figure 1b. Zoom-In of Fundamental Frequency of Conventional Buck Switching Converter RBW = 1kHz –20 AMPLITUDE (dBm) –110 410 37361 F01a Figure 1a. Output Noise Spectrum of Conventional Buck Switching Converter (LTC3776 with Spread Spectrum Disabled) Showing Fundamental and Harmonic Frequencies –10 RBW = 30Hz –110 410 450 490 530 FREQUENCY (kHz) 570 610 37361 F01d Figure 1d. Zoom-In of Fundamental Frequency of the LTC3776 Spread Spectrum Switching Converter. Note the >20dB Reduction in Peak Amplitude and Spreading of the Frequency Spectrum (Between Approximately 450kHz and 580kHz) Compared to Figure 1b. 3776fa 11 LTC3776 (Refer to Functional Diagram) output noise spectrum of a conventional buck switching converter (1/2 of LTC3776 with spread spectrum operation disabled) with VIN = 5V, VOUT = 2.5V and IOUT = 2A. Unlike conventional buck converters, the LTC3776’s internal oscillator can be selected to produce a clock pulse whose frequency is randomly varied between 450kHz and 580kHz by tying the SYNC/SSEN pin to VIN. This has the benefit of spreading the switching noise over a range of frequencies, thus significantly reducing the peak noise. Figures 1c and 1d show the output noise spectrum of the LTC3776 (with spread spectrum operation enabled) with VIN = 5V, VOUT = 2.5V and IOUT = 1A. Note the significant reduction in peak output noise (>20dBm). Dropout Operation When the input supply voltage (VIN) decreases towards the output voltage, the rate of change of the inductor current while the external P-channel MOSFET is on (ON cycle) decreases. This reduction means that the P-channel MOSFET will remain on for more than one oscillator cycle if the inductor current has not ramped up to the threshold set by the EAMP on the ITH pin. Further reduction in the input supply voltage will eventually cause the P-channel MOSFET to be turned on 100%; i.e., DC. The output voltage will then be determined by the input voltage minus the voltage drop across the P-channel MOSFET and the inductor. Undervoltage Lockout To prevent operation of the external MOSFETs below safe input voltage levels, an undervoltage lockout is incorporated in the LTC3776. When the input supply voltage (VIN) drops below 2.3V, the external P- and N-channel MOSFETs and all internal circuitry are turned off except for the undervoltage block, which draws only a few microamperes. Peak Current Sense Voltage Selection and Slope Compensation (IPRG1 and IPRG2 Pins) When controller 1 is operating below 20% duty cycle, the peak current sense voltage (between the SENSE1+ and SW1 pins) allowed across the external P-channel MOSFET is determined by: ΔVSENSE(MAX)1 = A1(VITH1 – 0.7V ) 10 where A1 is a constant determined by the state of the IPRG pins. Floating the IPRG1 pin selects A1 = 1; tying IPRG to VIN selects A1 = 5/3; tying IPRG1 to SGND selects A1 = 2/3. The maximum value of VITH1 is typically about 1.98V, so the maximum sense voltage allowed across the external P-channel MOSFET is 125mV, 85mV or 204mV for the three respective states of the IPRG1 pin. When controller 2 is operating below 20% duty cycle, the peak current sense voltage (between the SENSE2+ and SW2 pins) allowed across the external P-channel MOSFET is determined by: A2(VITH2 – 1.3V ) , VITH2 ≥ 1.3V 4.6 A2(VITH2 – 1.3V ) ΔVSENSE(MAX) = , VITH2 < 1.3V 5.4 where A is a constant determined by the state of the IPRG pins. Floating the IPRG2 pin selects A2 = 1; tying IPRG2 to VIN selects A = 5/3; tying IPRG2 to SGND selects A2 = 2/3. The maximum value of VITH2 is typically about 1.98V, so the maximum sense voltage allowed across the external P-channel MOSFET is 147mV, 100mV or 245mV for the three respective states of the IPRG2 pin. The minimum value of VITH2 is typically about 0.7V, so the minimum (most negative) peak sense voltage is –112mV, –75mV or –188mV, respectively. ΔVSENSE(MAX) = However, once the controller’s duty cycle exceeds 20%, slope compensation begins and effectively reduces the peak sense voltage by a scale factor given by the curve in Figure 2. 110 100 90 80 SF = I/IMAX (%) U OPERATIO 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 80 90 100 DUTY CYCLE (%) 3776 F02 Figure 2. Maximum Peak Current vs Duty Cycle 3776fa 12 LTC3776 U OPERATIO (Refer to Functional Diagram) The peak inductor current is determined by the peak sense voltage and the on-resistance of the external P-channel MOSFET: IPK = ΔVSENSE(MAX) RDS(ON) Power Good (PGOOD) Pin A window comparator monitors both feedback voltages and the open-drain PGOOD output pin is pulled low when either or both feedback voltages are not within ±10% of their reference voltages. PGOOD is low when the LTC3776 is shut down or in undervoltage lockout. 2-Phase Operation Why the need for 2-phase operation? Until recently, constant frequency dual switching regulators operated both controllers in phase (i.e., single phase operation). This means that both topside MOSFETs (P-channel) are turned on at the same time, causing current pulses of up to twice the amplitude of those from a single regulator to be drawn from the input capacitor. These large amplitude pulses increase the total RMS current flowing in the input capacitor, requiring the use of larger and more expensive input capacitors, and increase both EMI and power losses in the input capacitor and input power supply. With 2-phase operation, the two controllers of the LTC3776 are operated 180 degrees out of phase. This effectively interleaves the current pulses coming from the topside MOSFET switches, greatly reducing the time where they overlap and add together. The result is a significant reduction in the total RMS current, which in turn allows the use of smaller, less expensive input capacitors, reduces shielding requirements for EMI and improves real world operating efficiency. Figure 3 shows qualitatively example waveforms for a single phase dual controller versus a 2-phase LTC3776 system. In this case, 2.5V and 1.8V outputs, each drawing a load current of 2A, are derived from a 7V (e.g., a 2-cell Li-Ion battery) input supply. In this example, 2-phase operation would reduce the RMS input capacitor current from 1.79ARMS to 0.91ARMS. While this is an impressive reduction by itself, remember that power losses are proportional to IRMS2, meaning that actual power wasted is reduced by a factor of 3.86. The reduced input ripple current also means that less power is lost in the input power path, which could include batteries, switches, trace/connector resistances, and protection circuitry. Improvements in both conducted and radiated EMI also directly accrue as a result of the reduced RMS input current and voltage. Significant cost and board footprint savings are also realized by being able to use smaller, less expensive, lower RMS current-rated input capacitors. Single Phase Dual Controller 2-Phase Dual Controller SW1 (V) SW2 (V) IL1 IL2 IIN 3776 F03 Figure 3. Example Waveforms for a Single Phase Dual Controller vs the 2-Phase LTC3776 Of course, the improvement afforded by 2-phase operation is a function of the relative duty cycles of the two controllers, which in turn are dependent upon the input supply voltage. Figure 4 depicts how the RMS input current varies for single phase and 2-phase dual controllers with 2.5V and 1.8V outputs over a wide input voltage range. It can be readily seen that the advantages of 2-phase operation are not limited to a narrow operating range, but in fact extend over a wide region. A good rule of thumb for most applications is that 2-phase operation will reduce the input capacitor requirement to that for just one channel operating at maximum current and 50% duty cycle. 3776fa 13 LTC3776 U W U U APPLICATIO S I FOR ATIO inductor current is limited by the current threshold, set by the voltage on the ITH pin of the current comparator. The voltage on the ITH pin is internally clamped, which limits the maximum current sense threshold ΔVSENSE(MAX). 2.0 INPUT CAPACITOR RMS CURRENT 1.8 SINGLE PHASE DUAL CONTROLLER 1.6 1.4 2-PHASE DUAL CONTROLLER 1.2 1.0 The output current that the LTC3776 can provide is given by: 0.8 0.6 0.4 IOUT(MAX) = VOUT1 = 2.5V/2A VOUT2 = 1.8V/2A 0.2 0 2 3 4 8 6 5 7 INPUT VOLTAGE (V) 9 10 3776 F04 Figure 4. RMS Input Current Comparison The typical LTC3776 application circuit is shown in Figure 11. External component selection for each of the LTC3776’s controllers is driven by the load requirement and begins with the selection of the inductor (L) and the power MOSFETs (MP and MN). Power MOSFET Selection Each of the LTC3776’s two controllers requires two external power MOSFETs: a P-channel MOSFET for the topside (main) switch and an N-channel MOSFET for the bottom (synchronous) switch. Important parameters for the power MOSFETs are the breakdown voltage VBR(DSS) , threshold voltage VGS(TH), on-resistance RDS(ON) , reverse transfer capacitance CRSS, turn-off delay tD(OFF) and the total gate charge QG. The gate drive voltage is the input supply voltage. Since the LTC3776 is designed for operation down to low input voltages, a sublogic level MOSFET (RDS(ON) guaranteed at VGS = 2.5V) is required for applications that work close to this voltage. When these MOSFETs are used, make sure that the input supply to the LTC3776 is less than the absolute maximum MOSFET VGS rating, which is typically 8V. The P-channel MOSFET’s on-resistance is chosen based on the required load current. The maximum average output load current IOUT(MAX) is equal to the peak inductor current minus half the peak-to-peak ripple current IRIPPLE. The LTC3776’s current comparator monitors the drain-tosource voltage VDS of the P-channel MOSFET, which is sensed between the SENSE+ and SW pins. The peak ΔVSENSE(MAX) IRIPPLE – RDS(ON) 2 A reasonable starting point is setting ripple current IRIPPLE to be 40% of IOUT(MAX). Rearranging the above equation yields: RDS(ON)(MAX) = 5 ΔVSENSE(MAX) • 6 IOUT(MAX) for Duty Cycle < 20%. However, for operation above 20% duty cycle, slope compensation has to be taken into consideration to select the appropriate value of RDS(ON) to provide the required amount of load current: RDS(ON)(MAX) = ΔVSENSE(MAX) 5 • SF • 6 IOUT(MAX) where SF is a scale factor whose value is obtained from the curve in Figure 2. These must be further derated to take into account the significant variation in on-resistance with temperature. The following equation is a good guide for determining the required RDS(ON)MAX at 25°C (manufacturer’s specification), allowing some margin for variations in the LTC3776 and external component values: RDS(ON)(MAX) = ΔVSENSE(MAX) 5 • 0.9 • SF • 6 IOUT(MAX) • ρT The ρT is a normalizing term accounting for the temperature variation in on-resistance, which is typically about 0.4%/°C, as shown in Figure 5. Junction to case temperature TJC is about 10°C in most applications. For a maximum ambient temperature of 70°C, using ρ80°C ~ 1.3 in the above equation is a reasonable choice. 3776fa 14 LTC3776 U W U U APPLICATIO S I FOR ATIO Reasonable starting criteria for selecting the P-channel MOSFET are that it must typically have a gate charge (QG) less than 25nC to 30nC (at 4.5VGS) and a turn-off delay (tD(OFF)) of less than approximately 140ns. However, due to differences in test and specification methods of various MOSFET manufacturers, and in the variations in QG and tD(OFF) with gate drive (VIN) voltage, the P-channel MOSFET ultimately should be evaluated in the actual LTC3776 application circuit to ensure proper operation. ρT NORMALIZED ON RESISTANCE 2.0 1.5 1.0 0.5 0 – 50 50 100 0 JUNCTION TEMPERATURE (°C) 150 3776 F07 Figure 5. RDS(ON) vs Temperature The power dissipated in the top and bottom MOSFETs strongly depends on their respective duty cycles and load current. When the LTC3776 is operating in continuous mode, the duty cycles for the MOSFETs are: VOUT VIN V –V Bottom N-Channel Duty Cycle = IN OUT VIN Top P-Channel Duty Cycle = The MOSFET power dissipations at maximum output current are: PTOP PBOT V = OUT • IOUT (MAX)2 • ρT • RDS(ON) + 2 • VIN2 VIN • IOUT (MAX) • C RSS • fOSC V –V = IN OUT • IOUT (MAX)2 • ρT • RDS(ON) VIN Both MOSFETs have I2R losses and the PTOP equation includes an additional term for transition losses, which are largest at high input voltages. The bottom MOSFET losses are greatest at high input voltage or during a short circuit when the bottom duty cycle is nearly 100%. The LTC3776 utilizes a nonoverlapping, antishoot-through gate drive control scheme to ensure that the P- and N-channel MOSFETs are not turned on at the same time. To function properly, the control scheme requires that the MOSFETs used are intended for DC/DC switching applications. Many power MOSFETs, particularly P-channel MOSFETs, are intended to be used as static switches and therefore are slow to turn on or off. Shoot-through between the P-channel and N-channel MOSFETs can most easily be spotted by monitoring the input supply current. As the input supply voltage increases, if the input supply current increases dramatically, then the likely cause is shoot-through. Note that some MOSFETs that do not work well at high input voltages (e.g., VIN > 5V) may work fine at lower voltages (e.g., 3.3V). Table 1 shows a selection of P-channel MOSFETs from different manufacturers that are known to work well in LTC3776 applications. Selecting the N-channel MOSFET is typically easier, since for a given RDS(ON), the gate charge and turn-on and turnoff delays are much smaller than for a P-channel MOSFET. Table 1. Selected P-Channel MOSFETs Suitable for LTC3776 Applications PART NUMBER MANUFACTURER TYPE PACKAGE Si7540DP Siliconix Complementary P/N PowerPak SO-8 Si9801DY Siliconix Complementary P/N SO-8 FDW2520C Fairchild Complementary P/N TSSOP-8 FDW2521C Fairchild Complementary P/N TSSOP-8 Si3447BDV Siliconix Single P TSOP-6 Si9803DY Siliconix Single P SO-8 FDC602P Fairchild Single P TSOP-6 FDC606P Fairchild Single P TSOP-6 FDC638P Fairchild Single P TSOP-6 FDW2502P Fairchild Dual P TSSOP-8 FDS6875 Fairchild Dual P SO-8 HAT1054R Hitachi Dual P SO-8 On Semi Dual P SO-8 NTMD6P02R2-D 3776fa 15 LTC3776 U W U U APPLICATIO S I FOR ATIO Operating Frequency and Synchronization The choice of operating frequency, fOSC, is a trade-off between efficiency and component size. Low frequency operation improves efficiency by reducing MOSFET switching losses, both gate charge loss and transition loss. However, lower frequency operation requires more inductance for a given amount of ripple current. The internal oscillator for each of the LTC3776’s controllers runs at a nominal 550kHz frequency when the PLLLPF pin is left floating and the SYNC/SSEN pin is tied to GND. Pulling the PLLLPF to VIN selects 750kHz operation; pulling the PLLLPF to GND selects 300kHz operation. Alternatively, the LTC3776 will phase-lock to a clock signal applied to the SYNC/SSEN pin with a frequency between 250kHz and 850kHz (see Phase-Locked Loop and Frequency Synchronization). When spread spectrum operation is enabled (SYNC/ SSEN = VIN), the frequency of the LTC3776 is randomly varied over the range of frequencies between 450kHz and 580kHz. In this case, a capacitor (1nF to 4.7nF) should be connected between the FREQ pin and SGND to smooth out the changes in frequency. This not only provides a smoother frequency spectrum but also ensures that the switching regulator remains stable by preventing abrupt changes in frequency. A value of 2200pF is suitable in most applications. Inductor Value Calculation Given the desired input and output voltages, the inductor value and operating frequency fOSC directly determine the inductor’s peak-to-peak ripple current: IRIPPLE = VOUT ⎛ VIN – VOUT ⎞ ⎜ ⎟ VIN ⎝ fOSC • L ⎠ Lower ripple current reduces core losses in the inductor, ESR losses in the output capacitors, and output voltage ripple. Thus, highest efficiency operation is obtained at low frequency with a small ripple current. Achieving this, however, requires a large inductor. A reasonable starting point is to choose a ripple current that is about 40% of IOUT(MAX). Note that the largest ripple current occurs at the highest input voltage. To guarantee that ripple current does not exceed a specified maximum, the inductor should be chosen according to: L≥ VIN – VOUT VOUT • fOSC • IRIPPLE VIN Inductor Core Selection Once the inductance value is determined, the type of inductor must be selected. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Different core materials and shapes will change the size/ current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don’t radiate much energy, but generally cost more than powdered iron core inductors with similar characteristics. The choice of which style inductor to use mainly depends on the price vs size requirements and any radiated field/EMI requirements. New designs for surface mount inductors are available from Coiltronics, Coilcraft, Toko and Sumida. Schottky Diode Selection (Optional) The Schottky diodes D1 and D2 in Figure 16 conduct current during the dead time between the conduction of the power MOSFETs . This prevents the body diode of the bottom N-channel MOSFET from turning on and storing charge during the dead time, which could cost as much as 1% in efficiency. A 1A Schottky diode is generally a good Kool Mμ is a registered trademark of Magnetics, Inc. 3776fa 16 LTC3776 U W U U APPLICATIO S I FOR ATIO size for most LTC3776 applications, since it conducts a relatively small average current. Larger diodes result in additional transition losses due to their larger junction capacitance. This diode may be omitted if the efficiency loss can be tolerated. CIN and COUT Selection The selection of CIN is simplified by the 2-phase architecture and its impact on the worst-case RMS current drawn through the input network (battery/fuse/capacitor). It can be shown that the worst-case capacitor RMS current occurs when only one controller is operating. The controller with the highest (VOUT)(IOUT) product needs to be used in the formula below to determine the maximum RMS capacitor current requirement. Increasing the output current drawn from the other controller will actually decrease the input RMS ripple current from its maximum value. The out-of-phase technique typically reduces the input capacitor’s RMS ripple current by a factor of 30% to 70% when compared to a single phase power supply solution. In continuous mode, the source current of the P-channel MOSFET is a square wave of duty cycle (VOUT)/(VIN). To prevent large voltage transients, a low ESR capacitor sized for the maximum RMS current of one channel must be used. The maximum RMS capacitor current is given by: CIN Required IRMS ≈ [ ] 1/ 2 IMAX VOUT )( VIN – VOUT ) ( VIN This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturers’ ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may be paralleled to meet size or height requirements in the design. Due to the high operating frequency of the LTC3776, ceramic capacitors can also be used for CIN. Always consult the manufacturer if there is any question. The benefit of the LTC3776 2-phase operation can be calculated by using the equation above for the higher power controller and then calculating the loss that would have resulted if both controller channels switched on at the same time. The total RMS power lost is lower when both controllers are operating due to the reduced overlap of current pulses required through the input capacitor’s ESR. This is why the input capacitor’s requirement calculated above for the worst-case controller is adequate for the dual controller design. Also, the input protection fuse resistance, battery resistance, and PC board trace resistance losses are also reduced due to the reduced peak currents in a 2-phase system. The overall benefit of a multiphase design will only be fully realized when the source impedance of the power supply/battery is included in the efficiency testing. The sources of the P-channel MOSFETs should be placed within 1cm of each other and share a common CIN(s). Separating the sources and CIN may produce undesirable voltage and current resonances at VIN. A small (0.1μF to 1μF) bypass capacitor between the chip VIN pin and ground, placed close to the LTC3776, is also suggested. A 10Ω resistor placed between CIN (C1) and the VIN pin provides further isolation between the two channels. The selection of COUT is driven by the effective series resistance (ESR). Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering. The output ripple (ΔVOUT) is approximated by: ⎛ 1 ⎞ ΔVOUT ≈ IRIPPLE⎜ ESR + ⎟ ⎝ 8fC OUT ⎠ where f is the operating frequency, COUT is the output capacitance and IRIPPLE is the ripple current in the inductor. The output ripple is highest at maximum input voltage since IRIPPLE increases with input voltage. Setting Output Voltage The LTC3776’s channel 1 output voltage is set by an external feedback resistor divider carefully placed across the output, as shown in Figure 6. The regulated output voltage is determined by: ⎛ R ⎞ VOUT 1 = 0.6V • ⎜ 1 + B ⎟ ⎝ RA ⎠ 3776fa 17 LTC3776 U W U U APPLICATIO S I FOR ATIO Channel 2’s output voltage is set to 1/2 VREF by connecting the VFB2 pin to VOUT2. To improve the frequency response, a feed-forward capacitor, CFF, may be used. Great care should be taken to route the VFB line away from noise sources, such as the inductor or the SW line. VOUT1 CFF VOUT2 RB tSS1 = CSS • LTC3776 VFB1 During soft-start, the start-up of VOUT1 is controlled by slowly ramping the positive reference to the error amplifier from 0V to 0.6V, allowing VOUT1 to rise smoothly from 0V to its final value. The default internal soft-start time is 1ms. This can be increased by placing a capacitor between the RUN/SS pin and SGND. In this case, the soft-start time will be approximately: VFB2 600mV 0.7μA RA VREF Pin 3776 F06 The regulation of VOUT2 is controlled by the voltage on the VREF pin. Normally this pin is used in DDR memory termination applications so that VOUT2 tracks 1/2 VOUT1 as shown in Figure 8. Figure 6. Setting Output Voltage Run/Soft Start Function The RUN/SS pin is a dual purpose pin that provides the optional external soft-start function and a means to shut down the LTC3776. Pulling the RUN/SS pin below 0.65V puts the LTC3776 into a low quiescent current shutdown mode (IQ = 9μA). If RUN/SS has been pulled all the way to ground, there will be a delay before the LTC3776 comes out of shutdown and is given by: tDELAY = 0.65V • C SS = 0.93 s/μF • C SS 0.7μA RUN/SS RUN/SS D1 CSS CSS 3776 F07 Figure 7. RUN/SS Pin Interfacing R1B VOUT2 LTC3776 VFB1 VFB2 R1A VREF 3776 F08 Figure 8. Using the VREF Pin (VOUT2 is Regulated to 1/2 VREF = 1/2VOUT1) Phase-Locked Loop and Frequency Synchronization This pin can be driven directly from logic as shown in Figure 7. Diode D1 in Figure 7 reduces the start delay but allows CSS to ramp up slowly providing the soft-start function. This diode (and capacitor) can be deleted if the external soft-start is not needed. 3.3V OR 5V VOUT1 The LTC3776 has a phase-locked loop (PLL) comprised of an internal voltage-controlled oscillator (VCO) and a phase detector. This allows the turn-on of the external P-channel MOSFET of controller 1 to be locked to the rising edge of an external clock signal applied to the SYNC/SSEN pin. The turn-on of controller 2’s external P-channel MOSFET is thus 180 degrees out of phase with the external clock. The phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. This type of phase detector does not exhibit false lock to harmonics of the external clock. The output of the phase detector is a pair of complementary current sources that charge or discharge the external filter network connected to the PLLLPF pin. The relationship between the voltage on the PLLLPF pin and operating 3776fa 18 LTC3776 U W U U APPLICATIO S I FOR ATIO frequency, when there is a clock signal applied to SYNC/ SSEN, is shown in Figure 9 and specified in the Electrical Characteristics table. Note that the LTC3776 can only be synchronized to an external clock whose frequency is within range of the LTC3776’s internal VCO, which is nominally 200kHz to 1MHz. This is guaranteed, over temperature and process variations, to be between 250kHz and 850kHz. A simplified block diagram is shown in Figure 10. 1400 The loop filter components, CLP and RLP, smooth out the current pulses from the phase detector and provide a stable input to the voltage-controlled oscillator. The filter components CLP and RLP determine how fast the loop acquires lock. Typically RLP = 10k and CLP is 2200pF to 0.01μF. Typically, the external clock (on SYNC/SSEN pin) input high threshold is 1.6V, while the input low threshold is 1.2V. 1200 1000 FREQUENCY (kHz) oscillators are identical. At the stable operating point, the phase detector output is high impedance and the filter capacitor CLP holds the voltage. Table 2 summarizes the different states in which the PLLLPF pin can be used. 800 600 Table 2 400 PLLLPF PIN 200 0 0 0.5 1 1.5 2 PLLLPF PIN VOLTAGE (V) 2.4 3776 F09 SYNC/SSEN PIN FREQUENCY 0V GND 300kHz Floating GND 550kHz VIN GND 750kHz Clock Signal Phase-Locked to External Clock VIN Spread Spectrum Operation 450kHz to 550kHz RC Loop Filter Figure 9. Relationship Between Oscillator Frequency and Voltage at the PLLLPF Pin When Synchronizing to an External Clock Capacitor to GND 2.4V RLP Low Supply Operation CLP SYNC/ SSEN EXTERNAL OSCILLATOR PLLLPF DIGITAL PHASE/ FREQUENCY DETECTOR OSCILLATOR Although the LTC3776 can function down to below 2.4V, the maximum allowable output current is reduced as VIN decreases below 3V. Figure 11 shows the amount of change as the supply is reduced down to 2.4V. Also shown is the effect on VREF. 3776 F10 Figure 10. Phase-Locked Loop Block Diagram If the external clock frequency is greater than the internal oscillator’s frequency, fOSC, then current is sourced continuously from the phase detector output, pulling up the PLLLPF pin. When the external clock frequency is less than fOSC, current is sunk continuously, pulling down the PLLLPF pin. If the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. The voltage on the PLLLPF pin is adjusted until the phase and frequency of the internal and external NORMALIZED VOLTAGE OR CURRENT (%) 105 100 95 VREF MAXIMUM SENSE VOLTAGE 90 85 80 75 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 INPUT VOLTAGE (V) 3776 F11 Figure 11. Line Regulation of VREF and Maximum Sense Voltage for Low Input Supply 3776fa 19 LTC3776 U W U U APPLICATIO S I FOR ATIO Minimum On-Time Considerations Minimum on-time, tON(MIN), is the smallest amount of time in which the LTC3776 is capable of turning the top P-channel MOSFET on and then off. It is determined by internal timing delays and the gate charge required to turn on the top MOSFET. Low duty cycle and high frequency applications may approach the minimum on-time limit and care should be taken to ensure that: tON(MIN) < VOUT fOSC • VIN If the duty cycle falls below what can be accommodated by the minimum on-time, the LTC3776 will regulate by overvoltage protection. The minimum on-time for the LTC3776 is typically about 200ns. However, as the peak sense voltage (IL(PEAK) • RDS(ON)) decreases, the minimum on-time gradually increases up to about 250ns. Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting efficiency and which change would produce the most improvement. Efficiency can be expressed as: Efficiency = 100% – (L1 + L2 + L3 + …) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, five main sources usually account for most of the losses in LTC3776 circuits: 1) LTC3776 DC bias current, 2) MOSFET gate charge current, 3) I2R losses, and 4) transition losses. 1) The VIN (pin) current is the DC supply current, given in the electrical characteristics, excluding MOSFET driver currents. VIN current results in a small loss that increases with VIN. 2) MOSFET gate charge current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from SENSE+ to ground. The resulting dQ/dt is a current out of SENSE+, which is typically much larger than the DC supply current. In continuous mode, IGATECHG = f • QP. 3) I2R losses are calculated from the DC resistances of the MOSFETs and inductor. In continuous mode, the average output current flows through L but is “chopped” between the top P-channel MOSFET and the bottom N-channel MOSFET. The MOSFET RDS(ON)s multiplied by duty cycle can be summed with the resistance of L to obtain I2R losses. 4) Transition losses apply to the top external P-channel MOSFET and increase with higher operating frequencies and input voltages. Transition losses can be estimated from: Transition Loss = 2 (VIN)2IO(MAX)CRSS(f) Other losses, including CIN and COUT ESR dissipative losses and inductor core losses, generally account for less than 2% total additional loss. Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to (ΔILOAD)(ESR), where ESR is the effective series resistance of COUT. ΔILOAD also begins to charge or discharge COUT, which generates a feedback error signal. The regulator loop then returns VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing. OPTI-LOOP compensation allows the transient response to be optimized over a wide range of output capacitance and ESR values. The ITH series RC-CC filter (see Functional Diagram) sets the dominant pole-zero loop compensation. The ITH external components shown in the Typical Application on the front page of this data sheet will provide an adequate starting point for most applications. The values can be modified slightly (from 0.2 to 5 times their suggested values) to optimize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be decided upon because the various types and values 3776fa 20 LTC3776 U W U U APPLICATIO S I FOR ATIO PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3776. These items are illustrated in the layout diagram of Figure 12. Figure 13 depicts the current waveforms present in the various branches of the 2-phase dual regulator. 1) The power loop (input capacitor, MOSFETs, inductor, output capacitor) of each channel should be as small as possible and isolated as much as possible from the power loop of the other channel. Ideally, the drains of the P- and N-channel FETs should be connected close to one another with an input capacitor placed across the FET sources (from the P-channel source to the N-channel source) right at the FETs. It is better to have two separate, smaller valued input capacitors (e.g., two 10μF—one for each channel) than it is to have a single larger valued capacitor (e.g., 22μF) that the channels share with a common connection. 2) The signal and power grounds should be kept separate. The signal ground consists of the feedback resistor dividers, ITH compensation networks and the SGND pin. The PGND pins on the LTC3776 IC should be shorted together and connected to the common power ground connection (away from the switching currents). 3) Put the feedback resistors close to the VFB pins. The trace connecting the top feedback resistor (RB) to the output capacitor should be a Kelvin trace. The ITH compensation components should also be very close to the LTC3776. 4) The current sense traces (SENSE+ and SW) should be Kelvin connections right at the P-channel MOSFET source and drain. 5) Keep the switch nodes (SW1, SW2) and the gate driver nodes (TG1, TG2, BG1, BG2) away from the small-signal components, especially the opposite channels feedback resistors, ITH compensation components and the current sense pins (SENSE+ and SW). COUT1 2 3 4 5 6 7 8 9 10 11 12 SENSE1+ SW1 PGND IPRG1 VFB1 BG1 ITH1 SYNC/SSEN IPRG2 PLLLPF SGND VIN TG1 PGND TG2 RUN/SS VREF BG2 VFB2 PGND ITH2 SENSE2+ PGOOD SW2 VOUT1 L1 LTC3776EGN 1 24 23 22 MN1 CVIN1 21 MP1 20 CVIN 19 VIN 18 CVIN2 17 16 MN2 MP2 15 14 13 L2 + A second, more severe transient is caused by switching in loads with large (>1μF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. The only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25)(CLOAD). Thus a 10μF capacitor would require a 250μs rise time, limiting the charging current to about 200mA. The power grounds consist of the (–) terminal of the input and output capacitors and the source of the N-channel MOSFET. Each channel should have its own power ground for its power loop (as described in (1) above). The power grounds for the two channels should connect together at a common point. It is most important to keep the ground paths with high switching currents away from each other. + determine the loop feedback factor gain and phase. An output current pulse of 20% to 100% of full load current having a rise time of 1μs to 10μs will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability. The gain of the loop will be increased by increasing RC, and the bandwidth of the loop will be increased by decreasing CC. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. For a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to Application Note 76. COUT2 VOUT2 3776 F12 BOLD LINES INDICATE HIGH CURRENT PATHS Figure 12. LTC3776 Layout Diagram 3776fa 21 LTC3776 U W U U APPLICATIO S I FOR ATIO MP1 L1 VOUT1 COUT1 MN1 + RL1 VIN RIN CIN + MP2 BOLD LINES INDICATE HIGH, SWITCHING CURRENT LINES. KEEP LINES TO A MINIMUM LENGTH L2 MN2 VOUT2 COUT2 + RL2 3776 F13 Figure 13. Branch Current Waveforms 3776fa 22 LTC3776 U TYPICAL APPLICATIO S RFB1A 59k RFB1B 187k CITH1A 100pF VIN 5V CIN 10μF ×2 22 23 24 1 2 3 4 SW1 SENSE1 PGND IPRG1 BG1 VFB1 ITH1 SYNC/SSEN TG1 IPRG2 PGND PLLLPF SGND TG2 LTC3776EUF 5 VIN RUN/SS RITH1 CITH1 22k 1000pF RVIN 10Ω CITH2 CVIN 2.2nF 1μF RITH2 6.2k CSS 10nF CITH2B 330pF + 21 L1 1.5μH MP1 20 19 18 17 16 15 MN1 Si7540DP VDDQ 2.5V 5A COUT1 100μF 14 13 BG2 9 12 PGND PGOOD 7 11 SENSE2+ VFB2 8 ITH2 10 6 SW2 VREF PGND COUT2 100μF MN2 Si7540DP MP2 L2 1.5μH VTT 1.25V ±5A 25 3776 F14 Figure 14. 2-Phase, 550kHz, DDR Memory Supplies 3776fa 23 LTC3776 U TYPICAL APPLICATIO S RFB1A 59k RFB1B 187k CITH1A 100pF VIN 3.3V 22 23 24 1 2 3 4 SW1 PGND IPRG1 BG1 VFB1 ITH1 SYNC/SSEN TG1 IPRG2 PGND PLLLPF SGND TG2 LTC3776EUF 5 VIN RUN/SS RITH1 CITH1 22k 1000pF RVIN 10Ω CIN 22μF CITH2 CVIN 2.2nF 1μF RITH2 6.2k CSS 10nF CITH2A 330pF 21 SENSE1+ L1 2.2μH MP1 FDC638P 20 19 18 17 16 15 MN1 FDC637N VDDQ 2.5V 2A COUT1 47μF 14 13 BG2 9 12 PGND PGOOD 7 11 SENSE2+ VFB2 8 ITH2 10 6 VREF SW2 PGND COUT2 47μF MN2 FDC637N MP2 FDC638P L2 2.2μH VTT 1.25V ±2A 25 3776 F15 L1, L2: VISHAY IHLP-2525CZ-01 Figure 15. 2-Phase, 750kHz, DDR Memory Supplies with Ceramic Output Capacitors 3776fa 24 LTC3776 U TYPICAL APPLICATIO S CFF1 100pF CITH1 220pF CLP 10nF VIN 3.3V RFB1B 187k RITH1 15k RLP 15k RVIN 10Ω CIN 22μF CITH2 CVIN 220pF 1μF RITH2 15k CLK IN 1 2 3 4 5 6 7 + 24 SW1 SENSE1 IPRG1 PGND BG1 VFB1 ITH1 SYNC/SSEN TG1 IPRG2 PGND PLLLPF TG2 SGND LTC3776EGN 5 VIN RUN/SS MP1 23 22 21 20 19 18 SW1 L1 1.5μH MN1 Si7540DP D1 MN2 Si7540DP D2 VDDQ 2.5V 4A + COUT1 150μF 17 16 BG2 12 15 PGND PGOOD 10 14 SENSE2+ VFB2 11 ITH2 13 9 VREF SW2 MP2 SW2 + RFB1A 59k L2 1.5μH COUT2 150μF V TT 1.25V ±4A 3736 F16 COUT1, COUT2: SANYO 4TPB150MC D1, D2: OPTIONAL SCHOTTKY DIODES L1, L2: VISHAY IHLP-2525CZ-01 Figure 16. 2-Phase, Synchronizable, DDR Memory Supplies 3776fa 25 LTC3776 U PACKAGE DESCRIPTIO UF Package 24-Lead Plastic QFN (4mm × 4mm) (Reference LTC DWG # 05-08-1697) 0.70 ±0.05 4.50 ± 0.05 2.45 ± 0.05 3.10 ± 0.05 (4 SIDES) PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 4.00 ± 0.10 (4 SIDES) BOTTOM VIEW—EXPOSED PAD 0.75 ± 0.05 R = 0.115 TYP PIN 1 NOTCH R = 0.20 TYP OR 0.35 × 45° CHAMFER 23 24 0.40 ± 0.10 PIN 1 TOP MARK (NOTE 6) 1 2 2.45 ± 0.10 (4-SIDES) (UF24) QFN 0105 0.200 REF 0.00 – 0.05 0.25 ± 0.05 0.50 BSC NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3776fa 26 LTC3776 U PACKAGE DESCRIPTIO GN Package 24-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .337 – .344* (8.560 – 8.738) 24 23 22 21 20 19 18 17 16 15 1413 .033 (0.838) REF .045 ±.005 .229 – .244 (5.817 – 6.198) .254 MIN .150 – .157** (3.810 – 3.988) .150 – .165 1 .0165 ± .0015 2 3 4 5 6 7 8 9 10 11 12 .0250 BSC RECOMMENDED SOLDER PAD LAYOUT .015 ± .004 × 45° (0.38 ± 0.10) .0075 – .0098 (0.19 – 0.25) .0532 – .0688 (1.35 – 1.75) .004 – .0098 (0.102 – 0.249) 0° – 8° TYP .016 – .050 (0.406 – 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) .008 – .012 (0.203 – 0.305) TYP .0250 (0.635) BSC GN24 (SSOP) 0204 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 3776fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 27 LTC3776 U TYPICAL APPLICATIO 2-Phase, Spread Spectrum, DDR Memory Supplies with Ceramic Output Capacitors RFB1A 59k RFB1B 187k CITH1A 100pF CITH1 1000pF RITH1 22k 2200pF VIN 3.3V RVIN 10Ω CIN 22μF CITH2 CVIN 2.2nF 1μF RITH2 6.2k 22 23 24 1 2 3 4 21 SENSE1+ SW1 PGND IPRG1 BG1 VFB1 ITH1 SYNC/SSEN TG1 IPRG2 PGND PLLLPF SGND TG2 LTC3776EUF 5 VIN RUN/SS 20 19 18 17 16 15 MN1 FDC637N VDDQ 2.5V 2A COUT1 47μF 14 13 BG2 9 12 PGND PGOOD 7 11 SENSE2+ VFB2 8 ITH2 10 6 VREF SW2 PGND CSS 10nF CITH2A 330pF L1 2.2μH MP1 FDC638P COUT2 47μF MN2 FDC637N MP2 FDC638P L2 2.2μH VTT 1.25V ±2A 25 3776 TA02 L1, L2: VISHAY IHLP-2525CZ-01 RELATED PARTS PART NUMBER LTC1735 DESCRIPTION High Efficiency Synchronous Step-Down Controller LTC1772 Constant Frequency Current Mode Step-Down DC/DC Controller No RSENSETM Synchronous Step-Down Controller LTC1778 COMMENTS Burst Mode Operation, 16-Pin Narrow SSOP, Fault Protection, 3.5V ≤ VIN ≤ 36V 2.5V ≤ VIN ≤ 9.8V, IOUT Up to 4A, SOT-23 Package, 550kHz Current Mode Operation Without Sense Resistor, Fast Transient Response, 4V ≤ VIN ≤ 36V LTC2923 Power Supply Tracking Controller Controls Up to Three Supplies, 10-Lead MSOP LTC3411 1.25A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT = 0.8V, IQ = 60μA, ISD =