LTC3788-1
2-Phase, Dual Output
Synchronous Boost Controller
DESCRIPTION
FEATURES
Synchronous Operation for Highest Efficiency and
Reduced Heat Dissipation
n Wide Input Range: 4.5V to 38V (40V Abs Max) and
Operates Down to 2.5V After Start-Up
n Output Voltages Up to 60V
n ±1% 1.2V Reference Voltage
n R
SENSE or Inductor DCR Current Sensing
n 100% Duty Cycle Capability for Synchronous MOSFET
n Low Quiescent Current: 125µA
n Phase-Lockable Frequency (75kHz to 850kHz)
n Programmable Fixed Frequency (50kHz to 900kHz)
n Adjustable Output Voltage Soft-Start
n Power Good Output Voltage Monitor
n Low Shutdown Current I : < 8μA
Q
n Internal LDO Powers Gate Drive from VBIAS or EXTV
CC
n Available in a Narrow SSOP Package
The LTC®3788-1 is a high performance 2-phase dual
synchronous boost converter controller that drives all
N-channel power MOSFETs. Synchronous rectification
increases efficiency, reduces power losses and eases
thermal requirements, allowing the LTC3788-1 to be used
in high power boost applications.
n
A constant-frequency current mode architecture allows
a phase-lockable frequency of up to 850kHz. OPTI-LOOP
compensation allows the transient response to be optimized over a wide range of output capacitance and ESR
values. The LTC3788-1 features a precision 1.2V reference and a power good output indicator. A 4.5V to 38V
input supply range encompasses a wide range of system
architectures and battery chemistries.
Independent SS pins for each controller ramp the output
voltages during start-up. The PLLIN/MODE pin selects
among Burst Mode operation, pulse-skipping mode or
continuous inductor current mode at light loads.
APPLICATIONS
Industrial
Automotive
n Medical
n Military
n
For a leadless 32-pin QFN package with additional features
of adjustable current limit, clock out, phase modulation
and two PGOOD outputs, see the LTC3788 data sheet.
n
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. patents, including 5408150, 5481178, 5705919, 5929620, 6144194, 6177787, 6580258.
TYPICAL APPLICATION
VIN 4.5V TO 12V START-UP VOLTAGE
OPERATES THROUGH TRANSIENTS DOWN TO 2.5V
VIN
4.7µF
TG1 VBIAS INTVCC
1.25µH
VOUT
12V AT 5A
0.1µF
BOOST1
SW2
LTC3788-1
3.3µH
VOUT
24V AT 3A
0.1µF
BG2
SENSE1+
SENSE2+
SENSE1–
SENSE2–
PGND
110k
VFB1
220µF
15nF
12.1k
2.7k
FREQ
PLLIN/MODE
ITH1 SS1 SGND SS2 ITH2
100pF
0.1µF
0.1µF
80
15nF
220pF
8.66k
1000
70
60
100
50
40
10
30
VIN = 12V
1
VOUT = 24V
Burst Mode OPERATION
FIGURE 9 CIRCUIT
0
0.1
0.00001 0.0001 0.001 0.01
0.1
1
10
OUTPUT CURRENT (A)
20
232k
VFB2
10000
90
POWER LOSS (mW)
BG1
100
TG2
BOOST2
SW1
Efficiency and Power Loss
vs Load Current
220µF
4mΩ
EFFICIENCY (%)
4.7µF
3mΩ
10
220µF
37881 TA01b
12.1k
37881 TA01a
Rev D
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1
LTC3788-1
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 3)
VBIAS......................................................... –0.3V to 40V
BOOST1, BOOST2....................................... –0.3V to 76V
SW1, SW2................................................... –0.3V to 70V
RUN1, RUN2................................................. –0.3V to 8V
Maximum Current Sourced into Pin
from Source > 8V..............................................100µA
PGOOD1, PLLIN/MODE ................................ –0.3V to 6V
INTVCC, (BOOST1-SW1, BOOST2-SW2)....... –0.3V to 6V
EXTVCC......................................................... –0.3V to 6V
SENSE1+, SENSE1–,
SENSE2+, SENSE2–..................................... –0.3V to 40V
SENSE1+ – SENSE1–,
SENSE2+ – SENSE2–.................................. –0.3V to 0.3V
SS1, SS2, ITH1, ITH2, FREQ,
VFB1, VFB2............................................–0.3V to INTVCC
Operating Junction Temperature Range.....–40°C to 125°C
Storage Temperature Range................... –65°C to 125°C
Lead Temperature (Soldering, 10 seconds)............ 300°C
TOP VIEW
ITH1
1
28 SS1
VFB1
2
27 PGOOD1
SENSE1+
3
26 SW1
SENSE1–
4
25 TG1
FREQ
5
24 BOOST1
PLLIN/MODE
6
23 BG1
SGND
7
22 VBIAS
RUN1
8
21 PGND
RUN2
9
20 EXTVCC
SENSE2–
10
19 INTVCC
SENSE2+ 11
18 BG2
VFB2 12
17 BOOST2
ITH2 13
16 TG2
SS2 14
15 SW2
GN PACKAGE
28-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 80°C/W
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3788EGN-1#PBF
LTC3788EGN-1#TRPBF
LTC3788GN-1
28-Lead Plastic SSOP
–40°C to 125°C
LTC3788IGN-1#PBF
LTC3788IGN-1#TRPBF
LTC3788GN-1
28-Lead Plastic SSOP
–40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
ELECTRICAL
CHARACTERISTICS
The
l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C, VBIAS = 12V, unless otherwise noted (Note 2).
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Main Control Loop
VBIAS
Chip Bias Voltage Operating Range
4.5
VFB1,2
Regulated Feedback Voltage
ITH = 1.2V (Note 4)
IFB1,2
Feedback Current
(Note 4)
VREFLNREG
Reference Line Voltage Regulation
VIN = 6V to 38V
l
1.188
38
V
1.200
1.212
V
±5
±50
nA
0.002
0.02
%/V
Rev D
2
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LTC3788-1
ELECTRICAL
CHARACTERISTICS
The
l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C, VBIAS = 12V, unless otherwise noted (Note 2).
SYMBOL
PARAMETER
CONDITIONS
VLOADREG
Output Voltage Load Regulation
(Note 4)
TYP
MAX
UNITS
Measured in Servo Loop;
∆ITH Voltage = 1.2V to 0.7V
l
0.01
0.1
%
Measured in Servo Loop;
∆ITH Voltage = 1.2V to 2V
l
–0.01
–0.1
%
gm1,2
Error Amplifier Transconductance
ITH = 1.2V
IQ
Input DC Supply Current
(Note 5)
UVLO
MIN
2
mmho
Pulse-Skipping or Forced Continuous Mode RUN1 = 5V and RUN2 = 0V or RUN1 = 0V
(One Channel On)
and RUN2 = 5V; VFB1(2) = 1.25V (No Load)
0.9
mA
Pulse-Skipping or Forced Continuous Mode RUN1,2 = 5V; VFB1,2 = 1.25V (No Load)
(Both Channels On)
1.2
mA
Sleep Mode
(One Channel On)
RUN1 = 5V and RUN2 = 0V or RUN1 = 0V
and RUN2 = 5V; VFB1(2) = 1.25V (No Load)
125
190
µA
Sleep Mode
(Both Channels On)
RUN1,2 = 5V; VFB1,2 = 1.25V (No Load)
200
300
µA
8
20
µA
4.1
4.3
V
Shutdown
RUN1,2 = 0V
INTVCC Undervoltage Lockout Thresholds
VINTVCC Ramping Up
l
VINTVCC Ramping Down
l
3.6
3.8
VRUN Rising
l
1.18
1.28
VRUN1,2
RUN Pin On Threshold
VRUNHYS
RUN Pin Hysteresis
V
1.38
V
100
mV
IRUN1,2
RUN Pin Hysteresis Current
VRUN > 1.28V
4.5
µA
IRUN1,2
RUN Pin Current
VRUN < 1.28V
0.5
µA
ISS1,2
Soft-Start Charge Current
VSS = GND
10
µA
VSENSE(MAX)
Maximum Current Sense Threshold
VFB = 1.1V
VSENSE(CM)
SENSE Pins Common Mode Range (BOOST
Converter Input Supply Voltage VIN)
ISENSE1,2+
SENSE+ Pin Current
VFB = 1.1V
ISENSE1,2–
SENSE– Pin Current
VFB = 1.1V
l
68
75
2.5
200
82
mV
38
V
300
µA
±1
µA
t r(TG1,2)
Top Gate Rise Time
CLOAD = 3300pF (Note 6)
20
ns
t f(TG1,2)
Top Gate Fall Time
CLOAD = 3300pF (Note 6)
20
ns
t r(BG1,2)
Bottom Gate Rise Time
CLOAD = 3300pF (Note 6)
20
ns
t f(BG1,2)
Bottom Gate Fall Time
CLOAD = 3300pF (Note 6)
20
ns
RUP(TG1,2)
Top Gate Pull-Up Resistance
1.2
Ω
RDN(TG1,2)
Top Gate Pull-Down Resistance
1.2
Ω
RUP(TG1,2)
Bottom Gate Pull-Up Resistance
1.2
Ω
RDN(TG1,2)
Bottom Gate Pull-Down Resistance
1.2
Ω
t D(TG/BG)
Top Gate Off to Bottom Gate On
Switch-On Delay Time
CLOAD = 3300pF (Each Driver)
70
ns
t D(BG/TG)
Bottom Gate Off to Top Gate On
Switch-On Delay Time
CLOAD = 3300pF (Each Driver)
70
ns
DFMAX(BG1,2)
Maximum BG Duty Factor
96
%
tON(MIN)
Minimum BG On-Time
110
ns
(Note 7)
Rev D
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3
LTC3788-1
ELECTRICAL
CHARACTERISTICS
The
l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C, VBIAS = 12V, unless otherwise noted (Note 2).
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
5.2
5.4
5.6
V
0.5
2
%
INTVCC Linear Regulator
VINTVCCVIN
Internal VCC Voltage
6V < VBIAS < 38V, VEXTVCC = 0V
VLDOVIN
INTVCC Load Regulation
ICC = 0mA to 50mA, VEXTVCC = 0V
VINTVCCEXT
Internal VCC Voltage
VEXTVCC = 6V
VLDOEXT
INTVCC Load Regulation
ICC = 0mA to 40mA, VEXTVCC = 6V
VEXTVCC
EXTVCC Switchover Voltage
EXTVCC Ramping Positive
VLDOHYS
EXTVCC Hysteresis
5.2
4.5
5.4
5.6
V
0.5
2
%
4.8
5
V
250
mV
Oscillator and Phase-Locked Loop
fPROG
Programmable Frequency
RFREQ = 25k
105
RFREQ = 60k
335
RFREQ = 100k
400
kHz
465
760
kHz
kHz
fLOW
Lowest Fixed Frequency
VFREQ = 0V
320
350
380
kHz
fHIGH
Highest Fixed Frequency
VFREQ = INTVCC
485
535
585
kHz
fSYNC
Synchronizable Frequency
PLLIN/MODE = External Clock
850
kHz
VPGL1
PGOOD1 Voltage Low
IPGOOD1 = 2mA
0.4
V
IPGOOD1
PGOOD1 Leakage Current
VPGOOD1 = 5V
±1
µA
VPG1
PGOOD1 Trip Level
VFB1 with Respect to Set Regulated Voltage
–8
%
l
75
PGOOD1 Output
0.2
VFB1 Ramping Negative
–12
Hysteresis
2.5
VFB1 Ramping Positive
tPGOOD1(DELAY)
PGOOD1 Delay
–10
8
10
%
12
%
Hysteresis
2.5
%
PGOOD1 Going High to Low
25
µs
VSW1,2 = 12V; VBOOST1,2 – VSW1,2 = 4.5V;
FREQ = 0V, Forced Continuous or
Pulse-Skipping Mode
55
µA
BOOST1 and BOOST2 Charge Pump
IBOOST1,2
BOOST Charge Pump Available
Output Current
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3788-1 is tested under pulsed load conditions such that
TJ ≈ TA. The LTC3788E-1 is guaranteed to meet specifications from
0°C to 85°C junction temperature. Specifications over the –40°C to
125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3788I-1 is guaranteed over the full –40°C to 125°C operating
junction temperature range. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
impedance and other environmental factors. The junction temperature (TJ,
in °C) is calculated from the ambient temperature (TA, in °C) and power
dissipation (PD, in Watts) according to the formula: TJ = TA + (PD • θJA),
where θJA = 80°C/W.
Note 3: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
the device.
Note 4: The LTC3788-1 is tested in a feedback loop that servos VFB to the
output of the error amplifier while maintaining ITH at the midpoint of the
current limit range.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency.
Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 7: See Minimum On-Time Considerations in the Applications
Information section.
Rev D
4
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LTC3788-1
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency and Power Loss
vs Output Current
Efficiency and Power Loss
vs Output Current
100
10000
100
90
80
100
50
40
10
30
20
VIN = 12V
VOUT = 24V
FIGURE 9 CIRCUIT
10
0
0.01
10
0.1
1
OUTPUT CURRENT (A)
BURST EFFICIENCY
PULSE-SKIPPING
EFFICIENCY
CCM EFFICIENCY
1
0.1
37881 G01
60
40
10
30
VIN = 12V
1
VOUT = 24V
10
Burst Mode OPERATION
FIGURE 9 CIRCUIT
0
0.1
0.00001 0.0001 0.001 0.01
0.1
1
10
OUTPUT CURRENT (A)
20
37881 G02
BURST LOSS
PULSE-SKIPPING
LOSS
CCM LOSS
BURST EFFICIENCY
BURST LOSS
Load Step
Forced Continuous Mode
ILOAD = 2A
FIGURE 9 CIRCUIT
99
100
50
Efficiency vs Input Voltage
100
1000
70
POWER LOSS (mW)
60
EFFICIENCY (%)
1000
70
POWER LOSS (mW)
EFFICIENCY (%)
80
LOAD STEP
2A/DIV
98
EFFICIENCY (%)
10000
90
VOUT = 12V
97
96
INDUCTOR
CURRENT
5A/DIV
VOUT = 24V
95
94
93
VOUT
500mV/DIV
92
91
90
0
5
15
10
INPUT VOLTAGE (V)
20
25
VIN = 12V
200µs/DIV
VOUT = 24V
FIGURE 9 CIRCUIT
37881 G03
Load Step
Pulse-Skipping Mode
Load Step
Burst Mode Operation
LOAD STEP
2A/DIV
LOAD STEP
2A/DIV
INDUCTOR
CURRENT
5A/DIV
INDUCTOR
CURRENT
5A/DIV
VOUT
500mV/DIV
VOUT
500mV/DIV
VIN = 12V
200µs/DIV
VOUT = 24V
FIGURE 9 CIRCUIT
37881 G04
37881 G05
VIN = 12V
200µs/DIV
VOUT = 24V
FIGURE 9 CIRCUIT
37881 G06
Rev D
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5
LTC3788-1
TYPICAL PERFORMANCE CHARACTERISTICS
Inductor Current at Light Load
Soft Start-Up
FORCED
CONTINUOUS MODE
Burst Mode
OPERATION
5A/DIV
VOUT
5V/DIV
PULSE-SKIPPING
MODE
0V
37881 G07
VIN = 12V
5µs/DIV
VOUT = 24V
ILOAD = 200µA
FIGURE 9 CIRCUIT
VIN = 12V
20ms/DIV
VOUT = 24V
FIGURE 9 CIRCUIT
Regulated Feedback Voltage
vs Temperature
Soft-Start Pull-Up Current
vs Temperature
1.212
11.0
1.209
SOFT-START CURRENT (µA)
REGULATED FEEDBACK VOLTAGE (V)
37881 G08
1.206
1.203
1.200
1.197
1.194
10.5
10.0
9.5
1.191
1.188
–45 –20
80
55
30
TEMPERATURE (°C)
5
105
9.0
–45
130
10.5
5
37881 G09
105
130
37881 G10
Shutdown Current
vs Input Voltage
Shutdown Current vs Temperature
11.0
80
55
30
TEMPERATURE (°C)
–20
20
VIN = 12V
SHUTDOWN CURRENT (µA)
SHUTDOWN CURRENT (µA)
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
15
10
5
5.5
5.0
–45
–20
80
5
55
30
TEMPERATURE (°C)
105
130
0
0
5
10
37881 G11
15 20 25 30
INPUT VOLTAGE (V)
35
40
37881 G12
Rev D
6
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LTC3788-1
TYPICAL PERFORMANCE CHARACTERISTICS
Shutdown (RUN) Threshold
vs Temperature
Quiescent Current vs Temperature
4.3
1.35
140
130
120
1.25
1.20
RUN FALLING
100
–45 –20
1.10
–45 –20
105
130
5.1
5.0
4.9
4.8
4.7
4.6
10
15 20 25 30
INPUT VOLTAGE (V)
35
5.45
5.6
5.2
5.0
EXTVCC RISING
4.8
EXTVCC FALLING
4.6
130
OSCILLATOR FREQUENCY (kHz)
550
500
450
400
FREQ = GND
356
354
352
350
348
346
344
342
55
5
30
80
TEMPERATURE (°C)
105
130
37881 G19
340
5
10
25
30
20
15
INPUT VOLTAGE (V)
EXTVCC = 6V
5.15
5.00
0
35
40
37881 G20
20 40 60 80 100 120 140 160 180 200
INTVCC LOAD CURRENT (mA)
37881 G18
37881 G17
FREQ = GND
358
EXTVCC = 0V
5.25
5.05
360
VIN = 12V
5.20
5.10
105
130
37881 G15
5.30
4.2
55
30
5
80
TEMPERATURE (°C)
105
INTVCC vs INTVCC Load Current
5.35
4.4
–20
80
5
55
30
TEMPERATURE (°C)
5.40
INTVCC
5.4
–20
37881 G14
Oscillator Frequency
vs Input Voltage
FREQ = INTVCC
–20
3.4
–45
130
5.8
37881 G16
600
300
–45
3.7
5.50
4.0
–45
40
INTVCC FALLING
3.8
6.0
Oscillator Frequency
vs Temperature
350
105
INTVCC VOLTAGE (V)
EXTVCC AND INTVCC VOLTAGE (V)
5.2
5
3.9
EXTVCC Switchover and INTVCC
Voltages vs Temperature
INTVCC Line Regulation
0
80
55
30
TEMPERATURE (°C)
5
37881 G13
5.3
4.5
4.0
3.5
MAXIMUM CURRENT SENSE VOLTAGE (mV)
80
55
30
TEMPERATURE (°C)
4.1
3.6
1.15
5.4
INTVCC VOLTAGE (V)
RUN RISING
1.30
110
5
INTVCC RISING
4.2
INTVCC VOLTAGE (V)
150
RUN PIN VOLTAGE (V)
QUIESCENT CURRENT (µA)
VIN = 12V
VFB = 1.25V
160 RUN2 = GND
FREQUENCY (kHz)
4.4
1.40
170
5.5
Undervoltage Lockout Threshold
vs Temperature
120
Maximum Current Sense
Threshold vs ITH Voltage
PULSE-SKIPPING MODE
FORCED CONTINUOUS MODE
Burst Mode OPERATION
100
80
60
40
20
0
–20
–40
–60
0
0.2
0.4
0.6 0.8 1.0
ITH VOLTAGE (V)
1.2
1.4
37881 G21
Rev D
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7
LTC3788-1
TYPICAL PERFORMANCE CHARACTERISTICS
105
130
260
240
220
200
180
160
140
120
100
80
60
40
20
0
VSENSE = 12V
SENSE+ PIN
SENSE CURRENT (µA)
260
VSENSE = 12V
240
220
SENSE+ PIN
200
180
160
140
120
100
80
60
40
20
SENSE – PIN
0
55
30
–45 –20
5
80
TEMPERATURE (°C)
SENSE Pin Input Current
vs ITH Voltage
SENSE CURRENT (µA)
SENSE CURRENT (µA)
SENSE Pin Input Current
vs Temperature
SENSE – PIN
0
0.5
37881 G22
2
1.5
1
ITH VOLTAGE (V)
2.5
SENSE+ PIN
SENSE – PIN
2.5
7.5 12.5 17.5 22.5 27.5 32.5 37.5
VSENSE COMMON MODE VOLTAGE (V)
37881 G24
Charge Pump Charging Current
vs Operating Frequency
80
120
CHARGE PUMP CHARGING CURRENT (µA)
MAXIMUM CURRENT SENSE VOLTAGE (mV)
Maximum Current Sense
Threshold vs Duty Cycle
100
80
60
40
20
0
3
37881 G23
260
240
220
200
180
160
140
120
100
80
60
40
20
0
SENSE Pin Input Current
vs VSENSE Voltage
0
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
VSW = 12V
70 VBOOST – VSW = 4.5V
60
T = –45°C
T = 25°C
50
40
T = 130°C
30
20
10
0
50
150 250 350 450 550 650 750
OPERATING FREQUENCY (kHz)
37881 G26
37881 G25
PIN FUNCTIONS
ITH1, ITH2 (Pin 1, Pin 13): Current Control Threshold
and Error Amplifier Compensation Point. The voltage on
this pin sets the current trip threshold.
VFB1, VFB2 (Pin 2, Pin 12): Error Amplifier Feedback
Input. This pin receives the remotely sensed feedback
voltage from an external resistive divider connected
across the output.
SENSE1+, SENSE2+ (Pin 3, Pin 11): Positive Current
Sense Comparator Input. The (+) input to the current
comparator is normally connected to the positive terminal of a current sense resistor. The current sense resistor
is normally placed at the input of the boost controller in
series with the inductor. This pin also supplies power to
the current comparator.
Rev D
8
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LTC3788-1
PIN FUNCTIONS
SENSE1–, SENSE2– (Pin 4, Pin 10): Negative Current
Sense Comparator Input. The (–) input to the current
comparator is normally connected to the negative terminal of a current sense resistor connected in series with
the inductor. The common mode voltage range on these
pins is 2.5V to 38V (40V abs max).
FREQ (Pin 5): The frequency control pin for the internal
VCO. Connecting the pin to GND forces the VCO to a fixed
low frequency of 350kHz. Connecting the pin to INTVCC
forces the VCO to a fixed high frequency of 535kHz. The
frequency can be programmed from 50kHz to 900kHz
by connecting a resistor from the FREQ pin to GND. The
resistor and an internal 20µA source current create a voltage used by the internal oscillator to set the frequency.
Alternatively, this pin can be driven with a DC voltage to
vary the frequency of the internal oscillator.
PLLIN/MODE (Pin 6): External Synchronization Input to
Phase Detector and Forced Continuous Mode Input. When
an external clock is applied to this pin, it will force the
controller into forced continuous mode of operation and
the phase-locked loop will force the rising BG1 signal
to be synchronized with the rising edge of the external
clock. When not synchronizing to an external clock, this
input, which acts on both controllers, determines how
the LTC3788-1 operates at light loads. Pulling this pin to
ground selects Burst Mode operation. An internal 100k
resistor to ground also invokes Burst Mode operation
when the pin is floated. Tying this pin to INTVCC forces
continuous inductor current operation. Tying this pin to
a voltage greater than 1.2V and less than INTVCC – 1.3V
selects pulse-skipping operation. This can be done by
adding a 100k resistor between the PLLIN/MODE pin and
INTVCC.
SGND (Pin 7): Signal Ground. All small-signal components
and compensation components should connect to this
ground, which in turn connects to PGND at a single point.
RUN1, RUN2 (Pin 8, Pin 9): Run Control Input. An external resistor divider connects to VIN and sets the thresholds for converter operation with a threshold of 1.28V.
Once running, a 4.5µA current is sourced from the RUN
pin allowing the user to program hysteresis using the
resistor values.
INTVCC (Pin 19): Output of Internal 5.4V LDO. Power
supply for control circuits and gate drives. Decouple this
pin to GND with a minimum 4.7µF low ESR tantalum or
ceramic capacitor.
EXTVCC (Pin 20): External Power Input. When this pin is
higher than 4.8V an internal switch bypasses the internal regulator and supply power to INTVCC directly from
EXTVCC.
PGND (Pin 21): Driver Power Ground. Connects to the
sources of bottom (main) N-channel MOSFETs and the
(–) terminal(s) of CIN and COUT .
VBIAS (Pin 22): Main Supply Pin. It is normally tied to the
input supply VIN or to the output of the boost converter. A
bypass capacitor should be tied between this pin and the
signal ground pin. The operating voltage range on this pin
is 4.5V to 38V (40V abs max).
BG1, BG2 (Pin 23, Pin 18): Bottom Gate. Connect to the
gate of the main NMOS.
BOOST1, BOOST2 (Pin 24, Pin 17): Floating power supply for the synchronous NMOS. Bypass to SW with a
capacitor and supply with a Schottky diode connected
to INTVCC.
TG1, TG2 (Pin 25, Pin 16): Top Gate. Connect to the gate
of the synchronous NMOS.
SW1, SW2 (Pin 26, Pin 15): Switch Node. Connect to the
source of the synchronous NMOS, the drain of the main
NMOS and the inductor.
PGOOD1 (Pin 27): Power Good Indicator for Channel 1.
Open-drain logic output that is pulled to ground when the
output voltage is more than ±10% away from the regulated output voltage. To avoid false trips the output voltage
must be outside the range for 25µs before this output is
activated.
SS1, SS2 (Pin 28, Pin 14): Output Soft-Start Input. A
capacitor to ground at this pin sets the ramp rate of the
output voltage during start-up.
Rev D
For more information www.analog.com
9
LTC3788-1
BLOCK DIAGRAM
INTVCC
DUPLICATE FOR SECOND CONTROLLER CHANNEL
PGOOD1
1.32V
VFB1
1.08V
+
S
–
R
Q
SWITCHING
LOGIC
AND
CHARGE
PUMP
–
CLK2
VCO
COUT
INTVCC
BG
0.425V
CLK1
PFD
+
SLEEP
PGND
+
–
+
– +
+ –
L
–
2mV
SENSE –
2.8V
0.7V
SENSE+
SLOPE COMP
SYNC
DET
SENS LO
100k
–
+
EA –
–
0.5µA/
4.5µA
1.2V
SS
+
–
1.32V
ITH
EN
+
4.8V
–
5.4V
LDO
EN
RC
11V
–
+
3.8V
INTVCC
CC
CC2
10µA
5.4V
LDO
CIN
VFB
2.5V
OV
SHDN
RSENSE
VIN
+
VBIAS
EXTVCC
VOUT
SW
–
PLLIN/
MODE
CB
TG
SHDN
+
20µA
FREQ
DB
BOOST
SGND
SHDN
RUN
SENS
LO
SS
CSS
37881 BD
Rev D
10
For more information www.analog.com
LTC3788-1
OPERATION
(Refer to Block Diagram)
Main Control Loop
The LTC3788-1 uses a constant-frequency, current mode
step-up architecture with the two controller channels operating 180 degrees out-of-phase. During normal operation,
each external bottom MOSFET is turned on when the clock
for that channel sets the RS latch, and is turned off when
the main current comparator, ICMP, resets the RS latch.
The peak inductor current at which ICMP trips and resets
the latch is controlled by the voltage on the ITH pin, which
is the output of the error amplifier EA. The error amplifier
compares the output voltage feedback signal at the VFB
pin, (which is generated with an external resistor divider
connected across the output voltage, VOUT, to ground) to
the internal 1.200V reference voltage. When the load current increases, it causes a slight decrease in VFB relative
to the reference, which causes the EA to increase the ITH
voltage until the average inductor current matches the
new load current.
After the bottom MOSFET is turned off each cycle, the
top MOSFET is turned on until either the inductor current
starts to reverse, as indicated by the current comparator
IR, or the beginning of the next clock cycle.
INTVCC /EXTVCC Power
Power for the top and bottom MOSFET drivers and most
other internal circuitry is derived from the INTVCC pin.
When the EXTVCC pin is left open or tied to a voltage less
than 4.8V, the VBIAS LDO (low dropout linear regulator) supplies 5.4V from VBIAS to INTVCC. If EXTVCC is
taken above 4.8V, the VBIAS LDO is turned off and an
EXTVCC LDO is turned on. Once enabled, the EXTVCC LDO
supplies 5.4V from EXTVCC to INTVCC. Using the EXTVCC
pin allows the INTVCC power to be derived from a high
efficiency external source such as one of the LTC3788-1
switching regulator outputs.
Shutdown and Start-Up
(RUN1, RUN2 and SS1, SS2 Pins)
The two channels of the LTC3788-1 can be independently
shut down using the RUN1 and RUN2 pins. Pulling either
of these pins below 1.28V shuts down the main control
loop for that controller. Pulling both pins below 0.7V disables both controllers and most internal circuits, including
the INTVCC LDO’s. In this state, the LTC3788-1 draws only
8µA of quiescent current.
The RUN pin may be externally pulled up or driven directly
by logic. When driving the RUN pin with a low impedance
source, do not exceed the absolute maximum rating of
8V. The RUN pin has an internal 11V voltage clamp that
allows the RUN pin to be connected through a resistor to
a higher voltage (for example, VIN), as long as the maximum current into the RUN pin does not exceed 100µA.
The start-up of each controller’s output voltage VOUT is
controlled by the voltage on the SS pin for that channel.
When the voltage on the SS pin is less than the 1.2V
internal reference, the LTC3788-1 regulates the VFB voltage to the SS pin voltage instead of the 1.2V reference.
This allows the SS pin to be used to program a softstart by connecting an external capacitor from the SS pin
to SGND. An internal 10µA pull-up current charges this
capacitor creating a voltage ramp on the SS pin. As the
SS voltage rises linearly from 0V to 1.2V (and beyond up
to INTVCC), the output voltage VOUT rises smoothly to its
final value.
Light Load Current Operation—Burst Mode Operation,
Pulse-Skipping or Continuous Conduction
(PLLIN/MODE Pin)
The LTC3788-1 can be enabled to enter high efficiency
Burst Mode operation, constant-frequency pulse-skipping
mode or forced continuous conduction mode at low load
currents. To select Burst Mode operation, tie the PLLIN/
MODE pin to a ground (e.g., SGND). To select forced continuous operation, tie the PLLIN/MODE pin to INTVCC. To
select pulse-skipping mode, tie the PLLIN/MODE pin to a
DC voltage greater than 1.2V and less than INTVCC – 0.5V.
When a controller is enabled for Burst Mode operation,
the minimum peak current in the inductor is set to approximately 30% of the maximum sense voltage even though
the voltage on the ITH pin indicates a lower value. If the
average inductor current is higher than the load current,
the error amplifier EA will decrease the voltage on the ITH
pin. When the ITH voltage drops below 0.425V, the internal
sleep signal goes high (enabling sleep mode) and both
external MOSFETs are turned off.
Rev D
For more information www.analog.com
11
LTC3788-1
OPERATION
In sleep mode, much of the internal circuitry is turned
off, reducing the quiescent current that the LTC3788-1
draws. If one channel is shut down and the other channel is in sleep mode, the LTC3788-1 draws only 125µA
of quiescent current. If both channels are in sleep mode,
the LTC3788-1 draws only 200µA of quiescent current.
In sleep mode, the load current is supplied by the output
capacitor. As the output voltage decreases, the EA’s output begins to rise. When the output voltage drops enough,
the ITH pin is reconnected to the output of the EA, the
sleep signal goes low, and the controller resumes normal
operation by turning on the bottom external MOSFET on
the next cycle of the internal oscillator.
exhibits low output ripple as well as low audio noise and
reduced RF interference as compared to Burst Mode
operation. It provides higher low current efficiency than
forced continuous mode, but not nearly as high as Burst
Mode operation.
When a controller is enabled for Burst Mode operation,
the inductor current is not allowed to reverse. The reverse
current comparator (IR) turns off the top external MOSFET
just before the inductor current reaches zero, preventing
it from reversing and going negative. Thus, the controller
operates in discontinuous current operation.
The switching frequency of the LTC3788-1’s controllers
can be selected using the FREQ pin.
In forced continuous operation or when clocked by an
external clock source to use the phase-locked loop (see
the Frequency Selection and Phase-Locked Loop section),
the inductor current is allowed to reverse at light loads or
under large transient conditions. The peak inductor current is determined by the voltage on the ITH pin, just as
in normal operation. In this mode, the efficiency at light
loads is lower than in Burst Mode operation. However,
continuous operation has the advantages of lower output
voltage ripple and less interference to audio circuitry, as
it maintains constant-frequency operation independent
of load current.
When the PLLIN/MODE pin is connected for pulse-skipping mode, the LTC3788-1 operates in PWM pulse-skipping mode at light loads. In this mode, constant-frequency
operation is maintained down to approximately 1% of
designed maximum output current. At very light loads, the
current comparator ICMP may remain tripped for several
cycles and force the external bottom MOSFET to stay off
for the same number of cycles (i.e., skipping pulses). The
inductor current is not allowed to reverse (discontinuous
operation). This mode, like forced continuous operation,
Frequency Selection and Phase-Locked Loop (FREQ
and PLLIN/MODE Pins)
The selection of switching frequency is a trade-off between
efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
If the PLLIN/MODE pin is not being driven by an external
clock source, the FREQ pin can be tied to SGND, tied
to INTVCC , or programmed through an external resistor.
Tying FREQ to SGND selects 350kHz while tying FREQ
to INTVCC selects 535kHz. Placing a resistor between
FREQ and SGND allows the frequency to be programmed
between 50kHz and 900kHz, as shown in Figure 6.
A phase-locked loop (PLL) is available on the LTC3788-1
to synchronize the internal oscillator to an external clock
source that is connected to the PLLIN/MODE pin. The
LTC3788-1’s phase detector adjusts the voltage (through
an internal lowpass filter) of the VCO input to align the
turn-on of the first controller’s external bottom MOSFET
to the rising edge of the synchronizing signal. Thus,
the turn-on of the second controller’s external bottom
MOSFET is 180 degrees out-of-phase to the rising edge
of the external clock source.
The VCO input voltage is prebiased to the operating frequency set by the FREQ pin before the external clock is
applied. If prebiased near the external clock frequency,
the PLL loop only needs to make slight changes to the
VCO input in order to synchronize the rising edge of the
external clock’s to the rising edge of BG1. The ability to
prebias the loop filter allows the PLL to lock-in rapidly
without deviating far from the desired frequency.
Rev D
12
For more information www.analog.com
LTC3788-1
OPERATION
The typical capture range of the LTC3788-1’s PLL is
from approximately 55kHz to 1MHz, and is guaranteed to
lock to an external clock source whose frequency is between 75kHz and 850kHz.
The typical input clock thresholds on the PLLIN/MODE
pin are 1.6V (rising) and 1.2V (falling).
Operation When VIN > VOUT
When VIN rises above the regulated VOUT voltage, the
boost controller can behave differently depending on the
mode, inductor current and VIN voltage. In forced continuous mode, the loop works to keep the top MOSFET
on continuously once VIN rises above VOUT . The internal
charge pump delivers current to the boost capacitor to
maintain a sufficiently high TG voltage.
In pulse-skipping mode, if VIN is between 100% and
110% of the regulated VOUT voltage, TG turns on if the
inductor current rises above a certain threshold and turns
off if the inductor current falls below this threshold. This
threshold current is set approximately to 4% of the maximum current. If the controller is programmed to Burst
Mode operation under this same VIN window, then TG
remains off regardless of the inductor current.
If VIN rises above 110% of the regulated VOUT voltage
in any mode, the controller turns on TG regardless of
the inductor current. In Burst Mode operation, however,
the internal charge pump turns off if the entire chip is
asleep (the other channel is asleep or shut down). With
the charge pump off, there would be nothing to prevent
the boost capacitor from discharging, resulting in an
insufficient TG voltage needed to keep the top MOSFET
completely on. To prevent excessive power dissipation
across the body diode of the top MOSFET in this situation,
the chip can be switched over to forced continuous mode
to enable the charge pump, or a Schottky diode can also
be placed in parallel to the top MOSFET.
Power Good
The PGOOD1 pin is connected to an open-drain of an
internal N-channel MOSFET. The MOSFET turns on and
pulls the PGOOD1 pin low when the corresponding VFB1
pin voltage is not within ±10% of the 1.2V reference voltage. The PGOOD1 pin is also pulled low when the corresponding RUN1 pin is low (shut down). When the VFB1
pin voltage is within the ±10% requirement, the MOSFET
is turned off and the pin is allowed to be pulled up by an
external resistor to a source of up to 6V.
Operation at Low SENSE Pin Common Voltage
The current comparator in the LTC3788-1 is powered
directly from the SENSE + pin. This enables the common
mode voltage of SENSE + and SENSE – pins to operate at as
low as 2.5V, which is below the UVLO threshold. Figure 1
shows a typical application when the controller’s VBIAS
is powered from VOUT while VIN supply can go as low as
2.5V. If the voltage on SENSE + drops below 2.5V, the SS
pin will be held low. When the SENSE voltage returns to
the normal operating range, the SS pin will be released,
initiating a new soft-start cycle.
BOOST Supply Refresh and Internal Charge Pump
Each top MOSFET driver is biased from the floating
bootstrap capacitor CB, which normally recharges during each cycle through an external diode when the bottom MOSFET turns on. There are two considerations to
keep the BOOST supply at the required bias level. During
start-up, if the bottom MOSFET is not turned on within
100µs after UVLO goes low, the bottom MOSFET will be
forced to turn on for ~400ns. This forced refresh generates enough BOOST-SW voltage to allow the top MOSFET
ready to be fully enhanced instead of waiting for the initial
few cycles to charge up. There is also an internal charge
pump that keeps the required bias on BOOST. The charge
pump always operates in both forced continuous mode
and pulse-skipping mode. In Burst Mode operation, the
charge pump is turned off during sleep and enabled when
the chip wakes up. The internal charge pump can normally
supply a charging current of 55µA.
Rev D
For more information www.analog.com
13
LTC3788-1
APPLICATIONS INFORMATION
The Typical Application on the first page is a basic
LTC3788-1 application circuit. LTC3788-1 can be configured to use either inductor DCR (DC resistance) sensing
or a discrete sense resistor (RSENSE) for current sensing.
The choice between the two current sensing schemes
is largely a design trade-off between cost, power consumption and accuracy. DCR sensing is becoming popular because it does not require current sensing resistors
and is more power-efficient, especially in high current
applications. However, current sensing resistors provide
the most accurate current limits for the controller. Other
external component selection is driven by the load requirement, and begins with the selection of RSENSE (if RSENSE
is used) and inductor value. Next, the power MOSFETs are
selected. Finally, input and output capacitors are selected.
TO SENSE FILTER,
NEXT TO THE CONTROLLER
VIN
INDUCTOR OR RSENSE
37881 F01
Figure 1. Sense Lines Placement with
Inductor or Sense Resistor
VBIAS
SENSE+ and SENSE– Pins
The SENSE + and SENSE – pins are the inputs to the current comparators. The common mode input voltage range
of the current comparators is 2.5V to 38V. The current
sense resistor is normally placed at the input of the boost
controller in series with the inductor.
The SENSE + pin also provides power to the current comparator. It draws ~200µA during normal operation. There
is a small base current of less than 1µA that flows into
the SENSE – pin. The high impedance SENSE – input to the
current comparators allow accurate DCR sensing.
Filter components mutual to the sense lines should be
placed close to the LTC3788-1, and the sense lines should
run close together to a Kelvin connection underneath the
current sense element (shown in Figure 1). Sensing current elsewhere can effectively add parasitic inductance
and capacitance to the current sense element, degrading
the information at the sense terminals and making the
programmed current limit unpredictable. If DCR sensing
is used (Figure 2b), sense resistor R1 should be placed
close to the switching node, to prevent noise from coupling into sensitive small-signal nodes.
VBIAS
VIN
VIN
SENSE+
SENSE+
C1
(OPTIONAL)
R2
DCR
SENSE–
SENSE–
INTVCC
INTVCC
R1
LTC3788-1
LTC3788-1
BOOST
BOOST
TG
TG
VOUT
SW
L
INDUCTOR
VOUT
SW
BG
BG
SGND
SGND
37881 F02b
37881 F02a
PLACE C1 NEAR SENSE PINS
(2a) Using a Resistor to Sense Current
(R1||R2) • C1 =
L
DCR
RSENSE(EQ) = DCR •
R2
R1 + R2
(2b) Using the Inductor DCR to Sense Current
Figure 2. Two Different Methods of Sensing Current
Rev D
14
For more information www.analog.com
LTC3788-1
APPLICATIONS INFORMATION
Sense Resistor Current Sensing
A typical sensing circuit using a discrete resistor is shown
in Figure 2a. RSENSE is chosen based on the required output current.
The current comparator has a maximum threshold
VSENSE(MAX). The current comparator threshold sets the
peak of the inductor current, yielding a maximum average
output current, IMAX, equal to the peak value less half the
peak-to-peak ripple current, ∆IL. To calculate the sense
resistor value, use the equation:
R SENSE =
VSENSE(MAX)
IMAX +
ΔIL
2
When using the controller in low VIN and very high voltage
output applications, the maximum output current level will
be reduced due to the internal compensation required to
meet stability criterion for boost regulators operating at
greater than 50% duty factor. A curve is provided in the
Typical Performance Characteristics section to estimate
this reduction in peak output current level depending upon
the operating duty factor.
Inductor DCR Sensing
Using the inductor ripple current value from the Inductor
Value Calculation section, the target sense resistor value is:
R SENSE(EQUIV) =
VSENSE(MAX)
I MAX +
ΔIL
2
To ensure that the application will deliver full load current over the full operating temperature range, choose the
minimum value for the maximum current sense threshold
(VSENSE(MAX)).
Next, determine the DCR of the inductor. Where provided,
use the manufacturer’s maximum value, usually given at
20°C. Increase this value to account for the temperature
coefficient of resistance, which is approximately 0.4%/°C.
A conservative value for the maximum inductor temperature (TL(MAX)) is 100°C.
To scale the maximum inductor DCR to the desired sense
resistor value, use the divider ratio:
RD =
R SENSE(EQUIV)
DCRMAX at TL(MAX)
C1 is usually selected to be in the range of 0.1µF to 0.47µF.
This forces R1|| R2 to around 2k, reducing error that might
have been caused by the SENSE + pin’s ±1µA current.
For applications requiring the highest possible efficiency
at high load currents, the LTC3788-1 is capable of sensing
the voltage drop across the inductor DCR, as shown in
Figure 2b. The DCR of the inductor can be less than 1mΩ
for high current inductors. In a high current application
requiring such an inductor, conduction loss through a
sense resistor could reduce the efficiency by a few percent
compared to DCR sensing.
The equivalent resistance R1|| R2 is scaled to the room
temperature inductance and maximum DCR:
If the external R1||R2 • C1 time constant is chosen to
be exactly equal to the L/DCR time constant, the voltage
drop across the external capacitor is equal to the drop
across the inductor DCR multiplied by R2/(R1 + R2). R2
scales the voltage across the sense terminals for applications where the DCR is greater than the target sense
resistor value. To properly dimension the external filter
components, the DCR of the inductor must be known. It
can be measured using a good RLC meter, but the DCR
tolerance is not always the same and varies with temperature. Consult the manufacturer’s data sheets for detailed
information.
R1|| R2 =
L
(DCR at 20°C) • C1
The sense resistor values are:
R1 =
R1|| R2
RD
; R2 =
R1• RD
1− RD
The maximum power loss in R1 is related to duty cycle,
and will occur in continuous mode at VIN = 1/2 VOUT :
PLOSS R1 =
(VOUT − VIN ) • VIN
R1
Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
power loss when deciding whether to use DCR sensing
or sense resistors. Light load power loss can be modestly
higher with a DCR network than with a sense resistor,
For more information www.analog.com
Rev D
15
LTC3788-1
APPLICATIONS INFORMATION
due to the extra switching losses incurred through R1.
However, DCR sensing eliminates a sense resistor, reduces
conduction losses and provides higher efficiency at heavy
loads. Peak efficiency is about the same with either method.
Inductor Value Calculation
The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use
of smaller inductor and capacitor values. Why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because
of MOSFET gate charge and switching losses. In addition to this basic trade-off, the effect of inductor value
on ripple current and low current operation must also be
considered.
The inductor value has a direct effect on ripple current.
The inductor ripple current ∆IL decreases with higher
inductance or frequency and increases with higher VIN:
ΔIL =
VIN ⎛
V ⎞
1− IN ⎟
⎜
f • L ⎝ VOUT ⎠
Accepting larger values of ∆IL allows the use of low inductances, but results in higher output voltage ripple and
greater core losses. A reasonable starting point for setting
ripple current is ∆IL = 0.3(IMAX). The maximum ∆IL occurs
at VIN = 1/2 VOUT .
The inductor value also has secondary effects. The transition
to Burst Mode operation begins when the average inductor
current required results in a peak current below 10% of the
current limit determined by RSENSE. Lower inductor values
(higher ∆IL) will cause this to occur at lower load currents,
which can cause a dip in efficiency in the upper range of low
current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to decrease.
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite or molypermalloy cores. Actual core loss is independent of core size
for a fixed inductor value, but it is very dependent on
16
inductance selected. As inductance increases, core losses
go down. Unfortunately, because increased inductance
requires more turns of wire, copper losses will increase.
Ferrite core inductors have very low core loss and are
preferred at high switching frequencies, so design goals
can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard,” which means
that inductance collapses abruptly when the peak design
current is exceeded. This results in an abrupt increase in
inductor ripple current and consequent output voltage
ripple. Do not allow the core to saturate!
Power MOSFET Selection
Two external power MOSFETs must be selected for each
controller in the LTC3788-1: one N-channel MOSFET for
the bottom (main) switch, and one N-channel MOSFET
for the top (synchronous) switch.
The peak-to-peak gate drive levels are set by the INTVCC
voltage. This voltage is typically 5.2V during start-up
(see EXTVCC pin connection). Consequently, logic-level
threshold MOSFETs must be used in most applications.
The only exception is if low input voltage is expected (VIN
< 5V); then, sub-logic level threshold MOSFETs (VGS(TH)
< 3V) should be used. Pay close attention to the BVDSS
specification for the MOSFETs as well; many of the logic
level MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the
on-resistance RDS(ON), Miller capacitance CMILLER, input
voltage and maximum output current. Miller capacitance,
CMILLER, can be approximated from the gate charge curve
usually provided on the MOSFET manufacturer’s data
sheet. CMILLER is equal to the increase in gate charge
along the horizontal axis while the curve is approximately
flat divided by the specified change in VDS. This result is
then multiplied by the ratio of the application applied VDS
to the gate charge curve specified VDS. When the IC is
operating in continuous mode, the duty cycles for the top
and bottom MOSFETs are given by:
− VIN
V
Main Switch Duty Cycle = OUT
VOUT
Synchronous Switch Duty Cycle =
For more information www.analog.com
VIN
VOUT
Rev D
LTC3788-1
APPLICATIONS INFORMATION
The MOSFET power dissipations at maximum output current are given by:
PMAIN =
(VOUT − VIN )VOUT
V IN
2
2
• IOUT(MAX) • ( 1+ d )
3 IOUT(MAX)
• RDS(ON) + k • V OUT •
VIN
• RDR
• CMILLER • f
PSYNC =
VIN
VOUT
2
• IOUT(MAX) • ( 1+ d ) • RDS(ON)
where d is the temperature dependency of RDS(ON) and
RDR (approximately 1Ω) is the effective driver resistance
at the MOSFET’s Miller threshold voltage. The constant k,
which accounts for the loss caused by reverse recovery
current, is inversely proportional to the gate drive current
and has an empirical value of 1.7.
Both MOSFETs have I2R losses while the bottom N-channel
equation includes an additional term for transition losses,
which are highest at low input voltages. For high VIN the
high current efficiency generally improves with larger
MOSFETs, while for low VIN the transition losses rapidly
increase to the point that the use of a higher RDS(ON)
device with lower CMILLER actually provides higher efficiency. The synchronous MOSFET losses are greatest at
high input voltage when the bottom switch duty factor is
low or during overvoltage when the synchronous switch
is on close to 100% of the period.
The term (1+ d) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs Temperature curve, but
d = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
CIN and COUT Selection
The input ripple current in a boost converter is relatively
low (compared with the output ripple current), because
this current is continuous. The input capacitor CIN voltage rating should comfortably exceed the maximum input
voltage. Although ceramic capacitors can be relatively
tolerant of overvoltage conditions, aluminum electrolytic capacitors are not. Be sure to characterize the input
voltage for any possible overvoltage transients that could
apply excess stress to the input capacitors.
The value of the CIN is a function of the source impedance,
and in general, the higher the source impedance, the higher
the required input capacitance. The required amount of
input capacitance is also greatly affected by the duty cycle.
High output current applications that also experience high
duty cycles can place great demands on the input supply,
both in terms of DC current and ripple current.
In a boost converter, the output has a discontinuous current, so COUT must be capable of reducing the output
voltage ripple. The effects of ESR (equivalent series resistance) and the bulk capacitance must be considered when
choosing the right capacitor for a given output ripple voltage. The steady ripple voltage due to charging and discharging the bulk capacitance is given by:
VRIPPLE =
IOUT(MAX) • (VOUT − VIN(MIN) )
COUT • VOUT • f
V
where COUT is the output filter capacitor.
The steady ripple due to the voltage drop across the ESR
is given by:
∆VESR = IL(MAX) • ESR
The LTC3788-1 can also be configured as a 2-phase single
output converter where the outputs of the two channels
are connected together and both channels have the same
duty cycle. With 2-phase operation, the two channels of
the dual switching regulator are operated 180 degrees
out-of-phase. This effectively interleaves the output current pulses, greatly reducing the output capacitor ripple
current. As a result, the ESR requirement of the capacitor
can be relaxed. Because the ripple current in the output
capacitor is a square wave, the ripple current requirements for the output capacitor depend on the duty cycle,
the number of phases and the maximum output current.
Figure 3 illustrates the normalized output capacitor ripple
current as a function of duty cycle in a 2-phase configuration. To choose a ripple current rating for the output
capacitor, first establish the duty cycle range based on
the output voltage and range of input voltage. Referring
to Figure 3, choose the worst-case high normalized ripple
current as a percentage of the maximum load current.
Rev D
For more information www.analog.com
17
LTC3788-1
IORIPPLE /IOUT
APPLICATIONS INFORMATION
3.25
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
0.1
Soft-Start (SS Pins)
The start-up of each VOUT is controlled by the voltage on
the respective SS pins. When the voltage on the SS pin
is less than the internal 1.2V reference, the LTC3788-1
regulates the VFB pin voltage to the voltage on the SS
pin instead of 1.2V.
1-PHASE
2-PHASE
0.2
0.3 0.4 0.5 0.6 0.7 0.8
DUTY CYCLE OR (1-VIN /VOUT)
0.9
37881 F03
Figure 3. Normalized Output Capacitor Ripple
Current (RMS) for a Boost Converter
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, aluminum electrolytic and
ceramic capacitors are all available in surface mount
packages. Ceramic capacitors have excellent low ESR
characteristics but can have a high voltage coefficient.
Capacitors are now available with low ESR and high ripple
current ratings (i.e., OS-CON and POSCAP).
Setting Output Voltage
The LTC3788-1 output voltages are each set by an external feedback resistor divider carefully placed across the
output, as shown in Figure 4. The regulated output voltage
is determined by:
⎛ R ⎞
VOUT = 1.2V ⎜ 1+ B ⎟
⎝ RA ⎠
Great care should be taken to route the VFB line away from
noise sources, such as the inductor or the SW line.
VOUT
LTC3788-1
RB
VFB
RA
37881 F04
Figure 4. Setting Output Voltage
Soft-start is enabled by simply connecting a capacitor
from the SS pin to ground, as shown in Figure 5. An internal 10µA current source charges the capacitor, providing
a linear ramping voltage at the SS pin. The LTC3788-1
will regulate the VFB pin (and hence, VOUT) according to
the voltage on the SS pin, allowing VOUT to rise smoothly
from VIN to its final regulated value. The total soft-start
time will be approximately:
tSS = CSS •
1.2V
10µA
LTC3788-1
SS
CSS
SGND
37881 F05
Figure 5. Using the SS Pin to Program Soft-Start
INTVCC Regulators
The LTC3788-1 features two separate internal P-channel
low dropout linear regulators (LDO) that supply power at
the INTVCC pin from either the VBIAS supply pin or the
EXTVCC pin depending on the connection of the EXTVCC
pin. INTVCC powers the gate drivers and much of the
LTC3788-1’s internal circuitry. The VBIAS LDO and the
EXTVCC LDO regulate INTVCC to 5.4V. Each of these can
supply a peak current of 50mA and must be bypassed to
ground with a minimum of 4.7µF ceramic capacitor. Good
bypassing is needed to supply the high transient currents
required by the MOSFET gate drivers and to prevent interaction between the channels.
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maximum junction temperature rating for the LTC3788-1 to be
exceeded. The INTVCC current, which is dominated by the
gate charge current, may be supplied by either the VBIAS
LDO or the EXTVCC LDO. When the voltage on the EXTVCC
pin is less than 4.8V, the VBIAS LDO is enabled. In this
Rev D
18
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LTC3788-1
APPLICATIONS INFORMATION
case, power dissipation for the IC is highest and is equal
to VIN • IINTVCC. The gate charge current is dependent
on operating frequency, as discussed in the Efficiency
Considerations section. The junction temperature can be
estimated by using the equations given in Note 3 of the
Electrical Characteristics. For example, the LTC3788-1
INTVCC current is limited to less than 15mA from a 40V
supply when not using the EXTVCC supply:
TJ = 70°C + (15mA)(40V)(90°C/W) = 125°C
To prevent the maximum junction temperature from being
exceeded, the input supply current must be checked while
operating in continuous conduction mode (PLLIN/MODE
= INTVCC) at maximum VIN.
When the voltage applied to EXTVCC rises above 4.8V, the
VIN LDO is turned off and the EXTVCC LDO is enabled. The
EXTVCC LDO remains on as long as the voltage applied to
EXTVCC remains above 4.55V. The EXTVCC LDO attempts
to regulate the INTVCC voltage to 5.4V, so while EXTVCC
is less than 5.4V, the LDO is in dropout and the INTVCC
voltage is approximately equal to EXTVCC. When EXTVCC
is greater than 5.4V, up to an absolute maximum of 6V,
INTVCC is regulated to 5.4V.
Significant thermal gains can be realized by powering
INTVCC from an external supply. Tying the EXTVCC pin
to a 5V supply reduces the junction temperature in the
previous example from 125°C to 77°C:
TJ = 70°C + (15mA)(5V)(90°C/W) = 77°C
If more current is required through the EXTVCC LDO than
is specified, an external Schottky diode can be added
between the EXTVCC and INTVCC pins. Make sure that in
all cases EXTVCC ≤ VBIAS.
The following list summarizes possible connections for
EXTVCC:
EXTVCC Left Open (or Grounded). This will cause
INTVCC to be powered from the internal 5.4V regulator
resulting in an efficiency penalty at high input voltages.
EXTVCC Connected to an External Supply. If an external supply is available in the 5.4V to 6V range, it may
be used to power EXTVCC providing it is compatible
with the MOSFET gate drive requirements. Ensure that
EXTVCC < VBIAS.
Topside MOSFET Driver Supply (CB, DB)
External bootstrap capacitors CB connected to the BOOST
pins supply the gate drive voltages for the topside
MOSFETs. Capacitor CB in the Block Diagram is charged
though external diode DB from INTVCC when the SW pin is
low. When one of the topside MOSFETs is to be turned on,
the driver places the CB voltage across the gate-source
of the desired MOSFET. This enhances the MOSFET and
turns on the topside switch. The switch node voltage,
SW, rises to VIN and the BOOST pin follows. With the
topside MOSFET on, the boost voltage is above the input
supply: VBOOST = VIN + VINTVCC. The value of the boost
capacitor CB needs to be 100 times that of the total input
capacitance of the topside MOSFET(s). The reverse breakdown of the external Schottky diode must be greater than
VIN(MAX).
The external diode DB can be a Schottky diode or silicon
diode, but in either case it should have low leakage and
fast recovery. Pay close attention to the reverse leakage at high temperatures where it generally increases
substantially.
Each of the topside MOSFET drivers includes an internal charge pump that delivers current to the bootstrap
capacitor from the BOOST pin. This charge current maintains the bias voltage required to keep the top MOSFET
on continuously during dropout/overvoltage conditions.
The Schottky/silicon diodes selected for the topside drivers should have a reverse leakage less than the available output current the charge pump can supply. Curves
displaying the available charge pump current under different operating conditions can be found in the Typical
Performance Characteristics section.
A leaky diode DB in the boost converter can not only prevent the top MOSFET from fully turning on but it can also
completely discharge the bootstrap capacitor CB and create a current path from the input voltage to the BOOST
pin to INTVCC. This can cause INTVCC to rise if the diode
leakage exceeds the current consumption on INTVCC.
This is particularly a concern in Burst Mode operation
where the load on INTVCC can be very small. The external
Schottky or silicon diode should be carefully chosen such
that INTVCC never gets charged up much higher than its
normal regulation voltage.
Rev D
For more information www.analog.com
19
LTC3788-1
APPLICATIONS INFORMATION
At higher temperatures, or in cases where the internal
power dissipation causes excessive self-heating on chip
(such as an INTVCC short to ground), the overtemperature
shutdown circuitry will shut down the LTC3788-1. When
the junction temperature exceeds approximately 170°C,
the overtemperature circuitry disables the INTVCC LDO,
causing the INTVCC supply to collapse and effectively shut
down the entire LTC3788-1 chip. Once the junction temperature drops back to approximately 155°C, the INTVCC
LDO turns back on. Long term overstress (TJ > 125°C)
should be avoided as it can degrade the performance or
shorten the life of the part.
Phase-Locked Loop and Frequency Synchronization
The LTC3788-1 has an internal phase-locked loop (PLL)
comprised of a phase frequency detector, a low pass filter
and a voltage-controlled oscillator (VCO). This allows the
turn-on of the top MOSFET of controller 1 to be locked
to the rising edge of an external clock signal applied to
the PLLIN/MODE pin. The turn-on of controller 2’s top
MOSFET is thus 180 degrees out-of-phase with the external clock. The phase detector is an edge-sensitive digital type that provides zero degrees phase shift between
the external and internal oscillators. This type of phase
detector does not exhibit false lock to harmonics of the
external clock.
If the external clock frequency is greater than the internal
oscillator’s frequency, fOSC, then current is sourced continuously from the phase detector output, pulling up the
VCO input. When the external clock frequency is less than
fOSC, current is sunk continuously, pulling down the VCO
input. If the external and internal frequencies are the same
but exhibit a phase difference, the current sources turn
on for an amount of time corresponding to the phase difference. The voltage at the VCO input is adjusted until the
phase and frequency of the internal and external oscillators are identical. At the stable operating point, the phase
detector output is high impedance and the internal filter
capacitor, CLP, holds the voltage at the VCO input.
Typically, the external clock (on PLLIN/MODE pin) input
high threshold is 1.6V, while the input low threshold is 1.2V.
Note that the LTC3788-1 can only be synchronized to
an external clock whose frequency is within range of the
LTC3788-1’s internal VCO, which is nominally 55kHz to
1MHz. This is guaranteed to be between 75kHz and 850kHz.
Rapid phase locking can be achieved by using the FREQ
pin to set a free-running frequency near the desired synchronization frequency. The VCO’s input voltage is prebiased at a frequency corresponding to the frequency set
by the FREQ pin. Once prebiased, the PLL only needs
to adjust the frequency slightly to achieve phase lock
and synchronization. Although it is not required that the
free-running frequency be near external clock frequency,
doing so will prevent the operating frequency from passing through a large range of frequencies as the PLL locks.
Table 1 summarizes the different states in which the FREQ
pin can be used.
Table 1.
FREQ PIN
PLLIN/MODE PIN
FREQUENCY
0V
DC Voltage
350kHz
INTVCC
DC Voltage
535kHz
Resistor
DC Voltage
50kHz to 900kHz
Any of the Above
External Clock
Phase Locked to
External Clock
1000
900
800
FREQUENCY (kHz)
Fault Conditions: Overtemperature Protection
700
600
500
400
300
200
100
0
15 25 35 45 55 65 75 85 95 105 115 125
FREQ PIN RESISTOR (kΩ)
37881 F06
Figure 6. Relationship Between Oscillator
Frequency and Resistor Value at the FREQ Pin
Rev D
20
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LTC3788-1
APPLICATIONS INFORMATION
Minimum On-Time Considerations
Minimum on-time, tON(MIN), is the smallest time duration
that the LTC3788-1 is capable of turning on the bottom
MOSFET. It is determined by internal timing delays and
the gate charge required to turn on the top MOSFET. Low
duty cycle applications may approach this minimum ontime limit.
In forced continuous mode, if the duty cycle falls below
what can be accommodated by the minimum on-time, the
controller will begin to skip cycles but the output will continue to be regulated. More cycles will be skipped when
VIN increases. Once VIN rises above VOUT , the loop works
to keep the top MOSFET on continuously. The minimum
on-time for the LTC3788-1 is approximately 110ns.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the greatest improvement. Percent efficiency can
be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc., are the individual losses as a percentage of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3788-1 circuits: 1) IC VIN current, 2) INTVCC
regulator current, 3) I2R losses, 4) Bottom MOSFET transition losses.
1. The VIN current is the DC supply current given in the
Electrical Characteristics table, which excludes MOSFET
driver and control currents. VIN current typically results
in a small (1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT, causing a rapid drop in VOUT. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
CLOAD to COUT is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited to
approximately 25 • CLOAD. Thus, a 10µF capacitor would
require a 250µs rise time, limiting the charging current
to about 200mA.
Design Example
As a design example for one channel, assume VIN =
12V(nominal), VIN = 22V (max), VOUT = 24V, IOUT(MAX) =
4A, VSENSE(MAX) = 75mV, and f = 350kHz.
The inductance value is chosen first based on a 30% ripple current assumption. The highest value of ripple current occurs at the maximum input voltage. Tie the PLLLPF
pin to GND, generating 350kHz operation. The minimum
inductance for 30% ripple current is:
ΔIL =
VIN ⎛
V ⎞
1− IN ⎟
⎜
f • L ⎝ VOUT ⎠
A 6.8µH inductor will produce a 30% ripple current. The
peak inductor current will be the maximum DC value plus
one half the ripple current, or 9.25A.
The RSENSE resistor value can be calculated by using the
maximum current sense voltage specification with some
accommodation for tolerances:
R SENSE ≤
75mV
9.25A
= 0.008Ω
Choosing 1% resistors: RA = 5k and RB = 95.3k yields an
output voltage of 24.072V.
The power dissipation on the top side MOSFET can
be easily estimated. Choosing a Vishay Si7848BDP
MOSFET results in: RDS(ON) = 0.012Ω, CMILLER = 150pF.
At maximum input voltage with T(estimated) = 50°C:
PMAIN =
(24V − 12V) 24V
2
(12V)
• (4A)2
• [ 1+ (0.005)(50°C − 25°C)] • 0.008Ω
+ (1.7)(24V)3
4A
12V
(150pF)(350kHz) = 0.7W
COUT is chosen to filter the square current in the output.
The maximum output current peak is:
⎛ 31% ⎞
IOUT(PEAK) = 4 • ⎜ 1+
⎟ = 4.62A
⎝
2 ⎠
A low ESR (5mΩ) capacitor is suggested. This capacitor
will limit output voltage ripple to 23.1mV (assuming ESR
dominate ripple).
Rev D
22
For more information www.analog.com
LTC3788-1
APPLICATIONS INFORMATION
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 7. Figure 8 illustrates the current waveforms present in the various branches of the
2-phase synchronous regulators operating in the continuous mode. Check the following in your layout:
1. Put the bottom N-channel MOSFETs MBOT1 and
MBOT2 and the top N-channel MOSFETs MTOP1 and
MTOP2 in one compact area with COUT.
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return of
CINTVCC must return to the combined COUT (–) terminals.
The path formed by the bottom N-channel MOSFET and
the CIN capacitor should have short leads and PC trace
lengths. The output capacitor (–) terminals should be
connected as close as possible to the (–) terminals of
the input capacitor by placing the capacitors next to
each other.
3. Do the LTC3788-1 VFB pins’ resistive dividers connect
to the (+) terminals of COUT? The resistive divider must
be connected between the (+) terminal of COUT and
signal ground and placed close to the VFB pin. The
feedback resistor connections should not be along the
high current input feeds from the input capacitor(s).
4. Are the SENSE – and SENSE + leads routed together
with minimum PC trace spacing? The filter capacitor
between SENSE + and SENSE – should be as close as
possible to the IC. Ensure accurate current sensing
with Kelvin connections at the sense resistor.
5. Is the INTVCC decoupling capacitor connected close
to the IC, between the INTVCC and the power ground
pins? This capacitor carries the MOSFET drivers’ current peaks. An additional 1µF ceramic capacitor placed
immediately next to the INTVCC and PGND pins can
help improve noise performance substantially.
6. Keep the switching nodes (SW1, SW2), top gate nodes
(TG1, TG2) and boost nodes (BOOST1, BOOST2) away
from sensitive small-signal nodes, especially from
the opposites channel’s voltage and current sensing
feedback pins. All of these nodes have very large and
fast moving signals and, therefore, should be kept on
the output side of the LTC3788-1 and occupy a minimal
PC trace area.
7. Use a modified “star ground” technique: a low impedance, large copper area central grounding point on the
same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTVCC
decoupling capacitor, the bottom of the voltage feedback resistive divider and the SGND pin of the IC.
PC Board Layout Debugging
Start with one controller on at a time. It is helpful to use
a DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope
to the internal oscillator and probe the actual output voltage. Check for proper performance over the operating
voltage and current range expected in the application.
The frequency of operation should be maintained over the
input voltage range down to dropout and until the output
load drops below the low current operation threshold—
typically 10% of the maximum designed current level in
Burst Mode operation.
The duty cycle percentage should be maintained from
cycle to cycle in a well designed, low noise PCB implementation. Variation in the duty cycle at a subharmonic
rate can suggest noise pickup at the current or voltage sensing inputs or inadequate loop compensation.
Overcompensation of the loop can be used to tame a
poor PC layout if regulator bandwidth optimization is not
required. Only after each controller is checked for its individual performance should both controllers be turned on
at the same time. A particularly difficult region of operation is when one controller channel is nearing its current
comparator trip point while the other channel is turning
on its bottom MOSFET. This occurs around the 50% duty
cycle on either channel due to the phasing of the internal
clocks and may cause minor duty cycle jitter.
Reduce VIN from its nominal level to verify operation with
high duty cycle. Check the operation of the undervoltage
lockout circuit by further lowering VIN while monitoring
the outputs to verify operation.
Rev D
For more information www.analog.com
23
LTC3788-1
APPLICATIONS INFORMATION
Investigate whether any problems exist only at higher output currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
for inductive coupling between CIN, Schottky and the top
MOSFET components to the sensitive current and voltage
SENSE1–
SENSE1+
SS1
PGOOD1
SW1
TG1
LTC3788-1
sensing traces. In addition, investigate common ground
path voltage pickup between these components and the
SGND pin of the IC.
An embarrassing problem, which can be missed in an otherwise properly working switching regulator results when
the current sensing leads are hooked up backwards. The
output voltage under this improper hook-up will still be
maintained, but the advantages of current mode control
will not be realized. Compensation of the voltage loop
will be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
the current sensing resistor—don’t worry, the regulator
will still maintain control of the output voltage.
VPULL-UP
L1
CB1
BOOST1
BG1
VFB1
VBIAS
FREQ
PLLIN/MODE
SGND
RUN1
RUN2
M2
GND
PGND
EXTVCC
INTVCC
BG2
VFB2
BOOST2
ITH2
TG2
SW2
CB2
VOUT1
+
M1
+
fIN
ITH1
RSENSE1
M3
VIN
+
M4
VOUT2
L2
RSENSE2
SS2
SENSE2+
SENSE2–
37881 F07
Figure 7. Recommended Printed Circuit Layout Diagram
Rev D
24
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LTC3788-1
APPLICATIONS INFORMATION
RSENSE1
L1
SW1
VOUT1
COUT1
RL1
VIN
RIN
CIN
RSENSE2
BOLD LINES INDICATE
HIGH SWITCHING
CURRENT. KEEP LINES
TO A MINIMUM LENGTH.
L2
SW2
VOUT2
COUT2
RL2
37881 F08
Figure 8. Branch Current Waveforms
Rev D
For more information www.analog.com
25
LTC3788-1
APPLICATIONS INFORMATION
RA1
12.1k
RB1
232k
SENSE1–
SENSE1+
VFB1
CITH1
220pF
CITH1
15nF
RITH1
8.66k
CSS1
0.1µF
PGOOD2
PGOOD1
TG1
LTC3788-1
SW1
100k
INTVCC
MTOP1
L1
3.3µH
RSENSE1
4mΩ
COUTA1
22µF
×4
+
COUTB1
220µF
CB1
0.1µF
BOOST1
BG1
ITH1
SS1
SS2
ITH2
VFB2
MBOT1
VBIAS
INTVCC
CINT
4.7µF
PGND
BG2
PLLIN/MODE BOOST2
SGND
SW2
EXTVCC
RUN1
TG2
RUN2
FREQ
CB1
0.1µF
CINA
22µF
×4
+
VIN
5V TO 24V
CINB
220µF
VOUT
24V, 10A*
MBOT2
L2
3.3µH
RSENSE2
4mΩ
MTOP2
COUTA2
22µF
×4
SENSE2+
SENSE2–
+
COUTB2
220µF
37881 F09
CINA, COUTA1, COUTA2: SANYO, 50CE220AX
CINB, COUTB1, COUTB2: TDK C4532X5R1E226M
L1, L2: PULSE PA1494.362NL
MBOT1, MBOT2, MTOP1, MTOP2: RENESAS HAT2169H
*WHEN VIN < 8V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED.
Figure 9. High Efficiency 2-Phase 24V Boost Converter
Rev D
26
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LTC3788-1
APPLICATIONS INFORMATION
RS1, 53.6k, 1%
RS2
26.1k, 1%
RB1
232k
1%
C1
0.1µF
C3
0.1µF
RA1
12.1k, 1%
SENSE1–
SENSE1+
CITH1, 220pF
D3
MTOP1
TG1
L1
10.2µH
ITH1
BG1
CB1, 0.1µF
COUTB1
220µF
MBOT1
D1
SS1
INTVCC
PLLIN/MODE
SGND
VBIAS
INTVCC
RUN1
RFREQ
41.2k
RUN2
CINA
22µF
×4
CINT
4.7µF
PGND
EXTVCC
D2
BG2
CB1, 0.1µF
RITH2
23.7k, 1%
+
VIN
5V TO 24V
CINB
220µF
MBOT2B
MBOT2A
BOOST2
FREQ
CSS2, 0.01µF
L2
16µH
SS2
SW2
ITH2
TG2
D4
CITH2A, 220pF
RA2
12.1k, 1%
MTOP2
COUTA2
22µF
×4
VFB2
C4
0.1µF
RS4
30.1k, 1%
+
SW1
RITH1
8.87k, 1%
RB2
475k
1%
COUTA1
6.8µF
×4
VOUT1
24V, 4A
BOOST1
CSS1, 0.01µF
CITH2, 4.7nF
INTVCC
LTC3788-1
VFB1
CITH1, 15nF
PGOOD1
100k
C2
0.1µF
SENSE2+
+
VOUT2
48V, 2A
COUTB2
220µF
SENSE2–
RS3 42.2k, 1%
COUTA2: C4532x7R1H685K
COUTB2: SANYO 63CE220KX
CINA, COUTA1: TDK C4532X5R1E226M
CINB, COUTB1: SANYO 50CE220AX
L1: PULSE PA2050.103NL
L2: PULSE PA2050.163NL
MBOT1, MTOP1: RENESAS RJK0305
MBOT2A, MBOT2B, MTOP2: RENESAS RJK0652
D3: DIODES INC B340B
D4: DIODES INC B360A
37881 F10
Figure 10. High Efficiency Dual 24V/48V Boost Converter with Inductor DCR Current Sensing
Rev D
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27
LTC3788-1
PACKAGE DESCRIPTION
GN Package
28-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641 Rev B)
.386 – .393*
(9.804 – 9.982)
.045 ±.005
28 27 26 25 24 23 22 21 20 19 18 17 1615
.254 MIN
.033
(0.838)
REF
.150 – .165
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
.0250 BSC
.0165 ±.0015
1
RECOMMENDED SOLDER PAD LAYOUT
.015 ±.004
× 45°
(0.38 ±0.10)
.0075 – .0098
(0.19 – 0.25)
2 3
4
5 6
7
8
.0532 – .0688
(1.35 – 1.75)
9 10 11 12 13 14
.004 – .0098
(0.102 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
.008 – .012
(0.203 – 0.305)
TYP
.0250
(0.635)
BSC
GN28 REV B 0212
3. DRAWING NOT TO SCALE
4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Rev D
28
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LTC3788-1
REVISION HISTORY
REV
DATE
DESCRIPTION
A
3/10
Updates to Typical Application.
Updates in the Electrical Characteristics section.
Updates to PLLIN/MODE in Pin Functions.
Updates to Applications Information.
B
9/11
C
1/12
D
9/18
PAGE NUMBER
1
3, 4
9
15, 19, 22
New Figure 9 added.
26
Updated Note on Typical Application.
30
Updated Related Parts Table.
30
Updated the Topside MOSFET Driver Supply (CB, DB) section.
19
Updated the Related Parts.
30
Revised Figure 10.
27
Updated PGOOD section in the Electrical Characteristics tables.
4
Rev D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
more by
information
www.analog.com
29
LTC3788-1
TYPICAL APPLICATION
INTVCC
High Efficiency Dual 12V/24V Boost Converter
RB1
232k
1%
SENSE1–
SENSE1+
RA1
12.1k, 1%
INTVCC
TG1
VFB1
CITH1, 220pF
RSENSE1
4mΩ
COUTA1
22µF
×4
+
VOUT1*
24V, 5A
COUTB1
220µF
BOOST1
ITH1
LTC3788-1
BG1
CB1, 0.1µF
MBOT1
D1
CSS1, 0.1µF
SS1
VBIAS
INTVCC
PGND
PLLIN/MODE
SGND
BG2
EXTVCC
RUN1
BOOST2
RUN2
FREQ
CSS2, 0.1µF
CITH2, 15nF
L1
MTOP1 3.3µH
SW1
RITH1
8.66k
CITH1, 15nF
PGOOD1
100k
RITH2
2.7k
CITHA2, 100pF
RA2
12.1k
SS2
SW2
ITH2
TG2
CINA
22µF
×4
CINT
4.7µF
CINB
220µF
D2
CB1, 0.1µF
MBOT2
L2
1.25µH
RSENSE2
3mΩ
MTOP2
COUTA2
22µF
×4
VFB2
SENSE2+
SENSE2–
RB2
110k
+
VIN
5V TO 24V
+
VOUT2*
12V, 10A
COUTB2
220µF
37881 TA02
CINA, COUTA1, COUTA2: SANYO, 50CE220AX
CINB, COUTB1, COUTB2: TDK C4532X5R1E226M
L1: PULSE PA1494.362NL
L2: PULSE PA1294.132NL
MBOT1, MBOT2, MTOP1, MTOP2: RENESAS HAT2169H
* WHEN VIN < 8V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC3787/LTC3787-1 Multiphase, Dual Channel Synchronous
Step-Up Controller
4.5V (Down to 2.5V After Start-Up) ≤ VIN ≤ 38V, VOUT Up to 60V, 50kHz to 900kHz
Fixed Operating Frequency, 4mm × 5mm QFN-28, SSOP-28
Low IQ Synchronous Step-Up Controller
4.5V (Down to 2.5V After Start-Up) ≤ VIN ≤ 38V, VOUT Up to 60V, 50kHz to 900kHz
Fixed Operating Frequency, 3mm × 3mm QFN-32, MSOP-16E
LTC3862/LTC3862-1 Multiphase, Dual Channel Single Output
Current Mode Step-Up DC/DC Controller
4V ≤ VIN ≤ 36V, 5V or 10V Gate Drive, 75kHz to 500kHz Fixed Operating Frequency,
SSOP-24, TSSOP-24, 5mm × 5mm QFN-24
LTC3786
LTC3859A
Low IQ, Triple Output Buck/Buck/Boost
Synchronous DC/DC Controller
All Outputs Remain in Regulation Through Cold Crank, 4.5V (Down to 2.5V After
Start-Up) ≤ VIN ≤ 38V, VOUT(BUCK) Up to 24V, VOUT(BOOST) Up to 60V, IQ = 55µA
LTC3789
High Efficiency Synchronous 4-Switch
Buck-Boost DC/DC Controller
4V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 38V, SSOP-28, 4mm × 5mm QFN-28, SSOP-28
Rev D
30
D17164-0-9/18(D)
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