LTC3810-5
60V Current Mode
Synchronous Switching
Regulator Controller
Description
Features
High Voltage Operation: Up to 60V
n Large 1Ω Gate Drivers
n No Current Sense Resistor Required
n Dual N-Channel MOSFET Synchronous Drive
n Extremely Fast Transient Response
n ±0.5% 0.8V Voltage Reference
n Programmable Output Voltage Tracking/Soft-Start
n Generates 5.5V Driver Supply from Input Supply
n Synchronizable to External Clock
n Selectable Pulse Skip Mode Operation
n Power Good Output Voltage Monitor
n Adjustable On-Time/Frequency: t
ON(MIN) < 100ns
n Adjustable Cycle-by-Cycle Current Limit
n Programmable Undervoltage Lockout
n Output Overvoltage Protection
n 5mm × 5mm QFN Package
The LTC®3810-5 is a synchronous step-down switching
regulator controller that can directly step-down voltages
from up to 60V, making it ideal for telecom and automotive applications. The LTC3810-5 uses a constant on-time
valley current control architecture to deliver very low duty
cycles with accurate cycle-by-cycle current limit, without
requiring a sense resistor.
n
A precise internal reference provides 0.5% DC accuracy. A
high bandwidth (25MHz) error amplifier provides very fast
line and load transient response. Large 1Ω gate drivers
allow the LTC3810-5 to drive multiple MOSFETs for higher
current applications. The operating frequency is selected
by an external resistor and is compensated for variations
in VIN and can also be synchronized to an external clock
for switching-noise sensitive applications. A shutdown
pin allows the LTC3810-5 to be turned off, reducing the
supply current to 240µA.
Applications
48V Telecom and Base Station Power Supplies
n Networking Equipment, Servers
n Automotive and Industrial Control Systems
n
L, LT, LTC, LTM, Linear Technology, the Linear logo and No RSENSE are registered trademarks
of Linear Technology Corporation. All other trademarks are the property of their respective
owners. Protected by U.S. Patents including 5481178, 5847554, 6304066, 6476589, 6580258,
6677210, 6774611.
Integrated bias control generates gate drive power from
the input supply during start-up or when an output shortcircuit occurs, with the addition of a small external SOT23
MOSFET. When in regulation, power is derived from the
output for higher efficiency.
Typical Application
Efficiency vs Load Current
High Efficiency High Voltage Step-Down Converter
ION
VRNG
SS/TRACK
47pF
5pF
200k
VIN = 24V
BOOST
LTC3810-5
MODE/SYNC
1000pF
22µF
ZXMN10A07F
NDRV
PGOOD
+
100k
100
TG
Si7450DP
0.1µF
DRVCC
INTVCC
ITH
SENSE+
SENSE–
BGRTN
95
VIN = 42V
90
14k
+
MBR1100
270µF
Si7450DP
BG
SGND
VOUT
12V/6A
EXTVCC
SHDN
VFB
10µH
SW
EFFICIENCY (%)
274k
VIN
13V TO 60V
1µF
85
0
1
2
3
4
LOAD CURRENT (A)
5
6
38105 TA01b
1k
38105 TA01
38105fd
1
LTC3810-5
SW
TG
BOOST
NC
NC
NC
ION
TOP VIEW
NC
32 31 30 29 28 27 26 25
24 SENSE+
NC 1
VON 2
23 NC
VRNG 3
22 NC
PGOOD 4
21 NC
33
MODE/SYNC 5
20 SENSE–
ITH 6
19 BGRTN
VFB 7
18 BG
PLL/LPF 8
17 DRVCC
INTVCC
EXTVCC
NDRV
UVIN
SHDN
9 10 11 12 13 14 15 16
NC
Supply Voltages
INTVCC, DRVCC....................................... –0.3V to 14V
(DRVCC – BGRTN), (BOOST – SW)......... –0.3V to 14V
BOOST (Continuous)............................... –0.3V to 85V
BOOST (≤400ms)................................... –0.3V to 95V
BGRTN......................................................... –5V to 0V
EXTVCC................................................... –0.3V to 15V
(EXTVCC – INTVCC)................................... –12V to 12V
(NDRV – INTVCC) Voltage........................... –0.3V to 10V
SW, SENSE+ Voltage (Continuous)..................–1V to 70V
SW, SENSE+ Voltage (400ms).........................–1V to 80V
ION Voltage (Continuous)............................. –0.3V to 70V
ION Voltage (400ms).................................... –0.3V to 80V
SS/TRACK Voltage........................................ –0.3V to 5V
PGOOD Voltage............................................. –0.3V to 7V
VRNG, VON, MODE/SYNC, SHDN,
UVIN Voltages............................................. –0.3V to 14V
PLL/LPF, FB Voltages................................. –0.3V to 2.7V
TG, BG, INTVCC, EXTVCC RMS Currents.................50mA
Operating Junction Temperature Range (Notes 2, 3, 7)
LTC3810E-5........................................ –40°C to 125°C
LTC3810I-5......................................... –40°C to 125°C.
LTC3810H-5........................................ –40°C to 150°C
Storage Temperature Range................... –65°C to 125°C
Pin Configuration
NC
(Note 1)
SS/TRACK
Absolute Maximum Ratings
UH PACKAGE
32-LEAD (5mm × 5mm) PLASTIC QFN
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD (PIN 33) IS SGND, MUST BE SOLDERED TO PCB
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3810EUH-5#PBF
LTC3810EUH-5#TRPBF
38105
–40°C to 125°C
32-Lead (5mm × 5mm) Plastic QFN
LTC3810IUH-5#PBF
LTC3810IUH-5#TRPBF
38105
–40°C to 125°C
32-Lead (5mm × 5mm) Plastic QFN
LEAD BASED FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3810EUH-5
LTC3810EUH-5#TR
38105
–40°C to 125°C
32-Lead (5mm × 5mm) Plastic QFN
LTC3810IUH-5
LTC3810IUH-5#TR
38105
–40°C to 125°C
32-Lead (5mm × 5mm) Plastic QFN
LTC3810HUH-5
LTC3810HUH-5#TR
38105
–40°C to 150°C
32-Lead (5mm × 5mm) Plastic QFN
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
38105fd
2
LTC3810-5
Electrical
Characteristics
The
l denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 2), INTVCC = DRVCC = VBOOST = VON = VRNG = SHDN = UVIN =
VEXTVCC = VNDRV = 5V, VMODE/SYNC = VSENSE+ = VSENSE – = VBGRTN = VSW = 0V, unless otherwise specified.
SYMBOL
Main Control Loop
INTVCC
IQ
PARAMETER
IBOOST
INTVCC Supply Voltage
INTVCC Supply Current
INTVCC Shutdown Current
BOOST Supply Current
VFB
Feedback Voltage
DVFB,LINE
VSENSE(MAX)
Feedback Voltage Line Regulation
VSENSE(MIN)
Minimum Current Sense Threshold
IVFB
AVOL(EA)
fU
Feedback Current
Error Amplifier DC Open Loop Gain
Error Amp Unity-Gain Crossover
Frequency
MODE/SYNC Threshold
MODE/SYNC Current
Shutdown Threshold
SHDN Pin Input Current
UVIN Undervoltage Lockout
VMODE/SYNC
IMODE/SYNC
VSHDN
ISHDN
VUVIN
VVCCUV
Maximum Current Sense Threshold
INTVCC Undervoltage Lockout
Linear Regulator Mode
External Supply Mode
Trickle-Charge Mode
Oscillator and Phase-Locked Loop
On-Time
tON
tON(MIN)
tOFF(MIN)
tON(PLL)
IPLL/LPF
Driver
IBG,PEAK
RBG,SINK
ITG,PEAK
RTG,SINK
Minimum On-Time
Minimum Off-Time
tON Modulation Range by PLL
Down Modulation
Up Modulation
Phase Detector Output Current
Sinking Capability
Sourcing Capability
BG Driver Peak Source Current
BG Driver Pull-Down RDS(ON)
TG Driver Peak Source Current
TG Driver Pull-Down RDS(ON)
CONDITIONS
MIN
l
SHDN > 1.5V (Notes 4, 5)
SHDN = 0V
SHDN > 1.5V (Note 5)
SHDN = 0V
(Note 4)
0°C to 85°C
–40°C to 85°C
–40°C to 125°C (I-Grade)
–40°C to 150°C (H-Grade)
5V < INTVCC < 14V (Note 4)
l
l
l
l
0.796
0.794
0.792
0.792
0.792
256
70
170
65
(Note 6)
VMODE/SYNC Rising
MODE/SYNC = 5V
MAX
UNITS
3
240
270
0
0.800
0.800
0.800
0.800
0.800
0.002
14
6
600
400
5
0.804
0.806
0.806
0.808
0.812
0.02
V
mA
µA
µA
µA
V
V
V
V
V
%/V
320
95
215
–300
–85
–200
20
100
25
384
120
260
mV
mV
mV
mV
mV
mV
nA
dB
MHz
0.8
0
1.5
0
0.89
0.80
0.10
0.85
1
2
1
0.92
0.82
0.12
V
µA
V
µA
V
V
V
4.35
l
VRNG = 2V, VFB = 0.76V
VRNG = 0V, VFB = 0.76V
VRNG = INTVCC, VFB = 0.76V
VRNG = 2V, VFB = 0.84V
VRNG = 0V, VFB = 0.84V
VRNG = INTVCC, VFB = 0.84V
VFB = 0.8V
TYP
0.75
1.2
150
UVIN Rising
UVIN Falling
Hysteresis
l
l
0.86
0.78
0.07
INTVCC Rising, INDRV = 100µA
INTVCC Rising, NDRV = INTVCC = EXTVCC
INTVCC Rising, NDRV = INTVCC, EXTVCC = 0
INTVCC Falling
l
l
l
4.05
4.05
8.70
4.2
4.2
9
3.7
4.35
4.35
9.30
V
V
V
V
1.55
515
1.85
605
250
2.15
695
100
350
µs
ns
ns
ns
3.6
1.2
5
1.8
µs
µs
ION = 100µA
ION = 300µA
ION = 2000µA
ION = 100µA, VPLL/LPF = 0.6V
ION = 100µA, VPLL/LPF = 1.8V
2.2
0.6
fPLLIN < fSW
fPLLIN > fSW
VBG = 0V
0.7
VTG – VSW = 0
0.7
15
–25
µA
µA
1
1
1
1
A
Ω
A
Ω
1.5
1.5
38105fd
3
LTC3810-5
electrical characteristics
The l denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 2), INTVCC = DRVCC = VBOOST = VON = VRNG = SHDN = UVIN =
VEXTVCC = VNDRV = 5V, VMODE/SYNC = VSENSE+ = VSENSE – = VBGRTN = VSW = 0V, unless otherwise specified.
SYMBOL
PGOOD Output
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DVFBOV
PGOOD Upper Threshold
PGOOD Lower Threshold
PGOOD Hysterisis
VFB Rising
VFB Falling
VFB Returning
7.5
–7.5
10
–10
1.5
12.5
–12.5
3
%
%
%
PGOOD Low Voltage
PGOOD Leakage Current
PGOOD Delay
IPGOOD = 5mA
VPGOOD = 5V
VFB Falling
0.3
0
120
0.6
2
V
µA
µs
SS/TRACK Source Current
Feedback Voltage at Tracking
VSS/TRACK > 0.5V
VTRACK = 0V, ITH = 1.2V (Note 4)
VTRACK = 0.5V, ITH = 1.2V (Note 4)
1.4
–0.018
0.5
2.5
0.52
µA
V
V
4.7
0.25
5.5
75
0.4
5.8
150
V
V
V
mV
DVFB,HYST
VPGOOD
IPGOOD
PG Delay
Tracking
ISS/TRACK
VFB,TRACK
VCC Regulators
VEXTVCC
VINTVCC,1
DVEXTVCC,1
DVLOADREG,1
VINTVCC,2
DVLOADREG,2
INDRV
INDRVTO
VCCSR
ICCSR
0.7
0.48
EXTVCC Switchover Voltage
EXTVCC Rising
EXTVCC Hysterisis
INTVCC Voltage from EXTVCC
VEXTVCC - VINTVCC at Dropout
6V < VEXTVCC < 15V
ICC = 20mA, VEXTVCC = 5V
INTVCC Load Regulation from EXTVCC
ICC = 0mA to 20mA, VEXTVCC = 10V
INTVCC Voltage from NDRV Regulator
INTVCC Load Regulation from NDRV
Linear Regulator in Operation
ICC = 0mA to 20mA, VEXTVCC = 0
5.2
5.5
0.01
5.8
V
%
Current into NDRV Pin
Linear Regulator Timeout Enable
Threshold
Maximum Supply Voltage
Maximum Current into NDRV/INTVCC
VNDRV – VINTVCC = 3V
20
210
40
270
60
350
µA
µA
4.45
0.1
5.2
l
0.01
Trickle Charger Shunt Regulator
Trickle Charger Shunt Regulator,
INTVCC ≤ 16.7V (Note 8)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3810-5 is tested under pulsed load conditions such that
TJ ≈ TA. The LTC3810E-5 is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 125°C operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls. The LTC3810I-5 is guaranteed
to meet performance specifications over the full –40°C to 125°C operating
junction temperature range. The LTC3810H-5 is guaranteed to meet
performance specifications over the full –40°C to 150°C operating junction
temperature range. High junction temperatures degrade operating lifetimes;
operating lifetime is derated for junction temperatures greater than 125°C.
Note 3: TJ is calculated from the ambient temperature TA and power
15
10
%
V
mA
dissipation PD according to the following formula:
LTC3810-5: TJ = TA + (PD • 34°C/W)
Note 4: The LTC3810-5 is tested in a feedback loop that servos VFB to the
reference voltage with the ITH pin forced to a voltage between 1V and 2V.
Note 5: The dynamic input supply current is higher due to the power
MOSFET gate charging being delivered at the switching frequency
(QG • fOSC).
Note 6: Guaranteed by design. Not subject to test.
Note 7: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 150°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 8: ICC is the sum of current into NDRV and INTVCC.
Similar Parts Comparison
PARAMETER
LTC3810
LTC3810-5
LTC3812-5
Maximum VIN
100V
60V
60V
6.35V to 14V
4.5V to 14V
4.5V to 14V
6.2V
4.2V
4.2V
6V
4V
4V
MOSFET Gate Drive
INTVCC UV+
INTVCC
UV–
38105fd
4
LTC3810-5
Typical Performance Characteristics
Load Transient Response
INTVCC
5V/DIV
VOUT
100mV/DIV
SS/TRACK
4V/DIV
VIN
50V/DIV
IL
5A/DIV
IL
5A/DIV
38105 G01
50µs/DIV
VIN = 48V
0A TO 5A LOADSTEP
FRONT PAGE CIRCUIT
38105 G02
500µs/DIV
VIN = 48V
ILOAD = 1A
MODE/SYNC = 0V
FRONT PAGE CIRCUIT
Short-Circuit/
Foldback Operation
Pulse Skip Mode Operation
VOUT
SS/TRACK 100mV/DIV
VOUT
5V/DIV
VFB
0.5V/DIV
SS/TRACK
0.5V/DIV
VFB
0.5V/DIV
IL
5A/DIV
IL
5A/DIV
38105 G04
200µs/DIV
VIN = 48V
FRONT PAGE CIRCUIT
Efficiency vs Input Voltage
ITH
0.5V/DIV
VFB
IL
2A/DIV
38105 G05
500µs/DIV
VIN = 48V
ILOAD = 1A
MODE/SYNC = 0V
FRONT PAGE CIRCUIT
Frequency vs Input Voltage
280
100
IOUT = 5A
95
IOUT = 0.5A
80
20
50
40
30
60
INPUT VOLTAGE (V)
70
80
38105 G07
VIN = 36V
VIN = 60V
270
90
85
80
VOUT = 5V
Si7850 MOSFETs
MODE/SYNC = INTVCC
f = 250kHz
75
VOUT = 12V
Si7852 MOSFETs
f = 250kHz
10
VIN = 12V
FREQUENCY (kHz)
EFFICIENCY (%)
90
70
38105 G06
20µs/DIV
VIN = 48V
IOUT = 100mA
MODE/SYNC = INTVCC
FRONT PAGE CIRCUIT
Efficiency vs Load Current
100
38105 G03
10ms/DIV
VIN = 48V
RSHORT = 0.1Ω
FRONT PAGE CIRCUIT
Tracking
VOUT
5V/DIV
EFFICIENCY (%)
VOUT
10V/DIV
INTVCC
VOUT
5V/DIV
IOUT
5A/DIV
70
Short-Circuit/
Fault Timeout Operation
Start-Up
0
1
2
3
4
5
LOAD CURRENT (A)
6
IOUT = 0A
260
IOUT = 5A
250
240
7
38105 G08
230
MODE/SYNC = 0V
FRONT PAGE CIRCUIT
10
20
50
30
60
40
INPUT VOLTAGE (V)
70
80
38105 G09
38105fd
5
LTC3810-5
Typical Performance Characteristics
400
300
300
FORCED
CONTINUOUS
250
200
PULSE SKIP
100
50
0
0
1
2
3
5
4
On-Time vs ION Current
VRNG = 2V
1V
0.7V
0.5V
100
0
–300
–400
0
0.5
1.0
2.0
1.5
ITH VOLTAGE (V)
2.5
600
660
ON-TIME (ns)
500
300
200
ION = 300µA
2.5
100
1000
ION CURRENT (µA)
640
620
600
560
–50 –25
3
ION = 300µA
0
25
50
75
100 125 150
TEMPERATURE (°C)
250
200
150
100
50
0
VRNG = INTVCC
0
0.4
0.2
0.6
38105 G14
38105 G15
Maximum Current Sense
Threshold vs Temperature
200
100
0
0.5
1
1.5
2
VRNG VOLTAGE (V)
Reference Voltage vs
Temperature
230
0.803
0.802
220
REFERENCE VOLTAGE (V)
MAXIMUM CURRENT SENSE THRESHOLD (mV)
MAXIMUM CURRENT SENSE THRESHOLD (mV)
Maximum Current Sense
Threshold vs VRNG Voltage
300
0.8
VFB (V)
38105 G13
400
10000
Current Limit Foldback
580
100
2
1.5
1
VON VOLTAGE (V)
10
38105 G12
On-Time vs Temperature
680
0.5
10
3.0
38105 G11
700
0
100
–200
On-Time vs VON Voltage
ON-TIME (ns)
1000
–100
38105 G10
400
VON = INTVCC
1.4V
200
LOAD CURRENT (A)
0
10000
MAXIMUM CURRENT SENSE THRESHOLD (mV)
150
Current Sense Threshold
vs ITH Voltage
ON-TIME (ns)
350
CURRENT SENSE THRESHOLD (mV)
FREQUENCY (kHz)
Frequency vs Load Current
210
200
190
180
–50 –25
0.801
0.800
0.799
0.798
VRNG = INTVCC
0
25 50 75 100 125 150
TEMPERATURE (°C)
38105 G17
0.797
–50 –25
0
25
50
75
100 125 150
TEMPERATURE (°C)
38105 G18
38105 G16
38105fd
6
LTC3810-5
Typical Performance Characteristics
Driver Peak Source Current
vs Temperature
1.75
VBOOST = VINTVCC = 5V
Driver Peak Source Current
vs Supply Voltage
3.0
VBOOST = VINTVCC = 5V
PEAK SOURCE CURRENT (A)
1.50
1.25
RDS(ON) (Ω)
PEAK SOURCE CURRENT (A)
1.5
Driver Pull-Down RDS(ON)
vs Temperature
1.0
1.00
0.75
0.50
0.5
–50 –25
0
0.25
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
0
25
50
75
TEMPERATURE (°C)
1.5
1.0
0.5
0
4
5
38105 G20
6 7 8 9 10 11 12 13 14
DRVCC/BOOST VOLTAGE (V)
38105 G21
EXTVCC LDO Resistance at
Dropout vs Temperature
Driver Pull-Down RDS(ON)
vs Supply Voltage
5
7
1.1
INTVCC Current vs Temperature
RESISTANCE (Ω)
0.9
0.8
INTVCC CURRENT (mA)
6
1.0
5
4
3
2
0.7
4
3
2
1
5
0
–50 –25
6 7 8 9 10 11 12 13 14
DRVCC/BOOST VOLTAGE (V)
0
25
50
75
100 125 150
TEMPERATURE (°C)
1
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
38105 G23
38105 G22
INTVCC Shutdown Current
vs Temperature
400
3.5
INTVCC = 5V
INTVCC Current vs INTVCC Voltage
3.0
300
INTVCC CURRENT (mA)
4
INTVCC CURRENT (µA)
RDS(ON) (Ω)
2.0
100 125 150
38105 G19
0.6
2.5
200
100
2.5
2.0
1.5
1.0
0.5
0
–50 –25
0
25
50
75
100 125 150
TEMPERATURE (°C)
38105 G25
0
0
2
8
6
10
4
INTVCC VOLTAGE (V)
12
14
38105 G26
38105fd
7
LTC3810-5
Typical Performance Characteristics
INTVCC Shutdown Current
vs INTVCC Voltage
SS/TRACK Pull-Up Current
vs Temperature
3
300
SS/TRACK CURRENT (µA)
INTVCC CURRENT (µA)
250
200
150
100
2
1
50
0
0
2
8
6
10
4
INTVCC VOLTAGE (V)
12
0
–50 –25
14
0
25
50
75
100 125 150
TEMPERATURE (°C)
38105 G28
38105 G27
ITH Voltage
vs Load Current
Shutdown Threshold
vs Temperature
2.2
3.0
2.0
SHUTDOWN THRESHOLD (V)
ITH VOLTAGE (V)
2.5
2.0
1.5
1.0
0.5
0
1
4
3
5
2
LOAD CURRENT (A)
6
1.6
1.4
1.2
1.0
0.8
VRNG = 1V
FRONT PAGE CIRCUIT
0
1.8
7
0.6
–50 –25
0
25
50
75
100 125 150
TEMPERATURE (°C)
38105 G29
38105 G30
38105fd
8
LTC3810-5
Pin Functions
VON (Pin 2): On-Time Voltage Input. Voltage trip point
for the on-time comparator. Tying this pin to the output
voltage or to an external resistive divider from the output
makes the on-time proportional to VOUT. The comparator
defaults to 0.7V when the pin is grounded and defaults to
2.4V when the pin is connected to INTVCC. Tie this pin to
INTVCC in high VOUT applications to use a lower RON value.
VRNG (Pin 3): Sense Voltage Limit Set. The voltage at this
pin sets the nominal sense voltage at maximum output
current and can be set from 0.5V to 2V by a resistive divider from INTVCC. The nominal sense voltage defaults to
95mV when this pin is tied to ground, and 215mV when
tied to INTVCC.
PGOOD (Pin 4): Power Good Output. Open-drain logic
output that is pulled to ground when the output voltage
is not between ±10% of the regulation point. The output
voltage must be out of regulation for at least 120µs before
the power good output is pulled to ground.
MODE/SYNC (Pin 5): Pulse Skip Mode Enable/Sync Pin.
This multifunction pin provides pulse skip mode enable/
disable control and an external clock input to the phase
detector. Pulling this pin below 0.8V or to an external
logic-level synchronization signal disables pulse skip mode
operation and forces continuous operation. Pulling this
pin above 0.8V enables pulse skip mode operation. For a
clock input, the phase-locked loop will force the rising top
gate signal to be synchronized with the rising edge of the
clock signal.This pin can also be connected to a feedback
resistor divider from a secondary winding on the inductor
to regulate a second output voltage.
ITH (Pin 6): Error Amplifier Compensation Point and Current Control Threshold. The current comparator threshold
increases with this control voltage. The voltage ranges
from 0V to 2.6V with 1.2V corresponding to zero sense
voltage (zero current).
VFB (Pin 7): Feedback Input. Connect VFB through a resistor
divider network to VOUT to set the output voltage.
PLL/LPF (Pin 8): The phase-locked loop’s lowpass filter
is tied to this pin. The voltage at this pin defaults to 1.2V
when the IC is not synchronized with an external clock at
the MODE/SYNC pin.
SS/TRACK (Pin 9): Soft-Start/Tracking Input. For soft-start,
a capacitor to ground at this pin sets the ramp rate of the
output voltage (approximately 0.6s/µF). For coincident or
ratiometric tracking, connect this pin to a resistive divider
between the voltage to be tracked and ground.
SHDN (Pin 12): Shutdown Pin. Pulling this pin below
1.5V will shut down the LTC3810-5, turn off both of the
external MOSFET switches and reduce the quiescent supply current to 240µA.
UVIN (Pin 13): UVLO Input. This pin is input to the internal
UVLO and is compared to an internal 0.8V reference. An
external resistor divider is connected to this pin and the
input supply to program the undervoltage lockout voltage.
When UVIN is less than 0.8V, the LTC3810-5 is shut down.
NDRV (Pin 14): Drive Output for External Pass Device of
the Linear Regulator for INTVCC. Connect to the gate of
an external NMOS pass device and a pull-up resistor to
the input voltage VIN.
EXTVCC (Pin 15): External Driver Supply Voltage. When
this voltage exceeds 4.7V, an internal switch connects this
pin to INTVCC through an LDO and turns off the exter nal
MOSFET connected to NDRV, so that controller and gate
drive are drawn from EXTVCC.
INTVCC (Pin 16): Main Supply Pin. All internal circuits except the output drivers are powered from this pin. INTVCC
should be bypassed to ground (Pin 10) with at least a 0.1µF
capacitor in close proximity to the LTC3810-5.
DRVCC (Pin 17): Driver Supply Pin. DRVCC supplies power
to the BG output driver. This pin is normally connected to
INTVCC. DRVCC should be bypassed to BGRTN (Pin 20)
with a low ESR (X5R or better) 1µF-10µF capacitor in close
proximity to the LTC3810-5.
38105fd
9
LTC3810-5
pin functions
BG (Pin 18): Bottom Gate Drive. The BG pin drives the
gate of the bottom N-channel synchronous switch MOSFET.
This pin swings from BGRTN to DRVCC.
BGRTN (Pin 19): Bottom Gate Return. This pin connects to
the source of the pulldown MOSFET in the BG driver and
is normally connected to ground. Connecting a negative
supply to this pin allows the synchronous MOSFET ’s gate
to be pulled below ground to help prevent false turn-on
during high dV/dt transitions on the SW node. See the
Applications Information section for more details.
SENSE+, SENSE– (Pin 24, Pin 20): Current Sense Comparator Input. The (+) input to the current comparator is
normally connected to SW unless using a sense resistor.
The (–) input is used to accurately kelvin sense the bottom
side of the sense resistor or MOSFET.
SW (Pin 25): Switch Node Connection to Inductor and
Bootstrap Capacitor. The voltage swing at this pin is –0.7V
(a Schottky diode (external) voltage drop) to VIN.
TG (Pin 26): Top Gate Drive. The TG pin drives the gate of
the top N-channel synchronous switch MOSFET. The TG
driver draws power from the BOOST pin and returns to the
SW pin, providing true floating drive to the top MOSFET.
BOOST (Pin 27): Top Gate Driver Supply. The BOOST pin
supplies power to the floating TG driver. BOOST should
be bypassed to SW with a low ESR (X5R or better) 0.1µF
capacitor. An additional fast recovery Schottky diode from
DRVCC to the BOOST pin will create a complete floating
charge-pumped supply at BOOST.
ION (Pin 31): On-Time Current Input. Tie a resistor from VIN
to this pin to set the one-shot timer current and thereby
set the switching frequency.
SGND (Exposed Pad Pin 33): Signal Ground. All smallsignal components should connect to this ground and
eventually connect to PGND at one point.
38105fd
10
LTC3810-5
Functional Diagram
EXTVCC NDRV INTVCC
INTVCC
0.8V
REF
5V
REG
VIN
INTVCC
MODE
LOGIC
5.5V
+
NDRV
–
9V
RUV1 UVIN
+
–
13
4.2V
OFF
INTVCC
INTVCC
UV
VIN UV
RUV2
+
16
–
EXTVCC
15
+
0.8V
MODE/SYNC
–
5
+
F
270µA
–
+
+
VON
2
ION
tON =
31
VVON
(76pF)
IION
DRV OFF
R
S
4.7V
CIN
27
TG
FCNT
+
CB
M1
26
SW
SENSE+
SWITCH
LOGIC
IREV
L1
24
VOUT
DRVCC
–
–
17
SHDN
BG
OV
×
CVCC
18
M2
BGRTN
+
19
COUT
SENSE–
1.4V
20
OVERTEMP
SENSE
VRNG
PGOOD
ITH’
FOLDBACK
4
RFB1
FB
0.7V
+
ITH
0.72V
UV
6
2.6V
–
4V
VFB
7
RC
CC1
EA
+
FAULT
RUN
SHDN –
– + +
CC2
+
BOOST
25
ICMP
3
VIN
DB
ON
Q
20k
+
–
TIMEOUT
LOGIC
100nA
RON
5.5V
ON
1.4µA
PLL-SYNC
8
+
–
PLL/LPF
VIN
M3
14
VIN
+
RFB2
OV
–
0.88V
SGND
12
1.5V
0.8V
SS/TRACK
9
SHDN
12
38105 FD
38105fd
11
LTC3810-5
Operation
Main Control Loop
The LTC3810-5 is a current mode controller for DC/
DC step-down converters. In normal operation, the top
MOSFET is turned on for a fixed interval determined by
a one-shot timer (OST). When the top MOSFET is turned
off, the bottom MOSFET is turned on until the current
comparator ICMP trips, restarting the one-shot timer and
initiating the next cycle. Inductor current is determined
by sensing the voltage between the SENSE– and SENSE+
pins using a sense resistor or the bottom MOSFET onresistance. The voltage on the ITH pin sets the comparator
threshold corresponding to the inductor valley current.
The fast 25MHz error amplifier EA adjusts this voltage by
comparing the feedback signal VFB to the internal 0.8V
reference voltage. If the load current increases, it causes a
drop in the feedback voltage relative to the reference. The
ITH voltage then rises until the average inductor current
again matches the load current.
The operating frequency is determined implicitly by the top
MOSFET on-time and the duty cycle required to maintain
regulation. The one-shot timer generates an on time that is
proportional to the ideal duty cycle, thus holding frequency
approximately constant with changes in VIN. The nominal
frequency can be adjusted with an external resistor RON.
For applications with stringent constant frequency requirements, the LTC3810-5 can be synchronized with an
external clock. By programming the nominal frequency
the same as the external clock frequency, the LTC3810-5
PULSE SKIP MODE
behaves as a constant frequency part against the load and
supply variations.
Pulling the SHDN pin low forces the controller into its
shutdown state, turning off both M1 and M2. Forcing a
voltage above 1.5V will turn on the device.
Pulse Skip Mode
The LTC3810-5 can operate in one of two modes selectable
with the MODE/SYNC pin—pulse skip mode or forced continuous mode (see Figure 1). Pulse skip mode is selected
when increased efficiency at light loads is desired (see
Figure 2). In this mode, the bottom MOSFET is turned off
when inductor current reverses to minimize efficiency loss
due to reverse current flow and gate charge switching.
At low load currents, ITH will drop below the zero current
level (1.2V) shutting off both switches. Both switches will
remain off with the output capacitor supplying the load
current until the ITH voltage rises above the zero current
level to initiate another cycle. In this mode, frequency is
proportional to load current at light loads.
Pulse skip mode operation is disabled by comparator F
when the MODE/SYNC pin is brought below 0.8V, forcing
continuous synchronous operation. Forced continuous
mode is less efficient due to resistive losses, but has the
advantage of better transient response at low currents,
approximately constant frequency operation, and the ability
to maintain regulation when sinking current.
FORCED CONTINUOUS
100
90
PULSE
SKIP
80
0A
EFFICIENCY (%)
0A
DECREASING
LOAD
CURRENT
0A
0A
70
FORCED
CONTINUOUS
60
50
40
30
20
VIN = 12V
VIN = 42V
10
0A
0
0.01
0A
38105 F01
Figure 1. Comparison of Inductor Current Waveforms for Pulse Skip Mode
and Forced Continuous Operation
0.1
1
10
LOAD (A)
38105 F02
Figure 2. Efficiency in Pulse Skip/
Forced Continuous Modes
38105fd
12
LTC3810-5
OPERATION
Fault Monitoring/Protection
Constant on-time current mode architecture provides accurate cycle-by-cycle current limit protection—a feature
that is very important for protecting the high voltage power
supply from output short circuits. The cycle-by-cycle current monitor guarantees that the inductor current will never
exceed the value programmed on the VRNG pin.
Foldback current limiting provides further protection if the
output is shorted to ground. As VFB drops, the buffered
current threshold voltage ITHB is pulled down and clamped
to 1V. This reduces the inductor valley current level to
one-sixth of its maximum value as VFB approaches 0V.
Foldback current limiting is disabled at start-up.
Overvoltage and undervoltage comparators OV and UV
pull the PGOOD output low if the output feedback voltage
exits a ±10% window around the regulation point after the
internal 120µs power bad mask timer expires. Furthermore,
in an overvoltage condition, M1 is turned off and M2 is
turned on immediately and held on until the overvoltage
condition clears.
The LTC3810-5 provides two undervoltage lockout comparators—one for the INTVCC/DRVCC supply and one for
the input supply VIN. The INTVCC UV threshold is 4.2V to
guarantee that the MOSFETs have sufficient gate drive
voltage before turning on. The VIN UV threshold (UVIN pin)
is 0.8V with 10% hysteresis which allows programming
the VIN threshold with the appropriate resistor divider
connected to VIN. If either comparator inputs are under
the UV threshold, the LTC3810-5 is shut down and the
drivers are turned off.
skip mode operation, where it is possible that the bottom
MOSFET will be off for an extended period of time, an
internal timeout guarantees that the bottom MOSFET is
turned on at least once every 25µs for one on-time period
to refresh the bootstrap capacitor.
The bottom driver has an additional feature that helps
minimize the possibility of external MOSFET shoot-through.
When the top MOSFET turns on, the switch node dV/dt
pulls up the bottom MOSFET’s internal gate through the
Miller capacitance, even when the bottom driver is holding
the gate terminal at ground. If the gate is pulled up high
enough, shoot-through between the top side and bottom
side MOSFETs can occur. To prevent this from occurring,
the bottom driver return is brought out as a separate pin
(BGRTN) so that a negative supply can be used to reduce
the effect of the Miller pull-up. For example, if a –2V supply is used on BGRTN, the switch node dV/dt could pull
the gate up 2V before the VGS of the bottom MOSFET has
more than 0V across it.
VIN
DRVCC
LTC3810-5
DRVCC
BOOST
TG
+
DB
CB
M1
L
SW
BG
CIN
M2
VOUT
+
BGRTN
COUT
38105 F03
0V TO –5V
Figure 3. Floating TG Driver Supply and Negative BG Return
Strong Gate Drivers
IC/Driver Supply Power
The LTC3810-5 contains very low impedance drivers capable of supplying amps of current to slew large MOSFET
gates quickly. This minimizes transition losses and allows
paralleling MOSFETs for higher current applications. A
60V floating high side driver drives the top side MOSFET
and a low side driver drives the bottom side MOSFET
(see Figure 3). The bottom side driver is supplied directly
from the DRVCC pin. The top MOSFET drivers are biased
from floating bootstrap capacitor, CB, which normally is
recharged during each off cycle through an external diode
from DRVCC when the top MOSFET turns off. In pulse
The LTC3810-5’s internal control circuitry and top and
bottom MOSFET drivers operate from a supply voltage
(INTVCC, DRVCC pins) in the range of 4.5V to 14V. The
LTC3810-5 has two integrated linear regulator controllers
to easily generate this IC/driver supply from either the high
voltage input or from the output voltage. For best efficiency
the supply is derived from the input voltage during start-up
and then derived from the lower voltage output as soon
as the output is higher than 4.7V. Alternatively, the supply
can be derived from the input continuously if the output is
38105fd
13
LTC3810-5
Operation
270µA
I < 270µA
NDRV
NDRV
INTVCC
+
5.5V
LTC3810-5
INTVCC
+
5.5V
LTC3810-5
VOUT (> 4.7V)
EXTVCC
Mode 3: Trickle Charge Mode
VIN
EXTVCC
Mode 4: External Supply
NDRV
INTVCC
LTC3810-5
EXTVCC
NDRV
+
VOUT
5.5V
INTVCC
LTC3810-5
+
+
–
4.5V to
14V
EXTVCC
38105 F04
Figure 4. Operating Modes for IC/Driver Supply
14
38105fd
LTC3810-5
Applications Information
Maximum Sense Voltage and VRNG Pin
Inductor current is determined by measuring the voltage across a sense resistance that appears between the
SENSE– and SENSE+ pins. The maximum sense voltage
is set by the voltage applied to the VRNG pin and is equal
to approximately:
VSENSE(MAX) = 0.173VRNG – 0.026
The current mode control loop will not allow the inductor
current valleys to exceed VSENSE(MAX)/RSENSE. In practice, one should allow some margin for variations in the
LTC3810-5 and external component values and a good
guide for selecting the sense resistance is:
RSENSE =
VSENSE(MAX)
1.3 •IOUT(MAX)
An external resistive divider from INTVCC can be used
to set the voltage of the VRNG pin between 0.5V and 2V
resulting in nominal sense voltages of 60mV to 320mV.
Additionally, the VRNG pin can be tied to SGND or INTVCC
in which case the nominal sense voltage defaults to 95mV
or 215mV, respectively.
Connecting the SENSE+ and SENSE– Pins
The LTC3810-5 can be used with or without a sense resistor. When using a sense resistor, place it between the
source of the bottom MOSFET, M2 and PGND. Connect
the SENSE+ and SENSE– pins to the top and bottom of
the sense resistor. Using a sense resistor provides a well
defined current limit, but adds cost and reduces efficiency.
Alternatively, one can eliminate the sense resistor and use
the bottom MOSFET as the current sense element by simply
connecting the SENSE+ pin to the lower MOSFET drain
and SENSE – pin to the MOSFET source. This improves
efficiency, but one must carefully choose the MOSFET
on-resistance, as discussed below.
Power MOSFET Selection
The LTC3810-5 requires two external N-channel power
MOSFETs, one for the top (main) switch and one for the
bottom (synchronous) switch. Important parameters for
the power MOSFETs are the breakdown voltage BVDSS,
threshold voltage V(GS)TH, on-resistance RDS(ON), input
capacitance and maximum current IDS(MAX).
When the bottom MOSFET is used as the current sense
element, particular attention must be paid to its onresistance. MOSFET on-resistance is typically specified
with a maximum value RDS(ON)(MAX) at 25°C. In this case,
additional margin is required to accommodate the rise in
MOSFET on-resistance with temperature:
RDS(ON)(MAX) =
RSENSE
ρT
The ρT term is a normalization factor (unity at 25°C)
accounting for the significant variation in on-resistance
with temperature (see Figure 5) and typically varies
from 0.4%/°C to 1.0%/°C depending on the particular
MOSFET used.
2.0
ρT NORMALIZED ON-RESISTANCE
The basic LTC3810-5 application circuit is shown on the
first page of this data sheet. External component selection
is primarily determined by the maximum input voltage and
load current and begins with the selection of the sense
resistance and power MOSFET switches. The LTC3810-5
uses either a sense resistor or the on-resistance of the
synchronous power MOSFET for determining the inductor
current. The desired amount of ripple current and operating
frequency largely determines the inductor value. Next, CIN is
selected for its ability to handle the large RMS current into
the converter and COUT is chosen with low enough ESR to
meet the output voltage ripple and transient specification.
Finally, loop compensation components are selected to
meet the required transient/phase margin specifications.
1.5
1.0
0.5
0
–50
50
100
0
JUNCTION TEMPERATURE (°C)
150
38105 F05
Figure 5. RDS(ON) vs Temperature
38105fd
15
LTC3810-5
applications information
The most important parameter in high voltage applications
is breakdown voltage BVDSS. Both the top and bottom
MOSFETs will see full input voltage plus any additional
ringing on the switch node across its drain-to-source during its off-time and must be chosen with the appropriate
breakdown specification. The LTC3810-5 is designed to
be used with a 4.5V to 14V gate drive supply (DRVCC pin)
for driving logic-level MOSFETs (VGS(MIN) ≥ 4.5V).
For maximum efficiency, on-resistance RDS(ON) and input
capacitance should be minimized. Low RDS(ON) minimizes
conduction losses and low input capacitance minimizes
transition losses. MOSFET input capacitance is a combination of several components but can be taken from the
typical “gate charge” curve included on most data sheets
(Figure 6).
VIN
VGS
MILLER EFFECT
a
V
b
QIN
CMILLER = (QB – QA)/VDS
+
VGS
–
+V
DS
–
38105 F06
Figure 6. Gate Charge Characteristic
The curve is generated by forcing a constant input current into the gate of a common source, current source
loaded stage and then plotting the gate voltage versus
time. The initial slope is the effect of the gate-to-source
and the gate-to-drain capacitance. The flat portion of the
curve is the result of the Miller multiplication effect of the
drain-to-gate capacitance as the drain drops the voltage
across the current source load. The upper sloping line is
due to the drain-to-gate accumulation capacitance and
the gate-to-source capacitance. The Miller charge (the
increase in coulombs on the horizontal axis from a to b
while the curve is flat) is specified for a given VDS drain
voltage, but can be adjusted for different VDS voltages by
multiplying by the ratio of the application VDS to the curve
specified VDS values. A way to estimate the CMILLER term
is to take the change in gate charge from points a and b
on a manufacturers data sheet and divide by the stated
VDS voltage specified. CMILLER is the most important selection criteria for determining the transition loss term in
the top MOSFET but is not directly specified on MOSFET
data sheets. CRSS and COS are specified sometimes but
definitions of these parameters are not included.
When the controller is operating in continuous mode the
duty cycles for the top and bottom MOSFETs are given by:
Main Switch Duty Cycle =
VOUT
VIN
Synchronous Switch Duty Cycle =
VIN – VOUT
VIN
The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
VOUT
2
IMAX ) (ρT )RDS(ON) +
(
VIN
I
VIN2 MAX (RDR )(CMILLER ) •
2
⎡
1 ⎤
1
+
⎢
⎥ (f)
⎢⎣ VCC – VTH(IL) VTH(IL) ⎥⎦
V –V
PBOT = IN OUT (IMAX )2(ρT )RDS(0N)
VIN
PTOP =
where ρT is the temperature dependency of RDS(ON), RDR
is the effective top driver resistance (approximately 2Ω at
VGS = VMILLER), VIN is the drain potential and the change
in drain potential in the particular application. VTH(IL) is
the data sheet specified typical gate threshold voltage
specified in the power MOSFET data sheet at the specified
drain current. CMILLER is the calculated capacitance using
the gate charge curve from the MOSFET data sheet and
the technique described above.
Both MOSFETs have I2R losses while the topside N-channel
equation incudes an additional term for transition losses,
which peak at the highest input voltage. For high input
voltage low duty cycle applications that are typical for the
LTC3810-5, transition losses are the dominate loss term and
therefore using higher RDS(ON) device with lower CMILLER
usually provides the highest efficiency. The synchronous
MOSFET losses are greatest at high input voltage when
the top switch duty factor is low or during a short-circuit
when the synchronous switch is on close to 100% of
38105fd
16
LTC3810-5
Applications Information
the period. Since there is no transition loss term in the
synchronous MOSFET, optimal efficiency is obtained by
minimizing RDS(ON)—by using larger MOSFETs or paralleling multiple MOSFETs.
Multiple MOSFETs can be used in parallel to lower
RDS(ON) and meet the current and thermal requirements
if desired. The LTC3810-5 contains large low impedance
drivers capable of driving large gate capacitances without
significantly slowing transition times. In fact, when driving MOSFETs with very low gate charge, it is sometimes
helpful to slow down the drivers by adding small gate
resistors (10Ω or less) to reduce noise and EMI caused
by the fast transitions.
Operating Frequency
The choice of operating frequency is a tradeoff between
efficiency and component size. Low frequency operation
improves efficiency by reducing MOSFET switching losses
but requires larger inductance and/or capacitance in order
to maintain low output ripple voltage.
The operating frequency of LTC3810-5 applications is
determined implicitly by the one-shot timer that controls
the on-time, tON, of the top MOSFET switch. The on-time
is set by the current out of the ION pin and the voltage at
the VON pin according to:
VVON
(76pF)
IION
1000
f=
VOUT
[H ]
VVON • RON (76pF) Z
To hold frequency constant during output voltage changes,
tie the VON pin to VOUT or to a resistive divider from VOUT
when VOUT > 2.4V. The VON pin has internal clamps that
limit its input to the one-shot timer. If the pin is tied below
0.7V, the input to the one-shot is clamped at 0.7V. Similarly,
if the pin is tied above 2.4V, the input is clamped at 2.4V.
In high VOUT applications, tie VON to INTVCC. Figures 7a
and 7b show how RON relates to switching frequency for
several common output voltages.
Changes in the load current magnitude will cause frequency shift. Parasitic resistance in the MOSFET switches
and inductor reduce the effective voltage across the
inductance, resulting in increased duty cycle as the load
current increases. By lengthening the on-time slightly as
current increases, constant frequency operation can be
maintained. This is accomplished with a resistive divider
from the ITH pin to the VON pin and VOUT. The values
required will depend on the parasitic resistances in the
specific application. A good starting point is to feed about
25% of the voltage change at the ITH pin to the VON pin
as shown in Figure 8. Place capacitance on the VON pin
to filter out the ITH variations at the switching frequency.
1000
VOUT = 3.3V
VOUT = 1.5V
100
10
100
RON (kΩ)
VOUT = 2.5V
1000
38105 F07a
Figure 7a. Switching Frequency vs RON (VON = 0V)
SWITCHING FREQUENCY (kHz)
VOUT = 5V
SWITCHING FREQUENCY (kHz)
tON =
Tying a resistor RON from VIN to the ION pin yields an
on-time inversely proportional to VIN. For a step-down
converter, this results in approximately constant frequency
operation as the input supply varies:
VOUT = 12V
VOUT = 5V
VOUT = 3.3V
100
10
100
RON (kΩ)
1000
38105 F07b
Figure 7b. Switching Frequency vs RON (VON = INTVCC)
38105fd
17
LTC3810-5
applications information
Inductor Selection
INTVCC
5.5V
RVON1
100k
RVON2
30k
VON
CVON
0.01µF
100k LTC3810-5
Given the desired input and output voltages, the inductor value and operating frequency determine the ripple
current:
ITH
38105 F08
Figure 8. Correcting Frequency Shift with Load Current Changes
Minimum Off-Time and Dropout Operation
The minimum off-time tOFF(MIN) is the smallest amount of
time that the LTC3810-5 is capable of turning on the bottom MOSFET, tripping the current comparator and turning
the MOSFET back off. This time is generally about 250ns.
The minimum off-time limit imposes a maximum duty
cycle of tON/(tON + tOFF(MIN)). If the maximum duty cycle
is reached, due to a dropping input voltage for example,
then the output will drop out of regulation. The minimum
input voltage to avoid dropout is:
VIN(MIN) = VOUT
tON + tOFF(MIN)
SWITCHING FREQUENCY (MHz)
2.0
DROPOUT
REGION
1.0
A reasonable starting point is to choose a ripple current
that is about 40% of IOUT(MAX). The largest ripple current
occurs at the highest VIN. To guarantee that ripple current
does not exceed a specified maximum, the inductance
should be chosen according to:
⎛ V
⎞⎛
VOUT ⎞
OUT
L=⎜
⎟ ⎜ 1−
⎟
⎝ f ΔIL(MAX) ⎠ ⎝ VIN(MAX) ⎠
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy
or Kool Mµ® cores. A variety of inductors designed for
high current, low voltage applications are available from
manufacturers such as Sumida, Panasonic, Coiltronics,
Coilcraft and Toko.
Schottky Diode D1 Selection
0.5
0
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Highest efficiency operation is obtained at low
frequency with small ripple current. However, achieving
this requires a large inductor. There is a tradeoff between
component size, efficiency and operating frequency.
tON
A plot of maximum duty cycle vs frequency is shown in
Figure 9.
1.5
⎛V ⎞⎛ V ⎞
ΔIL = ⎜ OUT ⎟ ⎜ 1− OUT ⎟
VIN ⎠
⎝ f L ⎠⎝
0
0.25
0.50
0.75
DUTY CYCLE (VOUT/VIN)
1.0
38105 F09
Figure 9. Maximum Switching Frequency vs Duty Cycle
The Schottky diode D1 shown in the front page schematic
conducts during the dead time between the conduction
of the power MOSFET switches. It is intended to prevent
the body diode of the bottom MOSFET from turning on
and storing charge during the dead time, which can cause
a modest (about 1%) efficiency loss. The diode can be
rated for about one-half to one-fifth of the full load current
since it is on for only a fraction of the duty cycle. In order
for the diode to be effective, the inductance between it
38105fd
18
LTC3810-5
Applications Information
and the bottom MOSFET must be as small as possible,
mandating that these components be placed adjacently.
The diode can be omitted if the efficiency loss is tolerable.
by the aluminum capacitors alone, when used together,
the percentage of RMS current that will be supplied by the
aluminum capacitor is reduced to approximately:
Input Capacitor Selection
% IRMS,ALUM ≈
In continuous mode, the drain current of the top MOSFET
is approximately a square wave of duty cycle VOUT/VIN
which must be supplied by the input capacitor. To prevent
large input transients, a low ESR input capacitor sized for
the maximum RMS current is given by:
⎛ V
⎞
V
ICIN(RMS) ≅IO(MAX) OUT ⎜ IN – 1⎟
VIN ⎝ VOUT ⎠
1/2
This formula has a maximum at VIN = 2VOUT, where IRMS =
IO(MAX)/2. This simple worst-case condition is commonly
used for design because even significant deviations do not
offer much relief. Note that the ripple current ratings from
capacitor manufacturers are often based on only 2000
hours of life. This makes it advisable to further derate
the capacitor or to choose a capacitor rated at a higher
temperature than required. Several capacitors may also
be placed in parallel to meet size or height requirements
in the design.
Because tantalum and OS-CON capacitors are not available
in voltages above 30V, ceramics or aluminum electrolytics
must be used for regulators with input supplies above 30V.
Ceramic capacitors have the advantage of very low ESR
and can handle high RMS current, but ceramics with high
voltage ratings (> 50V) are not available with more than
a few microfarads of capacitance. Furthermore, ceramics have high voltage coefficients which means that the
capacitance values decrease even more when used at the
rated voltage. X5R and X7R type ceramics are recommended for their lower voltage and temperature coefficients. Another consideration when using ceramics is
their high Q which, if not properly damped, may result in
excessive voltage stress on the power MOSFETs. Aluminum electrolytics have much higher bulk capacitance,
but they have higher ESR and lower RMS current ratings.
A good approach is to use a combination of aluminum
electrolytics for bulk capacitance and ceramics for low ESR
and RMS current. If the RMS current cannot be handled
1
1+ (8fCR ESR )2
• 100%
where RESR is the ESR of the aluminum capacitor and C
is the overall capacitance of the ceramic capacitors. Using
an aluminum electrolytic with a ceramic also helps damp
the high Q of the ceramic, minimizing ringing.
Output Capacitor Selection
The selection of COUT is primarily determined by the ESR
required to minimize voltage ripple. The output ripple
(DVOUT) is approximately equal to:
⎛
1 ⎞
ΔVOUT ≤ ΔIL ⎜ ESR +
8fCOUT ⎟⎠
⎝
Since DIL increases with input voltage, the output ripple
is highest at maximum input voltage. ESR also has a significant effect on the load transient response. Fast load
transitions at the output will appear as voltage across the
ESR of COUT until the feedback loop in the LTC3810-5 can
change the inductor current to match the new load current
value. Typically, once the ESR requirement is satisfied the
capacitance is adequate for filtering and has the required
RMS current rating.
Manufacturers such as Nichicon, Nippon Chemi-Con
and Sanyo should be considered for high performance
throughhole capacitors. The OS-CON (organic semiconductor dielectric) capacitor available from Sanyo has the
lowest product of ESR and size of any aluminum electrolytic at a somewhat higher price. An additional ceramic
capacitor in parallel with OS-CON capacitors is recommended to reduce the effect of their lead inductance.
In surface mount applications, multiple capacitors placed
in parallel may be required to meet the ESR, RMS current
handling and load step requirements. Dry tantalum, special
polymer and aluminum electrolytic capacitors are available
in surface mount packages. Special polymer capacitors
offer very low ESR but have lower capacitance density
38105fd
19
LTC3810-5
applications information
than other types. Tantalum capacitors have the highest
capacitance density but it is important to only use types
that have been surge tested for use in switching power
supplies. Several excellent surge-tested choices are the
AVX, TPS and TPSV or the KEMET T510 series. Aluminum
electrolytic capacitors have significantly higher ESR, but
can be used in cost-driven applications providing that
consideration is given to ripple current ratings and long
term reliability. Other capacitor types include Panasonic
SP and Sanyo POSCAPs.
Output Voltage
The LTC3810-5 output voltage is set by a resistor divider
according to the following formula:
⎛ R ⎞
VOUT = 0.8V ⎜ 1+ FB1 ⎟
⎝ RFB2 ⎠
The external resistor divider is connected to the output as
shown in the Functional Diagram, allowing remote voltage
sensing. The resultant feedback signal is compared with
the internal precision 800mV voltage reference by the
error amplifier. The internal reference has a guaranteed
tolerance of less than ±1%. Tolerance of the feedback
resistors will add additional error to the output voltage.
0.1% to 1% resistors are recommended.
Input Voltage Undervoltage Lockout
A resistor divider connected from the input supply to the
UVIN pin (see Functional Diagram) is used to program the
input supply undervoltage lockout thresholds. When the
rising voltage at UVIN reaches 0.88V the LTC3810 turns
on, and when the falling voltage at UVIN drops below 0.8V,
the LTC3810 is shut down—providing 10% hysterisis.
The input voltage UVLO thresholds are set by the resistor
divider according to the following formulas:
VIN,FALLING = 0.8V (1 + RUV1/RUV2)
Top MOSFET Driver Supply (CB, DB)
An external bootstrap capacitor, CB, connected to the
BOOST pin supplies the gate drive voltage for the topside
MOSFET. This capacitor is charged through diode DB from
DRVCC when the switch node is low. When the top MOSFET
turns on, the switch node rises to VIN and the BOOST pin
rises to approximately VIN + INTVCC. The boost capacitor
needs to store about 100 times the gate charge required
by the top MOSFET. In most applications 0.1µF to 0.47µF ,
X5R or X7R dielectric capacitor is adequate.
The reverse breakdown of the external diode, DB, must be
greater than VIN(MAX). Another important consideration for
the external diode is the reverse recovery and reverse leakage, either of which may cause excessive reverse current
to flow at full reverse voltage. If the reverse current times
reverse voltage exceeds the maximum allowable power
dissipation, the diode may be damaged. For best results,
use an ultrafast recovery diode such as the MMDL770T1.
Bottom MOSFET Driver Return Supply (BGRTN)
The bottom gate driver, BG, switches from DRVCC to
BGRTN where BGRTN can be a voltage between ground
and –5V. Why not just keep it simple and always connect
BGRTN to ground? In high voltage switching converters,
the switch node dV/dt can be many volts/ns, which will
pull up on the gate of the bottom MOSFET through its
Miller capacitance. If this Miller current, times the internal
gate resistance of the MOSFET plus the driver resistance,
exceeds the threshold of the FET, shoot-through will occur. By using a negative supply on BGRTN, the BG can be
pulled below ground when turning the bottom MOSFET off.
This provides a few extra volts of margin before the gate
reaches the turn-on threshold of the MOSFET. Be aware
that the maximum voltage difference between DRVCC and
BGRTN is 14V. If, for example, VBGRTN = –2V, the maximum
voltage on DRVCC pin is now 12V instead of 14V.
and
IC/MOSFET Driver Supplies (INTVCC and DRVCC)
VIN,RISING = 0.88V (1 + RUV1/RUV2)
The LTC3810-5 drivers are supplied from the DRVCC
and BOOST pins (see Figure 2), which have an absolute
maximum voltage of 14V. Since the main supply voltage,
If input supply undervoltage lockout is not needed, it can
be disabled by connecting UVIN to INTVCC.
38105fd
20
LTC3810-5
Applications Information
VIN is typically much higher than 14V a separate supply
for the IC power (INTVCC) and driver power (DRVCC) must
be used. The LTC3810-5 has integrated bias supply control circuitry that allows the IC/driver supply to be easily
generated from VIN and/or VOUT with minimal external
components. There are four ways to do this as shown in
the simplified schematics of Figure 3 and explained in the
following sections.
Using the Linear Regulator for INTVCC/DRVCC Supply
In Mode 1, a small external SOT23 MOSFET, controlled
by the NDRV pin, is used to generate a 5.5V start-up
supply from VIN. The small SOT23 package can be used
because the NMOS is on continuously only during the brief
start-up period. As soon as the output voltage reaches
4.7V, the LTC3810-5 turns off the external NMOS and the
LTC3810-5 regulates the 5.5V supply from the EXTVCC
pin (connected to VOUT or a VOUT derived boost network)
through an internal low dropout regulator. For this mode to
work properly, EXTVCC must be in the range 4.7V < EXTVCC
< 15V. If VOUT < 4.7V, a charge pump or extra winding can
be used to raise EXTVCC to the proper voltage, or alternatively, Mode 2 should be used as explained later in this
section. If VOUT is shorted or otherwise goes below the
minimum 4.5V threshold, the MOSFET connected to VIN
is turned back on to maintain the 5.5V supply. However if
the output cannot be brought up within a timeout period,
the drivers are turned off to prevent the SOT23 MOSFET
from overheating. Soft-start cycles are then attempted at
low duty cycle intervals to try to bring the output back up
(see Figure 10). This fault timeout operation is enabled
by choosing the choosing RNDRV such that the resistor
FAULT TIMEOUT
ENABLED
SS/TRACK
RNDRV ≤
where
PMOSFET(MAX) / ICC − VTH
270µA
(
)
I = (f) QG(TOP) + QG(BOTTOM) + 3mA
CC
and VTH is the threshold voltage of the MOSFET.
The value of RNDRV also affects the VIN(MIN) as follows:
VIN(MIN) = VINTVCC(MIN) + (40µA) RNDRV +VT (1)
where VINTVCC(MIN) is normally 4.5V for driving logic-level
MOSFETs. If minimum VIN is not low enough, consider
reducing RNDRV and/or using a Darlington NPN instead
of an NMOS to reduce VT to ~1.4V.
When using RNDRV equal to the computed value, the
LTC3810-5 will enable the low duty cycle soft-start retries only when the desired maximum power dissipation,
PMOSFET(MAX), in the MOSFET is exceeded and leave the
drivers on continuously otherwise. The shutoff/restart
times are a function of the TRACK/SS capacitor value.
The external NMOS for the linear regulator should be a
standard 3V threshold type (i.e., not a logic-level threshold).
The rate of charge of INTVCC from 0V to 5.5V is controlled
by the LTC3810-5 to be approximately 75µs regardless
of the size of the capacitor connected to the INTVCC pin.
The charging current for this capacitor is approximately:
⎛ 5.5V ⎞
IC = ⎜
C
⎝ 75µs ⎟⎠ INTVCC
DRIVER OFF THRESHOLD
DRIVER POWER
FROM VOUT
DRIVER POWER
FROM VIN
DRIVER POWER
FROM VIN
START-UP
VOUT
current INDRV is greater than 270µA by using the following formulas:
ISS/TRACK = 1.4µA (SOURCE)
ISS/TRACK = 0.1µA (SINK)
EXTVCC UV THRESHOLD
SHORT-CIRCUIT EVENT
START-UP INTO SHORT-CIRCUIT
TG/BG
38105 F10
Figure 10. Fault Timeout Operation
38105fd
21
LTC3810-5
applications information
The safe operating area (SOA) for the external NMOS
should be chosen so that capacitor charging does not
damage the NMOS. Excessive values of capacitor are
unnecessary and should be avoided. Typically values in
the 1µF to 10µF work well.
One more design requirement for this mode is the minimum
soft-start capacitor value. The fault timeout is enabled
when SS/TRACK voltage is greater than 4V. This gives the
power supply time to bring the output up before it starts
the timeout sequence. To prevent timeout sequence from
starting prematurely during start-up, a minimum CSS value
is necessary to ensure that VSS/TRACK < 4V until VEXTVCC
> 4.7V. To ensure this, choose:
CSS > COUT • (2.3 • 10–6)/IOUT(MAX)
Mode 2 should be used if VOUT is outside of the 4.7V <
EXTVCC < 15V operating range and the extra complexity
of a charge pump or extra inductor winding is not wanted
to boost this voltage above 4.7V. In this mode, EXTVCC is
grounded and the NMOS is chosen to handle the worstcase power dissipation:
PMOSFET = VIN(MAX) ⎡( f ) QG(TOP) + QG(BOTTOM) + 3mA ⎤
⎣
⎦
(
) (
)
by the driver current IG. In order to ensure proper startup, CINTVCC/CDRVCC must be chosen large enough so that
the EXTVCC voltage reaches the switchover threshold of
4.7V before CINTVCC/CDRVCC discharges below the falling
UV threshold of 4V. This is ensured if:
CINTVCC + CDRVCC >
⎛
COUT
5.5 • 105 • CSS ⎞
or
IG • ⎜ larger of
⎟
IMAX
VOUT(REG) ⎠
⎝
Where IG is the gate drive current = (f)(QG(TOP) +
QG(BOTTOM)) and IMAX is the maximum inductor current
selected by VRNG.
For RPULLUP, the value should fall in the following range
to ensure proper start-up:
Min RPULLUP > (VIN(MAX) – 14V)/ICCSR
Max RPULLUP < (VIN(MIN) – 9V)/IQ,SHUTDOWN
Using an External Supply Connected to the INTVCC/
DRVCC Pins
To operate properly, the fault timeout operation must be
disabled by choosing
If an external supply is available between 4.5V and 14V,
the supply can be connected directly to the INTVCC/DRVCC
pins. In this mode, INTVCC, EXTVCC and NDRV must be
shorted together.
RNDRV > (VIN(MAX) – 5.5V – VTH)/270µA
INTVCC/DRVCC Supply and the EXTVCC Connection
If the required RNDRV value results in an unacceptable value
for VIN(MIN) (see Equation 1), fault timeout operation can
also be disabled by connecting a 500k to 1Meg resistor
from SS/TRACK pin to INTVCC.
The LTC3810-5 contains an internal low dropout regulator
to produce the 5.5V INTVCC /DRVCC supply from the EXTVCC
pin voltage. This regulator turns on when the EXTVCC pin
is above 4.7V and remains on until EXTVCC drops below
4.45V. This allows the IC/MOSFET power to be derived
from the output or an output derived boost network during
normal operation and from the external NMOS from VIN
during start-up or short-circuit. Using the EXTVCC pin in
this way results in significant efficiency gains compared
to what would be possible when deriving this power
continuously from the typically much higher VIN voltage.
The EXTVCC connection also allows the power supply to
be configured in trickle charge mode in which it starts up
with a high valued “bleed” resistor connected from VIN
to INTVCC to charge up the INTVCC capacitor. As soon as
the output rises above 4.7V the internal EXTVCC regulator
Using Trickle Charge Mode
Trickle charge mode is selected by shorting NDRV and
INTVCC and connecting EXTVCC to VOUT. Trickle charge
mode has the advantage of not requiring an external
MOSFET but takes longer to start up due to slow charge
up of CINTVCC and CDRVCC through RPULLUP (tDELAY = 0.77
• RPULLUP • CDRVCC) and usually requires larger INTVCC/
DRVCC capacitor values to hold up the supply voltage during start-up. Once the INTVCC/DRVCC voltage reaches the
trickle charge UV threshold of 9V, the drivers will turn on
and start discharging CINTVCC/CDRVCC at a rate determined
38105fd
22
LTC3810-5
Applications Information
takes over before the INTVCC capacitor discharges below
the UV threshold. When the EXTVCC regulator is active,
the EXTVCC pin can supply up to 50mA RMS. Do not apply more than 15V to the EXTVCC pin. The following list
summarizes the possible connections for EXTVCC:
1. EXTVCC grounded. This connection will require INTVCC
to be powered continuously from an external NMOS
from VIN resulting in an efficiency penalty as high as
10% at high input voltages.
2. EXTVCC connected directly to VOUT. This is the normal
connection for 4.7V < VOUT < 15V and provides the
highest efficiency. The power supply will start up using
an external NMOS or a bleed resistor until the output
supply is available.
3. EXTVCC connected to an output-derived boost network.
If VOUT < 4.7V. The low voltage output can be boosted
using a charge pump or flyback winding to greater
than 4.7V.
4. EXTVCC connected to INTVCC. This is the required connection for EXTVCC if INTVCC is connected to an external
supply where the external supply is 4.5V < VEXT < 15V.
Applications using large MOSFETs with a high input
voltage and high frequency of operation may result in a
large EXTVCC pin current. Due to the LTC3810-5 thermally
enhanced package, maximum junction temperature will
rarely be exceeded, however, it is good design practice
to verify that the maximum junction temperature rating
and RMS current rating are within the maximum limits.
Typically, most of the EXTVCC current consists of the
MOSFET gates current. In continuous mode operation,
this EXTVCC current is:
(
)
IEXTVCC = f QG(TOP) + QG(BOTTOM) + 3mA < 50mA
The junction temperature can be estimated from the
equations given in Note 2 of the Electrical Characteristics
as follows:
TJ = TA + IEXTVCC • (VEXTVCC – VINTVCC)(34°C/W)
The calculated TJ should be IOUT(MAX). The minimum value of current
limit generally occurs with the largest VIN at the highest
ambient temperature, conditions that cause the largest
power loss in the converter. Note that it is important to
check for self-consistency between the assumed MOSFET
junction temperature and the resulting value of ILIMIT
which heats the MOSFET switches.
Caution should be used when setting the current limit based
upon the RDS(ON) of the MOSFETs. The maximum current
limit is determined by the minimum MOSFET on-resistance.
Data sheets typically specify nominal and maximum values
for RDS(ON), but not a minimum. A reasonable assumption
is that the minimum RDS(ON) lies the same percentage
below the typical value as the maximum lies above it.
Consult the MOSFET manufacturer for further guidelines.
To further limit current in the event of a short-circuit to
ground, the LTC3810-5 includes foldback current limiting.
If the output falls by more than 50%, then the maximum
sense voltage is progressively lowered to about one-tenth
of its full value.
Be aware also that when the fault timeout is enabled for
the external NMOS regulator, an over current limit may
cause the output to fall below the minimum 4.5V UV
threshold. This condition will cause a linear regulator timeout/restart sequence as described in the Linear Regulator
Timeout section if this condition persists.
Soft-Start and Tracking
The LTC3810-5 has the ability to either soft-start by itself
with a capacitor or track the output of another supply.
When the device is configured to soft-start by itself, a
capacitor should be connected to the TRACK/SS pin. The
LTC3810-5 is put in a low quiescent current shutdown
state (IQ ~240µA) if the SHDN pin voltage is below 1.5V.
The TRACK/SS pin is actively pulled to ground in this
shutdown state. Once the SHDN pin voltage is above
1.5V, the LTC3810-5 is powered up. A soft-start current
of 1.4µA then starts to charge the soft-start capacitor CSS.
Note that soft-start is achieved not by limiting the maximum output current of the controller but by controlling
the ramp rate of the output voltage. Current foldback is
disabled during this soft-start phase. During the soft-start
phase, the LTC3810‑5 is ramping the reference voltage
until it reaches 0.8V. The force continuous mode is also
38105fd
27
LTC3810-5
applications information
Output Voltage Tracking
To implement the coincident tracking in Figure 15a, connect an additional resistive divider to VOUT1 and connect its
midpoint to the TRACK/SS pin of the slave IC. The ratio of
this divider should be selected the same as that of the slave
IC’s feedback divider shown in Figure 16. In this tracking
mode, VOUT1 must be set higher than VOUT2. To implement
the ratiometric tracking, the ratio of the divider should be
exactly the same as the master IC’s feedback divider. Note
that the internal soft-start current will introduce a small
error on the tracking voltage depending on the absolute
values of the tracking resistive divider.
The LTC3810-5 allows the user to program how its output ramps up by means of the TRACK/SS pin. Through
this pin, the output can be set up to either coincidentally
or ratiometrically track with another supply’s output, as
shown in Figure 15. In the following discussions, VOUT1
refers to the master LTC3810-5’s output and VOUT2 refers
to the slave LTC3810-5’s output.
By selecting different resistors, the LTC3810-5 can achieve
different modes of tracking including the two in Figure 15.
So which mode should be programmed? While either
mode in Figure 15 satisfies most practical applications,
there do exist some tradeoffs. The ratiometric mode saves
a pair of resistors, but the coincident mode offers better
output regulation. This can be better understood with the
disabled and PGOOD signal is forced low during this phase.
The total soft-start time can be calculated as:
tSOFTSTART = 0.8 • CSS/1.4µA
When the device is configured to track another supply,
the feedback voltage of the other supply is duplicated
by a resistor divider and applied to the TRACK/SS pin.
Therefore, the voltage ramp rate on this pin is determined
by the ramp rate of the other supply output voltage.
VOUT1
OUTPUT VOLTAGE
OUTPUT VOLTAGE
VOUT1
VOUT2
VOUT2
38105 F15
TIME
TIME
(15a) Coincident Tracking
(15b) Ratiometric Tracking
Figure 15. Two Different Modes of Output Voltage Tracking
VOUT1
TO
TRACK/SS2
PIN
VOUT2
R3
R4
R1
R2
TO
VFB1
PIN
TO
VFB2
PIN
VOUT1
R3
R4
VOUT2
R1
TO
TRACK/SS2
PIN
TO
VFB1
PIN
R2
TO
VFB2
PIN
R3
R4
38105 F16
(16a) Coincident Tracking Setup
(16b) Ratiometric Tracking Setup
Figure 16. Setup for Coincident and Ratiometric Tracking
38105fd
28
LTC3810-5
Applications Information
I
I
+
TRACK/SS2
0.8V
VFB2
D1
D2
EA2
–
D3
38105 F17
Figure 17. Equivalent Input Circuit of Error Amplifier
help of Figure 17. At the input stage of the slave IC’s error
amplifier, two common anode diodes are used to clamp
the equivalent reference voltage and an additional diode
is used to match the shifted common mode voltage. The
top two current sources are of the same amplitude. In the
coincident mode, the TRACK/SS voltage is substantially
higher than 0.8V at steady state and effectively turns off
D1. D2 and D3 will therefore conduct the same current
and offer tight matching between VFB2 and the internal
precision 0.8V reference. In the ratiometric mode, however,
TRACK/SS equals 0.8V at steady state. D1 will divert part
of the bias current to make VFB2 slightly lower than 0.8V.
Although this error is minimized by the exponential I-V
characteristic of the diode, it does impose a finite amount
of output voltage deviation. Furthermore, when the master
IC’s output experiences dynamic excursion (under load
transient, for example), the slave IC output will be affected
as well. For better output regulation, use the coincident
tracking mode instead of ratiometric.
Phase-Locked Loop and Frequency Synchronization
The LTC3810-5 has a phase-locked loop comprised of an
internal voltage controlled oscillator and phase detector.
This allows the top MOSFET turn-on to be locked to the
rising edge of an external source. The frequency range
of the voltage controlled oscillator is ±30% around the
center frequency fO. The center frequency is the operating
frequency discussed in the Operating Frequency section.
The LTC3810-5 incorporates a pulse detection circuit that
will detect a clock on the MODE/SYNC pin. In turn, it will
turn on the phase-locked loop function. The pulse width of
the clock has to be greater than 400ns and the amplitude
of the clock should be greater than 2V.
The internal oscillator locks to the external clock after
the second clock transition is received. When external
synchronization is detected, LTC3810-5 will operate in
forced continuous mode. If an external clock transition
is not detected for three successive periods, the internal
oscillator will revert to the frequency programmed by the
RON resistor.
During the start-up phase, phase-locked loop function is
disabled. When LTC3810-5 is not in synchronization mode,
PLL/LPF pin voltage is set to around 1.215V. Frequency
synchronization is accomplished by changing the internal
on-time current according to the voltage on the PLL/LPF pin.
The phase detector used is an edge sensitive digital type
which provides zero degrees phase shift between the external and internal pulses. This type of phase detector will
not lock up on input frequencies close to the harmonics
of the VCO center frequency. The PLL hold-in range, DfH,
is equal to the capture range, DfC:
DfH = DfC = ±0.3 fO
The output of the phase detector is a complementary pair of
current sources charging or discharging the external filter
network on the PLL/LPF pin. A simplified block diagram
is shown in Figure 18.
RLP
2.4V
CLP
PLL/LPF
MODE/SYNC
DIGITAL
PHASE/
FREQUENCY
DETECTOR
VCO
38105 F18
Figure 18. Phase-Locked Loop Block Diagram
38105fd
29
LTC3810-5
applications information
If the external frequency (fMODE) is greater than the
oscillator frequency fO, current is sourced continuously,
pulling up the PLL/LPF pin. When the external frequency
is less than fO, current is sunk continuously, pulling down
the PLL/LPF pin. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. Thus the voltage on the PLL/LPF
pin is adjusted until the phase and frequency of the external
and internal oscillators are identical. At this stable operating
point the phase comparator output is open and the filter
capacitor CLP holds the voltage. The LTC3810-5 MODE/
SYNC pin must be driven from a low impedance source
such as a logic gate located close to the pin.
The loop filter components (CLP , RLP) smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components CLP and RLP determine how fast the loop
acquires lock. Typically RLP = 10kΩ and CLP is 0.01µF
to 0.1µF.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Although all dissipative
elements in the circuit produce losses, four main sources
account for most of the losses in LTC3810-5 circuits:
1. DC I2R losses. These arise from the resistances of the
MOSFETs, inductor and PC board traces and cause the
efficiency to drop at high output currents. In continuous
mode the average output current flows through L, but is
chopped between the top and bottom MOSFETs. If the
two MOSFETs have approximately the same RDS(ON),
then the resistance of one MOSFET can simply be
summed with the resistances of L and the board traces
to obtain the DC I2R loss. For example, if RDS(ON) =
0.01Ω and RL = 0.005Ω, the loss will range from 15mW
to 1.5W as the output current varies from 1A to 10A.
2. Transition loss. This loss arises from the brief amount
of time the top MOSFET spends in the saturated region
during switch node transitions. It depends upon the
input voltage, load current, driver strength and MOSFET
capacitance, among other factors. The loss is significant at input voltages above 20V and can be estimated
from the second term of the PMAIN equation found in
the Power MOSFET Selection section. When transition
losses are significant, efficiency can be improved by
lowering the frequency and/or using a top MOSFET(s)
with lower CRSS at the expense of higher RDS(ON).
3. INTVCC/DRVCC current. This is the sum of the MOSFET
driver and control currents. Control current is typically
about 3mA and driver current can be calculated by:
IGATE = f(QG(TOP) + QG(BOT)), where QG(TOP) and QG(BOT)
are the gate charges of the top and bottom MOSFETs.
This loss is proportional to the supply voltage that
INTVCC/DRVCC is derived from, i.e., VIN for the external
NMOS linear regulator, VOUT for the internal EXTVCC
regulator, or VEXT when an external supply is connected
to INTVCC/DRVCC.
4. CIN loss. The input capacitor has the difficult job of filtering the large RMS input current to the regulator. It
must have a very low ESR to minimize the AC I2R loss
and sufficient capacitance to prevent the RMS current
from causing additional upstream losses in fuses or
batteries.
Other losses, including COUT ESR loss, Schottky diode D1
conduction loss during dead time and inductor core loss
generally account for less than 2% additional loss. When
making adjustments to improve efficiency, the input current is the best indicator of changes in efficiency. If you
make a change and the input current decreases, then the
efficiency has increased. If there is no change in input
current, then there is no change in efficiency.
Checking Transient Response
The regulator loop response can be checked by looking at the load transient response. Switching regulators
take several cycles to respond to a step in load current.
38105fd
30
LTC3810-5
Applications Information
When load step occurs, VOUT immediately shifts by an
amount equal to DILOAD (ESR), where ESR is the effective
series resistance of COUT. DILOAD also begins to charge or
discharge COUT generating a feedback error signal used by
the regulator to return VOUT to its steady-state value. During
this recovery time, VOUT can be monitored for overshoot
or ringing that would indicate a stability problem.
VSNS = 320mV, assume a junction temperature of about
55°C above a 70°C ambient (ρ125°C = 1.7):
ILIMIT ≥
320mV
1
+ • 2.4A = 7.3A
1.7 • 0.031Ω 2
and double-check the assumed TJ in the MOSFET:
PBOT =
60V − 5V
• 7.3A 2 • 1.7 • 0.031Ω = 2.6W
60V
Design Example
As a design example, take a supply with the following
specifications: VIN = 12V to 60V, VOUT = 5V ±5%, IOUT(MAX)
= 6A, f = 250kHz. First, calculate the timing resistor:
TJ = 70°C + 2.6W • 22°C/W = 127°C
RON =
5V
= 110k
2.4V • 250kHz • 76pF
Verify that the Si7850DP is also a good choice for the
top MOSFET by checking its power dissipation at current
limit and maximum input voltage, assuming a junction
temperature of 30°C above a 70°C ambient (ρ100°C = 1.5):
and choose the inductor for about 40% ripple current at
the maximum VIN:
L=
5V
5V ⎞
⎛
1−
= 7.6µH
⎜
250kHz • 0.4 • 6A ⎝ 60V ⎟⎠
With a 7.7µH inductor, ripple current will vary from 1.5A
to 2.4A (25% to 40%) over the input supply range.
Next, choose the bottom MOSFET switch. Since the
drain of the MOSFET will see the full supply voltage 60V
(max) plus any ringing, choose an 60V MOSFET. The
Si7850DP has:
BVDSS = 60V
RDS(ON) = 31mΩ (max)/25mΩ (nom),
δ = 0.007/°C,
CMILLER = (8.3nC – 2.8nC)/30V = 183pF,
VGS(MILLER) = 3.8V,
θJA= 22°C/W.
This yields a nominal sense voltage of:
VSNS(NOM) = 6A • 1.3 • 0.025Ω = 195mV
To guarantee proper current limit at worst-case conditions,
increase nominal VSNS by at least 50% to 320mV (by tying
VRNG to 2V). To check if the current limit is acceptable at
5V
• 7.3A 2 (1.5 • 0.031Ω )
60V
7.3A
1
1 ⎞
⎛
+ 60V 2 •
• 2Ω • 183pF • ⎜
+
• 250kHz
⎝ 5V − 3.8V 3.8V ⎟⎠
2
= 0.206W + 1.32W = 1.53W
PMAIN =
TJ = 70°C + 1.53W • 22°C/W = 104°C
The junction temperature will be significantly less at nominal current, but this analysis shows that careful attention to
heat sinking on the board will be necessary in this circuit.
Since VOUT > 4.7V, the INTVCC voltage can be generated
from VOUT with the internal LDO by connecting VOUT to
the EXTVCC pin. A small SOT23 MOSFET such as the
ZXMN10A07F can be used for the pass device if fault
timeout is enabled. Choose RNDRV to guarantee that fault
timeout is enabled when power dissipation of M3 exceeds
0.4W (max for 70°C ambient):
ICC = 250kHz • 2 • 18nC + 3mA = 12mA
RNDRV ≤
0.4W / 0.012A – 3V
= 112k
270µA
So, choose RNDRV = 100k.
38105fd
31
LTC3810-5
applications information
CIN is chosen for an RMS current rating of about 3A at
85°C. The output capacitors are chosen for a low ESR
of 0.018Ω to minimize output voltage changes due to
inductor ripple current and load steps. The ripple voltage
will be only:
DVOUT(RIPPLE) = DIL(MAX) • ESR = 2.4A • 0.018W
= 43mV
However, a 0A to 6A load step will cause an output change
of up to:
DVOUT(STEP) = DILOAD • ESR = 6A • 0.018Ω
= 108mV
An optional 10µF ceramic output capacitor is included
to minimize the effect of ESL in the output ripple. The
complete circuit is shown in Figure 19.
CON
100pF
10k
2
78.7k
0.01µF
10k
CSS
1000pF
RUV1
200k
ION
LTC3810-5
27
BOOST
TG
VON
SW
3 V
RNG
4
PGOOD
5
MODE_SYNC
6
ITH
7
V
8 FB
PLL/LPF
PGOOD
250kHz
CLOCK
9
SENSE+
SENSE
RUV2
14.3k
CC2
47pF
RFB2
1.91k
RC
200k
26
• Place CIN, COUT, MOSFETs, D1 and inductor all in one
compact area. It may help to have some components
on the bottom side of the board.
• Use an immediate via to connect the components to
ground plane including SGND and PGND of LTC3810-5.
Use several bigger vias for power components.
SS/TRACK
M3
ZXMN10A07F
VIN
12V TO 60V
CIN1
68µF
100V
DB
BAS19
CIN2
1µF
100V
PGND
CB 0.1µF
M1
SiR880DP
25
24
L1
10µH
VOUT
5V
6A
19
18
BG
17
DRVCC
16
INTVCC
15
EXTVCC
14
NDRV
SGND
CC1
5pF
• The ground plane layer should not have any traces and
it should be as close as possible to the layer with power
MOSFETs.
– 20
BGRTN
33
SGND
12
SHDN
13
UVIN
SHDN
When laying out a PC board follow one of two suggested
approaches. The simple PC board layout requires a dedicated ground plane layer. Also, for higher currents, it is
recommended to use a multilayer board to help with heat
sinking power components.
RNDRV
100k
RON
110k
31
PC Board Layout Checklist
CDRVCC
0.1µF
COUT1
270µF
6.3V
M2
SiR880DP
D1
B1100
CVCC
1µF
COUT2
10µF
6.3V
C5
1µF
RFB1
10k
PGND
38105 F19
Figure 19. 12V to 60V Input Voltage to 5V/6A Synchronized at 250kHz
38105fd
32
LTC3810-5
Applications Information
• Use compact plane for switch node (SW) to improve
cooling of the MOSFETs and to keep EMI down.
• Place M2 as close to the controller as possible, keeping
the PGND, BG and SW traces short.
• Use planes for VIN and VOUT to maintain good voltage
filtering and to keep power losses low.
• Connect the input capacitor(s) CIN close to the power MOSFETs. This capacitor carries the MOSFET AC
current.
• Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
component. You can connect the copper areas to any
DC net (VIN, VOUT, GND or to any other DC rail in your
system).
When laying out a printed circuit board, without a ground
plane, use the following checklist to ensure proper operation of the controller.
• Segregate the signal and power grounds. All small
signal components should return to the SGND pin at
one point which is then tied to the PGND pin close to
the source of M2.
• Keep the high dV/dt SW, BOOST and TG nodes away
from sensitive small-signal nodes.
• Connect the INTVCC decoupling capacitor CVCC closely
to the INTVCC and SGND pins.
• Connect the top driver boost capacitor CB closely to
the BOOST and SW pins.
• Connect the bottom driver decoupling capacitor CDRVCC
closely to the DRVCC and BGRTN pins.
38105fd
33
LTC3810-5
Typical Applications
7V to 60V Input Voltage to 5V/5A with IC Power from 12V Supply
and All Ceramic Output Capacitors
12V
RON
110k
CON
100pF
31
ION
TG
2
VON
3
VRNG
4
PGOOD
5
MODE_SYNC
6
ITH
7
VFB
8
PLL/LPF
PGOOD
RUV1
470k
CSS
1000pF
9
SS/TRACK
33
SGND
12
SHDN
13
UVIN
SHDN
RUV2
61.9k
CC2
47pF
RFB2
1.91k
RC
100k
SGND
CC1
5pF
SW
CIN1
68µF
100V
CIN2
1µF
100V
DB
BAS19
LTC3810-5
27
BOOST
26
VIN
7V TO 60V
PGND
CB 0.1µF
M1
Si7850DP
25
24
SENSE+
L1
4.7µH
20
SENSE–
19
BGRTN
18
BG
17
DRVCC
16
INTVCC
15
EXTVCC
14
NDRV
CDRVCC
0.1µF
VOUT
5V
5A
COUT
47µF
6.3V
×3
M2
Si7850DP
D1
B1100
CVCC
1µF
C5
22µF
PGND
RFB1
10k
38105 TA03
38105fd
34
LTC3810-5
typical Applications
15V to 60V Input Voltage to 3.3V/5A with Fault Timeout,
Pulse Skip and VIN UV Disabled
RNDRV
215k
RON
71.5k
CON
100pF
31
2
3
4
5
6
7
8
PGOOD
CSS
1000pF
ION
LTC3810-5
27
BOOST
TG
VON
VRNG
SW
PGOOD
MODE_SYNC
ITH
VFB
PLL/LPF
9
SS/TRACK
33
SGND
12
SHDN
13
UVIN
SHDN
CC2
47pF
RFB2
3.24k
RC
200k
SGND
CC1
5pF
RFB1
10.2k
26
M3
ZVN4210G
DB
BAS19
CB
0.1µF
VIN
15V TO 60V
CIN1
68µF
100V
CIN2
1µF
100V
PGND
M1
Si7850DP
25
24
SENSE+
L1
4.7µH
– 20
VOUT
3.3V
5A
SENSE
19
BGRTN
18
BG
17
DRVCC
16
INTVCC
15
EXTVCC
14
NDRV
CDRVCC
0.1µF
COUT1
270µF
6.3V
M2
Si7850DP
D1
B1100
CVCC
1µF
COUT2
10µF
6.3V
C5
1µF
PGND
38105 TA04
38105fd
35
LTC3810-5
Package Description
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693 Rev D)
0.70 ±0.05
5.50 ±0.05
4.10 ±0.05
3.50 REF
(4 SIDES)
3.45 ± 0.05
3.45 ± 0.05
PACKAGE OUTLINE
0.25 ± 0.05
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
5.00 ± 0.10
(4 SIDES)
BOTTOM VIEW—EXPOSED PAD
0.75 ± 0.05
R = 0.05
TYP
0.00 – 0.05
R = 0.115
TYP
PIN 1 NOTCH R = 0.30 TYP
OR 0.35 × 45° CHAMFER
31 32
0.40 ± 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
3.50 REF
(4-SIDES)
3.45 ± 0.10
3.45 ± 0.10
(UH32) QFN 0406 REV D
0.200 REF
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
0.25 ± 0.05
0.50 BSC
38105fd
36
LTC3810-5
Revision History
(Revision history begins at Rev D)
REV
DATE
DESCRIPTION
PAGE NUMBER
D
12/10
Change to Operating Temperature Range
2
Updated Order Information table
2
Change made to Feedback Voltage (VFB)
3
Change to Note 2 and Note 7
4
Addition of 150°C to graphs G14, G17, G18, G19, G20, G23, G24, G25, G28 and G30
6, 7, 8
Formula change: Type 2 and Type 3
26
Updated Related Parts table
38
38105fd
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
37
LTC3810-5
Typical Application
13V to 60V Input Voltage to 12V/10A with Trickle Charger Start-Up
RNDRV
100k
RON
263k
CON
100pF
31
ION
LTC3810-5
27
BOOST
2
VON
3
VRNG
4
PGOOD
5
MODE_SYNC
6 I
TH
7 V
FB
8
PLL/LPF
PGOOD
RUV1
200k
CSS
1000pF
9
SS/TRACK
33
SGND
12
SHDN
13
UVIN
SHDN
RUV2
13.3k
CC2
47pF
RFB2
1k
RC
200k
TG
SW
SENSE+
26
NDRV
M1
Si7850DP
L1
10µH
CDRVCC
0.1µF
VOUT
12V
10A
COUT1
270µF
16V
M2
Si7850DP
×2
D1
B1100
15
14
SGND
CC1
5pF
PGND
CB
0.1µF
24
18
BG
DRVCC 17
16
INTV
EXTVCC
CIN2
1µF
100V
DB
BAS19
25
SENSE– 20
19
BGRTN
CC
VIN
13V TO 60V
CIN1
68µF
100V
CVCC
1µF
COUT2
10µF
16V
C5
22µF
RFB1
14k
PGND
38105 TA05
Related Parts
PART NUMBER
DESCRIPTION
COMMENTS
LTC3891
60V, Low IQ, Synchronous Step-Down DC/DC
Controller
PLL Fixed Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ 24V,
TSSOP-20E, 3mm × 4mm QFN-20
LTC3890
60V, Low IQ, Dual Output 2-Phase Synchronous
Step-Down DC/DC Controller
PLL Fixed Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ 24V,
5mm × 5mm QFN-32
LTC3810
100V Synchronous Step-Down DC/DC Controller
Constant On-time Valley Current Mode, 4V ≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ 0.93VIN,
SSOP-28
LTC3812-5
60V Synchronous Step-Down DC/DC Controller
Constant On-time Valley Current Mode, 4V ≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ 0.93VIN,
TSSOP-16E
LTC3703
100V Synchronous Step-Down DC/DC Controller
PLL Fixed Frequency 100kHz to 600kHz, 4V ≤ VIN ≤ 100V, 0.8V ≤ VOUT ≤ 0.93VIN,
SSOP-16, SSOP-28
LT3845A
60V, Low IQ, Single Output Synchronous Step-Down
DC/DC Controller
Adjustable Fixed Frequency 100kHz to 500kHz, 4V≤ VIN ≤ 60V, 1.23V ≤ VOUT ≤
36V, TSSOP-16E
LTC3824
60V, Low IQ, Step-Down DC/DC Controller, 100%
Duty Cycle
Selectable Fixed Frequency 200kHz to 600kHz, 4V≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ VIN,
IQ = 40µA, MSOP-10E
38105fd
38
Linear Technology Corporation
LT 1210 REV D • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 l FAX: (408) 434-0507
l
www.linear.com
LINEAR TECHNOLOGY CORPORATION 2007
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