LTC3813
100V Current Mode
Synchronous Step-Up Controller
FEATURES
DESCRIPTION
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The LTC3813 is a synchronous step-up switching regulator
controller that can generate output voltages up to 100V.
The LTC3813 uses a constant off-time peak current control
architecture with accurate cycle-by-cycle current limit,
without requiring a sense resistor.
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High Output Voltages: Up to 100V
Large 1Ω Gate Drivers
No Current Sense Resistor Required
Dual N-Channel MOSFET Synchronous Drive
±0.5% 0.8V Voltage Reference
Fast Transient Response
Programmable Soft-Start
Generates 10V Driver Supply from Input Supply
Synchronizable to External Clock
Power Good Output Voltage Monitor
Adjustable Off-Time/Frequency: tOFF(MIN) < 100ns
Adjustable Cycle-by-Cycle Current Limit
Programmable Undervoltage Lockout
Output Overvoltage Protection
28-Pin SSOP Package
A precise internal reference provides ±0.5% DC accuracy.
A high bandwidth (25MHz) error amplifier provides very
fast line and load transient response. Large 1Ω gate drivers
allow the LTC3813 to drive multiple MOSFETs for higher
current applications. The operating frequency is selected
by an external resistor and is compensated for variations
in VIN and can also be synchronized to an external clock
for switching-noise sensitive applications. A shutdown pin
allows the LTC3813 to be turned off, reducing the supply
current to 240μA.
APPLICATIONS
PARAMETER
n
MOSFET Gate Drive
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LTC3813
LTC3814-5
100V
60V
6.35V to 14V
4.5V to 14V
6.2V
4.2V
6V
4V
Maximum VOUT
24V Fan Supplies
48V Telecom and Base Station Power Supplies
Networking Equipment, Servers
Automotive and Industrial Control Systems
INTVCC UV +
INTVCC
UV –
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Protected by U.S. Patents,
including 5481178, 5847554, 6304066, 6476589, 6580258, 6677210, 6774611.
TYPICAL APPLICATION
Efficiency vs Load Current
High Efficiency High Voltage Step-Up Converter
50k
500k
PGOOD
VRNG
BOOST
LTC3813
SYNC
1000pF
SHDN
0.1μF
VOUT
50V/5A
SW
DRVCC
D1
MBR1100
INTVCC
ITH
100k
SGND
SENSE–
BGRTN
1μF
VIN = 12V
90
85
30.9k
+
M2
Si7850DP
2x
BG
VIN = 24V
95
22μF
M1
Si7850DP
SENSE+
VFB
100pF
TG
EXTVCC
SS
0.01μF
+
10μH
VIN = 36V
VIN
10V TO 40V
NDRV
IOFF
EFFICIENCY (%)
VOUT
100
499Ω
270μF
2x
80
0
1
2
3
LOAD (A)
4
5
3813 TA01b
3813 TA01
3813fb
1
LTC3813
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
Supply Voltages
INTVCC, DRVCC....................................... –0.3V to 14V
(DRVCC - BGRTN), (BOOST - SW).......... –0.3V to 14V
BOOST ................................................. –0.3V to 114V
BGRTN ........................................................ –5V to 0V
EXTVCC .................................................. –0.3V to 15V
(NDRV - INTVCC) Voltage ........................... –0.3V to 10V
SW, SENSE+ Voltage ................................... –1V to 100V
IOFF Voltage .............................................. –0.3V to 100V
SS Voltage ................................................... –0.3V to 5V
PGOOD Voltage ............................................ –0.3V to 7V
VRNG, VOFF, SYNC, SHDN,
UVIN Voltages........................................ –0.3V to 14V
PLL/LPF, FB Voltages................................. –0.3V to 2.7V
TG, BG, INTVCC, EXTVCC RMS Currents .................50mA
Operating Temperature Range (Note 2)
LTC3813E............................................. –40°C to 85°C
LTC3813I............................................ –40°C to 125°C
Junction Temperature (Notes 3, 7)........................ 125°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
TOP VIEW
IOFF
1
28 BOOST
NC
2
27 TG
NC
3
26 SW
VOFF
4
25 SENSE+
VRNG
5
24 NC
PGOOD
6
23 NC
SYNC
7
22 NC
ITH
8
21 SENSE–
VFB
9
20 BGRTN
PLL/LPF 10
19 BG
SS 11
18 DRVCC
SGND 12
17 INTVCC
SHDN 13
16 EXTVCC
UVIN 14
15 NDRV
G PACKAGE
28-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 100°C/W
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3813EG#PBF
LTC3813EG#TRPBF
LTC3813EG
28-Lead Plastic SSOP
–40°C to 85°C
LTC3813IG#PBF
LTC3813IG#TRPBF
LTC3813IG
28-Lead Plastic SSOP
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The l denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, INTVCC = DRVCC = VBOOST = VOFF = VRNG = SHDN = UVIN = VEXTVCC =
VNDRV = 10V, VSYNC = VSENSE+ = VSENSE – = VBGRTN = VSW = 0V, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Main Control Loop
l
INTVCC
INTVCC Supply Voltage
IQ
INTVCC Supply Current
INTVCC Shutdown Current
SHDN > 1.5V, INTVCC = 9.5V (Notes 4, 5)
SHDN = 0V
IBOOST
BOOST Supply Current
SHDN > 1.5V (Note 5)
SHDN = 0V
6.35
14
V
3
240
6
600
mA
μA
270
0
400
5
μA
μA
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LTC3813
ELECTRICAL CHARACTERISTICS
The l denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, INTVCC = DRVCC = VBOOST = VOFF = VRNG = SHDN = UVIN = VEXTVCC =
VNDRV = 10V, VSYNC = VSENSE+ = VSENSE – = VBGRTN = VSW = 0V, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VFB
Feedback Voltage
(Note 4)
0°C to 85°C
–40°C to 85°C
–40°C to 125°C (I-Grade)
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l
l
0.796
0.794
0.792
0.792
0.800
0.800
0.800
0.800
0.804
0.806
0.806
0.808
V
V
V
V
ΔVFB,LINE
Feedback Voltage Line Regulation
7V < INTVCC < 14V (Note 4)
l
0.002
0.02
%/V
VSENSE(MAX)
Maximum Current Sense Threshold
VRNG = 2V, VFB = 0.76V
VRNG = 0V, VFB = 0.76V
VRNG = INTVCC, VFB = 0.76V
320
95
215
384
120
260
mV
mV
mV
VSENSE(MIN)
Minimum Current Sense Threshold
VRNG = 2V, VFB = 0.84V
VRNG = 0V, VFB = 0.84V
VRNG = INTVCC, VFB = 0.84V
IVFB
Feedback Current
VFB = 0.8V
AVOL(EA)
Error Amplifier DC Open Loop Gain
fU
Error Amp Unity Gain Crossover Frequency
(Note 6)
25
ISYNC
SYNC Current
SYNC = 10V
0
1
μA
VSHDN
Shutdown Threshold
1.5
2
V
ISHDN
SHDN Pin Input Current
0
1
μA
ISS
SS Source Current
256
70
170
–300
–85
–200
20
65
1.2
VSS > 0.5V
VVINUV
VIN Undervoltage Lockout
VIN Rising
VIN Falling
Hysteresis
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VVCCUV
INTVCC Undervoltage Lockout
INTVCC Rising
Hysteresis
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mV
mV
mV
150
100
nA
dB
MHz
0.7
1.4
2.5
μA
0.86
0.78
0.07
0.88
0.80
0.10
0.92
0.82
0.12
V
V
V
6.05
6.2
0.5
6.35
V
V
1.55
515
1.85
605
2.15
695
μs
ns
100
ns
Oscillator and Phase-Locked Loop
tOFF
Off-Time
IOFF = 100μA
IOFF = 300μA
tOFF(MIN)
Minimum Off-Time
IOFF = 2000μA
tON(MIN)
Minimum On-Time
tOFF(PLL)
tOFF Modulation Range by PLL
Down Modulation
Up Modulation
IOFF = 100μA, VPLL/LPF = 0.6V
IOFF = 100μA, VPLL/LPF = 1.8V
Phase Detector Output Current
Sinking Capability
Sourcing Capability
fPLLIN < fSW
fPLLIN > fSW
IBG,PEAK
BG Driver Peak Source Current
VBG = 0V
1.5
RBG,SINK
BG Driver Pulldown RDS(ON)
ITG,PEAK
TG Driver Peak Source Current
VTG – VSW = 0V
1.5
RTG,SINK
TG Driver Pulldown RDS(ON)
IPLL/LPF
350
2.2
0.6
3.6
1.2
ns
5
1.8
μs
μs
15
–25
μA
μA
2
A
Driver
1
1.5
2
1
Ω
A
1.5
Ω
12.5
–12.5
%
%
PGOOD Output
ΔVFBOV
PGOOD Upper Threshold
PGOOD Lower Threshold
VFB Rising
VFB Falling
ΔVFB,HYST
PGOOD Hysteresis
VFB Returning
1.5
3
%
VPGOOD
PGOOD Low Voltage
IPGOOD = 5mA
0.3
0.6
V
7.5
–7.5
10
–10
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LTC3813
ELECTRICAL CHARACTERISTICS
The l denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, INTVCC = DRVCC = VBOOST = VOFF = VRNG = SHDN = UVIN = VEXTVCC =
VNDRV = 10V, VSYNC = VSENSE+ = VSENSE– = VBGRTN = VSW = 0V, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
IPGOOD
PGOOD Leakage Current
VPGOOD = 5V
PG Delay
PGOOD Delay
VFB Falling
MIN
TYP
MAX
0
2
125
UNITS
μA
μs
VCC Regulators
VEXTVCC
EXTVCC Switchover Voltage
EXTVCC Rising
EXTVCC Hysteresis
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VINTVCC,1
INTVCC Voltage from EXTVCC
10.5V < VEXTVCC < 15V
ΔVEXTVCC,1
VEXTVCC - VINTVCC at Dropout
ICC = 20mA, VEXTVCC = 9.1V
ΔVLOADREG,1
INTVCC Load Regulation from EXTVCC
ICC = 0mA to 20mA, VEXTVCC = 12V
VINTVCC,2
INTVCC Voltage from NDRV Regulator
Linear Regulator in Operation
ΔVLOADREG,2
INTVCC Load Regulation from NDRV
ICC = 0mA to 20mA, VEXTVCC = 0
INDRV
Current into NDRV Pin
VNDRV – VINTVCC = 3V
VCCSR
Maximum Supply Voltage
Trickle Charger Shunt Regulator
ICCSR
Maximum Current into NDRV/INTVCC
Trickle Charger Shunt Regulator,
INTVCC ≤ 16.7V (Note 8)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3813E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC3813I is guaranteed to meet
performance specifications over the full –40°C to 125°C operating
temperature range.
Note 3: TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formula:
LTC3813: TJ = TA + (PD • 100°C/W)
6.4
0.1
6.7
0.25
0.5
V
V
9.4
10
10.6
V
170
250
mV
0.01
9.4
10
%
10.6
0.01
20
40
15
10
V
%
60
μA
V
mA
Note 4: The LTC3813 is tested in a feedback loop that servos VFB to the
reference voltage with the ITH pin forced to a voltage between 1V and 2V.
Note 5: The dynamic input supply current is higher due to the power
MOSFET gate charging being delivered at the switching frequency
(QG • fSW).
Note 6: Guaranteed by design. Not subject to test.
Note 7: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 8: ICC is the sum of current into NDRV and INTVCC.
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LTC3813
TYPICAL PERFORMANCE CHARACTERISTICS
Load Transient Response
VOUT
200mV/
DIV
VOUT
20V/DIV
VOUT
20V/DIV
SS
4V/DIV
IOUT
2A/DIV
IL
5A/DIV
IL
5A/DIV
3813 G01
100μs/DIV
FIGURE 14 CIRCUIT
VIN = 12V
0A TO 4A LOAD STEP
VOUT = 24V
3813 G02
1ms/DIV
FRONT PAGE CIRCUIT
VIN = 24V
ILOAD = 2A
300
FRONT PAGE CIRCUIT
VIN = 24V
RSHORT = 1Ω
Frequency vs Load Current
280
FRONT PAGE CIRCUIT
VIN = 12V
FRONT PAGE CIRCUIT
270
280
VIN = 5V
260
ILOAD = 0A
FREQUENCY (kHz)
FREQUENCY (kHz)
95
90
3813 G03
500μs/DIV
Frequency vs Input Voltage
Efficiency vs Load Current
100
EFFICIENCY (%)
Overcurrent Operation
Start-Up
260
ILOAD = 1A
240
85
250
VIN = 24V
240
230
VIN = 12V
220
220
210
80
0
1
2
3
200
4
200
10
LOAD (A)
15
25
30
20
INPUT VOLTAGE (V)
35
40
1
0
3813 G05
3
2
LOAD CURRENT (A)
4
3813 G06
3813 G04
Current Sense Threshold
vs ITH Voltage
Off-Time vs IOFF Current
10000
400
VOFF = INTVCC
VRNG = 2V
300
1.4V
1V
0.7V
0.5V
100
0
–100
500
1000
OFF-TIME (ns)
200
100
400
300
200
–200
100
–300
–400
IOFF = 300μA
600
OFF-TIME (ns)
CURRENT SENSE THRESHOLD (mV)
Off-Time vs VOFF Voltage
700
0
10
0
0.5
1
1.5
2
ITH VOLTAGE (V)
2.5
3
3813 G07
10
100
1000
IOFF CURRENT (μA)
10000
3813 G08
0
0.5
2
1.5
1
VOFF VOLTAGE (V)
2.5
3
3813 G09
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LTC3813
TYPICAL PERFORMANCE CHARACTERISTICS
Maximum Current Sense
Threshold vs VRNG Voltage
IOFF = 300μA
OFF-TIME (ns)
660
640
620
600
580
560
–50 –25
50
25
75
0
TEMPERATURE (°C)
100
125
400
300
200
100
0
0.5
1
1.5
2
VRNG = INTVCC
220
210
200
190
180
–50
–25
0.803
2.5
0.800
0.799
125
Driver Pulldown RDS(ON)
vs Temperature
1.50
VBOOST = VINTVCC = 10V
VBOOST = VINTVCC = 10V
1.25
2.0
1.00
RDS(ON) (Ω)
PEAK SOURCE CURRENT (A)
0.801
100
3813 G12
Driver Peak Source Current
vs Temperature
0.802
50
25
0
75
TEMPERATURE (°C)
3813 G11
Feedback Reference Voltage
vs Temperature
1.5
0.75
0.50
0.798
0.797
–50
230
VRNG VOLTAGE (V)
3813 G10
REFERENCE VOLTAGE (V)
Maximum Current Sense
Threshold vs Temperature
MAXIMUM CURRENT SENSE THRESHOLD (mV)
680
MAXIMUM CURRENT SENSE THRESHOLD (mV)
Off-Time vs Temperature
0.25
–25
50
25
0
75
TEMPERATURE (°C)
100
125
1
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
3813 G13
0
–50 –25
50
25
75
0
TEMPERATURE (°C)
3813 G14
Driver Peak Source Current
vs Supply Voltage
100
125
3813 G15
Driver Pulldown RDS(ON)
vs Supply Voltage
1.1
3.0
2.5
1.0
2.0
RDS(ON) (Ω)
PEAK SOURCE CURRENT (A)
125
1.5
0.9
0.8
1.0
0.7
0.5
0
0.6
5
6
8 9 10 11 12 13 14 15
7
DRVCC/BOOST VOLTAGE (V)
3813 G16
6
7
9 10 11 12 13
8
DRVCC/BOOST VOLTAGE (V)
14
15
3813 G17
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LTC3813
TYPICAL PERFORMANCE CHARACTERISTICS
EXTVCC LDO Resistance at
Dropout vs Temperature
INTVCC Shutdown Current
vs Temperature
INTVCC Current vs Temperature
14
4
400
3
300
10
8
6
4
INTVCC CURRENT (μA)
INTVCC CURRENT (mA)
RESISTANCE (Ω)
12
2
1
200
100
2
0
–50 –25
75
50
25
TEMPERATURE (°C)
0
100
0
–50
125
50
25
0
75
TEMPERATURE (°C)
–25
0
–50 –25
125
75
50
25
TEMPERATURE (°C)
0
3813 G19
3813 G18
3.5
125
SS Pull-Up Current
vs Temperature
300
4.0
100
3813 G20
INTVCC Shutdown Current
vs INTVCC Voltage
INTVCC Current vs INTVCC Voltage
3
INTVCC CURRENT (μA)
2.5
2.0
1.5
1.0
SS CURRENT (μA)
250
3.0
200
150
100
2
1
50
0.5
0
0
2
8
6
10
4
INTVCC VOLTAGE (V)
12
0
14
8
6
10
4
INTVCC VOLTAGE (V)
2
ITH Voltage
vs Load Current
3
12
0
–50 –25
14
50
25
75
0
TEMPERATURE (°C)
3813 G22
3813 G21
100
125
3813 G23
Shutdown Threshold
vs Temperature
2.2
FRONT PAGE CIRCUIT
VIN = 24V
VRNG = 1V
2.0
SHUTDOWN THRESHOLD (V)
0
ITH VOLTAGE (V)
INTVCC CURRENT (mA)
100
2
1
1.8
1.6
1.4
1.2
1.0
0.8
0
0
1
2
LOAD CURRENT (A)
3
4
3813 G24
0.6
–50 –25
75
50
25
TEMPERATURE (°C)
0
100
125
3813 G25
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LTC3813
PIN FUNCTIONS
IOFF (Pin 1): Off-Time Current Input. Tie a resistor from
VOUT to this pin to set the one-shot timer current and
thereby set the switching frequency.
SS (Pin 11): Soft-Start Input. A capacitor to ground at
this pin sets the ramp rate of the maximum current sense
threshold.
VOFF (Pin 4): Off-Time Voltage Input. Voltage trip point
for the on-time comparator. Tying this pin to an external
resistive divider from the input makes the off-time proportional to VIN. The comparator defaults to 0.7V when
the pin is grounded and defaults to 2.4V when the pin is
connected to INTVCC.
SGND (Pin 12): Signal Ground. All small signal components
should connect to this ground and eventually connect to
PGND at one point.
VRNG (Pin 5): Sense Voltage Limit Set. The voltage at this
pin sets the nominal sense voltage at maximum output
current and can be set from 0.5V to 2V by a resistive
divider from INTVCC. The nominal sense voltage defaults
to 95mV when this pin is tied to ground, and 215mV when
tied to INTVCC.
SHDN (Pin 13): Shutdown Pin. Pulling this pin below 1.5V
will shut down the LTC3813, turn off both of the external
MOSFET switches and reduce the quiescent supply current to 240μA.
UVIN (Pin 14): UVLO Input. This pin is input to the internal
UVLO and is compared to an internal 0.8V reference. An
external resistor divider is connected to this pin and the
input supply to program the undervoltage lockout voltage.
When UVIN is less than 0.8V, the LTC3813 is shut down.
PGOOD (Pin 6): Power Good Output. Open-drain logic
output that is pulled to ground when the output voltage
is not between ±10% of the regulation point. The output
voltage must be out of regulation for at least 125μs before
the power good output is pulled to ground.
NDRV (Pin 15): Drive Output for External Pass Device of
the Linear Regulator for INTVCC. Connect to the gate of an
external NMOS pass device and a pull-up resistor to the
input voltage VIN or the output voltage VOUT.
SYNC (Pin 7): Sync Pin. This pin provides an external
clock input to the phase detector. The phase-locked loop
will force the rising top gate signal to be synchronized
with the rising edge of the clock signal.
EXTVCC (Pin 16): External Driver Supply Voltage. When
this voltage exceeds 6.7V, an internal switch connects
this pin to INTVCC through an LDO and turns off the external MOSFET connected to NDRV, so that controller and
gate drive are drawn from EXTVCC.
ITH (Pin 8): Error Amplifier Compensation Point and Current Control Threshold. The current comparator threshold
increases with control voltage. The voltage ranges from
0V to 2.6V with 1.2V corresponding to zero sense voltage
(zero current).
INTVCC (Pin 17): Main Supply Pin. All internal circuits
except the output drivers are powered from this pin.
INTVCC should be bypassed to ground (Pin 10) with at
least a 0.1μF capacitor in close proximity to the
LTC3813.
VFB (Pin 9): Feedback Input. Connect VFB through a resistor
divider network to VOUT to set the output voltage.
DRVCC (Pin 18): Driver Supply Pin. DRVCC supplies power
to the BG output driver. This pin is normally connected to
INTVCC. DRVCC should be bypassed to BGRTN (Pin 20)
with a low ESR (X5R or better) 1μF capacitor in close
proximity to the LTC3813.
PLL/LPF (Pin 10): The phase-locked loop’s lowpass filter
is tied to this pin. The voltage at this pin defaults to 1.2V
when the IC is not synchronized with an external clock at
the SYNC pin.
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LTC3813
PIN FUNCTIONS
BG (Pin 19): Bottom Gate Drive. The BG pin drives the
gate of the bottom N-channel main switch MOSFET. This
pin swings from BGRTN to DRVCC.
BGRTN (Pin 20): Bottom Gate Return. This pin connects to
the source of the pulldown MOSFET in the BG driver and
is normally connected to ground. Connecting a negative
supply to this pin allows the main MOSFET’s gate to be
pulled below ground to help prevent false turn-on during
high dV/dt transitions on the SW node. See the Applications Information section for more details.
SENSE+, SENSE– (Pin 25, Pin 21): Current Sense Comparator Input. The (+) input to the current comparator is
normally connected to SW unless using a sense resistor.
The (–) input is used to accurately kelvin sense the bottom
side of the sense resistor or MOSFET.
SW (Pin 26): Switch Node Connection to Inductor and
Bootstrap Capacitor. Voltage swing at this pin is from a
Schottky diode (external) voltage drop below ground
to VOUT.
TG (Pin 27): Top Gate Drive. The TG pin drives the gate of
the top N-channel synchronous switch MOSFET. The TG
driver draws power from the BOOST pin and returns to the
SW pin, providing true floating drive to the top MOSFET.
BOOST (Pin 28): Top Gate Driver Supply. The BOOST pin
supplies power to the floating TG driver. BOOST should
be bypassed to SW with a low ESR (X5R or better) 0.1μF
capacitor. An additional fast recovery Schottky diode from
DRVCC to the BOOST pin will create a complete floating
charge-pumped supply at BOOST.
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LTC3813
FUNCTIONAL DIAGRAM
VIN
10V
+
NDRV
M3
15
–
OFF
INTVCC
17
VIN
5V
REG
RUV1
UVIN
RUV2
SYNC
14
EXTVCC
0.8V
REF
16
–
–
INTVCC
VIN UV
7
UV
+
0.8V
+
+
–
6.2V
PLL/LPF
+
10V
ON
PLL-SYNC
10
+
VOFF
–
6.7V
4
ROFF
VOUT
1
ON
Q
L
CB
SW
26
20k
+
CIN
28
27
R
S
+
BOOST
TG
VVOFF
tOFF =
(76pF)
IIOFF
IOFF
VIN
DB
OVERTEMP
SENSE
ICMP
SENSE+
SWITCH
LOGIC
25
M1
DRVCC
–
VOUT
18
SHDN
BG
OV
s
CVCC
19
M2
BGRTN
+
20
COUT
SENSE–
1.4V
21
VRNG
FAULT
5
PGOOD
1.4μA
+
ITH
6
RUN
SHDN –
–
0.7V
8
+
+
1.5V
0.72V
UV
–
2.6V
CC2
VFB
4V
RC
CC1
–
+
0.8V
9
SHDN
13
EA
R2
+
SGND
12
OV
–
R1
0.85V
SS
11
3813 FD
3813fb
10
LTC3813
OPERATION
Main Control Loop
The LTC3813 is a current mode controller for DC/DC stepup converters. In normal operation, the top MOSFET is
turned on for a fixed interval determined by a one-shot
timer (OST). When the top MOSFET is turned off, the bottom MOSFET is turned on until the current comparator
ICMP trips, restarting the one-shot timer and initiating the
next cycle. Inductor current is determined by sensing the
voltage between the SENSE– and SENSE+ pins using a
sense resistor or the bottom MOSFET on-resistance. The
voltage on the ITH pin sets the comparator threshold corresponding to the inductor peak current. The fast 25MHz
error amplifier EA adjusts this voltage by comparing the
feedback signal VFB to the internal 0.8V reference voltage. If the load current increases, it causes a drop in the
feedback voltage relative to the reference. The ITH voltage
then rises until the average inductor current again matches
the load current.
The operating frequency is determined implicitly by the
top MOSFET on-time (tOFF) and the duty cycle required to
maintain regulation. The one-shot timer generates a top
MOSFET on-time that is inversely proportional to the IOFF
current and proportional to the VOFF voltage. Connecting
VOUT to IOFF and VIN to VOFF with a resistive divider keeps
the frequency approximately constant with changes in VIN.
The nominal frequency can be adjusted with an external
resistor ROFF.
For applications with stringent constant-frequency requirements, the LTC3813 can be synchronized with an external
clock. By programming the nominal frequency the same as
the external clock frequency, the LTC3813 behaves as a constant-frequency part against the load and supply variations.
Pulling the SHDN pin low forces the controller into its
shutdown state, turning off both M1 and M2. Forcing a
voltage above 1.5V will turn on the device.
inductor current will never exceed the value programmed
on the VRNG pin.
Overvoltage and undervoltage comparators OV and UV
pull the PGOOD output low if the output feedback voltage
exits a ±10% window around the regulation point after the
internal 125μs power bad mask timer expires. Furthermore,
in an overvoltage condition, M1 is turned off and M2 is
turned on immediately and held on until the overvoltage
condition clears.
The LTC3813 provides two undervoltage lockout comparators—one for the INTVCC/DRVCC supply and one for
the input supply VIN. The INTVCC UV threshold is 6.2V to
guarantee that the MOSFETs have sufficient gate drive voltage before turning on. The VIN UV threshold (UVIN pin) is
0.8V with 10% hysteresis which allows programming the
VIN threshold with the appropriate resistor divider connected to VIN. If either comparator inputs are under the
UV threshold, the LTC3813 is shut down and the drivers
are turned off.
Strong Gate Drivers
The LTC3813 contains very low impedance drivers capable
of supplying amps of current to slew large MOSFET gates
quickly. This minimizes transition losses and allows paralleling MOSFETs for higher current applications. A 100V
floating high side driver drives the top side MOSFET and
a low side driver drives the bottom side MOSFET (see
Figure 1). The bottom side driver is supplied directly
from the DRVCC pin. The top MOSFET drivers are biased
from floating bootstrap capacitor CB, which normally is
recharged during each off cycle through an external diode
VIN
DRVCC
+
LTC3813
DRVCC
BOOST
TG
Fault Monitoring/Protection
Constant off-time current mode architecture provides
accurate cycle-by-cycle current limit protection—a feature that is very important for protecting the high voltage power supply from output overcurrent conditions.
The cycle-by-cycle current monitor guarantees that the
CIN
DB
L
CB
SW
BG
M2
M1
+
VOUT
COUT
BGRTN
3813 F01
0V TO –5V
Figure 1. Floating TG Driver Supply and Negative BG Return
3813fb
11
LTC3813
OPERATION
from DRVCC when the top MOSFET turns off. In an output
overvoltage condition, where it is possible that the bottom MOSFET will be off for an extended period of time,
an internal timeout guarantees that the bottom MOSFET
is turned on at least once every 25μs for one top MOSFET
on-time period to refresh the bootstrap capacitor.
The bottom driver has an additional feature that helps
minimize the possibility of external MOSFET shoot-thru.
When the top MOSFET turns on, the switch node dV/dt
pulls up the bottom MOSFET’s internal gate through the
Miller capacitance, even when the bottom driver is holding the gate terminal at ground. If the gate is pulled up
high enough, shoot-thru between the top side and bottom
side MOSFETs can occur. To prevent this from occurring,
the bottom driver return is brought out as a separate pin
(BGRTN) so that a negative supply can be used to reduce
the effect of the Miller pull-up. For example, if a –2V
supply is used on BGRTN, the switch node dV/dt could
pull the gate up 2V before the VGS of the bottom MOSFET
has more than 0V across it.
IC/Driver Supply Power and Linear Regulators
The LTC3813’s internal control circuitry and top and bottom
MOSFET drivers operate from a supply voltage (INTVCC ,
DRVCC pins) in the range of 6.2V to 14V. If the input supply
voltage or another available supply is within this voltage
range it can be used to supply IC/driver power. If a supply
in this range is not available, two internal regulators are
available to generate a 10V supply from the input or output.
An internal low dropout regulator is good for voltages up to
15V, and the second, a linear regulator controller, controls
the gate of an external NMOS to generate the 10V supply.
Since the NMOS is external, the user has the flexibility to
choose a BVDSS as high as necessary.
3813fb
12
LTC3813
APPLICATIONS INFORMATION
The basic LTC3813 application circuit is shown on the first
page of this data sheet. External component selection is
primarily determined by the maximum input voltage and
load current and begins with the selection of the sense
resistance and power MOSFET switches. The LTC3813
uses either a sense resistor or the on-resistance of the
synchronous power MOSFET for determining the inductor current. The desired amount of ripple current and
operating frequency largely determines the inductor
value. Next, COUT is selected for its ability to handle the
large RMS current and with low enough ESR to meet the
output voltage ripple and transient specification. Finally,
loop compensation components are selected to meet the
required transient/phase margin specifications.
Duty Cycle Considerations
For a boost converter, the duty cycle of the main switch is:
D = 1
VIN(MIN)
VIN
; DMAX = 1
VOUT
VOUT
The maximum VOUT capability of the LTC3813 is inversely
proportional to the minimum desired operating frequency
and minimum off-time:
VOUT(MAX) =
VIN(MIN)
f MIN• tOFF(MIN)
100V
Maximum Sense Voltage and the VRNG Pin
The control circuit in the LTC3813 measures the input
current by using the RDS(ON) of the bottom MOSFET or
by using a sense resistor in the bottom MOSFET source,
so the output current needs to be reflected back to the
input in order to dimension the power MOSFET properly
and to choose the maximum sense voltage. Based on the
fact that, ideally, the output power is equal to the input
power, the maximum average input current and average
inductor current is:
IIN(MAX) =IL,AVG(MAX) =
The current mode control loop will not allow the inductor peak to exceed VSENSE(MAX)/RSENSE. In practice, one
should allow some margin for variations in the LTC3813
and external component values, and a good guide for
selecting the maximum sense voltage when VDS sensing
is used is:
VSENSE(MAX) =
1.7 • RDS(ON) •IO(MAX)
1 DMAX
VSENSE is set by the voltage applied to the VRNG pin. Once
VSENSE is chosen, the required VRNG voltage is calculated
to be:
VRNG = 5.78 • (VSENSE(MAX) + 0.026)
An external resistive divider from INTVCC can be used
to set the voltage of the VRNG pin between 0.5V and 2V
resulting in nominal sense voltages of 60mV to 320mV.
Additionally, the VRNG pin can be tied to SGND or INTVCC
in which case the nominal sense voltage defaults to 95mV
or 215mV, respectively.
Connecting the SENSE+ and SENSE– Pins
The LTC3813 can be used with or without a sense resistor. When using a sense resistor, place it between the
source of the bottom MOSFET, M2, and PGND. Connect
the SENSE+ and SENSE– pins to the top and bottom of
the sense resistor. Using a sense resistor provides a well
defined current limit, but adds cost and reduces efficiency.
Alternatively, one can eliminate the sense resistor and use
the bottom MOSFET as the current sense element by simply
connecting the SENSE+ pin to the lower MOSFET drain
and SENSE – pin to the MOSFET source. This improves
efficiency, but one must carefully choose the MOSFET
on-resistance, as discussed in the following section.
IO(MAX)
1 DMAX
3813fb
13
LTC3813
APPLICATIONS INFORMATION
Power MOSFET Selection
The LTC3813 requires two external N-channel power
MOSFETs, one for the bottom (main) switch and one for
the top (synchronous) switch. Important parameters for
the power MOSFETs are the breakdown voltage BVDSS,
threshold voltage V(GS)TH, on-resistance RDS(ON), Miller
capacitance and maximum current IDS(MAX).
When the bottom MOSFET is used as the current sense
element, particular attention must be paid to its on-resistance. MOSFET on-resistance is typically specified with
a maximum value RDS(ON)(MAX) at 25°C. In this case,
additional margin is required to accommodate the rise in
MOSFET on-resistance with temperature:
RDS(ON)(MAX) =
RSENSE
T
The ρT term is a normalization factor (unity at 25°C)
accounting for the significant variation in on-resistance
with temperature (see Figure 2) and typically varies
from 0.4%/°C to 1.0%/°C depending on the particular
MOSFET used.
The most important parameter in high voltage applications
is breakdown voltage BVDSS. Both the top and bottom
MOSFETs will see full output voltage plus any additional
ringing on the switch node across its drain-to-source during its off-time and must be chosen with the appropriate
breakdown specification. Since most MOSFETs in the 60V
to 100V range have higher thresholds (typically VGS(MIN)
≥ 6V), the LTC3813 is designed to be used with a 6.2V to
14V gate drive supply (DRVCC pin).
For maximum efficiency, on-resistance RDS(ON) and input
capacitance should be minimized. Low RDS(ON) minimizes
conduction losses and low input capacitance minimizes
transition losses. MOSFET input capacitance is a combination of several components but can be taken from the
typical “gate charge” curve included on most data sheets
(Figure 3).
VOUT
VGS
MILLER EFFECT
a
V
b
QIN
CMILLER = (QB – QA)/VDS
+
VGS
–
3813 F03
2.0
RT NORMALIZED ON-RESISTANCE
+V
DS
–
Figure 3. Gate Charge Characteristic
1.5
1.0
0.5
0
–50
50
100
0
JUNCTION TEMPERATURE (°C)
150
3813 F02
Figure 2. RDS(ON) vs Temperature
The curve is generated by forcing a constant input current into the gate of a common source, current source
loaded stage and then plotting the gate voltage versus
time. The initial slope is the effect of the gate-to-source
and the gate-to-drain capacitance. The flat portion of the
curve is the result of the Miller multiplication effect of the
drain-to-gate capacitance as the drain drops the voltage
across the current source load. The upper sloping line is
due to the drain-to-gate accumulation capacitance and
the gate-to-source capacitance. The Miller charge (the
3813fb
14
LTC3813
APPLICATIONS INFORMATION
increase in coulombs on the horizontal axis from a to b
while the curve is flat) is specified for a given VDS drain
voltage, but can be adjusted for different VDS voltages by
multiplying by the ratio of the application VDS to the curve
specified VDS values. A way to estimate the CMILLER term
is to take the change in gate charge from points a and b
on a manufacturers data sheet and divide by the stated
VDS voltage specified. CMILLER is the most important selection criteria for determining the transition loss term in
the top MOSFET but is not directly specified on MOSFET
data sheets. CRSS and COS are specified sometimes but
definitions of these parameters are not included.
When the controller is operating in continuous mode
the duty cycles for the top and bottom MOSFETs are
given by:
Main Switch Duty Cycle =
VOUT VIN
VOUT
Synchronous Switch Duty Cycle =
VIN
VOUT
The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
2
IO(MAX)
PMAIN = DMAX
(T )RDS(ON)
1 DMAX
+
IO(MAX)
1
VOUT 2
(RDR )(CMILLER )
2
1 DMAX
where ρT is the temperature dependency of RDS(ON), RDR
is the effective top driver resistance (approximately 2Ω at
VGS = VMILLER). VTH(IL) is the data sheet specified typical
gate threshold voltage specified in the power MOSFET data
sheet at the specified drain current. CMILLER is the calculated
capacitance using the gate charge curve from the MOSFET
data sheet and the technique described above.
Both MOSFETs have I2R losses while the bottom N-channel
equation includes an additional term for transition losses.
Both top and bottom MOSFET I2R losses are greatest at
lowest VIN , and the top MOSFET I2R losses also peak
during an overcurrent condition when it is on close to
100% of the period. For most LTC3813 applications,
the transition loss and I2R loss terms in the bottom
MOSFET are comparable, so best efficiency is obtained
by choosing a MOSFET that optimizes both RDS(ON) and
CMILLER. Since there is no transition loss term in the synchronous MOSFET, however, optimal efficiency is obtained
by minimizing RDS(ON) —by using larger MOSFETs or
paralleling multiple MOSFETs.
Multiple MOSFETs can be used in parallel to lower RDS(ON)
and meet the current and thermal requirements if desired.
The LTC3813 contains large low impedance drivers capable
of driving large gate capacitances without significantly
slowing transition times. In fact, when driving MOSFETs
with very low gate charge, it is sometimes helpful to
slow down the drivers by adding small gate resistors
(10Ω or less) to reduce noise and EMI caused by the
fast transitions.
1
1
•
+
(f)
DRVCC – VTH(IL) VTH(IL)
1
PSYNC =
(IO(MAX) )2(T ) RDS(0N)
1 DMAX
3813fb
15
LTC3813
APPLICATIONS INFORMATION
Operating Frequency
The choice of operating frequency is a tradeoff between
efficiency and component size. Low frequency operation
improves efficiency by reducing MOSFET switching losses
but requires larger inductance and/or capacitance in order
to maintain low output ripple voltage.
The operating frequency of LTC3813 applications is determined implicitly by the one-shot timer that controls
the on-time tOFF of the synchronous MOSFET switch.
The on-time is set by the current into the IOFF pin and the
voltage at the VOFF pin according to:
tOFF =
VVOFF
(76pF )
IIOFF
Tying a resistor ROFF from VOUT to the IOFF pin yields a
synchronous MOSFET on-time inversely proportional to
VOUT. This results in the following operating frequency
and also keeps frequency constant as VOUT ramps up at
start-up:
f=
The VOFF pin can be connected to INTVCC or ground or
can be connected to a resistive divider from VIN. The VOFF
pin has internal clamps that limit its input to the one-shot
timer. If the pin is tied below 0.7V, the input to the oneshot is clamped at 0.7V. Similarly, if the pin is tied above
2.4V, the input is clamped at 2.4V. Note, however, that
if the VOFF pin is connected to a constant voltage, the
operating frequency will be proportional to the input
voltage VIN. Figures 4a and 4b illustrate how ROFF relates
to switching frequency as a function of the input voltage
and VOFF voltage. To hold frequency constant for input
voltage changes, tie the VOFF pin to a resistive divider from
VIN, as shown in Figure 5. Choose the resistor values so
that the VRNG voltage equals about 1.55V at the mid-point
of VIN as follows:
VIN,MID =
VIN(MAX) + VIN(MIN)
2
R1
= 1.55V • 1+
R2
VIN
(Hz)
VVOFF • ROFF (76pF)
1000
VIN = 5V
1+R1/R2 = 3.2
(VIN,MID = 5V)
SWITCHING FREQUENCY (kHz)
SWITCHING FREQUENCY (kHz)
1000
VIN = 24V
VIN = 12V
1+R1/R2 = 7.7
(VIN,MID =12V)
1+R1/R2 = 15.5
(VIN,MID = 24V)
100
100
10
100
ROFF (kΩ)
1000
3813 F04a
Figure 4a. Switching Frequency vs ROFF (VOFF = INTVCC)
10
100
ROFF (kΩ)
1000
3813 F04b
Figure 4b. Switching Frequency vs ROFF
(VOFF Connected to a Resistor Divider from VIN)
3813fb
16
LTC3813
APPLICATIONS INFORMATION
f=
1+ R1/ R2
(Hz)
ROFF (76pF)
for the range of 0.45VIN to 1.55 • VIN , and will be proportional to VIN outside of this range.
Changes in the load current magnitude will also cause
a frequency shift. Parasitic resistance in the MOSFET
switches and inductor reduce the effective voltage across
the inductance, resulting in increased duty cycle as the
load current increases. By shortening the off-time slightly
as current increases, constant-frequency operation can be
maintained. This is accomplished with a resistor connected
from the ITH pin to the IOFF pin to increase the IOFF current
slightly as VITH increases. The values required will depend
on the parasitic resistances in the specific application. A
good starting point is to feed about 10% of the ROFF current with RITH as shown in Figure 6.
VIN
R1
VOFF
R2
Minimum On-Time and Dropout Operation
The minimum on-time tON(MIN) is the smallest amount of
time that the LTC3813 is capable of turning on the bottom
MOSFET, tripping the current comparator and turning the
MOSFET back off. This time is generally about 350ns. The
minimum on-time limit imposes a minimum duty cycle
of tON(MIN)/(tON(MIN) + tOFF). If the minimum duty cycle is
reached, due to a rising input voltage, for example, then
the output will rise out of regulation. The maximum input
voltage to avoid dropout is:
VIN(MAX) = VOUT
tOFF
tON(MIN) + tOFF
A plot of maximum duty cycle vs switching frequency is
shown in Figure 7.
2.0
SWITCHING FREQUENCY (MHz)
With these resistor values, the frequency will remain
relatively constant at:
1.5
DROPOUT
REGION
1.0
0.5
LTC3813
0
0
0.25
3813 F05
Figure 5. VOFF Connection to Keep the Operating
Frequency Constant as the Input Supply Varies
0.50
VIN/VOUT
0.75
1.0
3813 F07
Figure 7. Maximum Duty Cycle vs Switching Frequency
Inductor Selection
VOUT
ROFF
IOFF
1000pF
RITH
LTC3813
ITH
RITH =
10ROFF
VOUT
3813 F06
Figure 6. Correcting Frequency Shift with Load Current Changes
An inductor should be chosen that can carry the maximum
input DC current which occurs at the minimum input voltage. The peak-to-peak ripple current is set by the inductance
and a good starting point is to choose a ripple current of
at least 40% of its maximum value:
IL = 40% •
IO(MAX)
1 DMAX
3813fb
17
LTC3813
APPLICATIONS INFORMATION
The required inductance can then be calculated to be:
L=
VIN(MIN) • DMAX
f • IL
The required saturation of the inductor should be chosen
to be greater than the peak inductor current:
IL(SAT)
IO(MAX)
1 DMAX
+
IL
2
where the first term is due to the bulk capacitance and
second term due to the ESR.
For many designs it is possible to choose a single capacitor
type that satisfies both the ESR and bulk C requirements
for the design. In certain demanding applications, however,
the ripple voltage can be improved significantly by connecting two or more types of capacitors in parallel. For
example, using a low ESR ceramic capacitor can minimize
the ESR step, while an electrolytic capacitor can be used
to supply the required bulk C.
Once the value for L is known, the type of inductor must be
selected. High efficiency converters generally cannot afford
the core loss found in low cost powdered iron cores, forcing
the use of more expensive ferrite, molypermalloy or Kool Mμ®
cores. A variety of inductors designed for high current, low
voltage applications are available from manufacturers such
as Sumida, Panasonic, Coiltronics, Coilcraft and Toko.
Schottky Diode D1 Selection
The Schottky diode D1 shown in the front page schematic
conducts during the dead time between the conduction of
the power MOSFET switches. It is intended to prevent the
body diode of the synchronous MOSFET from turning on
and storing charge during the dead time, which can cause
a modest (about 1%) efficiency loss. The diode can be
rated for about one half to one fifth of the full load current
since it is on for only a fraction of the duty cycle. The peak
reverse voltage that the diode must withstand is equal to
the regulator output voltage. In order for the diode to be
effective, the inductance between it and the synchronous
MOSFET must be as small as possible, mandating that
these components be placed adjacently. The diode can
be omitted if the efficiency loss is tolerable.
L
VIN
D
SW
COUT
RL
8a. Circuit Diagram
IIN
IL
8b. Inductor and Input Currents
ISW
tON
8c. Switch Current
ID
tOFF
IO
8d. Diode and Output Currents
Output Capacitor Selection
In a boost converter, the output capacitor requirements
are demanding due to the fact that the current waveform
is pulsed. The choice of component(s) is driven by the
acceptable ripple voltage which is affected by the ESR,
ESL and bulk capacitance as shown in Figure 8e. The total
output ripple voltage is:
VOUT
ΔVCOUT
VOUT
(AC)
ΔVESR
RINGING DUE TO
TOTAL INDUCTANCE
(BOARD + CAP)
8e. Output Voltage Ripple Waveform
3813 F08
Figure 8. Switching Waveforms for a Boost Converter
ESR
1
VOUT =IO(MAX)
+
f • COUT 1– DMAX
3813fb
18
LTC3813
APPLICATIONS INFORMATION
Once the output capacitor ESR and bulk capacitance
have been determined, the overall ripple voltage waveform should be verified on a dedicated PC board (see PC
Board Layout Checklist section for more information on
component placement). Lab breadboards generally suffer
from excessive series inductance (due to inter-component
wiring), and these parasitics can make the switching
waveforms look significantly worse than they would be
on a properly designed PC board.
The output capacitor in a boost regulator experiences high
RMS ripple currents, as shown in Figure 8d. The RMS
output capacitor ripple current is:
IRMS(COUT) IO(MAX) •
VO – VIN(MIN)
VIN(MIN)
Note that the ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life. This
makes it advisable to further derate the capacitor or to
choose a capacitor rated at a higher temperature than
required. Several capacitors may also be placed in parallel
to meet size or height requirements in the design.
Manufacturers such as Nichicon, Nippon Chemi-con
and Sanyo should be considered for high performance
throughhole capacitors. The OS-CON (organic semiconductor dielectric) capacitor available from Sanyo has the
lowest product of ESR and size of any aluminum electrolytic
at a somewhat higher price. An additional ceramic capacitor in parallel with OS-CON capacitors is recommended
to reduce the effect of their lead inductance.
In surface mount applications, multiple capacitors placed
in parallel may be required to meet the ESR, RMS current
handling and load step requirements. Dry tantalum, special
polymer and aluminum electrolytic capacitors are available
in surface mount packages. Special polymer capacitors
offer very low ESR but have lower capacitance density
than other types. Tantalum capacitors have the highest
capacitance density but it is important to only use types
that have been surge tested for use in switching power
supplies. Several excellent surge-tested choices are the
AVX TPS and TPSV or the KEMET T510 series. Aluminum
electrolytic capacitors have significantly higher ESR, but
can be used in cost-driven applications providing that
consideration is given to ripple current ratings and long
term reliability. Other capacitor types include Panasonic
SP and Sanyo POSCAPs. In applications with VOUT > 30V,
however, choices are limited to aluminum electrolytic and
ceramic capacitors.
Input Capacitor Selection
The input capacitor of a boost converter is less critical
than the output capacitor, due to the fact that the inductor
is in series with the input and the input current waveform
is continuous (see Figure 8b). The input voltage source
impedance determines the size of the input capacitor,
which is typically in the range of 10μF to 100μF. A low
ESR capacitor is recommended though not as critical as
for the output capacitor.
The RMS input capacitor ripple current for a boost converter is:
IRMS(CIN) = 0.3 •
VIN(MIN)
L•f
• DMAX
Please note that the input capacitor can see a very high
surge current when a battery is suddenly connected to
the input of the converter and solid tantalum capacitors
can fail catastrophically under these conditions. Be sure
to specify surge-tested capacitors!
Output Voltage
The LTC3813 output voltage is set by a resistor divider
according to the following formula:
R
VOUT = 0.8V 1+ FB1
RFB2
The external resistor divider is connected to the output as
shown in the Functional Diagram, allowing remote voltage
sensing. The resultant feedback signal is compared with
the internal precision 800mV voltage reference by the
error amplifier. The internal reference has a guaranteed
tolerance of < 1%. Tolerance of the feedback resistors
will add additional error to the output voltage. 0.1% to
1% resistors are recommended.
3813fb
19
LTC3813
APPLICATIONS INFORMATION
Input Voltage Undervoltage Lockout
A resistor divider connected from the input supply to the
UVIN pin (see Functional Diagram) is used to program the
input supply undervoltage lockout thresholds. When the
rising voltage at UVIN reaches 0.88V, the LTC3813 turns
on, and when the falling voltage at UVIN drops below 0.8V,
the LTC3813 is shut down—providing 10% hysteresis.
The input voltage UVLO thresholds are set by the resistor
divider according to the following formulas:
R
VIN,FALLING = 0.8V • 1+ UV1
RUV2
and
R
VIN,RISING = 0.88V • 1+ UV1
R
UV2
If input supply undervoltage lockout is not needed, it can
be disabled by connecting UVIN to INTVCC .
Top MOSFET Driver Supply (CB, DB)
An external bootstrap capacitor CB connected to the BOOST
pin supplies the gate drive voltage for the topside MOSFET.
This capacitor is charged through diode DB from DRVCC
when the switch node is low. When the top MOSFET turns
on, the switch node rises to VOUT and the BOOST pin
rises to approximately VOUT + DRVCC. The boost capacitor
needs to store about 100x the gate charge required by the
top MOSFET. In most applications, 0.1μF to 0.47μF, X5R
or X7R dielectric capacitor is adequate.
The reverse breakdown of the external diode, DB, must be
greater than VOUT. Another important consideration for the
external diode is the reverse recovery and reverse leakage,
either of which may cause excessive reverse current to flow
at full reverse voltage. If the reverse current times reverse
voltage exceeds the maximum allowable power dissipation, the diode may be damaged. For best results, use an
ultrafast recovery diode such as the MMDL770T1.
Bottom MOSFET Driver Return Supply (BGRTN)
The bottom gate driver, BG, switches from DRVCC to
BGRTN where BGRTN can be a voltage between ground
and –5V. Why not just keep it simple and always connect
BGRTN to ground? In high voltage switching converters,
the switch node dV/dt can be many volts/ns, which will
pull up on the gate of the bottom MOSFET through its
Miller capacitance. If this Miller current, times the internal
gate resistance of the MOSFET plus the driver resistance,
exceeds the threshold of the FET, shoot-through will occur. By using a negative supply on BGRTN, the BG can be
pulled below ground when turning the bottom MOSFET off.
This provides a few extra volts of margin before the gate
reaches the turn-on threshold of the MOSFET. Be aware
that the maximum voltage difference between DRVCC and
BGRTN is 14V. If, for example, VBGRTN = –2V, the maximum
voltage on DRVCC pin is now 12V instead of 14V.
IC/MOSFET Driver Supplies (INTVCC and DRVCC)
The LTC3813 drivers are supplied from the DRVCC pin
and the LTC3813 internal circuits from INTVCC pin (see
Figure 1). These pins have an operating range between
6.2V and 14V. If the input voltage or another supply is not
available in this voltage range, two internal regulators are
provided to simplify the generation of this IC/driver supply
voltage as described in the next sections.
The NDRV Pin Regulator
The NDRV pin controls the gate of an external NMOS as
shown in Figure 9b and can be used to generate a regulated 10V supply from VIN or VOUT. Since the NMOS is
external, it can be chosen with a BVDSS or power rating
as high as necessary to safely derive power from a high
voltage input or output voltage. In order to generate an
INTVCC supply that is always above the 6.2V UV threshold,
the supply connected to the drain must be greater than
6.2V + RNDRV • 40μA + VT.
The EXTVCC Pin Regulator
A second low dropout regulator is available for voltages
≤ 15V. When a supply that is greater than 6.7V is connected to the EXTVCC pin, the internal LDO will regulate
10V on INTVCC from the EXTVCC pin voltage and will also
disable the NDRV pin regulator. This regulator is disabled
when the IC is shut down, when INTVCC < 6.2V, or when
EXTVCC < 6.7V.
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LTC3813
APPLICATIONS INFORMATION
Using the INTVCC Regulators
One, both or neither of these regulators can be used to
generate the 10V IC/driver supply depending on the circuit
requirements, available supplies, and the voltage range
of VIN or VOUT. Deriving the 10V supply from VIN is more
efficient, however deriving it from VOUT has the advantage
of maintaining regulation of VOUT when VIN drops below
the UV threshold. Four possible configurations are shown
in Figures 9a through 9d, and are described as follows:
1. Figure 9a. If the VIN voltage or another low voltage
supply between 6.2V and 14V is available, the simplest approach is to connect this supply directly to the
INTVCC and DRVCC pins. The internal regulators are
disabled by shorting NDRV and EXTVCC to INTVCC.
2. Figure 9b. If VIN(MAX) > 14V, an external NMOS connected to the NDRV pin can be used to generate 10V
from VIN . VIN(MIN) must be > 6.2V + RNDRV • 40μA + VT
to keep INTVCC above the UV threshold and the BVDSS
of the external NMOS must be chosen to be greater
than VIN(MAX). The EXTVCC regulator is disabled by
grounding the EXTVCC pin.
3. Figure 9c. If the VIN(MAX) < 14.7V and VIN is allowed to
fall below 6.2V without disrupting the boost converter
operation, use this configuration. The INTVCC supply
is derived from VIN until the VOUT > 6.7V. Once INTVCC
is derived from VOUT, VIN can fall below the 6V UV
threshold without losing regulation of VOUT. Note that
in this configuration, VIN must be > 7V at least long
enough to start up the LTC3813 and charge VOUT >
6.7V. Also, since VOUT is connected to the EXTVCC pin,
this configuration is limited to VOUT < 15V.
4. Figure 9d. Similar to configuration 3 except that VOUT
is allowed to be >15V since VOUT is connected to an
external NMOS with appropriately rated BVDSS . VIN has
same start-up requirement as 3.
VIN
RNDRV
NDRV
NDRV
INTVCC
INTVCC
+
+
–
LTC3813
EXTVCC
6.2V to
14V
+
10V
LTC3813
EXTVCC
(a) 6.2V to 14V
Supply Available
(b) INTVCC from VIN,
VIN > 14V
VOUT
VIN < 14.7V
VIN < 14.7V
RNDRV
NDRV
NDRV
INTVCC
+
INTVCC
10V
+
10V
LTC3813
LTC3813
EXTVCC
VOUT ≤ 15V
EXTVCC
3813 F09
(c) INTVCC from VOUT,
VOUT ≤ 15V
(d) INTVCC from VOUT,
VOUT > 15V
Figure 9. Four Possible Ways to Generate INTVCC Supply
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LTC3813
APPLICATIONS INFORMATION
Power Dissipation Considerations
Applications using large MOSFETs and high frequency
of operation may result in a large DRVCC /INTVCC supply
current. Therefore, when using the linear regulators, it is
necessary to verify that the resulting power dissipation
is within the maximum limits. The DRVCC /INTVCC supply
current consists of the MOSFET gate current plus the
LTC3813 quiescent current:
H(s) =
VOUT (s) RL • VIN • VSENSE(MAX)
=
VITH (s) 2.4 • VOUT • RDS(ON)
1+ s • RESR • COUT
•
1+ s • RL • COUT
L VOUT 2
• 1 s •
•
RL VIN2
s = j2 f
ICC = (f)(QG(TOP) + QG(BOTTOM)) + 3mA
TJ = TA + IEXTVCC • (VEXTVCC – VINTVCC)(100°C/W)
and must not exceed 125°C.
Likewise, if the external NMOS regulator is used, the worst
case power dissipation is calculated to be:
PMOSFET = (VDRAIN(MAX) – 10V) • ICC
and can be used to properly size the device.
FEEDBACK LOOP/COMPENSATION
Introduction
180
90
GAIN
0
0
PHASE (DEG)
In a typical LTC3813 circuit, the feedback loop consists of
two sections: the modulator/output stage and the feedback
amplifier/compensation network. The modulator/output
stage consists of the current sense component and internal current comparator, the power MOSFET switches
and drivers, and the output filter and load. The transfer
function of the modulator/output stage for a boost converter consists of an output capacitor pole, RLCOUT, and
an ESR zero, RESRCOUT, and also a “right-half plane” zero,
(RL /L)(VIN 2 / VOUT 2). It has a gain/phase curve that is typically like the curve shown in Figure 10 and is expressed
mathematically in the following equation.
This portion of the power supply is pretty well out of the
user’s control since the current sense is chosen based on
maximum output load, and the output capacitor is usually
chosen based on load regulation and ripple requirements
without considering AC loop response. The feedback amplifier, on the other hand, gives us a handle on which to
adjust the AC response. The goal is to have an 180° phase
shift at DC so the loop regulates and less than 360° phase
shift at the point where the loop gain falls below 0dB, i.e.,
the crossover frequency, with as much gain as possible
at frequencies below the crossover frequency. Since the
feedback amplifier adds an additional 90° phase shift to
the phase shift already present from the modulator/output
stage, some phase boost is required at the crossover
frequency to achieve good phase margin. The design
procedure (described in more detail in the next section) is
to (1) obtain a gain/phase plot of modulator/output stage,
(2) choose a crossover frequency and the required phase
boost, and (3) calculate the compensation network.
GAIN (dB)
When using the internal LDO regulator, the power dissipation is internal so the rise in junction temperature can be
estimated from the equation given in Note 2 of the Electrical
Characteristics as follows:
(1)
PHASE
–90
–180
FREQUENCY (Hz)
3813 F10
Figure 10. Bode Plot of Boost Modulator/Output Stage
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LTC3813
APPLICATIONS INFORMATION
C1
R2
R1
FB
GAIN (dB)
IN
–6dB/OCT
GAIN
–6dB/OCT
–
OUT
RB
VREF
PHASE (DEG)
C2
0
FREQ
+
–90
–180
PHASE
–270
–360
3813 F11
Figure 11. Type 2 Schematic and Transfer Function
IN
R1
R3
FB
R2
GAIN (dB)
C3
C1
–6dB/OCT
–
GAIN
OUT
RB
VREF
PHASE (DEG)
C2
+6dB/OCT
–6dB/OCT
0
FREQ
+
–90
PHASE
–180
–270
–360
3813 F12
Figure 12. Type 3 Schematic and Transfer Function
The two types of compensation networks, Type 2 and Type
3 are shown in Figures 11 and 12. When component values
are chosen properly, these networks provide a “phase
bump” at the crossover frequency. Type 2 uses a single
pole-zero pair to provide up to about 60° of phase boost
while Type 3 uses two poles and two zeros to provide up
to 150° of phase boost.
The compensation of boost converters are complicated
by two factors: the RHP zero and the dependence of the
loop gain on the duty cycle. The RHP zero adds additional
phase lag and gain. The phase lag degrades phase margin
and the added gain keeps the gain high typically in the
frequency region where the user is trying the roll off the
gain below 0dB. This often forces the user to choose a
crossover frequency at a lower frequency than originally
desired. The duty cycle effect of gain (see above transfer
function) causes the phase margin and crossover frequency
to be dependent on the input supply voltage which may
cause problems if the input voltage varies over a wide range
since the compensation network can only be optimized
for a specific crossover frequency. These two factors
usually can be overcome if the crossover frequency is
chosen low enough.
Feedback Component Selection
Selecting the R and C values for a typical Type 2 or
Type 3 loop is a nontrivial task. The applications shown
in this data sheet show typical values, optimized for the
power components shown. They should give acceptable
performance with similar power components, but can be
way off if even one major power component is changed
significantly. Applications that require optimized transient
response will require recalculation of the compensation
values specifically for the circuit in question. The underlying mathematics are complex, but the component values
can be calculated in a straightforward manner if we know
the gain and phase of the modulator at the crossover
frequency.
Modulator gain and phase can be obtained in one of
three ways: measured directly from a breadboard, or if
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LTC3813
APPLICATIONS INFORMATION
the appropriate parasitic values are known, simulated or
generated from the modulator transfer function. Measurement will give more accurate results, but simulation
or transfer function can often get close enough to give
a working system. To measure the modulator gain and
phase directly, wire up a breadboard with an LTC3813
and the actual MOSFETs, inductor and input and output
capacitors that the final design will use. This breadboard
should use appropriate construction techniques for high
speed analog circuitry: bypass capacitors located close
to the LTC3813, no long wires connecting components,
appropriately sized ground returns, etc. Wire the feedback
amplifier with a 0.1μF feedback capacitor from ITH to FB
and a 10k to 100k resistor from VOUT to FB. Choose the
bias resistor (RB) as required to set the desired output
voltage. Disconnect RB from ground and connect it to
a signal generator or to the source output of a network
analyzer to inject a test signal into the loop. Measure the
gain and phase from the ITH pin to the output node at the
positive terminal of the output capacitor. Make sure the
analyzer’s input is AC coupled so that the DC voltages
present at both the ITH and VOUT nodes do not corrupt
the measurements or damage the analyzer.
If breadboard measurement is not practical, mathematical software such as MATHCAD or MATLAB can be used
to generate plots from the transfer function given in
equation 1. A SPICE simulation can also be used to generate approximate gain/phase curves. Plug the expected
capacitor, inductor and MOSFET values into the following
SPICE deck and generate an AC plot of VOUT/ VITH with gain
in dB and phase in degrees. Refer to your SPICE manual
for details of how to generate this plot.
*This file simulates a simplified model of
the LTC3813 for generating a v(out)/(vith)
or a v(out)/v(outin) bode plot
.param
.param
.param
.param
.param
.param
*
vout=24
vin=12
L=10u
cout=270u
esr=.018
rload=24
.param rdson=0.02
.param Vrng=1
.param vsnsmax={0.173*Vrng-0.026}
.param K={vsnsmax/rdson/1.2}
.param wz={1/esr/cout}
.param wp={2/rload/cout}
*
* Feedback Amplifier
rfb1 outin vfb 29k
rfb2 vfb 0 1k
eithx ithx 0 laplace {0.8-v(vfb)} =
{1/(1+s/1000)}
eith ith 0 value={limit(1e6*v(ithx),0,2.4)}
cc1 ith vfb 100p
cc2 ith x1 0.01μ
rc x1 vfb 100k
*
* Modulator/Output Stage
eout out 0 laplace {v(ith)} =
{0.5*K*Rload*vin/vout *(1+s/wz)/(1+s/wp)
*(1-s*L/Rload*vout*vout/vin/vin)}
rload out 0 {rload}
*
vstim out outin dc=0 ac=10m; ac stimulus
.ac dec 100 10 10meg
.probe
.end
With the gain/phase plot in hand, a loop crossover frequency can be chosen. Usually the curves look something
like Figure 10. Choose the crossover frequency about 25%
of the switching frequency for maximum bandwidth. Although it may be tempting to go beyond fSW/4, remember
that significant phase shift occurs at half the switching
frequency that isn’t modeled in the above H(s) equation
and PSPICE code. Note the gain (GAIN, in dB) and phase
(PHASE, in degrees) at this point. The desired feedback
amplifier gain will be –GAIN to make the loop gain at 0dB
at this frequency. Now calculate the needed phase boost,
assuming 60° as a target phase margin:
BOOST = – (PHASE + 30°)
If the required BOOST is less than 60°, a Type 2 loop can
be used successfully, saving two external components.
BOOST values greater than 60° usually require Type 3
loops for satisfactory performance.
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24
LTC3813
APPLICATIONS INFORMATION
Finally, choose a convenient resistor value for R1 (10k
is usually a good value). Now calculate the remaining
values:
(K is a constant, used in the calculations)
f = chosen crossover frequency
G = 10(GAIN/20) (this converts GAIN in dB to G in
absolute gain)
TYPE 2 Loop:
BOOST
K = tan
+ 45°
2
1
C2 =
2 • f • G • K • R1
(
)
C1= C2 K 2 1
K
R2 =
2 • f • C1
V (R1)
RB = REF
VOUT VREF
SPICE or mathematical software can be used to generate
the gain/phase plots for the compensated power supply to
do a sanity check on the component values before trying
them out on the actual hardware. For software, use the
following transfer function:
T(s) = A(s)H(s)
where H(s) was given in equation 1 and A(s) depends on
compensation circuit used:
Type 2:
A (s) =
Type 3:
A (s) =
1
2 • f • G • R1
C1= C2 (K 1)
C2 =
K
2 • f • C1
R1
R3 =
K1
1
C3 =
2f K • R3
V (R1)
RB = REF
VOUT VREF
R2 =
1
•
s • R1• (C2 + C3)
(1+ s • (R1+ R3) • C3) • (1+ s • R2 • C1)
C1• C2
(1+ s • R3 • C3) • 1+ s • R2 • C1+
C2
TYPE 3 Loop:
BOOST
K = tan2
+ 45°
4
1+ s • R3 • C2
C2 • C3
s • R1• (C2 + C3) • 1+ s • R3 •
C2 + C3
For SPICE, simulate the previous PSPICE code with
calculated compensation values entered and generate a
gain/phase plot of VOUT/VOUTIN.
Fault Conditions: Current Limit
The maximum inductor current is inherently limited in a
current mode controller by the maximum sense voltage.
In the LTC3813, the maximum sense voltage is controlled
by the voltage on the VRNG pin. With peak current control,
the maximum sense voltage and the sense resistance
determine the maximum allowed inductor peak current.
The corresponding output current limit is:
ILIMIT =
VSNS(MAX)
RDS(ON)
1
IL
T 2
The current limit value should be checked to ensure that
ILIMIT(MIN) > IOUT(MAX). The minimum value of current limit
generally occurs at the lowest VIN at the highest ambient
temperature, conditions that cause the largest power loss
in the converter. Note that it is important to check for
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25
LTC3813
APPLICATIONS INFORMATION
self-consistency between the assumed MOSFET junction
temperature and the resulting value of ILIMIT which heats
the MOSFET switches.
Caution should be used when setting the current limit
based upon the RDS(ON) of the MOSFETs. The maximum
current limit is determined by the minimum MOSFET
on-resistance. Data sheets typically specify nominal
and maximum values for RDS(ON), but not a minimum.
A reasonable assumption is that the minimum RDS(ON)
lies the same percentage below the typical value as the
maximum lies above it. Consult the MOSFET manufacturer
for further guidelines.
Note that in a boost mode architecture, it is only possible
to provide protection for “soft” shorts where VOUT > VIN .
For hard shorts, the inductor current is limited only by the
input supply capability.
Soft-Start
The LTC3813 has the ability to soft-start with a capacitor
connected to the SS pin. The LTC3813 is put in a low
quiescent current shutdown state (IQ ~240μA) if the
SHDN pin voltage is below 1.5V. The SS pin is actively
pulled to ground in this shutdown state. Once the SHDN
pin voltage is above 1.5V, the LTC3813 is powered up. A
soft-start current of 1.4μA then starts to charge the softstart capacitor CSS. Soft-start is achieved by limiting the
maximum output current of the controller by controlling
the ramp rate of the ITH voltage. The total soft-start time
can be calculated as:
t SOFTSTART 2.4 •
The LTC3813 incorporates a pulse detection circuit that
will detect a clock on the SYNC pin. In turn, it will turn on
the phase-locked loop function. The pulse width of the
clock has to be greater than 400ns and the amplitude of
the clock should be greater than 2V.
The internal oscillator locks to the external clock after the
second clock transition is received. If an external clock
transition is not detected for three successive periods, the
internal oscillator will revert to the frequency programmed
by the ROFF resistor.
During the start-up phase, phase-locked loop function is
disabled. When LTC3813 is not in synchronization mode,
PLL/LPF pin voltage is set to around 1.215V. Frequency
synchronization is accomplished by changing the internal off-time current according to the voltage on the
PLL/LPF pin.
The phase detector used is an edge sensitive digital type
which provides zero degrees phase shift between the external and internal pulses. This type of phase detector will
not lock up on input frequencies close to the harmonics
of the VCO center frequency. The PLL hold-in range, ΔfH,
is equal to the capture range, ΔfC:
ΔfH = ΔfC = ±0.3 fO
The output of the phase detector is a complementary pair of
current sources charging or discharging the external filter
network on the PLL/LPF pin. A simplified block diagram
is shown in Figure 13.
RLP
CSS
1.4μA
Phase-Locked Loop and Frequency Synchronization
The LTC3813 has a phase-locked loop comprised of an
internal voltage controlled oscillator and phase detector.
This allows the top MOSFET turn-on to be locked to the
rising edge of an external source. The frequency range
of the voltage controlled oscillator is ±30% around the
center frequency fO. The center frequency is the operating
frequency discussed in the Operating Frequency section.
2.4V
CLP
PLL/LPF
SYNC
DIGITAL
PHASE/
FREQUENCY
DETECTOR
VCO
3813 F13
Figure 13. Phase-Locked Loop Block Diagram
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LTC3813
APPLICATIONS INFORMATION
If the external frequency (fSYNC) is greater than the oscillator frequency fO, current is sourced continuously, pulling up the PLL/LPF pin. When the external frequency is
less than fO, current is sunk continuously, pulling down
the PLL/LPF pin. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. Thus the voltage on the PLL/LPF
pin is adjusted until the phase and frequency of the external
and internal oscillators are identical. At this stable operating
point the phase comparator output is open and the filter
capacitor CLP holds the voltage. The LTC3813 SYNC pin
must be driven from a low impedance source such as a
logic gate located close to the pin.
The loop filter components (CLP, RLP) smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components CLP and RLP determine how fast the loop
acquires lock. Typically RLP = 10kΩ and CLP is 0.01μF
to 0.1μF.
Pin Clearance/Creepage Considerations
The LTC3813 is available in the G28 package which
has 0.0106" spacing between adjacent pins. To
maximize PC board trace clearance between high voltage pins, the LTC3813 has three unconnected pins
between all adjacent high voltage and low voltage
pins, providing 4(0.0106") = 0.042" clearance which
will be sufficient for most applications up to 100V.
For more information, refer to the printed circuit board
design standards described in IPC-2221 (www.ipc.org).
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Although all dissipative
elements in the circuit produce losses, four main sources
account for most of the losses in LTC3813 circuits:
1. DC I2R losses. These arise from the resistances of the
MOSFETs, inductor and PC board traces and cause
the efficiency to drop at high input currents. The input
current is maximum at maximum output current and
minimum input voltage. The average input current flows
through L, but is chopped between the top and bottom
MOSFETs. If the two MOSFETs have approximately the
same RDS(ON), then the resistance of one MOSFET can
simply be summed with the resistances of L and the
board traces to obtain the DC I2R loss. For example, if
RDS(ON) = 0.01Ω and RL = 0.005Ω, the loss will range
from 15mW to 1.5W as the input current varies from
1A to 10A.
2. Transition loss. This loss arises from the brief amount
of time the bottom MOSFET spends in the saturated
region during switch node transitions. It depends upon
the output voltage, load current, driver strength and
MOSFET capacitance, among other factors. The loss
is significant at output voltages above 20V and can be
estimated from the second term of the PMAIN equation found in the Power MOSFET Selection section.
When transition losses are significant, efficiency can
be improved by lowering the frequency and/or using a
bottom MOSFET(s) with lower CRSS at the expense of
higher RDS(ON).
3. INTVCC /DRVCC current. This is the sum of the MOSFET
driver and control currents. Control current is typically
about 3mA and driver current can be calculated by:
IGATE = f(QG(TOP) + QG(BOT) ), where QG(TOP) and QG(BOT)
are the gate charges of the top and bottom MOSFETs.
This loss is proportional to the supply voltage that
INTVCC /DRVCC is derived from, i.e., VIN, VOUT or an
external supply connected to INTVCC /DRVCC.
4. COUT loss. The output capacitor has the difficult job
of filtering the large RMS input current out of the synchronous MOSFET. It must have a very low ESR to
minimize the AC I2R loss.
Other losses, including CIN ESR loss, Schottky diode D1
conduction loss during dead time and inductor core loss
generally account for less than 2% additional loss. When
making adjustments to improve efficiency, the input current is the best indicator of changes in efficiency. If you
make a change and the input current decreases, then the
efficiency has increased. If there is no change in input
current, then there is no change in efficiency.
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APPLICATIONS INFORMATION
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
load step occurs, VOUT immediately shifts by an amount
equal to ΔILOAD (ESR), where ESR is the effective series
resistance of COUT. ΔILOAD also begins to charge or discharge COUT generating a feedback error signal used by the
regulator to return VOUT to its steady-state value. During
this recovery time, VOUT can be monitored for overshoot
or ringing that would indicate a stability problem.
Design Example
As a design example, take a supply with the following specifications: VIN = 12V± 20%, VOUT = 24V ±5%, IOUT(MAX) =
5A, f = 250kHz. Since VIN can vary around the 12V nominal
value, connect a resistive divider from VIN to VOFF to keep
the frequency independent of VIN changes:
R1 12V
=
1= 6.74
R2 1.55V
Choose R1 = 133k and R2 = 20k. Now calculate timing
resistor ROFF :
ROFF =
1+ 133k / 20k
= 402.6k
250kHz • 76pF
The duty cycle is:
D = 1
12V
= 0.5
24V
and the maximum input current is:
IIN(MAX) =
5A
= 10A
1 0.5
Choose the inductor for about 40% ripple current at the
maximum VIN:
L=
The peak inductor current is:
IL(PEAK) =
5A
1
+ (4A) = 12A
1 0.5 2
Choose the CDEP147 5.9μH inductor with ISAT = 16.4A
at 100°C.
Next, choose the bottom MOSFET switch. Since the drain
of the MOSFET will see the full output voltage plus any
ringing, choose a 40V MOSFET to provide a margin of
safety. The Si7848DP has:
BVDSS = 40V
RDS(ON) = 9mΩ(max)/7.5mΩ(nom),
δ = 0.006/°C,
CMILLER = (14nC – 6nC)/20V = 400pF,
VGS(MILLER) = 3.5V,
θJA= 20°C/W.
This yields a nominal sense voltage of:
VSNS(NOM) =
1.7 • 0.0075 • 5A
= 128mV
1 0.5
To guarantee proper current limit at worst-case conditions,
increase nominal VSNS by 50% to 190mV. To check if the
current limit is acceptable at VSNS = 190mV, assume a
junction temperature of about 30°C above a 70°C ambient
(ρ100°C = 1.4):
IIN(MAX)
190mV
1
• 4A = 13A
1.4 • 0.009 2
IOUT(MAX) = IIN(MAX) • (1-DMAX) = 6.5A
and double-check the assumed TJ in the MOSFET:
1
2
PTOP =
6.5A ) (1.4)(0.009) = 1.06W
(
1 0.5
TJ = 70°C + 1.06W • 20°C/W = 91°C
12V
12V
1
= 6μH
250kHz • 0.4 • 10A 24V
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APPLICATIONS INFORMATION
Verify that the Si7848DP is also a good choice for the
bottom MOSFET by checking its power dissipation at
current limit and minimum input voltage, assuming a
junction temperature of 30°C above a 70°C ambient
(ρ100°C = 1.4):
Since VIN is always between 6.2V and 14V, it can be connected directly to the INTVCC and DRVCC pins.
COUT is chosen for an RMS current rating of about 5A at
85°C. The output capacitors are chosen for a low ESR
of 0.018Ω to minimize output voltage changes due to
inductor ripple current and load steps. The ripple voltage
will be only:
2
6.5A
PBOT = 0.5
(1.4) (0.009)
1 0.5
+
1
0.018
VOUT(RIPPLE) = (5A)
+
250kHz • 330μF 1 0.5
= 0.25V (about 1%)
1
6.5A
(24V)2
(2)(400pF)
1 0.5
2
1
1
+
•
(250kHz)
12V 3.5V 3.5V
A 0A to 5A load step will cause an output change of up to:
= 1.06W + 0.30W = 1.36W
ΔVOUT(STEP) = ΔILOAD • ESR = 5A • 0.018Ω
= 90mV
TJ = 70°C + 1.36W • 20°C/W = 97°C
An optional 10μF ceramic output capacitor is included
to minimize the effect of ESL in the output ripple. The
complete circuit is shown in Figure 14.
The junction temperature will be significantly less at
nominal current, but this analysis shows that careful attention to heat sinking on the board will be necessary in
this circuit.
CIN1
68μF
20V
VOUT
133k
ROFF
403k
COFF
100pF
20k
DB
BAS19
LTC3813
BOOST
1 I
OFF
TG
4
5
6
7
8
9
10
PGOOD
RUV1
115k
CSS
1000pF
11
SW
VOFF
VRNG
27
L1
5.9μH
CIN2
1μF
20V
PGND
CB
0.1μF
26
M1
Si7848DP
PGOOD
SYNC
ITH
+ 25
SENSE
21
SENSE–
20
BGRTN
VFB
PLL/LPF
BG
SS
DRVCC
19
18
17
INTVCC
16
EXTVCC
15
NDRV
12
SGND
13
SHDN
14
UVIN
SHDN
28
VIN
12V
SGND
CDRVCC
0.1μF
CVCC
1μF
D1
B1100
VOUT
24V
5A
COUT
330μF
35V
2x
M2
Si7848DP
PGND
CC2
470pF
RUV2
10k
RFB2
1k
RC
250k
CC1
47pF
RFB1
29.4k
3813 F14
Figure 14. 12V Input Voltage to 24V/5A
3813fb
29
LTC3813
APPLICATIONS INFORMATION
PC Board Layout Checklist
When laying out a PC board follow one of two suggested
approaches. The simple PC board layout requires a dedicated ground plane layer. Also, for higher currents, it is
recommended to use a multilayer board to help with heat
sinking power components.
• The ground plane layer should not have any traces and
it should be as close as possible to the layer with power
MOSFETs.
When laying out a printed circuit board, without a ground
plane, use the following checklist to ensure proper operation of the controller.
• Segregate the signal and power grounds. All small
signal components should return to the SGND pin at
one point which is then tied to the PGND pin close to
the source of M2.
• Place M2 as close to the controller as possible, keeping
the PGND, BG and SW traces short.
• Place CIN, COUT, MOSFETs, D1 and inductor all in one
compact area. It may help to have some components
on the bottom side of the board.
• Connect the input capacitor(s) CIN close to the power MOSFETs. This capacitor carries the MOSFET AC
current.
• Use an immediate via to connect the components to
ground plane including SGND and PGND of LTC3813.
Use several bigger vias for power components.
• Keep the high dV/dt SW, BOOST and TG nodes away
from sensitive small-signal nodes.
• Use compact plane for switch node (SW) to improve
cooling of the MOSFETs and to keep EMI down.
• Use planes for VIN and VOUT to maintain good voltage
filtering and to keep power losses low.
• Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
component. You can connect the copper areas to any
DC net (VIN, VOUT, GND or to any other DC rail in your
system).
• Connect the INTVCC decoupling capacitor CVCC closely
to the INTVCC and SGND pins.
• Connect the top driver boost capacitor CB closely to
the BOOST and SW pins.
• Connect the bottom driver decoupling capacitor CDRVCC
closely to the DRVCC and BGRTN pins.
3813fb
30
LTC3813
PACKAGE DESCRIPTION
G Package
28-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
9.90 – 10.50*
(.390 – .413)
28 27 26 25 24 23 22 21 20 19 18 17 16 15
1.25 ±0.12
7.8 – 8.2
5.3 – 5.7
0.42 ±0.03
7.40 – 8.20
(.291 – .323)
0.65 BSC
1 2 3 4 5 6 7 8 9 10 11 12 13 14
RECOMMENDED SOLDER PAD LAYOUT
2.0
(.079)
MAX
5.00 – 5.60**
(.197 – .221)
0° – 8°
0.09 – 0.25
(.0035 – .010)
0.55 – 0.95
(.022 – .037)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
0.65
(.0256)
BSC
0.22 – 0.38
(.009 – .015)
TYP
0.05
(.002)
MIN
G28 SSOP 0204
3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
3813fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
31
LTC3813
TYPICAL APPLICATION
24V Input Voltage to 50V/5A Synchronized at 250kHz
VOUT
RNDRV
100k
ROFF
806k
143k
COFF
100pF
1
10k
4
10k
CSS
1000pF
RUV1
140k
BOOST
19
BG
18
DRVCC
17
INTVCC
16
EXTVCC
15
NDRV
SS
12
SGND
13
SHDN
14
UVIN
SGND
RUV2
10k
CIN2
1μF
50V
PGND
L1
10μH
CB, 0.1μF
M1
Si7850DP
VOUT
50V
5A
25
SENSE+
SENSE– 21
20
BGRTN
11
SHDN
28
27
TG
26
SW
VOFF
5 V
RNG
6
PGOOD
7
SYNC
8
ITH
9
VFB
10
PLL/LPF
PGOOD
250kHz
CLOCK
0.01μF
IOFF
M3
ZXMN10A07F
DB
BAS19
LTC3813
VIN
12V TO 40V
CIN1
68μF
50V
CDRVCC
0.1μF
CVCC
1μF
D1
B1100
M2
Si7850
2x
COUT1
220μF
63V
2x
COUT2
10μF
100V
2x
PGND
CC2
330pF
RFB2
499Ω
RC
300k
CC1
150pF
RFB1
30.9k
3813 TA02
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No RSENSE is a trademark of Linear Technology Corporation.
3813fb
32
Linear Technology Corporation
LT 0408 REV B • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2007
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