LTC3836EGN#TRPBF

LTC3836 Dual 2-Phase, No RSENSETM Low VIN Synchronous Controller FEATURES DESCRIPTION n The LTC®3836 is a 2-phase dual output synchronous step-down switching regulator controller with tracking that drives external N-channel power MOSFETs using few external components. The constant-frequency current mode architecture with MOSFET VDS sensing eliminates the need for sense resistors and improves efficiency. The power loss and noise due to the ESR of the input capacitance are minimized by operating the two controllers out-of-phase. Pulse-skipping operation provides high efficiency at light loads. The 97% duty cycle capability provides low dropout operation, extending operating time in battery-powered systems. n n n n n n n n n n n n n n No Current Sense Resistors Required Out-of-Phase Controllers Reduce Required Input Capacitance All N-Channel Synchronous Drive VIN Range: 2.75V to 4.5V Constant-Frequency Current Mode Operation 0.6V ±1.5% Voltage Reference Low Dropout Operation: 97% Duty Cycle True PLL for Frequency Locking or Adjustment Selectable Pulse-Skipping/Continuous Operation Tracking Function Internal Soft-Start Circuitry Power Good Output Voltage Monitor Output Overvoltage Protection Micropower Shutdown: IQ = 6.5μA Tiny Low Profile (4mm × 5mm) QFN and Narrow SSOP Packages The operating frequency is selectable from 300kHz to 750kHz, allowing the use of small surface mount inductors and capacitors. For noise sensitive applications, the LTC3836 operating frequency can be externally synchronized from 250kHz to 850kHz. APPLICATIONS n n n The LTC3836 features an internal 1ms soft-start that can be extended with an external capacitor. A tracking input allows the second output to track the first during start-up. General Purpose 3.3V to 1.X Supplies Single Lithium-Ion Powered Devices Distributed DC Power Systems The LTC3836 is available in the tiny thermally enhanced (4mm × 5mm) QFN and 28-lead narrow SSOP packages. L, LT, LTC, LTM, Linear Technology, Burst Mode, OPTI-LOOP and the Linear logo are registered trademarks and No RSENSE is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5481178, 5929620, 6144194, 6304066, 6498466, 6580258, 6611131. TYPICAL APPLICATION High Efficiency, 2-Phase, Dual Synchronous DC/DC Step-Down Converter 22μF ×3 VIN BOOST1 BOOST2 SENSE1+ SENSE2+ 80 TG2 SW1 0.47μH SW2 LTC3836 BG1 VOUT1 1.8V AT 15A BG2 PGND 118k 820pF 100μF ×2 59k 15k VFB2 ITH2 VFB1 ITH1 SGND 59k 820pF 59k 15k 70 3.3V-1.2V EFFICIENCY 100μF ×2 3836 TA01 1000 60 50 100 3.3V-1.2V POWER LOSS 40 30 VOUT2 1.2V AT 15A 10000 3.3V-1.8V EFFICIENCY 90 EFFICIENCY (%) 0.47μH 100 20 3.3V-1.8V POWER LOSS POWER LOSS (mW) TG1 Efficiency/Power Loss vs Load Current VIN 3.3V 10 10 0 10 CIRCUIT OF FIGURE 15 100 1000 10000 LOAD CURRENT (mA) 1 100000 3836 TA01b 3836fb 1 LTC3836 ABSOLUTE MAXIMUM RATINGS (Note 1) BOOST1, BOOST2 Voltages ....................... –0.3V to 10V Input Supply Voltage (VIN) ........................ –0.3V to 4.5V PLLLPF, RUN/SS, SYNC/FCB, SENSE1+, SENSE2+, IPRG1, IPRG2 Voltages..................–0.3V to (VIN + 0.3V) VFB1, VFB2, ITH1, ITH2 , TRACK/SS2 Voltages ................................ –0.3V to 2.4V SW1, SW2 Voltages ............................... –2V to VIN + 1V PGOOD....................................................... –0.3V to 10V Operating Temperature Range (Note 2).... –40°C to 85°C Storage Temperature Range................... –65°C to 125°C Junction Temperature (Note 3) ............................. 125°C PIN CONFIGURATION TOP VIEW 26 PGND 8 VIN 9 23 TG1 22 PGND VFB2 11 18 N/C ITH2 12 17 PGND PGOOD 13 SW2 14 18 TG2 17 RUN/SS VIN 6 20 RUN/SS 19 BG2 19 PGND 29 SGND 5 21 TG2 TRACK/SS2 10 20 TG1 PLLLPF 4 TRACK/SS2 7 16 N/C VFB2 8 15 BG2 9 10 11 12 13 14 16 BOOST2 + 15 SENSE2 GN PACKAGE 28-LEAD PLASTIC SSOP PGND SGND 21 SYNC/FCB IPRG2 3 BOOST2 7 24 SYNC/FCB SENSE2+ PLLLPF 6 22 BG1 ITH1 2 SW2 IPRG2 5 25 BG1 ITH2 ITH1 4 28 27 26 25 24 23 VFB1 1 PGOOD VFB1 PGND 27 BOOST1 3 BOOST1 2 SENSE1+ N/C IPRG1 SW1 28 SENSE1+ N/C 1 IPRG1 TOP VIEW SW1 UFD PACKAGE 28-LEAD (4mm × 5mm) PLASTIC QFN TJMAX = 125°C, θJA = 43°C/W EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB TJMAX = 125°C, θJA = 90°C/W ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3836EGN#PBF LTC3836EGN#TRPBF LTC3836EGN 28-Lead Plastic SSOP –40°C to 85°C LTC3836EUFD#PBF LTC3836EUFD#TRPBF 3836 28-Lead (4mm × 5mm) Plastic QFN –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 3.3V unless otherwise specified. PARAMETER CONDITIONS MIN TYP MAX UNITS 450 6.5 4 700 15 10 μA μA μA Main Control Loops Input DC Supply Current Normal Mode Shutdown UVLO (Note 4) RUN/SS = VIN RUN/SS = 0V VIN = UVLO Threshold –200mV 3836fb 2 LTC3836 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 3.3V unless otherwise specified. PARAMETER CONDITIONS Undervoltage Lockout Threshold VIN Falling VIN Rising l l Shutdown Threshold at RUN/SS MIN TYP MAX UNITS 1.95 2.15 2.25 2.45 2.55 2.75 V V 0.45 0.65 0.85 V 0.4 0.65 1 μA 0.591 0.6 0.609 V Start-Up Current Source RUN/SS = 0V Regulated Feedback Voltage –40°C to 85°C (Note 5) Output Voltage Line Regulation 2.75V < VIN < 4.5V (Note 5) 0.05 0.2 mV/V Output Voltage Load Regulation ITH = 0.9V (Note 5) ITH = 1.7V 0.12 –0.12 0.5 –0.5 % % VFB1,2 Input Current (Note 5) 10 50 nA TRACK/SS2 Input Current TRACK/SS2 = 0V 1 1.5 2.2 μA Overvoltage Protect Threshold Measured at VFB 0.66 0.68 0.7 V l Overvoltage Protect Hysteresis 20 0.525 Auxiliary Feedback Threshold SYNC/FCB Ramping Positive Top Gate (TG) Drive 1, 2 Rise Time CL = 3000pF 40 ns Top Gate (TG) Drive 1, 2 Fall Time CL = 3000pF 40 ns Bottom Gate (BG) Drive 1, 2 Rise Time CL = 3000pF 50 ns Bottom Gate (BG) Drive 1, 2 Fall Time CL = 3000pF 40 ns l l l Maximum Current Sense Voltage (∆VSENSE(MAX)) IPRG = Floating (SENSE+ – SW) IPRG = 0V IPRG = VIN 110 70 185 0.6 mV 122 82 202 0.675 135 95 220 97 V mV mV mV Maximum Duty Cycle In Dropout % Soft-Start Time Time for VFB1 to Ramp from 0.05V to 0.55V 0.6 0.8 1 ms Unsynchronized (SYNC/FCB Not Clocked) PLLLPF = Floating PLLLPF = 0V PLLLPF = VIN 480 260 650 550 300 750 600 340 825 kHz kHz kHz 200 1150 250 850 kHz kHz Oscillator and Phase-Locked Loop Oscillator Frequency Phase-Locked Loop Lock Range Phase Detector Output Current Sinking Sourcing SYNC/FCB Clocked Minimum Synchronizable Frequency Maximum Synchronizable Frequency l l fOSC > fSYNC/FCB fOSC > fSYNC/FCB –4 4 μA μA PGOOD Voltage Low IPGOOD Sinking 1mA 140 mV PGOOD Trip Level VFB with Respect to Set Output Voltage VFB < 0.6V, Ramping Positive VFB < 0.6V, Ramping Negative VFB > 0.6V, Ramping Negative VFB > 0.6V, Ramping Positive PGOOD Output Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3836 is guaranteed to meet specified performance from 0°C to 85°C. Specifications over the –40°C to 85°C operating range are assured by design, characterization and correlation with statistical process controls. –13 –16 7 10 –10.0 –13.3 10.0 13.3 –7 –10 13 16 % % % % Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: TJ = TA + (PD • θJA°C/W) Note 4: Dynamic supply current is higher due to gate charge being delivered at the switching frequency. Note 5: The LTC3836 is tested in a feedback loop that servos ITH to a specified voltage and measures the resultant VFB voltage. Note 6: Peak current sense voltage is reduced dependent on duty cycle to a percentage of value as shown in Figure 1. 3836fb 3 LTC3836 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise noted. Load Step (Pulse-Skipping Mode) Load Step (Forced Continuous Mode) Efficiency vs Load Current 100 90 EFFICIENCY (%) 80 VOUT AC COUPLED 100mV/DIV VOUT AC COUPLED 100mV/DIV INDUCTOR CURRENT 5A/DIV INDUCTOR CURRENT 5A/DIV PULSE-SKIPPING MODE 70 60 FORCED CONTINUOUS MODE 50 40 30 20 100μs/DIV VIN = 3.6V VOUT = 1.8V CONTINUOUS MODE: 400mA TO 4A CIRCUIT OF FIGURE 15 SYNC/FCB = VIN SYNC/FCB = 0V 1 100 1000 10 LOAD CURRENT (mA) VIN = 3.3V VOUT = 1.5V CIRCUIT OF FIGURE 15 10000 3836 G03 3836 G01 Light Load (Pulse-Skipping Mode) Light Load (Forced Continuous Mode) VSW 2V/DIV VSW 2V/DIV VOUT 20mV/DIV AC COUPLED VOUT 20mV/DIV AC COUPLED INDUCTOR CURRENT 5A/DIV INDUCTOR CURRENT 5A/DIV VIN = 3.6V 2μs/DIV VOUT = 1.8V ILOAD = 300mA CIRCUIT OF FIGURE 15 100μs/DIV VIN = 3.6V VOUT = 1.8V PULSE-SKIPPING MODE: 400MA TO 4A CIRCUIT OF FIGURE 15 3836 G02 3836 G04 VOUT1 1.8V VOUT2 1.2V 500mV/DIV 2μs/DIV VIN = 3.6V VOUT = 1.8V ILOAD = 300mA CIRCUIT OF FIGURE 15 Tracking Start-Up with External Soft-Start (CRUN/SS = 0.01μF) Tracking Start-Up with Internal Soft-Start (CRUN/SS = 0μF) 3836 G05 250μs/DIV VIN = 3.6V RLOAD1 = RLOAD2 = 1Ω CIRCUIT OF FIGURE 15 3836 G06 Oscillator Frequency vs Input Voltage Sequential Start-Up VOUT1 1.8V VOUT1 1.8V VOUT2 1.2V 500mV/DIV VOUT2 1.2V 500mV/DIV 2.50ms/DIV VIN = 3.6V RLOAD1 = RLOAD2 = 1Ω CIRCUIT OF FIGURE 15 3836 G07 VIN = 3.3V 4ms/DIV RLOAD1 = RLOAD2 = 1Ω VOUT1: INTERNAL SOFT-START VOUT2: CTRACK/SS = 0.047μF CIRCUIT OF FIGURE 15 3836 G10 NORMALIZED FREQUENCY SHIFT (%) 5 4 3 2 1 0 –1 –2 –3 –4 –5 2.5 3.0 4.0 3.5 INPUT VOLTAGE (V) 4.5 3836 G08 3836fb 4 LTC3836 TYPICAL PERFORMANCE CHARACTERISTICS Regulated Feedback Voltage vs Temperature Maximum Current Sense Voltage vs ITH Pin Voltage FORCED CONTINUOUS MODE PULSE-SKIPPING MODE 0.606 1.0 0.605 0.9 0.604 FEEDBACK VOLTAGE (V) CURRENT LIMIT (%) 80 Shutdown (RUN/SS) Threshold vs Temperature 60 40 20 0 0.8 0.603 RUN/SS VOLTAGE (V) 100 TA = 25°C unless otherwise noted. 0.602 0.601 0.600 0.599 0.598 0.597 0.5 1 1.5 ITH VOLTAGE (V) 2 80 0 –60 –40 –20 0 20 40 60 TEMPERATURE (°C) 100 0.9 0.8 0.7 0.6 0.5 80 135 Oscillator Frequency vs Temperature 10 IPRG = FLOAT 130 125 120 115 –60 –40 –20 0 20 40 60 TEMPERATURE (°C) 4 2 0 –2 –4 –6 80 –10 –60 –40 –20 0 20 40 60 TEMPERATURE (°C) 100 Shutdown Quiescent Current vs Input Voltage 18 2.45 16 SHUTDOWN CURRENT (μA) 2.35 2.30 VIN FALLING 2.25 2.20 2.15 0.9 14 12 10 8 6 4 2 100 3836 G16 0 2.5 3.0 3.5 4.0 INPUT VOLTAGE (V) 100 RUN/SS Start-Up Current vs Input Voltage RUN/SS PIN PULL-UP CURRENT (μA) 2.50 80 3836 G15 3836 G14 Undervoltage Lockout Threshold vs Temperature 80 6 –8 3836 G13 VIN RISING 100 8 100 2.40 80 3836 G12 NROMALIZED FREQUENCY (%) MAXIMUM CURRENT SENSE THRESHOLD (mV) RUN/SS PULL-UP CURRENT (μA) 0.3 Maximum Current Sense Threshold vs Temperature 1.0 INPUT (VIN) VOLTAGE (V) 0.4 3836 G11 RUN/SS Pull-Up Current vs Temperature 2.10 20 40 60 –60 –40 –20 0 TEMPERATURE (°C) 0.5 0.1 0.594 20 40 60 –60 –40 –20 0 TEMPERATURE (°C) 3836 G09 0.4 20 40 60 –60 –40 –20 0 TEMPERATURE (°C) 0.6 0.2 0.596 0.595 –20 0.7 4.5 3836 G17 RUN/SS = 0V 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 2.5 3.0 3.5 4.0 INPUT VOLTAGE (V) 4.5 3836 G18 3836fb 5 LTC3836 PIN FUNCTIONS (GN Package)/(UFD Package) SW1/SW2 (Pins 1, 14)/(Pins 26, 11): Switch Node Connection to Inductor and External MOSFETs. Also the negative input to differential peak current comparator and an input to the reverse current comparator. Normally connected to the source of the main MOSFET, the drain of the synchronous MOSFET, and the inductor. NC (Pins 2, 18)/(Pins 16, 28): No Connection. IPRG1/IPRG2 (Pins 3, 6)/(Pins 27, 3): Three-State Pins to Select Maximum Peak Sense Voltage Threshold. These pins select the maximum allowed voltage drop between the SENSE+ and SW pins (i.e., the maximum allowed drop across the external main MOSFET) for each channel. Tie to VIN, GND or float to select 202mV, 82mV, or 122mV respectively. VFB1/VFB2 (Pins 4, 11)/(Pins 1, 8): Feedback Pins. Receives the remotely sensed feedback voltage for its controller from an external resistor divider across the output. ITH1/ITH2 (Pins 5, 12)/(Pins 2, 9): Current Threshold and Error Amplifier Compensation Point. Nominal operating range on these pins is from 0.7V to 2V. The voltage on these pins determines the threshold of the main current comparator. PLLLPF (Pin 7)/(Pin 4): Frequency Set/PLL Lowpass Filter. When synchronizing to an external clock, this pin serves as the lowpass filter point for the phase-locked loop. Normally a series RC is connected between this pin and ground. When not synchronizing to an external clock, this pin serves as the frequency select input. Tying this pin to GND selects 300kHz operation; tying this pin to VIN selects 750kHz operation. Floating this pin selects 550kHz operation. SGND (Pin 8)/(Pin 5): Small-Signal Ground. This pin serves as the ground connection for most internal circuits. VIN (Pin 9)/(Pin 6): Small-Signal Power Supply. This pin powers the entire chip except for the gate drivers. Externally filtering this pin with a lowpass RC network (e.g., R = 10Ω, C = 1μF) is suggested to minimize noise pickup, especially in high load current applications. TRACK/SS2 (Pin 10)/(Pin 7): Channel 2 Tracking and SoftStart Input. The LTC3836 regulates the VFB2 voltage to the smaller of 0.6V or the voltage on the TRACK/SS2 pin. An internal 1.5μA pull-up current source is connected to this pin. A capacitor to ground at this pin sets the ramp time to final regulated output voltage. Alternatively, a resistor divider on another voltage supply connected to this pin allows the LTC3836 output to track the other supply during start-up. PGOOD (Pin 13)/(Pin 10): Power-Good Output Voltage Monitor Open-Drain Logic Output. This pin is pulled to ground when the voltage on either feedback pin (VFB1, VFB2) is not within ±13.3% of its nominal set point. PGND (Pins 17, 22, 26)/(Pins 14, 19, 23): Power Ground. These pins serve as the ground connection for the gate drivers and the negative input to the reverse current comparators. The Exposed Pad must be soldered to PCB ground. RUN/SS (Pin 20)/(Pin 17): Run Control Input and Optional External Soft-Start Input. Forcing this pin below 0.65V shuts down the chip (both channels). Driving this pin to VIN or releasing this pin enables the chip, using the chip’s internal soft-start. An external soft-start can be programmed by connecting a capacitor between this pin and ground. TG1/TG2 (Pins 23, 21)/(Pins 20, 18): Top Gate Drive Output. These pins drive the gates of the external topside MOSFETs. These pins have an output swing from PGND to BOOST. SYNC/FCB (Pin 24)/(Pin 21): This pin performs two functions: 1) external clock synchronization input for phase-locked loop, and 2) pulse-skipping operation or forced continuous mode select. To synchronize with an external clock using the PLL, apply a CMOS compatible clock with a frequency between 250kHz and 850kHz. To select pulse-skipping operation at light loads, tie this pin to VIN. Grounding this pin selects forced continuous operation, which allows the inductor current to reverse. When synchronized to an external clock, pulse-skipping operation is enabled at light loads. BG1/BG2 (Pins 25, 19)/(Pins 22, 15): Bottom Gate Drive Output. These pins drive the gates of the external synchronous MOSFETs. These pins have an output swing from PGND to BOOST. 3836fb 6 LTC3836 PIN FUNCTIONS (GN/UFD Package) BOOST1/BOOST2 (Pins 27, 16)/(Pins 24, 13): Positive Supply Pin for the Gate Driver Circuitry. A bootstrapped capacitor, charged with an external Schottky diode and a boost voltage source, is connected between the BOOST and SW pins. Voltage swing at the BOOST pins is from boost source voltage (typically VIN) to this boost source voltage + VIN. FUNCTIONAL DIAGRAM Exposed Pad (Pin 29) UFD Package Only: Must be soldered to PCB ground. (Common Circuitry) RVIN VIN UNDERVOLTAGE LOCKOUT SENSE1+/SENSE2+ (Pins 28, 5)/(Pins 25, 12): Positive Input to Differential Current Comparator. Also powers the gate drivers. Normally connected to the drain of the main external MOSFET. VIN (TO CONTROLLER 1, 2) CVIN VOLTAGE REFERENCE 0.6V VREF 0.65μA SHDN RUN/SS EXTSS + tSEC = 1ms INTSS – SYNC/FCB PHASE DETECTOR SYNC DETECT PLLLPF VOLTAGE CONTROLLED OSCILLATOR CLK1 SLOPE COMP CLK2 – 0.6V + VFB1 FCB SLOPE1 SLOPE2 – UV1 FCB + PGOOD OV1 SHDN 0.54V + UV2 VFB2 OV2 37362 FD – 3836fb 7 LTC3836 FUNCTIONAL DIAGRAM (Controller 1) BOOST1 VIN SENSE1+ CIN RS1 CLK1 S CB TG1 Q R SWITCHING LOGIC AND BLANKING CIRCUIT OV1 SC1 FCB PGND SW1 ANTISHOOT THROUGH L1 VOUT1 BOOST1 COUT1 BG1 PGND IREV1 SLOPE1 SW1 – ICMP SENSE1+ + IPRG1 SHDN – + VFB1 R1B EAMP + R1A – 0.6V ITH1 EXTSS INTSS RITH1 SC1 OV1 + VFB1 – 0.68V IREV1 OVP + 0.12V – VFB1 – PGND CITH1 SCP RICMP + IPROG1 FCB SW1 3836 FD2 3836fb 8 LTC3836 FUNCTIONAL DIAGRAM (Controller 2) BOOST2 VIN SENSE2+ CIN RS2 CLK2 S CB TG2 Q R SWITCHING LOGIC AND BLANKING CIRCUIT OV2 SC2 FCB PGND SW2 ANTISHOOT THROUGH L2 VOUT2 BOOST2 COUT2 BG2 PGND IREV2 SLOPE2 SW2 – ICMP SENSE2+ + SHDN + EAMP + – IPRG2 R2B VFB2 0.60V R2A – VOUT1 1μA TRACK/SS2 RTRACKB RTRACKA SHDN ITH2 RITH2 SC2 + 0.12V – VFB2 – PGND + SW2 CITH2 SCP TRACK + OV2 VFB2 IREV2 OVP – 0.68V 3836 FD3 FCB 3836fb 9 LTC3836 OPERATION (Refer to Functional Diagram) Main Control Loop The LTC3836 uses a constant-frequency, current mode architecture with the two controllers operating 180 degrees out-of-phase. During normal operation, the top external power MOSFET is turned on when the clock for its channel sets the RS latch, and turned off when the current comparator (ICMP) resets the latch. The peak inductor current at which ICMP resets the RS latch is determined by the voltage on the ITH pin, which is driven by the output of the error amplifier (EAMP). The VFB pin receives the output voltage feedback signal from an external resistor divider. This feedback signal is compared to the internal 0.6V reference voltage by the EAMP. When the load current increases, it causes a slight decrease in VFB relative to the 0.6V reference, which in turn causes the ITH voltage to increase until the average inductor current matches the new load current. While the top N-channel MOSFET is off, the bottom N-channel MOSFET is turned on until either the inductor current starts to reverse, as indicated by the current reversal comparator, IRCMP, or the beginning of the next cycle. Shutdown, Soft-Start and Tracking Start-Up (RUN/SS and TRACK/SS2 Pins) The LTC3836 is shut down by pulling the RUN/SS pin low. In shutdown, all controller functions are disabled and the chip draws only 6.5μA. The TG and BG outputs are held low (off) in shutdown. Releasing RUN/SS allows an internal 0.65μA current source to charge up the RUN/SS pin. When the RUN/SS pin reaches 0.65V, the LTC3836’s two controllers are enabled. The start-up of VOUT1 is controlled by the LTC3836’s internal soft-start. During soft-start, the error amplifier EAMP compares the feedback signal VFB1 to the internal soft-start ramp (instead of the 0.6V reference), which rises linearly from 0V to 0.6V in about 1ms. This allows the output voltage to rise smoothly from 0V to its final value, while maintaining control of the inductor current. The 1ms soft-start time can be increased by connecting the optional external soft-start capacitor CSS between the RUN/SS and SGND pins. As the RUN/SS pin continues to rise linearly from approximately 0.65V to 1.3V (being charged by the internal 0.65μA current source), the EAMP regulates the VFB1 proportionally from 0V to 0.6V. The start-up of VOUT2 is controlled by the voltage on the TRACK/SS2 pin. When the voltage on the TRACK/SS2 pin is less than the 0.6V internal reference, the LTC3836 regulates the VFB2 voltage to the TRACK/SS2 pin voltage instead of the 0.6V reference. This allows the TRACK/SS2 pin to be used to program a soft-start by connecting an external capacitor from the TRACK/SS2 pin to SGND. An internal 1μA pull-up current charges this capacitor, creating a voltage ramp on the TRACK/SS2 pin. As the TRACK/SS2 voltage rises linearly from 0V to 0.6V (and beyond), the output voltage VOUT2 rises smoothly from zero to its final value. Alternatively, the TRACK/SS2 pin can be used to cause the start-up of VOUT2 to “track” that of another supply. Typically, this requires connecting to the TRACK/SS2 pin an external resistor divider from the other supply to ground (see Applications Information section). When the RUN/SS pin is pulled low to disable the LTC3836, or when VIN drops below its undervoltage lockout threshold, the TRACK/SS2 pin is pulled low by an internal MOSFET. When in undervoltage lockout, both controllers are disabled and the external MOSFETs are held off. Light Load Operation (Pulse-Skipping or Continuous Conduction) (SYNC/FCB Pin) The LTC3836 can be enabled to enter high efficiency pulseskipping operation or forced continuous conduction mode at low load currents. To select pulse-skipping operation, tie the SYNC/FCB pin to a DC voltage above 0.6V (e.g., VIN). To select forced continuous operation, tie the SYNC/FCB to a DC voltage below 0.6V (e.g., SGND). In forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. The peak inductor current is determined by the voltage on the ITH pin. The main N-channel MOSFET is turned on every cycle (constant-frequency) regardless of the ITH pin voltage. In this mode, the efficiency at light loads is lower than in pulse-skipping operation. However, continuous mode has the advantages of lower output ripple and less interference with audio circuitry. 3836fb 10 LTC3836 OPERATION (Refer to Functional Diagram) When the SYNC/FCB pin is tied to a DC voltage above 0.6V or when it is clocked by an external clock source to use the phase-locked loop (see Frequency Selection and Phase-Locked Loop), the LTC3836 operates in PWM pulse-skipping mode at light loads. In this mode, the current comparator ICMP may remain tripped for several cycles and force the main N-channel MOSFET to stay off for the same number of cycles. The inductor current is not allowed to reverse, though (discontinuous operation). This mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced RF interference. However, it provides low current efficiency higher than forced continuous mode. During start-up or a short-circuit condition (VFB1 or VFB2 ≤ 0.54V), the LTC3836 operates in pulse-skipping mode (no current reversal allowed), regardless of the state of the SYNC/FCB pin. Short-Circuit Protection When an output is shorted to ground (VFB < 0.12V), the switching frequency of that controller is reduced to onefifth of the normal operating frequency. The other controller maintains regulation in pulse-skipping mode. The short-circuit threshold on VFB2 is based on the smaller of 0.12V and a fraction of the voltage on the TRACK/SS2 pin. This also allows VOUT2 to start up and track VOUT1 more easily. Note that if VOUT1 is truly short-circuited (VOUT1 = VFB1 = 0V), then the LTC3836 will try to regulate VOUT2 to 0V if a resistor divider on VOUT1 is connected to the TRACK/SS pin. Frequency Selection and Phase-Locked Loop (PLLLPF and SYNC/FCB Pins) The selection of switching frequency is a tradeoff between efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. The switching frequency of the LTC3836’s controllers can be selected using the PLLLPF pin. If the SYNC/FCB is not being driven by an external clock source, the PLLLPF can be floated, tied to VIN or tied to SGND to select 550kHz, 750kHz or 300kHz respectively. A phase-locked loop (PLL) is available on the LTC3836 to synchronize the internal oscillator to an external clock source that is connected to the SYNC/FCB pin. In this case, a series RC should be connected between the PLLLPF pin and SGND to serve as the PLL’s loop filter. The LTC3836 phase detector adjusts the voltage on the PLLLPF pin to align the turn-on of controller 1’s top MOSFET to the rising edge of the synchronizing signal. Thus, the turn-on of controller 2’s top MOSFET is 180 degrees out-of-phase with the rising edge of the external clock source. The typical capture range of the LTC3836’s phase-locked loop is from approximately 200kHz to 1MHz, and is guaranteed over temperature between 250kHz and 850kHz. In other words, the LTC3836’s PLL is guaranteed to lock to an external clock source whose frequency is between 250kHz and 850kHz. Output Overvoltage Protection Dropout Operation As a further protection, the overvoltage comparator (OV) guards against transient overshoots, as well as other more serious conditions that may overvoltage the output. When the feedback voltage on the VFB pin has risen 13.33% above the reference voltage of 0.6V, the main N-channel MOSFET is turned off and the synchronous N-channel MOSFET is turned on until the overvoltage is cleared. Each top MOSFET driver is biased from the floating bootstrap capacitor CB, which normally recharges during each off cycle through an external diode when the top MOSFET turns off. If the input voltage VIN decreases to a voltage close to VOUT, the loop may enter dropout and attempt to turn on the top MOSFET continuously. The dropout detector detects this and forces the top MOSFET off for about 200ns every fourth cycle to allow CB to recharge. 3836fb 11 LTC3836 OPERATION (Refer to Functional Diagram) Undervoltage Lockout 110 100 Peak Current Sense Voltage Selection and Slope Compensation (IPRG1 and IPRG2 Pins) When a controller is operating below 20% duty cycle, the peak current sense voltage (between the SENSE+ and SW pins) allowed across the main N-channel MOSFET is determined by:
VSENSE(MAX) = A ( VITH – 0.7V ) 10 where A is a constant determined by the state of the IPRG pins. Floating the IPRG pin selects A = 1; tying IPRG to VIN selects A = 5/3; tying IPRG to SGND selects A = 2/3. The maximum value of VITH is typically about 1.98V, so the maximum sense voltage allowed across the main N-channel MOSFET is 122mV, 202mV, or 82mV for the three respective states of the IPRG pin. The peak sense voltages for the two controllers can be independently selected by the IPRG1 and IPRG2 pins. However, once the controller’s duty cycle exceeds 20%, slope compensation begins and effectively reduces the peak sense voltage by a scale factor given by the curve in Figure 1. The peak inductor current is determined by the peak sense voltage and the on-resistance of the main N-channel MOSFET: IPK =
VSENSE(MAX) RDS(ON) 90 80 SF = I/IMAX (%) To prevent operation of the external MOSFETs below safe input voltage levels, an undervoltage lockout is incorporated in the LTC3836. When the input supply voltage (VIN) drops below 2.25V, the external MOSFETs and all internal circuitry are turned off except for the undervoltage block, which draws only a few microamperes. 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 80 90 100 DUTY CYCLE (%) 37362 F01 Figure 1. Maximum Peak Current vs Duty Cycle Power-Good (PGOOD) Pin A window comparator monitors both feedback voltages and the open-drain PGOOD output pin is pulled low when either or both feedback voltages are not within ±10% of the 0.6V reference voltage. PGOOD is low when the LTC3836 is shut down or in undervoltage lockout. 2-Phase Operation Why the need for 2-phase operation? Many constant-frequency dual switching regulators operate both controllers in phase (i.e., single phase operation). This means that both topside MOSFETs are turned on at the same time, causing current pulses of up to twice the amplitude of those from a single regulator to be drawn from the input capacitor. These large amplitude pulses increase the total RMS current flowing in the input capacitor, requiring the use of larger and more expensive input capacitors, and increase both EMI and power losses in the input capacitor and input power supply. With 2-phase operation, the two controllers of the LTC3836 are operated 180 degrees out-of-phase. This effectively interleaves the current pulses coming from the topside MOSFET switches, greatly reducing the time where they overlap and add together. The result is a significant reduction in the total RMS current, which in turn allows the use of smaller, less expensive input capacitors, reduces shielding requirements for EMI and improves real world operating efficiency. 3836fb 12 LTC3836 OPERATION (Refer to Functional Diagram) Figure 2 shows example waveforms for a single phase dual controller versus a 2-phase LTC3836 system. In this case, two outputs of different voltage, each drawing the same load current are derived from a single input supply. In this example, 2-phase operation could halve the RMS input capacitor current. While this is an impressive reduction by itself, remember that power losses are proportional to IRMS2, meaning that just one-fourth the actual power is wasted. Single Phase Dual Controller 2-Phase Dual Controller SW1 (V) SW2 (V) The reduced input ripple current also means that less power is lost in the input power path, which could include batteries, switches, trace/connector resistances, and protection circuitry. Improvements in both conducted and radiated EMI also directly accrue as a result of the reduced RMS input current and voltage. Significant cost and board footprint savings are also realized by being able to use smaller, less expensive, lower RMS current-rated input capacitors. Of course, the improvement afforded by 2-phase operation is a function of the relative duty cycles of the two controllers, which in turn are dependent upon the input supply voltage. Figure 3 depicts how the RMS input current varies for single phase and 2-phase dual controllers with 2.5V and 1.8V outputs. A good rule of thumb for most applications is that 2-phase operation will reduce the input capacitor requirement to that for just one channel operating at maximum current and 50% duty cycle. INPUT CAPACITOR RMS CURRENT 2.0 IL1 IL2 SINGLE PHASE DUAL CONTROLLER 1.8 1.6 1.4 1.2 1.0 0.8 2-PHASE DUAL CONTROLLER 0.6 0.4 0.2 VOUT1 = 2.5V/2A VOUT2 = 1.8V/2A 0 3.0 IIN 3836 F02 Figure 2. Example Waveforms for a Single Phase Dual Controller vs the 2-Phase LTC3836 4.0 3.5 INPUT VOLTAGE (V) 4.5 3836 F03 Figure 3. RMS Input Current Comparison 3836fb 13 LTC3836 APPLICATIONS INFORMATION The typical LTC3836 application circuit is shown in Figure 13. External component selection for each of the LTC3836’s controllers is driven by the load requirement and begins with the selection of the inductor (L) and the power MOSFETs (M1 to M4). A reasonable starting point is setting ripple current IRIPPLE to be 40% of IOUT(MAX). Rearranging the above equation yields: 5
VSENSE(MAX) RDS(ON)(MAX) = • 6 IOUT(MAX) Power MOSFET Selection for Duty Cycle < 20%. Each of the LTC3836’s two controllers requires two external N-channel power MOSFETs for the topside (main) switch and the bottom (synchronous) switch. Important parameters for the power MOSFETs are the breakdown voltage VBR(DSS), threshold voltage VGS(TH), on-resistance RDS(ON), reverse transfer capacitance CRSS, turn-off delay tD(OFF) and the total gate charge QG. However, for operation above 20% duty cycle, slope compensation has to be taken into consideration to select the appropriate value of RDS(ON) to provide the required amount of load current:
VSENSE(MAX) 5 RDS(ON)(MAX) = • SF • 6 IOUT(MAX) The gate drive voltage is the input supply voltage. Since the LTC3836 is designed for operation down to low input voltages, a sublogic level MOSFET (RDS(ON) guaranteed at VGS = 2.5V) is required for applications that work close to this voltage. where SF is a scale factor whose value is obtained from the curve in Figure 1. The main MOSFET’s on-resistance is chosen based on the required load current. The maximum average output load current IOUT(MAX) is equal to the peak inductor current minus half the peak-to-peak ripple current IRIPPLE . The LTC3836’s current comparator monitors the drain-tosource voltage VDS of the main MOSFET, which is sensed between the SENSE+ and SW pins. The peak inductor current is limited by the current threshold, set by the voltage on the ITH pin of the current comparator. The voltage on the ITH pin is internally clamped, which limits the maximum current sense threshold ∆VSENSE(MAX) to approximately 122mV when IPRG is floating (82mV when IPRG is tied low; 202mV when IPRG is tied high). The output current that the LTC3836 can provide is given by:
VSENSE(MAX) IRIPPLE IOUT(MAX) = – RDS(ON) 2 These must be further derated to take into account the significant variation in on-resistance with temperature. The following equation is a good guide for determining the required RDS(ON)MAX at 25°C (manufacturer’s specification), allowing some margin for variations in the LTC3836 and external component values:
VSENSE(MAX) 5 RDS(ON)(MAX) = • 0.9 • SF • 6 IOUT(MAX) • T The ρT is a normalizing term accounting for the temperature variation in on-resistance, which is typically about 0.4%/°C, as shown in Figure 4. Junction to case temperature TJC is about 10°C in most applications. For a maximum ambient temperature of 70°C, using ρ80°C ≈ 1.3 in the above equation is a reasonable choice. The power dissipated in the top and bottom MOSFETs strongly depends on their respective duty cycles and load current. When the LTC3836 is operating in continuous mode, the duty cycles for the MOSFETs are: VOUT VIN V – VOUT Bottom MOSFET Duty Cycle = IN VIN Top MOSFET Duty Cycle = 3836fb 14 LTC3836 APPLICATIONS INFORMATION The MOSFET power dissipations at maximum output current are: PTOP = VOUT •IOUT(MAX)2 •
T • RDS(ON) + 2 • VIN2 VIN • IOUT(MAX) • CRSS • fOSC PBOT = VIN – VOUT •IOUT(MAX)2 •
T • RDS(ON) VIN Both MOSFETs have I2R losses and the PTOP equation includes an additional term for transition losses, which are largest at high input voltages. The bottom MOSFET losses are greatest at high input voltage or during a short-circuit when the bottom duty cycle is nearly 100%. ρT NORMALIZED ON RESISTANCE 2.0 1.5 Operating Frequency and Synchronization The choice of operating frequency, fOSC, is a trade-off between efficiency and component size. Low frequency operation improves efficiency by reducing MOSFET switching losses, both gate charge loss and transition loss. However, lower frequency operation requires more inductance for a given amount of ripple current. The internal oscillator for each of the LTC3836’s controllers runs at a nominal 550kHz frequency when the PLLLPF pin is left floating and the SYNC/FCB pin is a DC low or high. Pulling the PLLLPF to VIN selects 750kHz operation; pulling the PLLLPF to GND selects 300kHz operation. Alternatively, the LTC3836 will phase-lock to a clock signal applied to the SYNC/FCB pin with a frequency between 250kHz and 850kHz (see Phase-Locked Loop and Frequency Synchronization). Inductor Value Calculation Given the desired input and output voltages, the inductor value and operating frequency fOSC directly determine the inductor’s peak-to-peak ripple current:
V –V  V IRIPPLE = OUT  IN OUT  V  f •L  1.0 0.5 IN 0 –50 50 100 0 JUNCTION TEMPERATURE (°C) 150 3836 F04 Figure 4. RDS(ON) vs Temperature The LTC3836 utilizes a nonoverlapping, antishoot-through gate drive control scheme to ensure that the MOSFETs are not turned on at the same time. To function properly, the control scheme requires that the MOSFETs used are intended for DC/DC switching applications. Many power MOSFETs are intended to be used as static switches and therefore are slow to turn on or off. OSC Lower ripple current reduces core losses in the inductor, ESR losses in the output capacitors, and output voltage ripple. Thus, highest efficiency operation is obtained at low frequency with a small ripple current. Achieving this, however, requires a large inductor. A reasonable starting point is to choose a ripple current that is about 40% of IOUT(MAX). Note that the largest ripple current occurs at the highest input voltage. To guarantee that ripple current does not exceed a specified maximum, the inductor should be chosen according to: V –V V L
IN OUT • OUT fOSC •IRIPPLE VIN 3836fb 15 LTC3836 APPLICATIONS INFORMATION Inductor Core Selection Once the inductance value is determined, the type of inductor must be selected. Core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Schottky Diode Selection (Optional) The Schottky diodes D1 and D2 in Figure 16 conduct current during the dead time between the conduction of the power MOSFETs . This prevents the body diode of the bottom MOSFET from turning on and storing charge during the dead time, which could cost as much as 1% in efficiency. A 1A Schottky diode is generally a good size for most LTC3836 applications, since it conducts a relatively small average current. Larger diodes result in additional transition losses due to their larger junction capacitance. This diode may be omitted if the efficiency loss can be tolerated. CIN and COUT Selection The selection of CIN is simplified by the 2-phase architecture and its impact on the worst-case RMS current drawn through the input network (battery/fuse/capacitor). It can be shown that the worst-case capacitor RMS current occurs when only one controller is operating. The controller with the highest (VOUT)(IOUT) product needs to be used in the formula below to determine the maximum RMS capacitor current requirement. Increasing the output current drawn from the other controller will actually decrease the input RMS ripple current from its maximum value. The out-of- phase technique typically reduces the input capacitor’s RMS ripple current by a factor of 30% to 70% when compared to a single phase power supply solution. In continuous mode, the source current of the main N-channel MOSFET is a square wave of duty cycle (VOUT)/(VIN). To prevent large voltage transients, a low ESR capacitor sized for the maximum RMS current of one channel must be used. The maximum RMS capacitor current is given by: 1/2 I CIN Required IRMS
MAX ( VOUT ) ( VIN – VOUT )  VIN This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturers’ ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may be paralleled to meet size or height requirements in the design. Due to the high operating frequency of the LTC3836, ceramic capacitors can also be used for CIN. Always consult the manufacturer if there is any question. The benefit of the LTC3836 2-phase operation can be calculated by using the equation above for the higher power controller and then calculating the loss that would have resulted if both controller channels switched on at the same time. The total RMS power lost is lower when both controllers are operating due to the reduced overlap of current pulses required through the input capacitor’s ESR. This is why the input capacitor’s requirement calculated above for the worst-case controller is adequate for the dual controller design. Also, the input protection fuse resistance, battery resistance, and PC board trace resistance losses are also reduced due to the reduced peak currents in a 2-phase system. The overall benefit of a multiphase design will only be fully realized when the source impedance of the power supply/battery is included in the efficiency testing. The drains of the main MOSFETs should be placed within 1cm of each other and share a common CIN(s). Separating the drains and CIN may produce undesirable voltage and current resonances at VIN. 3836fb 16 LTC3836 APPLICATIONS INFORMATION A small (0.1μF to 1μF) bypass capacitor between the chip VIN pin and ground, placed close to the LTC3836, is also suggested. A 10Ω resistor placed between CIN (C1) and the VIN pin provides further isolation between the two channels. The selection of COUT is driven by the effective series resistance (ESR). Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering. The output ripple (∆VOUT) is approximated by:  1 
VOUT IRIPPLE  ESR + 8fCOUT   where f is the operating frequency, COUT is the output capacitance and IRIPPLE is the ripple current in the inductor. The output ripple is highest at maximum input voltage since IRIPPLE increases with input voltage. Setting Output Voltage The LTC3836 output voltages are each set by an external feedback resistor divider carefully placed across the output, as shown in Figure 5. The regulated output voltage is determined by:
R  VOUT = 0.6V •  1+ B   RA  RB Run/Soft-Start Function The RUN/SS pin is a dual purpose pin that provides the optional external soft-start function and a means to shut down the LTC3836. Pulling the RUN/SS pin below 0.65V puts the LTC3836 into a low quiescent current shutdown mode (IQ = 6.5μA). If RUN/SS has been pulled all the way to ground, there will be a delay before the LTC3836 comes out of shutdown and is given by: C tDELAY = 0.65V • SS = 1s/μF • CSS 0.65μA This pin can be driven directly from logic as shown in Figure 6. Diode DSS in Figure 6 reduces the start delay but allows CSS to ramp up slowly providing the soft-start function. This diode (and capacitor) can be deleted if the external soft-start is not needed. 3.3V OR 5V RUN/SS RUN/SS DSS CSS VOUT 1/2 LTC3836 To improve the frequency response, a feedforward capacitor, CFF, may be used. Great care should be taken to route the VFB line away from noise sources, such as the inductor or the SW line. CSS CFF VDD ≤ VIN VFB RUN/SS (INTERNAL SOFT-START) RA 3836 F05 3836 F06 Figure 5. Setting Output Voltage Figure 6. RUN/SS Pin Interfacing 3836fb 17 LTC3836 APPLICATIONS INFORMATION During soft-start, the start-up of VOUT1 is controlled by slowly ramping the positive reference to the error amplifier from 0V to 0.6V, allowing VOUT1 to rise smoothly from 0V to its final value. The default internal soft-start time is 1ms. This can be increased by placing a capacitor between the RUN/SS pin and SGND. In this case, the soft-start time will be approximately: t SS1 = CSS • 600mV 0.65μA regulates the VFB2 voltage to the TRACK/SS2 pin voltage instead of 0.6V. The start-up of VOUT2 may ratiometrically track that of VOUT1, according to a ratio set by a resistor divider (Figure 7c): VOUT1 + R TRACKB R R2A = • TRACKA VOUT2 R TRACKA R2B + R2A For coincident tracking (VOUT1 = VOUT2 during start-up), R2A = RTRACKA Tracking The start-up of VOUT2 is controlled by the voltage on the TRACK/SS2 pin. Normally this pin is used to allow the startup of VOUT2 to track that of VOUT1 as shown qualitatively in Figures 7a and 7b. When the voltage on the TRACK/SS2 pin is less than the internal 0.6V reference, the LTC3836 R2B = RTRACKB The ramp time for VOUT2 to rise from 0V to its final value is: + R TRACKB R 0.6 t SS2 = t SS1 • • TRACKA VOUT1F R TRACKA VOUT1 R1B VOUT2 LTC3836 VFB1 R2B VFB2 R1A R2A RTRACKB TRACK/SS2 3836 F07a RTRACKA Figure 7a. Using the TRACK/SS Pin VOUT2 VOUT1 OUTPUT VOLTAGE OUTPUT VOLTAGE VOUT1 VOUT2 3836 F07b_c TIME TIME (7b) Coincident Tracking (7c) Ratiometric Tracking Figures 7b and 7c. Two Different Modes of Output Voltage Tracking 3836fb 18 LTC3836 APPLICATIONS INFORMATION For coincident tracking, V t SS2 = t SS1 • OUT2F VOUT1F and internal oscillators. This type of phase detector does not exhibit false lock to harmonics of the external clock. where VOUT1F and VOUT2F are the final, regulated values of VOUT1 and VOUT2. VOUT1 should always be greater than VOUT2 when using the TRACK/SS2 pin for tracking. If no tracking function is desired, then the TRACK/SS2 pin may be tied to a capacitor to ground, which sets the ramp time to final regulated output voltage. Phase-Locked Loop and Frequency Synchronization The LTC3836 has a phase-locked loop (PLL) comprised of an internal voltage-controlled oscillator (VCO) and a phase detector. This allows the turn-on of the main N-channel MOSFET of controller 1 to be locked to the rising edge of an external clock signal applied to the SYNC/FCB pin. The turn-on of controller 2’s main N-channel MOSFET is thus 180 degrees out-of-phase with the external clock. The phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external The output of the phase detector is a pair of complementary current sources that charge or discharge the external filter network connected to the PLLLPF pin. The relationship between the voltage on the PLLLPF pin and operating frequency, when there is a clock signal applied to SYNC/ FCB, is shown in Figure 8 and specified in the Electrical Characteristics table. Note that the LTC3836 can only be synchronized to an external clock whose frequency is within range of the LTC3836’s internal VCO, which is nominally 200kHz to 1MHz. This is guaranteed, over temperature and variations, to be between 300kHz and 750kHz. A simplified block diagram is shown in Figure 9. If the external clock frequency is greater than the internal oscillator’s frequency, fOSC, then current is sourced continuously from the phase detector output, pulling up the PLLLPF pin. When the external clock frequency is less than fOSC, current is sunk continuously, pulling down the PLLLPF pin. If the external and internal frequencies 1400 1200 2.4V RLP FREQUENCY (kHz) 1000 CLP 800 SYNC/ FCB 600 EXTERNAL OSCILLATOR 400 PLLLPF DIGITAL PHASE/ FREQUENCY DETECTOR OSCILLATOR 200 0 0 0.5 1 1.5 2 PLLLPF PIN VOLTAGE (V) 2.4 3836 F09 3836 F08 Figure 8. Relationship Between Oscillator Frequency and Voltage at the PLLLPF Pin When Synchronizing to an External Clock Figure 9. Phase-Locked Loop Block Diagram 3836fb 19 LTC3836 APPLICATIONS INFORMATION are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. The voltage on the PLLLPF pin is adjusted until the phase and frequency of the internal and external oscillators are identical. At the stable operating point, the phase detector output is high impedance and the filter capacitor CLP holds the voltage. 5V supply is available. Note that in applications where the supply voltage to CB exceeds VIN , the BOOST pin will draw approximately 500μA in shutdown mode. The loop filter components, CLP and RLP, smooth out the current pulses from the phase detector and provide a stable input to the voltage-controlled oscillator. The filter components CLP and RLP determine how fast the loop acquires lock. Typically RLP = 10k and CLP is 2200pF to 0.01μF. SYNC/FCB PIN CONDITION 0V to 0.5V Forced Continuous Mode Current Reversal Allowed 0.7V to VIN Pulse-Skipping Operation Enabled No Current Reversal Allowed External Clock Signal Enable Phase-Locked Loop (Synchronize to External CLK) Pulse-Skipping at Light Loads No Current Reversal Allowed Table 2 summarizes the different states in which the SYNC/FCB pin can be used Table 2. Typically, the external clock (on SYNC/FCB pin) input high level is 1.6V, while the input low level is 1.2V. Table 1 summarizes the different states in which the PLLLPF pin can be used. Table 1. PLLLPF PIN SYNC/FCB PIN FREQUENCY 0V DC Voltage 300kHz Floating DC Voltage 550kHz VIN DC Voltage 750kHz RC Loop Filter Clock Signal Phase-Locked to External Clock Fault Condition: Short-Circuit and Current Limit To prevent excessive heating of the bottom MOSFET, foldback current limiting can be added to reduce the current in proportion to the severity of the fault. Foldback current limiting is implemented by adding diodes DFB1 and DFB2 between the output and the ITH pin as shown in Figure 11. In a hard short (VOUT = 0V), the current will be reduced to approximately 50% of the maximum output current. Topside MOSFET Drive Supply (CB, DB) In the Functional Diagram, external bootstrap capacitor CB is charged from a boost power source (usually VIN) through diode DB when the SW node is low. When a MOSFET is to be turned on, the CB voltage is applied across the gate-source of the desired device. When the topside MOSFET is on, the BOOST pin voltage is above the input supply. VBOOST = 2VIN. CB must be 100 times the total input capacitance of the topside MOSFET. The reverse breakdown of DB must be greater than VIN(MAX). Figure 6 shows how a 5V gate drive can be achieved if a secondary VOUT 1/2 LTC3836 ITH R2 + DFB1 VFB R1 DFB2 3836 F11 Figure 11. Foldback Current Limiting 3836fb 20 LTC3836 APPLICATIONS INFORMATION Using a Sense Resistor A sense resistor RSENSE can be connected between VIN and SW to sense the output load current. In this case, the drain of the topside N-channel MOSFET is connected to SENSE– pin and the source is connected to the SW pin of the LTC3836. Therefore, the current comparator monitors the voltage developed across RSENSE, not the VDS of the top MOSFET. The output current that the LTC3836 can provide in this case is given by: IOUT(MAX) =
VSENSE(MAX) IRIPPLE – RDS(ON) 2 Setting ripple current as 40% of IOUT(MAX) and using Figure 1 to choose SF, the value of RSENSE is:
VSENSE(MAX) 5 RSENSE = • SF • 6 IOUT(MAX) Variation in the resistance of a sense resistor is much smaller than the variation in on-resistance of an external MOSFET. Therefore the load current is well controlled with a sense resistor. However the sense resistor causes extra I2R losses in addition to those of the MOSFET. Therefore, using a sense resistor lowers the efficiency of LTC3836, especially at high load currents. Low Supply Operation Although the LTC3836 can function down to below 2.4V, the maximum allowable output current is reduced as VIN decreases below 3V. Figure 12 shows the amount of change as the supply is reduced down to 2.4V. Also shown is the effect on VREF. Minimum On-Time Considerations Minimum on-time, tON(MIN), is the smallest amount of time that the LTC3836 is capable of turning the main N-channel MOSFET on and then off. It is determined by internal timing delays and the gate charge required to turn on the top MOSFET. Low duty cycle and high frequency applications may approach the minimum on-time limit and care should be taken to ensure that: VOUT tON(MIN) < fOSC • VIN If the duty cycle falls below what can be accommodated by the minimum on-time, the LTC3836 will begin to skip cycles (unless forced continuous mode is selected). The output voltage will continue to be regulated, but the ripple current and ripple voltage will increase. The minimum ontime for the LTC3836 is typically about 200ns. However, as the peak sense voltage (IL(PEAK) • RDS(ON)) decreases, the minimum on-time gradually increases up to about 250ns. This is of particular concern in forced continuous applications with low ripple current at light loads. If forced continuous mode is selected and the duty cycle falls below the minimum on-time requirement, the output will be regulated by overvoltage protection. NORMALIZED VOLTAGE OR CURRENT (%) 105 100 95 VREF MAXIMUM SENSE VOLTAGE 90 85 80 75 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 INPUT VOLTAGE (V) 3836 F12 Figure 12. Line Regulation of VREF and Maximum Sense Voltage for Low Input Supply 3836fb 21 LTC3836 APPLICATIONS INFORMATION Efficiency Considerations Checking Transient Response The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting efficiency and which change would produce the most improvement. Efficiency can be expressed as: The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to (∆ILOAD)(ESR), where ESR is the effective series resistance of COUT. ∆ILOAD also begins to charge or discharge COUT, which generates a feedback error signal. The regulator loop then returns VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing. OPTI-LOOP® compensation allows the transient response to be optimized over a wide range of output capacitance and ESR values. Efficiency = 100% – (L1 + L2 + L3 + …) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, five main sources usually account for most of the losses in LTC3836 circuits: 1) LTC3836 DC bias current, 2) MOSFET gate charge current, 3) I2R losses, and 4) transition losses. 1) The VIN (pin) current is the DC supply current, given in the electrical characteristics, excluding MOSFET driver currents. VIN current results in a small loss that increases with VIN. 2) MOSFET gate charge current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from SENSE+ to ground. The resulting dQ/dt is a current out of SENSE+, which is typically much larger than the DC supply current. In continuous mode, IGATECHG = f • QP. 3) I2R losses are calculated from the DC resistances of the MOSFETs and inductor. In continuous mode, the average output current flows through L but is “chopped” between the top MOSFET and the bottom MOSFET. The MOSFET RDS(ON)s multiplied by duty cycle can be summed with the resistance of L to obtain I2R losses. 4) Transition losses apply to the top MOSFET and increase with higher operating frequencies and input voltages. Transition losses can be estimated from: Transition Loss = 2 (VIN)2IO(MAX)CRSS(f) Other losses, including CIN and COUT ESR dissipative losses and inductor core losses, generally account for less than 2% total additional loss. The ITH series RC-CC filter (see Functional Diagram) sets the dominant pole-zero loop compensation. The ITH external components shown in the Typical Application on the front page of this data sheet will provide an adequate starting point for most applications. The values can be modified slightly (from 0.2 to 5 times their suggested values) to optimize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be decided upon because the various types and values determine the loop feedback factor gain and phase. An output current pulse of 20% to 100% of full load current having a rise time of 1μs to 10μs will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability. The gain of the loop will be increased by increasing RC, and the bandwidth of the loop will be increased by decreasing CC. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. For a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to Application Note 76. A second, more severe transient is caused by switching in loads with large (>1μF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. The only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25)(CLOAD). Thus a 10μF capacitor would require a 250μs rise time, limiting the charging current to about 200mA. 3836fb 22 LTC3836 APPLICATIONS INFORMATION scribed above in item 1). The power grounds for the two channels should connect together at a common point. It is most important to keep the ground paths with high switching currents away from each other. PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3836. These items are illustrated in the layout diagram of Figure 13. Figure 14 depicts the current waveforms present in the various branches of the 2-phase dual regulator. The PGND pins on the LTC3836 should be shorted together and connected to the common power ground connection (away from the switching currents). 1) The power loop (input capacitor, MOSFETs, inductor, output capacitor) of each channel should be as small as possible and isolated as much as possible from the power loop of the other channel. Ideally, the main and synchronous FETs should be connected close to one another with an input capacitor placed right at the FETs. It is better to have two separate, smaller valued input capacitors (e.g., two 10μF —one for each channel) than it is to have a single larger valued capacitor (e.g., 22μF) that the channels share with a common connection. 3) Put the feedback resistors close to the VFB pins. The trace connecting the top feedback resistor (RB) to the output capacitor should be a Kelvin trace. The ITH compensation components should also be very close to the LTC3836. 4) The current sense traces (SENSE+ and SW) should be Kelvin connections right at the main N-channel MOSFET drains and sources. 5) Keep the switch nodes (SW1, SW2) and the gate driver nodes (TG1, TG2, BG1, BG2) away from the smallsignal components, especially the opposite channel’s feedback resistors, ITH compensation components, and the current sense pins (SENSE+ and SW). 2) The signal and power grounds should be kept separate. The signal ground consists of the feedback resistor dividers, ITH compensation networks and the SGND pin. The power grounds consist of the (–) terminal of the input and output capacitors and the source of the synchronous N-channel MOSFET. Each channel should have its own power ground for its power loop (as de- 6) Connect the boost capacitors to the switch nodes, not to the small signal nodes SWn. Connect the boost diodes to the positive terminal of the input capacitor. + COUT1 L1 LTC3836EGN 3 4 5 6 7 8 9 10 11 12 13 IPRG1 VFB1 ITH1 IPRG2 PLLLPF SGND + 28 SENSE1 BOOST1 PGND CB1 27 26 25 BG1 24 SYNC/FCB 23 TG1 22 PGND DB1 M1 CVIN1 M2 CVIN VIN 21 TG2 20 RUN/SS 19 BG2 TRACK/SS2 18 N/C VFB2 17 PGND ITH2 16 BOOST2 15 PGOOD SENSE2+ 14 SW2 VIN CVIN2 DB2 M3 CB2 M4 L2 + 1 SW1 2 N/C VOUT1 COUT2 VOUT2 3836 F13 BOLD LINES INDICATE HIGH CURRENT PATHS Figure 13. LTC3836 Layout Diagram 3836fb 23 LTC3836 APPLICATIONS INFORMATION L1 VOUT1 COUT1 + RL1 VIN RIN CIN + L2 VOUT2 COUT2 BOLD LINES INDICATE HIGH, SWITCHING CURRENT LINES. KEEP LINES TO A MINIMUM LENGTH + RL2 3836 F14 Figure 14. Branch Current Waveforms CFFW1, 33pF RFB1B, 118k RTRACKB, 12.4k RFB1A, 59k RTRACKA, 11.8k VFB1 7 CITH1A, 82pF CITH1, 820pF 2 27 RPLLLPF 4 21 CSS, 10nF VIN 2.75V TO 4.5V 17 5 CIN X2 BOOST1 CVIN, 1μF 6 RVIN, 10Ω 10 ITH1 TG1 IPRG1 BG1 PLLLPF PGND SYNC/FCB PGND RUN/SS PGND SGND VIN PGOOD IPRG2 9 I TH2 SENSE2+ SW2 RITH2, 15.8k RFB2A, 59k CB1, 0.22μF 24 26 L1 M1 25 VOUT1 1.8V 15A 20 22 M2 COUT1 X2 D1 23 29 19 14 PGND 15 BG2 18 TG2 3 CITH2A, 82pF CITH2, 820pF SW1 TRACK/SS2 SENSE1+ RITH1, 15.8k CPLLLPF DB1 LTC3836EUFD 1 M3 COUT2 X2 D2 VOUT2 1.2V 15A L2 12 M4 11 CB2, 0.22μF BOOST2 13 8 VFB2 N/C N/C 16 28 DB2 RFB2B, 59k L1, L2: VISHAY IHLP2525CZERR 47M01 CIN: 22μF X2, 6.3V, X5R COUT1, COUT2: TAIYO YUDEN JMK235BJ107MM X2 M1-M4: VISHAY Si7882DP 3836 F15 Figure 15. 2-Phase, 550kHz, Dual Output Synchronous DC/DC Converter with Ceramic Output Capacitors 3836fb 24 LTC3836 APPLICATIONS INFORMATION CFFW1, 82pF RFB1B, 88.7k, 1% RFB1A, 59k, 1% VFB1 CSS2, 10nF 7 CITH1A, 47pF BOOST1 SW1 TRACK/SS2 CB1, 0.22μF 24 26 L1 25 SENSE1+ VOUT1 1.5V 5A M1 CITH1, 470pF RITH1, 64.9k 2 ITH1 27 IPRG1 4 PLLLPF 21 SYNC/FCB CSS, 10nF VIN 17 3.3V 5 CIN X2 DB1 LTC3836EUFD 1 CVIN, 1μF 6 RVIN, 10Ω CITH2, 470pF BG1 PGND PGND PGND RUN/SS VIN SENSE2+ SW2 RITH2, 64.9k + D1 22 COUT1 23 29 19 14 PGND 15 BG2 18 TG2 SGND 10 PGOOD 3 IPRG2 9 I TH2 CITH2A, 47pF TG1 20 M2 D2 + COUT2 VOUT2 L2 12 1.1V 5A 11 CB2, 0.22μF BOOST2 13 RFB2A, 59k, 1% 8 VFB2 N/C N/C 16 28 DB2 RFB2B 49.9k, 1% L1, L2: VISHAY IHLP2525CZERR 47M01 CIN: 22μF X2, 6.3V, X5R COUT1, COUT2: SANYO POSCAP, 2R5TPE330M M1, M2: FAIRCHILD FDS6898A 3836 F16 CFFW2, 82pF Figure 16a. 2-Phase, 750kHz, Dual Output Synchronous DC/DC Converter 100 VOUT 200mV/DIV AC COUPLED CHANNEL 1 1.5V 90 EFFICIENCY (%) 80 IL1 5A/DIV 70 CHANNEL 2 1.1V 60 IL2 5A/DIV 50 40 ILOAD 5A/DIV 30 20 10 0 10 100 1000 LOAD CURRENT (mA) 10000 40μs/DIV VIN = 3.3V VOUT = 1.25V ILOAD = 10A TO 15A 3836 F17c 3836 F16b Figure 16b. Efficiency vs Load Current Figure 16c. Load Step 3836fb 25 LTC3836 TYPICAL APPLICATIONS CFFW1, 120pF RFB1B, 66.5k RTRACKB, 68.1k RFB1A, 61.9k RTRACKA, 61.9k VFB1 7 CITH1A, 100pF CITH1, 2700pF 2 27 RPLLLPF, 15k 500kHz 4 21 17 5 CVIN, 10RF 6 RVIN, 10< CIN X3 SW1 10 ITH1 TG1 IPRG1 BG1 PLLLPF PGND SYNC/FCB PGND RUN/SS PGND VIN PGOOD IPRG2 9 I TH2 8 26 SENSE2+ SW2 L1 M1 25 20 22 D1 B320A M2 23 COUT 29 19 14 PGND 15 BG2 18 TG2 SGND 3 CITH2A, 100pF CB1, 0.22RF 24 + CSS, 10nF VIN 2.75V TO 4.2V BOOST1 TRACK/SS2 SENSE1+ RITH1, 1.37k CPLLLPF, 0.015RF DB1 LTC3836EUFD 1 M3 VOUT 1.25V 20A D2 B320A L2 12 M4 11 3836 F17 CB2, 0.22RF BOOST2 13 VFB2 N/C N/C 16 28 DB2 L1, L2: TOKO 0.47RF FDV0630-R47M=P3 CIN: 22RF X3, 6.3V, X5R COUT: AVX CORECAP 560RF, 2.5V NPV V567M002 R003 M1, M2, M3, M4: SILICONIX Si7882DP Figure 17a. Single Output, High Current Application with External Frequency Synchronization 100 VOUT 200mV/DIV AC COUPLED VIN = 2.7V 90 EFFICIENCY (%) 80 IL1 5A/DIV 70 IL2 5A/DIV VIN = 3.6V 60 VIN = 4.2V 50 ILOAD 5A/DIV 40 30 20 10 1000 10000 100 LOAD CURRENT (mA) 100000 40μs/DIV VIN = 3.3V VOUT = 1.25V ILOAD = 10A TO 15A 3836 F17c 3836 F17b Figure 17b. Efficiency vs Load Current Figure 17c. Load Step 3836fb 26 LTC3836 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. GN Package 28-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .386 – .393* (9.804 – 9.982) .045 ±.005 28 27 26 25 24 23 22 21 20 19 18 17 1615 .254 MIN .033 (0.838) REF .150 – .165 .229 – .244 (5.817 – 6.198) .0165 ±.0015 .150 – .157** (3.810 – 3.988) .0250 BSC 1 RECOMMENDED SOLDER PAD LAYOUT .015 ± .004 × 45° (0.38 ± 0.10) .0075 – .0098 (0.19 – 0.25) 2 3 4 5 6 7 8 9 10 11 12 13 14 .0532 – .0688 (1.35 – 1.75) .004 – .0098 (0.102 – 0.249) 0° – 8° TYP .016 – .050 (0.406 – 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE .008 – .012 (0.203 – 0.305) TYP .0250 (0.635) BSC GN28 (SSOP) 0204 *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 3836fb 27 LTC3836 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UFD Package 28-Lead Plastic QFN (4mm × 5mm) (Reference LTC DWG # 05-08-1712 Rev B) 0.70 ±0.05 4.50 ± 0.05 3.10 ± 0.05 2.50 REF 2.65 ± 0.05 3.65 ± 0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 3.50 REF 4.10 ± 0.05 5.50 ± 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 ± 0.10 (2 SIDES) 0.75 ± 0.05 R = 0.05 TYP PIN 1 NOTCH R = 0.20 OR 0.35 × 45° CHAMFER 2.50 REF R = 0.115 TYP 27 28 0.40 ± 0.10 PIN 1 TOP MARK (NOTE 6) 1 2 5.00 ± 0.10 (2 SIDES) 3.50 REF 3.65 ± 0.10 2.65 ± 0.10 (UFD28) QFN 0506 REV B 0.200 REF 0.00 – 0.05 0.25 ± 0.05 0.50 BSC BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 3836fb 28 LTC3836 REVISION HISTORY REV DATE DESCRIPTION B 11/11 Updated Figure 17a (Revision history begins at Rev B) PAGE NUMBER 26 3836fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 29 LTC3836 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1735 High Efficiency Synchronous Step-Down Controller Burst Mode® Operation, 16-Pin Narrow SSOP, 3.5V ≤ VIN ≤ 36V LTC1778 No RSENSE Synchronous Step-Down Controller Current Mode Operation Without Sense Resistor, Fast Transient Response, 4V ≤ VIN ≤ 36V LTC2923 Power Supply Tracking Controller Controls Up to Three Supplies, 10-Lead MSOP LTC3411 1.25A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, IQ = 60μA, ISD =