LTC3850/LTC3850-1
Dual, 2-Phase Synchronous Step-Down
Switching Controller
FEATURES
DESCRIPTION
Dual, 180° Phased Controllers Reduce Required
Input Capacitance and Power Supply Induced Noise
n High Efficiency: Up to 95%
n R
SENSE or DCR Current Sensing
n ±1% 0.8V Output Voltage Accuracy
n Phase-Lockable Fixed Frequency 250kHz to 780kHz
n Supports Pre-Biased Output
n Dual N-Channel MOSFET Synchronous Drive
n Wide V Range: 4V to 24V (30V for LTC3850I)
IN
Operation
n Adjustable Soft-Start Current Ramping or Tracking
n Foldback Output Current Limiting
n Power Good Output Voltage Monitor
n 28-Pin 4mm × 4mm, 4mm × 5mm QFN and Narrow
SSOP Packages
n AEC-Q100 Qualified for Automotive Applications
The LTC®3850 is a high performance dual synchronous
step-down switching regulator controller that drives all
N-channel power MOSFET stages. A constant-frequency
current mode architecture allows a phase-lockable frequency of up to 780kHz. Power loss and supply noise are
minimized by operating the two controller output stages
out of phase.
n
OPTI-LOOP® compensation allows the transient response
to be optimized over a wide range of output capacitance
and ESR values. The LTC3850 features a precision 0.8V
reference and a power good output indicator. A wide 4V
to 24V (28V maximum/30V for LTC3850I) input supply
range encompasses most battery chemistries and intermediate bus voltages.
Independent TK/SS pins for each controller ramp the
output voltages during start-up. Current foldback limits
MOSFET heat dissipation during short-circuit conditions.
The MODE/PLLIN pin selects among Burst Mode® operation, pulse-skipping mode, or continuous inductor current mode and allows the IC to be synchronized to an
external clock.
APPLICATIONS
Notebook and Palmtop Computers
Portable Instruments
n Battery-Operated Digital Devices
n DC Power Distribution Systems
n
n
The LTC3850 is available in low profile 28-pin 4mm ×
4mm, 4mm × 5mm QFN and narrow SSOP packages.
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. patents, including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787,
6304066, 6580258.
TYPICAL APPLICATION
High Efficiency Dual 3.3V/2.5V Step-Down Converter
22µF
50V
4.7µF
VIN PGOOD INTVCC
BG1
2.2k
500kHz
MODE/PLLIN
ILIM
0.1µF
VOUT1
3.3V
5A
63.4k
220pF
100µF
6V
20k
15k
LTC3850
0.1µF
2.2µH
2.2k
BG2
PGND
ITH1
TK/SS1
BOOST2
SW2
1000
80
75
70
100
65
POWER LOSS
55
0.1µF
43.2k
ITH2
SGND
85
60
SENSE2+
RUN2
SENSE2–
VFB2
10nF
TK/SS2
0.1µF
10k
10000
EFFICIENCY
90
0.1µF
FREQ/PLLFLTR
SENSE1+
RUN1
SENSE1–
VFB1
VIN = 12V
95 VOUT = 3.3V
POWER LOSS (mW)
BOOST1
SW1
2.2µH
TG2
100
EFFICIENCY (%)
TG1
0.1µF
Efficiency
VIN
7V TO
24V
VOUT2
2.5V
5A
220pF
15k
50
10
100
1000
LOAD CURRENT (mA)
10
10000
38501 TA01b
100µF
6V
20k
38501 TA01
Rev. D
Document Feedback
For more information www.analog.com
1
LTC3850/LTC3850-1
ABSOLUTE MAXIMUM RATINGS
(Note 1)
SENSE1+, SENSE2+, SENSE1–,
SENSE2– Voltages..................................... 5.5V to –0.3V
MODE/PLLIN, ILIM,TK/SS1,TK/SS2, FREQ/PLLFLTR
Voltages.................................................INTVCC to –0.3V
ITH1 , ITH2 , VFB1 , VFB2 Voltages.................. 2.7V to –0.3V
INTVCC Peak Output Current.................................100mA
Operating Temperature Range (Note 2)....–40°C to 85°C
Junction Temperature (Note 3).............................. 125°C
Storage Temperature Range................... –65°C to 125°C
Lead Temperature (Soldering, 10 sec)
(GN Package)..................................................... 300°C
Input Supply Voltage (VIN).......................... 28V to –0.3V
Input Supply Voltage (VIN),
LTC3850I Only........................................ 30V to –0.3V
Input Supply Transient Voltage (VIN) < 500ms, with
INTVCC ≥ 5V, LTC3850I Only.................. 34V to –0.3V
Top Side Driver Voltages
BOOST1, BOOST2................................... 34V to –0.3V
Switch Voltage (SW1, SW2)........................... 28V to –5V
Switch Voltage (SW1, SW2),
LTC3850I Only...........................................30V to –5V
INTVCC , RUN1, RUN2, PGOOD, EXTVCC,
(BOOST1-SW1), (BOOST2-SW2).................. 6V to –0.3V
PIN CONFIGURATION
TOP VIEW
SGND
7
22 VIN
VFB2
8
21 INTVCC
ITH2
9
20 BG2
SENSE2+ 12
17 TG2
RUN2 13
16 SW2
ILIM (EXTVCC)* 14
20 BG1
VFB1 3
19 VIN
VFB2 4
18 INTVCC
17 BG2
29
ITH2 5
19 PGND
18 BOOST2
21 BOOST1
ITH1 2
TK/SS2 6
16 PGND
SENSE2– 7
15 BOOST2
8
SENSE2+
TK/SS2 10
SENSE2– 11
TG1
23 BG1
SW1
6
15 PGOOD
GN PACKAGE
28-LEAD NARROW PLASTIC SSOP
TJMAX = 125°C, θJA = 95°C/W
*PIN 14 = ILIM FOR LTC3850GN, EXTVCC FOR LTC3850GN-1
9 10 11 12 13 14
TG2
VFB1
28 27 26 25 24 23 22
TK/SS1 1
SW2
24 BOOST1
FREQ/PLLFLTR
5
MODE/PLLIN
25 TG1
ITH1
PGOOD
4
RUN1
26 SW1
TK/SS1
EXTVCC
27 MODE/PLLIN
3
SENSE1+
2
SENSE1–
ILIM
SENSE1+
RUN2
RUN1
28 FREQ/PLLFLTR
SENSE1–
TOP VIEW
1
UF PACKAGE
28-LEAD (4mm × 4mm) PLASTIC QFN
TJMAX = 125°C, θJA = 37°C/W, θJC = 2.6°C/W
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
TG1
SW1
MODE/PLLIN
FREQ/PLLFLTR
RUN1
SENSE1+
TOP VIEW
28 27 26 25 24 23
SENSE1– 1
22 BOOST1
TK/SS1 2
21 BG1
ITH1 3
20 VIN
VFB1 4
19 INTVCC
29
VFB2 5
18 BG2
ITH2 6
17 PGND
TK/SS2 7
16 BOOST2
SENSE2– 8
15 TG2
SW2
PGOOD
EXTVCC
ILIM
RUN2
SENSE2+
9 10 11 12 13 14
UFD PACKAGE
28-LEAD (4mm × 5mm) PLASTIC QFN
TJMAX = 125°C, θJA = 34°C/W, EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
2
Rev. D
For more information www.analog.com
LTC3850/LTC3850-1
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3850EGN#PBF
LTC3850EGN#TRPBF
LTC3850GN
28-Lead Narrow Plastic SSOP
–40°C to 85°C
LTC3850EGN-1#PBF
LTC3850EGN-1#TRPBF
LTC3850GN-1
28-Lead Narrow Plastic SSOP
–40°C to 85°C
LTC3850IGN#PBF
LTC3850IGN#TRPBF
LTC3850GN
28-Lead Narrow Plastic SSOP
–40°C to 85°C
LTC3850IGN-1#PBF
LTC3850IGN-1#TRPBF
LTC3850GN-1
28-Lead Narrow Plastic SSOP
–40°C to 85°C
LTC3850EUF#PBF
LTC3850EUF#TRPBF
3850
28-Lead (4mm × 4mm) Plastic QFN
–40°C to 85°C
LTC3850EUFD#PBF
LTC3850EUFD#TRPBF
3850
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 85°C
LTC3850IUF#PBF
LTC3850IUF#TRPBF
3850
28-Lead (4mm × 4mm) Plastic QFN
–40°C to 85°C
LTC3850IUFD#PBF
LTC3850IUFD#TRPBF
3850
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 85°C
LTC3850EGN#WPBF
LTC3850EGN#WTRPBF
LTC3850GN
28-Lead Narrow Plastic SSOP
–40°C to 85°C
LTC3850EGN-1#WPBF
LTC3850EGN-1#WTRPBF
LTC3850GN-1
28-Lead Narrow Plastic SSOP
–40°C to 85°C
LTC3850IGN#WPBF
LTC3850IGN#WTRPBF
LTC3850GN
28-Lead Narrow Plastic SSOP
–40°C to 85°C
LTC3850IGN-1#WPBF
LTC3850IGN-1#WTRPBF
LTC3850GN-1
28-Lead Narrow Plastic SSOP
–40°C to 85°C
AUTOMOTIVE PRODUCTS**
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your
local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
these models.
Rev. D
For more information www.analog.com
3
LTC3850/LTC3850-1
ELECTRICAL
CHARACTERISTICS
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 15V, VRUN1,2 = 5V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
0.792
0.800
0.808
V
–10
–50
nA
0.002
0.02
%/V
0.01
–0.01
0.1
–0.1
%
%
Main Control Loops
VFB1,2
Regulated Feedback Voltage
ITH1,2 Voltage = 1.2V; (Note 4)
IFB1,2
Feedback Current
(Note 4)
VREFLNREG
Reference Voltage Line Regulation
VIN = 6V to 24V (Note 4)
VLOADREG
Output Voltage Load Regulation
(Note 4)
Measured in Servo Loop; ∆ITH Voltage = 1.2V to 0.7V
Measured in Servo Loop; ∆ITH Voltage = 1.2V to 1.6V
l
l
l
gm1,2
Transconductance Amplifier gm
ITH1,2 = 1.2V; Sink/Source 5µA; (Note 4)
2.2
IQ
Input DC Supply Current
Normal Mode
Shutdown
(Note 5)
VIN = 15V; EXTVCC Tied to VOUT1; VOUT1 = 5V
VRUN1,2 = 0V
850
30
UVLO
Undervoltage Lockout on INTVCC
VINTVCC Ramping Down
UVLOHYS
UVLO Hysteresis
DFMAX
Maximum Duty Factor
In Dropout
VOVL
Feedback Overvoltage Lockout
Measured at VFB1,2
ISENSE
Sense Pin Bias Current
(Each Channel) VSENSE1,2 = 3.3V
ITK/SS1,2
Soft-Start Charge Current
VTK/SS1,2 = 0V
VRUN1,2
RUN Pin ON Threshold
VRUN1, VRUN2 Rising
VRUN1,2HYS
RUN Pin ON Hysteresis
VSENSE(MAX)
Maximum Current Sense Threshold
(Note 8)
VFB1,2 = 0.7V, VSENSE1,2 = 3.3V, ILIM = 0V
VFB1,2 = 0.7V, VSENSE1,2 = 3.3V, ILIM = Float
VFB1,2 = 0.7V, VSENSE1,2 = 3.3V, ILIM = INTVCC
TG RUP
TG Driver Pull-Up On-Resistance
TG High
2.6
Ω
TG RDOWN
TG Driver Pull-down On-Resistance
TG Low
1.5
Ω
BG RUP
BG Driver Pull-Up On-Resistance
BG High
2.4
Ω
BG RDOWN
BG Driver Pull-down On-Resistance
BG Low
1.1
Ω
TG1,2 tr
TG1,2 tf
TG Transition Time:
Rise Time
Fall Time
(Note 6)
CLOAD = 3300pF
CLOAD = 3300pF
25
25
ns
ns
BG1,2 tr
BG1,2 tf
BG Transition Time:
Rise Time
Fall Time
(Note 6)
CLOAD = 3300pF
CLOAD = 3300pF
25
25
ns
ns
TG/BG t1D
Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time
CLOAD = 3300pF Each Driver
30
ns
BG/TG t2D
Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time
CLOAD = 3300pF Each Driver
30
ns
tON(MIN)
Minimum On-Time
(Note 7)
90
ns
l
l
mmho
50
3
V
0.5
V
96
97.2
%
0.84
0.86
0.88
V
±1
±2
µA
0.9
1.3
1.7
µA
1.1
1.22
1.35
V
80
l
l
l
µA
µA
20
40
60
30
50
75
mV
40
60
90
mV
mV
mV
INTVCC Linear Regulator
VINTVCC
Internal VCC Voltage
7V < VIN < 24V
VLDO INT
INTVCC Load Regulation
ICC = 0mA to 50mA
VEXTVCC
EXTVCC Switchover Voltage
EXTVCC Ramping Positive
VLDO EXT
EXTVCC Voltage Drop
ICC = 20mA, VEXTVCC = 5V
VLDOHYS
EXTVCC Hysteresis
4
4.8
l
4.5
5
5.2
V
0.5
2
%
4.7
50
200
V
100
mV
mV
Rev. D
For more information www.analog.com
LTC3850/LTC3850-1
ELECTRICAL
CHARACTERISTICS
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 15V, VRUN1,2 = 5V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Oscillator and Phase-Locked Loop
fNOM
Nominal Frequency
VFREQ = 1.2V
450
500
550
kHz
fLOW
Lowest Frequency
VFREQ = 0V
210
250
290
kHz
fHIGH
Highest Frequency
VFREQ ≥ 2.4V
700
780
860
kHz
RMODE/PLLIN
MODE/PLLIN Input Resistance
IFREQ
Phase Detector Output Current
Sinking Capability
Sourcing Capability
VPGL
IPGOOD
VPG
250
kΩ
fMODE < fOSC
fMODE > fOSC
–13
13
µA
µA
PGOOD Voltage Low
IPGOOD = 2mA
0.1
PGOOD Leakage Current
VPGOOD = 5V
PGOOD Trip Level
VFB with Respect to Set Regulated Voltage
VFB Ramping Negative
VFB Ramping Positive
PGOOD Output
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3850E/LTC3850E-1 are guaranteed to meet performance
specifications from 0°C to 85°C. Specifications over the –40°C to 85°C
operating temperature range are assured by design, characterization and
correlation with statistical process controls. The LTC3850I/LTC3850I-1
are guaranteed to meet performance specifications over the –40°C to 85°C
operating temperature range.
Note 3: TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formulas:
–5
5
– 7.5
7.5
0.3
V
±2
µA
–10
10
%
%
LTC3850GN: TJ = TA + (PD • 95°C/W)
LTC3850UF: TJ = TA + (PD • 37°C/W)
LTC3850UFD: TJ = TA + (PD • 43°C/W)
Note 4: The LTC3850 is tested in a feedback loop that servos VITH1,2 to a
specified voltage and measures the resultant VFB1,2.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 7: The minimum on-time condition is specified for an inductor
peak-to-peak ripple current ≥40% of IMAX (see Minimum On-Time
Considerations in the Applications Information section).
Note 8: VSENSE(MAX) defaults to 50mV typical for the LTC3850-1.
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Output Current
and Mode
Efficiency vs Output Current
and Mode
100
BURST
DCM
60
50
40
30
CCM
20
DCM
60
50
40
30
CCM
VIN = 12V
VOUT = 3.3V
10
10
100
1000
LOAD CURRENT (mA)
CIRCUIT OF FIGURE 14
10000
38501 G01
0
10
EFFICIENCY
90
100
1000
LOAD CURRENT (mA)
CIRCUIT OF FIGURE 14
10000
38501 G02
For more information www.analog.com
1500
1000
POWER LOSS
500
85
20
10
0
95
70
2000
VOUT = 3.3V
IOUT = 2A
BURST
80
EFFICIENCY (%)
70
100
90
80
POWER LOSS (mW)
EFFICIENCY (%)
80
100
EFFICIENCY (%)
VIN = 12V
90 VOUT = 1.8V
Efficiency and Power Loss
vs Input Voltage
5
10
15
20
INPUT VOLTAGE (V)
CIRCUIT OF FIGURE 14
0
25
38501 G03
Rev. D
5
LTC3850/LTC3850-1
TYPICAL PERFORMANCE CHARACTERISTICS
Load Step
(Burst Mode Operation)
Load Step
(Forced Continuous Mode)
ILOAD
2A/DIV
200mA TO 2.5A
ILOAD
2A/DIV
200mA TO 2.5A
IL
2A/DIV
IL
2A/DIV
VOUT
100mV/DIV
AC COUPLED
VOUT
100mV/DIV
AC COUPLED
38501 G04
40µs/DIV
CIRCUIT OF FIGURE 14
VIN = 12V, VOUT = 1.8V
Load Step
(Pulse-Skipping Mode)
Inductor Current at Light Load
FORCED
CONTINUOUS
MODE
2A/DIV
ILOAD
2A/DIV
200mA TO 2.5A
IL
2A/DIV
Burst Mode
OPERATION
2A/DIV
VOUT
100mV/DIV
AC COUPLED
38501 G06
40µs/DIV
VOUT
2V/DIV
PULSE-SKIPPING
MODE
2A/DIV
1µs/DIV
CIRCUIT OF FIGURE 14
VIN = 12V, VOUT = 1.8V
CIRCUIT OF FIGURE 14
VIN = 12V, VOUT = 1.8V
ILOAD = 100µA
Prebiased Output at 2V
Coincident Tracking
RUN1
2V/DIV
VTK/SS
500mV/DIV
38501 G07
VOUT1, 3.3V
3Ω LOAD, 1V/DIV
VOUT2, 1.8V
1.5Ω LOAD
1V/DIV
VFB
500mV/DIV
2.5ms/DIV
6
38501 G05
40µs/DIV
CIRCUIT OF FIGURE 14
VIN = 12V, VOUT = 1.8V
38501 G08
1ms/DIV
38501 G09
Rev. D
For more information www.analog.com
LTC3850/LTC3850-1
TYPICAL PERFORMANCE CHARACTERISTICS
Tracking Up and Down
with External Ramp
5
TK/SS1
TK/SS2
2V/DIV
Quiescent Current
vs Input Voltage without EXTVCC
5.25
5.00
VOUT2
1.8V
1.5Ω LOAD
1V/DIV
3
2
1
38501 G10
10ms/DIV
INTVCC VOLTAGE (V)
SUPPLY CURRENT (mA)
4
VOUT1
3.3V
3Ω LOAD
1V/DIV
0
INTVCC Line Regulation
4.75
4.50
4.25
4.00
3.75
15
10
5
20
3.50
25
0
5
10
INPUT VOLTAGE (V)
15
20
38501 G11
Current Sense Threshold
vs ITH Voltage
20
ILIM = GND
0
–20
0
0.5
1
VITH (V)
1.5
2
70
60
ILIM = FLOAT
50
40
ILIM = GND
30
20
10
0
0
1
2
4
3
VSENSE COMMON MODE VOLTAGE (V)
38501 G13
60
ILIM = FLOAT
50
40
ILIM = GND
30
ILIM = INTVCC
70
60
ILIM = FLOAT
50
40
ILIM = GND
30
20
10
0
0
20
40
60
DUTY CYCLE (%)
80
100
38501 G15
2.00
ILIM = INTVCC
70
80
TK/SS Pull-Up Current
vs Temperature
Maximum Current Sense Voltage vs
Feedback Voltage (Current Foldback)
80
5
90
38501 G14
TK/SS CURRENT (µA)
40
100
ILIM = INTVCC
CURRENT SENSE THRESHOLD (mV)
CURRENT SENSE THRESHOLD (mV)
ILIM = FLOAT
MAXIMUM CURRENT SENSE VOLTAGE (mV)
VSENSE (mV)
Maximum Current Sense
Threshold vs Duty Cycle
80
ILIM = INTVCC
60
–40
38501 G12
Maximum Current Sense Threshold
vs Common Mode Voltage
80
25
INPUT VOLTAGE (V)
20
1.75
1.50
1.25
10
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
FEEDBACK VOLTAGE (V)
1.00
–50
38501 G16
–25
50
25
0
TEMPERATURE (°C)
75
100
38501 G17
Rev. D
For more information www.analog.com
7
LTC3850/LTC3850-1
TYPICAL PERFORMANCE CHARACTERISTICS
Regulated Feedback Voltage
vs Temperature
Shutdown (RUN) Threshold
vs Temperature
RUN PIN VOLTAGE (V)
1.4
1.3
ON
1.2
OFF
1.1
1.0
–50
–25
50
25
0
TEMPERATURE (°C)
900
804
800
802
800
798
796
–25
50
25
0
TEMPERATURE (°C)
75
400
100
380
10
5
15
20
5
40
QUIESCENT CURRENT (mA)
SHUTDOWN CURRENT (µA)
25
0
5
10
30
20
10
50
25
0
TEMPERATURE (°C)
15
75
100
20
25
INPUT VOLTAGE (V)
38501 G23
Quiescent Current
vs Temperature without EXTVCC
4
3
2
1
0
–50
–25
38501 G24
8
20
38501 G22
VIN = 15V
–25
30
INPUT VOLTAGE (V)
Shutdown Current
vs Temperature
0
–50
100
10
38501 G21
50
75
40
390
1
50
25
0
TEMPERATURE (°C)
50
25
0
TEMPERATURE (°C)
–25
50
INPUT CURRENT (µA)
2
VFREQ = 0V
Shutdown Current
vs Input Voltage
410
FREQUENCY (kHz)
INTVCC VOLTAGE (V)
4
–25
400
38501 G20
420
FALLING
VFREQ = 1.2V
500
Oscillator Frequency
vs Input Voltage
5
0
–50
600
38501 G19
Undervoltage Lockout Threshold
(INTVCC) vs Temperature
3
700
200
–50
100
75
38501 G18
RISING
VFREQ = INTVCC
300
794
–50
100
75
806
FREQUENCY (kHz)
REGULATED FEEDBACK VOLTAGE (mV)
1.5
Oscillator Frequency
vs Temperature
50
25
0
TEMPERATURE (°C)
75
100
38501 G25
Rev. D
For more information www.analog.com
LTC3850/LTC3850-1
PIN FUNCTIONS
(GN/UF/UFD)
RUN1, RUN2 (Pins 1, 13/Pins 26, 9/Pins 27, 10): Run
Control Inputs. A voltage above 1.2V on either pin turns
on the IC. However, forcing either of these pins below 1.2V
causes the IC to shut down that particular channel. There
are 0.5µA pull-up currents for these pins. Once the RUN
pin rises above 1.2V, an additional 4.5µA pull-up current
is added to the pin.
SENSE1+, SENSE2+ (Pins 2, 12/Pins 27, 8/Pins 28, 9):
Current Sense Comparator Inputs. The (+) inputs to the
current comparators are normally connected to DCR
sensing networks or current sensing resistors.
SENSE1–, SENSE2– (Pins 3, 11/Pins 28, 7/Pins 1, 8):
Current Sense Comparator Inputs. The (–) inputs to the
current comparators are connected to the outputs.
TK/SS1, TK/SS2 (Pins 4, 10/Pins 1, 6/Pins 2, 7): Output
Voltage Tracking and Soft-Start Inputs. When one channel
is configured to be master of the two channels, a capacitor to ground at this pin sets the ramp rate for the master
channel’s output voltage. When the channel is configured
to be the slave of two channels, the VFB voltage of the
master channel is reproduced by a resistor divider and
applied to this pin. Internal soft-start currents of 1.3µA
charge the soft-start capacitors.
ITH1, ITH2 (Pins 5, 9/Pins 2, 5/Pins 3, 6): Current Control
Thresholds and Error Amplifier Compensation Points.
Each associated channels’ current comparator tripping
threshold increases with its ITH control voltage.
VFB1, VFB2 (Pins 6, 8/Pins 3, 4/Pins 4, 5): Error Amplifier
Feedback Inputs. These pins receive the remotely sensed
feedback voltages for each channel from external resistive
dividers across the outputs.
SGND (Pin 7/Pin 29/Pin 29): Signal Ground. All small-signal components and compensation components should
connect to this ground, which in turn connects to PGND
at one point. Pin 29 is the Exposed Pad, only available on
the UF package.
EXTVCC (Pin 14, LTC3850-1 Only/Pin 11/Pin 12): External
Power Input to an Internal Switch Connected to INTVCC.
This switch closes and supplies the IC power, bypassing
the internal low dropout regulator, whenever EXTVCC is
higher than 4.7V. Do not exceed 6V on this pin and ensure
VIN > VEXTVCC at all times. On the GN package, EXTVCC is
the optional bonding in place of ILIM for LTC3850-1. In
the LTC3850-1, ILIM will default to 50mV.
ILIM (Pin 14, LTC3850 Only/Pin 10/Pin 11): Current
Comparator Sense Voltage Range Inputs. Tying this pin to
SGND, FLOAT or INTVCC sets the maximum current sense
threshold to three different levels for each comparator.
PGOOD (Pin 15/Pin 12/Pin 13): Power Good Indicator
Output. Open-drain logic out that is pulled to ground when
either channel output exceeds the ±7.5% regulation window,
after the internal 17µs power bad mask timer expires.
PGND (Pin 19/Pin 16/Pin 17): Power Ground Pin. Connect
this pin closely to the sources of the bottom N-channel
MOSFETs, the (–) terminal of CVCC and the (–) terminal
of CIN.
INTVCC (Pin 21/Pin 18/Pin 19): Internal 5V Regulator Output.
The control circuits are powered from this voltage.
Decouple this pin to PGND with a 4.7µF low ESR tantalum
or ceramic capacitor.
VIN (Pin 22/Pin 19/Pin 20): Main Input Supply. Decouple
this pin to PGND with a capacitor (0.1µF to 1µF). For
applications where the main input power is 5V, tie the VIN
and INTVCC pins together.
BG1, BG2 (Pins 23, 20/Pins 20, 17/Pins 21, 18): Bottom
Gate Driver Outputs. These pins drive the gates of the
bottom N-Channel MOSFETs and swings between PGND
and INTVCC.
BOOST1, BOOST2 (Pins 24, 18/Pins 21, 15/Pins 22, 16):
Boosted Floating Driver Supplies. The (+) terminal of the
boost-strap capacitors connect to these pins. These pins
swing from a diode voltage drop below INTVCC up to VIN
+ INTVCC.
TG1, TG2 (Pins 25, 17/Pins 22, 14/Pins 23, 15): Top Gate
Driver Outputs. These are the outputs of floating drivers
with a voltage swing equal to INTVCC superimposed on
the switch nodes voltages.
SW1, SW2 (Pins 26, 16/Pins 23, 13/Pins 24, 14):
Switch Node Connections to Inductors. Voltage swing
at these pins are from a body diode voltage drop below
ground to VIN.
Rev. D
For more information www.analog.com
9
LTC3850/LTC3850-1
PIN FUNCTIONS
MODE/PLLIN (Pin 27/Pin 24/Pin 25): Force Continuous
Mode, Burst Mode, or Pulse-Skipping Mode Selection
Pin and External Synchronization Input to Phase Detector
Pin. Connect this pin to SGND to force both channels into
the continuous mode of operation. Connect to INTVCC
to enable pulse-skipping mode of operation. Leaving the
pin floating will enable Burst Mode operation. A clock on
the pin will force the controller into continuous mode of
operation and synchronize the internal oscillator.
FREQ/PLLFLTR (Pin 28/Pin 25/Pin 26): The Phase-Locked
Loop’s Low-Pass Filter is Tied to This Pin. Alternatively,
this pin can be driven with a DC voltage to vary the frequency of the internal oscillator.
Exposed Pad (Pin 29, UF/UFD Packages Only): Signal
Ground. Must be soldered to PCB, providing a local
ground for the control components of the IC, and be tied
to the PGND pin under the IC.
FUNCTIONAL DIAGRAM
FREQ/PLLFLTR
MODE/PLLIN
EXTVCC
VIN
VIN
4.7V
+
–
F
0.8V
MODE/SYNC
DETECT
CIN
5V
REG
+
–
PLL-SYNC
+
INTVCC
INTVCC
F
BOOST
OSC
BURSTEN
S
R
3k
+
ON
–
ICMP
+
–
IREV
CB
TG
FCNT
Q
M1
SW
SWITCH
LOGIC
AND
ANTISHOOT
THROUGH
L1
SENSE+
SENSE–
+
RUN
M2
CVCC
SLOPE COMPENSATION
PGND
PGOOD
INTVCC
UVLO
+
1
51k
ITHB
UV
–
0.74V
VFB
+
–
–
+
SS
+
–
RUN
–
+
R2
R1
OV
0.86V
SGND
1.3µA
EA
– + +
0.8V
REF
SLOPE RECOVERY
ACTIVE CLAMP
SLEEP
VIN
0.64V
1.2V
0.5µA
0.55V
ITH
10
COUT
BG
OV
ILIM
VOUT
DB
RC
CC1
RUN
TK/SS
CSS
38501 FD
Rev. D
For more information www.analog.com
LTC3850/LTC3850-1
OPERATION
Main Control Loop
The LTC3850 is a constant-frequency, current mode stepdown controller with two channels operating 180 degrees
out-of-phase. During normal operation, each top MOSFET
is turned on when the clock for that channel sets the RS
latch, and turned off when the main current comparator,
ICMP, resets the RS latch. The peak inductor current at
which ICMP resets the RS latch is controlled by the voltage
on the ITH pin, which is the output of each error amplifier EA. The VFB pin receives the voltage feedback signal,
which is compared to the internal reference voltage by the
EA. When the load current increases, it causes a slight
decrease in VFB relative to the 0.8V reference, which in
turn causes the ITH voltage to increase until the average
inductor current matches the new load current. After the
top MOSFET has turned off, the bottom MOSFET is turned
on until either the inductor current starts to reverse, as
indicated by the reverse current comparator IREV, or the
beginning of the next cycle.
INTVCC/EXTVCC Power
Power for the top and bottom MOSFET drivers and most
other internal circuitry is derived from the INTVCC pin.
When the EXTVCC pin is left open or tied to a voltage less
than 4.7V, an internal 5V linear regulator supplies INTVCC
power from VIN. If EXTVCC is taken above 4.7V, the 5V
regulator is turned off and an internal switch is turned
on connecting EXTVCC. Using the EXTVCC pin allows the
INTVCC power to be derived from a high efficiency external
source such as one of the LTC3850 switching regulator
outputs.
Each top MOSFET driver is biased from the floating bootstrap capacitor CB, which normally recharges during each
off cycle through an external diode when the top MOSFET
turns off. If the input voltage VIN decreases to a voltage
close to VOUT, the loop may enter dropout and attempt
to turn on the top MOSFET continuously. The dropout
detector detects this and forces the top MOSFET off for
about one-twelfth of the clock period every third cycle to
allow CB to recharge. However, it is recommended that a
load be present during the drop-out transition to ensure
CB is recharged.
Shutdown and Start-Up (RUN1, RUN2 and TK/SS1,
TK/SS2 Pins)
The two channels of the LTC3850 can be independently
shut down using the RUN1 and RUN2 pins. Pulling either
of these pins below 1.2V shuts down the main control
loop for that controller. Pulling both pins low disables
both controllers and most internal circuits, including the
INTVCC regulator. Releasing either RUN pin allows an
internal 0.5µA current to pull up the pin and enable that
controller. Alternatively, the RUN pin may be externally
pulled up or driven directly by logic. Be careful not to
exceed the Absolute Maximum Rating of 6V on this pin.
The start-up of each controller’s output voltage VOUT is
controlled by the voltage on the TK/SS1 and TK/SS2 pins.
When the voltage on the TK/SS pin is less than the 0.8V
internal reference, the LTC3850 regulates the VFB voltage
to the TK/SS pin voltage instead of the 0.8V reference.
This allows the TK/SS pin to be used to program a softstart by connecting an external capacitor from the TK/SS
pin to SGND. An internal 1.3µA pull-up current charges
this capacitor, creating a voltage ramp on the TK/SS pin.
As the TK/SS voltage rises linearly from 0V to 0.8V (and
beyond), the output voltage VOUT rises smoothly from zero
to its final value. Alternatively the TK/SS pin can be used to
cause the start-up of VOUT to “track” that of another supply. Typically, this requires connecting to the TK/SS pin an
external resistor divider from the other supply to ground
(see the Applications Information section). When the corresponding RUN pin is pulled low to disable a controller, or when INTVCC drops below its undervoltage lockout
threshold of 3V, the TK/SS pin is pulled low by an internal
MOSFET. When in undervoltage lockout, both controllers
are disabled and the external MOSFETs are held off.
Light Load Current Operation (Burst Mode Operation,
Pulse-Skipping, or Continuous Conduction)
The LTC3850 can be enabled to enter high efficiency
Burst Mode operation, constant-frequency pulse-skipping mode, or forced continuous conduction mode. To
select forced continuous operation, tie the MODE/PLLIN
pin to a DC voltage below 0.8V (e.g., SGND). To select
pulse-skipping mode of operation, tie the MODE/PLLIN
pin to INTVCC. To select Burst Mode operation, float the
Rev. D
For more information www.analog.com
11
LTC3850/LTC3850-1
OPERATION
MODE/PLLIN pin. When a controller is enabled for Burst
Mode operation, the peak current in the inductor is set to
approximately one-third of the maximum sense voltage
even though the voltage on the ITH pin indicates a lower
value. If the average inductor current is higher than the
load current, the error amplifier EA will decrease the voltage on the ITH pin. When the ITH voltage drops below
0.5V, the internal sleep signal goes high (enabling “sleep”
mode) and both external MOSFETs are turned off.
In sleep mode, the load current is supplied by the output
capacitor. As the output voltage decreases, the EA’s output
begins to rise. When the output voltage drops enough,
the sleep signal goes low, and the controller resumes
normal operation by turning on the top external MOSFET
on the next cycle of the internal oscillator. When a controller is enabled for Burst Mode operation, the inductor current is not allowed to reverse. The reverse current
comparator (IREV) turns off the bottom external MOSFET
just before the inductor current reaches zero, preventing
it from reversing and going negative. Thus, the controller
operates in discontinuous operation. In forced continuous
operation, the inductor current is allowed to reverse at
light loads or under large transient conditions. The peak
inductor current is determined by the voltage on the ITH
pin, just as in normal operation. In this mode, the efficiency at light loads is lower than in Burst Mode operation.
However, continuous mode has the advantages of lower
output ripple and less interference with audio circuitry.
When the MODE/PLLIN pin is connected to INTVCC, the
LTC3850 operates in PWM pulse-skipping mode at light
loads. At very light loads, the current comparator ICMP
may remain tripped for several cycles and force the external top MOSFET to stay off for the same number of cycles
(i.e., skipping pulses). The inductor current is not allowed
to reverse (discontinuous operation). This mode, like
forced continuous operation, exhibits low output ripple
as well as low audio noise and reduced RF interference
as compared to Burst Mode operation. It provides higher
low current efficiency than forced continuous mode, but
not nearly as high as Burst Mode operation.
12
Frequency Selection and Phase-Locked Loop
(FREQ/PLLFLTR and MODE/PLLIN Pins)
The selection of switching frequency is a trade-off
between efficiency and component size. Low frequency
operation increases efficiency by reducing MOSFET
switching losses, but requires larger inductance and/or
capacitance to maintain low output ripple voltage. The
switching frequency of the LTC3850’s controllers can be
selected using the FREQ/PLLFLTR pin. If the MODE/PLLIN
pin is not being driven by an external clock source, the
FREQ/PLLFLTR pin can be used to program the controller’s operating frequency from 250kHz to 780kHz.
A phase-locked loop (PLL) is available on the LTC3850
to synchronize the internal oscillator to an external clock
source that is connected to the MODE/PLLIN pin. The controller is operating in forced continuous mode when it is
synchronized. A series R-C should be connected between
the FREQ/PLLFLTR pin and SGND to serve as the PLL’s
loop filter.
Power Good (PGOOD Pin)
The PGOOD pin is connected to an open drain of an internal N-channel MOSFET. The MOSFET turns on and pulls
the PGOOD pin low when either VFB pin voltage is not
within ±7.5% of the 0.8V reference voltage. The PGOOD
pin is also pulled low when either RUN pin is below 1.2V
or when the LTC3850 is in the soft-start or tracking phase.
When the VFB pin voltage is within the ±7.5% requirement,
the MOSFET is turned off and the pin is allowed to be
pulled up by an external resistor to a source of up to 6V.
The PGOOD pin will flag power good immediately when
both VFB pins are within the ±7.5% window. However,
there is an internal 17µs power bad mask when either VFB
goes out of the ±7.5% window.
Output Overvoltage Protection
An overvoltage comparator, OV, guards against transient
overshoots (> 7.5%) as well as other more serious conditions that may overvoltage the output. In such cases,
the top MOSFET is turned off and the bottom MOSFET is
turned on until the overvoltage condition is cleared.
Rev. D
For more information www.analog.com
LTC3850/LTC3850-1
APPLICATIONS INFORMATION
The Typical Application on the first page is a basic LTC3850
application circuit. LTC3850 can be configured to use either
DCR (inductor resistance) sensing or low value resistor
sensing. The choice between the two current sensing
schemes is largely a design trade-off between cost, power
consumption, and accuracy. DCR sensing is becoming
popular because it saves expensive current sensing resistors and is more power efficient, especially in high current
applications. However, current sensing resistors provide
the most accurate current limits for the controller. Other
external component selection is driven by the load requirement, and begins with the selection of RSENSE (if RSENSE is
used) and inductor value. Next, the power MOSFETs are
selected. Finally, input and output capacitors are selected.
Current Limit Programming
The ILIM pin is a tri-level logic input which sets the maximum current limit of the controller. When ILIM is either
grounded, floated or tied to INTVCC, the typical value for
the maximum current sense threshold will be 30mV,
50mV or 75mV, respectively.
Which setting should be used? For the best current limit
accuracy, use the 75mV setting. The 30mV setting will
allow for the use of very low DCR inductors or sense
resistors, but at the expense of current limit accuracy.
The 50mV setting is a good balance between the two. For
single output dual phase applications (see Figure 21), use
the 50mV or 75mV setting for optimal current sharing.
VIN
INTVCC
BOOST
TG
LTC3850
BG
PGND
SENSE+
SENSE–
SGND
RF
The SENSE+ and SENSE– pins are the inputs to the current
comparators. The common mode input voltage range of
the current comparators is 0V to 5V. Both SENSE pins
are high impedance inputs with small base currents of
less than 1µA. When the SENSE pins ramp up from 0V
to 1.4V, the small base currents flow out of the SENSE
pins. When the SENSE pins ramp down from 5V to 1.1V,
the small base currents flow into the SENSE pins. The
high impedance inputs to the current comparators allow
accurate DCR sensing. However, care must be taken not
to float these pins during normal operation.
Filter components mutual to the sense lines should be
placed close to the LTC3850, and the sense lines should
run close together to a Kelvin connection underneath the
current sense element (shown in Figure 1). Sensing current elsewhere can effectively add parasitic inductance
and capacitance to the current sense element, degrading
the information at the sense terminals and making the
programmed current limit unpredictable. If DCR sensing
is used (Figure 2b), sense resistor R1 should be placed
TO SENSE FILTER,
NEXT TO THE CONTROLLER
COUT
INDUCTOR OR RSENSE
VIN
INTVCC
SENSE RESISTOR
PLUS PARASITIC
INDUCTANCE
BOOST
VIN
INDUCTOR
TG
LTC3850
VOUT
ESL
38501 F01
Figure 1. Sense Lines Placement
with Inductor or Sense Resistor
VIN
RS
SW
SENSE+ and SENSE– Pins
L
SW
DCR
VOUT
BG
CF • 2RF ≤ ESL/RS
POLE-ZERO
CANCELLATION
PGND
R1
SENSE+
C1*
CF
R2
SENSE–
SGND
RF
38501 F02b
38501 F02a
*PLACE C1 NEAR SENSE+,
SENSE– PINS
FILTER COMPONENTS
PLACED NEAR SENSE PINS
(2a) Using a Resistor to Sense Current
R1||R2 × C1 =
L
DCR
RSENSE(EQ) = DCR
R2
R1 + R2
(2b) Using the Inductor DCR to Sense Current
Figure 2. Two Different Methods of Sensing Current
Rev. D
For more information www.analog.com
13
LTC3850/LTC3850-1
APPLICATIONS INFORMATION
close to the switching node, to prevent noise from coupling into sensitive small-signal nodes. The capacitor C1
should be placed close to the IC pins.
Low Value Resistors Current Sensing
A typical sensing circuit using a discrete resistor is
shown in Figure 2a. RSENSE is chosen based on the
required output current.
The current comparator has a maximum threshold
VSENSE(MAX) determined by the ILIM setting. The input
common mode range of the current comparator is 0V to
5V. The current comparator threshold sets the peak of
the inductor current, yielding a maximum average output
current IMAX equal to the peak value less half the peak-topeak ripple current, ∆IL. To calculate the sense resistor
value, use the equation:
RSENSE =
VSENSE(MAX)
ΔI
I(MAX) + L
2
Because of possible PCB noise in the current sensing
loop, the AC current sensing ripple of ∆VSENSE = ∆IL •
RSENSE also needs to be checked in the design to get a
good signal-to-noise ratio. In general, for a reasonably
good PCB layout, a 15mV ∆VSENSE voltage is recommended as a conservative number to start with, either
for RSENSE or DCR sensing applications.
For previous generation current mode controllers, the
maximum sense voltage was high enough (e.g., 75mV
for the LTC1628 / LTC3728 family) that the voltage drop
across the parasitic inductance of the sense resistor represented a relatively small error. For today’s highest current
density solutions, however, the value of the sense resistor
can be less than 1mΩ and the peak sense voltage can
be as low as 20mV. In addition, inductor ripple currents
greater than 50% with operation up to 1MHz are becoming more common. Under these conditions the voltage
drop across the sense resistor’s parasitic inductance is no
longer negligible. A typical sensing circuit using a discrete
resistor is shown in Figure 2a. In previous generations
of controllers, a small RC filter placed near the IC was
commonly used to reduce the effects of capacitive and
14
inductive noise coupled in the sense traces on the PCB.
A typical filter consists of two series 10Ω resistors connected to a parallel 1000pF capacitor, resulting in a time
constant of 20ns.
This same RC filter, with minor modifications, can be
used to extract the resistive component of the current
sense signal in the presence of parasitic inductance.
For example, Figure 3 illustrates the voltage waveform
across a 2mΩ sense resistor with a 2010 footprint for
the 1.2V/15A converter shown in Figure 18 operating at
100% load. The waveform is the superposition of a purely
resistive component and a purely inductive component.
It was measured using two scope probes and waveform
math to obtain a differential measurement. Based on additional measurements of the inductor ripple current and the
on-time and off-time of the top switch, the value of the
parasitic inductance was determined to be 0.5nH using
the equation:
ESL =
VESL(STEP) tON • tOFF
ΔIL
tON + tOFF
If the RC time constant is chosen to be close to the parasitic inductance divided by the sense resistor (L/R), the
resulting waveform looks resistive again, as shown in
Figure 4. For applications using low maximum sense
voltages, check the sense resistor manufacturer’s data
sheet for information about parasitic inductance. In the
absence of data, measure the voltage drop directly across
the sense resistor to extract the magnitude of the ESL
step and use the equation above to determine the ESL.
However, do not over-filter. Keep the RC time constant less
than or equal to the inductor time constant to maintain a
high enough ripple voltage on VRSENSE.
The above generally applies to high density / high current applications where I(MAX) > 10A and low values of
inductors are used. For applications where I(MAX) < 10A,
set RF to 10 Ohms and CF to 1000pF. This will provide a
good starting point.
The filter components need to be placed close to the
IC. The positive and negative sense traces need to be
routed as a differential pair and Kelvin connected to the
sense resistor.
Rev. D
For more information www.analog.com
LTC3850/LTC3850-1
APPLICATIONS INFORMATION
VESL(STEP)
VSENSE
20mV/DIV
500ns/DIV
Using the inductor ripple current value from the Inductor
Value Calculation section, the target sense resistor value is:
VSENSE(MAX)
RSENSE(EQUIV) =
ΔI
I(MAX) + L
2
To ensure that the application will deliver full load current over the full operating temperature range, choose
the minimum value for the Maximum Current Sense
Threshold (VSENSE(MAX)) in the Electrical Characteristics
table (20mV, 40mV, or 60mV, depending on the state of
the ILIM pin).
38501 F03
Figure 3. Voltage Waveform Measured
Directly Across the Sense Resistor.
Next, determine the DCR of the inductor. Where provided,
use the manufacturer’s maximum value, usually given
at 20°C. Increase this value to account for the temperature coefficient of resistance, which is approximately
0.4%/°C. A conservative value for TL(MAX) is 100°C.
VSENSE
20mV/DIV
500ns/DIV
To scale the maximum inductor DCR to the desired sense
resistor value, use the divider ratio:
38501 F04
Figure 4. Voltage Waveform Measured After the
Sense Resistor Filter. CF = 1000pF, RF = 100Ω.
RD =
Inductor DCR Sensing
R SENSE(EQUIV)
DCR (MAX) at TL(MAX)
For applications requiring the highest possible efficiency
at high load currents, the LTC3850 is capable of sensing
the voltage drop across the inductor DCR, as shown in
Figure 2b. The DCR of the inductor represents the small
amount of DC winding resistance of the copper, which can
be less than 1mΩ for today’s low value, high current inductors. In a high current application requiring such an inductor,
conduction loss through a sense resistor would cost several
points of efficiency compared to DCR sensing.
C1 is usually selected to be in the range of 0.047µF to
0.47µF. This forces R1 || R2 to around 2kΩ, reducing
error that might have been caused by the SENSE pins’
±1µA current.
If the external R1||R2 • C1 time constant is chosen to be
exactly equal to the L/DCR time constant, the voltage drop
across the external capacitor is equal to the drop across
the inductor DCR multiplied by R2/(R1 + R2). R2 scales the
voltage across the sense terminals for applications where
the DCR is greater than the target sense resistor value. To
properly dimension the external filter components, the DCR
of the inductor must be known. It can be measured using
a good RLC meter, but the DCR tolerance is not always the
same and varies with temperature; consult the manufacturers’ data sheets for detailed information.
The sense resistor values are:
The equivalent resistance R1|| R2 is scaled to the room
temperature inductance and maximum DCR:
L
R1||R2 =
(DCR at 20°C) • C1
R1=
R1|| R2
R1• RD
; R2 =
RD
1−RD
The maximum power loss in R1 is related to duty cycle,
and will occur in continuous mode at the maximum
input voltage:
PLOSS R1=
For more information www.analog.com
( VIN(MAX) − VOUT ) • VOUT
R1
Rev. D
15
LTC3850/LTC3850-1
APPLICATIONS INFORMATION
Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
power loss when deciding whether to use DCR sensing or
sense resistors. Light load power loss can be modestly
higher with a DCR network than with a sense resistor,
due to the extra switching losses incurred through R1.
However, DCR sensing eliminates a sense resistor,
reduces conduction losses and provides higher efficiency
at heavy loads. Peak efficiency is about the same with
either method.
To maintain a good signal to noise ratio for the current
sense signal, use a minimum ∆VSENSE of 10mV to 15mV.
For a DCR sensing application, the actual ripple voltage
will be determined by the equation:
ΔVSENSE =
VIN − VOUT VOUT
R1•C1 VIN • fOSC
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constantfrequency architectures by preventing subharmonic
oscillations at high duty cycles. It is accomplished internally by adding a compensating ramp to the inductor
current signal at duty cycles in excess of 40%. Normally,
this results in a reduction of maximum inductor peak current for duty cycles > 40%. However, the LTC3850 uses
a patented scheme that counteracts this compensating
ramp, which allows the maximum inductor peak current
to remain unaffected throughout all duty cycles.
Inductor Value Calculation
Given the desired input and output voltages, the inductor
value and operating frequency fOSC directly determine the
inductor’s peak-to-peak ripple current:
IRIPPLE =
VOUT ⎛ VIN – VOUT ⎞
VIN ⎜⎝ fOSC •L ⎟⎠
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors, and output voltage
ripple. Thus, highest efficiency operation is obtained at
low frequency with a small ripple current. Achieving this,
however, requires a large inductor.
16
A reasonable starting point is to choose a ripple current
that is about 40% of IOUT(MAX). Note that the largest ripple
current occurs at the highest input voltage. To guarantee
that ripple current does not exceed a specified maximum,
the inductor should be chosen according to:
V –V
V
L ≥ IN OUT • OUT
fOSC •IRIPPLE VIN
Inductor Core Selection
Once the inductance value is determined, the type of
inductor must be selected. Core loss is independent of
core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases,
core losses go down. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses
will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Power MOSFET and Schottky Diode
(Optional) Selection
Two external power MOSFETs must be selected for each
controller in the LTC3850: one N-channel MOSFET for
the top (main) switch, and one N-channel MOSFET for
the bottom (synchronous) switch.
The peak-to-peak drive levels are set by the INTVCC
voltage. This voltage is typically 5V during start-up
(see EXTVCC Pin Connection). Consequently, logic-level
threshold MOSFETs must be used in most applications.
The only exception is if low input voltage is expected (VIN
< 5V); then, sub-logic level threshold MOSFETs (VGS(TH)
< 3V) should be used. Pay close attention to the BVDSS
specification for the MOSFETs as well; most of the logic
level MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the
on-resistance RDS(ON) , Miller capacitance CMILLER, input
Rev. D
For more information www.analog.com
LTC3850/LTC3850-1
APPLICATIONS INFORMATION
voltage and maximum output current. Miller capacitance,
CMILLER, can be approximated from the gate charge curve
usually provided on the MOSFET manufacturers’ data
sheet. CMILLER is equal to the increase in gate charge
along the horizontal axis while the curve is approximately
flat divided by the specified change in VDS. This result is
then multiplied by the ratio of the application applied VDS
to the gate charge curve specified VDS. When the IC is
operating in continuous mode the duty cycles for the top
and bottom MOSFETs are given by:
V
Main Switch Duty Cycle = OUT
VIN
V –V
Synchronous Switch Duty Cycle = IN OUT
VIN
The MOSFET power dissipations at maximum output current are given by:
PMAIN =
The term (1 + d) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs Temperature curve, but
d = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
The optional Schottky diodes conduct during the dead
time between the conduction of the two power MOSFETs.
These prevent the body diodes of the bottom MOSFETs
from turning on, storing charge during the dead time and
requiring a reverse recovery period that could cost as
much as 3% in efficiency at high VIN. A 1A to 3A Schottky
is generally a good compromise for both regions of operation due to the relatively small average current. Larger
diodes result in additional transition losses due to their
larger junction capacitance.
Soft-Start and Tracking
VOUT
(IMAX )2 (1+ δ )RDS(ON) +
VIN
The LTC3850 has the ability to either soft-start by itself
with a capacitor or track the output of another channel
or external supply. When one particular channel is configured to soft-start by itself, a capacitor should be connected to its TK/SS pin. This channel is in the shutdown
state if its RUN pin voltage is below 1.2V. Its TK/SS pin is
actively pulled to ground in this shutdown state.
⎞
( VIN )2 ⎛⎜⎝ IMAX
⎟ (RDR ) (CMILLER ) •
2 ⎠
⎡
1 ⎤
1
+
⎢
⎥ • fOSC
⎢⎣ VINTVCC – VTH(MIN) VTH(MIN) ⎥⎦
or during a short-circuit when the synchronous switch is
on close to 100% of the period.
V –V
2
PSYNC = IN OUT (IMAX ) (1+ δ )RDS(ON)
VIN
where d is the temperature dependency of RDS(ON) and
RDR (approximately 2Ω) is the effective driver resistance
at the MOSFET’s Miller threshold voltage. VTH(MIN) is the
typical MOSFET minimum threshold voltage.
Both MOSFETs have I2R losses while the topside N-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For VIN < 20V
the high current efficiency generally improves with larger
MOSFETs, while for VIN > 20V the transition losses rapidly increase to the point that the use of a higher RDS(ON)
device with lower CMILLER actually provides higher efficiency. The synchronous MOSFET losses are greatest at
high input voltage when the top switch duty factor is low
Once the RUN pin voltage is above 1.2V, the channel powers up. A soft-start current of 1.3µA then starts to charge
its soft-start capacitor. Note that soft-start or tracking is
achieved not by limiting the maximum output current of
the controller but by controlling the output ramp voltage
according to the ramp rate on the TK/SS pin. Current
foldback is disabled during this phase to ensure smooth
soft-start or tracking. The soft-start or tracking range is
defined to be the voltage range from 0V to 0.8V on the
TK/SS pin. The total soft-start time can be calculated as:
t SOFTSTART = 0.8 •
C SS
1.3µA
Regardless of the mode selected by the MODE/PLLIN pin,
the regulator will always start in pulse-skipping mode up
to TK/SS = 0.64V. Between TK/SS = 0.64V and 0.74V, it
will operate in forced continuous mode and revert to the
Rev. D
For more information www.analog.com
17
LTC3850/LTC3850-1
APPLICATIONS INFORMATION
selected mode once TK/SS > 0.74V. The output ripple is
minimized during the 100mV forced continuous mode
window ensuring a clean PGOOD signal.
When the channel is configured to track another supply,
the feedback voltage of the other supply is duplicated by
a resistor divider and applied to the TK/SS pin. Therefore,
the voltage ramp rate on this pin is determined by the
ramp rate of the other supply’s voltage. Note that the
small soft-start capacitor charging current is always
flowing, producing a small offset error. To minimize this
error, select the tracking resistive divider value to be small
enough to make this error negligible.
In order to track down another channel or supply after
the soft-start phase expires, the LTC3850 is forced into
continuous mode of operation as soon as VFB is below the
undervoltage threshold of 0.74V regardless of the setting
on the MODE/PLLIN pin. However, the LTC3850 should
always be set in force continuous mode tracking down
when there is no load. After TK/SS drops below 0.1V, its
channel will operate in discontinuous mode.
Output Voltage Tracking
The LTC3850 allows the user to program how its output ramps up and down by means of the TK/SS pins.
Through these pins, the output can be set up to
either coincidentally or ratiometrically track another
supply’s output, as shown in Figure 5. In the following
discussions, VOUT1 refers to the LTC3850’s output 1 as a
master channel and VOUT2 refers to the LTC3850’s output
2 as a slave channel. In practice, though, either phase can
be used as the master. To implement the coincident tracking in Figure 5a, connect an additional resistive divider to
VOUT1 and connect its midpoint to the TK/SS pin of the
slave channel. The ratio of this divider should be the same
as that of the slave channel’s feedback divider shown in
Figure 6a. In this tracking mode, VOUT1 must be set higher
than VOUT2. To implement the ratiometric tracking, the
ratio of the VOUT2 divider should be exactly the same as
the master channel’s feedback divider. By selecting different resistors, the LTC3850 can achieve different modes
of tracking including the two in Figure 5.
So which mode should be programmed? While either
mode in Figure 5 satisfies most practical applications,
18
some tradeoffs exist. The ratiometric mode saves a pair
of resistors, but the coincident mode offers better output
regulation. This can be better understood with the help
of Figure 7. At the input stage of the slave channel’s error
amplifier, two common anode diodes are used to clamp
the equivalent reference voltage and an additional diode
is used to match the shifted common mode voltage. The
top two current sources are of the same amplitude. In the
coincident mode, the TK/SS voltage is substantially higher
than 0.8V at steady state and effectively turns off D1. D2
and D3 will therefore conduct the same current and offer
tight matching between VFB2 and the internal precision
0.8V reference. In the ratiometric mode, however, TK/SS
equals 0.8V at steady state. D1 will divert part of the bias
current to make VFB2 slightly lower than 0.8V.
Although this error is minimized by the exponential I-V
characteristic of the diode, it does impose a finite amount
of output voltage deviation. Furthermore, when the master
channel’s output experiences dynamic excursion (under
load transient, for example), the slave channel output will
be affected as well. For better output regulation, use the
coincident tracking mode instead of ratiometric.
INTVCC Regulators and EXTVCC
The LTC3850 features an NPN linear regulator that supplies power to INTVCC from the VIN supply. INTVCC powers the gate drivers and much of the LTC3850’s internal
circuitry. The linear regulator regulates the voltage at the
INTVCC pin to 5V when VIN is greater than 6.5V. EXTVCC
connects to INTVCC through a P-channel MOSFET and can
supply the needed power when its voltage is higher than
4.7V. Each of these can supply a peak current of 100mA
and must be bypassed to ground with a minimum of 1µF
ceramic capacitor or low ESR electrolytic capacitor. No
matter what type of bulk capacitor is used, an additional
0.1µF ceramic capacitor placed directly adjacent to the
INTVCC and PGND pins is highly recommended. Good
bypassing is needed to supply the high transient currents
required by the MOSFET gate drivers and to prevent interaction between the channels.
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maximum junction temperature rating for the LTC3850 to be
Rev. D
For more information www.analog.com
LTC3850/LTC3850-1
APPLICATIONS INFORMATION
VOUT1
OUTPUT VOLTAGE
OUTPUT VOLTAGE
VOUT1
VOUT2
TIME
VOUT2
TIME
38501 F03a
(5a) Coincident Tracking
38501 F03b
(5b) Ratiometric Tracking
Figure 5. Two Different Modes of Output Voltage Tracking
VOUT1
TO
TK/SS2
PIN
VOUT1
VOUT2
R3
R4
R1
R2
TO
VFB1
PIN
TO
VFB2
PIN
R3
TO
TK/SS2
PIN
R4
VOUT2
R1
R2
TO
VFB1
PIN
TO
VFB2
PIN
R3
R4
38501 F06
(6a) Coincident Tracking Setup
(6b) Ratiometric Tracking Setup
Figure 6. Setup for Coincident and Ratiometric Tracking
I
I
+
TK/SS2
D1
D2
–
0.8V
VFB2
EA2
D3
38501 F07
Figure 7. Equivalent Input Circuit of Error Amplifier
Rev. D
For more information www.analog.com
19
LTC3850/LTC3850-1
APPLICATIONS INFORMATION
exceeded. The INTVCC current, which is dominated by the
gate charge current, may be supplied by either the 5V linear regulator or EXTVCC. When the voltage on the EXTVCC
pin is less than 4.7V, the linear regulator is enabled. Power
dissipation for the IC in this case is highest and is equal
to VIN • IINTVCC. The gate charge current is dependent
on operating frequency as discussed in the Efficiency
Considerations section. The junction temperature can
be estimated by using the equations given in Note 3 of
the Electrical Characteristics. For example, the LTC3850
INTVCC current is limited to less than 24mA from a 24V
supply in the GN package and not using the EXTVCC supply:
1. EXTVCC left open (or grounded). This will cause
INTVCC to be powered from the internal 5V regulator
resulting in an efficiency penalty of up to 10% at high
input voltages.
TJ = 70°C + (24mA)(24V)(95°C/W) = 125°C
4. EXTVCC connected to an output-derived boost network. For 3.3V and other low voltage regulators,
efficiency gains can still be realized by connecting
EXTVCC to an output-derived voltage that has been
boosted to greater than 4.7V.
To prevent the maximum junction temperature from
being exceeded, the input supply current must be
checked while operating in continuous conduction mode
(MODE/PLLIN = SGND) at maximum VIN. When the
voltage applied to EXTVCC rises above 4.7V, the INTVCC
linear regulator is turned off and the EXTVCC is connected to the INTVCC. The EXTVCC remains on as long
as the voltage applied to EXTVCC remains above 4.5V.
Using the EXTVCC allows the MOSFET driver and control power to be derived from one of the LTC3850’s
switching regulator outputs during normal operation and
from the INTVCC when the output is out of regulation
(e.g., start-up, short-circuit). If more current is required
through the EXTVCC than is specified, an external Schottky
diode can be added between the EXTVCC and INTVCC pins.
Do not apply more than 6V to the EXTVCC pin and make
sure that EXTVCC < VIN.
2. EXTVCC connected directly to VOUT. This is the
normal connection for a 5V regulator and provides
the highest efficiency.
3. EXTVCC connected to an external supply. If a 5V
external supply is available, it may be used to power
EXTVCC providing it is compatible with the MOSFET
gate drive requirements.
For applications where the main input power is 5V, tie
the VIN and INTVCC pins together and tie the combined
pins to the 5V input with a 1Ω or 2.2Ω resistor as shown
in Figure 8 to minimize the voltage drop caused by the
gate charge current. This will override the INTVCC linear
regulator and will prevent INTVCC from dropping too low
due to the dropout voltage. Make sure the INTVCC voltage
is at or exceeds the RDS(ON) test voltage for the MOSFET
which is typically 4.5V for logic level devices.
LTC3850
VIN
RVIN
INTVCC
CINTVCC
4.7µF
1Ω
5V
+
Significant efficiency and thermal gains can be realized
by powering INTVCC from the output, since the VIN current resulting from the driver and control currents will be
scaled by a factor of (Duty Cycle)/(Switcher Efficiency).
Figure 8. Setup for a 5V Input
Tying the EXTVCC pin to a 5V supply reduces the junction
temperature in the previous example from 125°C to:
Topside MOSFET Driver Supply (CB, DB)
TJ = 70°C + (24mA)(5V)(95°C/W) = 81°C
However, for 3.3V and other low voltage outputs, additional circuitry is required to derive INTVCC power from
the output.
The following list summarizes the four possible connections for EXTVCC:
20
CIN
38501 F08
External bootstrap capacitors CB connected to the
BOOST pins supply the gate drive voltages for the topside MOSFETs. Capacitor CB in the Functional Diagram
is charged though external diode DB from INTVCC when
the SW pin is low. When one of the topside MOSFETs is
to be turned on, the driver places the CB voltage across
the gate source of the desired MOSFET. This enhances
Rev. D
For more information www.analog.com
LTC3850/LTC3850-1
APPLICATIONS INFORMATION
the MOSFET and turns on the topside switch. The switch
node voltage, SW, rises to VIN and the BOOST pin follows.
With the topside MOSFET on, the boost voltage is above
the input supply: VBOOST = VIN + VINTVCC. The value of the
boost capacitor CB needs to be 100 times that of the total
input capacitance of the topside MOSFET(s). The reverse
breakdown of the external Schottky diode must be greater
than VIN(MAX). When adjusting the gate drive level, the
final arbiter is the total input current for the regulator. If
a change is made and the input current decreases, then
the efficiency has improved. If there is no change in input
current, then there is no change in efficiency.
Undervoltage Lockout
The LTC3850 has two functions that help protect the controller in case of undervoltage conditions. A precision
UVLO comparator constantly monitors the INTVCC voltage
to ensure that an adequate gate-drive voltage is present.
It locks out the switching action when INTVCC is below
3V. To prevent oscillation when there is a disturbance on
the INTVCC, the UVLO comparator has 500mV of precision hysteresis.
Another way to detect an undervoltage condition is to
monitor the VIN supply. Because the RUN pins have a
precision turn-on reference of 1.2V, one can use a resistor
divider to VIN to turn on the IC when VIN is high enough.
An extra 4.5µA of current flows out of the RUN pin once
the RUN pin voltage passes 1.2V. One can program the
hysteresis of the run comparator by adjusting the values
of the resistive divider. For accurate VIN undervoltage
detection, VIN needs to be higher than 4V.
CIN and COUT Selection
The selection of CIN is simplified by the 2-phase architecture
and its impact on the worst-case RMS current drawn through
the input network (battery/fuse/capacitor). It can be shown
that the worst-case capacitor RMS current occurs when only
one controller is operating. The controller with the highest
(VOUT)(IOUT) product needs to be used in the formula below
to determine the maximum RMS capacitor current requirement. Increasing the output current drawn from the other
controller will actually decrease the input RMS ripple current from its maximum value. The out-of-phase technique
typically reduces the input capacitor’s RMS ripple current by
a factor of 30% to 70% when compared to a single phase
power supply solution.
In continuous mode, the source current of the top MOSFET
is a square wave of duty cycle (VOUT)/(VIN). To prevent
large voltage transients, a low ESR capacitor sized for the
maximum RMS current of one channel must be used. The
maximum RMS capacitor current is given by:
CIN Required IRMS ≈
1/2
IMAX
⎡⎣( VOUT ) ( VIN – VOUT ) ⎤⎦
VIN
This formula has a maximum at VIN = 2VOUT, where IRMS
= IOUT/2. This simple worst-case condition is commonly
used for design because even significant deviations do
not offer much relief. Note that capacitor manufacturers’
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature
than required. Several capacitors may be paralleled to
meet size or height requirements in the design. Due to
the high operating frequency of the LTC3850, ceramic
capacitors can also be used for CIN. Always consult the
manufacturer if there is any question.
The benefit of the LTC3850 2-phase operation can be
calculated by using the equation above for the higher
power controller and then calculating the loss that would
have resulted if both controller channels switched on at
the same time. The total RMS power lost is lower when
both controllers are operating due to the reduced overlap
of current pulses required through the input capacitor’s
ESR. This is why the input capacitor’s requirement calculated above for the worst-case controller is adequate
for the dual controller design. Also, the input protection
fuse resistance, battery resistance, and PC board trace
resistance losses are also reduced due to the reduced
peak currents in a 2-phase system. The overall benefit of
a multiphase design will only be fully realized when the
source impedance of the power supply/battery is included
in the efficiency testing. The sources of the top MOSFETs
should be placed within 1cm of each other and share a
common CIN(s). Separating the sources and CIN may produce undesirable voltage and current resonances at VIN.
A small (0.1µF to 1µF) bypass capacitor between the chip
VIN pin and ground, placed close to the LTC3850, is also
For more information www.analog.com
Rev. D
21
LTC3850/LTC3850-1
APPLICATIONS INFORMATION
suggested. A 2.2Ω – 10Ω resistor placed between CIN
(C1) and the VIN pin provides further isolation between
the two channels.
The selection of COUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement
is satisfied, the capacitance is adequate for filtering. The
output ripple (∆VOUT) is approximated by:
⎛
1 ⎞
ΔVOUT ≈IRIPPLE ⎜ ESR +
8fCOUT ⎟⎠
⎝
the soft-start or tracking up. Under short-circuit conditions with very low duty cycles, the LTC3850 will begin
cycle skipping in order to limit the short-circuit current.
In this situation the bottom MOSFET will be dissipating
most of the power but less than in normal operation. The
short-circuit ripple current is determined by the minimum
on-time tON(MIN) of the LTC3850 (≈ 90ns), the input voltage and inductor value:
ΔIL(SC) = tON(MIN) •
VIN
L
where f is the operating frequency, COUT is the output
capacitance and IRIPPLE is the ripple current in the inductor. The output ripple is highest at maximum input voltage
since IRIPPLE increases with input voltage.
The resulting short-circuit current is:
Setting Output Voltage
Phase-Locked Loop and Frequency Synchronization
The LTC3850 output voltages are each set by an external
feedback resistive divider carefully placed across the output, as shown in Figure 9. The regulated output voltage
is determined by:
The LTC3850 has a phase-locked loop (PLL) comprised of
an internal voltage-controlled oscillator (VCO) and a phase
detector. This allows the turn-on of the top MOSFET of
controller 1 to be locked to the rising edge of an external
clock signal applied to the MODE/PLLIN pin. The turn-on
of controller 2’s top MOSFET is thus 180 degrees outof-phase with the external clock. The phase detector is
an edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
⎛ R ⎞
VOUT = 0.8V • ⎜ 1+ B ⎟
⎝ RA ⎠
To improve the frequency response, a feed-forward
capacitor, CFF , may be used. Great care should be taken
to route the VFB line away from noise sources, such as
the inductor or the SW line.
VOUT
1/2 LTC3850
RB
CFF
VFB
RA
38501 F09
Figure 9. Setting Output Voltage
Fault Conditions: Current Limit and Current Foldback
The LTC3850 includes current foldback to help limit load
current when the output is shorted to ground. If the output falls below 50% of its nominal output level, then the
maximum sense voltage is progressively lowered from
its maximum programmed value to one-third of the maximum value. Foldback current limiting is disabled during
22
ISC =
1/3 VSENSE(MAX)
RSENSE
1
– ΔIL(SC)
2
The output of the phase detector is a pair of complementary current sources that charge or discharge the external
filter network connected to the FREQ/PLLFLTR pin. The
relationship between the voltage on the FREQ/PLLFLTR
pin and operating frequency is shown in Figure 10 and
specified in the Electrical Characteristics table. Note that
the LTC3850 can only be synchronized to an external
clock whose frequency is within range of the LTC3850’s
internal VCO. This is guaranteed to be between 250kHz and
780kHz. A simplified block diagram is shown in Figure 11.
If no clock is applied to MODE/PLLIN pin, the FREQ/
PLLFLTR pin will be high impedance.
If the external clock frequency is greater than the internal oscillator’s frequency, fOSC , then current is sourced
Rev. D
For more information www.analog.com
LTC3850/LTC3850-1
APPLICATIONS INFORMATION
Typically, the external clock (on MODE/PLLIN pin)
input high threshold is 1.6V, while the input low threshold
is 1V.
900
800
FREQUENCY (kHz)
700
600
Minimum On-Time Considerations
500
Minimum on-time tON(MIN) is the smallest time duration
that the LTC3850 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that
400
300
200
100
0
0
0.5
1
1.5
2
FREQ/PLLFLTR PIN VOLTAGE (V)
2.5
38501 F10
Figure 10. Relationship Between Oscillator
Frequency and Voltage at the FREQ/PLLFLTR Pin
2.4V
EXTERNAL
OSCILLATOR
MODE/
PLLIN
RLP
CLP
FREQ/
PLLFLTR
DIGITAL
PHASE/
FREQUENCY
DETECTOR
VCO
38501 F11
Figure 11. Phase-Locked Loop Block Diagram
continuously from the phase detector output, pulling
up the FREQ/PLLFLTR pin. When the external clock frequency is less than fOSC , current is sunk continuously,
pulling down the FREQ/PLLFLTR pin. If the external and
internal frequencies are the same but exhibit a phase
difference, the current sources turn on for an amount
of time corresponding to the phase difference. The voltage on the FREQ/PLLFLTR pin is adjusted until the phase
and frequency of the internal and external oscillators are
identical. At the stable operating point, the phase detector output is high impedance and the filter capacitor CLP
holds the voltage.
The loop filter components, CLP and RLP, smooth out the current pulses from the phase detector and provide a stable input
to the voltage-controlled oscillator. The filter components CLP
and RLP determine how fast the loop acquires lock. Typically
RLP = 10k and CLP is 2200pF to 0.01µF.
V
t ON(MIN) < OUT
VIN (f)
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The minimum on-time for the LTC3850 is approximately
90ns, with reasonably good PCB layout, minimum 30%
inductor current ripple and at least 10mV – 15mV ripple
on the current sense signal. The minimum on-time can be
affected by PCB switching noise in the voltage and current
loop. As the peak sense voltage decreases the minimum
on-time gradually increases to 130ns. This is of particular concern in forced continuous applications with low
ripple current at light loads. If the duty cycle drops below
the minimum on-time limit in this situation, a significant
amount of cycle skipping can occur with correspondingly
larger current and voltage ripple.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage of input power.
Rev. D
For more information www.analog.com
23
LTC3850/LTC3850-1
APPLICATIONS INFORMATION
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3850 circuits: 1) IC VIN current, 2) INTVCC
regulator current, 3) I2R losses, 4) Topside MOSFET transition losses.
1. The VIN current is the DC supply current given in
the Electrical Characteristics table, which excludes
MOSFET driver and control currents. VIN current typically results in a small (1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel with COUT , causing a rapid drop in VOUT . No regulator
can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load
switch resistance is low and it is driven quickly. If the ratio
of CLOAD to COUT is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited
to approximately 25 • CLOAD . Thus a 10µF capacitor would
require a 250µs rise time, limiting the charging current
to about 200mA.
PC Board Layout Checklist
When laying out the printed circuit board, the following checklist should be used to ensure proper operation
of the IC. These items are also illustrated graphically in
the layout diagram of Figure 12. Figure 13 illustrates the
current waveforms present in the various branches of
the 2-phase synchronous regulators operating in the
continuous mode. Check the following in your layout:
1. Are the top N-channel MOSFETs M1 and M3 located
within 1cm of each other with a common drain connection at CIN? Do not attempt to split the input decoupling for the two channels as it can cause a large resonant loop.
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return
of CINTVCC must return to the combined COUT (–) terminals. The VFB and ITH traces should be as short as possible. The path formed by the top N-channel MOSFET,
Schottky diode and the CIN capacitor should have short
leads and PC trace lengths. The output capacitor (–)
terminals should be connected as close as possible
to the (–) terminals of the input capacitor by placing
the capacitors next to each other and away from the
Schottky loop described above.
3. Do the LTC3850 VFB pins’ resistive dividers connect to
the (+) terminals of COUT? The resistive divider must be
connected between the (+) terminal of COUT and signal
ground. The feedback resistor connections should not
be along the high current input feeds from the input
capacitor(s).
4. Are the SENSE+ and SENSE– leads routed together
with minimum PC trace spacing? The filter capacitor
between SENSE+ and SENSE– should be as close as
possible to the IC. Ensure accurate current sensing with
Kelvin connections at the sense resistor or inductor,
whichever is used for current sensing.
Rev. D
For more information www.analog.com
25
LTC3850/LTC3850-1
APPLICATIONS INFORMATION
ITH1
TK/SS1
RPU2
PGOOD
PGOOD
VPULL-UP
VFB1
L1
SENSE1+
TG1
SENSE1–
SW1
CB1
ILIM
BG1
MODE/PLLIN
1µF
CERAMIC
VIN
INTVCC
SENSE2+
BG2
TK/SS2
+
SENSE2–
CIN
CINTVCC
COUT2
1µF
CERAMIC
M3
BOOST2
GND
+
EXTVCC
ITH2
COUT1
PGND
SGND
VFB2
RIN
CVIN
D1
+
VIN
RUN1
RUN2
M2
VOUT1
+
fIN
M1
BOOST1
PLLLPF
RSENSE
M4
D2
CB2
SW2
RSENSE
TG2
VOUT2
L2
38501 F12
Figure 13. Recommended Printed Circuit Layout Diagram
SW1
L1
D1
RSENSE1
VOUT1
COUT1
RL1
VIN
RIN
CIN
SW2
BOLD LINES INDICATE
HIGH SWITCHING
CURRENT. KEEP LINES
TO A MINIMUM LENGTH.
D2
L2
RSENSE2
VOUT2
COUT2
RL2
38501 F13
Figure 12. Branch Current Waveforms
26
Rev. D
For more information www.analog.com
LTC3850/LTC3850-1
APPLICATIONS INFORMATION
5. Is the INTVCC decoupling capacitor connected close
to the IC, between the INTVCC and the power ground
pins? This capacitor carries the MOSFET drivers current peaks. An additional 1µF ceramic capacitor placed
immediately next to the INTVCC and PGND pins can
help improve noise performance substantially.
6. Keep the switching nodes (SW1, SW2), top gate nodes
(TG1, TG2), and boost nodes (BOOST1, BOOST2) away
from sensitive small-signal nodes, especially from the
opposite channel’s voltage and current sensing feedback pins. All of these nodes have very large and fast
moving signals and therefore should be kept on the
“output side” of the LTC3850 and occupy minimum
PC trace area. If DCR sensing is used, place the top
resistor (Figure 2b, R1) close to the switching node.
7. Use a modified “star ground” technique: a low impedance, large copper area central grounding point on the
same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTVCC
decoupling capacitor, the bottom of the voltage feedback resistive divider and the SGND pin of the IC.
PC Board Layout Debugging
Start with one controller at a time. It is helpful to use a
DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope
to the internal oscillator and probe the actual output voltage as well. Check for proper performance over the operating voltage and current range expected in the application.
The frequency of operation should be maintained over
the input voltage range down to dropout and until the
output load drops below the low current operation
threshold—typically 10% of the maximum designed current level in Burst Mode operation.
The duty cycle percentage should be maintained from
cycle to cycle in a well-designed, low noise PCB implementation. Variation in the duty cycle at a subharmonic
rate can suggest noise pickup at the current or voltage sensing inputs or inadequate loop compensation.
Overcompensation of the loop can be used to tame a
poor PC layout if regulator bandwidth optimization is
not required. Only after each controller is checked for
its individual performance should both controllers be
turned on at the same time. A particularly difficult region
of operation is when one controller channel is nearing its
current comparator trip point when the other channel is
turning on its top MOSFET. This occurs around 50% duty
cycle on either channel due to the phasing of the internal
clocks and may cause minor duty cycle jitter.
Reduce VIN from its nominal level to verify operation
of the regulator in dropout. Check the operation of the
undervoltage lockout circuit by further lowering VIN while
monitoring the outputs to verify operation.
Investigate whether any problems exist only at higher output currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
for inductive coupling between CIN, Schottky and the top
MOSFET components to the sensitive current and voltage
sensing traces. In addition, investigate common ground
path voltage pickup between these components and the
SGND pin of the IC.
Design Example
As a design example for a two channel medium current regulator, assume VIN = 12V(nominal), VIN =
20V(maximum), VOUT1 = 3.3V, VOUT2 = 1.8V, IMAX1,2 =
5A, and f = 500kHz (see Figure 14).
The regulated output voltages are determined by:
⎛ R ⎞
VOUT = 0.8V • ⎜ 1+ B ⎟
⎝ RA ⎠
Using 20k 1% resistors from both VFB nodes to ground,
the top feedback resistors are (to the nearest 1% standard
value) 63.4k and 25.5k.
The frequency is set by biasing the FREQ/PLLFLTR pin to
1.2V (see Figure 10), using a divider from INTVCC. This
Rev. D
For more information www.analog.com
27
LTC3850/LTC3850-1
APPLICATIONS INFORMATION
4.7µF
D3
M1
0.1µF
L1
3.3µH
VIN PGOOD EXTVCC INTVCC
TG1
TG2
BOOST1
SW1
BG1
6.19k
1%
22µF
50V
1µF
2.2Ω
LTC3850
MODE/PLLIN
ILIM
1.33k
1%
COUT1
100µF
X2
1800pF
20k
1%
4.75k
1%
L2
2.2µH
BOOST2
SW2
BG2
4.12k
1%
10k, 1%
PGND
FREQ/PLLFLTR
SENSE1+
SENSE2+
SENSE1–
SENSE2–
0.1µF
RUN1
63.4k
1%
M2
0.1µF
0.1µF
33pF
VOUT1
3.3V
5A
D4
100pF
1.5k
1%
33pF
RUN2
VFB1
ITH1
TK/SS1
VIN
7V TO
20V
VFB2
ITH2
SGND
TK/SS2
0.1µF
0.1µF
2200pF
3.16k
1%
100pF
5.49k
1%
VOUT2
1.8V
5A
25.5k
1%
COUT2
100µF
X2
20k
1%
38501 F14
L1, L2: COILTRONICS HCP0703
M1, M2: VISHAY SILICONIX Si4816BDY
COUT1, COUT2: TAIYO YUDEN JMK325BJ107MM
Figure 14. High Efficiency Dual 500kHz 3.3V/1.8V Step-Down Converter
voltage will decrease as VIN approaches 5V, lowering the
switching frequency. If a separate 5V supply is connected
to EXTVCC, INTVCC will remain at 5V even if VIN decreases.
The inductance values are based on a 35% maximum
ripple current assumption (1.75A for each channel). The
highest value of ripple current occurs at the maximum
input voltage:
L=
VOUT
f • ΔIL(MAX)
⎛
VOUT ⎞
1−
⎜
⎟
VIN(MAX) ⎠
⎝
the maximum DC value plus one-half the ripple current,
or 5.725A for Channel 1 and 5.7A for Channel 2.
The minimum on-time occurs on Channel 1 at the maximum VIN, and should not be less than 90ns:
t ON(MIN) =
VOUT
VIN(MAX)f
=
1.8V
20V(500kHz)
= 180ns
With ILIM floating, the equivalent RSENSE resistor value
can be calculated by using the minimum value for the
maximum current sense threshold (40mV).
Channel 1 will require 3.2µH, and Channel 2 will require
1.9µH. The next highest standard values are 3.3µH
and 2.2µH. At the nominal input voltage (12V), the ripple
will be:
RSENSE(EQUIV) =
VSENSE(MIN)
=
ΔIL(NOM)
ILOAD(MAX) +
2
⎛
⎞
V
V
ΔIL(NOM) = OUT ⎜ 1− OUT ⎟
f •L ⎝
VIN(NOM) ⎠
40mV
≅ 7mΩ
1.5A
5A +
2
Channel 1 will have 1.45A (29%) ripple, and Channel 2 will
have 1.4A (28%) ripple. The peak inductor current will be
The equivalent RSENSE is the same for Channel 2.
28
Rev. D
For more information www.analog.com
LTC3850/LTC3850-1
APPLICATIONS INFORMATION
The Coiltronics (Cooper) HCP0703-2R2 (20mΩ DCRMAX
at 20°C) and HCP0703-3R3 (30mΩ DCRMAX at 20°C) are
chosen. At 100°C, the estimated maximum DCR values are
26.4mΩ and 39.6mΩ. The divider ratios are:
RD =
and
RSENSE(EQUIV)
DCRMAX at TL(MAX)
=
7mΩ
= 0.26;
26.4mΩ
7mΩ
≅ 0.18
39.6mΩ
For each channel, 0.1µF is selected for C1.
R1||R2 =
(DCRMAX
L
2.2µH
=
at 20°C)•C1 20mΩ • 0.1µF
The respective values for Channel 2 are R1 = 4.12k, R2 =
1.5k; and PLOSS R1 = 8mW.
Burst Mode operation is chosen for high light load efficiency (Figure 15) by floating the MODE/PLLIN pin. Power
loss due to the DCR sensing network is slightly higher
at light loads than would have been the case with a suitable sense resistor (7mΩ). At heavier loads, DCR sensing
provides higher efficiency.
The power dissipation on the topside MOSFET can be easily
estimated. Choosing a Siliconix Si4816BDY dual MOSFET
results in: RDS(ON) = 0.023Ω/0.016Ω, CMILLER @ 100pF.
At maximum input voltage with T(estimated) = 50°C:
PMAIN =
3.3µH
= 1.1k ; and
= 1.1k
30mΩ • 0.1µF
(0.023Ω ) + (20V )2 ⎛⎜⎝
For channel 1, the DCRSENSE filter/divider values are:
R1=
R1||R2 1.1k
=
≅ 6.19k;
RD
0.18
R1• RD 6.19k • 0.18
R2 =
=
≅ 1.33k
1−RD
1− 0.18
The power loss in R1 at the maximum input voltage is:
PLOSS R1=
R1
=
DCR
1
DCR
0.1
60
EFFICIENCY
POWER LOSS
0.1
1
LOAD CURRENT (mA)
10
POWER LOSS (mW)
7mΩ
70
40
0.01
(1/ 3) 50mV – 1 ⎛ 90ns(20V) ⎞ = 2.1A
0.007Ω
PSYNC =
10
90
50
A short-circuit to ground will result in a folded back current of:
2 ⎜⎝
3.3µH ⎟⎠
with a typical value of RDS(ON) and d = (0.005/°C)(20)
= 0.1. The resulting power dissipated in the bottom
MOSFET is:
100
80
5A ⎞
⎟ ( 2Ω ) (100pF ) •
2⎠
1 ⎤
⎡ 1
⎢⎣ 5 – 2.3 + 2.3 ⎥⎦ ( 500kHz ) = 186mW
ISC =
(20V − 3.3V)• 3.3V
= 9mW
6.19k
EFFICIENCY (%)
(VIN(MAX) − VOUT )• VOUT
3.3V 2
(5) [1+(0.005)(50°C – 25°C)] •
20V
0.01
20V – 3.3V
(2.1A )2 (1.125)(0.016Ω)
20V
= 66mW
which is less than under full-load conditions.
CIN is chosen for an RMS current rating of at least 2A at
temperature assuming only channel 1 or 2 is on. COUT is
chosen with an ESR of 0.02Ω for low output ripple. The
output ripple in continuous mode will be highest at the
maximum input voltage. The output voltage ripple due to
ESR is approximately:
VORIPPLE = RESR (∆IL) = 0.02Ω(1.5A) = 30mVP–P
38501 F15
Figure 15. Design Example Efficiency vs Load
Rev. D
For more information www.analog.com
29
LTC3850/LTC3850-1
TYPICAL APPLICATIONS
VIN
7V TO
24V
22µF
50V
2.2Ω
1µF
4.7µF
D3
M1
0.1µF
L2
2.2µH
BOOST1
SW1
BG1
10Ω
15pF
+
10Ω
63.4k
1%
COUT1
220µF
TG2
LTC3850
M2
0.1µF
20k
1%
1000pF
100pF
10k
1%
L2
3.3µH
BOOST2
SW2
BG2
MODE/PLLIN
PGND
ILIM
FREQ/PLLFLTR
SENSE1+
SENSE2+
SENSE1–
SENSE2–
10k
1%
10Ω
1000pF
8mΩ
VOUT1
3.3V
5A
D4
VIN PGOOD INTVCC
TG1
1000pF
RUN1
TK/SS1
EXTVCC
VFB2
ITH2
0.1µF
SGND
105k
1%
1000pF
TK/SS2
0.1µF
10pF
10Ω
RUN2
VFB1
ITH1
8mΩ
3.16k
1%
15k
1%
100pF
20k
1%
VOUT2
5V
5A
+
COUT2
150µF
38501 F16
L1: TDK RLF 7030T-2R2M5R4
L2: TDK ULF10045T-3R3N6R9
COUT1: SANYO 4TPE220MF
COUT2: SANYO 6TPE150MI
Figure 16. 3.3V/5A, 5V/5A Converter Using Sense Resistors
30
Rev. D
For more information www.analog.com
For more information www.analog.com
25.5k
20k
C12
100pF
C11
1000pF
C7
1000pF
C6
100pF
CSS
0.1µF
R18
4.99k
R12
7.5k
2.10k
C15
47pF
C10
33pF
BOOST2
PGND
BG2
INTVCC
C5
0.1µF
PGOOD
CVCC
4.7µF
CB2
0.1µF
D4
CMDSH-3
D3
CMDSH-3
CB1
0.1µF
CVIN
1µF
L2
0.68µH
M4
RJK0301DPB
R30
4.02k
M3
HAT2168H
PGND
GND
M2
RJK0301DPB
R27
L1
4.02k 0.68µH
M1
HAT2168H
Figure 17. 2.5V/15A, 1.8V/15A Converter with DCR Sensing and Coincident Rail Tracking
FSW = 350kHz
RPG
100k
SENSE2+ SGND RUN2 ILIM EXTVCC PGOOD SW2 TG2
SENSE2–
TK/SS2
ITH2
VFB2
VIN
VFB1
LTC3850
BG1
BOOST1
ITH1
TK/SS1
SENSE1– SENSE1+ RUN1 FREQ/ MODE/ SW1 TG1
PLLFLTR PLLIN
L1, L2: VISHAY IHLP5050EZ-01 0.68µH
COUT1, COUT2: SANYO 4TPD330M
R4
25.5k
R3
20k
R2
20k
R1
43.2k
C4
0.1µF
10k
38501 TA02
+
+
RVIN
2.2Ω
COUT2
330µF
4V
2X
COUT1
330µF
4V
2X
10µF
2x +
VOUT2
1.8V/
15A
VOUT1
2.5V/
15A
CIN
180µF
VIN
7V TO 14V
LTC3850/LTC3850-1
TYPICAL APPLICATIONS
Rev. D
31
32
CSS2
0.1µF
C12
100pF
C11
1000pF
C7
1000pF
C6
100pF
CSS1
0.1µF
R18
5.9k
R12
5.9k
For more information www.analog.com
R20
100Ω
R10
100Ω
R5
10k
PLLIN
400kHz
BOOST2
PGND
BG2
INTVCC
C5
1000pF
RPG
100k
PGOOD
CVCC
4.7µF
CB2
0.1µF
D4
CMDSH-3
D3
CMDSH-3
CB1
0.1µF
RVIN
2.2Ω
CVIN
1µF
M4
RJK0301DPB
M3
RJK0305DPB
PGND
GND
M2
RJK0301DPB
M1
RJK0305DPB
L2
0.4µH
L1
0.4µH
Figure 18. 1.5V/15A, 1.2V/15A Core-I/O Converter with Sense Resistor Synchronized at 400kHz
R22
100Ω
SENSE2+ SGND RUN2 ILIM EXTVCC PGOOD SW2 TG2
SENSE2–
TK/SS2
ITH2
VFB2
VIN
VFB1
LTC3850
BG1
BOOST1
ITH1
TK/SS1
SENSE1– SENSE1+ RUN1 FREQ/ MODE/ SW1 TG1
PLLFLTR PLLIN
L1, L2: VITEC 59PR9875
COUT1, COUT2: 2R5TPE330M9
R4
10k
R3
20k
R2
20k
R1
17.8k
C4
1000pF
R9
100Ω
C2
0.01µF
38501 F18
RSENSE2
0.002Ω
RSENSE1
0.002Ω
+
COUT2
330µF
2.5V
2X
COUT1
330µF
2.5V
2X
+
10µF
2x
+
C1
1000pF
VOUT2
1.2V/15A
VOUT1
1.5V/15A
CIN
180µF
VIN
7V TO 14V
LTC3850/LTC3850-1
TYPICAL APPLICATIONS
Rev. D
LTC3850/LTC3850-1
TYPICAL APPLICATIONS
5V ± 0.5V
4.7µF
6.3V
2x
1Ω
4.7µF
D3
M1
TG1
0.1µF
L1
0.75µH
BOOST1
SW1
BG1
1.2k
1%
PLLIN
750kHz
2.94k
1%
LTC3850
ILIM
COUT1
100µF
X2
0.1µF
L2
0.75µH
BOOST2
SW2
BG2
1.2k
1%
PGND
SENSE1+
SENSE2+
SENSE1–
SENSE2–
0.047µF
TK/SS1
100pF
14k
1%
4.99k
1%
0.047µF
100pF
RUN2
VFB1
ITH1
2200pF
20k
1%
M2
FREQ/PLLFLTR
RUN1
25.5k
1%
D4
TG2
MODE/PLLIN
47pF
VOUT1
1.8V
5A
VIN PGOOD EXTVCC INTVCC
VFB2
ITH2
SGND
0.1µF
1nF
TK/SS2
10k
1%
0.1µF
10k
1%
100pF
2200pF
10nF
COUT2
100µF
X2
20k
1%
14k
1%
VOUT2
1.2V
5A
38501 F19
L1, L2: TOKO FDV0630 0.75µH
M1, M2: VISHAY SILICONIX Si4816BDY
COUT1, COUT2: TAIYO YUDEN JMK325BJ107MM
Figure 19. 1.8V/5A, 1.2V/5A Core-I/O Converter with a 5V Input Synchronized at 750kHz
VIN1
12V
2.2Ω
1µF
4.7µF
4.7µF
D3
M1
0.1µF
L1
2.2µH
VIN PGOOD EXTVCC INTVCC
TG1
TG2
BOOST1
SW1
BG1
3.74k
1%
ILIM
COUT1
100µF
X2
0.1µF
BG2
1.2k
1%
10k
1%
SENSE2+
0.1µF
SENSE1–
10k
1%
L2
0.75µH
BOOST2
SW2
PGND
SENSE1+
2200pF
20k
1%
M2
FREQ/PLLFLTR
SENSE2–
RUN1
43.2k
1%
10k
D4
0.1µF
47pF
VOUT1
2.5V
5A
LTC3850
MODE/PLLIN
1.40k
1%
4.7µF
2x
13.0k
100pF
0.1µF
4.32k
1%
100pF
RUN2
VFB1
ITH1
TK/SS1
VIN2
3.3V
VFB2
ITH2
SGND
2200pF
TK/SS2
0.1µF
3.16k
1%
6.04k
1%
10k
1%
100pF
VOUT2
1.2V
5A
COUT2
100µF
X2
20k
1%
38501 F20
L1: TOKO FDV0630 2.2µH
L2: TOKO FDV0630 0.75µH
M1, M2: VISHAY SILICONIX Si4816BDY
COUT1, COUT2: TAIYO YUDEN JMK325BJ107MM
Figure 20. 2.5V/5A, 1.2V/5A Core-I/O Converter with Dual Inputs
Rev. D
For more information www.analog.com
33
LTC3850/LTC3850-1
PACKAGE DESCRIPTION
GN Package
28-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641 Rev B)
.386 – .393*
(9.804 – 9.982)
.045 ±.005
28 27 26 25 24 23 22 21 20 19 18 17 1615
.254 MIN
.033
(0.838)
REF
.150 – .165
.229 – .244
(5.817 – 6.198)
.0165 ±.0015
.150 – .157**
(3.810 – 3.988)
.0250 BSC
1
RECOMMENDED SOLDER PAD LAYOUT
.015 ±.004
× 45°
(0.38 ±0.10)
.0075 – .0098
(0.19 – 0.25)
2 3
4
5 6
7
8
.0532 – .0688
(1.35 – 1.75)
9 10 11 12 13 14
.004 – .0098
(0.102 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
.008 – .012
(0.203 – 0.305)
TYP
.0250
(0.635)
BSC
GN28 REV B 0212
3. DRAWING NOT TO SCALE
4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
34
Rev. D
For more information www.analog.com
LTC3850/LTC3850-1
PACKAGE DESCRIPTION
UF Package
28-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1721 Rev A)
0.70 ±0.05
4.50 ±0.05
3.10 ±0.05
2.64 ±0.05
(4 SIDES)
PACKAGE
OUTLINE
0.20 ±0.05
0.40 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 ±0.10
(4 SIDES)
0.75 ±0.05
R = 0.05
TYP
PIN 1
TOP MARK
(NOTE 6)
PIN 1 NOTCH
R = 0.20 TYP
OR 0.35 × 45°
CHAMFER
BOTTOM VIEW—EXPOSED PAD
R = 0.115
TYP
27 28
0.40 ±0.05
1
2
2.64 ±0.10
(4-SIDES)
(UF28) QFN 0106 REVA
0.200 REF
0.00 – 0.05
0.20 ±0.05
0.40 BSC
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
Rev. D
For more information www.analog.com
35
LTC3850/LTC3850-1
PACKAGE DESCRIPTION
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev C)
0.70 ±0.05
4.50 ±0.05
3.10 ±0.05
2.50 REF
2.65 ±0.05
3.65 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
3.50 REF
4.10 ±0.05
5.50 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 ±0.10
(2 SIDES)
R = 0.05
TYP
0.75 ±0.05
PIN 1 NOTCH
R = 0.20 OR 0.35
× 45° CHAMFER
2.50 REF
R = 0.115
TYP
27
28
0.40 ±0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
5.00 ±0.10
(2 SIDES)
3.50 REF
3.65 ±0.10
2.65 ±0.10
(UFD28) QFN 0816 REV C
0.200 REF
0.00 – 0.05
0.25 ±0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGHD-3).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
36
Rev. D
For more information www.analog.com
LTC3850/LTC3850-1
REVISION HISTORY
(Revision history begins at Rev C)
REV
DATE
DESCRIPTION
PAGE NUMBER
C
3/11
Updated Switch Voltage (SW1, SW2) LTC3850I only from 30V to –0.3V to 30V to –5V
2
D
1/20
Added AEC-Q100 Qualified Automotive parts
3
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
more by
information
www.analog.com
37
LTC3850/LTC3850-1
TYPICAL APPLICATION
20k
2.55k
1nF
0.1µF
7.5k
0.1µF
10k
RUN
RJK0305DPB
SENSE1– SENSE1+ RUN1 FREQ
MODE SW1 TG1
220pF
TK/SS1
2.2nF
2.74k
20k
ITH1
BG1
VIN
LTC3850
VIN
7V TO 14V
+
180µF
RJK0301DPB
CMDSH-3
2.2Ω
INTVCC
ITH2
BG2
4.7µF
1µF
PGND
TK/SS2
100µF
2x
CMDSH-3
SENSE2–
VOUT
1.1V/30A
+
COUT1
330µF
2.5V
4x
BOOST2
SENSE2+ SGND RUN2 ILIM EXTVCC PGOOD SW2 TG2
RJK0305DPB
0.1µF
0.1µF
20k
10µF
2x
BOOST1
VFB1
VFB2
0.1µF
2.21k
L1
0.56µH
L2
0.56µH
RJK0301DPB
2.21k
PGOOD
100k
RUN
L1, L2: VISHAY IHLP4040DZ-01 0.56µH
COUT: SANYO 2R5TPE330M9
38501 TA04
FOR SINGLE OUTPUT, DUAL PHASE OPERATION, TIE THE FOLLOWING PINS TOGETHER:
TK/SS1 TO TK/SS2
VFB1 TO VFB1
RUN1 TO RUN2
ITH1 TO ITH2
Figure 21. 1.1V/30A Dual Phase Core Converter, FSW = 400kHz
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LTC1625/
LTC1775
No RSENSE™ Current Mode Synchronous Step-Down Controllers
97% Efficiency, No Sense Resistor, 16-Pin SSOP
LTC1735
High Efficiency Synchronous Step-Down Switching Regulator
Programmable Fixed Frequency from 200kHz to 550kHz
LTC1778
No RSENSE Wide Input Range Synchronous Step-Down Controller
Up to 97% Efficiency, 4V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ (0.9)(VIN),
IOUT Up to 20A
LTC3727A-1
Dual, 2-Phase Synchronous Controller
Very Low Dropout; VOUT ≤ 14V, 4V ≤ VIN ≤ 36V
LTC3728
2-Phase 550kHz, Dual Synchronous Step-Down Controller
20A to 200A PolyPhase® Synchronous Controllers
QFN and SSOP Packages, High Frequency for Smaller L and C
LTC3731
3-Phase, Single Output From 250kHz to 600kHz Synchronous
Step-Down Controller
0.6V ≤ VOUT ≤ 6V, 4.5V ≤ VIN ≤ 32V, IOUT ≤ 60A,
Integrated MOSFET Drivers
LTC3773
Triple Output DC/DC Synchronous Controller
3-Phase Step-Down DC/DC Controller,
3.3V ≤ VIN ≤ 36V, Fixed Frequency 160kHz to 700kHz
LTC3810
100V Current Mode Synchronous Step-Down Switching Controller
0.8V ≤ VOUT ≤ 0.93VIN, 6.2V ≤ VIN ≤ 100V, No RSENSE
LTC3826
Low IQ, Dual, 2-Phase Synchronous Step-Down Controller
30µA IQ, 0.8V ≤ VOUT ≤ 10V, 4V ≤ VIN ≤ 36V
LTC3828
Dual, 2-Phase Synchronous Step-Down Controller with Tracking
Up to Six Phases, 0.8V ≤ VOUT ≤ 7V, 4.5V ≤ VIN ≤ 28V
LTC3834/
LTC3834-1
Low IQ, Synchronous Step-Down Controller
30µA IQ, 0.8V ≤ VOUT ≤ 10V, 4V ≤ VIN ≤ 36V
LT3845
Low IQ, High Voltage Single Output Synchronous Step-Down DC/
DC Controller
1.23V ≤ VOUT ≤ 36V, 4V ≤ VIN ≤ 60V, 120µA IQ
LTC3729
38
Expandable from 2-Phase to 12-Phase, Uses All Surface Mount
Components
Rev. D
01/20
www.analog.com
For more information www.analog.com
ANALOG DEVICES, INC. 2007-2020