LTC3874
PolyPhase Step-Down
Synchronous Slave Controller with
Sub-Milliohm DCR Sensing
FEATURES
DESCRIPTION
n
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The LTC®3874 is a dual PolyPhase® current mode synchronous step-down slave controller. It enables high current,
multi-phase applications when paired with a companion
master controller by extending the phase count. Compatible master controllers include the LTC3884, LTC3866,
LTC3875, LTC3877 and LTC3774. The LTC3874 employs a
unique architecture that enhances the signal-to-noise ratio
of the current sense signal, allowing the use of sub-milliohm
DC resistance power inductors to maximize efficiency while
reducing switching jitter. Its peak current mode architecture
allows for accurate phase to phase current sharing even
for dynamic loads.
Phase Extender for High Phase Count Voltage Rails
Accurate Phase-to-Phase Current Sharing
Sub-Milliohm DCR Current Sensing
Phase-Lockable Fixed Frequency 250kHz to 1MHz
Immediate Response to Master IC's Fault
Up to 12 Phase Operation
Wide VIN Range: 4.5V to 38V
VOUT Range: Up to 3.5V (LOWDCR Pin = INTVCC)
Up to 5.5V (LOWDCR Pin = OV)
n Proprietary Current Mode Control Loop
n Programmable CCM/DCM Operation
n Programmable Phase Shift Control
n Dual N-Channel MOSFET Gate Drivers
n 28-Lead (4mm × 5mm) QFN Package
n
APPLICATIONS
Effectively working with a master controller, the LTC3874
supports all the programmable features as well as fault
protection.
L, LT, LTC, LTM, Linear Technology, the Linear logo, PolyPhase and Burst Mode are registered
trademarks of Analog Devices, Inc. All other trademarks are the property of their respective
owners. Protected by U.S. Patents, including 5481178, 5705919, 5929620, 6100678, 6144194,
6177787, 6304066, 6580258.
High Current Distributed Power Systems
Telecom, Datacom, and Storage Systems
n Intelligent Energy Efficient Power Regulation
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TYPICAL APPLICATION
High Efficiency, 4-Phase 1.8V/120A Step-Down Supply
Dual Phase Efficiency and Power Loss
vs Output Current, Sub-Milliohm DCR
vs Traditional DCR
VIN
7V TO 14V
4.7µF
INTVCC
LTC3874 TG0
PHASMD BOOST0
SW0
EXTVCC
BG0
FREQ
ILIM
ISENSE0
+
ISENSE0–
LTC3884
VSENSE0+
VSENSE1
+
RUN0
RUN1
GPIO0
GPIO1
PGOOD0
PGOOD1
ITH0
ITH1
SYNC
RUN0
RUN1
FAULT0
FAULT1
MODE0
MODE1
ITH0
ITH1
SYNC
TG1
BOOST1
0.1µF
+
931Ω
470µF
×2
VOUT
1.8V
120A
0.22µF
0.1µF
0.33µH
(0.32mΩ DCR)
+
BG1
ISENSE1+
ISENSE1
–
931Ω
95
12
470µF
×2
10
EFFICIENCY
90
8
85
6
POWER LOSS
80
0.32mΩ
1.5mΩ
0.32mΩ
1.5mΩ
75
SW1
GND
14
VIN = 12V
VOUT = 1.8V
CCM
70
0
10
20
30
40
LOAD CURRENT (A)
50
4
POWER LOSS (W)
90k
LOWDCR
100
0.33µH
(0.32mΩ DCR)
EFFICIENCY (%)
VIN
2
0
60
3874 TA01b
0.22µF
3874 TA02
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1
LTC3874
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
SW0
TG0
FAULT1
FAULT0
LOWDCR
ITH0
TOP VIEW
28 27 26 25 24 23
MODE0 1
22 BOOST0
ISENSE0+ 2
21 BG0
ISENSE0– 3
20 VIN
RUN0 4
19 INTVCC
29
GND
RUN1 5
18 EXTVCC
ISENSE1– 6
17 BG1
ISENSE1+ 7
16 BOOST1
MODE1 8
15 SW1
TG1
PHASMD
SYNC
ILIM
ITH1
9 10 11 12 13 14
FREQ
VIN.............................................................. −0.3V to 40V
BOOST0, BOOST1....................................... −0.3V to 46V
SW0, SW1..................................................... −5V to 40V
(BOOST0-SW0), (BOOST1-SW1).................. −0.3V to 6V
ISENSE0+, ISENSE0 –, ISENSE1+, ISENSE1–.... −0.3V to INTVCC
EXTVCC, INTVCC, RUN0, RUN1..................... −0.3V to 6V
MODE0, MODE1, ILIM, LOWDCR,
PHASMD, FREQ..................................... −0.3V to INTVcc
SYNC, FAULT0, FAULT1, ITH0, ITH1.......... −0.3V to INTVcc
INTVCC Peak Output Current.................................100mA
Operating Junction Temperature Range
(Note 2)................................................... −40°C to 125°C
Storage Temperature Range................... −65°C to 150°C
UFD PACKAGE
28-LEAD (4mm × 5mm) PLASTIC QFN
θJA = 43°C/W, θJC = 3.4°C/W
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3874EUFD#PBF
LTC3874EUFD#TRPBF
3874
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 125°C
LTC3874IUFD#PBF
LTC3874IUFD#TRPBF
3874
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
2
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LTC3874
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, VRUN0,1 = 3.3V unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input Voltage
VIN
Input Voltage Range
4.5
38
V
VOUT
Output Voltage Range
LOWDCR = INTVCC (Note 3)
LOWDCR = 0V
3.5
5.5
V
V
IQ
Input DC Supply Current
Normal Operation
Shutdown
(Note 4)
VRUN0,1 = 3.3V
VRUN0,1 = 0V
4.6
1.8
mA
mA
VUVLO
Undervoltage Lockout Threshold
VINTVCC Falling
VINTVCC Rising
3.5
3.8
V
V
ISENSE Pins Bias Current
VISENSE0,1 < (VINTVCC – 3.3V)
VISENSE0,1 > (VINTVCC – 3.3V)
l
l
(Table 3)
ILIM = INTVCC, LOWDCR = INTVCC,
VISENSE0,1 = 1.2V, VITH = 2.18V
l
ILIM = 0V, LOWDCR = INTVCC,
VISENSE0,1 = 1.2V, VITH = 2.18V
Control Loop
IISENSE0,1
VISENSE(MAX) Maximum Current Sense Threshold
±0.15
±1
±0.4
±3
µA
µA
26.8
28.8
30.8
mV
l
14.5
16
17.5
mV
ILIM = INTVCC, LOWDCR = 0V,
VISENSE0,1 = 1.2V, VITH = 2.18V
l
65
72
79
mV
ILIM = 0V, LOWDCR = 0V,
VISENSE0,1 = 1.2V, VITH = 2.18V
l
33
40
47
mV
Gate Drivers
TG RUP
TG Pull-Up RDS(ON)
TG High
2.6
Ω
TG RDOWN
TG Pull-Down RDS(ON)
TG Low
1.5
Ω
BG RUP
BG Pull-Up RDS(ON)
BG High
2.4
Ω
BG RDOWN
BG Pull-Down RDS(ON)
BG Low
1.1
Ω
TG0,1
tr
tf
TG Transition Time:
Rise Time
Fall Time
(Note 5)
CLOAD = 3300pF
CLOAD = 3300pF
30
30
ns
ns
BG0,1
tr
tf
BG Transition Time:
Rise Time
Fall Time
(Note 5)
CLOAD = 3300pF
CLOAD = 3300pF
30
30
ns
ns
TG/BG t1D
Top Gate Off to Bottom Gate on Delay Time
CLOAD = 3300pF Each Driver (Note 5)
30
ns
BG/TG t2D
Bottom Gate Off to Top Gate On Delay Time
CLOAD = 3300pF Each Driver (Note 5)
30
ns
tON(MIN)
Minimum On-Time
(Note 6)
60
ns
INTVCC Regulator
VINTVCC
Internal VCC Voltage No Load
6V < VIN < 38V
VLDO INT
INTVCC Load Regulation
ICC = 0mA to 20mA
VEXTVCC
EXTVCC Switchover Voltage
EXTVCC Ramping Positive (Note 7)
VLDO EXT
EXTVCC Voltage Drop
ICC = 20mA, VEXTVCC = 5V
VLDOHYS
EXTVCC Hysteresis
5.25
l
4.5
5.5
5.75
V
0.5
2
%
100
mV
4.7
50
300
V
mV
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3
LTC3874
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, VRUN0,1 = 3.3V unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
1000
kHz
Oscillator and Phase-Locked Loop
fRANGE
PLL SYNC Range
fNOM
Nominal Frequency
IFREQ
Frequency Setting Current
θ SYNC-θ0
SYNC to Ch0 Phase Relationship Based on
the Falling Edge of SYNC and Rising Edge
of TG0
PHASMD = 0
PHASMD = 1/3 • INTVCC
PHASMD = 2/3 • INTVCC
PHASMD = INTVCC
180
60
120
90
Deg
Deg
Deg
Deg
θ SYNC-θ1
SYNC to Ch1 Phase Relationship Based on
the Falling Edge of SYNC and Rising Edge
of TG1
PHASMD = 0
PHASMD = 1/3 • INTVCC
PHASMD = 2/3 • INTVCC
PHASMD = INTVCC
0
300
240
270
Deg
Deg
Deg
Deg
l
250
VFREQ = 0.9V
500
9
10
kHz
11
µA
Digital Inputs RUN0, RUN1, MODE0, MODE1, FAULT0, FAULT1, LOWDCR
VIH
Input High Threshold Voltage
l
VIL
Input Low Threshold Voltage
l
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3874 is tested under pulsed load conditions such that
TJ ≈ TA. The LTC3874E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 125°C operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls. The LTC3874I is guaranteed
over the –40°C to 125°C operating junction temperature range. High
junction temperatures degrade operating lifetimes; operating lifetime
is derated for junction temperatures greater than 125°C. Note that the
maximum ambient temperature consistent with these specifications is
determined by specific operating conditions in conjunction with board
layout, the rated package thermal impedance and other environmental
factors. TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formula:
TJ = TA + (PD • 43˚C/W)
4
2.0
1.4
V
V
Note 3: Output voltage is set and controlled by master controller in
multiphase operations.
Note 4: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Application Information.
Note 5: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 6: The minimum on-time condition corresponds to an inductor
peak-to-peak ripple current ≥ 40% of IMAX (see Minimum On-Time
Considerations in the Applications Information section).
Note 7: EXTVCC is enabled only if VIN is higher than 7V.
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LTC3874
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Output Current
and Mode
90
80
80
70
60
50
DCM
VIN = 12V
VOUT = 1.2V
CCM
40
30
70
VIN = 12V
VOUT = 1.8V
30
10
100
CCM
40
10
1
10
LOAD CURRENT (A)
95
50
20
0
0.1
1
10
LOAD CURRENT (A)
100
IL(MASTER)
20A/DIV
IL(SLAVE1)
20A/DIV
IL(SLAVE1)
20A/DIV
IL(SLAVE0)
20A/DIV
VOUT
200mV/DIV
AC-COUPLED
IL(SLAVE0)
20A/DIV
VOUT
200mV/DIV
AC-Coupled
3874 G04
6
POWER LOSS
80
0.32mΩ
1.5mΩ
0.32mΩ
1.5mΩ
70
0
VIN = 12V
VOUT = 1.2V
ILOAD 5A TO 50A
10
20
30
40
LOAD CURRENT (A)
50
4
2
0
60
3874 G03
50µs/DIV
3874 G05
Start-Up Into a Pre-Biased Output
with Master Controller LTC3875
Inductor Current at Light Load
FORCED
CONTINUOUS
MODE
5A/DIV
RUN
5V/DIV
OV
DISCONTINUOUS
CONDUCTION
MODE
5A/DIV
VOUT
1V/DIV
OV
1µs/DIV
8
85
Load Step (Discontinuous
Conduction Mode) 3-Phase with
Master Controller LTC3866
IL(MASTER)
20A/DIV
50µs/DIV
10
EFFICIENCY
90
3874 G02
Load Step (Forced Continuous
Mode) 3-Phase with Master
Controller LTC3866
VIN = 12V
VOUT = 1.2V
ILOAD = 2A
12
75
3874 G01
VIN = 12V
VOUT = 1.2V
ILOAD 5A TO 50A
14
VIN = 12V
VOUT = 1.8V
CCM
DCM
60
20
0
0.1
100
EFFICIENCY (%)
100
90
EFFICIENCY (%)
100
Dual Phase Efficiency and Power
Loss vs Output Current
POWER LOSS (W)
EFFICIENCY (%)
Efficiency vs Output Current
and Mode
(TA = 25°C unless otherwise specified)
3874 G06
VIN = 12V
VOUT = 1.0V
20ms/DIV
3874 G06a
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5
LTC3874
TYPICAL PERFORMANCE CHARACTERISTICS
INTVCC Line Regulation
4
3
2
1
100
5
80
3
2
–5
45
TEMPERATURE (°C)
95
0
125
4.1
ILIM = INTVCC
0
5
10
ILIM = GND
10
5
0
20 25
VIN (V)
30
35
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
3874 G10
20
–40
40
5.5
LOWDCR = H,
RANGE = L
LOWDCR = H,
RANGE = H
0
0.5
1
2.5
2
3
3874 G09
Quiescent Current
vs Input Voltage without EXTVCC
5.1
3.7
3.5
FALLING
3.3
3.1
2.9
2.5
–50
1.5
VITH (V)
5.3
RISING
4.9
4.7
4.5
4.3
4.1
3.9
2.7
VISENSE COMMON MODE VOLTAGE (V)
6
15
Undervoltage Lockout Threshold
(INTVCC) vs Temperature
3.9
UVLO THRESHOLD (V)
CURRENT SENSE THRESHOLD (mV)
30
15
40
3874 G08
Maximum Current Sense
Threshold vs Common Mode
Voltage (LOWDCR = INTVCC,
VITH = 2.18V)
20
LOWDCR = L,
RANGE = L
–20
3874 G07
25
LOWDCR = L, RANGE = H
0
1
0
–50
Current Sense Threshold
vs ITH Voltage
60
4
VISENSE (mV)
INTVCC VOLTAGE (V)
QUIESCENT CURRENT (mA)
5
6
SUPPLY CURRENT (mA)
6
Quiescent Current
vs Temperature without EXTVCC
(TA = 25°C unless otherwise specified)
3.7
–5
45
95
125
TEMPERATURE (°C)
3874 G12
3.5
5
10
15
20
25
VIN (V)
30
35
40
3874 G14
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LTC3874
PIN FUNCTIONS
MODE0/MODE1 (PIN 1/Pin 8): DCM/CCM Mode Control
pins. Each channel runs in forced continuous mode if the
Mode pin is logic high. There is an internal 500k pull-down
resistor on Mode pin. To select discontinuous conduction
mode, float or pull down the MODE pin.
ISENSE0+/ISENSE1+ (Pin 2/Pin 7): Current Sense Comparator Inputs. The (+) inputs to the current comparators are
normally connected to DCR sensing networks.
ISENSE0−/ISENSE1− (Pin 3/Pin 6): Current Sense Comparator Inputs. The (−) inputs to the current comparators are
connected to the outputs.
RUN0/RUN1 (Pin 4/Pin 5): Enable Run Inputs. Logic high
on RUN pin enables the corresponding channel.
ITH0/ITH1 (Pin 28/Pin 9): Current Control Threshold. Each
associated channel’s current comparator tripping threshold
increases with its ITH voltage. These pins must be connected to the master controller’s ITH pins.
FREQ (Pin 10): Frequency Set Pin. There is a precision
10µA current flowing out of this pin. A resistor to ground
sets a voltage which in turn programs the frequency. This
pin sets the default switching frequency when there is no
external clock on the SYNC pin. See the application section
for detailed information.
ILIM (Pin 11): Current Comparators Sense Voltage Limit.
Program a DC voltage at this pin to set the maximum current sense threshold for the current comparators.
SYNC (Pin 12): External Clock Synchronization Input. If an
external clock is present at this pin, the switching frequency
will be synchronized to the falling edge of external clock.
Tie this pin to GND if not used.
PHASMD (Pin 13): Phase Set Pin. This pin determines the
relative phases between the external clock on pin SYNC
and the internal controllers. See Table 1 in the Operation
section for details.
TG0/TG1 (Pin 24/Pin 14): Top Gate Driver Outputs. These
are the outputs of floating drivers with a voltage swing
equal to INTVCC superimposed on the switch node voltages.
SW0/SW1 (Pin 23/Pin 15): Switch Node Connections.
Connect these pins to the output filter inductor, bottom
N-channel MOSFET drain and top N-channel MOSFET
source. Voltage swing at the pins are from a Schottky
diode (external) voltage drop below ground to VIN.
BOOST0/BOOST1 (Pin 22/Pin 16): Boosted Floating Driver
Supplies. The (+) terminal of the bootstrap capacitors connect to these pins. These pins swing from a diode voltage
drop below INTVCC up to VIN + INTVCC.
BG0/BG1 (Pin 21/Pin 17): Bottom Gate Driver Outputs.
These pins drive the gates of the bottom N-channel MOSFETs between GND and INTVCC.
EXTVCC (Pin 18): External Power Input to an Internal Switch
Connected to INTVCC. The switch closes and supplies the
IC power, bypassing the internal low dropout regulator,
whenever EXTVCC is higher than 4.7V and VIN is greater
than 7V. Do not exceed 6V on this pin.
INTVCC (Pin 19): Internal 5.5V Regulator Output. The control circuits are powered from this voltage. Decouple this
pin to GND with a minimum of 4.7μF low ESR tantalum
or ceramic capacitor.
VIN (Pin 20): Main Input Supply. Decouple this pin to GND
with a capacitor (0.1μF to 1μF).
FAULT0, FAULT1 (Pin 26/Pin 25): Master Controller Fault
Inputs. Connect these pins to the master chip fault indicator pins to respond to the fault signals from the master
controller. When a FAULT pin is floating or low, both TG
and BG pins are pulled down in the corresponding channel. There is an internal 500k pull-down resistor on each
FAULT pin.
LOWDCR (Pin 27): Sub-milliohm DCR Current Sensing
Enable Pin. There is an internal 500k pull-up resistor between LOWDCR pin and INTVCC. Floating or pulling this
pin logic high will enable the sub-milliohm DCR current
sensing. Puling this pin logic low will disable the submilliohm DCR current sensing.
GND (Exposed Pad Pin 29): Ground. Connect this pad,
through vias, to a solid ground plane under the circuit.
The sources of the bottom N-channel MOSFETs, the (–)
terminal of CINTVCC, and the (–) terminal of CIN should
connect to this ground plane as closely as possible to
the IC. All small-signal components and compensation
components should also connect to this ground plane.
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7
LTC3874
FUNCTIONAL BLOCK DIAGRAM
10µA
SYNC
One of Two Channels (CH0) Shown
PHASMD
EXTVCC
4.7V
FREQ
PLL-SYNC
–
+
ICMP
VIN
–
+
SYNC/PHASE
DETECT
+
5.5V
REG
OSC
S
R
IREV
5K
–
+
BOOST0
REV
UVLO
ILIM RANGE SELECT
HI: 1:1
LO: 1:1.8
TG0
FAULTB
1
5k
FCNT
DC
AMP
RUN
SW0
DB
+
BG0
GND
CVCC
VOUT0
COUT0
M2
ISENSE0+
ISENSE0–
UVLO
+
–
+
–
+
–
INTVCC
+
–
1
60k
CB
M1
SWITCH
LOGIC
AND
ANTISHOOTTHROUGH
SLOPE
COMPENSATION
INTVCC
CIN
INTVCC
Q
ON
ILIM
VIN
1.7V
REF
ITH0
LOWDCR
8
MODE0
RUN0
FAULT0
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LTC3874
OPERATION
Main Control Loop
INTVCC/EXTVCC Power
The LTC3874 is a constant frequency, LTC proprietary current mode step-down slave controller for parallel operation
with master controllers. During normal operation, each
top MOSFET is turned on when the clock for that channel
sets the RS latch, and turned off when the main current
comparator, ICMP, resets the RS latch. The peak inductor
current at which ICMP resets the RS latch is controlled by
the voltage on the ITH pin, which is the output of the master
controller. When the load current increases, the master
controller increases the ITH voltage, which in turn causes
the peak current in the corresponding slave channels to
increase, until the average inductor current matches the
new load current. After the top MOSFET has turned off,
the bottom MOSFET is turned on until the beginning of
the next cycle in Continuous Conduction Mode (CCM) or
until the inductor current starts to reverse, as indicated
by the reverse current comparator IREV, in Discontinuous
Conduction Mode (DCM). The LTC3874 slave controllers
DO NOT regulate the output voltage but regulate the current in each channel for current sharing with the master
controllers. Output voltage regulation is achieved through
the voltage feedback control loop in the master controllers.
Power for the top and bottom MOSFET drivers and most
other internal circuitry is derived from the INTVCC pin.
When the EXTVCC pin is left open or tied to a voltage less
than 4.7V, an internal 5.5V linear regulator supplies INTVCC
power from VIN. If EXTVCC is taken above 4.7V and VIN
is higher than 7V, the 5.5V regulator is turned off and an
internal switch is turned on connecting EXTVCC. EXTVCC
can be applied before VIN. Using the EXTVCC allows the
INTVCC power to be drawn from an external source.
Sub-Milliohm DCR Current Sensing
The LTC3874 employs a unique architecture to enhance
the signal-to-noise ratio that enables it to operate with
a small sense signal of a sub-milliohm value inductor
DCR to improve power efficiency and reduce jitter due to
switching noise.
Floating or pulling the LOWDCR pin high will enable submilliohm DCR current sensing. The LTC3874 can sense
a DCR value as low as 0.2mΩ with careful PCB layout.
The proprietary signal processing circuit provides a 14dB
signal-to-noise ratio improvement. As with conventional
current mode architectures, the current limit threshold is
still a function of the inductor peak current and the DCR
value, and can be accurately set with the ILIM and ITH pins.
Each top MOSFET driver is biased from the floating bootstrap capacitor CB, which normally recharges during each
off cycle through an external diode when the top MOSFET
turns off. If the input voltage VIN decreases to a voltage
close to VOUT, the loop may enter dropout and attempt to
turn on the top MOSFET continuously. A dropout detector
detects this and forces the top MOSFET off for about onetwelfth of the clock period plus 100ns every three cycles
to allow CB to recharge.
Start-Up and Shutdown (RUN0, RUN1)
The two channels of the LTC3874 can be independently
shut down using the RUN0 and RUN1 pins. Pulling either
of these pins below 1.4V shuts down the main control
circuits for that channel. During shutdown, both TG
and BG are pulled down to turn off the external power
MOSFETs. Pulling either of these pins above 2V enables
the controller. The RUN0/1 pins are actively pulled down
until the INTVCC voltage passes the undervoltage lockout
threshold of 3.8V. For multiphase operation, the RUN0/1
pins must be connected together and driven by the RUN
pins on the master controller. Because a large RC filter in
the LTC3874 needs to settle during initialization, the RUN
pins can only be pulled up 4ms after VIN is ready. Do not
exceed the Absolute Maximum Rating of 6V on these pins.
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9
LTC3874
OPERATION
The start-up of each channel’s output voltage VOUT is
controlled by the master controller. After the RUN pins are
released, the master controller drives the output based on
the programmed delay time and rise time. The slave controller LTC3874 follows the ITH voltage set by the master
to supply the same current to the output during startup.
Light Load Current Operation (Discontinuous
Conduction Mode, Continuous Conduction Mode)
The LTC3874 can operate either in discontinuous conduction mode or forced continuous conduction mode. To
select forced continuous mode, tie the MODE pin to a DC
voltage above 2V (e.g., INTVCC). To select discontinuous
conduction mode, tie the MODE pin to a DC voltage below
1.4V (e.g., GND).In forced continuous mode, the inductor current is allowed to reverse at light loads or under
large transient conditions. The peak inductor current is
determined by the voltage on the ITH pin. In this mode, the
efficiency at light loads is lower than in discontinuous mode.
However, continuous mode has the advantages of lower
output ripple and less interference with audio circuitry.
When the MODE pin is connected to GND, the LTC3874
operates in discontinuous mode at light loads. At very light
loads, the current comparator ICMP may remain tripped for
several cycles and force the external top MOSFET to stay
off for the same number of cycles (i.e., skipping pulses).
This mode provides higher light load efficiency than forced
continuous mode and the inductor current is not allowed
to reverse. There is a 500k pull-down resistor internally
connected to the MODE pin. If the MODE0/1 pins are left
floating, both channels are in discontinuous conduction
mode by default.
Multichip Operations (PHASMD and SYNC Pins)
The PHASMD pin determines the relative phases between
the internal channels as well as the external clock signal on
SYNC pin as shown in Table 1. The phases tabulated are
relative to zero degree phase being defined as the falling
edge of the clock on SYNC pin.
Table 1
PHASMD
CHANNEL 0 PHASE
CHANNEL 1 PHASE
GND
180°
0°
1/3 INTVCC
60°
300°
2/3 INTVCC or Float
120°
240°
INTVCC
90°
270°
The SYNC pin is used to synchronize switching frequency
between the master and slave controllers. Input capacitance
ESR requirements and efficiency losses are substantially
reduced because the peak current drawn from the input
capacitor is effectively divided by the number of phases
used and power loss is proportional to the RMS current
squared. A two stage, single output voltage implementation can reduce input path power loss by 75% and radically reduce the required RMS current rating of the input
capacitor(s).
Single Output Multiphase Operation
The LTC3874 is configured for single output multiphase
converters with a master controller by making these
connections
• Tie all the ITH pins of paralleled channels together for
current sharing between masters and slaves;
• Tie all SYNC or PLLIN pins of paralleled channels together or tie the master chip’s CLKOUT pin to the slave
chip’s SYNC pin for switching frequency synchronization
among channels.
• Tie all the RUN pins of paralleled channels together for
startup and shutdown at the same time.
• Tie the fault indictor pin of the master controller if available to the FAULT pin of the slave controller for fault
protection.
• The LTC3874 MODE pin can be tied to the master chip
PGOOD pin for start-up control. During soft-start, the
LTC3874 operates in DCM mode. When the soft-start
interval is done, the LTC3874 operates in CCM mode.
Examples of single output multiphase converters are
shown in Figure 1.
10
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LTC3874
OPERATION
3 PHASE OPERATION
3 PHASE + 1 PHASE OPERATION
CH0
0°
CH1
240°
CH1
CH2
0°
120°
CH1
60°
300°
LTC3866
LTC3874
LTC3884
LTC3874
CLKOUT
SYNC
SYNC
SYNC
PHASMD = 1/3 INTVCC
PHASMD = 1/3 INTVCC
4 PHASE OPERATION
CH1
CH2
0°
4 PHASE OPERATION
CH0
180°
CH1
90°
CH1
270°
CH2
0°
CH0
180°
CH1
90°
270°
LTC3875
LTC3874
LTC3884
LTC3874
CLKOUT
SYNC
SYNC
SYNC
PHASMD = FLOAT
PHASMD = GND
PHASMD = INTVCC
6 PHASE OPERATION
6 PHASE OPERATION
CH1
CH2
0°
CH0
180°
240°
CH0
CH1
120°
300°
CH0
CH1
60°
180°
CH1
CH2
0°
180°
CH0
CH1
60°
300°
CH0
CH1
120°
240°
LTC3875
LTC3874
LTC3874
LTC3884
LTC3874
LTC3874
CLKOUT
SYNC
SYNC
SYNC
SYNC
SYNC
PHASMD = INTVCC
PHASMD = GND
PHASMD = 2/3 INTVCC
PHASMD = 1/3 INTVCC
PHASMD = 2/3 INTVCC
3874 F01
Figure 1. Multiphase Operation
Frequency Selection and Phase-Locked Loop
(FREQ and SYNC Pins)
The selection of switching frequency is a trade-off between
efficiency and component size. Low frequency operation
increases efficiency by reducing MOSFET switching losses,
but requires larger inductance and/or capacitance to maintain low output ripple voltage. The switching frequency of
the LTC3874 controllers can be selected using the FREQ
pin. If the SYNC pin is not being driven by an external clock
source, the FREQ pin can be used to program the controller’s operating frequency from 250kHz to 1MHz. There is a
precision 10µA current flowing out of the FREQ pin, so the
user can program the controller’s switching frequency with
a single resistor to GND. A curve is provided later in the
application section showing the relationship between the
voltage on the FREQ pin and switching frequency (Figure
5). A phase-locked loop (PLL) is integrated in the LTC3874
to synchronize the internal oscillator to an external clock
source on the SYNC pin. The PLL loop filter network is
integrated inside the LTC3874. The phase-locked loop is
capable of locking to any frequency within the range of
250kHz to 1MHz. The frequency setting resistor should
always be present to set the controller’s initial switching
frequency before locking to the external clock.
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LTC3874
APPLICATIONS INFORMATION
The Typical Application on the first page of this data
sheet is a basic LTC3874 application circuit configured
as a slave controller. In paralleled operation, the current
sensing scheme and circuit parameters in the LTC3874
have to be the same as the master controller to achieve
balanced current sharing between masters and slaves.
Input and output capacitors are selected based on RMS
current rating, ripple and transient specs.
Table 3. Current Sense Threshold vs ITH Voltage
CURRENT SENSE THRESHOLD (mV)
LOWDCR = H
LOWDCR = L
ITH (V)
RANGE = H
RANGE = L
RANGE = H
RANGE = L
2.40
32.5
18.1
81.3
45.1
2.33
31.4
17.4
78.4
43.6
2.26
30.2
16.8
75.6
42.0
2.20
29.1
16.2
72.7
40.4
2.18
28.8
16.0
72.0
40.0
2.13
28.0
15.5
69.9
38.8
To match the master controller current limit, each channel of the LTC3874 can be programmed separately with
the ILIM and LOWDCR pins. The 4-level logic input pin
ILIM setup summary is shown in Table 2. When ILIM is
grounded, both channels are set to be low current range.
When ILIM is tied to INTVCC, both channels are set to be
high current range.
2.06
26.8
14.9
67.1
37.3
1.99
25.7
14.3
64.2
35.7
1.92
24.6
13.6
61.4
34.1
1.85
23.4
13.0
58.5
32.5
1.79
22.3
12.4
55.7
30.9
1.72
21.1
11.7
52.8
29.4
1.68
20.4
11.3
51.0
28.4
Which setting should be used? For balanced load current sharing, use the same current range setting as in
the master controller. Note, the LTC3874 does not have
active clamping circuit on ITH pin for peak current limit
and over current protection. Over current protection relies
on the master controller to drive the ITH pin not to exceed
the clamped voltage. The relationship between the current
sense threshold and ITH voltage can be found in Table 3.
1.58
18.9
10.5
47.2
26.2
1.51
17.7
9.9
44.3
24.6
1.45
16.6
9.2
41.5
23.0
1.38
15.5
8.6
38.6
21.4
Current Limit Programming
Table 2. ILIM vs Range
ILIM
CHANNEL 0
CURRENT LIMIT
CHANNEL 1
CURRENT LIMIT
GND
Range Low
Range Low
1/3 INTVCC
Range High
Range Low
2/3 INTVCC or Float
Range Low
Range High
INTVcc
Range High
Range High
12
ISENSE+ and ISENSE− Pins
ISENSE+ and ISENSE– are the inputs to the current comparators. When the LOWDCR pin is high, their common
mode input voltage range is 0V to 3.5V. ISENSE– should
be connected directly to VOUT of the master controller.
ISENSE+ is connected to an R • C filter with time constant
one-fifth of L/DCR of the output inductor. Care must be
taken not to float these pins during normal operation.
Filter components, especially capacitors, must be placed
close to the LTC3874, and the sense lines should run close
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APPLICATIONS INFORMATION
together to a Kelvin connection underneath the current
sense element. The LTC3874 is designed to be used with
a sub-milliohm DCR value; without proper care, parasitic
resistance, capacitance and inductance will degrade the
current sense signal integrity, making the programmed
current limit unpredictable. In Figure 2, resistor R must be
placed close to the output inductor and capacitor C close to
the IC pins to prevent noise coupling to the sense signal.
The LTC3874 can also be used like any conventional current mode controller by disabling the LOWDCR pin, connecting it to ground. An RC filter can be used to sense the
output inductor signal and connects to the ISENSE+ pin. Its
time constant, R • C, should equal to L/DCR of the output
inductor. By pulling down the LOWDCR pin, the current
limit increases by 2.5 times. See Table 3 for details. In
these applications, the common mode operating voltage
range of ISENSE+, ISENSE– is from 0V to 5.5V.
than 1mΩ for high current inductors. In high current and
low output voltage applications, conduction loss of a high
DCR or a sense resistor will cause a significant reduction
in power efficiency. For a specific output requirement,
choose the inductor with the DCR that satisfies the maximum desirable sense voltage, and use the relationship of
the sense pin filters to output inductor characteristics as
depicted below.
DCR =
VISENSE(MAX)
ΔI
IMAX + L
2
RC = L/(5 • DCR) when the LOWDCR pin is high
RC = L/DCR when the LOWDCR pin is low
where:
Table 4. Output Voltage Range vs LOWDCR Pin
VISENSE(MAX): Maximum sense voltage for a given ITH
voltage
LOWDCR
IMAX: Maximum load current
OUTPUT VOLTAGE
Low
0V to 5.5V
High
0V to 3.5V
VIN
INTVCC
ΔIL: Inductor ripple current
L, DCR: Output inductor characteristics
R, C: Filter time constant
VIN
LTC3874
BOOST
TG
INDUCTANCE
L
SW
DCR
VOUT
Typically, C is selected in the range of 0.047µF to 0.47µF.
This forces R to around 2kΩ, reducing error that might
have been caused by the ISENSE pins’ ±1uA current.
BG
GND
ISENSE+
ISENSE–
To ensure that the load current will be delivered over the full
operating temperature range, the temperature coefficient
of the DCR resistance, approximately 0.4%/°C, should be
taken into consideration.
R
C
There will be some power loss in R that relates to the duty
cycle. It will be highest in continuous mode at maximum
input voltage:
3874 F02
Figure 2 Inductor DCR Current Sensing
PLOSS (R) =
( VIN(MAX) − VOUT ) • VOUT
R
Inductor DCR Current Sensing
The LTC3874 is specifically designed for high load current
applications requiring the highest possible efficiency; it is
capable of sensing the signal of an inductor DCR in the
sub-milliohm range (Figure 2). The DCR is the DC winding
resistance of the inductor’s copper, which is often less
Ensure that R has a power rating higher than this value.
However, DCR sensing eliminates the conduction loss
of a sense resistor; it will provide a better efficiency at
heavy loads. To maintain a good signal-to-noise ratio for
the current sense signal, using a minimum ∆VISENSE of
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LTC3874
APPLICATIONS INFORMATION
2mV for duty cycles less than 40% is desirable when the
LOWDCR pin is high; use a minimum ∆VISENSE of 10mV
for duty cycles less than 40% when the LOWDCR pin is
low. The actual ripple voltage will be determined by the
following equation:
ΔVISENSE =
VOUT ⎛ VIN − VOUT ⎞
VIN ⎜⎝ R C • fOSC ⎟⎠
Power MOSFET and Schottky Diode
(Optional) Selection
Inductor Value Calculation
Given the desired input and output voltages, the inductor
value and operating frequency, fOSC, directly determine
the inductor’s peak-to-peak ripple current:
IRIPPLE =
VOUT ⎛ VIN – VOUT ⎞
VIN ⎜⎝ fOSC • L ⎟⎠
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors, and output voltage
ripple. Thus, highest efficiency operation is obtained at
low frequency with a small ripple current. Achieving this,
however, requires a large inductor.
A reasonable starting point is to choose a ripple current
that is about 40% of IOUT(MAX). Note that the largest ripple
current occurs at the highest input voltage. To guarantee
that ripple current does not exceed a specified maximum,
the inductor should be chosen according to:
L≥
VIN – VOUT VOUT
•
fOSC •IRIPPLE VIN
Inductor Core Selection
Once the inductance value is determined, the type of inductor must be selected. Core loss is independent of core
size for a fixed inductor value, but it is very dependent on
inductance selected. As inductance increases, core losses
go down. Unfortunately, increased inductance requires
more turns of wire and therefore copper losses will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can
14
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design current
is exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
At least two external power MOSFETs need to be selected:
One N-channel MOSFET for the top (main) switch and one
or more N‑channel MOSFET(s) for the bottom (synchronous) switch. The number, type and on-resistance of all
MOSFETs selected take into account the voltage step-down
ratio as well as the actual position (main or synchronous)
in which the MOSFET will be used. A much smaller and
much lower input capacitance MOSFET should be used
for the top MOSFET in applications that have an output
voltage that is less than one-third of the input voltage. In
applications where VIN >> VOUT , the top MOSFETs’ onresistance is normally less important for overall efficiency
than its input capacitance at operating frequencies above
300kHz. MOSFET manufacturers have designed special
purpose devices that provide reasonably low on-resistance
with significantly reduced input capacitance for the main
switch application in switching regulators.
The peak-to-peak MOSFET gate drive levels are set by the
internal regulator voltage, VINTVCC, requiring the use of
logic-level threshold MOSFETs in most applications. Pay
close attention to the BVDSS specification for the MOSFETs
as well; many of the logic-level MOSFETs are limited to
30V or less. Selection criteria for the power MOSFETs
include the on-resistance, RDS(ON), input capacitance,
input voltage and maximum output current. MOSFET input
capacitance is a combination of several components but
can be taken from the typical gate charge curve included
on most data sheets (Figure 3). The curve is generated by
forcing a constant input current into the gate of a common
source, current source loaded stage and then plotting the
gate voltage versus time.
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APPLICATIONS INFORMATION
VIN
VGS
MILLER EFFECT
a
V
b
+V
DS
–
+
QIN
VGS
–
CMILLER = (QB – QA)/VDS
3874 F03
Figure 3. Gate Charge Characteristic
The initial slope is the effect of the gate-to-source and
the gate-to-drain capacitance. The flat portion of the
curve is the result of the Miller multiplication effect of the
drain-to-gate capacitance as the drain drops the voltage
across the current source load. The upper sloping line is
due to the drain-to-gate accumulation capacitance and
the gate-to-source capacitance. The Miller charge (the
increase in coulombs on the horizontal axis from a to b
while the curve is flat) is specified for a given VDS drain
voltage, but can be adjusted for different VDS voltages by
multiplying the ratio of the application VDS to the curve
specified VDS values. A way to estimate the CMILLER term
is to take the change in gate charge from points a and b
on a manufacturer’s data sheet and divide by the stated
VDS voltage specified. CMILLER is the most important selection criteria for determining the transition loss term in
the top MOSFET but is not directly specified on MOSFET
data sheets. CRSS and COS are specified sometimes but
definitions of these parameters are not included. When the
controller is operating in continuous mode the duty cycles
for the top and bottom MOSFETs are given by:
Main Switch Duty Cycle =
The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
VOUT
VIN
⎛V –V ⎞
Synchronous Switch Duty Cycle = ⎜ IN OUT ⎟
VIN
⎝
⎠
PMAIN =
( ) (1+ δ )RDS(ON) +
VOUT
IMAX
VIN
2
⎛ IMAX ⎞
(RDR )(CMILLER ) •
⎝ 2 ⎟⎠
( VIN )2 ⎜
⎡
1 ⎤
1
+
⎢
⎥•f
⎢⎣ VINTVCC – VTH(MIN) VTH(MIN) ⎥⎦
2
V –V
PSYNC = IN OUT IMAX (1+ δ )RDS(ON)
VIN
( )
where δ is the temperature dependency of RDS(ON), RDR
is the effective top driver resistance (approximately 2Ω at
VGS = VMILLER), VIN is the drain potential and the change
in drain potential in the particular application. VTH(MIN)
is the data sheet specified typical gate threshold voltage
specified in the power MOSFET data sheet at the specified
drain current. CMILLER is the calculated capacitance using
the gate charge curve from the MOSFET data sheet and
the technique described above.
Both MOSFETs have I2R losses while the topside N-channel
equation includes an additional term for transition losses,
which peak at the highest input voltage. For VIN < 20V,
the high current efficiency generally improves with larger
MOSFETs, while for VIN > 20V, the transition losses rapidly
increase to the point that the use of a higher RDS(ON) device
with lower CMILLER actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
The term (1 + δ ) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
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LTC3874
APPLICATIONS INFORMATION
An optional Schottky diode across the synchronous
MOSFET conducts during the dead time between the conduction of the two large power MOSFETs. This prevents the
body diode of the bottom MOSFET from turning on, storing
charge during the dead time and requiring a reverse-recovery period which could cost as much as several percent in
efficiency. A 2A to 8A Schottky is generally a good compromise for both regions of operation due to the relatively
small average current. Larger diodes result in additional
transition loss due to their larger junction capacitance.
INTVCC Regulators and EXTVCC
The LTC3874 features a PMOS LDO that supplies power
to INTVCC from the VIN supply. INTVCC powers the gate
drivers and most of the LTC3874’s internal circuitry. The
linear regulator regulates the voltage at the INTVCC pin
to 5.5V when VIN is greater than 6V. EXTVCC connects
to INTVCC through another P-channel MOSFET and can
supply the needed power when its voltage is higher than
4.7V and VIN is higher than 7V. Each of these can supply
a peak current of 100mA and must be bypassed to ground
with a minimum value of 4.7µF ceramic capacitor or low
ESR electrolytic capacitor. No matter what type of bulk
capacitor is used, an additional 0.1µF ceramic capacitor
placed directly adjacent to the INTVCC and GND pins is
highly recommended. Good bypassing is needed to supply
the high transient currents required by the MOSFET gate
drivers and to prevent interaction between the channels.
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maximum junction temperature rating for the LTC3874 to be
exceeded. The INTVCC current, which is dominated by the
gate charge current, may be supplied by either the 5.5V
linear regulator from VIN or EXTVCC. When the voltage on
the EXTVCC pin is less than 4.4V, the linear regulator is
enabled. Power dissipation for the IC in this case is highest and is equal to VIN • IINTVCC. The gate charge current
is dependent on operating frequency. The junction temperature can be estimated by using the equations given
in Note 2 of the Electrical Characteristics. For example,
16
the LTC3874 INTVCC current is limited to less than 34mA
from a 38V supply in the UFD package and not using the
EXTVCC supply:
TJ = 70°C + (34mA)(38V)(43°C/W) = 125°C
To prevent the maximum junction temperature from being
exceeded, the input supply current must be checked while
operating in continuous conduction mode (MODE = INTVCC)
at maximum VIN. When the voltage applied to EXTVCC rises
above 4.7V and VIN above 7V, the INTVCC linear regulator is turned off and the EXTVCC is connected to INTVCC.
Using the EXTVCC allows the MOSFET driver and control
power to be derived from other high efficiency sources
such as +5V rails in the system. Do not apply more than
6V to the EXTVCC pin.
Significant efficiency and thermal gains can be realized
by powering INTVCC from EXTVCC. Tying the EXTVCC pin
to a 5V supply reduces the junction temperature in the
previous example from 125°C to:
TJ = 70°C + (34mA)(5V)(43°C/W) = 77°C
However, for low voltage outputs, additional circuitry is
required to derive INTVCC power from the output.
The following list summarizes the three possible connections for EXTVCC:
1. EXTVCC left open (or grounded). This will cause
INTVCC to be powered from the internal LDO resulting
in an efficiency penalty of up to 10% at high input
voltages.
2. EXTVCC connected to an external supply. If a 5V external
supply is available, it may be used to power EXTVCC
providing it is compatible with the MOSFET gate drive
requirements.
3. EXTVCC connected to an output-derived boost network.
For 3.3V and other low voltage regulators, efficiency
gains can still be realized by connecting EXTVCC to an
output-derived voltage that has been boosted to greater
than 4.7V.
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For applications where the main input power is 5V, tie
the VIN and INTVCC pins together and tie the combined
pins to the 5V input with a 1Ω or 2.2Ω resistor as shown
in Figure 4 to minimize the voltage drop caused by the
gate charge current. This will override the INTVCC linear
regulator and will prevent INTVCC from dropping too low
due to the dropout voltage. Make sure the INTVCC voltage
is at or exceeds the RDS(ON) test voltage for the MOSFET,
which is typically 4.5V for logic-level devices.
Undervoltage Lockout
The LTC3874 has a precision UVLO comparator constantly
monitoring the INTVCC voltage to ensure that an adequate
gate-drive voltage is present. It locks out the switching
action and pulls down RUN pins when INTVCC is below
3.5V. In multiphase operation, when the LTC3874 is in
undervoltage lockout, the RUN pin is pulled down to disable the master’s switching action. To prevent oscillation
when there is a disturbance on the INTVCC, the UVLO
comparator has 300mV of precision hysteresis.
LTC3874
VIN
INTVCC
Phase-Locked Loop and Frequency Synchronization
RVIN
1Ω
CINTVCC
4.7µF
+
5V
CIN
3874 F04
Figure 4. Setup for a 5V Input
Topside MOSFET Driver Supply (CB, DB)
External bootstrap capacitor, CB, connected to the BOOST
pin, supplies the gate drive voltages for the topside
MOSFET. Capacitor CB in the Functional Diagram is charged
though external diode DB from INTVCC when the SW pin
is low. When the topside MOSFET is to be turned on, the
driver places the CB voltage across the gate source of the
MOSFET. This enhances the MOSFET and turns on the
topside switch. The switch node voltage, SW, rises to VIN
and the BOOST pin follows. With the topside MOSFET on,
the boost voltage is above the input supply:
VBOOST = VIN + VINTVCC – VDB
The value of the boost capacitor, CB, needs to be 100 times
that of the total input capacitance of the topside MOSFET(s).
The reverse breakdown of the external Schottky diode
must be greater than VIN(MAX). When adjusting the gate
drive level, the final arbiter is the total input current for
the regulator. If a change is made and the input current
decreases, then the efficiency has improved. If there is
no change in input current, then there is no change in
efficiency.
The LTC3874 has a phase-locked loop (PLL) comprised
of an internal voltage-controlled oscillator (VCO) and a
phase detector. This allows the internal clock to be locked
to the falling edge of an external clock signal applied to the
SYNC pin. The turn-on of the top MOSFET is synchronized
or out-of-phase with the falling edge of external clock.
The phase detector is an edge sensitive digital type that
provides zero degrees phase shift between the external
and internal oscillators. This type of phase detector does
not exhibit false lock to harmonics of the external clock.
The output of the phase detector is a pair of complementary current sources that charge or discharge the internal
filter network. There is a precision 10µA of current flowing
out of the FREQ pin. This allows the user to use a single
resistor to GND to set the switching frequency when no
external clock is applied to the SYNC pin. The internal
switch between the FREQ pin and the integrated PLL
filter network is ON, allowing the filter network to be precharged to the same voltage potential as the FREQ pin.
The relationship between the voltage on the FREQ pin and
the operating frequency is shown in Figure 5 and specified
in the Electrical Characteristic table. If an external clock is
detected on the SYNC pin, the internal switch mentioned
above will turn off and isolate the influence of the FREQ
pin. Note that the LTC3874 can only be synchronized to
an external clock whose frequency is within the range
of the LTC3874’s internal VCO. This is guaranteed to be
between 250kHz and 1MHz. A simplified block diagram
is shown in Figure 6.
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LTC3874
APPLICATIONS INFORMATION
1600
Fault Protection and Response
1400
Master controllers monitor system voltage, current, temperature and provide many protection features during all
kinds of fault conditions. The LTC3874 slave controllers
do not provide as many fault protections as master controllers but respond to the fault signal from the master
controller. FAULT0 and FAULT1 pins are designed to share
the fault signal between masters and slaves. In a typical
parallel application, connect the fault pins on LTC3874 to
the master fault indictor pins, so that the slave controller
can respond to all fault signals from the master. When
the FAULT pin is pulled below 1.4V, both TG and BG in
the corresponding channel are pulled down and external
MOSFETs are turned off. When the FAULT pin voltage is
above 2V, the corresponding channel is back to normal
operation. During fault conditions, all internal circuits in
the LTC3874 are still running so the slave controllers can
immediately return to normal operation when the FAULT
pin is released.
FREQUENCY (kHz)
1200
1000
800
600
400
200
0
0
0.5
1
1.5
2
FREQ PIN VOLTAGE (V)
2.5
3874 F05
Figure 5. Relationship Between Oscillator Frequency
and Voltage at the FREQ Pin
2.4V 5.5V
RSET
10µA
FREQ
EXTERNAL
OSCILLATOR
SYNC
DIGITAL
SYNC
PHASE/
FREQUENCY
DETECTOR
VCO
3874 F06
Figure 6. Phase-Locked Loop Block Diagram
If the external clock frequency is greater than the internal oscillator’s frequency, fOSC, then current is sourced
continuously from the phase detector output, pulling up
the filter network. When the external clock frequency is
less than fOSC, current is sunk continuously, pulling down
the filter network. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. The voltage on the filter network is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the filter capacitor holds the voltage.
Typically, the external clock (on the SYNC pin) input high
threshold is 2V, while the input low threshold is 1.4V.
18
The LTC3874 has internal thermal shutdown protection
which pulls all TG and BG pins low when the junction
temperature is higher than 160°C. The thermal shutdown
has 10°C of hysteresis. In thermal shutdown, the FAULT0
and FAULT1 pins are also pulled low. The RUN pins are not
internally pulled low. There is a 500k pull-down resistor
on each FAULT pin which sets the default voltage on the
FAULT pins low if the FAULT pins are floating.
Transient Response and Loop Stability
In a typical parallel operation, the LTC3874 cooperates
with master controllers to supply more current. To achieve
balanced current sharing between master and slave, it is
recommended that each slave channel copies the power
stage design from the master channel. Select the same
inductors, same power MOSFETs, and same output capacitors between the master and slave channels. Control loop
and compensation design on the ITH pin should start with
the single phase operation of the master controller. The
multiphase transient response and loop stability is almost
the same as the single phase operation of the master by
tying the ITH pins together between master and slaves.
For example, design the compensation for a single phase
1.8V/20A output using LTC3866 with a 0.33μH inductor
3874fb
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LTC3874
APPLICATIONS INFORMATION
To minimize the high frequency noise on the ITH trace
between master and slave ITH pins, a small filter capacitor
in the range of tens of pF can be placed closely at each ITH
pin of the slave controller. This small capacitor normally
does not significantly affect the closed-loop bandwidth
but increases the gain margin at high frequency.
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated, but
the ripple voltage and current will increase. The minimum
on-time for the LTC3874 is approximately 90ns, with reasonably good PCB layout, minimum 30% inductor current
ripple and at least 2mV – 3mV (10mV – 15mV when the
LOWDCR pin is low) ripple on the current sense signal.
The minimum on-time can be affected by PCB switching noise in the current loop. As the peak sense voltage
decreases the minimum on-time gradually increases to
130ns. This is of particular concern in forced continuous
applications with low ripple current at light loads. If the
duty cycle drops below the minimum on-time limit in this
situation, a significant amount of cycle skipping can occur
with correspondingly larger current and voltage ripple.
Mode Selection and Pre-Biased Startup
PC Board Layout Checklist
and 530μF output capacitors. To extend the output to
1.8V/40A, simply parallel one channel of LTC3874 with
the same inductor and output capacitors (total output
capacitors are 1060μF) and tie the ITH pin of LTC3874 to
the master ITH. The loop stability and transient responses
of the two phase converter are very similar to the single
phase design without any extra compensator on the ITH
pin of the slave controller. Furthermore, LTpowerCAD is
provided on the LTC website as a free download for transient and stability analysis.
There may be situations that require the power supply to
start up with a pre-bias on the output capacitors. In this
case, it is desirable to start up without discharging the
output capacitors. The LTC3874 can be configured to
operate in DCM mode for pre-biased start-up. The master
chip’s PGOOD pin can be connected to the MODE pins of
the LTC3874 to ensure the DCM operation at startup and
CCM operation in steady state.
Minimum On-Time Considerations
Minimum on-time tON(MIN) is the smallest time duration
that the LTC3874 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
tON(MIN) <
VOUT
VIN • f
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 7. Figure 8 illustrates the current
waveforms present in the various branches of the 2-phase
synchronous regulators operating in the continuous mode.
Check the following in the PC layout:
1. Are the top N-channel MOSFETs M1 and M3 located
within 1cm of each other with a common drain connection at CIN? Do not attempt to split the input decoupling
for the two channels as it can cause a large resonant
loop.
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return of
CINTVCC must return to the combined COUT (–) terminals.
The ITH traces should be as short as possible. The path
formed by the top N-channel MOSFET, Schottky diode
and the CIN capacitor should have short leads and PC
trace lengths. The output capacitor (–) terminals should
be connected as close as possible to the (–) terminals
of the input capacitor by placing the capacitors next to
each other and away from the Schottky loop described
above.
3874fb
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19
LTC3874
APPLICATIONS INFORMATION
ITH1
LTC3874
ISENSE1–
L1
VOUT1
TG1
SW1
CB1
M1
BOOST1
SYNC
COUT1
CVIN
RIN
GND
VIN
BG0
+
ISENSE0+
SW0
COUT0
1µF
CERAMIC
M3
BOOST0
+
INTVCC
GND
CIN
CINTVCC
ISENSE0–
ITH0
+
VIN
RUN0
RUN1
D1
1µF
CERAMIC
BG1
fIN
M2
+
ISENSE1+
M4
D0
CB0
TG0
VOUT0
L0
3874 F07
Figure 7. Recommended Printed Circuit Layout Diagram
3. Are the ISENSE+ and ISENSE– leads routed together with
minimum PC trace spacing? The filter capacitor between
ISENSE+ and ISENSE– should be as close as possible to
the IC. Ensure accurate current sensing with Kelvin
connections at the sense resistor or inductor, whichever
is used for current sensing.
4. Is the INTVCC decoupling capacitor connected close
to the IC, between the INTVCC and the power ground
pins? This capacitor carries the MOSFET drivers current peaks. An additional 1μF ceramic capacitor placed
immediately next to the INTVCC and GND pins can help
improve noise performance substantially.
20
5. Keep the switching nodes (SW1, SW0), top gate nodes
(TG1, TG0), and boost nodes (BOOST1, BOOST0) away
from sensitive small-signal nodes, especially from the
opposite channel’s current sensing feedback pins. All
of these nodes have very large and fast moving signals
and therefore should be kept on the output side of the
LTC3874 and occupy minimum PC trace area. If DCR
sensing is used, place the resistor (Figure 2, “R”) close
to the switching node.
6. Use a modified star ground technique: a low impedance,
large copper area central grounding point on the same
side of the PC board as the input and output capacitors
with tie-ins for the bottom of the INTVCC decoupling
capacitor, the bottom of the voltage feedback resistive
divider and the GND pin of the IC.
3874fb
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LTC3874
APPLICATIONS INFORMATION
SW1
L1
D1
VOUT1
COUT1
RL1
VIN
RIN
CIN
SW0
BOLD LINES INDICATE
HIGH SWITCHING
CURRENT. KEEP LINES
TO A MINIMUM LENGTH.
D0
L0
VOUT0
COUT0
RL0
3874 F08
Figure 8. Branch Current Waveforms
3874fb
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21
LTC3874
APPLICATIONS INFORMATION
PC Board Layout Debugging
Start with one controller at a time. It is helpful to use a
DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope
to the internal oscillator and probe the actual output voltage
as well. Check for proper performance over the operating
voltage and current range expected in the application. The
frequency of operation should be maintained over the input
voltage range down to dropout and until the output load
drops below the low current operation threshold.
The duty cycle percentage should be maintained from cycle
to cycle in a well-designed, low noise PCB implementation.
Variation in the duty cycle at a subharmonic rate can suggest noise pickup at the current or voltage sensing inputs
or inadequate loop compensation. Overcompensation of
the loop can be used to tame a poor PC layout if regulator
bandwidth optimization is not required. Only after each
controller is checked for its individual performance should
both controllers be turned on at the same time. A particularly
difficult region of operation is when one controller channel
is nearing its current comparator trip point when the other
channel is turning on its top MOSFET. This occurs around
50% duty cycle on either channel due to the phasing of
the internal clocks and may cause minor duty cycle jitter.
Reduce VIN from its nominal level to verify operation of
the regulator in dropout. Check the operation of the undervoltage lockout circuit by further lowering VIN while
monitoring the outputs to verify operation.
Investigate whether any problems exist only at higher output currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
for inductive coupling between CIN, Schottky and the top
22
MOSFET components to the sensitive current and voltage
sensing traces. In addition, investigate common ground
path voltage pickup between these components and the
GND pin of the IC.
Design Example
As a design example using master controller LTC3866 and
slave controller LTC3874 for a 3-phase high current regulator, assume VIN = 12V (nominal), VIN = 20V (maximum),
VOUT = 1.5V, IMAX = 90A, and f = 400kHz (see Figure 9).
The master controller LTC3866 design can be found in the
LTC3866 data sheet Design Example section.
The regulated output voltage is determined by the LTC3866:
⎛ R ⎞
VOUT = 0.6V • ⎜ 1+ B ⎟
⎝ RA ⎠
Using a 20k 1% resistor from the VFB node to ground,
the top feedback resistor is (to the nearest 1% standard
value) 30.1k.
The frequency is set by biasing the LTC3866 FREQ pin to
1V. The LTC3866 CLKOUT pin is connected to the LTC3874
SYNC pin through an inverter. The LTC3874 PHASMD pin
is connected to 1/3 • INTVCC.
The inductance value is based on a 35% maximum ripple
current assumption per phase (10.5A). The highest value
of ripple current occurs at the maximum input voltage:
⎞
VOUT ⎛
V
L=
1– OUT ⎟
⎜
f • ΔIL(MAX) ⎝ VIN(MAX) ⎠
This design will require 0.33μH. The Würth
744301033,0.33μH inductor is chosen for both the
LTC3866 and the LTC3874. At the nominal input voltage
(12V), the ripple current will be:
ΔIL(NOM) =
VOUT ⎛
VOUT ⎞
1–
⎜
⎟
f •L ⎝ VIN(NOM) ⎠
It will have 10A (33%) ripple. The peak inductor current
will be the maximum DC value plus one-half the ripple
current, or 35A.
3874fb
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LTC3874
APPLICATIONS INFORMATION
100k
FREQ
MODE/PLLIN
PGOOD
RUN
0.1µF
10k
20k RA
RB
ITH
VFB
EXTVCC
VIN
DIFFOUT
INTVCC
10µF
×2
2.2Ω
CMDSH-3
ITEMP
TK/SS
30.1k
VIN
4.5V TO 14V
120k
LTC3866
DIFFP
BOOST
0.1µF
1.5nF
C1
220nF
C2
220nF
DIFFN
TG
SNSD+
SW
SNS–
BG
SNSA+
ILIM
BSC050NE2LS
BSC010NE2LS
PGND
CLKOUT
SGND
L1
0.33µH
DCR = 0.32mΩ
931Ω
R2
4.64k
R1
VOUT
1.5V
90A
100µF
×6
+
330µF
×6
1µF
4.7µF
GND
30.1k
10k
220pF
1k
2.2Ω
10µF
×2
2N3904
CMDSH-3
4.7µF
VIN
BSC050NE2LS
0.33µH
DCR = 0.32mΩ
TG0
SW0
L2
BSC010NE2LS
R3
931Ω
C3
220nF
4.7nF
10pF
120k
LTC3874
+
ISENSE0
ISENSE0–
RUN1
BG1
0.33µH
DCR = 0.32mΩ
L3
BSC010NE2LS
R4
931Ω
ISENSE1
C4
220nF
–
ISENSE1
EXTVCC
LOWDCR
FAULT1
MODE0
ILIM
PHASMD
ITH1
0.1µF
+
FAULT0
MODE1
ITH0
1µF
BSC050NE2LS
SW1
BG0
RUN0
2N7002
INTVCC
TG1
BOOST1
BOOST0
0.1µF
10µF
×2
CMDSH-3
FREG
20k
75k
GND
10k
GND
SYNC
L1, L2, L3 = WÜRTH 744301033
3874 F09
Figure 9. High Efficiency, Triple Phase Sub-Milliohm DCR Sensing 1.5V/90A Step-Down Supply
3874fb
For more information www.linear.com/LTC3874
23
LTC3874
APPLICATIONS INFORMATION
The minimum on-time occurs at the maximum VIN, and
should not be less than 90ns:
t
ON(MIN) =
VOUT
VIN(MAX) • f
=
1.5V
= 187ns
20V(400kHz)
DCR current sensing is used in this circuit. For the LTC3866,
if C1 and C2 are chosen to be 220nF, based on the chosen
0.33μH inductor with 0.32mΩ DCR, R1 and R2 can be
calculated as:
L
= 4.69k
DCR •C1
L
= 937Ω
R2 =
DCR •C2 • 5
R1=
For the LTC3874, if C3 and C4 are chosen to be 220nF,
based on the chosen 0.33μH inductor with 0.32mΩ DCR,
R3 and R4 can be calculated as:
L
= 937Ω
DCR •C3 • 5
L
= 937Ω
R4 =
DCR •C4 • 5
R3 =
The LTC3866 and LTC3874 choose the same power
MOSFET, CIN, and COUT.
The power dissipation on the topside MOSFET can be
easily estimated. Choosing an Infineon BSC050NE2LS
MOSFET results in: RDS(ON) = 7.1mΩ (max), VMILLER =
2.8V, CMILLER ≅ 35pF. At maximum input voltage with TJ
(estimated) = 75˚C:
The maximum DCR of the inductor is 0.34mΩ. The
VSENSE(MAX) is calculated as:
1 ⎤
1
⎡
⎢⎣ 5.5V – 2.8V + 2.8V ⎥⎦ (400kHz)
= 599mW +122mW
= 721mW
VSENSE(MAX) =IPEAK •DCRMAX = 12mV
The current limit is chosen to be 15mV for the LTC3866.
When the current limit is 15mV for the LTC3866, the ITH
pin voltage is 2V. Based on Table 3, the LTC3874 LOWDCR
pin is pulled high and the ILIM pin is pulled low to choose
both channels' current limit to be 14.4mV when the ITH
pin voltage is 2V.
24
1.5V
(30A)2[1+(0.005)(75°C – 25°C)]
20V
⎛ 30A ⎞
•(0.0071Ω)+(20V)2 ⎜
(2Ω)(35pF)•
⎝ 2 ⎟⎠
PMAIN =
Choose R3 = 931 Ω and R4 = 931Ω.
The LTC3866 PGOOD pin is connected to the LTC3874
FAULT pins through a NMOS switch. The switch is controlled by the LTC3866 TK/SS pin. During the soft-start,
the switch is off. The LTC3874 FAULT pins are pulled up
by a 120k resistor. When the soft-start interval is done,
the NMOS switch is turned on. The LTC3874 FAULT pins
are controlled by the LTC3866 PGOOD pin.
The LTC3874 Mode pins are tied to the LTC3866 PGOOD
pin for start-up control.
Choose R1 = 4.64k and R2 = 931Ω.
Both ICs’ RUN pins are connected together. During startup, the LTC3866 has 1µA current to pull up the RUN pins.
A 4.7nF capacitor is connected to the RUN pins to ensure
the LTC3874 RUN pins have 4mS delay after VIN is ready.
An Infineon BSC010NE2LS, RDS(ON) = 1.1mΩ, is chosen
for the bottom FET. The resulting power loss is:
PSYNC =
20V – 1.5V
(30A)2[1+(0.005)(75°C – 25°C)]
20V
•(0.001 1Ω) = 1.14W
3874fb
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LTC3874
APPLICATIONS INFORMATION
Design Example 2
Using master controller LTC3884 and slave controller
LTC3874 for a dual-output, 3 + 1 phase high current
regulator, assume VIN = 12V (nominal), and VIN = 15V
(maximum). LTC3884 channel 0 provides VOUT0 of 1.5V
and 30A output current, and channel 1 together with
channel 0 and channel 1 in the LTC3874 provides VOUT1
of 1.0V, with 90A output current (see Figure 11).
The master chip LTC3884 design can be found in the
LTC3884 data sheet (Design Example section).
The LTC3884 SYNC pin is connected to the LTC3874
SYNC pin for switching frequency synchronization. The
LTC3874 PHASMD pin is forced to 1/3 INTVCC to form a
PolyPhase configuration.
The slave chip LTC3874 should use the same inductor,
power MOSFET, CIN, and COUT as the master chip. DCR
sensing is also used for the slave chip.
The LTC3884 ITH1, the LTC3874 ITH0 and the LTC3874 ITH1
pins are connected together. The LTC3874 LOWDCR pin
is pulled high and the ILIM pin is forced to 0V to obtain
the same current limit as LTC3884 CH1.
The LTC3884 RUN1, the LTC3874 RUN0 and the LTC3874
RUN1 pins are connected together. The LTC3884 FAULT pins
are connected to LTC3874’s FAULT pins so the LTC3874
will be disabled if the LTC3884 is under any fault event.
The LTC3874 MODE pins are tied to the LTC3884 PGOOD1
pin for start-up control. During soft-start, the LTC3874
operates in DCM mode. When the soft-start interval is
done, the LTC3874 operates in CCM mode.
3874fb
For more information www.linear.com/LTC3874
25
LTC3874
APPLICATIONS INFORMATION
2.2Ω
10µF
×2
4.7µF
CMDSH-3
VIN
TG2
BSC050NE2LS
0.25µH
DCR = 0.32mΩ
INTVCC
BOOST2
0.1µF
L2
SNSD2+
220nF
220nF
ENTEMPB
SNS1–
SNSA2+
SNSA1+
RUN1
VOSNS1+
RUN2
VOSNS2+
ITH1
VOSNS1–
ITH2
VOSNS2–
10nF
2.2nF
0.1µF
TK/SS1
EXTVCC
TK/SS2
PGOOD
FREQ
4.02k
220pF
100k
TAVG
+
330µF
×12
13.3k
220nF 715Ω
100k
30.1k
ILIM
TRSET2
VOUT
1.0V
120A
100µF
×12
220nF
IFAST
CLKOUT
1µF
3.57k
SNSD1+
SNS2–
L1
BSC010NE2LSI
BG1
LTC3875
TCOMP1
TCOMP2
PHASMD
0.25µH
DCR = 0.32mΩ
0.1µF
SW1
BG2
3.57k
715Ω
BSC050NE2LS
TG1
BOOST1
SW2
BSC010NE2LSI
10µF
×2
CMDSH-3
VIN
4.5V TO 14V
20k
TRSET1
10k
MODE/PLLIN
SGND/PGND
GND
2.2Ω
10µF
×2
CMDSH-3
4.7µF
VIN
BSC050NE2LS
0.25µH
DCR = 0.32mΩ
TG0
BOOST0
0.1µF
L3
SW1
BG1
ISENSE0–
RUN0
RUN1
2N7002
BSC010NE2LSI
ISENSE1
715Ω
220nF
ISENSE1–
EXTVCC
LOWDCR
FAULT1
MODE0
ILIM
MODE1
ITH0
PHASMD
SYNC
120k
0.25µH
DCR = 0.32mΩ
L4
+
FAULT0
ITH1
100pF
0.1µF
LTC3874
+
1µF
BSC050NE2LS
BOOST1
BG0
ISENSE0
220nF
INTVCC
TG1
SW0
BSC010NE2LSI
715Ω
10µF
×2
CMDSH-3
FREQ
GND
L1, L2, L3, L4: WÜRTH 744301025
75k
GND
3874 F10
Figure 10. High Efficiency, 4-Phase 1V/120A Step-Down Supply
26
3874fb
For more information www.linear.com/LTC3874
100µF
6.3V
x2
VOUT0
1.5V / 30A
For more information www.linear.com/LTC3874
SYNC
INTVCC
BG1
1500pF
VDD33
ISENSE1–
VSENSE1+
VSENSE1–
TSNS1
ITH1
ISENSE1+
EXTVCC
PHASE_CFG
2.2µF
VDD25
1µF
ITHR1
VDD33 PGND SGND VDD25
ISENSE0–
VSENSE0+
VSENSE0–
TSNS0
ITH0
ITHR0
ISENSE0+
RUN0
RUN1
WP
SHARE_CLK
ASEL0
ASEL1
FREQ_CFG
D1
1500pF
ITH1
17.8k
20k
VDD25
0.1µF
47pF
220nF
4.32k
24.9k
10nF
Q4
BSC010NE2LSI
Q2
BSC050NE2LS
2mΩ
270µF
16V
x2
1Ω
1%
715Ω
1%
330µF
6.3V
x2
744301025
DCR=0.32 mΩ
L2
0.25µH
C3
1µF
100µF
6.3V
x2
330µF
6.3V
x2
100µF
6.3V
x2
VOUT1 1.0V / 90A
VIN
7V to 14V
744301025
DCR=0.32 mΩ
L3
0.25µH
715Ω
1%
Q7
BSC010NE2LSI
Q6
BSC050NE2LS
10µF
x2
D3
220nF
SYNC
FAULT
RUN1
0.1µF
4.7µF
VIN
SYNC
RUN0
RUN1
FAULT0
FAULT1
ITH0
ITH1
ISENSE0–
TG1
MODE0
MODE1
GND
FREQ
ILIM
PHASMD
EXTVCC
ISENSE1–
ISENSE1+
BG1
SW1
BOOST1
INTVCC
LTC3874
ISENSE0+
BG0
SW0
BOOST0
TG0
INTVCC1
10µF
x2
100K
Q9
BSC010NE2LSI
Q8
BSC050NE2LS
D1, D2, D3, D4: CMDSH3-TR
PGOOD1
220nF
0.1µF
D4
L4
0.25µH
INTVCC1
715Ω
1%
744301025
10K
20K
Figure 11. Master/Slave 3 +1 High Efficiency, Dual-Output, 1.5V/30A and 1.0V/90A Buck Converter (LTC3884/LTC3874)
150pF
RUN1
10k
220nF
RUN0
10k
FAULT1
VOUT1_CFG
VOUT0_CFG
SW1
BOOST1
TG1
IIN–
BG0
SDA SDA
SCL
SCL
ALERT
ALERT
FAULT
FAULT0
10k
IIN+
LTC3884
VIN
SW0
BOOST0
TG0
D2
SYNC
10k PGOOD0
PGOOD0
PGOOD1 PGOOD1
4.99k
0.1µF
4.7µF
SHARE_CLK
10k
10k
10k
10k
10k
10nF
931Ω
1%
VDD33
Q3
BSC010NE2LSI
Q1
BSC050NE2LS
MMBT3906-AL3-R
330µF
6.3V
x2
744301033
DCR=0.32 mΩ
L1
0.33µH
10µF
x2
10µF
x2
2mΩ
100µF
6.3V
x2
3874 F11
330µF
6.3V
x2
LTC3874
APPLICATIONS INFORMATION
3874fb
27
LTC3874
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC3874#packaging for the most recent package drawings.
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev C)
0.70 ±0.05
4.50 ±0.05
3.10 ±0.05
2.50 REF
2.65 ±0.05
3.65 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
3.50 REF
4.10 ±0.05
5.50 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 ±0.10
(2 SIDES)
0.75 ±0.05
R = 0.05
TYP
PIN 1 NOTCH
R = 0.20 OR 0.35
× 45° CHAMFER
2.50 REF
R = 0.115
TYP
27
28
0.40 ±0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
5.00 ±0.10
(2 SIDES)
3.50 REF
3.65 ±0.10
2.65 ±0.10
(UFD28) QFN 0816 REV C
0.200 REF
0.00 – 0.05
0.25 ±0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGHD-3).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
28
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For more information www.linear.com/LTC3874
LTC3874
REVISION HISTORY
REV
DATE
DESCRIPTION
A
12/15
Added Tape and Reel information link
B
01/16
C
05/17
PAGE NUMBER
2
Updated Applications schematic
1
Added additional drawing to Figure 1
11
Added application schematic
27
Reduced Minimum On-Time
3
Changed VISENSE(MAX) description from Table 1 to Table 3
3
3874fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representaFor more
information
www.linear.com/LTC3874
tion that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
29
LTC3874
TYPICAL APPLICATION
High Efficiency Dual 1.0V/1.5V Step-Down Converter
VIN
4.7µF
M1
L1
0.33µH
(0.32mΩ DCR)
VOUT0
1.0V
60A
470µF
×2
+
931Ω
VIN
INTVCC
TG0
0.1µF
M3
BOOST0
SW1
BG0
BG1
+
ISENSE0
ISENSE0–
VSENSE0+
VOUT1
VSENSE1+
BOOST1
SW0
0.1µF
M4
LTC3874
0.22µF
LTC3884
M2
TG1
RUN0
RUN1
GPIO0
GPIO1
PGOOD0
PGOOD1
ITH0
ITH1
SYNC
RUN0
RUN1
FAULT0
FAULT1
MODE0
MODE1
ITH0
ITH1
SYNC
L2
0.33µH
(0.32mΩ DCR)
931Ω
0.22µF
+
ISENSE1
+
VOUT1
1.5V
60A
470µF
×2
ISENSE1–
L1, L2: WÜRTH 744301033
M1, M2: BSC050NE2LS
M3, M4: BSC010NE2LS
EXTVCC
LOWDCR
ILIM
PHASMD
FREQ
GND
90k
3874 TA02
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LTM4676A
Dual 13A or Single 26A Step-Down DC/DC
µModule Regulator with Digital Power System
Management
4.5V ≤ VIN ≤17V; 0.5V ≤ VOUT (±0.5%) ≤ 5.5V, I2C/PMBus Interface, 16mm × 16mm
× 5mm, BGA Package
LTM4675
Dual 9A or Single 18A μModule Regulator with
Digital Power System Management
4.5V ≤ VIN ≤17V; 0.5V ≤ VOUT (±0.5%) ≤ 5.5V, I2C/PMBus Interface, 11.9mm ×
16mm × 5mm, BGA Package
LTM4677
Dual 18A or Single 36A μModule Regulator with
Digital Power System Management
4.5V ≤ VIN ≤16V; 0.5V ≤ VOUT (±0.5%) ≤ 1.8V, I2C/PMBus Interface, 16mm × 16mm
× 5.01mm, BGA Package
LTC3884
Dual Output Multiphase Step-Down Controller with 4.5V ≤ VIN ≤ 38V, 0.5V ≤ VOUT (±0.5%) ≤ 5.5V, 70ms Start-Up, I2C/PMBus Interface,
Sub mΩ DCR Sensing Current Mode Control and Programmable Analog Loop Compensation, Input Current Sense
Digital Power System Management
LTC3887/
LTC3887-1
Dual Output Multiphase Step-Down DC/DC
4.5V ≤ VIN ≤ 24V, 0.5V ≤ VOUT0,1 (±0.5%) ≤ 5.5V, 70ms Start-Up, I2C/PMBus
Controller with Digital Power System Management, Interface, -1 Version Uses DrMOS or Power Blocks
70ms Start-Up
LTC3882/
LTC3882-1
Dual Output Multiphase Step-Down DC/DC Voltage 3V ≤ VIN ≤ 38V, 0.5V ≤ VOUT1,2 ≤ 5.25V, ±0.5% VOUT Accuracy I2C/PMBus Interface,
Mode Controller with Digital Power System
Uses DrMOS or Power Blocks
Management
LTC3866
Single Output Current Mode Synchronous StepDown Controller with Sub-Milliohm DCR Sensing
4.5V ≤ VIN ≤ 38V, 0.6V ≤ VOUT ≤ 3.5V, with Remote VOUT Sense, 4mm × 4mm,
QFN-24, TSSOP-24 Packages
LTC3883/
LTC3883-1
Single Phase Step-Down DC/DC Controller with
Digital Power System Management
VIN Up to 24V, 0.5V ≤ VOUT ≤ 5.5V, Input Current Sense Amplifier, I2C/PMBus
Interface with EEPROM and 16-Bit ADC, ±0.5% VOUT Accuracy
LT3875
Dual, Multiphase Current Mode Synchronous
Step-Down Controller with Sub-Milliohm DCR
Sensing, Up to 12 Phases
4.5V ≤ VIN ≤ 38V, 0.6V ≤ VOUT ≤ 3.5V, with Remote Sense
LTC3774
Dual, Multiphase Current Mode Synchronous
Step-Down Controller with Sub-Milliohm DCR
Sensing, Up to 12 Phases
VIN Up to 40V, 0.6V ≤ VOUT ≤ 3.5V, Very High Output Current Applications with
Accurate Current Share Between Phases Supporting LTC3880/-1, LTC3883/-1,
LTC3886, LTC3887/-1
LTC3877
Dual Phase Step-Down Synchronous Controller
with 6-Bit VID Output Voltage Programming and
Low Value DCR Sensing
4.5V ≤ VIN ≤ 38V, 0.6V ≤ VOUT ≤ 1.23V with VID in 10mV Steps, 0.6V ≤ VOUT ≤ 5V
without VID, Up to 12-Phase Operation
30
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LT 0517 REV C • PRINTED IN USA
For more information www.linear.com/LTC3874
www.linear.com/LTC3874
LINEAR TECHNOLOGY CORPORATION 2013
