LTC3884IUK

Care and Feeding of FPGA Power Supplies: A How and Why Guide to Success By Nathan Enger Share on Introduction Modern FPGAs are among the most complex integrated circuits ever created. They employ the most advanced transistor technology and cutting-edge architectural structures to achieve both incredible flexibility and the highest performance. Over time, as technology has advanced, this complexity has dictated certain compromises in the design and implementation of systems using the FPGAs. This is nowhere more apparent than in the power supplies, which must be ever more accurate, more agile, more controllable, smaller, more efficient, and more fault aware with each new FPGA generation. In this article, we look specifically at some of the constraining specifications for the Altera® Arria 10 FPGA, and what they mean for a power supply design. Then we discuss the best power delivery solutions, and lay out the plan to successfully meet all of the specifications and make our FPGA perform at its optimal efficiency, speed, and power level using Analog Devices’ complete set of power system management (PSM) ICs, including the LTC3887, LTC2977, and LTM4677. FPGA Power Requirements (Interpreting the Data Sheet) Notice the line labeled “SmartVID,” with a range of 0.82 V to 0.93 V. This represents a broad range of voltages that are possible when the FPGA is requesting its own core voltage through the SmartVID2 interface (more on this later). This SmartVID specification is an indication of an underlying truth about the FPGA: it can operate at different voltages, depending upon its particular manufacturing tolerance, and upon the particular logic design that it is implementing. The static voltage required by one FPGA might be different from another FPGA. The power supply must be able to respond and adapt. The goal is to produce just the right performance level to operate the programmed functions without burning unnecessary power. We know from semiconductor physics, as well as published data from Altera, Xilinx® (Figure 1), and others, that both dynamic and static power will increase dramatically with increased core VDD, so the goal is to give the FPGA just enough voltage to meet its timing requirements, but no more. Excess power dissipation does nothing to increase performance. In fact, it makes things worse because transistor leakage current increases with higher temperatures, dissipating even more unwanted power. For these reasons, the imperative is to optimize the voltage for the design and operating point. Relative Power Change with Core Voltage Change Voltage Accuracy Core power supply voltage is one of the most important keys to balancing FPGA power and performance. The specification documents give a range of acceptable voltages, but the total range is not the complete picture. As with all things, there are trade-offs and optimizations to be made. Table 1 is an example of core voltage specifications from the popular Altera Arria 10 FPGA.1 Though these numbers are specific to the Arria 10, they are representative of other FPGA core voltage requirements. The range amounts to a ±3.3% tolerance around the nominal voltage. The FPGA will operate just fine within this voltage window, but the complete picture is more complicated. Table 1. Altera Arria 10 Core Voltage Specification Symbol Description Condition Minimum Typical Maximum Unit VCC Core voltage power supply Standard and low power 0.87 0.9 0.93 V 0.92 0.95 0.98 V SmartVID 0.82 0.93 V Analog Dialogue 52-11, November 2018 15 10 Percent Power Change Engineers should spend most of their time programming—they don’t want to spend time and energy thinking about designing suitable power supplies. Indeed, the best approach to power delivery is to use a robust, flexible, proven design that meets the requirements and expands with the project. Here we take a closer look at some of the important power specifications and what they mean. 20 5 0 –5 –10 % Static Power % Dynamic Power –15 –20 –6 –4 –2 0 2 4 6 Percentage Voltage Change Figure 1. Xilinx Virtex V power vs. core VCC. This optimization process requires a very accurate power supply for success. Regulator inaccuracy must be baked into the error budget and subtracted from the available voltage range that can be used for optimization. If the core voltage drops below the requirement, the FPGA may fail due to timing errors. If core voltage drifts above the maximum specification, it may damage the FPGA, or it may create hold-time failures in the logic. All of these scenarios must be guarded against by taking into account the power supply tolerance range, and only commanding voltages that are guaranteed to remain within the specification limits. analogdialogue.com 1 Relative Current vs. Operating Temperature 10 9 8 IGATE IDRAIN ITOTAL 7 Relative Current The problem is that most power regulators are not accurate enough. The regulated voltage may be anywhere within the tolerance range around the commanded voltage, and it may drift with load conditions, temperature, and age. A power supply that guarantees a ±2% tolerance may regulate anywhere within a 4% voltage window. In order to compensate for the possibility that the voltage may be 2% too low, the commanded voltage must be raised by 2% above that required to meet timing. If the regulator then drifts to 2% above the commanded voltage, it will operate 4% above the minimum voltage required at that operating point. This still meets the specified voltage required by the FPGA, but it wastes a lot of power (Figure 2). 6 5 4 3 Max Spec 2 1 0 –50 0 Wasted Power Voltage Command Steps 100 150 200 Figure 3. Power supply current vs. operating temperature. Regulator Tolerance Commanded Voltage Min Spec Voltage Violation Figure 2. Power supply regulator tolerance trade-offs. The solution is to choose a power supply regulator that can operate with a much tighter voltage tolerance. A regulator with a ±0.5% tolerance can be commanded to operate much closer to the minimum required specification at the desired operating frequency, and it is guaranteed to be less than 1% from that required voltage. The FPGA will be functional and it will be dissipating the minimum power possible at that operating condition. The LTC388x family of power supply controllers guarantees regulated output voltage tolerance better than ±0.5% over a wide, configurable voltage range. The LTC297x family of power system managers guarantee a trimmed voltage regulator tolerance of better than ±0.25%. With these accuracies, there is a clear path to optimizing the power vs. performance trade-off for any FPGA. Thermal Management A more subtle implication of power supply accuracy manifests itself in the thermal budget. Because static power dissipation is far from negligible, the FPGA heats up even when it is doing nothing. The increased temperature causes more static power dissipation, which further increases operating temperature (Figure 3). Adding unnecessary voltage to the power supply only makes this problem worse. An inaccurate power supply requires a guard band in operating voltage to ensure that there is enough voltage to do the job. The power supply voltage uncertainty that results from variability in tolerance, system assembly variability, and operating temperature can create voltages significantly higher than the minimum required. This additional voltage, when applied to the FPGA, can cause thermal complications, or even thermal run-away at high processing loads. 2 50 Temperature (°C) The remedy is a very accurate power supply that creates just the right voltage, and no more than necessary, which is exactly what the ADI power system management (PSM) devices do well. SmartVID SmartVID is the Altera name for the technique of operating each individual FPGA at its optimal voltage, as requested by the FPGA itself. There is a register inside of the FPGA that contains a device-specific voltage (programmed at the factory) at which the FPGA is guaranteed to operate efficiently. A piece of compiled IP inside of the FPGA can read this register and make a request over an external bus to the power supply to provide this exact voltage (Figure 4). Once the voltage is reached, it remains static during operation. VCC FPGA VID Register Temperature Sensor VID Soft Controller IP Raw Data Voltage Regulator System Controller VRD Interface Programmable Voltage Regulator System Sense Lines Figure 4. Altera SmartVID structure. The demands of the SmartVID application on the power supply include the specific bus protocol, voltage accuracy, and speed. The bus protocol is one of several methods that the FPGA uses to communicate its required voltage to the power regulator. Of the available methods, PMBus is the most flexible because it addresses the widest variety of power management ICs. The SmartVID IP uses two PMBus commands: VOUT_MODE, and VOUT_COMMAND, with which it commands the PMBus-compliant power regulator to the correct voltage. The voltage accuracy and speed requirements for the regulator include an autonomous boot voltage (before the PMBus is active), the ability to accept a new voltage command every 10 ms, the ability to take 10 mV steps every 10 ms during the voltage adjustment phase, and the ability to settle to within 30 mV (~3%) of the target within the 10 ms step time, ultimately ramping to the commanded voltage and remaining static during FPGA operation. Analog Dialogue 52-11 November 2018 Though Altera uses SmartVID, there are other, similar techniques in use around the industry that accomplish much the same thing. One of the simplest is to test each board at the factory and program into the power supply’s nonvolatile memory an exact voltage that optimizes performance for that particular board. This technique does not require any further intervention for the power supply to operate at the correct voltage. This is an advantage of a power supply manager or controller with EEPROM. All of the requirements for Altera SmartVID can be met by the LTC388x family of power supply controllers. In addition, the LTM4675/LTM4676/ LTM4677 µModule regulators easily meet the requirements and offer a complete solution in a single compact form. Timing Closure The computing speed of any logic block depends on its supply voltage. Within limits, a higher voltage gives faster performance. We have already seen why we cannot simply operate at the highest voltage in order to guarantee the best speed. On the other hand, we must operate at a high enough voltage for the application, as shown in Figure 5. Operating Point VDD The Altera Arria 10 prescription divides the power supplies into three sequence groups (1, 2, and 3), and requires that they sequence up in order 1, 2, and 3, and down in the reverse order: 3, 2, and 1.3 Power-Up Sequence Requirement Group 1 VCC VCCR_GXB VCCERAM VCCP VCCT_GXB VCCL_HPS 90% of Nominal Voltage Group 1 Group 2 VCCPT VCCH_GXB VCCA_PLL VCCPLL_HPS VCCT_GXB VCCIOREF_HPS 90% of Nominal Voltage Group 2 Group 3 VCCPGM VCCIO_HPS VCCIO Group 3 Figure 6. Altera Arria 10 up-sequence group order. VMAX nc tio na l Similarly, the Xilinx recommendation for the Virtex UltraScale FPGA up-sequence is: VCCINT/VCCINT_IO, VCCBRAM, VCCAUX/VCCAUX_IO, and VCCO. Down-sequencing is the reverse of the up-sequence order.4 Fa ili ng Fu VOP Given the number of power supplies for each FPGA, the complexity of the sequencing task is considerable. These are just two of the many FPGAs available. Nearly every modern FPGA system has multiple power supply rails, and one of the most obvious questions to ask is, in what order should they turn on and off? Even if there is no explicit sequencing requirement there are good reasons to enforce a deterministic sequence of events. Here are some of the available design options. VMIN FOP No sequencing: Let the power supplies rise and fall on their own. What could go wrong? XX Hardware cascade sequencing: Each rising power supply is hardwired to enable the next one. This only works when the supplies are rising. XX CPLD-based sequencing: Use programmable logic to create a custom solution. This is flexible, but the entire challenge rests on the designer. XX Event-based sequencing: Event-based sequencing is similar to cascade sequencing, but more flexible because it can operate both up and down. A dedicated sequencer IC can be programmable and take care of many fault scenarios and corner cases. XX Time-based sequencing: Time-based sequencing triggers each event at a specified time. Coupled with comprehensive fault management, timebased sequencers can be flexible, deterministic, and safe. FCLK Figure 5. FPGA operating frequency vs. VDD trade-off. An important implication of Figure 5 is what can be done when a particular design does not meet its logic timing requirements, and falls into the failing area. Often the edge between functional and failing is not well defined before a design is committed to hardware, and the particular voltage at which it will pass timing cannot be predetermined. The only options are to either commit in advance to a voltage that is well above the minimum, thus wasting power to guarantee functionality, or to design a flexible power supply that can adapt to the needs of the hardware at test time, or even, as in the case of SmartVID, at power-up time. The ability to adapt to unknown demands makes the accuracy of ADI PSM devices more valuable, as FPGA designers can trade off power for performance in the real design, and at any stage of development. Power Supply Sequencing 101 Moore’s law drives the trend of shrinking transistors in modern FPGAs and forces the trade-offs involved in using these tiny transistors, which are very fast and small, but much more fragile. A chip containing hundreds of millions of transistors must be segmented into cores, blocks, and partitions that can be designed and managed independently. The practical result of these considerations is an FPGA with many power domains. Some recent FPGAs have upwards of a dozen power supplies that need to be kept happy. This includes, in addition to voltage, current, ripple, and noise, the sequence order during start-up, shutdown, and fault conditions. Recent FPGA specifications call out specific requirements for sequence order when starting-up and shutting down the power supplies. Both Xilinx and Altera recommend specific ordering and timing to ensure that the FPGA gets reset properly, maintains minimal current draw, and maintains its I/Os in the proper tristate configuration during the power transitions. Analog Dialogue 52-11, November 2018 XX The following sections explore these options in more detail. No Sequencing It is possible to turn-on a power supply system with no management at all. When main power becomes available, or the ON switch is activated, the regulators start regulating. When power is removed, or the ON switch turns off, the regulators stop regulating. Of course, the problems with this approach are many. Some more obvious than others. Lack of timing determinism can have various effects in a system. The first is simply that it stresses the sensitive FPGA. This might cause immediate catastrophic failure, or it might cause premature aging that slowly degrades performance. Neither is good. It may also cause unpredictable power-on-reset behavior or indeterminate logic states at power-up, which make system stability questionable and difficult to debug. Questions of fault detection and response, energy management, and debug support are left entirely unanswered in this scheme. In general, to avoid power supply sequencing is to invite disaster. 3 VDD12 VDD1 VDD2 Supply 1 VIN RUN Supply 2 VOUT RUN PGOOD VDD3 VIN A Supply 3 VOUT VIN B RUN PGOOD VOUT C RUN PGOOD READY Supply 3 VIN VOUT RUN PGOOD D VDD4 ... RUN ... A ... B ... C ... D ... READY Figure 7. PGOOD-to-RUN cascade sequencing. 12 V 5V 3.3 V 2.5 V DC-to-DC Converters 1.8 V 1.5 V 1.2 V V2 V1 CMP1 V3 V4 V5 System V6 CMP2 FPGA CMP3 GPIO1 CMP4 GPIO2 LTC2936 CMP5 UVDIS MARG GPIO3 OV RST ALERT CMP6 SDA GPI1 GPI2 VPWR VDD33 0.1 µF GND ASEL1 ASEL0 SCL 0.1 µF Figure 8. LTC2936 programmable voltage supervisor. Cascade Sequencing A slightly more organized approach to sequencing is the classic PGOODto-RUN hardwired cascade shown in Figure 7. This is like dominoes falling: each one taps the next in the sequence, which guarantees progress in order. This technique has the benefit of simplicity. Unfortunately, it also has its shortcomings. While it often works adequately for sequencing up a power system, it cannot operate in reverse (or in any other order) for down-sequencing. There can be only one sequence order. Additionally, this scheme cannot gracefully handle faults or manage energy in uncertain operating conditions. It is not smart enough to make any decisions. If one stage of the sequence fails, what happens next? If one operating power supply browns-out, what happens? The answers are undefined, and debugging these problems is not easy. a digital control block that can be programmed into an FPGA to control the power supply of another FPGA. Here the decision can be deceptive because a power supply system is not as simple as it may appear from a digital control perspective. FPGA or CPLD Sequencing Using an auxiliary CPLD or FPGA on the board to sequence the supplies is an option that many designers choose. In a system designed by and for digital designers, it has a certain appeal. There is a natural fit to designing For the intrepid designers who wish to take this path, Analog Devices provides several analog front-end ICs to help with the task. At the interface between the digital bits and the analog power supply, the LTC2936 provides six rugged, highly accurate programmable threshold analog comparators to 4 If designers wish to tackle the power supply sequencing, control, and management problem from top to bottom, they must first thoroughly understand its complexities. We have already discussed many of these, and there are more as well, such as detecting and responding to overvoltage and undervoltage conditions that can happen on the microsecond time scale, detecting hazardous currents and temperatures, logging telemetry and status, and providing bring-up and debug services to make life easier for the hardware guys. All of these considerations require dedicated analog hardware in addition to the digital algorithms. Analog Dialogue 52-11 November 2018 DC-to-DC Converters 12 V VIN SDA SCL ALERTB I2C/SMBus Interface VPWR LTC2937 ON MARGB FAULTB RSTB SPCLK SHARE_CLK ASEL1 ASEL2 ASEL3 WP VDD GND To/From Other Devices R1 3.3 kΩ C1 2.2 µF EN1 EN2 EN3 EN4 EN5 EN6 RUN1 RUN2 RUN3 RUN4 RUN5 RUN6 GND OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 5.0 V 3.3 V 2.5 V 1.8 V 1.5 V 1.2 V V1 V2 V3 V4 V5 V6 Figure 9. LTC2937 power supply supervisor and sequencer. DCIN IBC 4.5 V ≤ VIBUS ≤ 15 V IN OUT EN IIN_SNSP IIN_SNSM ISENSEP VIN_SNS VOUT DC-to-DC Converter AUXFAULTB *LTC2975 May Also Be Powered Directly from an External 3.3 V Supply PMBus Interface VPWR* VDD33* VFB ISENSEM VSENSEP LTC2975 SDA SCL VIN RUN Load VSENSEM VDAC ALERTB R20 R30 R10 CONTROL VOUT_EN FAULT TSENSE PWRGD GND MMBT3906 Note: Some Details Omitted for Clarity Only One of Four Channels Shown Figure 10. LTC2975 4-channel power system manager. detect fast events and send digital status to the logic. It also has three programmable GPIO pins for additional functionality. This programmable IC has an EEPROM for nearly instant-on functionality at start-up, and has the ability to store fault telemetry for debugging through its I2C/SMBus interface. A convenient way to use LTC2936 is shown in Figure 8. In addition to the fast comparator functions, there must be an analog-todigital converter (ADC) to gather telemetry. A proven choice is the LTC2418, which can monitor up to 16 channels of analog signals with its fast-settling 24 bit Σ-Δ ADC and 4-wire SPI interface. The board controller can readily stream measurements and monitor many points of interest in the system. In general, there are many, many options for using an FPGA or CPLD to control power sequencing. This approach works, but somebody must own the digital and analog designs, including all of the inevitable design bugs, opportunities for unimaginable corner cases and faults, and the unhappy question of support. There are certainly easier ways to build a power system. Simple Sequencer/Supervisors Solving the puzzle of robust sequencing and fault handling is the domain of the simple sequencer/supervisors. These do the important job of sequencing the power rails and ensuring that they remain within their specified limits during operation (supervision). The LTC2928 is an easy to use pin-strap configurable sequencer with configurable sequence timing (down is the reverse of up), and configurable supervisor voltage thresholds. Analog Dialogue 52-11, November 2018 It has the potential to meet the requirements, but has no frills and offers no digital programmability or telemetry. In the category of programmable sequencer and supervisor with EEPROM is the LTC2937. It features full digital programmability, features timebased and event-based sequencing, and can sequence and supervise any number of power supplies, handling faults, and logging fault status to the EEPROM black box. It is a worthy solution for cases where voltage management and telemetry are not required. Power System Management To fully capture all of the benefits of complete PSM, use one of the Analog Devices PSM ICs. These introduce the ability to autonomously sequence up and down any number of power rails; accurately control rail voltages to better than 0.5% (or 0.25% in some cases); measure and report voltage, current, temperature, and status telemetry; cooperatively handle complex fault scenarios; and record detailed fault information to EEPROM. Sequencing is done by a system of timing handshaking, with all ICs agreeing on time zero and the time base, and all sequence events happening at preprogrammed times (time-based sequencing). This allows any number of rails to sequence up and sequence down autonomously. The family of PSM ICs includes controllers that have their own switch drivers and analog loop control to handle the switching power supply in all 5 aspects. Alternatively, power supply managers contain a servo loop that wraps around an external power supply, adding all of the features of power supply management, including sequencing, supervision, and monitoring, to any power rail, from switching power regulators to LDO regulators. An example of a power supply manager is the LTC2975, pictured in Figure 10. µModule Devices The most tightly integrated solutions, providing the most functionality per square centimeter, in a BGA or LGA footprint, are PSM µModule® devices. These are complete power supply systems in a single package, including controller ICs, inductors, switches, and capacitors. Some µModule regulators, such as the LTM4650, do not contain digital functions, so they can benefit from additional sequencing and management with the LTC2975. Some µModule regulators, such as the LTM4676A, contain their own PSM functions and can easily integrate with other PSM ICs in the system. VIN 5.75 V to 26.5 V 22 µF ×3 On/Off Control Fault Interrupts, Power Sequencing VOUT0 VIN0 VIN1 VOSNS0+ SVIN RUN0 RUN1 VOUT0, Adjustable up to 13 A LOAD0 VOSNS0– LTM4676A GPIO0 GPIO1 VOUT1, Adjustable up to 13 A VOUT1 VOSNS1 LOAD1 PWM Clock and Time-Based Synchronization Register Write Protection SYNC SHARE_CLK WP GND 100 µF ×7 SGND 100 µF ×7 There is an additional consideration when sequencing down the supplies: energy management. Increasingly, it is important to provide deterministic timing for power supplies as they sequence down, and this requires carefully considering where the stored energy in the system is dissipated. A high power supply is likely to have dozens of large electrolytic capacitors as bulk charge storage elements, and these will be charged to the supply voltage, holding enough energy to blow-up an improperly protected device under unfortunate conditions. To avoid this, FPGA manufacturers specify a down-sequence that protects the device. For the Altera Arria 10 this sequence is shown in Figure 12.5 Power-Down Sequence Requirement Group 1 VCC VCCR_GXB VCCERAM Group 1 VCCP VCCT_GXB VCCL_HPS 10% of Nominal Voltage Group 2 VCCPT VCCH_GXB VCCA_PLL VCCPLL_HPS VCCT_GXB VCCIOREF_HPS GROUP 3 10% of Nominal Voltage Group 3 VCCPGM VCCIO_HPS Group 2 VCCIO Group 3 Figure 12. Altera Arria 10 down-sequence group order. SCL SDA ALERT I2C/SMBus I/F with PMBus Command Set to/from IPMI or Other Board Management Controller Figure 11. LTM4676A PSM µModule dual 13 A regulator. Shared Sequencing The PSM micromodules, manager ICs, and controller ICs all cooperate together in sequencing up and sequencing down by sharing timing information through a simple one-wire bus called SHARE_CLK. Through this single wire all of the PSM ICs share information about when sequencing should begin (time zero), when each tick of the clock occurs, and other status information that affects sequencing. It is enough to simply connect all of the SHARE_CLK pins together in the system to enable this coordination. Each IC has its own programming for sequence timing that can use the shared time base to accurately and reliably time events such as enabling and disabling, ramping, and timing-out in case of a fault. The SHARE_CLK pin, at its most basic level, is an open-drain, 100 kHz clock pin. The open-drain nature means that an IC can either pull-down actively or let go and allow the bus to float. When all devices on the bus let go, the pull-up resistors pull the voltage to 3.3 V. This allows one device to stop the clock by pulling down until it is ready, and means that all devices must agree before the clock can start: an effective mechanism for communicating time zero, as well as indicating sequencing status by stopping the clock. Shared Fault Handling Similar to the SHARE_CLK pin is the FAULT bus. Each of the PSM ICs in the system is connected to the shared FAULT wire, and can either pull it low using its open-drain output, or respond when another device pulls low. This provides a simple, quick way for the entire family of PSM devices to communicate and respond to faults. The behavior is fully configurable, and allows a coordinated response when something goes wrong, either during sequencing or during steady state. The system can be configured to remove power and attempt to re-sequence according to specified timing, while recording black-box information about the state of the system and causes of the fault when it occurred. This EEPROM black-box information is available for later processing over the I2C bus. 6 Down-Sequencing and Managing Stored Energy Implicit in this down-sequence is the requirement that all of that stored energy in the capacitors goes somewhere and is safely dissipated. There are several ways to do this. The simplest is a fixed resistor across the capacitor. This resistor always dissipates power while the supply is turned on, but its resistance can be made large enough that the comparative loss is minimal, and the RC discharge time constant is acceptably short. The time that it takes to sufficiently discharge the supply is a multiple (usually 5×) of the RC time constant, and should be optimized to make the static power dissipated in the resistor acceptable (