LTC3886/LTC3886-1
60V Dual Output
Step-Down Controller with Digital
Power System Management
DESCRIPTION
FEATURES
PMBus/I2C Compliant Serial Interface
n Telemetry Read-Back Includes V , I , V
IN IN OUT, IOUT,
Temperature and Faults
n Programmable Voltage, Current Limit, Digital
Soft-Start/Stop, Sequencing, Margining, OV/UV/OC,
Frequency, and Control Loop Compensation
n Output Error Less Than ±0.5% Over Temperature
n Integrated 16-Bit ADC and 12-Bit DAC
n Integrated High Side Current Sense Amplifier
n Internal EEPROM with ECC and Fault Logging
n Integrated N-Channel MOSFET Gate Drivers
Power Conversion
n Wide V Range: 4.5V to 60V
IN
n V
,
OUT0 VOUT1 Range: 0.5V to 13.8V
n Analog Current Mode Control
n Accurate PolyPhase® Current Sharing for
Up to 6 Phases (100kHz to 750kHz)
n Available in a 52-Lead (7mm × 8mm) QFN Package
n
APPLICATIONS
Telecom, Datacom, and Storage Systems
n Industrial and Point of Load Applications
The LTC®3886/LTC3886-1 is a dual PolyPhase DC/DC synchronous step-down switching regulator controller with
I2C-based PMBus compliant serial interface. This controller
employs a constant-frequency, current-mode architecture,
with high voltage input and output capability along with
programmable loop compensation. The LTC3886 is supported by the LTpowerPlay® software development tool with
graphical user interface (GUI).
The EXTVCC pin supports voltages up to 14V allowing for
optimized circuit efficiency and die temperature, and for
the controller output to supply the chip power. Switching
frequency, output voltage, and device address can be
programmed both by digital interface as well as external
configuration resistors. Parameters can be set via the
digital interface or stored in EEPROM. Both outputs have
an independent power good indicator and FAULT function.
The LTC3886 can be configured for discontinuous (pulseskipping) mode or continuous inductor current mode.
The LTC3886-1 also includes a sequencing off feature to
discharge very large output capacitors.
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. Patents including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 5408150,
6580258, 6304066, 7420359, 8786268 Patent Pending. Licensed under U.S. Patent 7000125
and other related patents worldwide.
n
TYPICAL APPLICATION
10µF
5mΩ
INTVCC VIN IIN+ IIN–
0.1µF
TG1
BOOST0
3.1µH
SW1
BG0
BG1
+
6.81k
0.22µF
VOUT0
5V
15A
530µF
+
10nF
BOOST1
SW0
6.82µH
4700pF
220pF
ISENSE0
–
90
FAULT MANAGEMENT
7.5k
80
1µF
70
TO/FROM
OTHER ADI DEVICES
+
ISENSE1
0.22µF 7.5k
–
ISENSE0
ISENSE1
EXTVCC
VSENSE0+
VSENSE1
VSENSE0–
TSNS0
TSNS1
ITH0
ITH1
ITHR0
ITHR1
VDD33 GND VDD25
1µF
VOUT1
12V
15A
+
2200pF
1µF
530µF
10nF
9
VIN = 48V
VOUT = 12V
fSW = 150kHz
8
7
6
60
5
50
4
40
3
30
2
20
10
0
0.01
EFFICIENCY
POWER LOSS
1
0.1
10
LOAD CURRENT (A)
1
0
100
3883 TA01b
220pF
*SOME DETAILS OMITTED FOR CLARITY
Document Feedback
100
POWER LOSS (W)
PMBus
INTERFACE
Efficiency and Power Loss
vs Load Current
0.1µF
LTC3886*
FAULT0
SDA
FAULT1
SCL
PGOOD0
ALERT
PGOOD1
RUN0
RUN1 SHARE_CLK
6.81k
1µF
TG0
VIN
18V TO 48V
1µF
EFFICIENCY (%)
10µF
2Ω
3886 TA01a
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Rev G
1
LTC3886/LTC3886-1
TABLE OF CONTENTS
Features...................................................... 1
Power Conversion.................................................1
Applications................................................. 1
Typical Application ......................................... 1
Description.................................................. 1
Absolute Maximum Ratings............................... 4
Order Information........................................... 4
Pin Configuration........................................... 4
Electrical Characteristics.................................. 5
Typical Performance Characteristics................... 10
Pin Functions............................................... 13
Block Diagram.............................................. 15
Operation................................................... 16
Overview.................................................................. 16
Main Control Loop................................................... 16
EEPROM.................................................................. 17
Power-Up and Initialization...................................... 17
Soft-Start................................................................. 18
Time-Based Sequencing.......................................... 18
Event-Based Sequencing......................................... 19
Shutdown................................................................ 19
Light-Load Current Operation..................................20
PWM Loop Compensation.......................................20
Switching Frequency and Phase..............................20
Output Voltage Sensing........................................... 21
Output Current Sensing........................................... 21
Input Current Sensing.............................................. 21
PolyPhase Load Sharing..........................................22
External/Internal Temperature Sense.......................22
RCONFIG (Resistor Configuration) Pins...................23
Fault Handling..........................................................23
Status Registers and ALERT Masking.................. 24
Mapping Faults to FAULT Pins.............................26
Power Good Pins.................................................26
CRC Protection ...................................................26
Serial Interface........................................................26
Communication Protection ................................. 27
Device Addressing................................................... 27
2
Responses to VOUT and IOUT Faults/Warnings......... 27
Output Overvoltage Fault Response.................... 27
Output Undervoltage Response .......................... 28
Peak Output Overcurrent Fault Response............ 28
Responses to Timing Faults..................................... 28
Responses to VIN OV Faults..................................... 28
Responses to OT/UT Faults...................................... 28
Internal Overtemperature Fault/Warn
Response............................................................. 28
External Overtemperature and Undertemperature
Fault Response ...................................................29
Responses to External Faults ..................................29
Fault Logging...........................................................29
Bus Timeout Protection...........................................29
Similarity Between PMBus, SMBus and I2C
2-Wire Interface.......................................................30
PMBus Serial Digital Interface.................................30
PMBus Command Summary............................. 35
PMBus Commands..................................................35
*Data Format...........................................................40
Applications Information................................. 41
Current Limit Programming..................................... 41
ISENSE+ and ISENSE– Pins.......................................... 41
Low Value Resistor Current Sensing........................ 42
Inductor DCR Current Sensing.................................43
Slope Compensation and Inductor Peak Current.....44
Inductor Value Calculation.......................................44
Inductor Core Selection...........................................45
Power MOSFET and Optional Schottky Diode
Selection..................................................................45
CIN and COUT Selection............................................46
Variable Delay Time, Soft-Start and Output Voltage
Ramping..................................................................46
Digital Servo Mode.................................................. 47
Soft Off (Sequenced Off).........................................48
INTVCC Regulator..................................................... 49
Topside MOSFET Driver Supply (CB, DB).................50
Undervoltage Lockout..............................................50
Rev G
For more information www.analog.com
LTC3886/LTC3886-1
TABLE OF CONTENTS
Fault Indications......................................................50
Open-Drain Pins...................................................... 51
Phase-Locked Loop and Frequency
Synchronization....................................................... 51
Minimum On-Time Considerations.......................... 52
External Temperature Sense.................................... 52
Derating EEPROM Retention at Temperature.......53
Input Current Sense Amplifier..................................54
External Resistor Configuration Pins (RCONFIG).....54
Voltage Selection.................................................54
Frequency Selection ...........................................55
Phase Selection...................................................56
Address Selection Using RCONFIG......................56
Efficiency Considerations........................................56
Programmable Loop Compensation........................ 57
Checking Transient Response..................................58
PolyPhase Configuration......................................... 59
PC Board Layout Checklist...................................... 59
PC Board Layout Debugging....................................62
Design Example.......................................................63
Additional Design Checks........................................65
Connecting the USB to I2C/SMBus/PMBus Adapter to
the LTC3886 In System...........................................65
LTpowerPlay: An Interactive GUI for Digital Power..66
PMBus Communication and Command
Processing...............................................................66
PMBus Command Details................................ 69
Addressing and Write Protect..................................69
General Configuration COMMANDS......................... 71
On/Off/Margin.........................................................72
ON_OFF_CONFIG.....................................................73
PWM Configuration................................................. 74
Voltage..................................................................... 78
Input Voltage and Limits...................................... 78
Output Voltage and Limits................................... 79
For EnableMfrVoffThreshold = 0......................... 81
For EnableMfrVoffThreshold = 1.........................82
Output Current and Limits....................................... 82
Input Current and Limits .....................................84
Temperature.............................................................85
External Temperature Calibration........................85
Timing.....................................................................86
Timing—On Sequence/Ramp..............................86
Timing—Off Sequence/Ramp............................. 87
Precondition for Restart......................................88
Fault Response........................................................88
Fault Responses All Faults...................................88
Fault Responses Input Voltage............................89
Fault Responses Output Voltage..........................89
Fault Responses Output Current..........................92
Fault Responses IC Temperature.........................93
Fault Responses External Temperature................94
Fault Sharing............................................................95
Fault Sharing Propagation...................................95
Fault Sharing Response....................................... 97
Scratchpad.............................................................. 97
Identification............................................................98
Fault Warning and Status.........................................99
Telemetry............................................................... 106
EEPROM Memory Commands............................... 110
Store/Restore.................................................... 110
Fault Logging......................................................111
Fault Log Operation............................................111
Block Memory Write/Read................................ 116
Typical Applications..................................... 117
Package Description.................................... 120
Revision History......................................... 121
Typical Application...................................... 122
Related Parts............................................. 122
Rev G
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3
LTC3886/LTC3886-1
* See Derating EEPROM Retention at Temperature in the Applications
Information section for junction temperatures in excess of 125°C.
BG1
INTVCC
VIN
48 47 46
IIN–
BG0
50
IIN+
BOOST0
52
44 43 42
SW0 1
40 BOOST1
TG0 2
39 SW1
38 TG1
ISENSE0+ 4
ISENSE0– 5
36 TSNS1
TSNS0 6
35 VSENSE1+
VSENSE0+ 7
34 PGOOD0
53
GND
VSENSE0– 8
33 PGOOD1
ISENSE1+ 9
32 ITHR1
ISENSE1– 10
31 ITH1
30 VDD33
ITHR0 11
ITH0 12
29 SHARE_CLK
28 WP
SYNC 13
27 VDD25
SCL 14
PHAS_CFG
FREQ_CFG
VOUT1_CFG
VOUT0_CFG
ASEL1
ASEL0
RUN1
RUN0
FAULT1
FAULT0
15 16 17 18 19 20 21 22 23 24 25 26
SDA
Top Gate Transient Voltage (TG0, TG1)........–0.3V to 71V
BOOST0, BOOST1........................................–0.3V to 71V
Switch Transient Voltage (SW0, SW1)........... –5V to 65V
INTVCC, BG0, BG1, (BOOST0– SW0),
(BOOST1– SW1)........................................... –0.3V to 6V
VSENSE0+, VSENSE1+, ISENSE0+, ISENSE1+,
ISENSE0 –, ISENSE1–, EXTVCC......................... –0.3V to 15V
VSENSE0 –.................................................... –0.3V to 0.3V
RUN, SDA, SCL, ALERT.............................. –0.3V to 5.5V
ASELn, VOUTn_CFG, FREQ_CFG,
PHAS_CFG, VDD25................................... –0.3V to 2.75V
(VIN – IINP), (VIN – IINM)............................. –0.3V to 0.3V
PGOOD0, PGOOD1, FAULT, SHARE_CLK,
ITH0, ITH1, ITHR0, ITHR1, VDD33, WP,
TSNS0, TSNS1, SYNC................................ –0.3V to 3.6V
(EXTVCC – VIN).......................................................13.2V
INTVCC Peak Output Current.................................100mA
Operating Junction Temperature Range
(Notes 2, 15, 16)............................... –40°C to 125°C*
Storage Temperature Range................. –65°C to 150°C*
TOP VIEW
EXTVCC
PIN CONFIGURATION
(Note 1)
VIN, IIN+, IIN –............................................... –0.3V to 65V
ALERT
ABSOLUTE MAXIMUM RATINGS
UKG PACKAGE
VARIATION: UKG52(46)
52-LEAD (7mm × 8mm) PLASTIC QFN
TJMAX = 125°C, θJA = 31°C/W, θJC = 2°C/W
EXPOSED PAD (PIN 53) IS GND, MUST BE SOLDERED TO PCB
Note: Pins omitted to achieve high input voltage rating.
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3886EUKG#PBF
LTC3886EUKG#TRPBF
LTC3886UKG
52-Lead (7mm × 8mm) Plastic QFN
–40°C to 125°C
LTC3886IUKG#PBF
LTC3886IUKG#TRPBF
LTC3886UKG
52-Lead (7mm × 8mm) Plastic QFN
–40°C to 125°C
LTC3886EUKG-1#PBF
LTC3886EUKG-1#TRPBF
LTC38861UKG
52-Lead (7mm × 8mm) Plastic QFN
–40°C to 125°C
LTC3886IUKG-1#PBF
LTC3886IUKG-1#TRPBF
LTC38861UKG
52-Lead (7mm × 8mm) Plastic QFN
–40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
4
Rev G
For more information www.analog.com
LTC3886/LTC3886-1
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). VIN = 16V, EXTVCC = 0V, VRUN0 = 3.3V, VRUN1 = 3.3V
fSYNC = 350kHz (externally driven), and all programmable parameters at factory default unless otherwise specified.
SYMBOL
PARAMETER
Input Voltage
Input Voltage Range
VIN
Input Voltage Supply Current
IQ
Normal Operation
VUVLO
TINIT
Undervoltage Lockout Threshold
When VIN > 4.2V
Initialization Time
Control Loop
Range 0 Maximum VOUT
VOUTR0
Range 0 Set Point Accuracy
Range 0 Resolution
Range 0 LSB Step Size, FSR = 16.38
Range 1 Maximum VOUT
VOUTR1
Range 1 Set Point Accuracy
Range 1 Resolution
Range 1 LSB Step Size, FSR = 8.19V
Line Regulation
VLINEREG
Load Regulation
VLOADREG
gm0,1
RITHR0,1
IISENSE
IVSENSE0
IVSENSE1
VI(lLIMIT)
Resolution
Error Amplifier gm(MAX)
Error Amplifier gm(MIN)
Error Amplifier gm LSB Step Size
Resolution
Compensation Resistor RITHR(MAX)
Compensation Resistor RITHR(MIN)
Input Current
VSENSE0 Input Current
VSENSE1 Input Current
Resolution
VILIM(MAX)
VILIM(MIN)
Gate Driver
TG
tr
tf
BG
tr
tf
TG/BG t1D
BG/TG t2D
tON(MIN)
TG Transition Time:
Rise Time
Fall Time
BG Transition Time:
Rise Time
Fall Time
Top Gate Off to Bottom Gate On Delay Time
Bottom Gate Off to Top Gate On Delay Time
Minimum On-Time
CONDITIONS
MIN
(Note 12)
(Note 14)
VRUN = 3.3V, No Caps on TG and BG
VRUN = 0V
VINTVCC Falling
VINTVCC Rising
Delay from RESTORE_USER_ALL,
MFR_REST, or VINTVCC > VUVLO Until
TON_DELAY Can Begin
l
2.0V ≤ VOUT ≤ 13.8V
l
4.5
(Notes 9, 10)
16V < VIN < 60V
∆VITH = 1.35V – 0.7V
∆VITH = 1.35V – 2.0V
–0.5
l
–0.5
60
14.0
12
4
7.0
12
2
l
0.01
–0.01
3
5.76
1.00
0.68
5
62
0
±1
l
l
ITH =1.35V
ITH =1.35V
ITH =1.35V
VISENSE = 14V
VPIN = 14V
VPIN = 14V
l
Hi Range
Lo Range
Hi Range
Lo Range
l
l
(Note 4)
CLOAD = 3300pF
CLOAD = 3300pF
(Note 4)
CLOAD = 3300pF
CLOAD = 3300pF
(Note 4) CLOAD = 3300pF
(Note 4) CLOAD = 3300pF
MAX
26
22
3.7
3.95
35
(Notes 9, 10)
1.0V ≤ VOUT ≤ 6.6V
TYP
l
l
68
44
3
75
50
37.5
25
UNITS
V
mA
mA
V
V
ms
0.5
0.5
±0.02
0.1
–0.1
±2
250
315
82
56
V
%
Bits
mV
V
%
Bits
mV
%/V
%
%
bits
mmho
mmho
mmho
bits
kΩ
kΩ
µA
µA
µA
bits
mV
mV
mV
mV
30
30
ns
ns
20
20
10
30
90
ns
ns
ns
ns
ns
Rev G
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5
LTC3886/LTC3886-1
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). VIN = 16V, EXTVCC = 0V, VRUN0 = 3.3V, VRUN1 = 3.3V
fSYNC = 350kHz (externally driven), and all programmable parameters at factory default unless otherwise specified.
SYMBOL
PARAMETER
OV/UV Output Voltage Supervisor
N
Resolution
Range 0 Maximum Threshold
VRANGE0
Range 1 Maximum Threshold
VRANGE1
Range 0 Step Size, FSR = 16.352V
VOUSTP0
Range 1 Step Size, FSR = 8.176V
VOUSTP1
Range 0 Threshold Accuracy
VTHACC0
Range 1 Threshold Accuracy
VTHACC1
OV Comparator to FAULT Low Time
tPROPOV1
UV Comparator to FAULT Low Time
tPROPUV1
VIN Voltage Supervisor
N
Resolution
Full-Scale Voltage
VIN(RANGE)
Step Size
VIN(STP)
VIN(THACCH) Threshold Accuracy 12V < VIN < 60V
VIN(THACCL) Threshold Accuracy 4.5V < VIN < 15V
Comparator Response Time
tPROP(VIN)
(VIN_ON and VIN_OFF)
Output Voltage Readback
N
Resolution
LSB Step Size
Full-Scale Sense Voltage
VF/S
Total Unadjusted Error
VOUT_TUE
Zero-Code Offset Voltage
VOS
Conversion Time
tCONVERT
VIN Voltage Readback
N
Resolution
Full-Scale Input Voltage
VF/S
Total Unadjusted Error
VIN_TUE
CONDITIONS
MIN
l
l
l
l
VOD = 10% of Threshold
16
250
16.384
0.2
l
l
(Note 6)
(Note 5)
(Note 11)
TJ = 25°C, VVIN > 4.5V
IF/S
IOUT_TUE
VOS
tCONVERT
6
Full-Scale Output Current
Total Unadjusted Error
Zero-Code Offset Voltage
Conversion Time
(Note 6)
±3
±6
100
Bits
V
mV
%
%
µs
±0.5
±500
10
66.56
(Note 6)
(Note 5)
0V ≤ |VISENSE+ – VISENSE–| < 16mV
16mV ≤ |VISENSE+ – VISENSE–| < 32mV
32mV ≤ |VISENSE+ – VISENSE–| < 64mV
64mV ≤ |VISENSE+ – VISENSE–| < 100mV
(Note 7) RISENSE = 1mΩ
(Note 8) 10mV ≤ VISENSE ≤ 100mV
±2.5
±2.5
35
100
Bits
V
V
mV
mV
%
%
µs
µs
90
0.4
2
l
Conversion Time
tCONVERT
Output Current Readback
N
Resolution
LSB Step Size
UNITS
9
61.32
120
(Note 11)
(Note 10) VRUN = 0V (Note 8)
TJ = 25°C, VOUT > 1.0V
(Note 8)
MAX
9
14
7
32
16
(Note 10)
2V < VOUT < 14V
1V < VOUT < 7V
VOD = 10% of Threshold
VOD = 10% of Threshold
TYP
90
10
15.26
30.52
61
122
±100
±1.5
±32
l
90
Bits
µV
V
%
%
µV
ms
Bits
V
%
%
ms
Bits
µV
µV
µV
µV
A
%
µV
ms
Rev G
For more information www.analog.com
LTC3886/LTC3886-1
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). VIN = 16V, EXTVCC = 0V, VRUN0 = 3.3V, VRUN1 = 3.3V
fSYNC = 350kHz (externally driven), and all programmable parameters at factory default unless otherwise specified.
SYMBOL
PARAMETER
Input Current Readback
N
Resolution
LSB Step Size, Full-Scale Range = 16mV
LSB Step Size, Full-Scale Range = 32mV
LSB Step Size, Full-Scale Range = 64mV
Total Unadjusted Error (Note 8)
IIN_TUE
Input Current, IIN+ and IIN–
IIIN
Zero-Code Offset Voltage
VOS
Conversion Time
tCONVERT
Supply Current Readback
N
Resolution
LSB Step Size, Full-Scale Range = 256mV
Total Unadjusted Error
ICHIP_TUE
Conversion Time
tCONVERT
Temperature Readback (T0, T1)
Resolution
TRES_T
T0_TUE
External TSNS TUE (Note 8)
MFR_PWM_MODE_LTC3886[5] = 0
MFR_PWM_MODE_LTC3886[5] = 1
TI_TUE
Internal TSNS TUE
Update Rate
tCONVERT_T
INTVCC Regulator
VINTVCC_VIN Internal VCC Voltage No Load
INTVCC Load Regulation
VLDO_VIN
VINTVCC_EXT Internal VCC Voltage No Load
INTVCC Load Regulation
VLDO_EXT
VEXT_THRES EXTVCC Switchover Voltage
EXTVCC Hysteresis Voltage
VEXT_HYS
VDD33 Regulator
Internal VDD33 Voltage
VDD33
VDD33 Current Limit
ILIM
VDD33 Overvoltage Threshold
VDD33_OV
VDD33 Undervoltage Threshold
VDD33_UV
VDD25 Regulator
Internal VDD25 Voltage
VDD25
VDD25 Current Limit
ILIM
Oscillator and Phase-Locked Loop
Oscillator Frequency Accuracy
fOSC
VTH(SYNC)
SYNC Input Threshold
VOL(SYNC)
ILEAK(SYNC
SYNC Low Output Voltage
SYNC Leakage Current in Slave Mode
CONDITIONS
(Note 5)
8x Gain, 0V ≤ |IIN+ – IIN–| ≤ 5mV
4x Gain, 0V ≤ |IIN+ – IIN–| ≤ 20mV
2x Gain, 0V ≤ |IIN+ – IIN–| ≤ 50mV
8x Gain, 2.5mV ≤ |IIN+ – IIN–| ≤ 5mV
4x Gain, 4mV ≤ |IIN+ – IIN–| ≤ 20mV
2x Gain, 6mV ≤ |IIN+ – IIN–| ≤ 50mV
VIN = VIIN+ = VIIN– = 30V
MIN
TYP
10
15.26
30.52
61
±1.6
±1.3
±1.2
±2
±50
l
l
l
l
(Note 6)
90
(Note 5)
10
244
20mV ≤ |IIN+ – VIN| ≤ 200mV
(Note 6)
6V < VIN < 60V
ICC = 0mA to 50mA
5.5V < EXTVCC < 14V
ICC = 0mA to 50mA, EXTVCC = 12V
EXTVCC Ramping Positive
l
4.8
l
4.8
0.25
°C
±3
±7
°C
°C
°C
ms
5
0.5
5
0.5
4.7
80
5.2
±2
5.2
±2
4.95
V
%
V
%
V
mV
3.3
100
3.5
3.1
3.4
V
mA
V
V
±1
90
4.5
4.5V < VINTVCC
VDD33 = GND, VIN = INTVCC = 4.5V
3.2
2.5
80
VDD25 = GND, VIN = INTVCC = 4.5V
l
l
Bits
µV
µV
µV
%
%
%
µA
µV
ms
90
±2.5
l
l
UNITS
Bits
µV
%
ms
l
�VTSNS = 72mV (Note 17)
VTSNS ≤ 1.85V (Note 17)
VRUN = 0.0V (Note 8)
(Note 6)
100kHz < fSYNC < 750kHz Measured
Falling Edge-to-Falling Edge of SYNC with
FREQUENCY_SWITCH = 100.0 and 750.0
VCLKIN Falling
VCLKIN Rising
ILOAD = 3mA
0V ≤ VPIN ≤ 3.6V
MAX
1
1.5
0.2
V
mA
±10
%
0.4
±5
V
V
V
µA
Rev G
For more information www.analog.com
7
LTC3886/LTC3886-1
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). VIN = 16V, EXTVCC = 0V, VRUN0 = 3.3V, VRUN1 = 3.3V
fSYNC = 350kHz (externally driven), and all programmable parameters at factory default unless otherwise specified.
SYMBOL
SYNC-0
CONDITIONS
MFR_PWM_CONFIG_LTC3886[2:0] = 0,2,3
MFR_PWM_CONFIG_LTC3886[2:0] = 5
MFR_PWM_CONFIG_LTC3886[2:0] = 1
MFR_PWM_CONFIG_LTC3886[2:0] = 4,6
SYNC-1
SYNC to Channel 1 Phase Relationship Based MFR_PWM_CONFIG_LTC3886[2:0] = 3
on the Falling Edge of Sync and Rising Edge MFR_PWM_CONFIG_LTC3886[2:0] = 0
MFR_PWM_CONFIG_LTC3886[2:0] = 2,4,5
of TG1
MFR_PWM_CONFIG_LTC3886[2:0] = 1
MFR_PWM_CONFIG_LTC3886[2:0] = 6
EEPROM Characteristics
Endurance
(Note 13)
0°C < TJ < 85°C During EEPROM Write
Operations
Retention
(Note 13)
TJ < 125°C
Mass_Write Mass Write Operation Time
STORE_USER_ALL, 0°C < TJ ≤ 85°C
During EEPROM Write Operations
Digital Inputs SCL, SDA, RUNn, FAULTn
Input High Threshold Voltage
SCL, SDA, RUN, FAULT
VIH
Input Low Threshold Voltage
SCL, SDA, RUN, FAULT
VIL
Input Hysteresis
SCL, SDA
VHYST
Input Capacitance
CPIN
Digital Input WP
Input Pull-Up Current
WP
IPUWP
Open-Drain Outputs SCL, SDA, FAULTn, ALERT, RUNn, SHARE_CLK, PGOODn
Output Low Voltage
ISINK = 3mA
VOL
Digital Inputs SHARE_CLK, WP
Input High Threshold Voltage
VIH
Input Low Threshold Voltage
VIL
Leakage Current SDA, SCL, ALERT, RUN
Input Leakage Current
0V ≤ VPIN ≤ 5.5V
IOL
Leakage Current FAULTn, PGOODn
Input Leakage Current
0V ≤ VPIN ≤ 3.6V
IGL
Digital Filtering of FAULTn
Input Digital Filtering FAULTn
tFAULT
Digital Filtering of PGOODn
Output Digital Filtering PG00Dn
tPGOOD
Digital Filtering of RUNn
Input Digital Filtering RUNn
tRUN
PMBus Interface Timing Characteristics
Serial Bus Operating Frequency
fSCL
Bus Free Time Between Stop and Start
tBUF
Hold Time After Start Condition. After This
tHD(STA)
Period, the First Clock Is Generated
Repeated Start Condition Setup Time
tSU(STA)
Stop Condition Setup Time
tSU(STO)
Data Hold Time
tHD(DAT)
Receiving Data
Transmitting Data
8
PARAMETER
SYNC to Channel 0 Phase Relationship Based
on the Falling Edge of Sync and Rising Edge
of TG0
MIN
TYP
0
60
90
120
120
180
240
270
300
MAX
UNITS
Deg
Deg
Deg
Deg
Deg
Deg
Deg
Deg
Deg
l
10,000
Cycles
l
10
Years
ms
440
l
1.35
l
l
4100
0.8
0.08
10
10
V
V
V
pF
µA
0.4
V
1.8
V
V
l
±5
µA
l
±2
µA
l
l
l
0.6
1.5
1.0
3
µs
60
µs
10
µs
10
1.3
0.6
400
kHz
µs
µs
0.6
0.6
10000
l
µs
µs
l
l
0
0.3
l
l
l
l
0.9
µs
µs
Rev G
For more information www.analog.com
LTC3886/LTC3886-1
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). VIN = 16V, EXTVCC = 0V, VRUN0 = 3.3V, VRUN1 = 3.3V
fSYNC = 350kHz (externally driven), and all programmable parameters at factory default unless otherwise specified.
SYMBOL
tSU,DAT
PARAMETER
Data Setup Time
Receiving Data
tTIMEOUT_SMB Stuck PMBus Timer Non-Block Reads
Stuck PMBus Timer Block Reads
Serial Clock Low Period
tLOW
Serial Clock High Period
tHIGH
CONDITIONS
MIN
l
MAX
0.1
Measured from the Last PMBus Start Event
32
255
l
l
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3886 is tested under pulsed load conditions such that TJ ≈
TA. The LTC3886E is guaranteed to meet performance specifications from
0°C to 85°C. Specifications over the –40°C to 125°C operating junction
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC3886I is guaranteed over the
–40°C to 125°C operating junction temperature range. TJ is calculated from
the ambient temperature, TA, and power dissipation, PD, according to the
following formula:
TJ = TA + (PD • JA)
The maximum ambient temperature consistent with these specifications
is determined by specific operating conditions in conjunction with board
layout, the rated package thermal impedance and other environmental
factors.
Note 3: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
Note 4: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 5: The data format in PMBus is 5 bits exponent (signed) and 11 bits
mantissa (signed). This limits the output resolution to 10 bits though the
internal ADC is 16 bits and the calculations use 32-bit words.
Note 6: The data conversion is done in round robin fashion. All input
signals are continuously converted for a typical latency of 90ms. Unless
the MFR_ADC_CONTROL command is utilized.
Note 7: The IOUT_CAL_GAIN = 1.0mΩ and MFR_IOUT_TC = 0.0. Value as
read from READ_IOUT in amperes.
TYP
1.3
0.6
10000
UNITS
µs
ms
ms
µs
µs
Note 8: Part tested with PWM disabled. Evaluation in application
demonstrates capability. TUE (%) = ADC Gain Error (%) + 100 •
[Zero Code Offset + ADC Linearity Error]/Actual Value.
Note 9: All VOUT commands assume the ADC is used to auto-zero the
output to achieve the stated accuracy. LTC3886 is tested in a feedback
loop that servos VOUT to a specified value.
Note 10: The maximum programmable VOUT voltage is 13.8V.
Note 11: The maximum VIN voltage is 60V.
Note 12: When VIN < 6V, INTVCC must be tied to VIN.
Note 13: EEPROM endurance is guaranteed by design, characterization
and correlation with statistical process controls. Data retention is
production tested via a high temperature bake at wafer level. The minimum
retention specification applies for devices whose EEPROM has been cycled
less than the minimum endurance specification. The RESTORE_USER_ALL
command (EEPROM read) is valid over the entire operating temperature
range.
Note 14: The LTC3886 quiescent current (IQ) equals the IQ of VIN plus the
IQ of EXTVCC.
Note 15: The LTC3886 includes overtemperature protection that is
intended to protect the device during momentary overload conditions.
Junction temperature will exceed 125°C when overtemperature protection
is active. Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
Note 16: Write operations above TJ = 85°C or below 0°C are possible
although the Electrical Characteristics are not guaranteed and the EEPROM
will be degraded. Read operations performed at temperatures between
–40°C and 125°C will not degrade the EEPROM. Writing to the EEPROM
above 85°C will result in a degradation of retention characteristics.
Note 17: Limits guaranteed by TSNS voltage and current measurements
during test, including ADC readback.
Rev G
For more information www.analog.com
9
LTC3886/LTC3886-1
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25C, VIN = 16V, EXTVCC = 0V, unless otherwise noted.
70
70
EFFICIENCY (%)
80
60
50
40
VIN = 48V
VOUT = 12V
fSW = 150kHz
L = 6.8µH
DCR = 1.86mΩ
30
20
10
0
0.01
0.1
1
10
LOAD CURRENT (A)
98
CCM
DCM
90
80
Efficiency and Power Loss
vs Input Voltage
60
50
40
VIN = 48V
VOUT = 5V
fSW = 150kHz
L = 6.8µH
DCR = 1.86mΩ
30
20
10
0
0.01
100
0.1
1
10
LOAD CURRENT (A)
3886 G01
97
8
96
6
95
94
100
10
EFFICIENCY
POWER LOSS
4
VIN = 12V
fSW = 150kHz
L = 6.8µH
DCR = 1.86mΩ
18
28
38
48
2
VIN (V)
3883 G02
EXTVCC Switchover
vs Temperature
POWER LOSS (W)
EFFICIENCY (%)
100
CCM
DCM
90
Efficiency vs Load Current,
VOUT = 5V
EFFICIENCY (%)
100
Efficiency vs Load Current,
VOUT = 12V
3886 G03
Load Step
(Forced Continuous Mode)
Load Step
(Pulse-Skipping Mode)
4.710
ILOAD
5A/DIV
ILOAD
5A/DIV
INDUCTOR
CURRENT
5A/DIV
INDUCTOR
CURRENT
5A/DIV
VOUT
100mV/DIV
AC-COUPLED
VOUT
100mV/DIV
AC-COUPLED
4.708
EXTVCC (V)
4.706
4.704
4.702
4.700
–50
VIN = 12V
50µs/DIV
VOUT = 1.8V
0.3A TO 5A STEP
–25
25
50
75
0
TEMPERATURE (°C)
100
3886 G05
VIN = 12V
50µs/DIV
VOUT = 1.8V
0.3A TO 5A STEP
3886 G06
125
3886 G04
Inductor Current at Light Load
Start-Up into a Pre-Biased Load
FORCED
CONTINUOUS
MODE
2A/DIV
Soft-Start Ramp
RUN
2V/DIV
RUN
2V/DIV
VOUT
1V/DIV
VOUT
1V/DIV
PULSE-SKIPPING
MODE
2A/DIV
VIN = 12V
VOUT = 1.8V
ILOAD = 100µA
10
1µs/DIV
3886 G07
tRISE = 10ms
tDELAY = 5ms
VOUT = 2V
5ms/DIV
3886 G08
tRISE = 10ms
tDELAY = 5ms
5ms/DIV
3886 G09
Rev G
For more information www.analog.com
LTC3886/LTC3886-1
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25C, VIN = 16V, EXTVCC = 0V, unless otherwise noted.
Regulated Output Voltage
vs Temperature
Soft-Off Ramp
0.5020
RUN
2V/DIV
0.5015
VOUT (V)
0.5010
VOUT
1V/DIV
0.5005
0.5000
0.4995
0.4990
tFALL = 5ms
tDELAY = 10ms
3886 G10
5ms/DIV
0.4985
0.4980
0.4975
–50 –25
55
MAXIMUM CURRENT SENSE THRESHOLD (mV)
0.5025
0
Maximum Current Sense Threshold
vs Duty Cycle, VOUT = 0V
50mV SENSE CONDITION
54
53
52
51
50
49
48
47
46
45
25 50 75 100 125 150
TEMPERATURE (°C)
30
0
70
50
DUTY CYCLE (%)
90
3886 G12
3886 G11
SHARE_CLK Frequency
vs Temperature
Quiescent Current vs Temperature
105
100
95
VOUT Measurement Error vs VOUT
25.0
0.6
24.5
0.4
MEASURED ERROR (mV)
QUIESCENT CURRENT (mA)
SHARE_CLK FREQUENCY (kHz)
110
24.0
23.5
23.0
0.2
0
–0.2
–0.4
22.5
90
–50 –25
0
22.0
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
50
25
75
0
TEMPERATURE (°C)
100
3883 G13
125
–0.6
0
2
8
6
VOUT (V)
4
10
12
3886 G14
VOUT Command INL
3886 G15
VOUT Command DNL
0.8
5.25
0.4
14
INTVCC Line Regulation
0.6
0.4
DNL (LSBs)
0
–0.2
–0.4
–0.6
4.75
INTVCC (V)
0.2
INL (LSBs)
5.00
0.2
0
4.50
–0.2
–0.8
4.25
–1.0
–1.2
0
4
8
12
16
–0.4
0
4
8
16
12
VOUT (V)
VOUT (V)
3886 G16
3886 G17
4.00
0
10
20
30
VIN (V)
40
50
60
3886 G18
Rev G
For more information www.analog.com
11
LTC3886/LTC3886-1
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25C, VIN = 16V, EXTVCC = 0V, unless otherwise noted.
VOUT OV Threshold
vs Temperature (1V Target)
VOUT OV Threshold
vs Temperature (5V Target)
1.000
0.995
5.02
12.03
5.01
12.02
12V OV THRESHOLD (V)
1.005
5V OV THRESHOLD (V)
1V OV THRESHOLD (V)
1.010
VOUT OV Threshold
vs Temperature (12V Target)
5.01
12.01
5.00
12.00
5.00
0.990
–50
–25
75
0
25
50
TEMPERATURE (°C)
100
11.99
4.99
–50
125
–25
25
50
75
0
TEMPERATURE (°C)
3886 G19
MEASUREMENT ERROR (mA)
0.2
0
–0.2
–0.4
–0.6
5
6
4
4
2
0
–2
–4
–6
–0.8
–1.0
–50
–25
25
0
75
50
TEMPERATURE (°C)
100
125
–8
100
125
IIN Error vs IIN
8
MEASUREMENT ERROR (mA)
0.8
0.4
25
50
75
0
TEMPERATURE (°C)
3886 G21
IOUT Error vs IOUT
1.0
0.6
–25
3886 G20
External Temperature Error
vs Temperature
MEASUREMENT ERROR (°C)
11.98
–50
125
100
3
2
1
0
–1
–2
0
10
5
15
OUTPUT CURRENT (A)
20
–3
0
1
2
3886 G23
3886 G22
3886 G24
Dynamic Current Sharing During a
Load Transient in a 4-Phase System
DC Output Current Matching in a
2-Phase System (LTC3886)
3
INPUT CURRENT (A)
Dynamic Current Sharing During a
Load Transient in a 4-Phase System
25
CHANNEL CURRENT (A)
20
15
CURRENT
5A/DIV
CURRENT
5A/DIV
10
5
0
CHAN 0
CHAN 1
0
5
25 30
10 15 20
TOTAL CURRENT (A)
35
40
3886 G25
12
VIN = 48V
10µs/DIV
VOUT = 5V
fSW = 150kHz
L = 6.8µH; RSENSE = 3mΩ
0A TO 10A LOAD STEP
3886 G26
VIN = 48V
10µs/DIV
VOUT = 5V
f SW = 150kHz
L = 6.8µH; RSENSE = 3mΩ
10A TO 0A LOAD STEP
3886 G27
Rev G
For more information www.analog.com
LTC3886/LTC3886-1
PIN FUNCTIONS
SW0/SW1 (Pins 1, 39): Switch Node Connections to
Inductors. Voltage swings at the pins are from a Schottky
diode (external) voltage drop below ground to VIN.
TG0/TG1 (Pins 2, 38): Top Gate Driver Outputs. These are
the outputs of floating drivers with a voltage swing equal
to INTVCC superimposed on the switch node voltages.
ISENSE0+/ISENSE1+ (Pins 4, 9): Current Sense Comparator
Inputs. The (+) input to the current comparator is normally connected to the DCR sensing network or current
sensing resistor.
ISENSE0–/ISENSE1– (Pins 5, 10): Current Sense Comparator
Inputs. The (–) input is connected to the output.
TSNS0/TSNS1 (Pins 6, 36): External Diode Temperature
Sense. Connect to the anode of a diode-connected PNP
transistor in order to sense remote temperature. Directly
connect the cathode using a separate ground return path
to Pin 53 of the LTC3886. A bypass capacitor between
the anode and cathode must be located in close proximity
to the transistor. If external temperature sense elements
are not installed, short pin to ground and set the UT_
FAULT_LIMIT to –275°C and the UT_FAULT_RESPONSE
to ignore.
VSENSE0+/VSENSE1+ (Pins 7, 35): Positive Output Voltage
Sense Inputs.
VSENSE0– (Pin 8): Channel 0 Negative Output Voltage
Sense Input.
ITHR0/ITHR1 (Pins 11, 32): Loop Compensation Nodes.
ITH0/ITH1 (Pins 12, 31): Current Control Threshold and
Error Amplifier Compensation Nodes. Each associated
channel’s current comparator tripping threshold increases
with its ITH voltage.
SYNC (Pin 13): External Clock Synchronization Input and
Open-Drain Output Pin. If an external clock is present
at this pin, the switching frequency will be synchronized
to the external clock. If clock master mode is enabled,
this pin will pull low at the switching frequency with a
500ns pulse width to ground. A resistor pull-up to 3.3V
is required in the application.
SCL (Pin 14): Serial Bus Clock Input. Open-drain output,
can hold the output low if clock stretching is enabled.
A pull-up resistor to a voltage between 1.8V to 3.3V is
required in the application.
SDA (Pin 15): Serial Bus Data Input and Output. A pull-up
resistor to a voltage between 1.8V to 3.3V is required in
the application.
ALERT (Pin 16): Open-Drain Digital Output. Connect the
SMBALERT signal to this pin. A pull-up resistor to 3.3V
is required in the application.
FAULT0/FAULT1 (Pins 17, 18): Digital Programmable
General Purpose Inputs and Outputs. Open-drain output.
A pull-up resistor to a voltage between 1.8V to 3.3V is
required in the application.
RUN0/RUN1 (Pins 19, 20): Enable Run Input and Output.
Logic high on this pin enables the controller. Open-drain
output holds the pin low until the LTC3886 is out of reset.
This pin should be driven by an open-drain digital output.
A pull-up resistor to a voltage between 1.8V to 3.3V is
required in the application.
ASEL0/ASEL1 (Pin 21/Pin 22): Serial Bus Address Select
Inputs. Connect optional 1% resistor dividers between
VDD25 and GND to these pins to select the serial bus
interface address. Refer to the Applications Information
section for more detail. Minimize capacitance when the
pin is open to assure accurate detection of the pin state.
VOUT_CFG0 /VOUT_CFG1 (Pins 23, 24): Output Voltage
Select Pins. Connect a ±1% resistor divider between the
chip VDD25, VOUT_CFG and GND in order to select output
voltage. If the pin is left open, the IC will use the value
programmed in the EEPROM. Refer to the Applications
Information section for more detail. Minimize capacitance
when the pin is open to assure accurate detection of the
pin state.
FREQ_CFG (Pin 25): Frequency Select Pin. Connect a
±1% resistor divider between the chip VDD25 FREQ_CFG
and GND in order to select switching frequency. If the pin
is left open, the IC will use the value programmed in the
EEPROM. Refer to the Applications Information section
for more detail. Minimize capacitance when the pin is
open to assure accurate detection of the pin state.
Rev G
For more information www.analog.com
13
LTC3886/LTC3886-1
PIN FUNCTIONS
PHAS_CFG (Pin 26): Phase Configuration Input. Connect
an optional 1% resistor divider between VDD25 and GND
to this pin to configure the phase of each PWM channel
relative to SYNC. Refer to the Applications Information
section for more detail. Minimize capacitance when the
pin is open to assure accurate detection of the pin state.
VDD25 (Pin 27): Internally Generated 2.5V Power Supply
Output. Bypass this pin to GND with a low ESR 1μF capacitor. Do not load this pin externally except for the resistor
dividers needed for the LTC3886 resistor con-figuration
pins.
WP (Pin 28): Write Protect Pin Active High. An internal
10µA current source pulls the pin to VDD33. If WP is high,
the PMBus writes are restricted.
SHARE_CLK (Pin 29): Share Clock, Bidirectional OpenDrain Clock Sharing Pin. Nominally 100kHz. Used to synchronize the timing between multiple ADI controllers. Tie
all the SHARE_CLK pins together. All ADI controllers will
synchronize to the fastest clock. A pull-up resistor to 3.3V
is required in the application.
VDD33 (Pin 30): Internally Generated 3.3V Power Supply
Output. Bypass this pin to GND with a low ESR 1μF capacitor. Do not load this pin with external current.
PGOOD0/PGOOD1 (Pins 34, 33): Power Good Indicator
Outputs. Open-drain logic output that is pulled to ground
when the output exceeds OV/UV thresholds. The output
is deglitched by an internal 60μs filter. A pull-up resistor
to 3.3V is required in the application.
BOOST1/BOOST0 (Pins 40, 52): Boosted Floating Driver
Supplies. The (+) terminal of the bootstrap capacitor connects to this pin. This pin swings from a diode voltage
drop below INTVCC up to VIN + INTVCC.
14
BG0/BG1 (Pins 50, 42): Bottom Gate Driver Outputs. This
pin drives the gates of the bottom N-channel MOSFET
between GND and INTVCC.
EXTVCC (Pin 43): External power input to an internal LDO
connected to INTVCC. This LDO supplies INTVCC power
bypassing the internal LDO powered from VIN whenever
EXTVCC is higher than 4.7V. See EXTVCC connection in the
Applications Information Section. Do not float or exceed
14V on this pin. Decouple this pin to GND with a minimum
of 4.7μF low ESR tantalum or ceramic capacitor. If the
EXTVCC pin is not used, tie the pin to GND. The EXTVCC
pin may be connected to a higher voltage than the VIN
pin. If the EXTVCC pin is tied to an output of the controller and the external load can pull the output below –0.3V,
a Schottky diode from GND to EXTVCC must be used to
protect the EXTVCC pin.
INTVCC (Pin 44): Internal Regulator 5V Output. The control circuits are powered from this voltage. Decouple this
pin to GND with a minimum of 4.7μF low ESR tantalum
or ceramic capacitor.
IIN– (Pin 46): Negative Input of High Side Current Sense
Amplifier.
IIN+ (Pin 47): Positive Input of High Side Current Sense
Amplifier.
VIN (Pin 48): Main Input Supply. Decouple this pin to GND
with a capacitor (0.1µF to 1µF). For applications where
the main input power is 5V, tie the VIN and INTVCC pins
together. If the input current sense amplifier is not used,
this pin must be shorted to the IIN+ and IIN– pins.
GND (Exposed Pad Pin 53): Ground. All small-signal
and compensation components should connect to this
ground, at one point.
Rev G
For more information www.analog.com
LTC3886/LTC3886-1
BLOCK DIAGRAM
RIINSNS
IIN+
RVIN
VIN
34
+
PGOOD0
VIN
IIN–
47
46
EXTVCC
48
43
5V REG
–
+
OV
PGOOD
EXTVCC
CVCC
CIN
INTVCC
xR
R
VDD33
3.3V
SUBREG
ICMP
yR
R
DB
52
– IREV
+
3k
+
–
VDD33
30
BOOST0
S
R Q
PWM_CLOCK
INTVCC
44
UV
TG0
2
FCNT
SWITCH
LOGIC
AND
ANTISHOOTTHROUGH
UV
UVLO
SS
ILIM RANGE SELECT
HI: 1:1
LO: 1:1.5
M1
SW0
1
ON
REV
CB
ISENSE+
4
ISENSE–
+
5
RUN
BG0
OV
VOUT
COUT
M2
50
CVCC
SLOPE
COMPENSATION
INTVCC
UVLO
GM
ACTIVE
CLAMP
16-BIT
ADC
ILIM DAC
(3 BITS)
+
–
ITH0
12
CC1
ITHR0
2µA
11
EA
CC2
+ –
30µA
RTH
4R
R
–
AO
+
R
4R
PWM0
PWM1
+ –
8
VSENSE–
VSENSE+
7
TSNS0
OV
UV
+ –
GND
+
–
–
+
+
–
+
8:1 –
+
MUX –
+
–
+
–
+
–
6
TMUX
+ –
4R
53
GND
R
GND
9-BIT
VIN_ON
THRESHOLD DAC
12-BIT
SET POINT
DAC
9-BIT
OV
DAC
9-BIT
UV
DAC
M2
VCO
PHASE SELECTOR
VSTBY
SHARE_CLK 29
WP 28
SCL 14
SDA 15
PMBus
INTERFACE
(400kHz
COMPATIBLE)
1.22V
VDD33
GND
PWM
CLOCK
VDD33
VDD25
CLOCK DIVIDER
VDD33
COMPARE
REF
13 SYNC
PHASE DET
2.5V
SUBREG
SLAVE
MISO
27 VDD25
GND
MAIN
CONTROL
ALERT 16
CLK MOSI
MASTER
SINC3
UVLO
OSC
(32MHz)
26 PHAS_CFG
25 FREQ_CFG
RUN0 19
FAULT0 17
CHANNEL
TIMING
MANAGEMENT
CONFIG
DETECT
SYNC
PROGRAM
ROM
RAM
EEPROM
23 VOUT0_CFG
21 ASEL0
22 ASEL1
3886 F01
Figure 1. Block Diagram, One of Two Channels (CH0) Shown
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Rev G
15
LTC3886/LTC3886-1
OPERATION
OVERVIEW
The LTC3886 is a dual channel/dual phase, constant frequency, analog current mode controller for DC/DC stepdown applications with a digital interface. The LTC3886
digital interface is compatible with PMBus which supports
bus speeds of up to 400kHz. A typical application circuit
is shown on the first page of this data sheet.
In addition all the LTC3886 features, the LTC3886-1 also
includes a sequencing off feature to fully discharge very
large output capacitors as fast as safely possible.
Major features include:
Programmable Output Voltage
n
Programmable Input Voltage Comparator
n
Programmable Current Limit
n
Programmable Switching Frequency
n
Programmable OV and UV Comparators
n
Programmable On and Off Delay Times
n
Programmable Output Rise/Fall Times
n
Programmable Loop Compensation
n
Dedicated Power Good Pin for Each Channel
n
n
n
Internal Die Temperature
External System Temperature via Optional Diode
Sense Elements
n
Average Output Current
n
Average Output Voltage
n
Average Input Voltage
n
Average Input Current
n
n
n
The PMBus interface provides access to important power
management data during system operation including:
Configurable, Latched and Unlatched Individual Fault
and Warning Status
Individual channels are accessed through the PMBus
using the PAGE command, i.e., PAGE 0 or 1.
Fault reporting and shutdown behavior are fully configurable using the FAULTn outputs. A dedicated pin for
ALERT is provided. The shutdown operation also allows
all faults to be individually masked and can be operated
in either unlatched (retry) or latched modes.
Phase-Locked Loop for Synchronous, PolyPhase
Operation (2, 3, 4 or 6 Phases)
Input and Output Voltage/Current, and Temperature
Telemetry
Individual status commands enable fault reporting over
the serial bus to identify the specific fault event. Fault or
warning detection includes the following:
n
Output Undervoltage/Overvoltage
n
Input Undervoltage/Overvoltage
n
Input and Output Overcurrent
Fully Differential Remote Sense on Channel 0
n
n
Internal Overtemperature
Integrated Gate Drivers
n
n
External Overtemperature
Nonvolatile Configuration Memory with ECC
n
n
Communication, Memory or Logic (CML) Fault
n
n
Optional External Configuration Resistors for Key
Operating Parameters
Optional Time-Base Interconnect for Synchronization
Between Multiple Controllers
n
Fault Logging
n
WP Pin to Protect Internal EEPROM Configuration
n
Standalone Operation After User Factory Configuration
n
PMBus Version 1.2, 400kHz Compliant Interface
16
MAIN CONTROL LOOP
The LTC3886 is a constant-frequency, current-mode
step-down controller that operates at a user-defined
relative phasing. During normal operation the top
MOSFET is turned on when the clock for that channel
sets the RS latch, and turned off when the main current comparator, ICMP , resets the RS latch. The peak
inductor current at which ICMP resets the RS latch is
controlled by the voltage on the ITH pin which is the
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Rev G
LTC3886/LTC3886-1
OPERATION
output of the error amplifier, EA. The EA negative terminal is equal to the VSENSE voltage divided by 16
(8 if range = 1). The positive terminal of the EA is
connected to the output of a 12-bit DAC with values
ranging from 0V to 1.024V. The output voltage, through
feedback of the EA, will be regulated to 16 times the
DAC output (8 times if range = 1). The DAC value is
calculated by the part to synthesize the users desired
output voltage. The output voltage is programmed by the
user either with the resistor configuration pins detailed in
Table 3 or by the VOUT command (either from EEPROM,
or by PMBus command). Refer to the PMBus command
section of the data sheet or the PMBus specification for
more details. The output voltage can be modified by the
user at any time with a PMBus VOUT_COMMAND. This
command will typically have a latency less than 10ms.
The user is encouraged to reference the PMBus Power
System Management Protocol Specification to understand how to program the LTC3886.
Continuing the basic operation description, the current
mode controller will turn off the top gate when the peak
current is reached. If the load current increases, VSENSE
will slightly droop with respect to the DAC reference. This
causes the ITH voltage to increase until the average inductor current matches the new load current. After the top
MOSFET has turned off, the bottom MOSFET is turned
on. In continuous conduction mode, the bottom MOSFET
stays on until the end of the switching cycle.
EEPROM
The LTC3886 contains internal EEPROM, also referred to
as NVM (nonvolatile memory), with error correction coding (ECC) to store user configuration settings and fault log
information. EEPROM endurance and retention for user
space and fault log pages are specified in the Absolute
Maximum Ratings and Electrical Characteristics table. The
LTC3886 EEPROM also contains a manufacturing section
that has internal redundancy.
The integrity of the entire onboard EEPROM is checked with
a CRC calculation each time its data is to be read, such as
after a power-on reset or execution of a RESTORE_USER_
ALL command. If a CRC error occurs, the CML bit is set in
the STATUS_BYTE and STATUS_WORD commands, the
EEPROM CRC Error bit in the STATUS_MFR_SPECIFIC
command is set, and the ALERT and RUN pins pulled low
(PWM channels off). At that point the device will respond
at special address 0x7C, which is activated only after an
invalid CRC has been detected. The chip will also respond
at the global addresses 0x5A and 0x5B, but use of these
addresses when attempting to recover from a CRC issue
is not recommended. All power supply rails associated
with either PWM channel of a device reporting an invalid
CRC should remain disabled until the issue is resolved.
ADI recommends that the EEPROM not be written when
die temperature is greater than 85°C. If internal die temperature exceeds 130°C, all EEPROM operations except
RESTORE_USER_ALL and MFR_RESET are disabled. Full
EEPROM operation is not re-enabled until die temperature
falls below 125°C. Refer to the Applications Information
section for equations to predict retention degradation due
to elevated operating temperatures.
See the Applications Information section or contact the
factory for details on efficient in-system EEPROM programming, including bulk EEPROM programming, which
the LTC3886 also supports.
POWER-UP AND INITIALIZATION
The LTC3886 is designed to provide standalone supply
sequencing and controlled turn-on and turn-off operation. It can operate from a single VIN input supply (4.5V
to 60V) while three on-chip linear regulators generate
internal 2.5V, 3.3V and 5V. If VIN does not exceed 6V,
and the EXTVCC pin is not driven by an external supply, the INTVCC and VIN pins must be tied together. The
LTC3886 EXTVCC pin can driven by an external supply to
improve efficiency of the circuit and minimize power on
the LTC3886. The EXTVCC pin must exceed approximately
4.8V before the INTVCC voltage LDO operates from the
EXTVCC pin. To minimize application power, the EXTVCC
pin can be supplied by a switching regulator, or an output
of the LTC3886. The EXTVCC pin voltage may exceed the
VIN pin voltage. The controller configuration is initialized
by an internal threshold based UVLO where VIN must be
approximately 4.2V and the 5V, 3.3V and 2.5V linear regulators must be within approximately 20% of the regulated
Rev G
For more information www.analog.com
17
LTC3886/LTC3886-1
OPERATION
values. A PMBus RESTORE_USER_ALL or MFR_RESET
command forces this same initialization.
During initialization, the external configuration resistors
are identified and/or contents of the EEPROM are read
into the controller’s commands. The BGn, TGn, PGOODn
and RUNn pins are held low. The FAULTn pins are in high
impedance mode. The LTC3886 will use the contents of
Tables 3 to 6 to determine the resistor defined parameters.
See the Resistor Configuration section for more detail. The
resistor configuration pins only control some of the preset
values of the controller. The remaining values are programmed in EEPROM either at the factory or by the user.
If the configuration resistors are not inserted or if the
ignore RCONFIG bit is asserted (bit 6 of the MFR_CONFIG_
ALL_LTC3886 configuration command), the LTC3886
will use only the contents of EEPROM to determine the
DC/DC characteristics. The ASEL0 and ASEL1 values read
at power-up or reset are always respected unless the pins
are open. See the Applications Information section for
more detail.
After the part has initialized, an additional comparator
monitors VIN. The VIN_ON threshold must be exceeded
before the output power sequencing can begin. After VIN
is initially applied, the part will typically require 70ms to
initialize and begin the TON_DELAY timer. The read back of
voltages and currents require an additional 0ms to 90ms.
SOFT-START
The part must enter the run state prior to soft-start. The
RUN pin is released by the LTC3886 after the part initializes and VIN is greater than the VIN_ON threshold. If
multiple LTC3886s are used in an application, they all hold
their respective run pins low until all devices initialize and
VIN exceeds the VIN_ON threshold for every device. The
SHARE_CLK pin assures all the devices connected to the
signal use the same time base. The SHARE_CLK pin is
held low until the part has initialized after VIN is applied
and VIN exceeds the VIN_ON threshold. The LTC3886 can
be set to turn off (or remain off) if SHARE_CLK is low
(set bit 2 of MFR_CHAN_CONFIG_LTC3886 to a 1). This
allows the user to assure synchronization across numerous ADI ICs even if the RUN pins can not be connected
18
together due to board constraints. In general, if the user
cares about synchronization between chips it is best to
connect all the respective RUN pins together and to connect all the respective SHARE_CLK pins together and pull
up to VDD33 with a 5.49k resistor. This assures all chips
begin sequencing at the same time and use the same
time base.
After the RUNn pin releases and prior to entering a constant output voltage regulation state, the LTC3886 performs a monotonic initial ramp or “soft-start”. Soft-start
is performed by actively regulating the load voltage while
digitally ramping the target voltage from 0V to the commanded voltage set-point. Once the LTC3886 is commanded to turn on, (after power up and initialization)
the controller waits for the user specified turn-on delay
(TON_DELAY) prior to initiating this output voltage ramp.
The rise time of the voltage ramp can be programmed
using the TON_RISE command to minimize inrush currents associated with the start-up voltage ramp. The softstart feature is disabled by setting the value of TON_RISE
to any value less than 0.25ms. The LTC3886 PWM always
uses discontinuous mode during the TON_RISE operation. In discontinuous mode, the bottom gate is turned
off as soon as reverse current is detected in the inductor.
This will allow the regulator to start up into a pre-biased
load. When the TON_MAX_FAULT_LIMIT is reached, the
part transitions to continuous mode, if so programmed.
If TON_MAX_FAULT_LIMIT is set to zero, there is no time
limit and the part transitions to the desired conduction
mode after TON_RISE completes and VOUT has exceeded
the VOUT_UV_FAULT_LIMIT and IOUT_OC is not present.
TIME-BASED SEQUENCING
The default mode for sequencing the output on and off
is time based. The output is enabled after waiting TON_
DELAY amount of time following either the RUNn pin
going high, a PMBus command to turn on, or the VIN
pin voltage rising above a preprogrammed voltage. Off
sequencing is handled in a similar way. To assure proper
sequencing, make sure all ICs connect the SHARE_CLK
pins together and RUN pins together. If the RUN pins
can not be connected together for some reason, set
bit 2 of MFR_CHAN_CONFIG_LTC3886 to a 1. This bit
Rev G
For more information www.analog.com
LTC3886/LTC3886-1
OPERATION
requires the SHARE_CLK pin to be clocking before the
power supply output can start. When the RUNn pin is
pulled low, the LTC3886 will hold the pin low for the
MFR_RESTART_DELAY. The minimum MFR_RESTART_
DELAY is TOFF_DELAY + TOFF_FALL + 136ms. This delay
assures proper sequencing of all rails. The LTC3886 calculates this delay internally and will not process a shorter
delay. However, a longer commanded MFR_RESTART_
DELAY will be used by the part. The maximum allowed
value is 65.52 seconds.
EVENT-BASED SEQUENCING
The PGOODn pin is be asserted when the output UV
threshold is exceeded. It is possible to feed the PGOODn
pin from one LTC3886 into the RUN pin of the next
LTC3886 in the sequence. This can be implemented
across multiple LTC3886s. If a fault in the string of rails
is detected, only the faulted rail and downstream rails will
fault off. The rails in the string of devices in front of the
faulted rail will remain on unless commanded off.
Event-Based Sequencing by Cascading PGOODs Into RUN Pins
START
RUN 0
PG0OD0
LTC3886
RUN 1
PGOOD1
RUN 0
PGOOD0
LTC3886
RUN 1
PGOOD1
3886 F02
TO NEXT CHANNEL
IN THE SEQUENCE
Figure 2. Event (Voltage) Based Sequencing
SHUTDOWN
The LTC3886 supports three shutdown modes. The
first mode is continuous conduction mode, with userdefined turn-off delay (TOFF_DELAY) and ramp down rate
(TOFF_FALL). The controller will draw current from the
load to force TOFF_FALL. The second mode is discontinuous conduction mode. In discontinuous conduction
mode the controller will not draw current from the load
and the fall time will be set by the output capacitance and
load current.
The third shutdown mode occurs in response to a fault
condition or loss of SHARE_CLK (if bit 2 of MFR_CHAN_
CONFIG_LTC3886 is set to a 1) or VIN falling below the
VIN_OFF threshold or FAULTn pulled low externally (if the
MFR_FAULT_RESPONSE is set to inhibit). Under these
conditions the power stage is disabled in order to stop
the transfer of energy to the load as quickly as possible.
The shutdown state can be entered from the soft-start or
active regulation states either through user intervention
(de-asserting RUN or the PMBus OPERATION command)
or in response to a detected fault or an external fault via
the bidirectional FAULTn pin, or loss of SHARE_CLK (if
bit 2 of MFR_CHAN_CONFIG_LTC3886 is set to a 1) or
VIN falling below the VIN_OFF threshold.
The LTC3886-1 shutdown mode allows very large output
capacitors to be fully discharged as fast as safely possible in continuous conduction mode. The PWM channel output will remain active until the output voltage is
verified by the internal ADC to be below the MFR_VOFF_
THRESHOLD value. The PWM channel will shut down
between 90ms and 300ms after the output voltage is
below the MFR_VOFF_THRESHOLD.
In retry mode, the controller responds to a fault by shutting down and entering the inactive state for a programmable delay time (MFR_RETRY_DELAY). This delay minimizes the duty cycle associated with autonomous retries
if the fault that caused the shutdown disappears once the
output is disabled. The retry delay time of the LTC3886
is determined by the longer of the MFR_RETRY_DELAY
command or the time required for the regulated output to decay below 12.5% of the programmed value.
The retry delay time of the LTC3886-1 when the MFR_
CHAN_CONFIG bit #0 set to 0 is determined by the longer of the MFR_RETRY_DELAY command or the time
required for the regulated output to decay below the
MFR_VOFF_THRESHOLD value. If the time from when
the channel is faulted off until channel’s output voltage
is below MFR_VOFF_THRESHOLD exceeds TOFF_MAX_
WARN_LIMIT, then a TOFF_MAX warning status will be
generated. The retry delay time of the LTC3886-1 when
Rev G
For more information www.analog.com
19
LTC3886/LTC3886-1
OPERATION
the MFR_CHAN_CONFIG bit #0 set to 1 is determined
by the MFR_RETRY_DELAY command. If the channel’s
output voltage is above MFR_VOFF_THRESHOLD, the
channel will proceed to sequence on into what could be
a pre-biased load. TOFF_MAX Warning status will not
be generated. If multiple outputs are controlled by the
same FAULTn pin, the decay time of the faulted output
determines the retry delay. If the natural decay time of
the output is too long, it is possible to remove the voltage requirement of the MFR_RETRY_DELAY command
by asserting bit 0 of MFR_CHAN_CONFIG_LTC3886.
Alternatively, the controller can be configured so that
it remains latched-off following a fault and clearing
requires user intervention such as toggling RUN or commanding the part OFF then ON.
LIGHT-LOAD CURRENT OPERATION
The LTC3886 has two PWM modes of operation, discontinuous conduction mode or forced continuous conduction mode. Mode selection is done using the MFR_PWM_
MODE_LTC3886 command (discontinuous conduction is
always the start-up mode, forced continuous is the default
running mode).
If a controller is enabled for discontinuous conduction operation, the inductor current is not allowed to reverse. The
reverse current comparator, IREV , turns off the bottom gate
external MOSFET just before the inductor current reaches
zero, preventing it from reversing and going negative.
Thus, the controller can operate in discontinuous operation. In forced continuous operation, the inductor current
is allowed to reverse at light loads or under large transient
conditions. The peak inductor current is determined solely
by the voltage on the ITH pin. In this mode, the efficiency
at light loads is lower than in discontinuous conduction
operation. However, continuous mode exhibits lower output ripple and less interference with audio circuitry. Forced
continuous conduction mode may result in reverse inductor current, which can cause the input supply to boost.
The VIN_OV_FAULT_LIMIT can detect this and turn off
the offending channel. However, this fault is based on an
ADC read and can take up to 90ms to detect. If there is a
concern about the input supply boosting, keep the part in
discontinuous conduction.
20
PWM LOOP COMPENSATION
The internal PWM loop compensation resistors RITHn of
the LTC3886 can be adjusted using bit[4:0] of the MFR_
PWM_COMP command.
The transconductance of the LTC3886 PWM error amplifier can be adjusted using bit[7:5] of the MFR_PWM_COMP
command.
Refer to the Programmable Loop Compensation subsection
in the Applications Information section for further details.
SWITCHING FREQUENCY AND PHASE
The switching frequency of the PWM can be established
with an internal oscillator or an external time base. The
internal phase-locked loop (PLL) synchronizes PWM control to this timing reference with proper phase relation,
whether the clock is provided internally or externally. The
device can also be configured to provide the master clock
to other ICs through PMBus command, EEPROM setting,
or external configuration resistors as outlined in Tables
4 and 5.
As clock master, the LTC3886 will drive its open-drain
SYNC pin at the selected rate with a pulse width of 500ns.
An external pull-up resistor between SYNC and VDD33
is required in this case. Only one device connected to
SYNC should be designated to drive the pin. If multiple
LTC3886s programmed as clock masters are wired to the
same SYNC line with a pull-up resistor, just one of the
devices is automatically elected to provide clocking, and
the others disable their SYNC outputs.
The LTC3886 will automatically accept an external
SYNC input, disabling its own SYNC drive if necessary.
Whether configured to drive SYNC or not, the LTC3886
can continue PWM operation using its own internal
oscillator if an external clock signal is subsequently lost.
The device can also be programmed to always require
an external oscillator for PWM operation by setting bit 4
of MFR_CONFIG_ALL_LTC3886. The status of the SYNC
driver circuit is indicated by bit 10 of MFR_PADS.
The MFR_PWM_CONFIG_LTC3886 command can be
used to configure the phase of each channel. Desired phase
can also be set from EEPROM or external configuration
Rev G
For more information www.analog.com
LTC3886/LTC3886-1
OPERATION
resistors as outlined in Table 5. Designated phase is
the relationship between the falling edge of SYNC and
the internal clock edge that sets the PWM latch to turn
on the top power switch. Additional small propagation
delays to the PWM control pins will also apply. Both
channels must be off before the FREQUENCY_SWITCH
and MFR_PWM_CONFIG_LTC3886 commands can be
written to the LTC3886.
The phase relationships and frequency are independent
of each other, providing numerous application options.
Multiple LTC3886 ICs can be synchronized to realize
a PolyPhase array. In this case the phases should be
separated by 360/n degrees, where n is the number of
phases driving the output voltage rail.
OUTPUT VOLTAGE SENSING
The channel 0 differential amplifier allows remote, differential sensing of the load voltage with VSENSE0n pins.
The channel 1 sense pin (VSENSE1) is referenced to GND.
The (telemetry) ADC is fully differential and makes measurements of channels 0 and 1 output voltages at the
VSENSE0n and VSENSE1/GND pins, respectively. The maximum allowed differential sense voltage for VSENSE0+ to
VSENSE0– is 14V.
OUTPUT CURRENT SENSING
For DCR current sense applications, a resistor in series
with a capacitor is placed across the inductor. In this
configuration, the resistor is tied to the FET side of the
inductor while the capacitor is tied to the load side of
the inductor as shown in Figure 3. If the RC values are
chosen such that the RC time constant matches the inductor time constant (L/DCR, where DCR is the inductor
series resistance), the resultant voltage (VDCR) appearing across the capacitor will equal the voltage across the
inductor series resistance and thus represent the current flowing through the inductor. The RC calculations
are based on the room temperature DCR of the inductor.
The RC time constant should remain constant, as a function of temperature. This assures the transient response of
the circuit is the same regardless of the temperature. The
DCR of the inductor has a large temperature coefficient,
approximately 3900ppm/°C. The temperature coefficient
of the inductor must be written to the MFR_IOUT_CAL_
GAIN_TC command. The external temperature is sensed
near the inductor and is used to modify the internal current limit circuit to maintain an essentially constant current limit with temperature. In this application, the ISENSE+
pin is connected to the FET side of the capacitor while
the ISENSE– pin is placed on the load side of the capacitor.
The current sensed from the input is then given by the
expression VDCR/DCR. VDCR is digitized by the LTC3886’s
telemetry ADC with an input range of ±100mV, a noise
floor of 7µVRMS, and a peak-peak noise of approximately
46.5µV. The LTC3886 computes the inductor current
using the DCR value stored in the IOUT_CAL_GAIN command and the temperature coefficient stored in command
MFR_IOUT_CAL_GAIN_TC. The resulting current value is
returned by the READ_IOUT command.
INPUT CURRENT SENSING
To sense the total input current consumed by the LTC3886
and the power stage, a resistor is placed between the supply voltage and the drain of the top N-channel MOSFET.
The IIN+ and IIN– pins are connected to the sense resistor.
The filtered voltage is amplified by the internal high side
current sense amplifier and digitized by the LTC3886’s
telemetry ADC. The input current sense amplifier has
three gain settings of 2x, 4x, and 8x set by the bit[6:5] of
the MFR_PWM_CONFIG_3886 command. The maximum
differential input sense voltage for the three gain settings
is 50mV, 20mV, and 5mV respectively. The LTC3886
computes the input current using the R value stored in the
IIN_CAL_GAIN command. The resulting measured power
stage current is returned by the READ_IIN command.
The LTC3886 uses the RVIN resistor to measure the VIN
pin supply current being consumed by the LTC3886. This
value is returned by the MFR_READ_ICHIP command.
The chip current is calculated by using the R value stored
in the MFR_RVIN command. Refer to the subsection
titled Input Current Sense Amplifier in the Applications
Information section for further detail.
Rev G
For more information www.analog.com
21
LTC3886/LTC3886-1
OPERATION
10k
10k
4.99k
10k
10k
LTC3886 + POWER STAGE
ITHR0
ITH0
ITH1
ISENSE0+
ISENSE0–
FAULT0
VSENSE0+
RUN0
RUN1
VSENSE0–
ALERT
FAULT1
SYNC (ENABLED)
ISENSE1+
SHARE_CLK
VDD33
ISENSE1–
PGOOD0
VSENSE1
PGOOD1
GND
10k
RUN
ALERT
FAULT
SYNC
SHARE_CLK
PGOOD
1µF
1/2 LTC3886 + POWER STAGE
ITH0
VDD33
1µF
NOTE: SOME CONNECTORS
AND COMPONENTS OMITTED
FOR CLARITY
ISENSE0+
RUN0
ALERT
ISENSE0–
FAULT0
VSENSE0+
SYNC (DISABLED)
VSENSE0–
SHARE_CLK
PGOOD0
GND
LOAD
3886 F03
Figure 3. Load Sharing Connections for 3-Phase Operation
PolyPhase LOAD SHARING
Multiple LTC3886’s can be connected in parallel in order
to provide a balanced load-share solution by connecting
the necessary pins. Figure 3 illustrates the shared connections required for load sharing.
The SYNC pin should only be enabled on one of the
LTC3886s. The other(s) should be programmed to disable SYNC with the oscillator frequency set to the nominal value. When bit[7] of the MFR_PWM_CONFIG command is set, Channel 1 will use the feedback node of
Channel 0 as its point of regulation. Do not assert bit[7] of
MFR_PWM_CONFIG except in a PolyPhase application
when both VOUT pins are connected together and both
ITH pins are tied together.
EXTERNAL/INTERNAL TEMPERATURE SENSE
External temperature can best be measured using a
remote, diode-connected PNP transistor such as the
MMBT3906. The emitter should be connected to a TSNS
pin while the base and collector terminals of the PNP
transistor must be connected and returned directly to the
22
Pin 53 of the LTC3886 GND using a Kelvin connection.
The bypass capacitor between the emitter and collector
must be located near the transistor. Two different currents
are applied to the diode (nominally 2μA and 32μA) and
the temperature is calculated from a ΔVBE measurement
made with the internal 16-bit monitor ADC.
The LTC3886 also supports direct VBE based external temperature measurements. In this case the diode or diode
network is trimmed to a specific voltage at a specific current and temperature. In general this method does not
yield as accurate of a result as the single PNP transistor,
but may function better in noisy applications. Refer to
MFR_PWM_MODE_LTC3886 in the PMBus Command
Details section for additional information on programming
the LTC3886 for these two external temperature sense
configurations.
The calculated temperature is returned by the PMBus
READ_TEMPERATURE_1 command. Refer to the
Applications Information section for details on proper
layout of external temperature sense elements and PMBus
commands that can be used to improve the accuracy of
calculated temperatures.
Rev G
For more information www.analog.com
LTC3886/LTC3886-1
OPERATION
The READ_TEMPERATURE_2 command returns the internal junction temperature of the LTC3886 using an on-chip
diode with a ΔVBE measurement and calculation.
RCONFIG (RESISTOR CONFIGURATION) PINS
There are six input pins utilizing 1% resistor dividers
between VDD25 and GND to select key operating parameters. The pins are ASEL0, ASEL1, FREQ_CFG, VOUT0_
CFG, VOUT1_CFG, PHAS_CFG. If pins are floated, the value
stored in the corresponding EEPROM command is used.
If bit 6 of the MFR_CONFIG_ALL_LTC3886 configuration
command is asserted in EEPROM, the resistor inputs are
ignored upon power-up except for ASEL0 and ASEL1
which are always respected. The resistor configuration
pins are only measured during power-up and an execution
of a RESTORE_USER_ALL or MFR_RESET command.
The VOUTn_CFG pin settings are described in Table 3. These
pins select the output voltages for the LTC3886’s analog
PWM controllers. If the pin is open, the VOUT_COMMAND
command is loaded from EEPROM to determine the output voltage. The default setting is to have the switcher off
unless the voltage configuration pins are installed.
The following parameters are set as a percentage of the
output voltage if the RCONFIG pins are used to determined output voltage:
VOUT_OV_FAULT_LIMIT................................ +10%
n VOUT_OV_WARN_LIMIT............................... +7.5%
n VOUT_MAX.................................................... +7.5%
n VOUT_MARGIN_HIGH...................................... +5%
n VOUT_MARGIN_LOW....................................... –5%
n VOUT_UV_WARN_LIMIT............................... –6.5%
n VOUT_UV_FAULT_LIMIT.................................. –7%
The FREQ_CFG pin settings are described in Table 4. This
pin selects the switching frequency. The phase relationships between the two channels and SYNC pin is determined by the PHAS_CFG pin described in Table 5. To synchronize to an external clock, the part should be put into
external clock mode (SYNC output disabled but frequency
set to the nominal value). If no external clock is supplied,
the part will clock at the programmed frequency. If the
n
application is multi-phase and the SYNC signal between
chips is lost, the parts will not be at the same frequency
increasing the ripple voltage on the output, possibly producing undesirable operation. If the external SYNC signal
is being generated internally and external SYNC is not
selected, bit 10 of MFR_PADS will be asserted. If no frequency is selected and the external SYNC frequency is
not present, a PLL_FAULT will occur. If the user does not
wish to see the ALERT from a PLL_FAULT even if there is
not a valid synchronization signal at power-up, the ALERT
mask for PLL_FAULT must be written. See the description
on SMBALERT_MASK for more details. If the SYNC pin
is connected between multiple ICs only one of the ICs
should have the SYNC pin enabled, all other ICs should
be configured to SYNC pin disabled.
The ASEL0 and ASEL1 pin settings are described in
Table 6. ASEL1 selects the top 3 bits of the slave address
for the LTC3886. ASEL0 selects the bottom 4 bits of the
slave address for the LTC3886. If ASEL1 is floating, the
3 most significant bits are retrieved from the EEPROM
MFR_ADDRESS command. If ASEL0 is floating, the 4 LSB
bits stored in EEPROM MFR_ADDRESS command are
used to determine the 4 LSB bits of the slave address.
For more detail, refer to Table 6.
Note: Per the PMBus specification, pin programmed
parameters can be overridden by commands from the
digital interface with the exception of the ASELn pins
which are always honored. Do not set any part address
to 0x5A or 0x5B because these are global addresses and
all parts will respond to them.
FAULT HANDLING
A variety of fault and warning reporting and handling
mechanisms are available. Fault and warning detection
capabilities include:
n
Input OV/FAULT Protection and UV Warning
n
Average Input OC Warn
n
Output OV/UV Fault and Warn Protection
n
Output OC Fault and Warn Protection
Rev G
For more information www.analog.com
23
LTC3886/LTC3886-1
OPERATION
n
Internal and External Overtemperature Fault and
Warn Protection
n
External Undertemperature Fault and Warn Protection
n
CML Fault (Communication, Memory or Logic)
n
External Fault Detection via the Bidirectional FAULTn
Pins.
In addition, the LTC3886 can map any combination of fault
indicators to the FAULTn pin using the propagate FAULTn
response commands, MFR_FAULT_PROPAGATE_
LTC3886. Typical usage of the FAULTn pin is as a driver
for an external crowbar device, overtemperature alert,
overvoltage alert or as an interrupt to cause a microcontroller to poll the fault commands. Alternatively, the
FAULTn pin can be used as an input to detect external
faults downstream of the controller that require an immediate response.
As described in the Soft-Start section, it is possible to control start-up through concatenated events. If FAULTn is used
to drive the RUN pin of another controller, the unfiltered
VOUT_UV fault limit should be mapped to the FAULTn pin.
Any fault or warning event will cause the ALERT pin to
assert low unless the fault or warning is masked by the
SMBALERT_MASK. The pin will remain asserted low until
the CLEAR_FAULTS command is issued, the fault bit is
written to a 1, bias power is cycled or a MFR_RESET
command is issued, the RUN pin is toggled OFF/ON, or
the part is commanded OFF/ON via PMBus. The MFR_
FAULT_PROPAGATE_LTC3886 command determines if
the FAULTn pin is pulled low when a fault is detected.
Output and input fault event handling is controlled by the
corresponding fault response byte as specified in Tables 7
to 11. Shutdown recovery from these types of faults can
either be autonomous or latched. For autonomous recovery, the faults are not latched, so if the fault condition is
not present after the retry interval has elapsed, a new
soft-start is attempted. If the fault persists, the controller
will continue to retry. The retry interval is specified by the
MFR_RETRY_DELAY command and prevents damage to
the regulator components by repetitive power cycling,
assuming the fault condition itself is not immediately
destructive. The MFR_RETRY_DELAY must be greater
than 120ms. It can not exceed 83.88 seconds.
24
Status Registers and ALERT Masking
Figure 4 summarizes the internal LTC3886 status registers accessible by PMBus command. These contain indication of various faults, warnings and other important
operating conditions. As shown, the STATUS_BYTE and
STATUS_WORD commands also summarize contents of
other status registers. Refer to PMBus Command Details
for specific information.
NONE OF THE ABOVE in STATUS_BYTE indicates that
one or more of the bits in the most-significant nibble of
STATUS_WORD are also set.
In general, any asserted bit in a STATUS_x register also
pulls the ALERT pin low. Once set, ALERT will remain low
until one of the following occurs.
n
n
n
n
n
A CLEAR_FAULTS, RESTORE_USER_ALL or MFR_
RESET Command Is Issued
The Related Status Bit Is Written to a One
The Faulted Channel Is Properly Commanded Off and
Back On
The LTC3886 Successfully Transmits Its Address
During a PMBus ARA
Bias Power Is Cycled
With some exceptions, the SMBALERT_MASK command
can be used to prevent the LTC3886 from asserting ALERT
for bits in these registers on a bit-by-bit basis. These
mask settings apply to STATUS_WORD and STATUS_
BYTE in the same fashion as the status bits themselves.
For example, if ALERT is masked for all bits in Channel 0
STATUS_VOUT, then ALERT is effectively masked for the
VOUT bit in STATUS_WORD for PAGE 0.
The BUSY bit in STATUS_BYTE also asserts ALERT low
and cannot be masked. This bit can be set as a result of
various internal interactions with PMBus communication.
This fault occurs when a command is received that cannot
be safely executed with one or both channels enabled. As
discussed in Application Information, BUSY faults can
be avoided by polling MFR_COMMON before executing
some commands.
Rev G
For more information www.analog.com
LTC3886/LTC3886-1
OPERATION
STATUS_WORD
STATUS_VOUT
7
6
5
4
3
2
1
0
VOUT_OV Fault
VOUT_OV Warning
VOUT_UV Warning
VOUT_UV Fault
VOUT_MAX Warning
TON_MAX Fault
TOFF_MAX Warning
(reads 0)
15
14
13
12
11
10
9
8
VOUT
IOUT
INPUT
MFR_SPECIFIC
POWER_GOOD#
(reads 0)
(reads 0)
(reads 0)
7
6
5
4
3
2
1
0
BUSY
OFF
VOUT_OV
IOUT_OC
(reads 0)
TEMPERATURE
CML
NONE OF THE ABOVE
STATUS_BYTE
(PAGED)
STATUS_IOUT
7
6
5
4
3
2
1
0
IOUT_OC Fault
(reads 0)
IOUT_OC Warning
(reads 0)
(reads 0)
(reads 0)
(reads 0)
(reads 0)
MFR_COMMON
7
6
5
4
3
2
1
0
Chip Not Driving ALERT Low
Chip Not Busy
Internal Calculations Not Pending
Output Not In Transition
EEPROM Initialized
(reads 0)
SHARE_CLK_LOW
WP Pin High
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
EEPROM ECC Status
Reserved
Reserved
Reserved
Reserved
STATUS_TEMPERATURE
OT Fault
OT Warning
(reads 0)
UT Fault
(reads 0)
(reads 0)
(reads 0)
(reads 0)
STATUS_CML
7
6
5
4
3
2
1
0
Invalid/Unsupported Command
Invalid/Unsupported Data
Packet Error Check Failed
Memory Fault Detected
Processor Fault Detected
(reads 0)
Other Communication Fault
Other Memory or Logic Fault
DESCRIPTION
General Fault or Warning Event
General Non-Maskable Event
Dynamic
Status Derived from Other Bits
7
6
5
4
3
2
1
0
Internal Temperature Fault
Internal Temperature Warning
EEPROM CRC Error
Internal PLL Unlocked
Fault Log Present
VDD33 UV or OV Fault
VOUT Short Cycled
FAULT Pulled Low By External Device
(PAGED)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VDD33 OV Fault
VDD33 UV Fault
(reads 0)
(reads 0)
Invalid ADC Result(s)
SYNC Clocked by External Source
Channel 1 Power Good
Channel 0 Power Good
LTC3886 Forcing RUN1 Low
LTC3886 Forcing RUN0 Low
RUN1 Pin State
RUN0 Pin State
LTC3886 Forcing FAULT1 Low
LTC3886 Forcing FAULT0 Low
FAULT Pin State
FAULT Pin State
MFR_PADS
MFR_INFO
(PAGED)
VIN_OV Fault
(reads 0)
VIN_UV Warning
(reads 0)
Unit Off for Insuffcient VIN
(reads 0)
IIN_OC Warning
(reads 0)
STATUS_MFR_SPECIFIC
(PAGED)
(PAGED)
7
6
5
4
3
2
1
0
STATUS_INPUT
7
6
5
4
3
2
1
0
3886 F04
MASKABLE GENERATES ALERT BIT CLEARABLE
Yes
No
No
No
Yes
Yes
No
Not Directly
Yes
Yes
No
No
Figure 4. LTC3886 Status Register Summary
Rev G
For more information www.analog.com
25
LTC3886/LTC3886-1
OPERATION
If masked faults occur immediately after power up, ALERT
may still be pulled low because there has not been time
to retrieve all of the programmed masking information
from EEPROM.
Status information contained in MFR_COMMON and
MFR_PADS can be used to further debug or clarify the
contents of STATUS_BYTE or STATUS_WORD as shown,
but the contents of these registers do not affect the state
of the ALERT pin and may not directly influence bits in
STATUS_BYTE or STATUS_WORD.
Mapping Faults to FAULT Pins
The FAULTn pins of the LTC3886 can share faults between
channels and with all ADI PMBus products including the
LTC3880, LTC2974, LTC2978, LTC4676 µModule®, etc. In
the event of an internal fault, one or more of the LTC3886s
is configured to pull the bussed FAULTn pins low. The
other LTC3886s are then configured to shut down when
the FAULTn pin bus is pulled low. For autonomous group
retry, the faulted LTC3886 channel is configured to release
the FAULTn pin bus after a retry interval, assuming the
original fault has cleared. All the channels in the group
then begin a soft-start sequence. If the fault response is
LATCH_OFF, the FAULTn pin remains asserted low until
either the RUN pin is toggled OFF/ON or the part is commanded OFF/ON. The toggling of the RUN either by the
pin or OFF/ON command will clear faults associated with
the LTC3886. If it is desired to have all faults cleared when
either RUN pin is toggled, set bit 0 of MFR_CONFIG_ALL_
LTC3886 to a 1.
digital filter. The PGOODn pin and PGOOD status may be
different at times due to internal communication latency
of up to 10µs.
CRC Protection
The integrity of the EEPROM memory is checked after a
power-on reset. A CRC error will prevent the controller
from leaving the reset state. If a CRC error occurs, the
CML bit is set in the STATUS_BYTE and STATUS_WORD
commands, the appropriate bit is set in the STATUS_
MFR_SPECIFIC command, and the ALERT pin will be
pulled low. EEPROM repair can be attempted by writing
the desired configuration to the controller and executing
a STORE_USER_ALL command followed by a CLEAR_
FAULTS command.
The LTC3886 protects the integrity of the manufacturing
data and the user data by implementing ECC and CRC
checks in the EEPROM. If the ECC cannot correct the
contents of a single bit fault in the EEPROM, a CRC failure will occur. This assures that all double bit faults are
detected. If the CRC checks fail in either the manufacturing or user data sections of the EEPROM, the “EEPROM
CRC Fault” in the STATUS_MFR_SPECIFIC command is
set. If this bit remains set after being cleared by issuing a
CLEAR_FAULTS or writing a 1 to this bit, an irrecoverable
fault has occurred. There are no provisions for field repair
of the EEPROM for these types of faults.
SERIAL INTERFACE
Power Good Pins
The LTC3886 serial interface is a PMBus compliant slave
device and can operate at any frequency between 10kHz
and 400kHz. The address is configurable using either
the EEPROM or an external resistor divider. In addition
the LTC3886 always responds to the global broadcast
address of 0x5A (7) or 0x5B (7).
The PGOODn pins of the LTC3886 are connected to the
open drains of internal MOSFETs. The MOSFETs turn on
and pull the PGOODn pins low when the channel output voltage is not within the channels UV and OV voltage
thresholds. During TON_DELAY and TON_RISE sequencing, the PGn pin is held low. The PGOODn pin is also
pulled low when the respective RUNn pin is low. The
PGOODn pin response is deglitched by an internal 60µs
The serial interface supports the following protocols
defined in the PMBus specifications: 1) send command,
2) write byte, 3) write word, 4) group, 5) read byte, 6) read
word, 7) read block, 8) write block, 9) PAGE_PLUS_READ,
10) PAGE_PLUS_WRITE, 11) SMBALERT_MASK read
and 12) SMBALERT_MASK. All read operations will return
a valid PEC if the PMBus master requests it. If the PEC_
REQUIRED bit is set in the MFR_CONFIG_ALL_LTC3886
The status of all faults and warnings is summarized in the
STATUS_WORD and STATUS_BYTE commands.
Additional fault detection and handling capabilities are:
26
For more information www.analog.com
Rev G
LTC3886/LTC3886-1
OPERATION
command, the PMBus write operations will not be acted
upon until a valid PEC has been received by the LTC3886.
Communication Protection
PEC write errors (if PEC_REQUIRED is active), attempts
to access unsupported commands, or writing invalid data
to supported commands will result in a CML fault. The
CML bit is set in the STATUS_BYTE and STATUS_WORD
commands, the appropriate bit is set in the STATUS_CML
command, and the ALERT pin is pulled low.
All four means of PMBus addressing require the user to
employ disciplined planning to avoid addressing conflicts.
Communication to LTC3886 devices at global and rail
addresses should be limited to command write operations.
RESPONSES TO VOUT AND IOUT FAULTS/WARNINGS
VOUT OV and UV conditions are monitored by comparators. The OV and UV limits are set in three ways.
n
DEVICE ADDRESSING
n
The LTC3886 offers four different types of addressing over
the PMBus interface, specifically: 1) global, 2) device, 3)
rail addressing and 4) alert response address (ARA).
n
Global addressing provides a means of the PMBus master
to address all LTC3886 devices on the bus. The LTC3886
global address is fixed 0x5A (7) or 0xB4 (8) and cannot
be disabled. Commands sent to the global address act the
same as if PAGE is set to a value of 0xFF. Commands sent are
written to both channels simultaneously. Global command
0x5B (7) or 0xB6 (8) is paged and allows channel specific
command of all LTC3886 devices on the bus. Other ADI
device types may respond at one or both of these global
addresses; therefore do not read from global addresses.
As a Percentage of the VOUT if Using the Resistor
Configuration Pins
In EEPROM if Either Programmed at the Factory or
Through the GUI
By PMBus Command
The IIN and IOUT overcurrent monitors are performed by
ADC readings and calculations. Thus these values are
based on average currents and can have a time latency
of up to 120ms. The IOUT calculation accounts for the
sense resistor and the temperature coefficient of the resistor. The input current is equal to the voltage measured
across the RIINSNS resistor divided by the resistors value
as set with the MFR_IIN_CAL_GAIN command. If this calculated input current exceeds the IN_OC_WARN_LIMIT
the ALERT pin is pulled low and the IIN_OC_WARN bit is
asserted in the STATUS_INPUT command.
Rail addressing provides a means for the bus master to
simultaneously communicate with all channels connected
together to produce a single output voltage (PolyPhase).
While similar to global addressing, the rail address can
be dynamically assigned with the paged MFR_RAIL_
ADDRESS command, allowing for any logical grouping
of channels that might be required for reliable system
control. Do not read from rail addresses since multiple
ADI devices may respond.
The digital processor within the LTC3886 provides the
ability to ignore the fault, shut down and latch off or shut
down and retry indefinitely (retry). The retry interval is set
in MFR_RETRY_DELAY and can be from 120ms to 83.88
seconds in 1ms increments. The shutdown for OV/UV and
OC can be done immediately or after a user selectable
deglitch time.
Device addressing provides the standard means of the
PMBus master communicating with a single instance of
an LTC3886. The value of the device address is set by a
combination of the ASEL0 and ASEL1 configuration pins
and the MFR_ADDRESS command. Device addressing can be disabled by writing a value of 0x80 to the
MFR_ADDRESS.
A programmable overvoltage comparator (OV) guards
against transient overshoots as well as long-term overvoltages at the output. In such cases, the top MOSFET is
turned off and the bottom MOSFET is turned on until the
overvoltage condition is cleared regardless of the PMBus
VOUT_OV_FAULT_RESPONSE command byte value. This
hardware level fault response delay is typically 2µs from
Output Overvoltage Fault Response
Rev G
For more information www.analog.com
27
LTC3886/LTC3886-1
OPERATION
the overvoltage condition to BG asserted high. Using the
VOUT_OV_FAULT_RESPONSE command, the user can
select any of the following behaviors:
n
OV Pull-Down Only (OV Cannot Be Ignored)
n
Shut Down (Stop Switching) Immediately—Latch Off
n
Shut Down Immediately—Retry Indefinitely Using
the Time Interval Specified in MFR_RETRY_DELAY
Either the Latch Off or Retry fault responses can be
deglitched in increments of (0-7) • 10µs. See Table 7.
Output Undervoltage Response
The response to an undervoltage comparator output can
be either:
RESPONSES TO TIMING FAULTS
TON_MAX_FAULT_LIMIT is the time allowed for VOUT to
rise and settle at start-up. The TON_MAX_FAULT_LIMIT
condition is predicated upon detection of the VOUT_UV_
FAULT_LIMIT as the output is undergoing a soft-start
sequence. The TON_MAX_FAULT_LIMIT time is started
after TON_DELAY has been reached and a soft-start
sequence is started. The resolution of the TON_MAX_
FAULT_LIMIT is 10µs. If the VOUT_UV_FAULT_LIMIT is
not reached within the TON_MAX_FAULT_LIMIT time,
the response of this fault is determined by the value of
the TON_MAX_FAULT_RESPONSE command value. This
response may be one of the following:
n
Ignore
Shut Down (Stop Switching) Immediately—Latch Off
n
Ignore
n
n
Shut Down Immediately—Latch Off
n
n
Shut Down Immediately—Retry Indefinitely Using
the Time Interval Specified in MFR_RETRY_DELAY
The UV responses can be deglitched. See Table 8.
Peak Output Overcurrent Fault Response
Due to the current mode control algorithm, peak output
current across the inductor is always limited on a cycle by
cycle basis. The value of the peak current limit is specified in sense voltage in the EC table. The current limit
circuit operates by limiting the ITH maximum voltage. If
DCR sensing is used, the ITH maximum voltage has a
temperature dependency directly proportional to the TC
of the DCR of the inductor. The LTC3886 automatically
monitors the external temperature sensors and modifies
the maximum allowed ITH to compensate for this term.
The overcurrent fault processing circuitry can execute the
following behaviors:
Shut Down Immediately—Retry Indefinitely at the
Time Interval Specified in MFR_RETRY_DELAY
This fault response is not deglitched. A value of 0 in
TON_MAX_FAULT_LIMIT means the fault is ignored. The
TON_MAX_FAULT_LIMIT should be set longer than the
TON_RISE time.
See Table 11.
RESPONSES TO VIN OV FAULTS
VIN overvoltage is measured with the ADC. The response
is deglitched by the 90ms typical response time of the
ADC. The fault responses are:
n
Ignore
n
Shut Down Immediately—Latch Off
n
Shut Down Immediately—Retry Indefinitely Using
the Time Interval Specified in MFR_RETRY_DELAY
See Table 11.
n
Current Limit Indefinitely
n
Shut Down Immediately—Latch Off
RESPONSES TO OT/UT FAULTS
Shut Down Immediately—Retry Indefinitely Using
the Time Interval Specified in MFR_RETRY_DELAY
Internal Overtemperature Fault/Warn Response
n
The overcurrent responses can be deglitched in increments of (0-7) • 16ms. See Table 9.
28
An internal temperature sensor protects against EEPROM
damage. Above 85°C, no writes to EEPROM are recommended. Above 130°C, the internal overtemperature warn
Rev G
For more information www.analog.com
LTC3886/LTC3886-1
OPERATION
threshold is exceeded and the part will NACK any EEPROM
related command except RESTORE_USER_ALL or MFR_
RESET and issue a CML fault for Invalid/Unsupported
Command. Full EEPROM operation is re-enabled when the
internal temperature has dropped below 125°C. When the
die temperature exceeds 160°C the internal overtemperature fault response is enabled and the PWM is disabled
until the die temperature drops below 150°C. Temperature
is measured by the ADC. Internal temperature faults cannot be ignored. Internal temperature limits cannot be
adjusted by the user.
See Table 10.
External Overtemperature and Undertemperature
Fault Response
An external temperature sensor can be used to sense
critical circuit elements like the inductor and power
MOSFETs. The OT_FAULT_RESPONSE and UT_FAULT_
RESPONSE commands are used to determine the appropriate response to an overtemperature and undertemperature
condition, respectively. If no external sense element is used
(not recommended) set the UT_FAULT_RESPONSE to ignore
and set the UT_FAULT_LIMIT to –275°C. However, not using
an external temperature sense element is not recommended.
The fault responses are:
n Ignore
n
n
Shut Down Immediately—Latch Off
Shut Down Immediately—Retry Indefinitely Using
the Time Interval Specified in MFR_RETRY_DELAY
See Table 11.
asserting low when FAULT is pulled low, assert bit 1 of
MFR_CHAN_CONFIG_LTC3886, or mask the ALERT using
the SMBALERT_MASK command.
FAULT LOGGING
The LTC3886 has fault logging capability. Data is logged
into memory in the order shown in Table 13. The data is
stored in a continuously updated buffer in RAM. When a
fault event occurs, the fault log buffer is copied from the
RAM buffer into EEPROM. Fault logging is allowed at temperatures above 85°C; however, retention of 10 years is
not guaranteed. When the die temperature exceeds 130°C,
the fault logging is delayed until the die temperature drops
below 125°C. The fault log data remains in EEPROM until
a MFR_FAULT_LOG_CLEAR command is issued. Issuing
this command re-enables the fault log feature. Before
re-enabling fault log, be sure no faults are present and a
CLEAR_FAULTS command has been issued.
When the LTC3886 powers-up or exits reset state, it
checks the EEPROM for a valid fault log. If a valid fault
log exists in EEPROM, the “Valid Fault Log” bit in the
STATUS_MFR_SPECIFIC command will be set and an
ALERT event will be generated. Also, fault logging will
be blocked until the LTC3886 has received a MFR_
FAULT_LOG_CLEAR command before fault logging will
be re-enabled.
The information is stored in EEPROM in the event of any
fault that disables the controller. The FAULTn pin being
externally pulled low will not trigger a fault logging event.
BUS TIMEOUT PROTECTION
RESPONSES TO EXTERNAL FAULTS
When either FAULTn pin is pulled low, the respective
FAULTn bit is de-asserted in the MFR_PADS command,
the FAULTn bit is set in the STATUS_MFR_SPECIFC
command, the NONE_OF_THE_ABOVE bit is set in the
STATUS_BYTE command, and the ALERT pin is pulled
low. Responses are not deglitched. Each channel can be
configured to ignore or shut down then retry in response
to its FAULTn pin going low by modifying the MFR_
FAULT_RESPONSE command. To avoid the ALERT pin
The LTC3886 implements a timeout feature to avoid persistant faults on the serial interface. The data packet timer
begins at the first START event before the device address
write byte. Data packet information must be completed
within 30ms or the LTC3886 will three-state the bus and
ignore the given data packet. If more time is required,
assert bit 3 of MFR_CONFIG_ALL_LTC3886 to allow typical
bus timeouts of 255ms. Data packet information includes
the device address byte write, command byte, repeat start
event (if a read operation), device address byte read (if a
read operation), all data bytes and the PEC byte if applicable.
Rev G
For more information www.analog.com
29
LTC3886/LTC3886-1
OPERATION
The LTC3886 allows for PMBus timeouts proportional to the length of the block read data packets. The part will add 1ms for every byte of length in
excess of 32 bytes. The additional block read timeout
applies primarily to the MFR_FAULT_LOG command.
The timeout period defaults to 30ms.
The user is encouraged to use as high a clock rate as
possible to maintain efficient data packet transfer between
all devices sharing the serial bus interface. The LTC3886
supports the full PMBus frequency range from 10kHz
to 400kHz.
SIMILARITY BETWEEN PMBus, SMBus AND I2C
2-WIRE INTERFACE
The PMBus 2-wire interface is an incremental extension
of the SMBus. SMBus is built upon I2C with some minor
differences in timing, DC parameters and protocol. The
PMBus/SMBus protocols are more robust than simple I2C
byte commands because PMBus/SMBus provide timeouts to prevent persistent bus errors and optional packet
error checking (PEC) to ensure data integrity. In general, a
master device that can be configured for I2C communication can be used for PMBus communication with little or
no change to hardware or firmware. Repeat start (restart)
is not supported by all I2C controllers but is required for
SMBus/PMBus reads. If a general purpose I2C controller
is used, check that repeat start is supported.
The LTC3886 supports the maximum SMBus clock
speed of 100kHz and is compatible with the higher speed
PMBus specification (between 100kHz and 400kHz) if
MFR_COMMON polling or clock stretching is enabled. For
robust communication and operation refer to the Note section in the PMBus Command Summary. Clock stretching is
enabled by asserting bit 1 of MFR_CONFIG_ALL_LTC3886.
PMBus SERIAL DIGITAL INTERFACE
The LTC3886 communicates with a host (master) using
the standard PMBus serial bus interface. The Timing
Diagram, Figure 5, shows the timing relationship of the
signals on the bus. The two bus lines, SDA and SCL,
must be high when the bus is not in use. External pull-up
resistors or current sources are required on these lines.
30
The LTC3886 is a slave device. The master can communicate with the LTC3886 using the following formats:
n
Master transmitter, slave receiver
n
Master receiver, slave transmitter
The following PMBus protocols are supported:
n
Write Byte, Write Word, Send Byte
n
Read Byte, Read Word, Block Read, Block Write
n
Alert Response Address
Figures 6-23 illustrate the aforementioned PMBus protocols. All transactions support PEC (parity error check)
and GCP (group command protocol). The Block Read
supports 255 bytes of returned data. For this reason, the
PMBus timeout may be extended when reading the fault
log.
Figure 6 is a key to the protocol diagrams in this section.
PEC is optional.
A value shown below a field in the following figures is a
mandatory value for that field.
The data formats implemented by PMBus are:
n
n
n
Master transmitter transmits to slave receiver. The
transfer direction in this case is not changed.
Master reads slave immediately after the first byte.
At the moment of the first acknowledgment (provided by the slave receiver) the master transmitter
becomes a master receiver and the slave receiver
becomes a slave transmitter.
Combined format. During a change of direction
within a transfer, the master repeats both a start
condition and the slave address but with the R/W bit
reversed. In this case, the master receiver terminates
the transfer by generating a NACK on the last byte of
the transfer and a STOP condition.
Refer to Figure 6 for a legend.
Handshaking features are included to ensure robust
system communication. Please refer to the PMBus
Communication and Command Processing subsection
of the Applications Information section for further details.
Rev G
For more information www.analog.com
LTC3886/LTC3886-1
OPERATION
SDA
tf
tr
tLOW
tSU(DAT)
tHD(SDA)
tf
tSP
tr
tBUF
SCL
tHD(STA)
tHD(DAT)
tSU(STA)
tHIGH
tSU(STO)
3886 F05
START
CONDITION
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
Figure 5. Timing Diagram
Table 1. Abbreviations of Supported Data Formats
PMBus
TERMINOLOGY
SPECIFICATION
ADI
REFERENCE TERMINOLOGY DEFINITION
L11
Linear
Part II ¶7.1
Linear_5s_11s
L16
Linear VOUT_MODE
Part II ¶8.2
Linear_16u
CF
DIRECT
Part II ¶7.2
Varies
Reg
register bits
Part II ¶10.3
Reg
ASC
text characters
Part II ¶22.2.1
ASCII
Floating point 16-bit data: value = Y • 2N,
where N = b[15:11] and Y = b[10:0], both
two’s compliment binary integers.
EXAMPLE
b[15:0] = 0x9807 = 10011_000_0000_0111
value = 7 • 2–13 = 854E-6
Floating point 16-bit data: value = Y • 2–12, b[15:0] = 0x4C00 = 0100_1100_0000_0000
where Y = b[15:0], an unsigned integer.
value = 19456 • 2–12 = 4.75
16-bit data with a custom format
defined in the detailed PMBus command
description.
Often an unsigned or two’s compliment
integer.
Per-bit meaning defined in detailed PMBus PMBus STATUS_BYTE command.
command description.
ISO/IEC 8859-1 [A05]
LTC (0x4C5443)
Rev G
For more information www.analog.com
31
LTC3886/LTC3886-1
OPERATION
S
START CONDITION
Sr
REPEATED START CONDITION
Rd
READ (BIT VALUE OF 1)
Wr
WRITE (BIT VALUE OF 0)
A
ACKNOWLEDGE (THIS BIT POSITION MAY BE 0
FOR AN ACK OR 1 FOR A NACK)
P
STOP CONDITION
PEC PACKET ERROR CODE
MASTER TO SLAVE
SLAVE TO MASTER
...
CONTINUATION OF PROTOCOL
3886 F06
Figure 6. PMBus Packet Protocol Diagram Element Key
1
7
S
1
1
SLAVE ADDRESS Rd/Wr A
1
P
3886 F07
Figure 7. Quick Command Protocol
1
S
1
1
SLAVE ADDRESS Wr A COMMAND CODE A
7
1
1
8
P
3886 F08
Figure 8. Send Byte Protocol
1
S
7
1
1
8
1
SLAVE ADDRESS Wr A COMMAND CODE A
8
1
1
PEC
A
P
3886 F09
Figure 9. Send Byte Protocol with PEC
1
S
7
1
1
8
1
SLAVE ADDRESS Wr A COMMAND CODE A
8
1
1
DATA BYTE
A
P
3886 F10
Figure 10. Write Byte Protocol
1
S
7
1
1
8
1
SLAVE ADDRESS Wr A COMMAND CODE A
8
1
8
1
1
DATA BYTE
A
PEC
A
P
3886 F11
Figure 11. Write Byte Protocol with PEC
1
S
7
1
1
8
1
SLAVE ADDRESS Wr A COMMAND CODE A
8
1
8
1
1
DATA BYTE LOW
A
DATA BYTE HIGH
A
P
3886 F12
Figure 12. Write Word Protocol
1
S
7
1
1
8
1
SLAVE ADDRESS Wr A COMMAND CODE A
8
1
8
1
8
1
1
DATA BYTE LOW
A
DATA BYTE HIGH
A
PEC
A
P
3886 F13
Figure 13. Write Word Protocol with PEC
32
Rev G
For more information www.analog.com
LTC3886/LTC3886-1
OPERATION
1
S
7
1
1
8
1
1
1
7
1
SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A
8
1
1
DATA BYTE
A
P
3886 F14
Figure 14. Read Byte Protocol
1
S
7
1
1
8
1
7
1
1
1
SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A
8
1
DATA BYTE
A
PEC
1
1
A
P
3886 F15
Figure 15. Read Byte Protocol with PEC
1
S
7
1
1
8
1
1
SLAVE ADDRESS Wr A COMMAND CODE A
7
1
1
Sr SLAVE ADDRESS Rd A
8
1
DATA BYTE LOW
A
1
1
DATA BYTE HIGH A
8
P
3886 F16
Figure 16. Read Word Protocol
1
S
7
1
1
8
1
1
7
1
1
SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A
8
1
DATA BYTE LOW
A
8
1
DATA BYTE HIGH A
8
1
1
PEC
A
P
3886 F17
Figure 17. Read Word Protocol with PEC
1
S
7
1
1
8
1
7
1
1
1
SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A
8
1
BYTE COUNT = N A
8
1
8
1 …
8
1
1
DATA BYTE 1
A
DATA BYTE 2
A …
DATA BYTE N
A
P
…
3886 F18
Figure 18. Block Read Protocol
1
S
7
1
1
8
1
1
7
1
1
SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A
8
1
BYTE COUNT = N A
8
1
8
1 …
8
1
8
1
1
DATA BYTE 1
A
DATA BYTE 2
A …
DATA BYTE N
A
PEC
A
P
…
3886 F19
Figure 19. Block Read Protocol with PEC
Rev G
For more information www.analog.com
33
LTC3886/LTC3886-1
OPERATION
1
S
7
1
1
8
1
8
1
SLAVE ADDRESS Wr A COMMAND CODE A BYTE COUNT = M A
8
1
DATA BYTE 2
1
7
1
8
A …
1
Sr SLAVE ADDRESS Rd A
1
A
…
1
A …
DATA BYTE M
8
8
DATA BYTE 1
1
BYTE COUNT = N A
8
1
1
DATA BYTE 1
A
…
8
1 …
8
1
1
DATA BYTE 2
A …
DATA BYTE N
A
P
3886 F20
Figure 20. Block Write – Block Read Process Call
1
S
7
1
1
8
1
8
1
SLAVE ADDRESS Wr A COMMAND CODE A BYTE COUNT = M A
8
1
DATA BYTE 2
1
7
1
8
A …
1
Sr SLAVE ADDRESS Rd A
1
A
…
1
DATA BYTE M
8
8
DATA BYTE 1
A …
1
BYTE COUNT = N A
8
1
1
DATA BYTE 1
A
…
8
1 …
8
1
8
1
1
DATA BYTE 2
A …
DATA BYTE N
A
PEC
A
P
3886 F21
Figure 21. Block Write – Block Read Process Call with PEC
1
7
1
1
8
1
1
S ALERT RESPONSE Rd A DEVICE ADDRESS A
ADDRESS
P
3886 F22
Figure 22. Alert Response Address Protocol
1
7
1
1
8
1
S ALERT RESPONSE Rd A DEVICE ADDRESS A
ADDRESS
8
1
PEC
A
1
P
3886 F23
Figure 23. Alert Response Address Protocol with PEC
34
Rev G
For more information www.analog.com
LTC3886/LTC3886-1
PMBus COMMAND SUMMARY
PMBus COMMANDS
The following tables list supported PMBus commands
and manufacturer specific commands. A complete
description of these commands can be found in the
PMBus Power System Mgt Protocol Specification. Users
are encouraged to reference this specification. Exceptions
or manufacturer specific implementations are listed below
in Table 2. Floating point values listed in the “DEFAULT
VALUE” column are either Linear 16-bit Signed (PMBus
Section 8.3.1) or Linear_5s_11s (PMBus Section 7.1)
format, whichever is appropriate for the command. All
commands from 0xD0 through 0xFF not listed in this table
are implicitly reserved by the manufacturer. Users should
avoid blind writes within this range of commands to avoid
undesired operation of the part. All commands from 0x00
through 0xCF not listed in this table are implicitly not
supported by the manufacturer. Attempting to access
non-supported or reserved commands may result in a
CML command fault event. All output voltage settings and
measurements are based on the VOUT_MODE setting of
0x14. This translates to an exponent of 2–12.
If PMBus commands are received faster than they are
being processed, the part may become too busy to handle
new commands. In these circumstances the part follows
the protocols defined in the PMBus Specification v1.2,
Part II, Section 10.8.7, to communicate that it is busy.
The part includes handshaking features to eliminate busy
errors and simplify error handling software while ensuring robust communication and system behavior. Please
refer to the subsection titled PMBus Communication and
Command Processing in the Applications Information
section for further details.
Table 2. Summary (Note: The Data Format abbreviations are detailed at the end of this table.)
COMMAND NAME
CMD
CODE DESCRIPTION
TYPE
DATA
PAGED FORMAT UNITS EEPROM
DEFAULT
VALUE PAGE
PAGE
0x00 Provides integration with multi-page PMBus
devices.
R/W Byte
N
Reg
0x00
69
OPERATION
0x01 Operating mode control. On/off, margin high
and margin low.
R/W Byte
Y
Reg
Y
0x40
73
ON_OFF_CONFIG
0x02 RUN pin and PMBus bus on/off command
configuration.
R/W Byte
Y
Reg
Y
0x1E
73
CLEAR_FAULTS
0x03 Clear any fault bits that have been set.
Send Byte
N
PAGE_PLUS_WRITE
0x05 Write a command directly to a specified page.
W Block
N
NA
99
69
PAGE_PLUS_READ
0x06 Read a command directly from a specified
page.
Block R/W
N
70
WRITE_PROTECT
0x10 Level of protection provided by the device
against accidental changes.
R/W Byte
N
STORE_USER_ALL
0x15 Store user operating memory to EEPROM.
Send Byte
RESTORE_USER_ALL
0x16 Restore user operating memory from
EEPROM.
CAPABILITY
0x19 Summary of PMBus optional communication
protocols supported by this device.
SMBALERT_MASK
0x1B Mask ALERT activity
VOUT_MODE
0x20 Output voltage format and exponent (2–12).
VOUT_COMMAND
0x00
70
N
NA
110
Send Byte
N
NA
110
R Byte
N
Reg
0xB0
98
Block R/W
Y
Reg
see CMD
100
R Byte
Y
Reg
2–12
0x14
79
0x21 Nominal output voltage set point.
R/W Word
Y
L16
V
Y
1.0 0x1000
80
VOUT_MAX
0x24 Upper limit on the commanded output voltage
including VOUT_MARGIN_HI.
R/W Word
Y
L16
V
Y
14.0
0xE000
79
VOUT_MARGIN_HIGH
0x25 Margin high output voltage set point. Must be
greater than VOUT_COMMAND.
R/W Word
Y
L16
V
Y
1.05
0x10CD
80
Reg
Y
Y
Rev G
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35
LTC3886/LTC3886-1
PMBus COMMAND SUMMARY
COMMAND NAME
CMD
CODE DESCRIPTION
TYPE
DATA
PAGED FORMAT UNITS EEPROM
DEFAULT
VALUE PAGE
VOUT_MARGIN_LOW
0x26 Margin low output voltage set point. Must be
less than VOUT_COMMAND.
R/W Word
Y
L16
V
Y
0.95
0x0F33
80
VOUT_TRANSITION_
RATE
0x27 Rate the output changes when VOUT
commanded to a new value.
R/W Word
Y
L11
V/ms
Y
0.25
0xAA00
87
FREQUENCY_SWITCH
0x33 Switching frequency of the controller.
R/W Word
N
L11
kHz
Y
350
0xFABC
77
VIN_ON
0x35 Input voltage at which the unit should start
power conversion.
R/W Word
N
L11
V
Y
6.5
0xCB40
78
VIN_OFF
0x36 Input voltage at which the unit should stop
power conversion.
R/W Word
N
L11
V
Y
6.0
0xCB00
78
IOUT_CAL_GAIN
0x38 The ratio of the voltage at the current sense
R/W Word
pins to the sensed current. For devices using a
fixed current sense resistor, it is the resistance
value in mΩ.
Y
L11
mΩ
Y
1.8
0xBB9A
82
VOUT_OV_FAULT_LIMIT
0x40 Output overvoltage fault limit.
R/W Word
Y
L16
V
Y
1.1
0x119A
79
VOUT_OV_FAULT_
RESPONSE
0x41 Action to be taken by the device when an
output overvoltage fault is detected.
R/W Byte
Y
Reg
Y
0xB8
89
VOUT_OV_WARN_LIMIT
0x42 Output overvoltage warning limit.
R/W Word
Y
L16
V
Y
1.075
0x1133
80
VOUT_UV_WARN_LIMIT
0x43 Output undervoltage warning limit.
R/W Word
Y
L16
V
Y
0.925
0x0ECD
81
VOUT_UV_FAULT_LIMIT
0x44 Output undervoltage fault limit.
R/W Word
Y
L16
V
VOUT_UV_FAULT_
RESPONSE
0x45 Action to be taken by the device when an
output undervoltage fault is detected.
R/W Byte
Y
Reg
IOUT_OC_FAULT_LIMIT
0x46 Output overcurrent fault limit.
R/W Word
Y
L11
IOUT_OC_FAULT_
RESPONSE
0x47 Action to be taken by the device when an
output overcurrent fault is detected.
R/W Byte
Y
Reg
IOUT_OC_WARN_LIMIT
0x4A Output overcurrent warning limit.
R/W Word
Y
L11
OT_FAULT_LIMIT
0x4F External overtemperature fault limit.
R/W Word
Y
L11
OT_FAULT_RESPONSE
0x50 Action to be taken by the device when an
external overtemperature fault is detected,
R/W Byte
Y
Reg
OT_WARN_LIMIT
0x51 External overtemperature warning limit.
R/W Word
Y
L11
UT_FAULT_LIMIT
0x53 External undertemperature fault limit.
R/W Word
Y
L11
UT_FAULT_RESPONSE
0x54 Action to be taken by the device when an
external undertemperature fault is detected.
R/W Byte
Y
Reg
VIN_OV_FAULT_LIMIT
0x55 Input supply overvoltage fault limit.
R/W Word
N
L11
VIN_OV_FAULT_
RESPONSE
0x56 Action to be taken by the device when an input
overvoltage fault is detected.
R/W Byte
Y
Reg
VIN_UV_WARN_LIMIT
0x58 Input supply undervoltage warning limit.
R/W Word
N
L11
IIN_OC_WARN_LIMIT
0x5D Input supply overcurrent warning limit.
R/W Word
N
L11
36
Y
0.9 0x0E66
81
Y
0xB8
90
Y
29.75
0xDBB8
83
Y
0x00
92
A
Y
20.0
0xDA80
84
C
Y
100.0
0xEB20
85
Y
0xB8
94
C
Y
85.0
0xEAA8
85
C
Y
–40.0
0xE580
86
Y
0xB8
94
Y
48.0
0xE300
78
Y
0x80
89
V
Y
6.3
0xCB26
78
A
Y
10.0
0xD280
84
A
V
Rev G
For more information www.analog.com
LTC3886/LTC3886-1
PMBus COMMAND SUMMARY
COMMAND NAME
CMD
CODE DESCRIPTION
TYPE
DATA
PAGED FORMAT UNITS EEPROM
DEFAULT
VALUE PAGE
TON_DELAY
0x60 Time from RUN and/or Operation on to output
rail turn-on.
R/W Word
Y
L11
ms
Y
0.0
0x8000
86
TON_RISE
0x61 Time from when the output starts to rise
until the output voltage reaches the VOUT
commanded value.
R/W Word
Y
L11
ms
Y
8.0
0xD200
86
TON_MAX_FAULT_LIMIT
0x62 Maximum time from the start of TON_RISE for R/W Word
VOUT to cross the VOUT_UV_FAULT_LIMIT.
Y
L11
ms
Y
10.00
0xD280
86
TON_MAX_FAULT_
RESPONSE
0x63 Action to be taken by the device when a TON_
MAX_FAULT event is detected.
R/W Byte
Y
Reg
Y
0xB8
92
TOFF_DELAY
0x64 Time from RUN and/or Operation off to the
start of TOFF_FALL ramp.
R/W Word
Y
L11
ms
Y
0.0 0x8000
87
TOFF_FALL
0x65 Time from when the output starts to fall until
the output reaches zero volts.
R/W Word
Y
L11
ms
Y
8.00
0xD200
87
TOFF_MAX_WARN_LIMIT 0x66 Maximum allowed time, after TOFF_FALL
completed, for the output to decay below
12.5% (LTC3886), MFR_VOFF_THRESHOLD
(LTC3886-1).
R/W Word
Y
L11
ms
Y
150.0
0xF258
88
STATUS_BYTE
R/W Byte
Y
Reg
NA
101
STATUS_WORD
0x79 Two byte summary of the unit’s fault condition. R/W Word
Y
Reg
NA
101
STATUS_VOUT
0x7A Output voltage fault and warning status.
R/W Byte
Y
Reg
NA
102
STATUS_IOUT
0x7B Output current fault and warning status.
R/W Byte
Y
Reg
NA
102
STATUS_INPUT
0x7C Input supply fault and warning status.
R/W Byte
N
Reg
NA
103
STATUS_TEMPERATURE
0x7D External temperature fault and warning status
for READ_TEMERATURE_1.
R/W Byte
Y
Reg
NA
103
STATUS_CML
0x7E Communication and memory fault and warning R/W Byte
status.
N
Reg
NA
104
STATUS_MFR_SPECIFIC
0x80 Manufacturer specific fault and state
information.
R/W Byte
Y
Reg
NA
104
READ_VIN
0x88 Measured input supply voltage.
R Word
N
L11
V
NA
107
READ_IIN
0x89 Measured input supply current.
R Word
N
L11
A
NA
107
READ_VOUT
0x8B Measured output voltage.
R Word
Y
L16
V
NA
107
READ_IOUT
0x8C Measured output current.
R Word
Y
L11
A
NA
107
READ_TEMPERATURE_1
0x8D External temperature sensor temperature. This
is the value used for all temperature related
processing, including IOUT_CAL_GAIN.
R Word
Y
L11
C
NA
107
READ_TEMPERATURE_2
0x8E Internal die junction temperature. Does not
affect any other commands.
R Word
N
L11
C
NA
107
READ_FREQUENCY
0x95 Measured PWM switching frequency.
R Word
Y
L11
kHz
NA
107
READ_POUT
0x96 Calculated output power.
R Word
Y
L11
W
NA
108
READ_PIN
0x97 Calculated input power
R Word
N
L11
W
NA
108
PMBUS_REVISION
0x98 PMBus revision supported by this device.
Current revision is 1.2.
R Byte
N
Reg
0x22
98
MFR_ID
0x99 The manufacturer ID of the LTC3886 in ASCII.
R String
N
ASC
LTC
98
MFR_MODEL
0x9A LTC3886 manufacturer part number in ASCII.
LTC3886-1 manufacturer part number in ASCII.
R String
N
ASC
LTC3886
LTC3886-1
98
MFR_VOUT_MAX
0xA5 Maximum allowed output voltage including
VOUT_OV_FAULT_LIMIT.
R Word
Y
L16
14.0
0xE000
81
0x78 One byte summary of the unit’s fault condition.
V
Rev G
For more information www.analog.com
37
LTC3886/LTC3886-1
PMBus COMMAND SUMMARY
CMD
CODE DESCRIPTION
IC_DEVICE_ID
0xAD Identification of the IC (LTC3886-1 only)
R Block
N
ASC
Y
LTC3886-1
98
IC_DEVICE_REV
0xAE Revision of the IC (LTC3886-1 only)
R Block
N
ASC
Y
ACA0
99
USER_DATA_00
0xB0 OEM RESERVED. Typically used for part
serialization.
R/W Word
N
Reg
Y
NA
97
USER_DATA_01
0xB1 Manufacturer reserved for LTpowerPlay.
R/W Word
Y
Reg
Y
NA
97
USER_DATA_02
0xB2 OEM RESERVED. Typically used for part
serialization
R/W Word
N
Reg
Y
NA
97
USER_DATA_03
0xB3 An EEPROM word available for the user.
R/W Word
Y
Reg
Y
0x0000
97
USER_DATA_04
0xB4 An EEPROM word available for the user.
R/W Word
N
Reg
Y
0x0000
97
MFR_INFO
0xB6 Manufacturing Specific Information
NA
104
MFR_EE_UNLOCK
0xBD Contact factory.
116
MFR_EE_ERASE
0xBE Contact factory.
116
TYPE
DATA
PAGED FORMAT UNITS EEPROM
DEFAULT
VALUE PAGE
COMMAND NAME
R Word
Reg
116
MFR_EE_DATA
0xBF Contact factory.
MFR_CHAN_CONFIG_
LTC3886
0xD0 LTC3886 Channel specific configuration bits.
LTC3886-1 Channel specific configuration bits.
R/W Byte
R/W Byte
Y
Y
Reg
Reg
Y
Y
0x1D
0x3D
72
MFR_CONFIG_ALL_
LTC3886
0xD1 General configuration bits.
R/W Byte
N
Reg
Y
0x21
72
MFR_FAULT_
PROPAGATE_LTC3886
0xD2 Configuration that determines which faults are
propagated to the FAULT pin.
R/W Word
Y
Reg
Y
0x6993
95
MFR_PWM_COMP
0xD3 PWM loop compensation configuration
R/W Byte
Y
Reg
Y
0x70
75
MFR_PWM_MODE_
LTC3886
0xD4 Configuration for the PWM engine.
R/W Byte
Y
Reg
Y
0xC1
74
MFR_FAULT_RESPONSE
0xD5 Action to be taken by the device when the
FAULT pin is externally asserted low.
R/W Byte
Y
Reg
Y
0xC0
97
MFR_OT_FAULT_
RESPONSE
0xD6 Action to be taken by the device when an
internal overtemperature fault is detected.
R Byte
N
Reg
0xC0
93
MFR_IOUT_PEAK
0xD7 Report the maximum measured value of
READ_IOUT since last MFR_CLEAR_PEAKS.
R Word
Y
L11
NA
108
MFR_ADC_CONTROL
0xD8 ADC telemetry parameter selected for repeated
fast ADC read back
R/W Byte
N
Reg
0x00
108
MFR_VOFF_THRESHOLD
0xDA The PWM channel remains active until the
ADC measures VOUT below this value during
sequencing OFF (LTC3886-1 only).
R/W Word
Y
L16
V
Y
0.1
0x019A
81
MFR_RETRY_DELAY
0xDB Retry interval during FAULT retry mode.
R/W Word
Y
L11
ms
Y
350.0
0xFABC
88
MFR_RESTART_DELAY
0xDC Minimum time the RUN pin is held low by the
LTC3886.
R/W Word
Y
L11
ms
Y
500.0
0xFBE8
88
MFR_VOUT_PEAK
0xDD Maximum measured value of READ_VOUT
since last MFR_CLEAR_PEAKS.
R Word
Y
L16
V
NA
107
MFR_VIN_PEAK
0xDE Maximum measured value of READ_VIN since
last MFR_CLEAR_PEAKS.
R Word
N
L11
V
NA
109
MFR_TEMPERATURE_1_
PEAK
0xDF Maximum measured value of external
Temperature (READ_TEMPERATURE_1) since
last MFR_CLEAR_PEAKS.
R Word
Y
L11
C
NA
109
MFR_READ_IIN_PEAK
0xE1 Maximum measured value of READ_IIN
command since last MFR_CLEAR_PEAKS
R Word
N
L11
A
NA
109
38
A
Rev G
For more information www.analog.com
LTC3886/LTC3886-1
PMBus COMMAND SUMMARY
COMMAND NAME
CMD
CODE DESCRIPTION
MFR_CLEAR_PEAKS
0xE3 Clears all peak values.
MFR_READ_ICHIP
0xE4 Measured supply current of the LTC3886
MFR_PADS
0xE5 Digital status of the I/O pads.
MFR_ADDRESS
0xE6 Sets the 7-bit I2C address byte.
MFR_SPECIAL_ID
0xE7 Manufacturer code representing the LTC3886.
Manufacturer code representing the LTC3886-1.
MFR_IIN_CAL_GAIN
0xE8 The resistance value of the input current sense R/W Word
element in mΩ.
TYPE
DATA
PAGED FORMAT UNITS EEPROM
Send Byte
N
R Word
N
L11
R Word
N
Reg
R/W Byte
N
Reg
R Word
N
Reg
N
L11
A
Y
mΩ
Y
DEFAULT
VALUE PAGE
NA
100
NA
109
NA
105
0x4F
71
0x460X
0x461X
98
5.0
0xCA80
84
MFR_FAULT_LOG_STORE 0xEA Command a transfer of the fault log from RAM
to EEPROM.
Send Byte
N
NA
112
MFR_FAULT_LOG_CLEAR 0xEC Initialize the EEPROM block reserved for fault
logging.
Send Byte
N
NA
116
NA
110
NA
105
NA
111
NA
109
Y
0x10
76
MFR_FAULT_LOG
0xEE Fault log data bytes.
R Block
N
Reg
MFR_COMMON
0xEF Manufacturer status bits that are common
across multiple ADI chips.
R Byte
N
Reg
MFR_COMPARE_USER_
ALL
0xF0 Compares current command contents with
EEPROM.
Send Byte
N
MFR_TEMPERATURE_2_
PEAK
0xF4 Peak internal die temperature since last
MFR_CLEAR_PEAKS.
R Word
N
L11
MFR_PWM_CONFIG_
LTC3886
0xF5 Set numerous parameters for the DC/DC
controller including phasing.
R/W Byte
N
Reg
MFR_IOUT_CAL_GAIN_
TC
0xF6 Temperature coefficient of the current sensing
element.
R/W Word
Y
CF
ppm/
˚C
Y
3900
0x0F3C
82
MFR_RVIN
0xF7 The resistance value of the VIN pin filter
element in mΩ.
R/W Word
N
L11
mΩ
Y
2000
0x0BE8
78
MFR_TEMP_1_GAIN
0xF8 Sets the slope of the external temperature
sensor.
R/W Word
Y
CF
Y
1.0
0x4000
85
MFR_TEMP_1_OFFSET
0xF9 Sets the offset of the external temperature
sensor with respect to –273.1°C
R/W Word
Y
L11
Y
0.0
0x8000
85
MFR_RAIL_ADDRESS
0xFA Common address for PolyPhase outputs to
adjust common parameters.
R/W Byte
Y
Reg
Y
0x80
71
MFR_RESET
0xFD Commanded reset without requiring a power
down.
Send Byte
N
NA
74
Note 1: Commands indicated with Y in the EEPROM column indicate that
these commands are stored and restored using the STORE_USER_ALL
and RESTORE_USER_ALL commands, respectively.
Note 2: Commands with a default value of NA indicate “not applicable”.
Commands with a default value of FS indicate “factory set on a per part
basis”.
Note 3: The LTC3886 contains additional commands not listed in this
table. Reading these commands is harmless to the operation of the IC;
however, the contents and meaning of these commands can change
without notice.
Y
C
C
Note 4: Some of the unpublished commands are read-only and will
generate a CML bit 6 fault if written.
Note 5: Writing to commands not published in this table is not permitted.
Note 6: The user should not assume compatibility of commands
between different parts based upon command names. Always refer to
the manufacturer’s data sheet for each part for a complete definition of a
command’s function.
ADI strives to keep command functionality compatible between all ADI
devices. Differences may occur to address specific product requirements.
Rev G
For more information www.analog.com
39
LTC3886/LTC3886-1
PMBus COMMAND SUMMARY
*DATA FORMAT
L11
Linear_5s_11s
PMBus data field b[15:0]
Value = Y • 2N
where N = b[15:11] is a 5-bit two’s complement integer and Y = b[10:0] is an 11-bit
two’s complement integer
Example:
For b[15:0] = 0x9807 = ‘b10011_000_0000_0111
Value = 7 • 2–13 = 854 • 10–6
From “PMBus Spec Part II: Paragraph 7.1”
L16
Linear_16u
PMBus data field b[15:0]
Value = Y • 2N
where Y = b[15:0] is an unsigned integer and N = Vout_mode_parameter is a 5-bit two’s
complement exponent that is hardwired to –12 decimal
Example:
For b[15:0] = 0x9800 = ‘b1001_1000_0000_0000
Value = 38912 • 2–12 = 9.50
From “PMBus Spec Part II: Paragraph 8.2”
Reg
Register
PMBus data field b[15:0] or b[7:0].
Bit field meaning is defined in detailed PMBus Command Description.
I16
Integer Word
PMBus data field b[15:0]
Value = Y
where Y = b[15:0] is a 16 unsigned integer
Example:
For b[15:0] = 0x9807 = ‘b1001_1000_0000_0111
Value = 38919 (decimal)
CF
ASC
Custom Format
Value is defined in detailed PMBus Command Description.
This is often an unsigned or two’s complement integer scaled by an MFR specific
constant.
ASCII Format
A variable length string of text characters conforming to ISO/IEC 8859-1 standard.
40
Rev G
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LTC3886/LTC3886-1
APPLICATIONS INFORMATION
The Typical Application on the last page of this data sheet
is a common LTC3886 application circuit. The LTC3886
can be configured to use either DCR (inductor resistance) sensing or low value resistor sensing. The choice
between the two current sensing schemes is largely a
design trade-off between cost, power consumption and
accuracy. DCR sensing is popular because it saves expensive current sensing resistors and is more power efficient,
especially in high current applications. The LTC3886 can
nominally account for the temperature dependency of the
DCR sensing element. The accuracy of the current reading and current limit are typically limited by the accuracy
of the DCR of the inductor (which is programmed as the
IOUT_CAL_GAIN register of the LTC3886). However, current sensing resistors provide the most accurate current
sense and limiting. Other external component selections
are driven by the load requirement, and begins with the
selection of RSENSE (if RSENSE is used) and inductor value.
Next, the power MOSFETs are selected. Then the input and
output capacitors are selected. Finally the current limit is
selected. All of these components and ranges are required
to be determined prior to selecting the RITH and EA_GM
values in the MFR_PWM_COMP register and calculating
the external compensation components. The current limit
range is required because the two ranges (25mV to 50mV
vs 37.5mV to 75mV) have different EA gains set with bit 7
of the MFR_PWM_MODE_LTC3886 command. The voltage RANGE bit also affects the loop gain and impacts the
compensation network. The voltage RANGE is set with
bit 1 of MFR_PWM_MODE_LTC3886. All other programmable parameters do not affect the loop gain, allowing
parameters to be modified without impacting the transient
response to load changes.
CURRENT LIMIT PROGRAMMING
The LTC3886 has two ranges of current limit programming
and a total of eight levels within each range. Refer to the
IOUT_OC_FAULT_LIMIT section of the PMBus commands.
Within each range the error amp gain is fixed, resulting
in constant loop gain. The LTC3886 will account for the
temperature coefficient of the inductor DCR and automatically adjust the current limit when inductor temperature
changes. The temperature coefficient of the DCR is stored
in the MFR_IOUT_CAL_GAIN_TC command.
For the best current limit accuracy, use the 75mV setting.
The 25mV setting will allow for the use of very low DCR
inductors or sense resistors, but at the expense of current
limit accuracy. Peak current limiting is on a cycle-by-cycle
basis. The average inductor current is monitored by the
ADC converter and can provide a warning if too much
average output current is detected. An overcurrent fault
is detected when the ITH voltage exceeds the limit set by
IOUT_OC_FAULT_LIMIT. The digital processor within the
LTC3886 provides the ability to either ignore the fault,
shut down and latch off or shut down and retry indefinitely
(retry). Refer to the overcurrent portion of the Operation
section for more detail.
ISENSE+ and ISENSE– PINS
The ISENSE+ and ISENSE– pins are the inputs to the current
comparator and the A/D. The common mode input voltage
range of the current comparators is 0V to 14V. Both the
SENSE pins are high impedance inputs with small input
currents typically less than 1µA. The high impedance
inputs to the current comparators enable accurate DCR
sensing. Do not float these pins during normal operation.
Filter components connected to the ISENSE traces should
be placed close to the IC. The positive and negative traces
should be routed differentially and Kelvin connected to
the current sense element, see Figure 24. A non-Kelvin
connection or improper placement can add parasitic
inductance and capacitance to the current sense element, degrading the signal at the sense terminals and
making the programmed current limit perform poorly. In
a PolyPhase system, poor placement of the sensing element will result in sub-optimal current sharing between
power stages. If DCR sensing is used (Figure 25a), sense
resistor R1 should be placed close to the inductor to
prevent noise from coupling into sensitive small-signal
nodes. The capacitor C1 should be placed close to the IC
TO SENSE FILTER,
NEXT TO THE CONTROLLER
COUT
INDUCTOR OR RSENSE
3886 F24
Figure 24. Optimal Sense Line Placement
Rev G
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41
LTC3886/LTC3886-1
APPLICATIONS INFORMATION
pins. Any impedance difference between the ISENSE+ and
ISENSE– signal paths can result in loss of accuracy in the
current reading of the ADC. The current reading accuracy can be improved by matching the impedance of the
two signal paths. To accomplish this add a series resistor
between VOUT and ISENSE– equal to R1. A capacitor of 1µF
or greater should be placed in parallel with this resistor.
If the peak voltage is 1µF
R1
ISENSE+
C1*
R2
ISENSE–
3886 F25a
R2
IOUT_CAL_GAIN = DCR ×
R1 + R2 + R3
*PLACE C1 NEAR SENSE+, SENSE– PINS
Figure 25a. Inductor DCR Current Sense Circuit
VIN
INTVCC
VIN
SENSE RESISTOR
PLUS PARASITIC
INDUCTANCE
BOOST
TG
RS
SW
ESL
VOUT
LTC3886
BG
GND
RF
CF • 2RF ≤ ESL/RS
POLE-ZERO
CANCELLATION
CF
3886 F25b
RF
FILTER COMPONENTS
PLACED NEAR SENSE PINS
Figure 25b. Resistor Current Sense Circuit
VSENSE(MAX)
ΔI
IMAX + L
2
Due to possible PCB noise in the current sensing loop, the
AC current sensing ripple of ∆VSENSE = ∆IL • RSENSE also
needs to be checked in the design to get a good signal-tonoise ratio. In general, for a reasonably good PCB layout,
a 15mV minimum ∆VSENSE voltage is recommended as
a conservative number to start with, either for RSENSE or
DCR sensing applications.
R3
OPTIONAL
2 ×L
((R1+ R3)||R2) × C1 =
DCR
R3 = R1
RSENSE =
BG
GND
42
The current comparator has a maximum threshold
VSENSE(MAX) determined by the ILIMIT setting. The input
common mode range of the current comparator is 0V to
14V (if VIN is greater than 15V). The current comparator
threshold sets the peak of the inductor current, yielding a maximum average output current IMAX equal to the
peak value less half the peak-to-peak ripple current ∆IL.
To calculate the sense resistor value, use the equation:
VOUT
LTC3886
ISENSE–
A typical sensing circuit using a discrete resistor is shown
in Figure 25b. RSENSE is chosen based on the required
output current.
INDUCTOR
TG
ISENSE+
LOW VALUE RESISTOR CURRENT SENSING
For previous generation current mode controllers, the
maximum sense voltage was high enough (e.g., 75mV for
the LTC1628/LTC3728 family) that the voltage drop across
the parasitic inductance of the sense resistor represented
a relatively small error. In the newer and higher current
density solutions, the value of the sense resistor can be
less than 1mΩ and the peak sense voltage can be less than
20mV. Also, inductor ripple currents greater than 50%
with operation up to 750kHz are becoming more common.
Under these conditions, the voltage drop across the sense
resistor’s parasitic inductance is no longer negligible. A
typical sensing circuit using a discrete resistor is shown in
Figure 25b. In previous generations of controllers, a small
RC filter placed near the IC was commonly used to reduce
the effects of the capacitive and inductive noise coupled
in the sense traces on the PCB. A typical filter consists of
two series 100Ω resistors connected to a parallel 1000pF
capacitor, resulting in a time constant of 200ns.
Rev G
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LTC3886/LTC3886-1
APPLICATIONS INFORMATION
This same RC filter with minor modifications, can be used
to extract the resistive component of the current sense
signal in the presence of parasitic inductance. For example, Figure 26 illustrates the voltage waveform across a
2mΩ resistor with a PCB footprint of 2010. The waveform
is the superposition of a purely resistive component and a
purely inductive component. It was measured using two
scope probes and waveform math to obtain a differential
measurement. Based on additional measurements of the
inductor ripple current and the on-time, tON, and off-time,
tOFF, of the top switch, the value of the parasitic inductance was determined to be 0.5nH using the equation:
ESL =
VESL(STEP) tON • tOFF
•
ΔIL
tON + tOFF
(1)
If the RC time constant is chosen to be close to the parasitic inductance divided by the sense resistor (L/R), the
resultant waveform looks resistive, as shown in Figure 27.
For applications using low maximum sense voltages,
check the sense resistor manufacturer’s data sheet for
information about parasitic inductance. In the absence of
VSENSE
20mV/DIV
VESL(STEP)
500ns/DIV
INDUCTOR DCR CURRENT SENSING
For applications requiring the highest possible efficiency
at high load currents, the LTC3886 is capable of sensing
the voltage drop across the inductor DCR, as shown in
Figure 25a. The DCR of the inductor represents the small
amount of DC winding resistance of the copper, which
can be less than 1mΩ for today’s low value, high current
inductors. In a high current application requiring such an
inductor, conduction loss through a sense resistor would
reduce the efficiency by a few percent compared to DCR
sensing.
If R1 = R3 and the external (R1 + R3)||R2 • C1 time constant is chosen to be exactly equal to the 2 • L/DCR time
constant, assuming R1 = R3, the voltage drop across
the external capacitor,C1, is equal to the drop across the
inductor DCR multiplied by R2/(R1 + R2 + R3). R2 scales
the voltage across the sense terminals for applications
where the DCR is greater than the target sense resistor
value. The DCR value is entered as the IOUT_CAL_GAIN
in mΩ unless R2 is required. If R2 is used:
3886 F26
Figure 26. Voltage Measured Directly Across RSENSE
VSENSE
20mV/DIV
500ns/DIV
data, measure the voltage drop directly across the sense
resistor to extract the magnitude of the ESL step and use
Equation 1 to determine the ESL. However, do not overfilter the signal. Keep the RC time constant less than or
equal to the inductor time constant to maintain a sufficient
ripple voltage on VRSENSE for optimal operation of the
current loop controller.
3886 F27
Figure 27. Voltage Measured After the RSENSE Filter
IOUT _ CAL _ GAIN = DCR •
R2
R1+ R2 + R3
R2 can be removed if there is no need to attenuate the
current sense signal in order to remain within the desired
current sense range. To properly select the external filter
components, the DCR of the inductor must be known.
It can be measured using an accurate RLC meter, but
the DCR tolerance is not always the same and varies
with temperature. Consult the inductor manufacturers’
data sheets for detailed information. The LTC3886 will
correct for temperature variation if the correct temperature coefficient value is entered into the MFR_IOUT_
CAL_GAIN_TC command. Typically the resistance has a
3900ppm/°C coefficient.
Rev G
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43
LTC3886/LTC3886-1
APPLICATIONS INFORMATION
Assuming R1 = R3, C2 can be optimized for a flat frequency response using the following equation:
C2 =
L
( 2R1+ R2 )
DCR
R12
2R1• R2 • C1–
Using the inductor ripple current value from the Inductor
Value Calculation section, the target sense resistor value is:
RSENSE(EQUIV) =
VSENSE(MAX)
ΔI
IMAX + L
2
To ensure that the application will deliver full load current
over the full operating temperature range, be sure to pick
the optimum ILIMIT value accounting for tolerance in the
DCR versus the MFR_IOUT_CAL_GAIN parameter entered.
Next, determine the DCR of the inductor. Use the manufacturer’s maximum value, which is usually specified at 20°C.
Increase this value to account for tolerances in the temperature sensing element of 3°C to 5°C and any additional
temperature differences associated with the proximity of
the temperature sensor element to the inductor.
power loss when deciding whether to use DCR sensing or
sense resistors. Light load power loss can be modestly
higher with a DCR network than with a sense resistor
due to the extra switching losses incurred through R1.
However, DCR sensing eliminates a sense resistor, reducing conduction losses and provides higher efficiency at
heavy loads. Peak efficiency is about the same with either
method. Selecting discontinuous mode will improve the
converter efficiency at light loads regardless of the current
sensing method.
To maintain a good signal-to-noise ratio for the current
sense signal, use a minimum ∆VISENSE of 10mV to 15mV.
For a DCR sensing application, the actual ripple voltage
will be determined by the equation:
ΔVISENSE =
VIN – VOUT
V
• OUT
R1•C1
VIN • fOSC
SLOPE COMPENSATION AND INDUCTOR PEAK
CURRENT
C1 is usually selected to be in the range of 0.047µF to
4.7µF. This forces (R1 + R3)||R2 to be approximately 2k.
Adding optional elements R3 and C2 shown in Figure 18a
will minimize offset errors associated with the ISENSE leakage currents. Set R3 equal to the value of R1. Set C2 to a
value of 1µF or greater to ensure adequate noise filtering.
Slope compensation provides stability in constant frequency current mode architectures by preventing subharmonic oscillations at high duty cycles. This is accomplished internally by adding a compensation ramp to the
inductor current signal at duty cycles in excess of 35%.
The LTC3886 uses a patented current limit technique that
cancels the effect of the compensating ramp. This allows
the maximum inductor peak current to remain unaffected
throughout all duty cycles.
The equivalent resistance (R1 + R3)||R2 is scaled to the
room temperature inductance and maximum DCR:
INDUCTOR VALUE CALCULATION
(R1+R3) ||R2 =
2 •L
(DCR at 20°C) •C1
The maximum power loss in R1 is related to the duty
cycle, and will occur in continuous mode at the maximum
input voltage:
PLOSS R1=
( VIN(MAX) – VOUT ) • VOUT
R1
Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
44
Given the desired input and output voltages, the inductor
value and operating frequency, fOSC, directly determine
the inductor peak-to-peak ripple current:
V
( VIN – VOUT )
IRIPPLE = OUT
VIN • fOSC • L
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors, and output voltage
ripple. Thus, highest efficiency operation is obtained at the
lowest frequency with a small ripple current. Achieving
this, however, requires a large inductor.
Rev G
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LTC3886/LTC3886-1
APPLICATIONS INFORMATION
A reasonable starting point is to choose a ripple current
that is about 40% of IOUT(MAX). Note that the largest ripple
current occurs at the highest input voltage. To guarantee
that the ripple current does not exceed a specified maximum, the inductor should be chosen according to:
L≥
VOUT ( VIN – VOUT )
VIN • fOSC •IRIPPLE
INDUCTOR CORE SELECTION
Once the inductor value is determined, the type of inductor must be selected. Core loss is independent of core
size for a fixed inductor value, but it is very dependent
on inductance. As the inductance increases, core losses
go down. Unfortunately, increased inductance requires
more turns of wire and therefore copper losses increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite
core materials saturate hard, which means that the inductance collapse abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
voltage and maximum output current. Miller capacitance,
CMILLER, can be approximated from the gate charge curve
usually provided on the MOSFET manufacturers’ data
sheet. CMILLER is equal to the increase in gate charge
along the horizontal axis while the curve is approximately
flat divided by the specified change in VDS. This result is
then multiplied by the ratio of the application applied VDS
to the gate charge curve specified VDS. When the IC is
operating in continuous mode the duty cycles for the top
and bottom MOSFETs are given by:
V
Main Switch Duty Cycle = OUT
VIN
V –V
Synchronous Switch Duty Cycle = IN OUT
VIN
The MOSFET power dissipations at maximum output current are given by:
PMAIN =
⎞
( VIN )2 ⎛⎜⎝ IMAX
)•
⎟ (R ) (C
2 ⎠ DR MILLER
⎡
1 ⎤
1
+
⎢
⎥ • fOSC
⎢⎣ VINTVCC – VTH(MIN) VTH(MIN) ⎥⎦
POWER MOSFET AND OPTIONAL SCHOTTKY DIODE
SELECTION
Two external power MOSFETs must be selected for each
output channel in the LTC3886: one N-channel MOSFET
for the top (main) switch, and one N-channel MOSFET for
the bottom (synchronous) switch.
The peak-to-peak gate drive levels are set by the INTVCC
voltage. This voltage is typically 5V. Consequently, logiclevel threshold MOSFETs must be used in most applications. The only exception is if low input voltage is expected
(VIN < 5V); then, sub-logic level threshold MOSFETs
(VGS(TH) < 3V) should be used. Pay close attention to the
BVDSS specification for the MOSFETs as well; most of the
logic-level MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the
on-resistance, RDS(ON) , Miller capacitance, CMILLER, input
VOUT
2
IMAX ) (1+ δ )RDS(ON) +
(
VIN
PSYNC =
VIN – VOUT
2
IMAX ) (1+ δ )RDS(ON)
(
VIN
wheredis the temperature dependency of RDS(ON) and
RDR (approximately 2Ω) is the effective driver resistance
at the MOSFET’s Miller threshold voltage. VTH(MIN) is the
typical MOSFET minimum threshold voltage.
Both MOSFETs have I2R losses while the topside N-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For VIN < 20V
the high current efficiency generally improves with larger
MOSFETs, while for VIN > 20V the transition losses rapidly increase to the point that the use of a higher RDS(ON)
device with lower CMILLER actually provides higher efficiency. The synchronous MOSFET losses are greatest at
high input voltage when the top switch duty factor is low
Rev G
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45
LTC3886/LTC3886-1
APPLICATIONS INFORMATION
or during a short-circuit when the synchronous switch is
on close to 100% of the period.
The term (1 +d) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs Temperature curve,
butd= 0.005/°C can be used as an approximation for low
voltage MOSFETs.
The optional Schottky diodes connected from ground to
SWn conduct during the dead time between the conduction of the two power MOSFETs. These prevent the body
diodes of the bottom MOSFETs from turning on, storing
charge during the dead time and requiring a reverse recovery period that could cost as much as 3% in efficiency at
high VIN. A 1A to 3A Schottky is generally a good compromise for both regions of operation due to the relatively
small average current. Larger diodes result in additional
transition losses due to their larger junction capacitance.
CIN AND COUT SELECTION
In continuous mode, the source current of the top MOSFET
is a square wave of duty cycle (VOUT)/(VIN). To prevent
large voltage transients, a low ESR capacitor sized for the
maximum RMS current of one channel must be used. The
maximum RMS capacitor current is given by:
CIN Required IRMS ≈
1/2
IMAX
⎡⎣( VOUT ) ( VIN – VOUT ) ⎤⎦
VIN
This formula has a maximum at VIN = 2 • VOUT, where
IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations
do not offer much relief. Note that capacitor manufacturers’ ripple current ratings are often based on only 2000
hours of life. This makes it advisable to further derate
the capacitor, or to choose a capacitor rated at a higher
temperature than required. Several capacitors may be paralleled to meet size or height requirements in the design.
Due to the high operating frequency of the LTC3886,
ceramic capacitors can also be used for CIN. Always consult the manufacturer if there is any question.
The benefit of using a LTC3886 in 2-phase operation can
be calculated by using the equation above for the higher
power channel and then calculating the loss that would
have resulted if both controller channels switched on at
46
the same time. The total RMS power lost is lower when
both channels are operating due to the reduced overlap
of current pulses required through the input capacitor’s
ESR. This is why the input capacitor’s requirement calculated above for the worst-case scenario is adequate for
the dual controller design. Also, if applicable the power
losses due to the input protection fuse resistance, VIN
source impedance, and PC board trace resistance losses
are also reduced due to the reduced peak currents in
a 2-phase system. The overall benefit of a multiphase
design will only be fully realized when the source impedance of the VIN power supply/battery is included in the
efficiency testing. The drain terminals of the top MOSFETs
should be placed within 1cm of each other and share a
common CIN(s). Separating the sources and CIN may produce undesirable voltage and current resonances on VIN.
A small (0.1µF to 1µF) bypass capacitor between the chip
VIN pin and ground, placed close to the LTC3886, is also
suggested. A 2.2Ω to 10Ω RVIN resistor placed between
CIN (C1) and the VIN pin provides further isolation if multiple LTC3886s are used.
The selection of COUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement
is satisfied, the capacitance is adequate for filtering. The
output ripple (∆VOUT) is approximated by:
⎛
1 ⎞
ΔVOUT ≈IRIPPLE ⎜ ESR+
8fCOUT ⎟⎠
⎝
where f is the operating frequency, COUT is the output
capacitance and IRIPPLE is the ripple current in the
inductor. The output ripple is highest at maximum input
voltage since IRIPPLE increases with input voltage.
VARIABLE DELAY TIME, SOFT-START AND OUTPUT
VOLTAGE RAMPING
The LTC3886 must enter the run state prior to soft-start.
The RUNn pin is released after the part initializes and VIN is
greater than the VIN_ON threshold. If multiple LTC3886s
are used in an application, they should be configured to
share the same RUNn pins. They all hold their respective
RUNn pins low until all devices initialize and VIN exceeds
the VIN_ON threshold for all devices. The SHARE_CLK
Rev G
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LTC3886/LTC3886-1
APPLICATIONS INFORMATION
pin assures all the devices connected to the signal use
the same time base for time delay operations.
After the RUNn pin releases, the controller waits for the
user-specified turn-on delay (TON_DELAY) prior to initiating an output voltage ramp. Multiple LTC3886s and
other ADI parts can be configured to start with equal or
unique delay times. To work within a desired synchronization scheme all devices must use the same timing clock
(SHARE_CLK) and all devices must share the RUNn pin.
This allows the relative delay of all parts to be synchronized. The actual variation in the delays will be dependent
on the highest clock rate of the devices connected to the
SHARE_CLK pin (all Analog Devices ICs are configured to
allow the fastest SHARE_CLK signal to control the timing
of all devices). The SHARE_CLK signal can be ±10% in
frequency, thus the actual time delays will have proportional variance.
Soft-start is performed by actively regulating the load voltage while digitally ramping the target voltage from 0.0V
to the commanded voltage set point. The rise time of the
voltage ramp can be programmed using the TON_RISE
command to minimize inrush currents associated with the
start-up voltage ramp. The soft-start feature is disabled
by setting TON_RISE to any value less than 0.250ms. The
LTC3886 will perform the necessary math to assure the
voltage ramp is controlled to the desired slope. However,
the voltage slope can not be any faster than the fundamental limits of the power stage. The shorter TON_RISE
time is set, the larger the discrete steps in the TON_RISE
ramp will appear. The number of steps in the ramp is equal
to TON_RISE/0.1ms.
The LTC3886 PWM will always use discontinuous mode
during the TON_RISE operation. In discontinuous mode,
the bottom gate is turned off as soon as reverse current
is detected in the inductor. This will allow the regulator to
start up into a pre-biased load.
The LTC3886 does not include a traditional tracking feature. However, two outputs can be given the same TON_
RISE and TON_DELAY times to effectively ramp up at the
same time. If the RUN pin is released at the same time and
both LTC3886s use the same time base, the outputs will
track very closely. If the circuit is in a PolyPhase configuration, all timing parameters for that rail must be the same.
The previously described method of start-up sequencing
is time based. For concatenated events it is possible to
control the RUNn pins based on the FAULTn pin of a different controller, or the PGOODn pin(s) of the LTC3886. The
FAULTn pins can be configured to release when the output
voltage of the converter is greater than the VOUT_UV_
FAULT_LIMIT. It is recommended to use the deglitched
VOUT UV fault limit because there is little appreciable time
delay between the converter crossing the UV threshold
and the FAULTn pin releasing. The deglitched output can
be enabled by setting the Mfr_FAULT_propagate_vout_
uvuf bit in the MFR_FAULT_PROPAGATE_LTC3886 command. Refer to the MFR section of the PMBus commands
in this document. The UV comparator output signal may
have some glitching as the VOUT signal transitions through
the comparator threshold. The LTC3886 includes a 70µs
digital deglitch filter to greatly reduce the probability of
multiple transitions. To minimize the risk of FAULTn pins
glitching, make the TON_RISE times less than 100ms.
If unwanted transitions still occur on FAULTn, place a
capacitor to ground on the FAULTn pin to filter the waveform. The RC time-constant of the filter should be set
sufficiently fast to assure no appreciable delay is incurred.
A delay of 300µs to 500µs will provide some additional
filtering without significantly delaying the trigger event.
DIGITAL SERVO MODE
For maximum accuracy in the regulated output voltage,
enable the digital servo loop by asserting bit 6 of the
MFR_PWM_MODE_LTC3886 command. In digital servo
mode the LTC3886 will adjust the regulated output voltage based on the ADC voltage reading. Every 90ms the
digital servo loop will step the LSB of the DAC (nominally
4mV or 2mV depending on the voltage range bit) until
the output is at the correct ADC reading. At power-up this
mode engages after TON_MAX_FAULT_LIMIT unless the
limit is set to 0 (infinite). If the TON_MAX_FAULT_LIMIT
is set to 0 (infinite), the servo begins after TON_RISE
is complete and VOUT has exceeded the VOUT_UV_
FAULT_LIMIT. This same point in time is when the output
changes from discontinuous to the programmed mode as
indicated in MFR_PWM_MODE_LTC3886 bit 0. Refer to
Figure 28 for details on the VOUT waveform under timebased sequencing.
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LTC3886/LTC3886-1
APPLICATIONS INFORMATION
RUN
TON_MAX_FAULT_LIMIT
DIGITAL SERVO
MODE ENABLED FINAL OUTPUT
VOLTAGE REACHED
RUN
VOUT
DISCHARGE OF A LARGE VOUT BYPASS
CAPACITOR DUE TO THE REVERSE
CURRENT LIMIT OF THE POWER STAGE
VOUT_UV_FAULT_LIMIT
DAC VOLTAGE
ERROR (NOT
TO SCALE)
VOUT
TIME DELAY OF
200ms TO 400ms
LTC3886-1 PWM ACTIVE WHILE
WAITING FOR ADC TO DETECT
VOUT < MFR_VOFF_THRESHOLD
2 ADC MEASUREMENTS
REQUIRED. 90ms TO 300ms
STANDARD PMBus
TOFF_FALL ALGORITHM
LTC3886
LTC3886-1
TON_DELAY
TON_RISE
TIME
3886 F28
TOFF_DELAY
TOFF_FALL
3886 F28
Figure 28. Timing Controlled VOUT Rise
Figure 29. TOFF_DELAY and TOFF_FALL
If the TON_MAX_FAULT_LIMIT is set to a value greater
than 0 and the TON_MAX_FAULT_RESPONSE is set to
ignore (0x00), the servo begins:
commanded off. If the part faults off or FAULTn is pulled
low externally and the part is programmed to respond to
FAULTn, the output will three-state by turning off both the
main and synchronous MOSFETs turned off. The output
will decay as a function of the load rather than exhibiting
a controlled ramp.
1. After the TON_RISE sequence is complete
2. After the TON_MAX_FAULT_LIMIT time is reached.
3. After the VOUT_UV_FAULT_LIMIT has been exceed or
the IOUT_OC_FAULT_LIMIT is not longer active.
If the TON_MAX_FAULT_LIMIT is set to a value greater
than 0 and the TON_MAX_FAULT_RESPONSE is not set
to ignore 0X00, the servo begins:
1. After the TON_RISE sequence is complete;
2. After the TON_MAX_FAULT_LIMIT time has expired
and both VOUT_UV_FAULT and IOUT_OC_FAULT are
not present.
The maximum rise time is limited to 1.3 seconds.
In a PolyPhase application only one phase should have
digital servo mode enabled. This will ensure the phases
servo to the same output regulation point.
SOFT OFF (SEQUENCED OFF)
In addition to a controlled start-up, the LTC3886 also supports controlled turn-off. The TOFF_DELAY and TOFF_
FALL functions are shown in Figure 29. TOFF_FALL is
processed when the RUN pin goes low or if the part is
48
The output voltage will ramp as shown in Figure 29 so
long as the part is in forced continuous mode and the
TOFF_FALL time is slow enough that the power stage can
achieve the desired slope. The TOFF_FALL time can only
be met if the power stage and controller can sink sufficient
current to assure the output is at zero volts by the end of
the fall time interval. If the TOFF_FALL time is set shorter
than the time required to discharge the load capacitance,
the output will not reach the desired zero volt state. At the
end of TOFF_FALL, the controller will cease to sink current
and VOUT will decay at the natural rate determined by the
load impedance. The LTC3886-1 sequence off feature is
enabled by bit[5] of the MFR_CHAN_CONFIG_LTC3886
command. When enabled, the sequence off feature keeps
the power stage on until the output voltage has ramped
below the MFR_VOFF_THRESHOLD value. This allows the
LTC3886-1, in continuous mode, to fully discharge very
large output capacitors regardless if the controller power
stage can sink enough current to meet the TOFF_FALL
time. If the controller is in discontinuous mode, the controller will not pull negative current and the output will be
Rev G
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LTC3886/LTC3886-1
APPLICATIONS INFORMATION
pulled low by the load, not the power stage. The maximum
fall time is limited to 1.3 seconds. The shorter TOFF_FALL
time is set, the larger the discrete steps of the TOFF_FALL
ramp will appear. The number of steps in the ramp is typically TOFF_FALL/0.1ms.
power INTVCC, the EXTVCC pin must be tied to GND, do
not float this pin. The VIN current resulting from the gate
driver and control circuitry will be reduced to a minimum
by supplying the INTVCC current from the EXTVCC pin with
an external supply or an output derived source.
INTVCC REGULATOR
Tying the EXTVCC pin to a 5V supply reduces the junction
temperature in the previous example from 125°C to:
The LTC3886 features a PMOS linear regulator that supplies power to INTVCC from the VIN or EXTVCC supply.
INTVCC powers the gate drivers, VDD33 and much of the
LTC3886 internal circuitry. The linear regulator produces
5V at the INTVCC pin when VIN or EXTVCC is greater than
approximately 5.5V. The regulator can supply a peak current of 100mA and must be bypassed to ground with a
minimum of 1µF ceramic capacitor or low ESR electrolytic
capacitor. No matter what type of bulk capacitor is used,
an additional 0.1µF ceramic capacitor placed directly adjacent to the INTVCC and GND pins is highly recommended.
Good bypassing is needed to supply the high transient
currents required by the MOSFET gate drivers.
High input voltage application in which large MOSFETs
are being driven at high frequencies may cause the
maximum die junction temperature rating for the
LTC3886 to be exceeded. To reduce die temperature,
the INTVCC current, of which a large percentage is due
to the gate charge current, may be supplied from either
the VIN or EXTVCC pin. If the LTC3886 internal regulator is powered from the VIN pin, the power through the
IC is equal to VIN • IINTVCC. The gate charge current is
dependent on operating frequency as discussed in the
Efficiency Considerations section. The junction temperature can be estimated by using the equations in Note 2
of the Electrical Characteristics. For example, at 70°C
ambient, the LTC3886 INTVCC current is limited to less
than 44mA from a 40V supply:
TJ = 70°C + 44mA • 5V • 31°C/W + 2mA • 40V • 31°C/W
= 80°C
Do not tie INTVCC on the LTC3886 to an external supply
because INTVCC will attempt to pull the external supply
high and hit current limit, significantly increasing the
die temperature.
Applying voltages below –0.3V to the EXTVCC pin may
result in permanent damage to the device. If the EXTVCC
pin is tied to an output of the controller and the external
load can pull the output below –0.3V, a Schottky diode
from GND to EXTVCC must be used to protect the EXTVCC
pin.
For applications where VIN is 5V, tie the VIN and INTVCC
pins together and tie the combined pins to the 5V input
with a 1Ω or 2.2Ω resistor as shown in Figure 30. To
minimize the voltage drop caused by the gate charge current a low ESR capacitor must be connected to the VIN/
INTVCC pins. This configuration will override the INTVCC
linear regulator and will prevent INTVCC from dropping
too low. Make sure the INTVCC voltage exceeds the RDS(ON)
test voltage for the MOSFETs which is typically 4.5V for
logic level devices. The UVLO on INTVCC is set to approximately 4V.
TJ = 70°C + 44mA • 40V • 31°C/W = 125°C
To prevent the maximum junction temperature from being
exceeded, the LTC3886 internal LDO can be can powered
from the EXTVCC pin. If the EXTVCC pin is not used to
VIN
LTC3886
INTVCC
RVIN
1Ω
CINTVCC
4.7µF
+
5V
CIN
3886 F30
Figure 30. Setup for a 5V Input
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49
LTC3886/LTC3886-1
APPLICATIONS INFORMATION
TOPSIDE MOSFET DRIVER SUPPLY (CB, DB)
External bootstrap capacitors, CB, connected to the
BOOSTn pin supplies the gate drive voltages for the topside
MOSFETs. Capacitor CB in the Block Diagram is charged
though external diode DB from INTVCC when the SWn
pin is low. When one of the topside MOSFETs is to be
turned on, the driver places the CB voltage across the
gate source of the desired MOSFET. This enhances the
MOSFET and turns on the topside switch. The switch node
voltage, SWn, rises to VIN and the BOOSTn pin follows.
With the topside MOSFET on, the boost voltage is above
the input supply: VBOOST = VIN + VINTVCC. The value of the
boost capacitor CB needs to be 100 times that of the total
input capacitance of the topside MOSFET(s). The reverse
breakdown of the external Schottky diode must be greater
than VIN(MAX).
PWM jitter has been observed in some designs operating
at higher VIN/VOUT ratios. This jitter does not substantially
affect the circuit accuracy. Referring to Figure 31, PWM
jitter can be removed by inserting a series resistor with a
value of 1Ω to 5Ω between the cathode of the diode and
the BOOSTn pin.
VIN
1Ω TO 5Ω
BOOST
TGATE
VIN
CB
0.2µF
DB
LTC3886
exceeded before the power sequencing can begin. When
VIN drops below the VIN_OFF threshold, the SHARE_CLK
pin will be pulled low and VIN must increase above the
VIN_ON threshold before the controller will restart. The
normal start-up sequence will be allowed after the VIN_
ON threshold is crossed. If FAULTn is held low when VIN
is applied, ALERT will be asserted low even if the part is
programmed to not assert ALERT when FAULTn is held
low. If I2C communication occurs before the LTC3886 is
out of reset and only a portion of the command is seen by
the part, this can be interpreted as a CML fault. If a CML
fault is detected, ALERT is asserted low.
It is possible to program the contents of the EEPROM in
the application if the VDD33 supply is externally driven.
This will activate the digital portion of the LTC3886 without engaging the high voltage sections. PMBus communications are valid in this supply configuration. If VIN
has not been applied to the LTC3886, bit 3 (EEPROM
Not Initialized)in MFR_COMMON will be asserted low. If
this condition is detected, the part will only respond to
addresses 5A and 5B. To initialize the part issue the following set of commands: global address 0x5B command
0xBD data 0x2B followed by global address 5B command
0xBD and data 0xC4. The part will now respond to the
correct address. Configure the part as desired then issue
a STORE_USER_ALL. When VIN is applied a MFR_RESET
command must be issued to allow the PWM to be enabled
and valid ADC conversions to be read.
SW
INTVCC
BGATE
CINTVCC
10µF
FAULT INDICATIONS
GND
3886 F31
Figure 31. Boost Circuit to Minimize PWM Jitter
UNDERVOLTAGE LOCKOUT
The LTC3886 is initialized by an internal threshold-based
UVLO where VIN must be approximately 4V and INTVCC,
VDD33, VDD25 must be within approximately 20% of
the regulated values. In addition, VDD33 must be within
approximately 7% of the targeted value before the RUN
pin is released. After the part has initialized, an additional
comparator monitors VIN. The VIN_ON threshold must be
50
The LTC3886 FAULTn pins are configurable to indicate a
variety of faults including OV, UV, OC, OT, timing faults,
peak overcurrent faults. In addition the FAULTn pins can
be pulled low by external sources indicating a fault in
some other portion of the system. The fault response is
configurable and allows the following options:
n
Ignore
n
Shut Down Immediately—Latch Off
n
Shut Down Immediately—Retry Indefinitely at the
Time Interval Specified in MFR_RETRY_DELAY
Refer to the PMBus section of the data sheet and the PMBus
specification for more details regarding fault responses.
Rev G
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LTC3886/LTC3886-1
APPLICATIONS INFORMATION
The OV response is always automatic. If an OV condition
is detected, TGn goes low and BGn is asserted.
oscillator is set for 500kHz and the load is 100pF and a
3x time constant is required, the resistor calculation is
as follows:
OPEN-DRAIN PINS
R PULLUP =
2µs – 500ns
= 5k
The LTC3886 has the following open-drain pins:
3.3V Pins
1. FAULTn
2. SYNC
3. SHARE_CLK
4. PGOODn
5V Pins (5V pins operate correctly when pulled to
3.3V.)
1. RUNn
2. ALERT
3. SCL
4. SDA
If timing errors are occurring or if the SYNC frequency is
not as fast as desired, monitor the waveform and determine if the RC time constant is too long for the application. If possible reduce the parasitic capacitance. If not
reduce the pull up resistor sufficiently to assure proper
timing. The SHARE_CLK pull-up resistor has a similar
equation with a period of 10μs and a pull-down time of
1µs. The RC time constant should be approximately 3µs
or faster.
All the above pins have on-chip pull-down transistors that
can sink 3mA at 0.4V. Unless there are transient speed
issues associated with the RC time constant of the resistor pull-up and parasitic capacitance to ground, a 10k
resistor or larger is generally recommended.
For high speed signals such as the SDA, SCL and SYNC,
a lower value resistor may be required. The RC time constant should be set to 1/3 to 1/5 the required rise time
to avoid timing issues. For a 100pF load and a 400kHz
PMBus communication rate, the rise time must be less
than 300ns. The resistor pull-up on the SDA and SCL pins
with the time constant set to 1/3 the rise time:
R PULLUP =
t RISE
3 • 100pF
= 1k
Minimize parasitic capacitance on the SDA and SCL pins
to avoid communication problems. To estimate the loading capacitance, monitor the signal in question and measure how long it takes for the desired signal to reach
approximately 63% of the output value. This is one
time constant.
The SYNC pin has an on-chip pull-down transistor with
the output held low for nominally 500ns. If the internal
3 • 100pF
PHASE-LOCKED LOOP AND FREQUENCY
SYNCHRONIZATION
The LTC3886 has a phase-locked loop (PLL) comprised
of an internal voltage-controlled oscillator (VCO) and a
phase detector. The PLL is locked to the falling edge of
the SYNC pin. The phase relationship between the PWM
controller and the falling edge of SYNC is controlled by the
lower 3 bits of the MFR_PWM_CONFIG_LTC3886 command. For PolyPhase applications, it is recommended all
the phases be spaced evenly. Thus for a 2-phase system
the signals should be 180° out of phase and a 4-phase
system should be spaced 90°.
The phase detector is an edge-sensitive digital type that
provides a known phase shift between the external and
internal oscillators. This type of phase detector does not
exhibit false lock to harmonics of the external clock.
The output of the phase detector is a pair of complementary current sources that charge or discharge the internal
filter network. The PLL lock range is guaranteed between
100kHz and 750kHz. Nominal parts will have a range
beyond this; however, operation to a wider frequency
range is not guaranteed.
The PLL has a lock detection circuit. If the PLL should
lose lock during operation, bit 4 of the STATUS_MFR_
SPECIFIC command is asserted and the ALERT pin is
pulled low. The fault can be cleared by writing a 1 to the
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51
LTC3886/LTC3886-1
APPLICATIONS INFORMATION
bit. If the user does not want the ALERT pin to assert if
a PLL_FAULT occurs, the SMBALERT_MASK command
can be used to prevent the alert.
If there is no external signal applied to the SYNC pin in
the application, the nominal programmed frequency will
control the PWM circuitry. If FREQUENCY_SWITCH is
programmed to external oscillator, and no external SYNC
signal is present, the LTC3886 PWM engine will run at the
lowest free running frequency of the PLL oscillator. This
may result in excess inductor current and undesirable
operation. If multiple parts share the SYNC signal and
the external SYNC signal is not present, the parts will not
be synchronized and excess voltage ripple on the output
may be present.
Multiple LTC3886s are required to share one SYNC signal in PolyPhase configurations, for other configurations connecting the SYNC pins to form a single SYNC
signal is optional. If the SYNC pin is shared between
LTC3886s, only one LTC3886 should be programmed
with a frequency output. All the other LTC3886s should
be programmed to disable their SYNC output. However
their frequency should be programmed to the nominal
desired value. If the LTC3886 is programmed with a frequency output, and an external signal is present. Bit 10 of
MFR_PADS will be asserted low if this condition exists.
If the PWM signal appears to be running at too high a
frequency, monitor the SYNC pin. Extra transitions on
the falling edge will result in the PLL trying to lock on to
noise versus the intended signal. Review routing of digital
control signals and minimize crosstalk to the SYNC signal
to avoid this problem.
MINIMUM ON-TIME CONSIDERATIONS
Minimum on-time, tON(MIN), is the smallest time duration
that the LTC3886 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn off the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
t ON(MIN) <
52
VOUT
VIN • fOSC
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The minimum on-time for the LTC3886 is approximately
90ns. Good PCB layout, minimum 30% inductor current
ripple and at least 10mV to 15mV ripple on the current
sense signal are required to avoid increasing the minimum on-time. The minimum on-time can be affected by
PCB switching noise in the voltage and current loop. As
the peak current sense voltage decreases, the minimum
on-time gradually increases to 130ns. This is of particular concern in forced continuous applications with low
ripple current at light loads. If the duty cycle drops below
the minimum on-time limit in this situation, a significant
amount of cycle skipping can occur with correspondingly
larger current and voltage ripple.
EXTERNAL TEMPERATURE SENSE
The LTC3886 is capable of measuring the temperature of
the power stage temperature of each channel. Multiple
methods using silicon junction remote sensors are supported. The voltage produced by the remote sense circuit is digitized by the internal ADC, and the computed
temperature value is returned by the paged READ_
TEMPERATURE_1 telemetry command.
The most accurate external temperature measurement
can be made using a diode-connected PNP transistor
such as the MMBT3906 as shown in Figure 32. Bit 5 of
MFR_PWM_MODE_LTC3886 should be set to 0 (ΔVBE
method) when using this sensor configuration. The transistor should be placed in contact with or immediately
adjacent to the power stage inductor. Its emitter should
be connected to the TSNSn pin while the base and collector terminals of the PNP transistor must be connected
and returned directly to Pin 53 of the LTC3886 using a
Kelvin connection. For best noise immunity, the connections should be routed differentially and a 10nF capacitor
should be placed in parallel with the diode-connected PNP.
Parasitic PCB trace inductance between the capacitor and
transistor should be minimized. Avoid placing PCB vias
between the transistor and capacitor.
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LTC3886/LTC3886-1
APPLICATIONS INFORMATION
If an external temperature sense element is not used, the
TSNSn pin must be shorted to GND. The UT_FAULT_
LIMIT must be set to –275°C, the UT_FAULT_RESPONSE
must be set to ignore, and the IOUT_CAL_GAIN_TC to a
value of 0.
TSNS
LTC3886
10nF
GND
MMBT3906
GND
3886 F32
Figure 32. External ΔVBE Temperature Sense
495µA
TSNS
LTC3886
GND
GND
1nF
1.35V AT 25°C
3886 F33
Figure 33. 2D+R Temperature Sense
The LTC3886 also supports direct junction voltage measurements when bit 5 of MFR_PWM_MODE_LTC3886 is
set to one. The factory defaults support a resistor-trimmed
dual diode network as shown in Figure 33. This second
measurement method is not generally as accurate as the
first, but it supports legacy power blocks or may prove
necessary if high noise environments prevent use of the
∆VBE approach with its lower signal levels.
For either method, the slope of the external temperature sensor can be modified with the coefficient stored
in MFR_TEMP_1_GAIN. With the ∆VBE approach, typical PNPs require temperature slope adjustments slightly
less than 1. The MMBT3906 has a recommended value
of approximately MFR_TEMP_1_GAIN = 0.991 based
on the ideality factor of 1.01. Simply invert the ideality factor to calculate the MFR_TEMP_1_GAIN. Different
manufacturers and different lots may have different ideality factors. Consult with the manufacturer to set this
value. Characterization over temperature of a prototype
or prototypes is recommended before selecting a final
MFR_TEMP_1_GAIN value when using the direct p-n
junction measurement method.
The offset of the external temperature sense can be
adjusted using MFR_TEMP_1_OFFSET.
To ensure proper use of these temperature adjustment
parameters, refer to the specific formulas given for the
two methods in the MFR_PWM_MODE_LTC3886 command section.
Derating EEPROM Retention at Temperature
EEPROM read operations between –40°C and 125°C will
not affect data storage. But retention will be degraded if
the EEPROM is written above 85°C or stored or operated
above 125°C. If an occasional fault log is generated above
85°C, the slight reduction in data retention in the EEPROM
fault log area will not affect the use of the function or other
EEPROM storage. See the Operation section for other high
temperature EEPROM functional details. Degradation in
data can be approximated by calculating the dimensionless acceleration factor using the following equation.
⎡⎛ Ea ⎞ ⎛
⎞⎤
1
1
–
⎥
⎢⎜⎝ ⎟⎠ •⎜
k ⎝ TUSE +273 TSTRESS +273 ⎟⎠ ⎦
AF = e ⎣
where:
AF = acceleration factor
Ea = activation energy = 1.4eV
k = 8.617 • 10–5 eV/°K
TUSE = is the specified junction temperature
TSTRESS = actual junction temperature in °C
As an example, if the device is stored at 130°C for 10
hours,
TSTRESS = 130°C, and
1 ⎞⎤
1.4
⎡⎛
⎞ ⎛ 1
⎢⎜⎝ 8.617•10 –5 ⎟⎠ •⎜⎝ 398 – 403 ⎟⎠ ⎥
⎦
AF = e ⎣
= 1.66
indicating the effect is the same as operating the device at
125°C for 10 • 1.66 = 16.6 hours, resulting in a retention
derating of 6.6 hours.
Rev G
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53
LTC3886/LTC3886-1
APPLICATIONS INFORMATION
INPUT CURRENT SENSE AMPLIFIER
The LTC3886 input current sense amplifier can sense the
supply current into the VIN pin using an external resistor as well as the power stage current using an external sense resistor. Unless care is taken to mitigate the
frequency noise caused by the discontinuous input
current, significant input current measurement error
may occur. The noise will be the greatest in high current
applications and at large step-down ratios. Careful layout
and filtering at the VIN pin is recommended to minimize
measurement error. The VIN pin should be filtered with
a resistor and a ceramic capacitor. The filter should be
located as close to the VIN pin as possible. The supply
side of the VIN pin filter should be Kelvin connected to the
supply side of the RIINSNS resistor. A 2Ω resistor should
be sufficient for most applications. The resistor will cause
an IR voltage drop from the supply to the VIN pin due to
the current flowing into the VIN pin. To compensate for
this voltage drop, the MFR_RVIN command value should
be set to the nominal resistor value. The LTC3886 will
multiply the MFR_READ_ICHIP measurement value by
the user defined MFR_RVIN value and add this voltage to
the measured voltage at the VIN pin.
EXTERNAL RESISTOR CONFIGURATION PINS
(RCONFIG)
The LTC3886 is factory programmed to use external
resistor configuration. This allows output voltage, PWM
frequency, PWM phasing, and the PMBus address to be
set by the user without programming the part through
the PMBus interface or purchasing custom programmed
parts. To use resistor programming, the RCONFIG pin(s)
require a resistor divider between VDD25 and GND. The
RCONFIG pins are only interrogated at initial power up
and during a reset, so modifying their values on the fly
while the part is powered will have no effect. RCONFIG
pins on the same IC can be shared with a single resistor
divider if they require identical programming. Resistors
with a tolerance of 1% or better must be used to assure
proper operation. In the following tables, RTOP is connected between VDD25 and the RCONFIG pin while RBOT is
connected between the pin and GND. Noisy clock signals
should not be routed near these pins.
VIN
54
TG
M1
IIN-
2Ω
Therefore, the READ_VIN command will return the value
of the voltage at the supply side of the VIN pin filter. If no
VIN filter element is used, set MFR_RVIN = 0.
If the input current sense amplifier is not used, short the
VIN, IIN+ and IIN– and pins together.
10µF
LTC3886
READ_VIN = VVIN_PIN + (MFR_READ_ICHIP • MFR_RVIN)
The capacitor from the drain of the topside MOSFET to
ground should be a low ESR ceramic capacitor. It should
be placed as close as possible to the drain of the topside
MOSFET to supply high frequency transient input current.
This will help prevent noise from the top gate MOSFET
from feeding into the input current sense amplifier inputs
and supply.
RIINSNS
10µF
IIN+
SW
VIN
BG
M2
3886 F34
Figure 34. Low Noise Input Current Sense Circuit
Voltage Selection
When an output voltage is set using the VOUT_CFGn pins
the following parameters are set as a percentage of the
output voltage:
VOUT_OV_FAULT_LIMIT.................................. +10%
n VOUT_OV_WARN_LIMIT..................................+7.5%
n VOUT_MAX.......................................................+7.5%
n VOUT_MARGIN_HIGH.........................................+5%
n VOUT_MARGIN_LOW..........................................–5%
n VOUT_UV_WARN_LIMIT................................. –6.5%
n VOUT_UV_FAULT_LIMIT.................................... –7%
n
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APPLICATIONS INFORMATION
Refer to Table 3 to set the output voltage using the VOUT_
CFGn pins. 1% resistors must be used to assure proper
operation. If VOUT is seven volts or lower, low range is
used. When VOUT is set using the VOUTn_CFG pins, the
part will turn on the rail modifying the OPERATION command, if required, to respond to PMBus commands.
Table 3. VOUT_CFGn
RTOP (kΩ)
RBOTTOM (kΩ)
VOUT (V)
ON/OFF
0 or Open
Open
EEPROM
EEPROM
10
23.2
12.0
ON
10
15.8
8.0
ON
16.2
20.5
7.0
ON
16.2
17.4
6.0
ON
20
17.8
5.0
ON
20
15
3.3
ON
20
12.7
2.5
ON
20
11
1.8
ON
24.9
11.3
1.5
ON
24.9
9.09
1.2
ON
24.9
7.32
1.1
ON
24.9
5.76
1.0
ON
24.9
4.32
0.9
ON
30.1
3.57
0.75
ON
30.1
1.96
0.65
ON
Open
0
EEPROM
OFF
Frequency Selection
The PWM switching frequency is set according to Table 4.
The SYNC pins must be shared in poly-phase configurations where multiple LTC3886s or multiple LTC3886s and
LTC3870s are used to produce the output. If the configuration is not PolyPhase the SYNC pins do not have to be
shared. If the SYNC pins are shared between LTC3886s
only one SYNC pin should be enabled, all other SYNC pins
should be disabled. A pull-up resistor to VDD33 is required
on the SYNC pin.
For example in a 4-phase configuration clocked at 250kHz,
all of the LTC3886s must be set to the desired frequency
and phase and one LTC3886 should be set to the desired
frequency with the SYNC pin disabled. All phasing is with
respect to the falling edge of SYNC.
For LTC3886 chip 1, set the frequency to 250kHz with 90°
and 270° phase shift with the SYNC pin enabled:
Frequency: RTOP = 24.9kΩ and RBOT = 11.3kΩ
Phase: RTOP = 30.1kΩ and RBOT = 1.96kΩ
For LTC3886 chip 2, set the frequency to 250kHz with 0°
and 180° phase shift and the SYNC pin disabled:
Frequency: RTOP = 24.9kΩ and RBOT = 11.3kΩ
Phase: RTOP = 24.9kΩ and RBOT = 11.3kΩ
All configurations in frequency and phase can be achieved
using the FREQ_CFG and PHAS_CFG pins. In the above
application, if the SYNC pin connection is lost from chip 1,
chip 2 will internally detect the frequency as missing and
continue switching at 250kHz. However, because the
SYNC pin is disconnected between the chips, the output
voltage ripple will likely be higher than desired. Bit 10 of
MFR_PADS will assert low on chip 2 indicating chip 2 is
providing its own internal oscillator when it is expecting
an external SYNC input.
Table 4. FREQ_CFG Resistor Programming
RTOP (kΩ)
RBOT (kΩ)
SWITCHING
FREQUENCY (kHz)
0 or Open
Open
EEPROM
10
23.2
EEPROM
10
15.8
750
16.2
20.5
650
16.2
17.4
575
20
17.8
500
20
15
425
20
12.7
350
20
11
300
24.9
11.3
250
24.9
9.09
225
24.9
7.32
200
24.9
5.76
175
24.9
4.32
150
30.1
3.57
125
30.1
1.96
100
Open
0
External SYNC Only
Rev G
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LTC3886/LTC3886-1
APPLICATIONS INFORMATION
Phase Selection
Table 6. ASELn Resistor Programming
The phase of the channels with respect to the falling edge
of SYNC is set using the values in Table 5.
Table 5. PHAS_CFG Resistor Programming
RTOP (kΩ) RBOT (kΩ)
RTOP (kΩ)
RBOT (kΩ)
SYNC TO 0
SYNC TO 1
SYNC
OUTPUT
0 or Open
Open
EEPROM
EEPROM
EEPROM
10
23.2
EEPROM
EEPROM
EEPROM
EEPROM
10
15.8
EEPROM
EEPROM
16.2
20.5
120°
300°
16.2
17.4
60°
240°
20
12.7
120°
240°
20
15
0°
120°
20
12.7
0°
240°
20
11
90°
270°
24.9
11.3
0°
180°
24.9
9.09
120°
300°
24.9
7.32
60°
240°
24.9
5.76
120°
240°
24.9
4.32
0°
120°
30.1
3.57
0°
240°
30.1
1.96
90°
270°
Open
0
0°
180°
DISABLED
ENABLED
ASEL0
LTC3886 DEVICE
ADDRESS BITS[6:4]
LTC3886 DEVICE
ADDRESS BITS[3:0]
BINARY
HEX
EEPROM
BINARY
0 or Open
Open
10
23.2
1111
HEX
EEPROM
F
10
15.8
1110
E
16.2
20.5
1101
D
16.2
17.4
1100
C
20
17.8
1011
B
20
15
1010
A
20
12.7
1001
9
20
11
1000
8
24.9
11.3
111
7
0111
7
24.9
9.09
110
6
0110
6
24.9
7.32
101
5
0101
5
24.9
5.76
100
4
0100
4
24.9
4.32
011
3
0011
3
30.1
3.57
010
2
0010
2
30.1
1.96
001
1
0001
1
Open
0
000
0
0000
0
EFFICIENCY CONSIDERATIONS
Address Selection Using RCONFIG
The LTC3886 address is selected based on the programming of the two configuration pins ASEL0 and ASEL1
according to Table 6. ASEL0 programs the bottom four
bits of the device address for the LTC3886, and ASEL1
programs the three most-significant bits. Either portion of
the address can also be retrieved from the MFR_ADDRESS
value in EEPROM. If both pins are left open, the full 7-bit
MFR_ADDRESS value stored in EEPROM is used to determine the device address. The LTC3886 always responds
to 7-bit global addresses 0x5A and 0x5B. MFR_ADDRESS
should not be set to either of these values because these
are global addresses and all parts will respond to them.
56
ASEL1
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3886 circuits: 1) IC VIN current, 2) INTVCC
regulator current, 3) I2R losses, 4) Topside MOSFET transition losses.
Rev G
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APPLICATIONS INFORMATION
1. The VIN current is the DC supply current given in
the Electrical Characteristics table, which excludes
MOSFET driver and control currents. Supplying the
INTVCC current from the EXTVCC pin with an external
supply will reduce the VIN current required to a
minimum.
2. INTVCC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
from INTVCC to ground. The resulting dQ/dt is a current out of INTVCC that is typically much larger than the
control circuit current. In continuous mode, IGATECHG
= f(QT + QB), where QT and QB are the gate charges of
the topside and bottom side MOSFETs.
3. I2R losses are predicted from the DC resistances of
the fuse (if used), MOSFET, inductor and current sense
resistor. In continuous mode, the average output current
flows through L and RSENSE, but is “chopped” between
the topside MOSFET and the synchronous MOSFET.
If the two MOSFETs have approximately the same
RDS(ON), then the resistance of one MOSFET can simply be summed with the resistances of L and RSENSE to
obtain I2R losses. For example, if each RDS(ON) = 10mΩ,
RL = 10mΩ, RSENSE = 5mΩ, then the total resistance
is 25mΩ. This results in losses ranging from 2% to
8% as the output current increases from 3A to 15A for
a 5V output, or a 3% to 12% loss for a 3.3V output.
Efficiency varies as the inverse square of VOUT for the
same external components and output power level. The
combined effects of increasingly lower output voltages
and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system!
4. Transition losses apply only to the topside MOSFET(s),
and become significant only when operating at high
input voltages (typically 15V or greater). Transition
losses can be estimated from:
Transition Loss = (1.7) VIN2 IO(MAX) CRSS f
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these “system” level losses during
the design phase. The internal battery and fuse resistance
losses can be minimized by making sure that CIN has
adequate charge storage and very low ESR at the switching frequency. A 25W supply will typically require a minimum of 20µF to 40µF of capacitance having a maximum
of 20mΩ to 50mΩ of ESR. The LTC3886 2-phase architecture typically halves this input capacitance requirement over competing solutions. Other losses including
Schottky conduction losses during dead time and inductor core losses generally account for less than 2% total
additional loss.
PROGRAMMABLE LOOP COMPENSATION
The LTC3886 offers programmable loop compensation to
optimize the transient response without any hardware
change. As shown in Figure 35, the error amplifier gain
gm varies from 1.0mmho to 5.73mmho, and the compensation resistor RTH varies from 0kΩ to 62kΩ inside the
controller. Two compensation capacitors, CTH and CTHP,
are required in the design and the typical ratio between
CTH and CTHP is 10.
gm
RTH
ITH_R
ITH
CTH
CTHP
+
VREF
–
FB
3886 F35
Figure 35. Programmable Loop Compensation
Rev G
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57
LTC3886/LTC3886-1
APPLICATIONS INFORMATION
By adjusting the gm and RTH only, the LTC3886 can provide a flexible type II compensation network to optimize
the loop over a wide range of output capacitors. Adjusting
the gm will change the gain of the compensation over the
whole frequency range without moving the pole and zero
location, as shown in Figure 36.
TYPE II COMPENSATION
GAIN
INCREASE gm
FREQUENCY
3886 F36
Figure 36. Error Amp gm Adjust
Adjusting the RTH will change the pole and zero location,
as shown in Figure 37. It is recommended that the user
determines the appropriate value for the gm and RTH using
the LTpowerCAD® tool.
TYPE II COMPENSATION
GAIN
INCREASE RTH
FREQUENCY
Figure 37. RITH Adjust
3886 F37
CHECKING TRANSIENT RESPONSE
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, VOUT shifts by an
58
amount equal to ∆ILOAD (ESR), where ESR is the effective
series resistance of COUT . ∆ILOAD also begins to charge
or discharge COUT generating the feedback error signal
that forces the regulator to adapt to the current change
and return VOUT to its steady-state value. During this
recovery time VOUT can be monitored for excessive overshoot or ringing, which would indicate a stability problem.
The availability of the ITH pin not only allows optimization
of control loop behavior but also provides a DC-coupled
and AC-filtered closed-loop response test point. The
DC step, rise time and settling at this test point truly
reflects the closed-loop response. Assuming a predominantly second order system, phase margin and/or
damping factor can be estimated using the percentage
of overshoot seen at this pin. The bandwidth can also
be estimated by examining the rise time at the pin. The
ITHR external capacitor shown in the Typical Application
circuit will provide an adequate starting point for most
applications. The programmable parameters that affect
loop gain are the voltage range, bit[1] of the MFR_PWM_
CONFIG_LTC3886 command, the current range, bit 7 of
the MFR_PWM_MODE_LTC3886 command, the gm of the
PWM channel amplifier, bits [7:5] of MFR_PWM_COMP,
and the internal RITH compensation resistor, bits[4:0] of
MFR_PWM_COMP. Be sure to establish these settings
prior to compensation calculation.
The ITH series internal RITH - external CC filter sets the
dominant pole-zero loop compensation. The internal RITH
value can be modified (from 0Ω to 62kΩ) using bits[4:0]
of the MFR_PWM_COMP command. Adjust the value of
RITH to optimize transient response once the final PC layout is done and the particular CC filter capacitor and output capacitor type and value have been determined. The
output capacitors need to be selected because the various
types and values determine the loop gain and phase. An
output current pulse of 20% to 80% of full-load current
having a rise time of 1µs to 10µs will produce output
voltage and ITH pin waveforms that will give a sense of
the overall loop stability without breaking the feedback
loop. Placing a power MOSFET with a resistor to ground
directly across the output capacitor and driving the gate
with an appropriate signal generator is a practical way to
Rev G
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APPLICATIONS INFORMATION
produce a load step. The MOSFET + RSERIES will produce
output currents approximately equal to VOUT/RSERIES.
RSERIES values from 0.1Ω to 2Ω are valid depending on
the current limit settings and the programmed output voltage. The initial output voltage step resulting from the step
change in output current may not be within the bandwidth
of the feedback loop, so this signal cannot be used to
determine phase margin. This is why it is better to look
at the ITH pin signal which is in the feedback loop and is
the filtered and compensated control loop response. The
gain of the loop will be increased by increasing RITH and
the bandwidth of the loop will be increased by decreasing CC. If RITH is increased by the same factor that CC
is decreased, the zero frequency will be kept the same,
thereby keeping the phase shift the same in the most
critical frequency range of the feedback loop. The gain
of the loop will be proportional to the transconductance
of the error amplifier which is set using bits[7:5] of the
MFR_PWM_COMP command. The output voltage settling behavior is related to the stability of the closed-loop
system and will demonstrate the actual overall supply
performance.
must be set to the desired switching frequency, and all
other FREQUENCY_SWITCH commands must be set to
External Clock. If an external oscillator is provided, set the
FREQUENCY_SWITCH command to External Clock for all
LTC3886s. The relative phasing of all the channels should
be spaced equally. The MFR_RAIL_ADDRESS of all the
devices should be set to the same value.
A second, more severe transient is caused by switching
in loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT , causing a rapid drop in VOUT . No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
CLOAD to COUT is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited
to approximately 25 • CLOAD . Thus a 10µF capacitor would
require a 250µs rise time, limiting the charging current
to about 200mA.
2. Are signal ground and power ground kept separate?
The ground return of CINTVCC must return to the combined COUT (–) terminals.
PolyPhase CONFIGURATION
When configuring a PolyPhase rail with multiple
LTC3886s, the user must share the SYNC, ITH, SHARE_
CLK, FAULTn, PGOODn and ALERT pins of both parts. Be
sure to use pull-up resistors on FAULTn, PGOODn, SYNC,
SHARE_CLK and ALERT. One of the LTC3886’s SYNC pin
When connecting a PolyPhase rail with LTC3886s, connect the VIN pins of the LTC3886s directly back to the
supply voltage through the VIN pin filter networks.
PC BOARD LAYOUT CHECKLIST
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 38. Figure 39 illustrates the current waveforms present in the various branches of the
synchronous regulator operating in the continuous mode.
Check the following in your layout:
1. Is the top N-channel MOSFET, M1, located within 1cm
of CIN?
3. The ITH trace should be as short as possible.
4. The loop formed by the top N-channel MOSFET,
Schottky diode and the CIN capacitor should have
short leads and PC trace lengths.
5. The output capacitor (–) terminals should be
connected as close as possible to the (–) terminals
of the input capacitor by placing the capacitors next to
each other and away from the Schottky loop described
in item 4.
6. Are the ISENSE+ and ISENSE– leads routed together
with minimum PC trace spacing? The filter capacitor
between ISENSE+ and ISENSE– should be as close as
possible to the IC. Ensure accurate current sensing
with Kelvin connections at the sense resistor or
inductor, whichever is used for current sensing.
Rev G
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59
LTC3886/LTC3886-1
APPLICATIONS INFORMATION
VIN
RIINSNS
IIN–
TSNS
IIN+
Q1
LTC3886
RVIN
C1
ISENSE+
ISENSE–
VIN
CVIN
L
TG
SW
CB
BOOST
SYNC
RUN
VSENSE+
VSENSE–
M1
BG
RSENSE
VOUT
M2
D1
1µF
CERAMIC
ITHR
ITH
INTVCC
VDD25
+
+
CINTVCC
CIN
COUT
+
VDD33
GND
3886 F38
Figure 38. Recommended Printed Circuit Layout Diagram, Single Phase Shown
60
Rev G
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APPLICATIONS INFORMATION
SW1
L1
RSENSE1
D1
VOUT1
COUT1
RL1
VIN
RIN
CIN
SW0
BOLD LINES INDICATE
HIGH SWITCHING
CURRENT. KEEP LINES
TO A MINIMUM LENGTH.
L0
RSENSE0
D0
VOUT0
COUT0
RL0
3886 F39
Figure 39. Branch Current Waveforms
Rev G
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61
LTC3886/LTC3886-1
APPLICATIONS INFORMATION
7. Is the INTVCC decoupling capacitor connected close
to the IC, between the INTVCC and the power ground
pins? This capacitor carries the MOSFET driver
current peaks. An additional 1µF ceramic capacitor
placed immediately next to the INTVCC and GND pins
can help improve noise performance substantially.
8. Keep the switching nodes (SWn), top gate nodes
(TGn), and boost nodes (BOOSTn) away from
sensitive small-signal nodes, especially from the
voltage and current sensing feedback pins. All of
these nodes have very large and fast moving signals
and therefore should be kept on the “output side” of
the LTC3886 and occupy minimum PC trace area. If
DCR sensing is used, place the top resistor (Figure
25a, R1) close to the switching node.
9. Use a modified “star ground” technique: a low impedance, large copper area central grounding point on
the same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTVCC
and EXTVCC decoupling capacitors, the bottom of the
voltage feedback resistive divider and the GND pin of
the IC.
10. Are the IIN+ and IIN– pins Kelvin connected to the
RSENSEIN sense resistor? This will prevent the PCB
trace resistance from causing errors in the input
current measurement. These traces should be as
short as possible and routed away from any noisy
nodes such as the switching or boost nodes.
11. Is the VIN filter Kelvin connected to the input side
of the RSENSEIN resistor? This can help improve
the noise performance of the input current sense
amplifier by reducing the voltage transients between
the amplifier inputs and amplifier supply caused by
the discontinuous power stage current.
62
PC BOARD LAYOUT DEBUGGING
It is helpful to use a DC-50MHz current probe to monitor the current in the inductor while testing the circuit. Monitor the output switching node (SWn pin)
to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well.
Check for proper performance over the operating voltage and current range expected in the application.
The frequency of operation should be maintained over
the input voltage range down to dropout and until the
output load drops below the low current operation
threshold.
The duty cycle percentage should be maintained from
cycle to cycle in a well-designed, low noise PCB implementation. Variation in the duty cycle at a subharmonic
rate can suggest noise pickup at the current or voltage sensing inputs or inadequate loop compensation.
Overcompensation of the loop can be used to tame a
poor PC layout if regulator bandwidth optimization is not
required.
Reduce VIN from its nominal level to verify operation
of the regulator in dropout. Check the operation of the
undervoltage lockout circuit by further lowering VIN
while monitoring the outputs to verify operation.
Investigate whether any problems exist only at higher output currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents, look for capacitive coupling between the BOOSTn,
SWn, TGn, and possibly BGn connections and the sensitive voltage and current pins. The capacitor placed across
the current sensing pins needs to be placed immediately
adjacent to the pins of the IC. This capacitor helps to
minimize the effects of differential noise injection due
to high frequency capacitive coupling. If problems are
encountered with high current output loading at lower
input voltages, look for inductive coupling between CIN,
Schottky and the top MOSFET components to the sensitive current and voltage sensing traces. In addition,
investigate common ground path voltage pickup between
these components and the GND pin of the IC.
Rev G
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APPLICATIONS INFORMATION
10µF
5mΩ
10µF
M1
L0
3.7µH
D1 INTV V I + I –
CC IN IN IN
TG0
0.1µF
TG1
BOOST0
5k
1.61k
10k
4.7µF
10k
10k
VDD33
10k
10k
10k
10k
10k
10k
10k
1.61k
BG0
SYNC
22µF
4×
+
150µF
2×
LTC3886
M4
BG1
4.7µF
6.04k
PGOOD0
PGOOD1
VDD25
SDA
SCL
ALERT
20k
10k
10k
10k
24.9k
12.7k
23.2k
23.2k
23.2k
11.3k
VOUT0_CFG
FAULT0
FAULT1
RUN0
VOUT1_CFG
ASEL0
ASEL1
FREQ_CFG
RUN1
WP
PHAS_CFG
SHARE_CLK
ISENSE0+
ISENSE1+
ISENSE0–
ISENSE1–
6.04k
0.470µF
1µF
12.1k
VOUT1
12V
5A
VSENSE1
EXTVCC
TSNS1
ITH1
ITHR1
V
GND VDD25
4700pF DD33
100pF
L1
10µH
SW1
VSENSE0+
VSENSE0–
TSNS0
ITH0
ITHR0
10nF
M2
0.1µF
0.470µF
VOUT0
3.3V
10A
1µF
VIN
20V TO 48V
BOOST1
SW0
M3
D2
22µF
2Ω
10nF
4700pF
1µF
4.7µF
22µF
4×
+
150µF
2×
100pF
L0: WURTH 7443551370 3.7µH
L1: WURTH 74435561100 10µH
M1, M2: INFINEON BSC039N06NS
M3, M4: INFINEON BSC014N06NS
3886 F40
Figure 40. High Efficiency Dual 250kHz 12V/3.3V Step-Down Converter
DESIGN EXAMPLE
As a design example for a medium current regulator,
assume VIN = 48V nominal, VIN = 55V maximum, VOUT0
= 3.3V, VOUT1 = 12V, IMAX0,1 = 10A and f = 250kHz (see
Figure 40).
The regulated outputs are established by the VOUT_
COMMAND stored in EEPROM or placing the following
resistor divider between VDD25 the VOUTn_CFG pin and
GND:
1. VOUT0_CFG, RTOP = 20k, RBOTTOM = 12.7k
2. VOUT1_CFG, RTOP = 10k, RBOTTOM = 23.2k
Rev G
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LTC3886/LTC3886-1
APPLICATIONS INFORMATION
The frequency and phase are set by EEPROM or by setting
the resistor dividers between VDD25 and GND.
1. FREQ_CFG, RTOP = 24.9k, RBOTTOM = 11.3k
2. PHAS_CFG, RTOP = Open, RBOTTOM = 0
The address is set to XF where X is the MSB stored in
EEPROM.
The following parameters are set as a percentage of the
output voltage if the resistor configuration pins are used
to determined output voltage:
minimum on time occurs on channel 0 at the maximum
VIN, and should not be less than 90ns:
The inductance values are based on a 35% maximum
ripple current assumption (3.5A). The highest value of
ripple current occurs at the maximum input voltage:
L=
⎤
VOUT ⎡
V
⎢1– OUT ⎥
f • ΔIL(MAX) ⎢⎣ VIN(MAX) ⎥⎦
Channel 0 will require 3.5µH and channel 1 will require
10.7µH. The nearest standard values are 3.7µH and 10µH
respectively. At the nominal input the ripple will be:
⎤
⎡
V
V
ΔIL(NOM) = OUT ⎢1– OUT ⎥
f •L ⎢⎣ VIN(NOM) ⎥⎦
Channel 0 will have 3.32A (33%) ripple, and channel 1
will have 3.6A (36%) ripple. The peak inductor current will
be the maximum DC value plus one-half the ripple current or 11.6A for channel 0 and 11.8A for channel 1. The
64
VIN(MAX) • f
=
3.3V
55V ( 250kHz )
= 240ns
The Würth 7443551370 3.7µH (4.9mΩ DCRTYP at 25°C)
channel 0 and the Wurth 744355611000 10µH (7mΩ
DCRTYP at 25°C) channel 1 are the chosen inductors.
VOUT_OV_FAULT_LIMIT...................................+10%
n VOUT_OV_WARN_LIMIT..................................+7.5%
n VOUT_MAX.......................................................+7.5%
n VOUT_MARGIN_HIGH.........................................+5%
n VOUT_MARGIN_LOW..........................................–5%
n VOUT_UV_WARN_LIMIT..................................–6.5%
n VOUT_UV_FAULT_LIMIT.....................................–7%
All other user defined parameters must be programmed
into the EEPROM. The GUI can be utilized to quickly set
up the part with the desired operating parameters.
n
VOUT
t ON(MIN) =
(R1+R3) =
2 •L
2 • 3.7µH
=
(DCR at 25°C) •C1 4.9mΩ • 0.47µF
R1 = R3 = 1.61kΩ.
IOUT _ CAL _ GAIN = 4.9m�
The maximum power loss in R1 is related to the duty
cycle, and will occur in continuous mode at the maximum
input voltage:
PLOSS • R1=
=
( VIN(MAX) – VOUT ) • VOUT
R1
( 55 – 3.3 ) • 3.3
3.05k
= 55.9mW
The respective values for channel 1 are C1 = 0.47µF, R1 =
R3 = 6.08kΩ, R2 = 12.1kΩ, IOUT_CAL_GAIN = 3.45mΩ
and PLOSSR1 = 84.9mW.
The current limit will be set 20% higher than the peak
value to assure variation in components and noise in the
system do not limit the average current.
VILIMIT = IPEAK • RDCR(MAX) = 1.2 •11.3A •3.5mΩ =
47.46mV
The closest VILIMIT setting is 42.9mV or 48.2mV. The values are entered with the IOUT_OC_FAULT_LIMIT command. Based on expected variation and measurement in
the lab across the sense capacitor the user can determine the optimal setting. For channel 1 the VILIMIT value
is 49.56mV. The closest value is 53.6mV.
The power dissipation on the topside MOSFET can be
easily estimated. Choose an INFINEON BSC039N06NS
Rev G
For more information www.analog.com
LTC3886/LTC3886-1
APPLICATIONS INFORMATION
topside MOSFET. RDS(ON) = 3.9mΩ, CMILLER = 75pF.
At maximum input voltage with T estimated = 50°C
and a bottom side INFINEON BSC014N06NS MOSFET,
RDS(ON) = 1.45mΩ:
3.3V
2
PMAIN =
• (11.6 ) • ⎡⎣1+ ( 0.005) ( 50°C – 25°C) ⎤⎦
55V
1 ⎞
⎛ 1
2
•0.0039Ω + ( 55V ) ( 5.8A ) • 2 ⎜
+
⎝ 5 – 2.8 2.8 ⎟⎠
(59pF )(250kHz ) = 0.455W
The loss in the bottom side MOSFET is:
PSYNC =
(55V – 3.3V ) •
(11.6A )2 •
55V
⎡⎣1+ ( 0.005) ( 50°C – 25°C) ⎤⎦ • 0.00145Ω
= 0.206W
Both MOSFETS have I2R losses while the PMAIN equation
includes an additional term for transition losses, which
are highest at high input voltages.
CIN is chosen for an RMS current rating of:
IRMS =
11.8
1/2
⎡⎣( 3.3) • ( 55 – 3.3) ⎤⎦ = 2.8A
55
at temperature. COUT is chosen with an ESR of 0.01Ω for
low output ripple. The output ripple in continuous mode
will be highest at the maximum input voltage. The output
voltage ripple due to ESR is
VORIPPLE = R(∆IL) = 0.01Ω • 3.6A = 36mV.
ADDITIONAL DESIGN CHECKS
Tie FAULT0 and FAULT1 together and pull up to VDD33
with a 10k resistor.
Tie RUN0 and RUN1 together and pull up to VDD33 with
a 10k resistor.
If there are other ADI PSM parts, connect the RUN pins
between chips and connect the FAULT pins between chips.
Be sure all PMBus pins have resistor pull-up to VDD33
and connect these inputs across all ADI PSM parts in
the application.
Tie SHARE_CLK high with a 10k resistor to VDD33 and
share between all ADI PSM parts in the application.
Be sure a unique address for each chip can be decoded
with the ASEL0 and ASEL1 pins. Refer to Table 6.
For maximum flexibility, allow board space for RTOP and
RBOTTOM for any parameter that is set with resistors such
as ASEL0 and ASEL1.
CONNECTING THE USB TO I2C/SMBus/PMBus
ADAPTER TO THE LTC3886 IN SYSTEM
The ADI USB to I2C/SMBus/PMBus adapter (DC1613A or
equivalent) can be interfaced to the LTC3886 on the user’s
board for programming, telemetry and system debug.
The adapter, when used in conjunction with LTpowerPlay,
provides a powerful way to debug an entire power system.
Faults are quickly diagnosed using telemetry, fault status
commands and the fault log. The final configuration can
be quickly developed and stored to the LTC3886 EEPROM.
Figure 41 illustrates the application schematic for powering, programming and communication with one or
more LTC3886s via the ADI I2C/SMBus/PMBus adapter
regardless of whether or not system power is present. If
system power is not present, the adapter will power the
LTC3886 through the VDD33 supply pin. To initialize the
part when VIN is not applied and the VDD33 pin is powered
use global address 0x5B command 0xBD data 0x2B followed by address 0x5B command 0xBD data 0xC4. The
LTC3886 will now communicate normally, and the project
file can be updated. To write the updated project file to the
EEPROM issue a STORE_USER_ALL command. When
VIN is applied, a MFR_RESET must be issued to allow
the PWM to be enabled and valid ADCs to be read.
Because of the adapter’s limited current sourcing capability, only the LTC3886s, their associated pull-up resistors and the I2C pull-up resistors should be powered
Rev G
For more information www.analog.com
65
LTC3886/LTC3886-1
APPLICATIONS INFORMATION
VIN
ADI
CONTROLLER
HEADER
ISOLATED
3.3V
SDA
100k
100k
VIN
VDD33
TP0101K
SCL
1µF
10k
VDD25
1µF
LTC3886
SDA
10k
SCL
WP GND
TO LTC DC1613
USB TO I2C/SMBus/PMBus
CONTROLLER
VIN
TP0101K
VDD33
1µF
VDD25
1µF
LTC3886
SDA
VGS MAX ON THE TP0101K IS 8V IF VIN > 16V
CHANGE THE RESISTOR DIVIDER ON THE PFET GATE
SCL
WP GND
3886 F41
Figure 41. ADI Controller Connection
from the ORed 3.3V supply. In addition any device sharing the I2C bus connections with the LTC3886 should not
have body diodes between the SDA/SCL pins and their
respective VDD node because this will interfere with bus
communication in the absence of system power. If VIN
is applied the DC1613A will not supply power to the
LTC3886s on the board. It is recommended the RUNn
pins be held low or no voltage configuration resistors
inserted to avoid providing power to the load until the
part is fully configured.
The LTC3886 is fully isolated from the host PC’s ground by
the DC1613A. The 3.3V from the adapter and the LTC3886
VDD33 pin must be driven to each LTC3886 with a separate PFET. If VIN is not applied, the VDD33 pins can be in
parallel because the on-chip LDO is off. The DC1613A’s
3.3V current limit is 100mA but typical VDD33 currents
are under 15mA. The VDD33 does back drive the INTVCC/
EXTVCC pins. Normally this is not an issue if VIN is open.
LTpowerPlay: AN INTERACTIVE GUI FOR DIGITAL
POWER
LTpowerPlay is a powerful Windows-based development environment that supports Analog Devices digital
power ICs including the LTC3886. The software supports
66
a variety of different tasks. LTpowerPlay can be used to
evaluate Analog Devices ICs by connecting to a demo
board or the user application. LTpowerPlay can also be
used in an offline mode (with no hardware present) in
order to build multiple IC configuration files that can be
saved and re-loaded at a later time. LTpowerPlay provides
unprecedented diagnostic and debug features. It becomes
a valuable diagnostic tool during board bring-up to program or tweak the power system or to diagnose power
issues when bringing up rails. LTpowerPlay utilizes Analog
Devices’ USB-to-I2C/SMBus/PMBus adapter to communication with one of the many potential targets including
the DC2155A demo board, or a customer target system.
The software also provides an automatic update feature
to keep the revision current with the latest set of device
drivers and documentation. A great deal of context sensitive help is available with LTpowerPlay along with several
tutorial demos. Complete information is available at:
LTpowerPlay
PMBus COMMUNICATION AND COMMAND
PROCESSING
The LTC3886 has a one deep buffer to hold the last data
written for each supported command prior to processing
Rev G
For more information www.analog.com
LTC3886/LTC3886-1
APPLICATIONS INFORMATION
Figure 42. LTpowerPlay Screen Shot
CMD
PMBus
WRITE
WRITE COMMAND
DATA BUFFER
DECODER
CMDS
DATA
MUX
CALCULATIONS
PENDING
S
R
PAGE
•
•
•
VOUT_COMMAND
0x00
0x21
•
•
•
MFR_RESET
INTERNAL
PROCESSOR
FETCH,
CONVERT
DATA
AND
EXECUTE
0xFD
x1
3886 F43
Figure 43. Write Command Data Processing
as shown in Figure 43; Write Command Data Processing.
When the part receives a new command from the bus,
it copies the data into the Write Command Data Buffer,
indicates to the internal processor that this command data
needs to be fetched, and converts the command to its
internal format so that it can be executed.
Two distinct parallel blocks manage command buffering
and command processing (fetch, convert, and execute) to
ensure the last data written to any command is never lost.
Command data buffering handles incoming PMBus writes
by storing the command data to the Write Command Data
Buffer and marking these commands for future processing. The internal processor runs in parallel and handles
the sometimes slower task of fetching, converting and
executing commands marked for processing.
Some computationally intensive commands (e.g., timing
parameters, temperatures, voltages and currents) have
internal processor execution times that may be long
relative to PMBus timing. If the part is busy processing a command, and new command(s) arrive, execution
may be delayed or processed in a different order than
received. The part indicates when internal calculations
Rev G
For more information www.analog.com
67
LTC3886/LTC3886-1
APPLICATIONS INFORMATION
// wait until chip is not busy
do
{
mfrCommonValue = PMBUS_READ_BYTE(0xEF);
partReady = (mfrCommonValue & 0x68) == 0x68;
}while(!partReady)
// now the part is ready to receive the next command
PMBUS_WRITE_WORD(0x21, 0x2000); //write VOUT_COMMAND to 2V
Figure 44. Example of a Command Write of VOUT_COMMAND
are in process via bit 5 of MFR_COMMON (‘calculations not pending’). When the part is busy calculating,
bit 5 is cleared. When this bit is set, the part is ready for
another command. An example polling loop is provided in
Figure 44 which ensures that commands are processed in
order while simplifying error handling routines.
When the part receives a new command while it is busy,
it will communicate this condition using standard PMBus
protocol. Depending on part configuration it may either
NACK the command or return all ones (0xFF) for reads. It
may also generate a BUSY fault and ALERT notification, or
stretch the SCL clock low. Clock stretching can be enabled
by asserting bit 1 of MFR_CONFIG_ALL_LTC3886. Clock
stretching will only occur if enabled and the bus communication speed exceeds 100kHz.
PMBus busy protocols are well accepted standards, but
can make writing system level software somewhat complex. The part provides three ‘hand shaking’ status bits
which reduce complexity while enabling robust system
level communication.
The three hand shaking status bits are in the MFR_
COMMON register. When the part is busy executing an internal operation, it will clear bit 6 of MFR_
COMMON (‘chip not busy’). When the part is busy
specifically because it is in a transitional VOUT state
(margining hi/lo, power off/on, moving to a new output voltage set point, etc.) it will clear bit 4 of MFR_
COMMON (‘output not in transition’). When internal
68
calculations are in process, the part will clear bit 5 of
MFR_COMMON (‘calculations not pending’). These
three status bits can be polled with a PMBus read
byte of the MFR_COMMON register until all three bits
are set. A command immediately following the status
bits being set will be accepted without NACKing or
generating a BUSY fault/ALERT notification. The part
can NACK commands for other reasons, however, as
required by the PMBus spec (for instance, an invalid
command or data). An example of a robust command
write algorithm for the VOUT_COMMAND register is
provided in Figure 44.
It is recommended that all command writes (write byte,
write word, etc. ) be preceded with a polling loop to avoid
the extra complexity of dealing with busy behavior and
unwanted ALERT notification. A simple way to achieve this
is to create a SAFE_WRITE_BYTE() and SAFE_WRITE_
WORD() subroutine. The above polling mechanism allows
your software to remain clean and simple while robustly
communicating with the part. For a detailed discussion
of these topics and other special cases please refer to the
application notes AN135 and AN152.
When communicating using bus speeds at or below
100kHz, the polling mechanism shown here provides a
simple solution that ensures robust communication without clock stretching. At bus speeds in excess of 100kHz,
it is strongly recommended that the part be configured
to enable clock stretching. This requires a PMBus master that supports clock stretching. System software that
detects and properly recovers from the standard PMBus
NACK/BUSY faults is required.
The LTC3886 is not recommended in applications with
bus speeds in excess of 400kHz.
Rev G
For more information www.analog.com
LTC3886/LTC3886-1
PMBus COMMAND DETAILS
ADDRESSING AND WRITE PROTECT
CMD
CODE DESCRIPTION
0x00 Provides integration with multi-page PMBus devices.
0x05 Write a supported command directly to a PWM
channel.
0x06 Read a supported command directly from a PWM
channel.
0x10 Level of protection provided by the device against
accidental changes.
0xE6 Sets the 7-bit I2C address byte.
0xFA Common address for PolyPhase outputs to adjust
common parameters.
COMMAND NAME
PAGE
PAGE_PLUS_WRITE
PAGE_PLUS_READ
WRITE_PROTECT
MFR_ADDRESS
MFR_RAIL_ADDRESS
DATA
DEFAULT
TYPE
PAGED FORMAT UNITS EEPROM VALUE
R/W Byte
N
Reg
0x00
W Block
N
Block
R/W
R/W Byte
N
N
Reg
Y
0x00
R/W Byte
R/W Byte
N
Y
Reg
Reg
Y
Y
0x4F
0x80
PAGE
The PAGE command provides the ability to configure, control and monitor both PWM channels through only one physical address, either the MFR_ADDRESS or GLOBAL device address. Each PAGE contains the operating commands for
one PWM channel.
Pages 0x00 and 0x01 correspond to Channel 0 and Channel 1, respectively, in this device.
Setting PAGE to 0xFF applies any following paged commands to both outputs. Reading from the device with PAGE
set to 0xFF is not recommended.
This command has one data byte.
PAGE_PLUS_WRITE
The PAGE_PLUS_WRITE command provides a way to set the page within a device, send a command, and then send
the data for the command, all in one communication packet. Commands allowed by the present write protection level
may be sent with PAGE_PLUS_WRITE.
The value stored in the PAGE command is not affected by PAGE_PLUS_WRITE. If PAGE_PLUS_WRITE is used to send
a non-paged command, the Page Number byte is ignored.
This command uses Write Block protocol. An example of the PAGE_PLUS_WRITE command with PEC sending a command that has two data bytes is shown in Figure 45.
1
7
S
SLAVE
ADDRESS
1
1
W
PAGE_PLUS
A
A
COMMAND CODE
8
8
LOWER DATA
BYTE
1
8
BLOCK COUNT
(= 4)
1
8
A
PAGE
NUMBER
1
8
1
8
1
A
UPPER DATA
BYTE
A
PEC BYTE
A
1
8
1
A
COMMAND
CODE
A
…
1
P
3886 F45
Figure 45. Example of PAGE_PLUS_WRITE
Rev G
For more information www.analog.com
69
LTC3886/LTC3886-1
PMBus COMMAND DETAILS
PAGE_PLUS_READ
The PAGE_PLUS_READ command provides the ability to set the page within a device, send a command, and then read
the data returned by the command, all in one communication packet .
The value stored in the PAGE command is not affected by PAGE_PLUS_READ. If PAGE_PLUS_READ is used to access
data from a non-paged command, the Page Number byte is ignored.
This command uses Block Write-Block Read Process Call protocol. An example of the PAGE_PLUS_READ command
with PEC is shown in Figure 46.
1
7
S
SLAVE
ADDRESS
1
7
Sr
SLAVE
ADDRESS
1
R
1
1
W
PAGE_PLUS
A
A
COMMAND CODE
8
1
8
A
BLOCK COUNT
(= 2)
1
8
BLOCK COUNT
(= 2)
1
8
A
LOWER DATA
BYTE
1
8
A
PAGE
NUMBER
1
8
1
A
COMMAND
CODE
A
1
8
1
8
A
UPPER DATA
BYTE
A
PEC BYTE
1
…
1
NA P
3886 F46
Figure 46. Example of PAGE_PLUS_READ
Note: PAGE_PLUS commands cannot be nested. A PAGE_PLUS command cannot be used to read or write another
PAGE_PLUS command. If this is attempted, the LTC3886 will NACK the entire PAGE_PLUS packet and issue a CML
fault for Invalid/Unsupported Data.
WRITE_PROTECT
The WRITE_PROTECT command is used to control writing to the LTC3886 device. This command does not indicate
the status of the WP pin which is defined in the MFR_COMMON command. The WP pin takes precedence over the
value of this command.
BYTE MEANING
0x80 Disable all writes except to the WRITE_PROTECT, PAGE, MFR_
EE_UNLOCK, and STORE_USER_ALL command.
0x40 Disable all writes except to the WRITE_PROTECT, PAGE,
MFR_EE_UNLOCK, MFR_CLEAR_PEAKS, STORE_USER_ALL,
OPERATION and CLEAR_FAULTS command. Individual fault
bits can be cleared by writing a 1 to the respective bits in the
STATUS commands.
0x20 Disable all writes except to the WRITE_PROTECT, OPERATION,
MFR_EE_UNLOCK, MFR_CLEAR_PEAKS, CLEAR_FAULTS,
PAGE, ON_OFF_CONFIG, VOUT_COMMAND and STORE_USER_
ALL. Individual fault bits can be cleared by writing a 1 to the
respective bits in the STATUS commands.
0x10 Reserved, must be 0
0x08 Reserved, must be 0
0x04 Reserved, must be 0
0x02 Reserved, must be 0
0x01 Reserved, must be 0
70
Rev G
For more information www.analog.com
LTC3886/LTC3886-1
PMBus COMMAND DETAILS
When WRITE_PROTECT is set to 0x00, writes to all commands are enabled.
If WP pin is high, PAGE, OPERATION, MFR_CLEAR_PEAKS, MFR_EE_UNLOCK, WRITE_PROTECT and CLEAR_
FAULTS commands are supported. Individual fault bits can be cleared by writing a 1 to the respective bits in the
STATUS commands.
MFR_ADDRESS
The MFR_ADDRESS command byte sets the 7 bits of the PMBus slave address for this device.
Setting this command to a value of 0x80 disables device addressing. The GLOBAL device address, 0x5A and 0x5B,
cannot be deactivated. If RCONFIG is set to ignore, the ASEL0 and ASEL1 pins are still used to determine the LSB
and MSB, respectively, of the channel address. If the ASEL0 and ASEL1 pins are both open, the LTC3886 will use the
address value stored in EEPROM. If the ASEL0 pin is open, the LTC3886 will use the lower 4 bits of the MFR_ADDRESS
value stored in EEPROM to construct the effective address of the part. If the ASEL1 pin is open, the LTC3886 will use
the upper 3 bits of the MFR_ADDRESS value stored in EEPROM to construct the effective address of the part.
This command has one data byte.
MFR_RAIL_ADDRESS
The MFR_RAIL_ADDRESS command enables direct device address access to the PAGE activated channel. The value
of this command should be common to all devices attached to a single power supply rail.
The user should only perform command writes to this address. If a read is performed from this address and the rail
devices do not respond with EXACTLY the same value, the LTC3886 will detect bus contention and may set a CML
communications fault.
Setting this command to a value of 0x80 disables rail device addressing for the channel.
This command has one data byte.
GENERAL CONFIGURATION COMMANDS
DEFAULT
DATA
PAGED FORMAT UNITS EEPROM VALUE
COMMAND NAME
CMD
CODE
MFR_CHAN_CONFIG_LTC3886
0xD0
LTC3886 Channel specific configuration bits.
R/W Byte
LTC3886-1 Channel specific configuration bits. R/W Byte
Y
Y
Reg
Reg
Y
Y
0x1D
0x3D
MFR_CONFIG_ALL_LTC3886
0xD1
General configuration bits.
N
Reg
Y
0x21
DESCRIPTION
TYPE
R/W Byte
Rev G
For more information www.analog.com
71
LTC3886/LTC3886-1
PMBus COMMAND DETAILS
MFR_CHAN_CONFIG_LTC3886
General purpose configuration command common to multiple ADI products.
BIT
MEANING
7
Reserved
6
Reserved
5
LTC3886: Reserved
LTC3886-1: Asserting this bit enables the MFR_VOFF_THRESHOLD sequence off feature to discharge large output capacitors.
4
Disable RUN Low. When asserted the RUN pin is not pulsed low if commanded OFF.
3
Short Cycle. When asserted the output will immediate off if commanded ON while waiting for TOFF_DELAY or TOFF_FALL. TOFF_MIN of 120ms
is honored then the part will command ON.
2
SHARE_CLOCK control. If SHARE_CLOCK is held low, the output is disabled.
1
ALERT is not pulled low if FAULT is pulled low externally.
0
Disables the VOUT decay value requirement for MFR_RETRY_TIME processing. When this bit is set to a 0, the output must decay to less than
12.5% of the programmed value(LTC3886), or below the MFR_VOFF_THRESHOLD value (LTC3886-1) before the PWM will restart. This applies
to any action that turns off the PWM including a fault, an OFF/ON command, or a RUN pin transition from high to low. A TOFF_MAX warning
status will not be generated when this bit is set to a 1.
This command has one data byte.
MFR_CONFIG_ALL_LTC3886
General purpose configuration command common to multiple ADI products.
BIT
MEANING
7
Enable Fault Logging
6
Ignore Resistor Configuration Pins
5
Disable CML Fault for Quick Command Message.
4
Disable SYNC output
3
Enable 255ms PMBus timeout
2
PMBus command writes require a valid Packet Error Checking, PEC, byte to be accepted.*
1
Enable the use of PMBus clock stretching
0
Execute CLEAR_FAULTS on rising edge of either RUN pin.
*PMBus command writes that have a valid PEC byte are always processed.
PMBus command writes that have an invalid PEC byte are not processed
and set a CML status fault.
This command has one data byte.
ON/OFF/MARGIN
COMMAND NAME
CMD
CODE DESCRIPTION
ON_OFF_CONFIG
0x02
OPERATION
MFR_RESET
72
DEFAULT
DATA
FORMAT UNITS EEPROM VALUE
TYPE
PAGED
RUN pin and PMBus bus on/off command configuration.
R/W Byte
Y
Reg
Y
0x1E
0x01
Operating mode control. On/off, margin high and margin
low.
R/W Byte
Y
Reg
Y
0x40
0xFD
Commanded reset without requiring a power-down.
Send Byte
N
NA
Rev G
For more information www.analog.com
LTC3886/LTC3886-1
PMBus COMMAND DETAILS
ON_OFF_CONFIG
The ON_OFF_CONFIG command specifies the combination of RUNn pin input state and PMBus commands needed to
turn the PWM channel on and off.
Supported Values:
VALUE
MEANING
0x1F
OPERATION value and RUNn pin must both command the device to start/run. Device executes immediate off when commanded off.
0x1E
OPERATION value and RUNn pin must both command the device to start/run. Device uses TOFF_ command values when commanded off.
0x17
RUNn pin control with immediate off when commanded off. OPERATION on/off control ignored.
0x16
RUNn pin control using TOFF_ command values when commanded off. OPERATION on/off control ignored.
Note: A high on the RUN pin is always required to start power conversion. Power conversion will always stop with a low on RUN.
Programming an unsupported ON_OFF_CONFIG value will generate a CML fault and the command will be ignored.
This command has one data byte.
OPERATION
The OPERATION command is used to turn the unit on and off in conjunction with the input from the RUNn pins. It
is also used to cause the unit to set the output voltage to the upper or lower MARGIN VOLTAGEs. The unit stays in
the commanded operating mode until a subsequent OPERATION command or change in the state of the RUNn pin
instructs the device to change to another mode. If the part is stored in the MARGIN_LOW/HIGH state, the next RESET
or POWER_ON cycle will ramp to that state. If the OPERATION command is modified, for example ON is changed
to MARGIN_LOW, the output will move at a fixed slope set by the VOUT_TRANSITION_RATE. The default operation
command is sequence off. If VIN is applied to a part with factory default programming and the VOUT_CONFIG resistor
configuration pins are not installed, the outputs will be commanded off.
The part defaults to the Sequence Off state.
This command has one data byte.
Supported Values:
VALUE
MEANING
0xA8
Margin high.
0x98
Margin low.
0x80
On (VOUT back to nominal even if bit 3 of ON_OFF_CONFIG is not set).
0x40*
Soft off (with sequencing).
0x00*
Immediate off (no sequencing).
*Device does not respond to these commands if bit 3 of ON_OFF_CONFIG is not set.
Programming an unsupported OPERATION value will generate a CML fault and the command will be ignored.
This command has one data byte.
Rev G
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73
LTC3886/LTC3886-1
PMBus COMMAND DETAILS
MFR_RESET
This command provides a means to reset the LTC3886 from the serial bus. This forces the LTC3886 to turn off both
PWM channels, load the operating memory from internal EEPROM, clear all faults and then perform a soft-start of
both PWM channels, if enabled.
This write-only command has no data bytes.
PWM CONFIGURATION
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED
DEFAULT
DATA
FORMAT UNITS EEPROM VALUE
MFR_PWM_COMP
0xD3
PWM loop compensation configuration
R/W Byte
Y
Reg
Y
0x70
MFR_PWM_MODE_
LTC3886
0xD4
Configuration for the PWM engine.
R/W Byte
Y
Reg
Y
0xC1
MFR_PWM_CONFIG_
LTC3886
0xF5
Set numerous parameters for the DC/DC controller R/W Byte
including phasing.
N
Reg
Y
0x10
FREQUENCY_SWITCH
0x33
Switching frequency of the controller.
N
L11
Y
350
0xFABC
R/W
Word
kHz
MFR_PWM_MODE_LTC3886
The MFR_PWM_MODE_LTC3886 command sets important PWM controls for each channel. Bits [0] and [6] may be
changed when the addressed channel(s) is on,however the channel(s) must be turned off if any other bits are changed
when the command is issued. The LTC3886 will issue a CML fault and ignore the command and its data if the channel
is on and any bits other than [0] and [6] are changed.
The MFR_PWM_MODE_LTC3886 command allows the user to program the PWM controller to use discontinuous
(pulse-skipping mode), or forced continuous conduction mode.
BIT
MEANING
7
0b
1b
Use High Range of ILIMIT
Low Current Range
High Current Range
6
Enable Servo Mode
5
External temperature sense:
0: ΔVBE measurement.
1: Direct voltage measurement.
[4:2]
1
0b
1b
Bit[0]
0b
1b
Reserved
VOUT Range
The maximum output voltage is 13.2V
The maximum output voltage is 7V
Mode
Discontinuous
Forced Continuous
Bit [7] of this command determines if the part is in high range or low range of the IOUT_OC_FAULT_LIMIT command.
Changing this bit value changes the PWM loop gain and compensation. This bit value cannot be changed when the
channel output is active. Writing this bit when the channel is active will generate a CML fault.
74
Rev G
For more information www.analog.com
LTC3886/LTC3886-1
PMBus COMMAND DETAILS
Bit [6] The LTC3886 will not servo while the part is OFF, ramping on or ramping off. When set to a one, the output servo
is enabled. The output set point DAC will be slowly adjusted to minimize the difference between the READ_VOUT_ADC
and the VOUT_COMMAND (or the appropriate margined value).
When Bit[5] is cleared, the LTC3886 computes temperature in °C from ∆VBE measured by the ADC at the TSNSn pin as
T = (G • ΔVBE • q/(K • ln(16))) – 273.15 + O
When Bit[5] is set, the LTC3886 computes temperature in °C from TSNSn voltage measured by the ADC as
T = (G • (1.35 – VTSNSn + O)/4.3e-3) + 25
For both equations,
G = MFR_TEMP_1_GAIN • 2–14, and
O = MFR_TEMP_1_OFFSET
Bit[1] of this command determines if the part is in high range or low voltage range. Changing this bit value changes
the PWM loop gain and compensation. This bit value cannot be changed when the channel output is active. Writing
this bit when the channel is active will generate a CML fault.
Bit[0] determines if the PWM mode of operation is discontinuous (pulse-skipping mode), or forced continuous conduction mode. This command has one data byte. Whenever the channel is ramping on, the PWM mode will be discontinuous, regardless of the value of this command.
MFR_PWM_COMP
The MFR_PWM_COMP command sets the gm of the PWM channel error amplifiers and the value of the internal RITHn
compensation resistors. This command affects the loop gain of the PWM output which may require modifications to
the external compensation network.
BIT
MEANING
BIT [7:5]
EAgm (mS)
000b
1.00
001b
1.68
010b
2.35
011b
3.02
100b
3.69
101b
4.36
110b
5.04
111b
5.73
BIT [4:0]
RITH (kΩ)
00000b
0
00001b
0.25
00010b
0.5
00011b
0.75
00100b
1
00101b
1.25
Rev G
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75
LTC3886/LTC3886-1
PMBus COMMAND DETAILS
BIT
MEANING
00110b
1.5
00111b
1.75
01000b
2
01001b
2.5
01010b
3
01011b
3.5
01100b
4
01101b
4.5
01110b
5
01111b
5.5
10000b
6
10001b
7
10010b
8
10011b
9
10100b
11
10101b
13
10110b
15
10111b
17
11000b
20
11001b
24
11010b
28
11011b
32
11100b
38
11101b
46
11110b
54
11111b
62
This command has one data byte.
MFR_PWM_CONFIG_LTC3886
The MFR_PWM_CONFIG_LTC3886 command sets the switching frequency phase offset with respect to the falling
edge of the SYNC signal. The part must be in the OFF state to process this command. Either the RUN pins must be low
or the part must be commanded off. If either channel is in the RUN state and this command is written, the command
will be NACK’d and a BUSY fault will be asserted.
BIT
MEANING
7
0b
1b
Use VFBO
Feedback nodes of both channels are independent.
Channel 1 uses the Channel 0 feedback node.
[6:5]
00b
01b
10b
11b
76
Input current sense gain.
2x gain. 0mV to 50mV range.
4x gain. 0mV to 20mV range.
8x gain. 0mV to 5mV range.
Rev G
For more information www.analog.com
LTC3886/LTC3886-1
PMBus COMMAND DETAILS
BIT
4
BIT [2:0]
MEANING
Share Clock Enable : If this bit is 1, the SHARE_CLK pin
will not be released until VIN > VIN_ON. The SHARE_CLK
pin will be pulled low when VIN
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