LTC3897-2
PolyPhase® Synchronous Boost Controller
with Input/Output Protection
DESCRIPTION
FEATURES
Input Supply Range: 4.5V to 65V (Up to 75V Surge)
n Reverse Input Protection to –40V
n Inrush Current Control, Overcurrent Protection and
Output Disconnect for Boost Converter
n Input Voltage Surge Protection with Adjustable
Clamp Voltage
n Onboard Ideal Diode Controller
n Low Quiescent Current: 55µA
n 2-Phase Operation Reduces Required Input and
Output Capacitance and Noise
n Output Voltage Up to 60V
n Adjustable Gate Drive Level 5V to 10V (OPTI-DRIVE)
for Logic-Level or Standard Threshold FETs
n No External Bootstrap Diodes Required
n 5mm × 9mm QFN-44 Package with High Voltage
Pin Spacing
n
APPLICATIONS
The LTC®3897-2 is a synchronous boost DC/DC controller
with surge stopper and ideal diode controller.
The boost controller drives two N-channel power MOSFET
stages out-of-phase to reduce input and output capacitor
requirements, allowing the use of smaller inductors than
the single-phase equivalent. Synchronous rectification
reduces power loss and eases thermal requirements.
The surge stopper controls the gate of an external N-channel
MOSFET to protect against high voltage input transients and
provides inrush current control, overcurrent protection and
output disconnect for the boost converter. The integrated
ideal diode controller drives another N-channel MOSFET to
replace a Schottky diode for reverse input protection and
voltage holdup or peak detection. It controls the forward
voltage drop across the MOSFET and minimizes reverse
current flow.
The differences between the LTC3897-2 and LTC3897 are
shown in Table 1.
Industrial
Automotive
n Military/Avionics
n Telecommunications
n
All registered trademarks and trademarks are the property of their respective owners. Protected
by U. S. Patents, including 5408150, 5481178, 5705919, 5929620, 6144194, 6177787,
6580258.
n
TYPICAL APPLICATION
24V/10A 2-Phase Synchronous Boost Converter with Surge Protection and Reverse Protection
VIN
6V TO
55V
2mΩ
0.1µF
15nF
RUN
SS
SW1
TG1
SENSE2+
–
LTC3897-2 SENSE2
BG2
1µF
4.7µF
5mΩ
3.5µH
VOUT
24V
10A
220µF
0.1µF
BOOST2
TG2
INTVCC
DRVCC
VFB
DRVSET
DRVUV FREQ
DTC
60
50
BURST LOSS
100
40
30
20
10
0
0.001
1k
VIN = 12V
VOUT = 24V
Burst Mode OPERATION
FIGURE 17 CIRCUIT
0.01
0.1
1
OUTPUT CURRENT (A)
10
10
1
38972 TA01b
SW2
ITH
10k
70
POWER LOSS (mW)
IS–
IS+
DG
CS
SG
VIN
100k
BURST EFFICIENCY
80
BOOST1
0.1µF
VIN OPERATES THROUGH TRANSIENTS UP TO 75V.
WHEN VIN > 24V, VOUT FOLLOWS VIN UP TO 57V.
BG1
12.1k
8.66k
90
SENSE1–
549k
10nF
PINS NOT SHOWN IN THIS CIRCUIT:
PLLIN/MODE, ILIM, PHASMD,
CLKOUT, EXTVCC, SGEN, DGEN
100
SPFB
10Ω
3.5µH
SENSE1+
VBIAS
33µF
5mΩ
Efficiency and Power Loss
vs Output Current
EFFICIENCY (%)
INPUT VOLTAGE SURGE PROTECTION
IN-RUSH/OVERCURRENT PROTECTION
REVERSE CURRENT PROTECTION (IDEAL DIODE)
REVERSE INPUT VOLTAGE PROTECTION
475k
38972 TA01a
24.9k
GND
TMR
1nF
Rev. A
Document Feedback
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1
LTC3897-2
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
44 43 42
DGEN
1
PLLIN/MODE
2
FREQ
3
PHASMD
4
CS
DG
IS+
IS–
SPFB
TMR
SGEN
TOP VIEW
40 39 38 37
36 SG
34 VIN
ILIM
5
32 TG1
SENSE1+
6
31 SW1
SENSE1–
7
DTC
8
DRVUV
9
30 BOOST1
45
GND
28 BG1
DRVSET 10
27 VBIAS
26 EXTVCC
INTVCC 11
RUN 12
25 DRVCC
24 BG2
ITH 13
14
SW2
20 21 22
BOOST2
CLKOUT
SS
VFB
15 16 17 18
TG2
SENSE2–
SENSE2+
VIN, SGEN.................................................... –40V to 76V
VBIAS, IS+, IS–, ..........................................................76V
SENSE1+, SENSE2+, SENSE1–, SENSE2–...................65V
CS................................................................ –40V to 76V
SG, DG (Note 8)............................CS – 0.3V to CS + 10V
BOOST1 and BOOST2..................................–0.3V to 71V
SW1 and SW2................................................ –5V to 65V
BG1, BG2, TG1, TG2............................................ (Note 9)
RUN, DGEN................................................. –0.3V to 76V
PLLIN/MODE, TMR, VFB, SPFB..................... –0.3V to 6V
INTVCC.......................................................... –0.3V to 6V
EXTVCC....................................................... –0.3V to 14V
DRVCC, (BOOST1-SW1), (BOOST2-SW2).....–0.3V to 11V
(SENSE1+-SENSE1–),
(SENSE2+-SENSE2–).............................. –0.3V to 0.3V
ILIM, SS, ITH, FREQ,
PHASMD, DTC........................ –0.3V to INTVCC + 0.3V
DRVUV, DRVSET.........................–0.3V to INTVCC + 0.3V
Operating Junction Temperature Range
(Notes 2, 3)......................................... –40°C to 150°C
Storage Temperature Range................... –65°C to 150°C
UHG PACKAGE
44(38)-LEAD (5mm × 8mm) PLASTIC QFN
θJA = 36°C/W
EXPOSED PAD (PIN 45) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3897EUHG-2#PBF
LTC3897EUHG-2#TRPBF
38972
38-Lead (5mm × 8mm) Plastic QFN
–40°C to 125°C
LTC3897IUHG-2#PBF
LTC3897IUHG-2#TRPBF
38972
38-Lead (5mm × 8mm) Plastic QFN
–40°C to 125°C
LTC3897HUHG-2#PBF
LTC3897HUHG-2#TRPBF 38972
38-Lead (5mm × 8mm) Plastic QFN
–40°C to 150°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
2
Rev. A
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LTC3897-2
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, VBIAS = 12V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage and Operating Current
VBIAS
VIN
IQ
Bias Voltage Operating Range
4.5
75
V
SENSE Pins Common Mode Range
(BOOST Converter Input Supply Voltage)
2.3
65
V
Input Supply Voltage Operating Range
4.2
75
V
–10
µA
Reverse Input Current
VIN = –30V
Input DC Supply Current
(Note 5)
Pulse-Skipping or Forced Continuous Mode
RUN = 12V, VFB = 1.25V (No Load)
Burst Mode (Sleep)
RUN = 12V, DGEN = SGEN = 0V, VFB = 1.25V
(No Load), CS = IS+ = IS– = VSPFB = 0V
55
90
µA
RUN = DGEN = 12V, SGEN = 0V, VFB = 1.25V
(No Load), CS = 12V, IS+ = IS– = CS – 0.1V
125
190
µA
RUN = 12V, DGEN = 0V, SGEN = 12V,
VFB = 1.25V (No Load), CS = IS+ = IS– = 12V
260
380
µA
RUN = DGEN = SGEN = 12V, VFB = 1.25V
(No Load), CS = 12V, IS+ = IS– = CS – 0.1V
325
450
µA
RUN = DGEN = SGEN = 0V
15
22
µA
60
V
1.200
1.212
V
±10
±50
nA
0.002
0.02
%/V
Shutdown
0
1.32
mA
BOOST Controller Main Control Loop
VOUT
Regulated Boost Output Voltage in
Synchronous Configuration
VFB
Regulated Feedback Voltage
ITH = 1.2 V (Note 4)
IFB
Feedback Current
(Note 4)
Reference Line Voltage Regulation
(Note 4) VIN = 6V to 75V
Output Voltage Load Regulation
(Note 4)
l
(Note 4) Measured in Servo Loop,
ITH Voltage = 1V to 0.6V
l
0.01
0.1
%
(Note 4) Measured in Servo Loop,
ITH Voltage = 1V to 1.4V
l
–0.01
–0.1
%
gm
Error Amplifier Transconductance
ITH = 1.2 V
UVLO
Undervoltage Lockout
DRVCC Ramping Up
DRVUV = 0V
DRVUV = INTVCC
l
l
DRVCC Ramping Down
DRVUV = 0V
DRVUV = INTVCC
l
l
VRUN Rising
l
VRUN
RUN Pin ON Threshold
1.188
2
4.0
7.5
4.2
7.8
V
V
3.6
6.4
3.8
6.7
4.0
7.0
V
V
1.18
1.28
1.38
V
RUN Pin Hysteresis
ISS
Soft-Start Charge Current
VSENSE1,2(MAX) Maximum Current Sense Threshold
Matching Between VSENSE1(MAX) and
VSENSE2(MAX)
mmho
100
VSS = GND
mV
7
10
13
µA
VFB = 1.15V, ILIM = INTVCC, VSENSE+ = 12V
l
125
140
155
mV
VFB = 1.15V, ILIM = Float, VSENSE+ = 12V
l
85
95
105
mV
VFB = 1.15V, ILIM = GND, VSENSE+ = 12V
l
41
48
55
mV
VFB = 1.15V, ILIM = INTVCC, VSENSE+ = 12V
l
–12
0
12
mV
VFB = 1.15V, ILIM = Float, VSENSE+ = 12V
l
–10
0
10
mV
VFB = 1.15V, ILIM = GND, VSENSE+ = 12V
l
–9
0
9
mV
Rev. A
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3
LTC3897-2
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, VBIAS = 12V, unless otherwise noted.
SYMBOL
BDSW
PARAMETER
CONDITIONS
SENSE+ Pin Current
VFB = 1.1V, ILIM = Float
SENSE– Pin Current
VFB = 1.1V, ILIM = Float
Top Gate Pull-Up Resistance
DRVCC = 10V
2.5
Ω
Top Gate Pull-Down Resistance
DRVCC = 10V
1.5
Ω
Bottom Gate Pull-Up Resistance
DRVCC = 10V
2.5
Ω
Bottom Gate Pull-Down Resistance
DRVCC = 10V
1
Ω
BOOST to DRVCC Switch On-Resistance
VSW = 0V, VDRVSET = INTVCC
3.7
Ω
Top Gate Off to Bottom Gate On Switch-On
Delay Time
DTC = 0V
Bottom Gate Off to Top Gate On Switch-On
Delay Time
MIN
2.6
Minimum BG On-Time
MAX
UNITS
250
350
µA
±2
µA
55
75
ns
DTC = Float
90
130
ns
DTC = INTVCC
170
275
ns
DTC = 0V
55
75
ns
DTC = Float
90
130
ns
DTC = INTVCC
170
275
ns
Maximum BG Duty Factor
tON(MIN)
TYP
(Note 7) VDRVSET = INTVCC
96
%
90
ns
DRVCC LDO Regulator
DRVCC Voltage from Internal VBIAS LDO
VEXTVCC = 0V
7V < VBIAS < 75V, DRVSET = 0V
11V < VBIAS < 75V, DRVSET = INTVCC
DRVCC Load Regulation from VBIAS LDO
ICC = 0mA to 50mA, VEXTVCC = 0V,
VDRVSET = INTVCC
DRVCC Voltage from Internal EXTVCC LDO
7V < VEXTVCC < 13V, DRVSET = 0V
11V < VEXTVCC < 13V, DRVSET = INTVCC
DRVCC Load Regulation from
Internal EXTVCC LDO
ICC = 0mA to 50mA, VEXTVCC = 8.5V,
VDRVSET = 0V
EXTVCC LDO Switchover Voltage
EXTVCC Ramping Positive
DRVUV = 0V
DRVUV = INTVCC
5.8
9.6
5.8
9.6
4.5
7.4
EXTVCC Hysteresis
Programmable DRVCC
RDRVSET = 50kΩ, VEXTVCC = 0V
Programmable DRVCC
RDRVSET = 70kΩ, VEXTVCC = 0V
Programmable DRVCC
RDRVSET = 90kΩ, VEXTVCC = 0V
6.4
6.0
10.0
6.2
10.4
V
V
0.7
2
%
6.0
10.0
6.2
10.4
V
V
0.7
2
%
4.7
7.7
4.9
8.0
V
V
250
mV
5.0
V
7.0
7.6
9.0
V
V
Oscillator and Phase-Locked Loop
Programmable Frequency
fSYNC
4
RFREQ = 25k
105
kHz
RFREQ = 60k
335
400
465
kHz
Lowest Fixed Frequency
VFREQ = 0V
320
350
380
kHz
Highest Fixed Frequency
VFREQ = INTVCC
488
535
585
kHz
Synchronizable Frequency
PLLIN/MODE = External Clock
l
75
550
kHz
PLLIN/MODE Input High Level
PLLIN/MODE = External Clock
l
2.5
PLLIN/MODE Input Low Level
PLLIN/MODE = External Clock
l
V
0.5
V
Rev. A
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LTC3897-2
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, VBIAS = 12V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
BOOST1 and BOOST2 Charge Pump
BOOST Charge Pump Available Output
Current
FREQ = 0V, Forced Continuous or
Pulse-Skipping Mode
VSW1,2 = 12V; VBOOST1,2 = 16.5V
VSW1,2 = 12V; VBOOST1,2 = 19.5V
SGEN Pin ON Threshold
VSGEN Rising
l
1.16
VIN = 4.2V, ISG = 0, –1µA, DG – CS = 1V
l
4.5
VIN = 8V to 70V, ISG = 0, −1µA
l
10
SG Pin Pull-Up Current
VIN = SG = DG = CS = 12V
l
SG Pin Pull-Down Current
Overvoltage: SPFB = 1.5V, SG – CS = 5V
l
Overcurrent: ΔVIS = 100mV, SG – CS = 5V
70
30
µA
µA
Surge Stopper
SGEN Pin Hysteresis
CS Pin Input Current
ΔVIS
ITMR,UP
ITMR,DN
V
mV
8
V
12
16
V
–5
–10
–15
50
130
mA
l
50
130
mA
Shutdown: DGEN = SGEN = 0V, SG – CS = 5V
l
0.4
1
VIN = CS = 12V, IS+ = IS– = 11.9V, SGEN = Float
l
VIN = CS = 12V, SGEN = 0V
l
25
100
µA
VCS = –30V
l
–2.5
–3.5
mA
V
Regulated Surge Protection Feedback Voltage
Overcurrent Fault Threshold, (VIS+ – VIS–)
1.36
100
SG Pin Output High Voltage (VSG – VCS)
VSPFB
1.26
2
µA
mA
6
µA
l
1.205
1.235
1.265
IS– > 2.5V
l
45
50
55
mV
IS– = 1.5V
l
21
27
33
mV
35
100
µA
IS+ Pin Input Current
IS+ = IS– = VIN = CS = 12V, SGEN = DGEN = Float
IS+ = IS– = VIN = CS = 12V, SGEN = DGEN = 0V
l
1
15
µA
SPFB Pin Input Current
SPFB = 1.235V
l
±20
±500
nA
IS– Pin Input Current
IS+ = IS– = VIN = CS = 12V, SGEN = DGEN = Float
IS+ = IS– = VIN = CS = 12V, SGEN = DGEN = 0V
l
20
100
µA
l
5
15
µA
TMR Pin Pull-Up Current, Overvoltage
TMR = 1V, SPFB = 1.5V, VIN – VIS– = 0.5V
TMR = 1V, SPFB = 1.5V, VIN – VIS– = 70V
l
l
–1.5
–43
–2.5
–53
–3.7
–63
µA
µA
TMR Pin Pull-Up Current, Overcurrent
TMR = 1V, ΔVIS = 60mV, VIN – VIS– = 0.5V
TMR = 1V, ΔVIS = 60mV, VIN – VIS– = 70V
l
l
–6
–210
–10
–250
–16
–290
µA
µA
TMR Pin Pull-Up Current, Warning
TMR = 1.3V, SPFB = 1.5V, VIN – VIS– = 0.5V
l
–3
–5
–8
µA
TMR Pin Pull-Up Current, Retry
TMR = 1V, SPFB = 1.5V
l
–1.5
–2.5
–3.7
µA
TMR Pin Pull-Down Current
TMR = 1V, SPFB = 1.5V, Retry
SGEN = 0V
l
l
1.2
0.4
2
0.75
2.8
1.5
µA
mA
Retry Duty Cycle, Overcurrent
ΔVIS = 60mV, VIN – VIS– = 12V
l
0.06
0.08
0.12
%
TMR Pin Thresholds
SG Falling, VIN = 4.2V to 70V
SG Rising (after 32 cycles), VIN = 4.2V to 70V
l
l
1.31
0.13
1.35
0.15
1.38
0.18
V
V
DGEN Pin ON Threshold
VDGEN Rising
l
1.16
1.26
1.36
V
l
Ideal Diode
DGEN Pin Hysteresis
DG Pin Output High Voltage, (VDG − VCS)
DG Pin Pull-Up Current
100
mV
VIN = 4.2V, IDG = 0, −1µA, No Fault, SG Open
l
4.5
8V < VIN < 70V, IDG = 0, −1µA, No Fault, SG
Open
l
10
12
16
V
l
–5
–10
–15
µA
DG = CS = VIN = 12V, CS – IS+ = 0.1V
V
Rev. A
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5
LTC3897-2
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, VBIAS = 12V, unless otherwise noted.
SYMBOL
ΔVSD
PARAMETER
CONDITIONS
MIN
TYP
DG Pin Pull-Down Current
DG = CS + 5V, CS – IS+ = –0.2V
l
60
130
mA
DG = CS + 5V, SGEN = DGEN = 0V
l
0.4
1
mA
DG – CS = 2.5V, VIN = CS = 4.2V to 70V
l
20
30
Source-Drain Regulation Voltage, (VCS
− VIS+)
MAX
40
UNITS
mV
l
DG Turn Off Propagation Delay in Fault
CS – IS+ = –1V, DG High to Low
0.6
2
µS
Condition
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
Note 3: This IC includes overtemperature protection that is intended to
may cause permanent damage to the device. Exposure to any Absolute
protect the device during momentary overload conditions. The maximum
Maximum Rating condition for extended periods may affect device
rated junction temperature will be exceeded when this protection is active.
reliability and lifetime.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
Note 2: The LTC3897-2 is tested under pulsed load conditions such
the device.
that TJ ≈ TA. The LTC3897E-2 is guaranteed to meet specifications
from 0°C to 85°C junction temperature. Specifications over the –40°C
Note 4: The LTC3897-2 is tested in a feedback loop that servos VFB to the
to 125°C operating junction temperature range are assured by design,
output of the error amplifier while maintaining ITH at the midpoint of the
characterization and correlation with statistical process controls. The
current limit range.
LTC3897I-2 is guaranteed over the –40°C to 125°C operating junction
Note 5: Dynamic supply current is higher due to the gate charge being
temperature range. The LTC3897H-2 is guaranteed over the –40°C to
delivered at the switching frequency.
150°C operating temperature range. High junction temperatures degrade
Note 6: Rise and fall times are measured using 10% and 90% levels.
operation lifetime. Operation lifetime is derated for junction temperatures
Delay times are measured using 50% levels.
greater than 125°C. Note that the maximum ambient temperature
Note 7: See Minimum On-Time Considerations in the Applications
consistent with these specifications is determined by specific operating
Information section.
conditions in conjunction with board layout, the rated package thermal
Note 8: Internal clamps limit the SG and DG pins to minimum of 10V
impedance and other environmental factors. The junction temperature
above the CS pin. Driving these pins to voltages beyond the clamp may
(TJ, in °C) is calculated from the ambient temperature (TA, in °C) and
damage the device.
power dissipation (PD, in watts) according to the formula:
Note 9: Do not apply a voltage or current source to these pins. They must
TJ = TA + (PD • θJA), where θJA = 36°C/W for the QFN package.
be connected to capacitive loads only, otherwise permanent damage may
occur.
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency and Power Loss
vs Output Current
Efficiency and Power Loss
vs Output Current
90
80
90
FCM LOSS
10k
BURST LOSS
1k
50
PULSE–SKIPPING
40 EFFICIENCY
FCM EFFICIENCY
100
30
20
10
0
0.001
10
VIN = 12V
VOUT = 24V
FIGURE 17 CIRCUIT
0.01
0.1
1
OUTPUT CURRENT (A)
10
70
60
50
BURST LOSS
30
20
0
0.001
1k
100
40
38972 G01
6
10k
80
10
1
100k
BURST EFFICIENCY
VIN = 12V
VOUT = 24V
Burst Mode OPERATION
FIGURE 17 CIRCUIT
0.01
0.1
1
OUTPUT CURRENT (A)
POWER LOSS (mW)
70
PULSE–SKIPPING
60 LOSS
100
POWER LOSS (mW)
EFFICIENCY (%)
100k
BURST EFFICIENCY
EFFICIENCY (%)
100
TA = 25°C unless otherwise noted.
10
10
1
38972 G02
Rev. A
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LTC3897-2
TYPICAL PERFORMANCE CHARACTERISTICS
Load Step
Forced Continuous Mode
EFFICIENCY (%)
Efficiency vs Input Current
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
TA = 25°C unless otherwise noted.
LOAD STEP
5A/DIV
INDUCTOR
CURRENT
5A/DIV
VOUT
500mV/DIV
IOUT = 2A
VOUT = 24V
FIGURE 17 CIRCUIT
0
5
10
15
INPUT VOLTAGE (V)
20
25
38972 G04
200µs/DIV
VIN = 12V
VOUT = 24V
LOAD STEP FROM 100mA TO 5A
FIGURE 17 CIRCUIT
38972 G03
Load Step
Burst Mode Operation
Load Step
Pulse-Skipping Mode
LOAD STEP
5A/DIV
LOAD STEP
5A/DIV
INDUCTOR
CURRENT
5A/DIV
INDUCTOR
CURRENT
5A/DIV
VOUT
500mV/DIV
VOUT
500mV/DIV
200µs/DIV
VIN = 12V
VOUT = 24V
LOAD STEP FROM 100mA TO 5A
FIGURE 17 CIRCUIT
38972 G05
38972 G06
200µs/DIV
VIN = 12V
VOUT = 24V
LOAD STEP FROM 100mA TO 5A
FIGURE 17 CIRCUIT
Inductor Currents at Light Load
Start-Up
VOUT
FORCED
CONTINUOUS
MODE
SG
VOUT
10V/DIV
Burst Mode
OPERATION
5A/DIV
PULSESKIPPING
MODE
VIN
CS
0V
5µs/DIV
VIN = 12V
VOUT = 24V
ILOAD = 200µA
FIGURE 17 CIRCUIT
38972 G07
10ms/DIV
VIN = 12V
VOUT = 48V
FIGURE 16 CIRCUIT
38972 G08
Rev. A
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7
LTC3897-2
TYPICAL PERFORMANCE CHARACTERISTICS
Regulated Feedback Voltage
vs Temperature
Soft-Start Pull-Up Current
vs Temperature
1.212
Shutdown Current vs Temperature
20
11.0
18
1.206
1.203
1.200
1.197
1.194
SHUTDOWN CURRENT (µA)
1.209
SOFT-START CURRENT (µA)
10.5
10.0
9.5
1.191
9.0
–75 –50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
18
INPUT SUPPLY CURRENT (µA)
6
4
15
14
13
12
300.0
1.40
RUN = 0V
SGEN = DGEN = 12V
IS+ = IS– = CS – 0.1V
1.35
250.0
200.0
150.0
QUIESCENT CURRENT
VFB = 1.25V
SGEN = DGEN = 0V
100.0
12.5
25
37.5
50
INPUT VOLTAGE (V)
62.5
0
–75 –50 –25
75
RUN RISING
1.25
RUN FALLING
1.20
1.10
–75 –50 –25
0 25 50 75 100 125 150
TEMPRATURE (°C)
38972 G13
Undervoltage Lockout Threshold
vs Temperature
9
11
DRVSET = INTVCC
DRVCC RISING
10
0 25 50 75 100 125 150
INPUT VOLTAGE (V)
38972 G14
DRVCC and EXTVCC
vs Load Current
DRVCC Line Regulation
6.4
6.2
DRVSET = INTVCC
EXTVCC = 0V
6.0
5.8
DRVCC VOLTAGE (V)
DRVCC FALLING
6
5 DRVSET = GND
DRVCC RISING
4
DRVCC FALLING
3
2
–75 –50 –25
1.30
1.15
50.0
0
0 25 50 75 100 125 150
TEMPERATURE (°C)
BOOST Shutdown (RUN)
Threshold vs Temperature
DRVCC VOLTAGE (V)
SOFT-START CURRENT (µA)
350.0
16
38972 G12
DRVCC VOLTAGE (V)
8
38972 G11
400.0
11
9
8
7
6
EXTVCC = 8.5V
5.6
5.4
5.2
5.0
4.8
EXTVCC = 5V
4.6
DRVSET = GND
4.4
VBIAS = 12V
DRVSET = GND
4.2
0 25 50 75 100 125 150
TEMPERATURE (°C)
5
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75
INPUT VOLTAGE (V)
38972 G15
8
10
Input Supply Current vs
Temperature
VIN = VBIAS
17
7
12
38972 G10
Shutdown Current
vs Input Voltage
8
14
0
–75 –50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
38972 G09
10
16
2
1.188
–75 –50 –25
RUN PIN VOLTAGE (V)
REGULATED FEFEDBACK VOLTAGE (V)
TA = 25°C unless otherwise noted.
38972 G16
4.0
0
25
50
75
100
LOAD CURRENT (mA)
125
150
38972 G17
Rev. A
For more information www.analog.com
LTC3897-2
TYPICAL PERFORMANCE CHARACTERISTICS
EXTVCC Switchover and DRVCC
Voltages vs Temperature
600
FREQ = INTVCC
550
8
EXTVCC RISING
7
EXTVCC FALLING
DRVCC
DRVSET = GND
5
450
400
350
EXTVCC RISING
EXTVCC FALLING
4
–75 –50 –25 0 25 50 75 100 125 150
TEMPERATURE (°C)
300
–75 –50 –25
BURST MODE
OPERATION
ILIM = FLOAT
30
ILIM = GND
0
SENSE CURRENT (µA)
MAXIMUM CURRENT SENSE VOLTAGE (mV)
120 PULSE–SKIPPING MODE
–30
FORCED CONTINUOUS MODE
0
0.2
0.4
0.6 0.8 1.0
ITH VOLTAGE (V)
300
0 25 50 75 100 125 150
TEMPERATURE (°C)
1.2
1.4
38972 G21
38972 G22
38972 G24
CHARGE PUMP CHARGING CURRENT (µA)
50
40
30
20
0
T = 155°C
T = 25°C
T = –55°C
0
25
35
45
55
INPUT VOLTAGE (V)
65
75
38972 G23
BOOST-SW Charge Pump Charging
Current vs Switch Voltage
50
VSW = 12V
VBOOST – VSW = 7.5V
10
15
320
ILIM = INTVCC
300 VSENSE = 12V
280
260
ILIM = FLOAT
240 SENSE+ PIN
220
200
ILIM = GND
180
160
140
120
100
80
60
ILIM = INTVCC
40
ILIM = FLOAT
20
ILIM = GND
SENSE– PIN
0
0 0.20 0.40 0.60 0.80 1 1.20 1.40 1.60
ITH VOLTAGE (V)
BOOST-SW Charge Pump Charging
Current vs Operating Frequency
320
+
ILIM = INTVCC
300 SENSE PIN
280
260
ILIM = FLOAT
240
220
200
ILIM = GND
180
160
140
120
100
80
60
ILIM = INTVCC
40
ILIM = FLOAT
20
ILIM = GND
SENSE– PIN
0
5 10 15 20 25 30 35 40 45 50 55 60 65
VSENSE COMMON MODE VOLTAGE (V)
5
SENSE Pin Input Current
vs ITH Voltage
280
260 VSENSE = 12V
SENSE+ PIN
240 ILIM = FLOAT
220
200
180
160
140
120
100
80
60
40
20
SENSE– PIN
0
–75 –50 –25 0 25 50 75 100 125 150
TEMPERATURE (°C)
SENSE Pin Input Current
vs VSENSE Voltage
FREQ = GND
38972 G20
SENSE Pin Input Current
vs Temperature
ILIM = INTVCC
60
400
38972 G19
Maximum Current Sense
Threshold vs ITH Voltage
90
450
350
38972 G18
150
500
FREQ = GND
SENSE CURRENT (µA)
6
500
FREQUENCY (kHz)
DRVSET = INTVCC
FREQ = INTVCC
550
CHARGE PUMP CHARGING CURRENT (µA)
9
FREQUENCY (kHz)
DRVCC VOLTAGE (V)
600
DRVCC
10
SENSE CURRENT (µA)
Oscillator Frequency
vs Input Voltage
Oscillator Frequency
vs Temperature
11
–60
TA = 25°C unless otherwise noted.
100
200
300
400
500
OPERATING FREQUENCY (kHz)
600
38972 G25
VBOOST – VSW = 7.5V
40
FREQ = INTVCC
30
FREQ = GND
20
10
0
5 10 15 20 25 30 35 40 45 50 55 60 65
SWITCH VOLTAGE (V)
38972 G26
Rev. A
For more information www.analog.com
9
LTC3897-2
Ideal Diode Regulation Voltage
vs VIN
–250
TMR Current vs Temperature
200
TMR = 1V
–225
GATE PULL-DOWN CURRENT (mA)
T = 155°C
T = –55°C
T = 25°C
–200
31
TMR CURRENT (µA)
IDEAL DIODE REGULATION VOLTAGE (mV)
32
TMR Current vs VIN – IS– Voltage
30
29
–175
OVERCURRENT CONDITION
–150
–125
–100
–75
OVERVOLTAGE CONDITION
–50
–25
28
0
15
30
45
VIN (V)
60
75
0
0
15
30
45
60
VIN – IS– VOLTAGE (V)
38972 G27
Overcurrent Threshold vs
IS– Voltage
15
SG(DG) CHARGING CURRENT (mV)
OVERCURRENT THREADSHOLD (mV)
60
50
40
30
20
10
VSG – VCS = VDG – VCS = 5V
VIN = 12V
170
155
DG PULL–DOWN CURRENT
VSG – VCS = 200mV
140
125
110
95
80
SG PULL–DOWN CURRENT
VIS+ – VIS– = 100mV OR VSPFB = 1.5V
65
50
–75 –50 –25
75
0 25 50 75 100 125 150
TEMPERATURE (°C)
38972 G28
38972 G29
SG(DG) Charging Current
vs VIN Voltage
VSG = VDG = VCS = VIN
13
12
11
10
9
8
7
6
0 0.50 1 1.50 2 2.50 3 3.50 4 4.50 5
IS– VOLTAGE (V)
14
185
38972 G30
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75
VIN VOLTAGE (V)
38972 G31
SG(DG) GATE Voltage vs GATE
Pull-Down Current
SG(DG) GATE Voltage vs VIN
Voltage
15
15
14
VSG(DG) – VCS
13
SG(DG) GATE VOLTAGE (v)
SG(DG) GATE VOLTAGE (v)
14
12
11
10
9
8
7
6
12
11
10
9
8
7
0
1
2 3 4 5 6 7 8 9
GATE PULLDOWN CURRENT (µA)
10
38972 G32
10
VSG(DG) – VCS
13
6
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75
VIN VOLTAGE (V)
38972 G33
Rev. A
For more information www.analog.com
LTC3897-2
PIN FUNCTIONS
DGEN (Pin 1): Ideal Diode Enable Pin. This pin enables
regulation for the ideal diode’s forward drop. Tying this
pin to SGND disables the regulation but still keeps the
reverse input voltage protection.
PLLIN/MODE (Pin 2): External Synchronization Input to
Phase Detector and Forced Continuous Mode Input. When
an external clock is applied to this pin, it will force the
controller into pulse-skipping mode of operation and the
phase-locked loop will force the rising BG1 signal to be
synchronized with the rising edge of the external clock.
When not synchronizing to an external clock, this input
determines how the LTC3897-2 operates at light loads.
Pulling this pin to ground selects Burst Mode operation.
An internal 100k resistor to ground also invokes Burst
Mode® operation when the pin is floated. Tying this pin
to INTVCC forces continuous inductor current operation.
Tying this pin to a voltage greater than 1.2V and less than
INTVCC – 1.3V selects pulse-skipping operation. This can
be done by adding a 100k resistor between the PLLIN/
MODE pin and INTVCC.
FREQ (Pin 3): The frequency control pin for the internal
VCO. Connecting the pin to GND forces the VCO to a fixed
low frequency of 350kHz. Connecting the pin to INTVCC
forces the VCO to a fixed high frequency of 535kHz. The
frequency can be programmed by connecting a resistor
from the FREQ pin to GND. The resistor and an internal
20µA source current create a voltage used by the internal
oscillator to set the frequency. Alternatively, this pin can
be driven with a DC voltage to vary the frequency of the
internal oscillator.
PHASMD (Pin 4): This pin can be floated, tied to GND, or
tied to INTVCC to program the phase relationship between
the rising edges of BG1 and BG2, as well as the phase
relationship between BG1 and CLKOUT.
ILIM (Pin 5): Current Comparator Sense Voltage Range
Input. This pin is used to set the peak current sense voltage in the current comparator. Connect this pin to GND,
open, and INTVCC to set the peak current sense voltage
to 48mV, 95mV and 140mV, respectively.
SENSE1+, SENSE2+ (Pins 6, 15): Positive Current Sense
Comparator Input for each channel of the boost controller.
The (+) input to the Current Comparator is normally connected to the positive terminal of a current sense resistor.
This pin also supplies power to the current comparator.
SENSE1–, SENSE2– (Pins 7, 14): Negative Current Sense
Comparator Input for each channel of the boost controller.
The (–) input to the Current Comparator is normally
connected to the negative terminal of a current sense
resistor connected in series with the inductor.
DTC (Pin 8): Dead Time Control. This pin selects different
dead times between TG and BG. Floating this pin sets the
dead time to 100nS. Tying this pin to GND or INTVCC sets
the dead time to 60nS or 200nS, respectively.
DRVUV (Pin 9): Sets the higher or lower DRVCC UVLO and
EXTVCC switchover thresholds, as listed on the Electrical
Characteristics table. Tying this pin to GND sets the lower
thresholds whereas tying this pin to INTVCC sets the higher
thresholds. See the Electrical Characteristics table for the
rising/falling threshold values and tolerances.
DRVSET (Pin 10): Sets the regulated output voltage of the
DRVCC LDO regulator. Tying this pin to GND sets DRVCC to
6.0V. Tying this pin to INTVCC sets DRVCC to 10.0V. Other
voltages between 5.0V and 10.0V can be programmed by
using a resistor (50k to 100k) between the DRVSET pin
and GND. When programming DRVSET with a resistor, do
not choose a resistor value less than 50k (unless shorting
DRVSET to GND) or higher than 100k.
INTVCC (Pin 11): Output of the Internal 3.5V Low Dropout
Regulator. Supply pin for the low voltage analog and digital circuits. A low ESR 0.1µF ceramic bypass capacitor
should be connected between INTVCC and GND, as close
as possible to the IC. INTVCC should not be used to power
or bias any external circuitry other than to configure the
FREQ, PHASMD, ILIM, DTC, DRVUV, DRVSET and PLLIN/
MODE pins.
Rev. A
For more information www.analog.com
11
LTC3897-2
PIN FUNCTIONS
RUN (Pin 12): Run Control Input for the boost controller.
Forcing this pin below 1.28V shuts down the controller.
Forcing this pin as well as the SGEN and DGEN pins
below 0.7V shuts down the entire LTC3897-2, reducing
quiescent current to approximately 15µA. An external
resistor divider connected to VBIAS can set the threshold
for converter operation.
ITH (Pin 13): Error Amplifier Outputs and Switching
Regulator Compensation Point. The current comparator
trip point increases with this control voltage.
VFB (Pin 16): This pin receives the remotely sensed feedback voltage from the external resistive divider across the
boost controller output.
SS (Pin 17): Output Soft-Start Input. A capacitor to ground
at this pin sets the ramp rate of the output voltage during
startup.
CLKOUT (Pin 18): A digital output used for daisy-chaining
multiple LTC3897-2 ICs in multi-phase systems. The
PHASMD pin voltage controls the relationship between
BG1 and CLKOUT. This pin swings between GND and
INTVCC.
TG2, TG1 (Pins 20, 32): Top Gate. Connect to the gate of
the synchronous N-channel MOSFET.
SW2, SW1 (Pins 21, 31): Switch Node. Connect to the
source of the synchronous N-channel MOSFET (TG), the
drain of the main N-channel MOSFET (BG), and the inductor.
BOOST2, BOOST1 (Pins 22, 30): Floating power supply
for the synchronous N-channel MOSFET. Bypass to SW
pin with a capacitor.
BG2, BG1 (Pins 24, 28): Bottom Gate. Connect to the gate
of the main N-channel MOSFET.
DRVCC (Pin 25): Output of the Internal Low Dropout (LDO)
Regulator that powers the boost controller gate drivers.
The regulated DRVCC voltage is set by the DRVSET pin.
Must be decoupled to ground with a minimum of 4.7µF
ceramic or other low ESR capacitor. Do not use the DRVCC
pin for any other purpose.
12
EXTVCC (Pin 26): External Power Input to an Internal LDO
Connected to DRVCC. This LDO supplies DRVCC power from
EXTVCC, bypassing the internal LDO powered from VBIAS
whenever EXTVCC is higher than its switchover threshold
(4.7V or 7.7V depending on the state of the DRVUV pin).
See EXTVCC Connection in the Applications Information
section. Do not float or exceed 14V on this pin. Do not
connect EXTVCC to a voltage greater than VBIAS. Connect
to GND if not used.
VBIAS (Pin 27): Bias Supply Pin. This pin powers most of
the chip. When the ideal diode is used at the input to block
negative input voltage, connect a Schottky diode from the
VIN pin to the VBIAS pin. A bypass capacitor should be tied
between this pin and the signal ground pin.
VIN (Pin 34): Input Supply Pin. A bypass capacitor should
be tied between this pin and the GND pins. The supply
input ranges from 4.2V to 75V for normal operation. It can
also be pulled below ground potential by up to 40V during
a reverse battery condition, without damaging the part.
SG (Pin 36): N-Channel MOSFET Gate Drive Output for
Surge Stopper Controller. The SG pin is pulled up by an
internal charge pump current source and clamped to 12V
above the CS pin. An external capacitor connected to this
pin can provide slew rate and inrush current control. A
voltage and current amplifier controls the SG pin to regulate
the SPFB pin voltage. When the overcurrent comparator
monitoring the IS+ and IS– pins is tripped, the SG pin is
pulled low, forming an electronic current breaker.
CS (Pin 37): Common Source Input and Gate Drive Return.
Connect this pin directly to the sources of the external backto-back N-Channel MOSFETs and the resistance should be
limited to below 10Ω. CS is the anode of the ideal diode
and the voltage sensed between this pin and the IS+ pin
is used to control the source-drain voltage across the
N-Channel MOSFET (forward voltage of the ideal diode).
Rev. A
For more information www.analog.com
LTC3897-2
PIN FUNCTIONS
DG (Pin 38): N-Channel Gate Drive Output for Ideal Diode
Controller. When the load current creates more than 30mV
of voltage drop across the MOSFET, the DG pin is pulled
high by an internal charge pump current source and
clamped to 12V above the CS pin. When the load current
is small, the DG pin is actively driven to maintain 30mV
across the MOSFET. If reverse current develops, a 100mA
fast pull-down circuit quickly connects the DG pin to the
CS pin, turning off the MOSFET.
IS+ (Pin 39): Positive Overcurrent Sense Input. Connect
this pin to the input of the overcurrent sense resistor. The
current limit circuit pulls the SG pin low if the sense voltage
between the IS+ and IS– pins exceed 50mV if IS– is above
2.5V. When IS– drops below 1.5V, the sense voltage is
reduced to 27mV for additional protection during output
overcurrent condition. The voltage difference with the
IS– pin must be limited to less than 30V. Connect to the
IS– pin if unused.
protected and ground. During an overvoltage condition,
the SG pin is servoed to maintain a 1.235V threshold at
the SPFB pin. Connect to GND to disable the overvoltage clamp.
TMR (Pin 43): Fault Timer Input for the Surge Stopper.
Connect a capacitor between this pin and ground to set
the times for fault and cool down periods. When either
overvoltage or overcurrent is detected, a current source
charges up the TMR pin. The current charging up this
pin during the fault conditions depends on the voltage
difference between VIN and IS– pins. When VTMR reaches
1.35V, the pass transistor turns off. As soon as the fault
condition disappears, a cool down interval commences
while the TMR pin cycles 32 times between 0.15V and
1.35V with 2.5µA charge and 2µA discharge currents. At
the end of the cool down period, the SG pin is allowed to
pull high turning the pass transistor back on.
IS– (Pin 40): Negative Overcurrent Sense Input. Connect
this pin to the output of the overcurrent sense resistor.
SGEN (Pin 44): Surge Gate Enable Pin. This pin enables
the surge stopper controller (voltage clamp and output
protection). When SGEN is low, SG is pulled to CS.
SPFB (Pin 42): Surge Protection Voltage Regulator
Feedback Input. Connect this pin to the center tap of the
resistive divider connected between the voltage being
GND (Exposed Pad Pin 45): Ground. The exposed pad
must be soldered to the PCB for rated electrical and thermal performance.
Table 1. Summary of the Main Differences Between the LTC3897 and the LTC3897-2
LTC3897-2
LTC3897
Pulse Skipping Mode
(Discontinuous)
Forced Continuous Mode
Output Overvoltage Protection
when VFB > 110% of Regulation
No TG Crowbar
TG Crowbar
(TG Forced On)
Programmable Frequency
50kHz to 550kHz
50kHz to 900kHz
Package
5×8 QFN-44(38)
5×7 QFN-38
TSSOP-38
Light Load Mode when
Synchronized to an External Clock
Rev. A
For more information www.analog.com
13
LTC3897-2
BLOCK DIAGRAM
DTC
CLKOUT
DUPLICATE FOR SECOND CONTROLLER CHANNEL
DRVCC
BOOST
PHASMD
S
INTVCC
Q
R
SWITCHING
LOGIC
AND
CHARGE
PUMP
SHDN
20µA
FREQ
CLK2
VCO
+
0.425V
CLK1
DRVCC
PGND
– +
+ –
+
IREV
–
2mV
SYNC
DET
100k
CIN
–
2V
–
EA +
+
VFB
1.2V
SS
1.2V
2V
ITH
0.5µA
LDO
4.7V/7.7V
SHDN
RUN
LDO
10µA
+
+
SENS
LO
SHDN
INTVCC
LDO
–
CC
CC2
RC
SS
EN
EN
RSENSE
VBIAS
20µA
EXTVCC
L
+
CURRENT
LIMIT
DRVSET
DRVUV
SENSE+
SLOPE COMP
SENS LO
ILIM
VBIAS
SENSE –
1.6V
0.7V
PLLIN/
MODE
COUT
BG
SLEEP
–
ICMP
+
VOUT
SW
–
PFD
CB
TG
DRVCC
4.7V/7.7V
INTVCC
–
BOOST CONTROLLER
IS–
GND
IS+
1.235V 50mV
+
SPFB
VA
–
+
+
–
–
+
IA
–
+
–
+
30mV
–
+
30mV
–
0.5µA
10µA
CHARGE
PUMP
10µA
COUNTER
32×
CONTROL
LOGIC
+
–
0.5µA
SG OFF
2.5µA
–
+
DG OFF
1.35V
12V
0.15V
2µA
12V
VIN
SGEN
SG
CS
DG
DGEN
SURGE PROTECTOR AND IDEAL DIODE CONTROLLERS
14
TMR
38972 BD
Rev. A
For more information www.analog.com
LTC3897-2
OPERATION
Overview
The LTC3897-2 includes a polyphase step-up (boost) controller as well as surge stopper and ideal diode controllers
to enable input/output protections for the boost controller.
All three controllers can be individually enabled or disabled
for building different boost converter applications that
have a variety of combinations of the protection circuits.
The surge stopper controls the gate of an external N-channel
MOSFET to protect against high voltage input transients
and provide in-rush current control and output disconnect
for the boost converter. The current limited circuit breaker
protects against short-circuited boost outputs and other
overcurrent events.
The integrated ideal diode controller drives another
N-channel MOSFET to replace a Schottky diode for reverse
(negative) input protection and voltage holdup or peak
detection. It controls the forward voltage drop across the
MOSFET and minimizes reverse current transients during
power source failure, brownout or input short.
BOOST Controller Main Control Loop
The LTC3897-2’s boost controller uses a constant-frequency, current mode step-up architecture with the two
controller channels operating out of phase. During normal
operation, each external bottom MOSFET is turned on
when the clock for that channel sets the RS latch, and is
turned off when the main current comparator, ICMP, resets
the RS latch. The peak inductor current at which ICMP
trips and resets the latch is controlled by the voltage on
the ITH pin, which is the output of the error amplifier EA.
The error amplifier compares the output voltage feedback
signal at the VFB pin (which is generated with an external
resistor divider connected across the output voltage,
VOUT, to ground), to the internal 1.200V reference voltage. In a boost converter, the required inductor current is
determined by the load current, VIN and VOUT. When the
load current increases, it causes a slight decrease in VFB
relative to the reference, which causes the EA to increase
the ITH voltage until the average inductor current in each
channel matches the new requirement based on the new
load current.
After the bottom MOSFET is turned off each cycle, the
top MOSFET is turned on until either the inductor current
starts to reverse, as indicated by the current comparator,
IR, or the beginning of the next clock cycle.
DRVCC/EXTVCC/INTVCC Power
Power for the top and bottom MOSFET drivers is derived
from the DRVCC pin. The DRVCC supply voltage can be
programmed from 5V to 10V through control of the
DRVSET pin. When the EXTVCC pin is tied to a voltage
below its switchover voltage (4.7V or 7.7V depending on
the DRVSET voltage), the VBIAS LDO (low dropout linear
regulator) supplies the DRVCC voltage set by DRVSET from
VBIAS to DRVCC. If EXTVCC is taken above the switchover
voltage, the VBIAS LDO is turned off and an EXTVCC LDO
is turned on. Once enabled, the EXTVCC LDO supplies
the voltage from EXTVCC to DRVCC. Using the EXTVCC
pin allows the DRVCC power to be derived from a high
efficiency external source, thus removing the power dissipation of the VBIAS LDO.
Each top MOSFET driver is biased from the floating bootstrap capacitor, CB, which normally recharges during each
cycle through an internal switch whenever SW goes low.
The INTVCC supply powers most of the other internal
circuits in the LTC3897-2’s boost controller. The INTVCC
LDO regulates to a fixed value of 3.5V and its power is
derived from the DRVCC supply.
Shutdown and Start-Up (RUN, SGEN, DGEN and SS
Pins)
The LTC3897-2's boost controller, surge stopper, and ideal
diode can be shut down independently using the enable
pins, i.e. the RUN pin, the SGEN pin and the DGEN pin.
Pulling the RUN pin below 1.28V shuts down the main
control loops for both phases of the boost controller.
Pulling the RUN pin below 0.7V disables both phases and
most internal circuits. If SGEN and DGEN are both low,
pulling the RUN pin below 0.7V also disables the DRVCC
and INTVCC LDOs. In this state, the LTC3897-2 draws only
15µA of quiescent current.
Rev. A
For more information www.analog.com
15
LTC3897-2
OPERATION
NOTE: When the input/output protections are not used,
do not apply a heavy load for an extended time while the
chip is in shutdown. The top MOSFETs will be turned off
during shutdown and the output load may cause excessive
dissipation in the body diodes.
Releasing any of the enable pins (RUN, SGEN or DGEN)
allows a small internal current to pull up the pin to enable
the corresponding circuits. The enable pins may be externally pulled up or driven directly by logic. Each of the
enable pins can tolerate up to 75V (absolute maximum),
so it can be conveniently tied to the supplies in always-on
applications where the controllers or the protections are
enabled continuously and never shutdown. Note that the
SGEN pin can also tolerate negative voltage up to –40V,
so it can be tied to the VIN supply directly.
When the input/output protections are enabled, the boost
controller is not enabled until IS– pin is above (VIN – 0.7V).
This is to ensure that the external MOSFETs for the input/
output protections are fully turned on before the BOOST
controller can start operating.
The start-up of the boost controller’s output voltage VOUT is
controlled by the voltage on the SS pin. When the voltage
on the SS pin is less than the 1.2V internal reference, the
LTC3897-2 regulates the VFB voltage to the SS pin voltage
instead of the 1.2V reference. This allows the SS pin to
be used to program a soft-start by connecting an external
capacitor from the SS pin to GND. An internal 10µA pullup current charges this capacitor creating a voltage ramp
on the SS pin. As the SS voltage rises linearly from 0V to
1.2V (and beyond up to INTVCC), the output voltage rises
smoothly to its final value.
Light Load Current Operation—Burst Mode Operation,
Pulse-Skipping or Continuous Conduction (PLLIN/
MODE Pin)
The LTC3897-2’s boost controller can be enabled to enter
high efficiency Burst Mode operation, constant-frequency,
pulse-skipping mode or forced continuous conduction
mode at low load currents. To select Burst Mode operation, tie the PLLIN/MODE pin to ground (e.g., GND). To
16
select forced continuous operation, tie the PLLIN/MODE
pin to INTVCC. To select pulse-skipping mode, tie the
PLLIN/MODE pin to a DC voltage greater than 1.2V and
less than INTVCC – 1.3V.
When the controller is enabled for Burst Mode operation,
the minimum peak current in the inductor is set to
approximately 30% of the maximum sense voltage even
though the voltage on the ITH pin indicates a lower value.
If the average inductor current is higher than the required
current, the error amplifier EA will decrease the voltage
on the ITH pin. When the ITH voltage drops below 0.425V,
the internal sleep signal goes high (enabling sleep mode)
and both external MOSFETs are turned off.
In sleep mode, much of the internal circuitry is turned off
and the LTC3897-2 boost controller draws only 55µA of
quiescent current when the input/output protections are
not used. In sleep mode the load current is supplied by
the output capacitor. As the output voltage decreases,
the EA’s output begins to rise. When the output voltage
drops enough, the sleep signal goes low and the controller
resumes normal operation by turning on the bottom external
MOSFET on the next cycle of the internal oscillator.
When the controller is enabled for Burst Mode operation,
the inductor current is not allowed to reverse. The
reverse current comparator (IR) turns off the top external
MOSFET just before the inductor current reaches zero,
preventing it from reversing and going negative. Thus,
the controller operates in discontinuous current operation.
In forced continuous operation, the inductor current is
allowed to reverse at light loads or under large transient
conditions. The peak inductor current is determined by
the voltage on the ITH pin, just as in normal operation. In
this mode, the efficiency at light loads is lower than in
Burst Mode operation. However, continuous operation
has the advantages of lower output voltage ripple and less
interference to audio circuitry, as it maintains constantfrequency operation independent of load current.
When the PLLIN/MODE pin is connected for pulse-skipping
mode, or when it is driven by an external clock source to
use the phase-locked loop, the LTC3897-2 operates in
Rev. A
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LTC3897-2
OPERATION
PWM pulse-skipping mode at light loads. In this mode,
constant-frequency operation is maintained down to
approximately 1% of designed maximum output current. At
very light loads, the current comparator ICMP may remain
tripped for several cycles and force the external bottom
MOSFET to stay off for the same number of cycles (i.e.,
skipping pulses). The inductor current is not allowed to
reverse (discontinuous operation). This mode, like forced
continuous operation, exhibits low output ripple as well as
low audio noise and reduced RF interference as compared
to Burst Mode operation. It provides higher low current
efficiency than forced continuous mode, but not nearly as
high as Burst Mode operation.
Frequency Selection and Phase-Locked Loop (FREQ
and PLLIN/MODE Pins)
The selection of switching frequency is a trade-off between
efficiency and component size. Low frequency operation
increases efficiency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
The switching frequency of the LTC3897-2’s controllers
can be selected using the FREQ pin.
If the PLLIN/MODE pin is not being driven by an external
clock source, the FREQ pin can be tied to GND, tied to
INTVCC, or programmed through an external resistor. Tying
FREQ to GND selects 350kHz while tying FREQ to INTVCC
selects 535kHz. Placing a resistor between FREQ and GND
allows the frequency to be programmed between 50kHz
and 550kHz, as shown in Figure 7.
A phase-locked loop (PLL) is available on the LTC3897-2
to synchronize the internal oscillator to an external clock
source that is connected to the PLLIN/MODE pin. The
LTC3897-2’s phase detector adjusts the voltage (through
an internal lowpass filter) of the VCO input to align the
turn-on of the first controller’s external bottom MOSFET
to the rising edge of the synchronizing signal. Thus, the
turn-on of the second controller’s external bottom MOSFET
is 180 or 240 degrees out-of-phase to the rising edge of
the external clock source.
The VCO input voltage is prebiased to the operating
frequency set by the FREQ pin before the external clock
is applied. If prebiased near the external clock frequency,
the PLL loop only needs to make slight changes to the
VCO input in order to synchronize the rising edge of the
external clock’s to the rising edge of BG1. The ability to
prebias the loop filter allows the PLL to lock-in rapidly
without deviating far from the desired frequency.
The typical capture range of the LTC3897-2’s PLL is from
approximately 55kHz to 600kHz, and is guaranteed to lock
to an external clock source whose frequency is between
75kHz and 550kHz.
The typical input clock thresholds on the PLLIN/MODE
pin are 1.6V (rising) and 1.2V (falling). The recommended
maximum amplitude for low level and minimum amplitude
for high level of external clock are 0V and 2.5V, respectively.
PolyPhase Applications (CLKOUT and PHASMD Pins)
The LTC3897-2 features two pins, CLKOUT and PHASMD,
that allow other controller ICs to be daisy chained with the
LTC3897-2 in PolyPhase applications. The clock output
signal on the CLKOUT pin can be used to synchronize
additional power stages in a multiphase power supply
solution feeding a single, high current output or multiple
separate outputs. The PHASMD pin is used to adjust the
phase of the CLKOUT signal as well as the relative phases
between the two internal controllers, as summarized in
Table 2. The phases are calculated relative to the zero
degrees phase being defined as the rising edge of the
bottom gate driver output of controller 1 (BG1). Depending
on the phase selection, a PolyPhase application with multiple LTC3897-2s can be configured for 2-, 3-, 4- , 6- and
12-phase operation.
Table 2.
VPHASMD
CONTROLLER 2 PHASE
CLKOUT PHASE
GND
180°
60°
Floating
180°
90°
INTVCC
240°
120°
CLKOUT is disabled when the controller is in shutdown
or in sleep mode.
Rev. A
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17
LTC3897-2
OPERATION
Boost Controller Operation When VIN > Regulated VOUT
When the input voltage to the boost channel rises above
the regulated VOUT voltage, the boost controller can behave
differently depending on the mode, inductor current and
VIN voltage. In forced continuous mode, the loop works
to keep the top MOSFET on continuously once VIN rises
above VOUT. The internal charge pump delivers current to
the boost capacitor to maintain a sufficiently high TG voltage. The amount of current the charge pump can deliver
is characterized by two curves in the Typical Performance
Characteristics section.
In pulse-skipping mode, if VIN is greater than the regulated
VOUT voltage, TG turns on if the inductor current rises
above a certain threshold and turns off if the inductor
current falls below this threshold. This threshold current
is set to approximately 6%, 4% or 3% of the maximum
ILIM current when the ILIM pin is grounded, floating or tied
to INTVCC, respectively. If the controller is programmed
to Burst Mode operation under this same VIN condition,
then TG remains off regardless of the inductor current.
Operation at Low SENSE Pin Common Mode Voltage
The current comparator in the LTC3897-2 is powered
directly from the SENSE+ pin. This enables the common
mode voltage of the SENSE+ and SENSE– pins to operate
at as low as 2.3V, which is below the UVLO threshold. The
figure on the first page shows a typical application in which
the controller’s VBIAS is powered from VOUT while the VIN
supply can go as low as 2.3V. If the voltage on SENSE+
drops below 2.3V, the SS pin will be held low. When the
SENSE voltage returns to the normal operating range, the
SS pin will be released, initiating a new soft-start cycle.
BOOST Supply Refresh and Internal Charge Pump
Each top MOSFET driver is biased from the floating
bootstrap capacitor, C B , which normally recharges
during each cycle through an internal switch when the
bottom MOSFET turns on. There are two considerations
for keeping the BOOST supply at the required bias level.
During start-up, if the bottom MOSFET is not turned on
within 100µs after UVLO goes low, the bottom MOSFET
will be forced to turn on for ~400ns. This forced refresh
18
generates enough BOOST-SW voltage to allow the top
MOSFET ready to be fully enhanced instead of waiting for
the initial few cycles to charge up. There is also an internal
charge pump that keeps the required bias on BOOST. The
charge pump always operates in both forced continuous
mode and pulse-skipping mode. In Burst Mode operation,
the charge pump is turned off during sleep and enabled
when the chip wakes up. The internal charge pump can
normally supply a charging current of 30µA.
Surge Stopper and Ideal Diode Controllers
The LTC3897-2 includes input/output protections that are
designed to suppress high voltage surges and limit the
input voltage of the boost controller and ensure normal
operation in high availability power systems. The LTC3897-2
drives an N-channel MOSFET MSG at the SG pin to limit
the voltage and current to the boost controller during
supply transients or overcurrent events. The LTC3897-2
also drives a second N-channel MOSFET MDG at the DG
pin as an ideal diode to protect the boost controller from
damage during reverse polarity input conditions, and to
block reverse current flow in the event the input collapses.
The LTC3897-2 operates from a wide range of VIN supply
voltage, from 4.2V to 75V. With a clamp limiting the VIN
supply, the input voltage may be higher than 75V. The
input supply can also be pulled below ground potential
by up to 40V without damaging the LTC3897-2. The low
power supply requirement of 4.2V allows it to operate even
during cold cranking conditions in automotive applications.
Normally, the pass device MSG is fully on, supplying current
to the load with very little power loss. If the input voltage
surges too high, the voltage amplifier (VA) controls the
gate of MSG and regulates the voltage at the IS– pin to
a level that is set by an external resistive divider (SFPB
pin) from the IS– pin to ground and the internal 1.235V
reference. The LTC3897-2 also detects an overcurrent
condition by monitoring the voltage across an external
sense resistor placed between the IS+ and IS– pins. An
active current limit circuit (IA) controls the gate of MSG to
limit the sense voltage to 50mV if IS– is above 2.5V. In the
case of a severe output overcurrent that brings IS– below
1.5V, the sense voltage is reduced to 27mV to reduce the
stress on MSG.
Rev. A
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LTC3897-2
OPERATION
During an overvoltage or overcurrent event, a current source
starts charging up the capacitor connected at the TMR pin
to ground. The pull-up current source in overcurrent condition is 5 times of that in overvoltage to accelerate turn-off.
The pass device MSG stays on and the TMR pin is further
charged up until it reaches 1.35V, at which point the SG
pin pulls low and turns off MSG. The fault timer allows the
load to continue functioning during brief transient events
while protecting the MOSFET from being damaged by a
long period of input overvoltage, such as load dump in
vehicles. The fault timer period decreases with the voltage
across the MOSFET, to help keep the MOSFET within its
safe operating area (SOA). MSG turns back on after a cool
down timer cycle.
the load, as compared to using a discrete blocking diode.
If MDG is driven fully on and the load current results in
more than 30mV of forward voltage, the forward voltage
is equal to RDS(ON) • ILOAD.
The source and drain of MOSFET MDG serve as the anode
and cathode of the ideal diode. The LTC3897-2 controls
the DG pin to maintain a 30mV forward voltage across the
drain and source terminals of MDG. It reduces the power
dissipation and increases the available supply voltage to
If the IS+ and IS– pins (and so the CS pin, through the
body diode of MDG) drops below GND, the SG pin is pulled
to the CS pin voltage, turning MSG off and shutting down
the forward current path.
In the event of an input short or a power supply failure,
reverse current temporarily flows through the MOSFET
MDG that is on. If the reverse voltage exceeds –30mV,
the LTC3897-2 pulls the DG pin low strongly and turns
off MDG, minimizing the disturbance at the output.
If the VIN pin drops below the GND pin voltage, the DG pin
is pulled to the CS pin voltage, keeping MDG off. When the
SG pin pulls low in any fault condition, the DG pin also
pulls low, so both pass devices are turned off.
Rev. A
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19
LTC3897-2
APPLICATIONS INFORMATION
The Typical Application on the first page is a basic
LTC3897-2 application circuit. The boost controller of
the LTC3897-2 can be configured to use either inductor
DCR (DC resistance) sensing or a discrete sense resistor
(RSENSE) for current sensing. The choice between the
two current sensing schemes is largely a design trade-off
between cost, power consumption and accuracy. DCR
sensing is becoming popular because it does not require
current sensing resistors and is more power-efficient,
especially in high current applications. However, current
sensing resistors provide the most accurate current limits
for the controller. Other external component selection
is driven by the load requirement, and begins with the
selection of RSENSE (if RSENSE is used) and inductor value.
Next, the power MOSFETs are selected. Finally, input and
output capacitors are selected. Note that the two controller
channels of the LTC3897-2 should be designed with the
same components.
current elsewhere can effectively add parasitic inductance
and capacitance to the current sense element, degrading
the information at the sense terminals and making the
programmed current limit unpredictable. If DCR sensing
is used (Figure 2b), resistor R1 should be placed close to
the switching node, to prevent noise from coupling into
sensitive small-signal nodes.
SENSE+ and SENSE– pins are rated at 65V abs max. If
input supply is expected to go above 65V, these pins
need to be protected using the surge protection voltage
regulator (SPFB pin).
VBIAS
(OPTIONAL)
SENSE–
LTC3897-2
BOOST
SENSE+ and SENSE– Pins
TG
The SENSE+ and SENSE– pins are the inputs to the current
SW
comparators. The common mode input voltage range of
the current comparators is 2.3V to 65V (abs max), allowing
the boost controller to operate from inputs over this full
range. The current sense resistor is normally placed at
the input of the boost controller in series with the inductor. The SENSE+ pin also provides power to the current
comparator. It draws ~250µA during normal operation.
There is a small base current of less than 1µA that flows
into the SENSE– pin. The high impedance SENSE– input
to the current comparators allows accurate DCR sensing
VOUT
BG
SGND
38972 F02a
(2a) Using a Resistor to Sense Current
VBIAS
VIN
SENSE+
C1
R2
DCR
R1
L
SENSE–
LTC3897-2
INDUCTOR
BOOST
TO SENSE FILTER,
NEXT TO THE CONTROLLER
TG
VOUT
SW
VIN
BG
INDUCTOR OR RSENSE
38972 F01
SGND
38972 F02b
Figure 1. Sense Lines Placement with
Inductor or Sense Resistor
PLACE C1 NEAR SENSE PINS
Filter components mutual to the sense lines should be
placed close to the LTC3897-2, and the sense lines should
run close together to a Kelvin connection underneath
the current sense element (shown in Figure 1). Sensing
20
VIN
SENSE+
L
(R1||R2) • C1 =
DCR
RSENSE(EQ) = DCR •
R2
R1 + R2
(2b) Using the Inductor DCR to Sense Current
Figure 2. Two Different Methods of Sensing Current
Rev. A
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LTC3897-2
APPLICATIONS INFORMATION
Sense Resistor Current Sensing
A typical sensing circuit using a discrete resistor is shown
in Figure 2a. RSENSE is chosen based on the required
output current.
The current comparator has a maximum threshold
VSENSE(MAX). When the ILIM pin is grounded, floating or
tied to INTVCC, the maximum threshold is set to 48mV,
95mV or 140mV, respectively. The current comparator
threshold sets the peak of the inductor current, yielding
a maximum average inductor current, IMAX, equal to the
peak value less half the peak-to-peak ripple current, ΔIL.
To calculate the sense resistor value, use the equation:
RSENSE =
VSENSE(MAX)
ΔI
IMAX + L
2
If the external R1||R2 • C1 time constant is chosen to be
exactly equal to the L/DCR time constant, the voltage drop
across the external capacitor is equal to the drop across
the inductor DCR multiplied by R2/(R1 + R2). R2 scales the
voltage across the sense terminals for applications where
the DCR is greater than the target sense resistor value.
To properly dimension the external filter components, the
DCR of the inductor must be known. It can be measured
using a good RLC meter, but the DCR tolerance is not
always the same and varies with temperature. Consult
the manufacturers’ data sheets for detailed information.
Using the inductor ripple current value from the inductor
value calculation section, the target sense resistor value is:
RSENSE(EQUIV) =
The actual value of IMAX for each channel depends on the
required output current IOUT(MAX) and can be calculated
using:
⎛ IOUT(MAX) ⎞ ⎛ VOUT ⎞
IMAX = ⎜
⎟•⎜
⎟
2
⎝
⎠ ⎝ VIN ⎠
When using the controller in low VIN and very high voltage
output applications, the maximum inductor current and
correspondingly the maximum output current level will
be reduced due to the internal compensation required to
meet stability criterion for boost regulators operating at
greater than 50% duty factor. A curve is provided in the
Typical Performance Characteristics section to estimate
this reduction in peak inductor current level depending
upon the operating duty factor.
Inductor DCR Sensing
For applications requiring the highest possible efficiency
at high load currents, the LTC3897-2 is capable of sensing
the voltage drop across the inductor DCR, as shown in
Figure 2b. The DCR of the inductor can be less than 1mΩ
for high current inductors. In a high current application
requiring such an inductor, conduction loss through a
sense resistor could reduce the efficiency by a few percent
compared to DCR sensing.
VSENSE(MAX)
ΔI
IMAX + L
2
To ensure that the application will deliver full load current
over the full operating temperature range, choose the
minimum value for the maximum current sense threshold
(VSENSE(MAX)).
Next, determine the DCR of the inductor. Where provided,
use the manufacturer’s maximum value, usually given at
20°C. Increase this value to account for the temperature
coefficient of resistance, which is approximately 0.4%/°C.
A conservative value for the maximum inductor temperature
(TL(MAX)) is 100°C.
To scale the maximum inductor DCR to the desired sense
resistor value, use the divider ratio:
RD =
RSENSE(EQUIV)
DCRMAX at TL(MAX)
C1 is usually selected to be in the range of 0.1µF to 0.47µF.
This forces R1|| R2 to around 2k, reducing error that might
have been caused by the SENSE– pin’s ±1µA current.
The equivalent resistance R1|| R2 is scaled to the room
temperature inductance and maximum DCR:
R1||R2 =
L
(DCR at 20°C)•C1
Rev. A
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21
LTC3897-2
APPLICATIONS INFORMATION
The resistor values are:
R1=
R1||R2
R1•RD
; R2 =
RD
1−RD
The maximum power loss in R1 is related to duty cycle,
and will occur in continuous mode at VIN = 1/2VOUT:
PLOSS_R1 =
(VOUT − VIN )• VIN
R1
Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
power loss when deciding whether to use DCR sensing or
sense resistors. Light load power loss can be modestly
higher with a DCR network than with a sense resistor,
due to the extra switching losses incurred through R1.
However, DCR sensing eliminates a sense resistor, reduces
conduction losses and provides higher efficiency at heavy
loads. Peak efficiency is about the same with either method.
Inductor Value Calculation
The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use of
smaller inductor and capacitor values. Why would anyone
ever choose to operate at lower frequencies with larger
components? The answer is efficiency. A higher frequency
generally results in lower efficiency because of MOSFET
gate charge and switching losses. Also, at higher frequency
the duty cycle of body diode conduction is higher, which
results in lower efficiency. In addition to this basic tradeoff, the effect of inductor value on ripple current and low
current operation must also be considered.
The inductor value has a direct effect on ripple current.
The inductor ripple current ΔIL decreases with higher
inductance or frequency and increases with higher VIN:
ΔIL =
VIN ⎛
V ⎞
⎜1− IN ⎟
f •L ⎝ VOUT ⎠
Accepting larger values of ΔIL allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ΔIL = 0.3(IMAX). The maximum
ΔIL occurs at VIN = 1/2VOUT.
22
The inductor value also has secondary effects. The transition
to Burst Mode operation begins when the average inductor
current required results in a peak current below 25% of
the current limit determined by RSENSE. Lower inductor
values (higher ΔIL) will cause this to occur at lower load
currents, which can cause a dip in efficiency in the upper
range of low current operation. In Burst Mode operation,
lower inductance values will cause the burst frequency to
decrease. Once the value of L is known, an inductor with
low DCR and low core losses should be selected.
Also, for high duty cycle and/or high output voltage applications (particularly those operating near the maximum
BG duty factor), it is recommended to keep the operating
frequency at 400kHz or less.
Power MOSFET Selection for the BOOST Controller
Two external power MOSFETs must be selected for each
phase of the boost controller in the LTC3897-2: one
N-channel MOSFET for the bottom (main) switch, and
one N-channel MOSFET for the top (synchronous) switch.
The peak-to-peak drive levels are set by the DRVCC voltage. This voltage can range from 5V to 10V depending on
configuration of the DRVSET pin. Therefore, both logic-level
and standard-level threshold MOSFETs can be used in
most applications depending on the programmed DRVCC
voltage. Pay close attention to the BVDSS specification for
the MOSFETs as well.
The LTC3897-2’s unique ability to adjust the gate drive
level between 5V to 10V (OPTI-DRIVE) allows an application circuit to be precisely optimized for efficiency. When
adjusting the gate drive level, the final arbiter is the total
input current for the regulator. If a change is made and the
input current decreases, then the efficiency has improved.
If there is no change in input current, then there is no
change in efficiency.
Selection criteria for the power MOSFETs include the
on-resistance RDS(ON), Miller capacitance CMILLER, input
voltage and maximum output current. Miller capacitance,
CMILLER, can be approximated from the gate charge curve
usually provided on the MOSFET manufacturer’s data
sheet. CMILLER is equal to the increase in gate charge
along the horizontal axis while the curve is approximately
Rev. A
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LTC3897-2
APPLICATIONS INFORMATION
flat divided by the specified change in VDS. This result is
then multiplied by the ratio of the application applied VDS
to the gate charge curve specified VDS. When the IC is
operating in continuous mode, the duty cycles for the top
and bottom MOSFETs are given by:
V −V
Main Switch Duty Cycle = OUT IN
VOUT
Synchronous Switch Duty Cycle =
VIN
VOUT
If the maximum output current is IOUT(MAX) and each
channel takes one half of the total output current, the
MOSFET power dissipations in each channel at maximum
output current are given by:
2
(VOUT − VIN )VOUT ⎛ IOUT(MAX) ⎞
PMAIN =
•⎜
⎟ • (1+δ)
2
V 2 IN
⎝
⎠
• RDS(ON) +k • VOUT 3 •
IOUT(MAX)
2 • VIN
• CMILLER • f
2
VIN ⎛ IOUT(MAX) ⎞
PSYNC =
•⎜
⎟ • (1+δ) •RDS(ON)
VOUT ⎝
2
⎠
where σ is the temperature dependency of R DS(ON)
(approximately 1Ω). The constant k, which accounts for
the loss caused by reverse recovery current, is inversely
proportional to the gate drive current and has an empirical value of 1.7.
Both MOSFETs have I2R losses while the bottom N-channel
equation includes an additional term for transition losses,
which are highest at low input voltages. For high VIN the
high current efficiency generally improves with larger
MOSFETs, while for low VIN the transition losses rapidly
increase to the point that the use of a higher RDS(ON) device
with lower CMILLER actually provides higher efficiency.
The synchronous MOSFET losses are greatest at high
input voltage when the bottom switch duty factor is low
or during overvoltage when the synchronous switch is on
close to 100% of the period.
The term (1 + σ) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs Temperature curve, but
σ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
Boost Converter CIN and COUT Selection
The input ripple current in a boost converter is relatively
low (compared with the output ripple current), because
this current is continuous. The voltage rating of the input
capacitor CIN at the input end of the boost converter
should comfortably exceed the maximum input voltage.
Although ceramic capacitors can be relatively tolerant of
overvoltage conditions, aluminum electrolytic capacitors
are not. Be sure to characterize the input voltage for any
possible overvoltage transients that could apply excess
stress to the input capacitors.
The value of CIN is a function of the source impedance, and
in general, the higher the source impedance, the higher the
required input capacitance. The required amount of input
capacitance is also greatly affected by the duty cycle. High
output current applications that also experience high duty
cycles can place great demands on the input supply, both
in terms of DC current and ripple current.
In a boost converter, the output has a discontinuous current,
so COUT must be capable of reducing the output voltage
ripple. The effects of ESR (equivalent series resistance) and
the bulk capacitance must be considered when choosing
the right capacitor for a given output ripple voltage. The
steady ripple voltage due to charging and discharging
the bulk capacitance in a single phase boost converter
is given by:
VRIPPLE =
IOUT(MAX) •(VOUT − VIN(MIN) )
COUT • VOUT • f
V
where COUT is the output filter capacitor.
The steady ripple due to the voltage drop across the ESR
is given by:
ΔVESR = IL(MAX) • ESR
Rev. A
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LTC3897-2
The LTC3897-2’s boost controller is configured as a
2-phase single output converter where the outputs of the
two channels are connected together and both channels
have the same duty cycle. With 2-phase operation, the
two channels are operated 180 degrees out-of-phase.
This effectively interleaves the output capacitor current
pulses, greatly reducing the output capacitor ripple current.
As a result, the ESR requirement of the capacitor can be
relaxed. Because the ripple current in the output capacitor
is a square wave, the ripple current requirements for the
output capacitor depend on the duty cycle, the number
of phases and the maximum output current. Figure 3
illustrates the normalized output capacitor ripple current
as a function of duty cycle in a 2-phase configuration. To
choose a ripple current rating for the output capacitor,
first establish the duty cycle range based on the output
voltage and range of input voltage. Referring to Figure 3,
choose the worst-case high normalized ripple current as
a percentage of the maximum load current.
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, aluminum electrolytic and
ceramic capacitors are all available in surface mount
packages. Ceramic capacitors have excellent low ESR
characteristics but can have a high voltage coefficient.
Capacitors are now available with low ESR and high ripple
current ratings (e.g., OS-CON and POSCAP).
24
IORIPPLE /IOUT
APPLICATIONS INFORMATION
3.25
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
0.1
1-PHASE
2-PHASE
0.2
0.3 0.4 0.5 0.6 0.7 0.8
DUTY CYCLE OR (1-VIN /VOUT)
0.9
38972 F03
Figure 3. Normalized Output Capacitor Ripple
Current (RMS) for a Boost Converter
PolyPhase Operation
For output loads that demand high current, multiple
LTC3897-2s can be cascaded to run out-of-phase to provide
more output current and at the same time to reduce input
and output voltage ripple. The PLLIN/MODE pin allows the
LTC3897-2 to synchronize to the CLKOUT signal of another
LTC3897-2. The CLKOUT signal can be connected to the
PLLIN/MODE pin of the following LTC3897-2 stage to line
up both the frequency and the phase of the entire system.
Tying the PHASMD pin to INTVCC, SGND or floating
generates a phase difference (between PLLIN/MODE and
CLKOUT) of 240°, 60° or 90°, respectively, and a phase
difference (between CH1 and CH2) of 120°, 180°or 180°.
Figure 4 shows the connections necessary for 3-, 4-, 6- or
12-phase operation. A total of 12 phases can be cascaded to
run simultaneously out-of-phase with respect to each other.
Rev. A
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LTC3897-2
APPLICATIONS INFORMATION
0°, 240°
VOUT
PLLIN/MODE CLKOUT
PHASMD
LTC3897-2
VFB
120°, CHANNEL 2 NOT USED
+120°
PLLIN/MODE CLKOUT
PHASMD
LTC3897-2
SS
RUN
VFB
ITH
SS
RUN
ITH
INTVCC
(4a) 3-Phase Operation
0°, 180°
VOUT
PHASMD
LTC3897-2
VFB
90°, 270°
+90°
PLLIN/MODE CLKOUT
PLLIN/MODE CLKOUT
PHASMD
LTC3897-2
SS
RUN
VFB
ITH
SS
RUN
ITH
(4b) 4-Phase Operation
0°, 180°
VOUT
PHASMD
LTC3897-2
VFB
60°, 240°
+60°
PLLIN/MODE CLKOUT
PHASMD
LTC3897-2
SS
RUN
VFB
ITH
120°, 300°
+60°
PLLIN/MODE CLKOUT
PLLIN/MODE CLKOUT
PHASMD
LTC3897-2
SS
RUN
VFB
ITH
SS
RUN
ITH
(4c) 6-Phase Operation
0°, 180°
VOUT
PLLIN/MODE CLKOUT
PHASMD
LTC3897-2
VFB
RUN
VFB
ITH
210°, 30°
PHASMD
LTC3897-2
SS
RUN
ITH
60°, 240°
PLLIN/MODE CLKOUT
PHASMD
LTC3897-2
SS
PLLIN/MODE CLKOUT
VFB
+60°
+60°
RUN
VFB
ITH
270°, 90°
PHASMD
LTC3897-2
120°, 300°
PLLIN/MODE CLKOUT
PHASMD
LTC3897-2
SS
PLLIN/MODE CLKOUT
VFB
+60°
+60°
SS
RUN
ITH
(4d) 12-Phase Operation
+90°
SS
RUN
ITH
330°, 150°
PLLIN/MODE CLKOUT
PHASMD
LTC3897-2
VFB
SS
RUN
ITH
38972 F04
Figure 4. PolyPhase Operation
Rev. A
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25
LTC3897-2
APPLICATIONS INFORMATION
Setting Output Voltage
DRVCC and INTVCC Regulators (OPTI-DRIVE)
The LTC3897-2 output voltage is set by an external feedback resistor divider carefully placed across the output,
as shown in Figure 5. The regulated output voltage is
determined by:
The LTC3897-2 features two separate internal P-channel
low dropout linear regulators (LDO) that supply power
at the DRVCC pin from either the VBIAS supply pin or the
EXTVCC pin depending on the connections of the EXTVCC
and DRVSET pins. A third P-channel LDO supplies power
at the INTVCC pin from the DRVCC pin. DRVCC powers the
gate drivers whereas INTVCC powers much of the LTC38972’s internal circuitry. The VBIAS LDO and the EXTVCC LDO
regulate DRVCC between 5V to 10V, depending on how
the DRVSET pin is set. Each of these LDOs can supply a
peak current of at least 50mA and must be bypassed to
ground with a minimum of 4.7µF ceramic capacitor. Good
bypassing is needed to supply the high transient currents
required by the MOSFET gate drivers and to prevent interaction between the channels. The INTVCC supply must be
bypassed with a 0.1µF ceramic capacitor.
Great care should be taken to route the VFB line away from
noise sources, such as the inductor or the SW line. Also keep
the VFB node as small as possible to avoid noise pickup.
VOUT
RB
LTC3897-2
VFB
RA
38972 F05
Figure 5. Setting Output Voltage
Soft-Start (SS Pin)
The start-up of VOUT is controlled by the voltage on the
SS pin. When the voltage on the SS pin is less than the
internal 1.2V reference, the LTC3897-2 regulates the VFB
pin voltage to the voltage on the SS pin instead of 1.2V.
Soft-start is enabled by simply connecting a capacitor from
the SS pin to ground, as shown in Figure 6. An internal
10µA current source charges the capacitor, providing a
linear ramping voltage at the SS pin. The LTC3897-2 will
regulate the VFB pin (and hence, VOUT) according to the
voltage on the SS pin, allowing VOUT to rise smoothly
from VIN to its final regulated value. The total soft-start
time will be approximately:
t SS = C SS •
The DRVSET pin programs the DRVCC supply voltage.
Tying the DRVSET pin to INTVCC programs DRVCC to 10V.
Tying the DRVSET pin to GND programs DRVCC to 6V.
By placing a 50k to 100k resistor between DRVSET and
GND the DRVCC voltage can be programmed between 5V
to 10V, as shown in Figure 7.
11
10
DRVCC VOLTAGE (V)
⎛ R ⎞
VOUT =1.2V ⎜1+ B ⎟
⎝ RA ⎠
9
8
7
6
5
4
1.2V
50 55 60 65 70 75 80 85 90 95 100
DRVSET PIN RESISTOR (kΩ)
38972 F07
10µA
Figure 7. Relationship Between DRVCC
Voltage and Resistor Value at DRVSET Pin
LTC3897-2
SS
CSS
SGND
38972 F06
Figure 6. Using the SS Pin to Program Soft-Start
26
Rev. A
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APPLICATIONS INFORMATION
High voltage applications in which large MOSFETs are
being driven at high frequencies may cause the maximum junction temperature rating for the LTC3897-2 to
be exceeded. The DRVCC current, which is dominated by
the gate charge current, may be supplied by either the
VBIAS LDO or the EXTVCC LDO. When the voltage on the
EXTVCC pin is less than its switchover threshold (4.7V or
7.7V as determined by the DRVUV pin), the VBIAS LDO is
enabled. Power dissipation for the IC in this case is highest
and is equal to VBIAS • IDRVCC. The gate charge current
is dependent on operating frequency as discussed in the
Efficiency Considerations section. The junction temperature
can be estimated by using the equations given in Note 2
of the Electrical Characteristics. For example, using the
LTC3897-2 in the QFN package and setting DRVCC to 6V,
the DRVCC current is limited to less than 47mA from a
40V supply when not using the EXTVCC supply at a 70°C
ambient temperature:
LDO than is specified, an external Schottky diode can be
added between the EXTVCC and DRVCC pins. In this case,
do not apply more than 10V to the EXTVCC pin and make
sure that EXTVCC ≤ VBIAS. Significant thermal gains can
be realized by powering DRVCC from an external supply.
Tying the EXTVCC pin to an 8.5V supply reduces the junction
temperature in the previous example from 125°C to 74°C:
TJ = 70°C + (47mA)(8.5V – 6V)(34°C/W) = 74°C
and from 125°C to 74°C in an FE package:
TJ = 70°C + (57mA)(8.5V – 6V)(34°C/W) = 74°C
The following list summarizes two possible connections
for EXTVCC:
1. EXTVCC grounded. This will cause DRVCC to be powered
from the internal VBIAS regulator resulting in an efficiency
penalty of up to 10% at high input voltages.
In the FE package, , the DRVCC current is limited to less
than 57mA from a 40V supply when not using the EXTVCC
supply at a 70°C ambient temperature:
2. EXTVCC connected to an external supply. If an external
supply is available in the 5V to 14V range, it may be
used to power EXTVCC providing it is compatible with
the MOSFET gate drive requirements. Ensure that
EXTVCC ≤ VBIAS.
TJ = 70°C + (57mA)(40V – 6V)(28°C/W) = 125°C
Topside MOSFET Driver Supply (CB)
To prevent the maximum junction temperature from being
exceeded, the VBIAS supply current must be checked while
operating in forced continuous mode (PLLIN/MODE =
INTVCC) at maximum VBIAS.
External bootstrap capacitors, CB, connected to the BOOST
pins supply the gate drive voltage for the topside MOSFET.
The LTC3897-2 features an internal switch between DRVCC
and the BOOST pin for each controller. These internal
switches eliminate the need for external bootstrap diodes
between DRVCC and BOOST. Capacitor CB in the Functional
Diagram is charged through this internal switch from DRVCC
when the SW pin is low. When the topside MOSFET is to
be turned on, the driver places the CB voltage across the
gate-source of the MOSFET. This enhances the top MOSFET
switch and turns it on. The switch node voltage, SW,
rises to VIN and the BOOST pin follows. With the topside
MOSFET on, the boost voltage is above the input supply:
VBOOST = VIN + VDRVCC (VBOOST = VOUT + VDRVCC for the
boost controller). The value of the boost capacitor, CB,
needs to be 100 times that of the total input capacitance
of the topside MOSFET(s).
TJ = 70°C + (47mA)(40V – 6V)(34°C/W) = 125°C
When the voltage applied to EXTVCC rises above its switch
over threshold, the VBIAS LDO is turned off and the EXTVCC
LDO is enabled. The EXTVCC LDO remains on as long as the
voltage applied to EXTVCC remains above the switchover
threshold minus the comparator hysteresis. The EXTVCC
LDO attempts to regulate the DRVCC voltage to the voltage
as programmed by the DRVSET pin, so while EXTVCC is
less than this voltage, the LDO is in dropout and the DRVCC
voltage is approximately equal to EXTVCC. When EXTVCC
is greater than the programmed voltage, up to an absolute
maximum of 14V, DRVCC is regulated to the programmed
voltage. If more current is required through the EXTVCC
Rev. A
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27
LTC3897-2
APPLICATIONS INFORMATION
The LTC3897-2 has an internal phase-locked loop (PLL)
comprised of a phase frequency detector, a lowpass filter
and a voltage-controlled oscillator (VCO). This allows the
turn-on of the bottom MOSFET of channel 1 to be locked
to the rising edge of an external clock signal applied to
the PLLIN/MODE pin. The turn-on of channel 2’s bottom
MOSFET is thus 180 degrees out-of-phase with the external
clock. The phase detector is an edge-sensitive digital type
that provides zero degrees phase shift between the external
and internal oscillators. This type of phase detector does
not exhibit false lock to harmonics of the external clock.
If the external clock frequency is greater than the internal
oscillator’s frequency, fOSC, then current is sourced continuously from the phase detector output, pulling up the VCO
input. When the external clock frequency is less than fOSC,
current is sunk continuously, pulling down the VCO input.
If the external and internal frequencies are the same but
exhibit a phase difference, the current sources turn on for
an amount of time corresponding to the phase difference.
The voltage at the VCO input is adjusted until the phase
and frequency of the internal and external oscillators are
identical. At the stable operating point, the phase detector
output is high impedance and the internal filter capacitor,
CLP , holds the voltage at the VCO input.
Typically, the external clock (on the PLLIN/MODE pin) input
high threshold is 1.6V, while the input low threshold is 1.2V.
Note that the LTC3897-2 can only be synchronized to
an external clock whose frequency is within range of the
LTC3897-2’s internal VCO, which is nominally 55kHz
to 600kHz. This is guaranteed to be between 75kHz
and 550kHz.
Rapid phase locking can be achieved by using the FREQ pin
to set a free-running frequency near the desired synchronization frequency. The VCO’s input voltage is prebiased
at a frequency corresponding to the frequency set by the
FREQ pin. Once prebiased, the PLL only needs to adjust
the frequency slightly to achieve phase lock and synchronization. Although it is not required that the free-running
frequency be near external clock frequency, doing so will
prevent the operating frequency from passing through a
large range of frequencies as the PLL locks.
28
Table 3 summarizes the different states in which the FREQ
pin can be used.
Table 3.
FREQ PIN
PLLIN/MODE PIN
FREQUENCY
0V
DC Voltage
350kHz
INTVCC
DC Voltage
550kHz
Resistor
DC Voltage
50kHz to 550kHz
Any of the Above
External Clock
Phase Locked to
External Clock
700
600
FREQUENCY (kHz)
Phase-Locked Loop and Frequency Synchronization
500
400
300
200
100
0
15
25
35
45
55
65
75
85
38972 F08
FREQ PIN RESISTOR (kΩ)
Figure 8. Relationship Between Oscillator
Frequency and Resistor Value at the FREQ Pin
Minimum On-Time Considerations
Minimum on-time, tON(MIN), is the smallest time duration
that the LTC3897-2 is capable of turning on the bottom
MOSFET. It is determined by internal timing delays and
the gate charge required to turn on the top MOSFET. Low
duty cycle applications may approach this minimum ontime limit.
In forced continuous mode, if the duty cycle falls below
what can be accommodated by the minimum on-time,
the controller will begin to skip cycles but the output will
continue to be regulated. More cycles will be skipped when
VIN increases. Once VIN rises above VOUT, the loop keeps
the top MOSFET continuously on. The minimum on-time
for the LTC3897-2 is approximately 90ns.
Rev. A
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LTC3897-2
APPLICATIONS INFORMATION
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the greatest improvement. Percent efficiency
can be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc., are the individual losses as a percentage of input power.
Although all dissipative elements in the circuit produce
losses, five main sources usually account for most of
the losses in LTC3897-2 circuits: 1) IC VBIAS current, 2)
DRVCC regulator current, 3) I2R losses, 4) bottom MOSFET
transition losses, 5) body diode conduction losses.
1. The VBIAS current is the DC supply current given in the
Electrical Characteristics table, which excludes MOSFET
driver and control currents. VBIAS current typically results
in a small ( tr simplifying the above to:
1
2
P 2t = ILOAD2 ( VPK – VREG ) τ
2
For the transient conditions of VPK = 80V, VIN = 12V, VREG=
16V, tr = 10µs and τ = 1ms, and a load current of 3A,
P2t is 18.4W2s—easily handled by a MOSFET in a D-pak
package. The P2t of other transient waveshapes is evaluated by integrating the square of MOSFET power versus
time. LTspice® can be used to simulate timer behavior for
more complex transients and cases where overvoltage
and overcurrent faults coexist.
Overcurrent Stress for MSG
SOA stress of MSG must also be calculated for output
overcurrent conditions. Short-circuit P2t is given by:
2
⎛
ΔV ⎞
P t = ⎜ VIN • IS ⎟ • tOC
R ⎠
⎝
2
IS
where ΔVIS is the overcurrent fault threshold and tOC is
the overcurrent timer interval.
34
For VIN = 15V, IS– = 0V, ΔVIS = 25mV, RIS = 12mΩ and
CTMR = 100nF, P2t is 2.2W2s—less than the transient
SOA calculated in the previous example. Nevertheless,
to account for circuit tolerances this figure should be
doubled to 4.4W2s.
Checking Transient Response (Boost Controller)
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, VOUT shifts by an
amount equal to ΔILOAD(ESR), where ESR is the effective
series resistance of COUT. ΔILOAD also begins to charge or
discharge COUT generating the feedback error signal that
forces the regulator to adapt to the current change and
return VOUT to its steady-state value. During this recovery
time VOUT can be monitored for excessive overshoot
or ringing, which would indicate a stability problem.
OPTI‑LOOP® compensation allows the transient response
to be optimized over a wide range of output capacitance
and ESR values. The availability of the ITH pin not only
allows optimization of control loop behavior, but it also
provides a DC coupled and AC filtered closed loop response
test point. The DC step, rise time and settling at this test
point truly reflects the closed loop response. Assuming a
predominantly second order system, phase margin and/
or damping factor can be estimated using the percentage
of overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin. The ITH
external components shown in the Figure 10 circuit will
provide an adequate starting point for most applications.
The ITH series RC – CC filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
to optimize transient response once the final PC layout
is complete and the particular output capacitor type and
value have been determined. The output capacitors must
be selected because the various types and values determine
the loop gain and phase. An output current pulse of 20%
to 80% of full-load current having a rise time of 1µs to
10µs will produce output voltage and ITH pin waveforms
that will give a sense of the overall loop stability without
breaking the feedback loop.
Rev. A
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LTC3897-2
APPLICATIONS INFORMATION
Placing a power MOSFET and load resistor directly
across the output capacitor and driving the gate with an
appropriate signal generator is a practical way to produce
a realistic load step condition. The initial output voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
is why it is better to look at the ITH pin signal which is in
the feedback loop and is the filtered and compensated
control loop response.
The gain of the loop will be increased by increasing
RC and the bandwidth of the loop will be increased by
decreasing CC. If RC is increased by the same factor that
CC is decreased, the zero frequency will be kept the same,
thereby keeping the phase shift the same in the most
critical frequency range of the feedback loop. The output
voltage settling behavior is related to the stability of the
closed-loop system and will demonstrate the actual overall
supply performance.
A second, more severe transient is caused by switching
in loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT , causing a rapid drop in VOUT . No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
CLOAD to COUT is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited to
approximately 25 • CLOAD. Thus, a 10µF capacitor would
require a 250µs rise time, limiting the charging current
to about 200mA.
Boost Converter Design Example
As a design example, assume VIN = 12V (nominal), VIN = 22V
(max), VOUT = 24V, IOUT(MAX) = 8A, VSENSE(MAX) = 95mV,
and f = 350kHz.
The components are designed based on single channel
operation. The inductance value is chosen first based on a
30% ripple current assumption. Tie the FREQ pin to GND,
generating 350kHz operation. The minimum inductance
for 30% ripple current is:
The largest ripple happens when VIN = 1/2VOUT = 12V,
where the average maximum inductor current for each
channel is:
⎛ IOUT(MAX) ⎞ ⎛ VOUT ⎞
IMAX = ⎜
⎟•⎜
⎟ = 8A
2
⎝
⎠ ⎝ VIN ⎠
A 6.8µH inductor will produce a 31% ripple current. The
peak inductor current will be the maximum DC value plus
one half the ripple current, or 9.25A.
The RSENSE resistor value can be calculated by using the
maximum current sense voltage specification with some
accommodation for tolerances:
RSENSE ≤
75mV
= 0.008Ω
9.25A
Choosing 1% resistors: RA = 24.9k and RB = 475k yields
an output voltage of 24.092V.
The power dissipation on the top side MOSFET in each channel can be easily estimated. Choosing a Vishay Si7848BDP
MOSFET results in: RDS(ON) = 0.012Ω, CMILLER = 150pF.
At maximum input voltage with T (estimated) = 50°C:
PMAIN =
(24V – 12V) 24V
2
(12V)
•(4A)2
• [1+(0.005)(50°C – 25°C)] • 0.008Ω
+ (1.7)(24V)3
4A
(150pF)(350kHz)= 0.7W
12V
COUT is chosen to filter the square current in the output.
The maximum output current peak is:
⎛ 31% ⎞
IOUT(PEAK) = 8 • ⎜1+
⎟ = 9.3A
⎝
2 ⎠
A low ESR (5mΩ) capacitor is suggested. This capacitor
will limit output voltage ripple to 46.5mV (assuming ESR
dominate ripple).
Rev. A
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35
LTC3897-2
APPLICATIONS INFORMATION
+
D3
SMAJ24A
R2
10Ω
D2
1.5KE200A
R1
1.21k
0.5W
C1
0.1µF
RIS
10mΩ
MDG
FDB3682
MSG
FDB33N25
MAX DC:
100V/–24V VIN
MAX 1ms 12V
TRANSIENT:
200V
R3
100Ω
D4
1N4148W
VIN
CHG
0.1µF
SG
CS
IS+
DG
R5
104.3k
1%
IS–
SGEN
D1
CMZ5945B
68V
CL
22µF
VIN-BOOST
4A
CLAMPED AT 27V
SPFB
R4
4.99k
1%
LTC3897-2
DGEN
GND
TMR
38972 F14
CTMR
47nF
Figure 14. 4A, 12V Overvoltage and Reverse Current Protection
Surge Stopper and Ideal Diode Design Example
As a design example, consider an application with the
following specifications: VIN = 6V to 14V DC with a peak
transient of 200V and decay time constant τ of 1ms, input
to the boost controller VIN-BOOST ≤ 27V, minimum current
limit ILIM(MIN) at 4A, and 1ms of overvoltage early warning
(Figure 14).
Selection of CMZ5945B for D1 will limit the voltage at
the VIN pin to less than 71V during the 200V surge. The
minimum required voltage at the VIN pin is 4.2V when
input supply is at 6V; the supply current for LTC3897-2
is 1.3mA. The maximum value for R1 to ensure proper
operation is:
R1=
6V – 4.2V
1.3mA
= 1.4k
I D1(PK) =
1.1k
VREG =
= 124mA
1.235V • (R4+R5)
R4
= 27V
Choosing 250µA for the resistive divider:
1.235V
R4 =
250µA
= 5k
Select 4.99k for R4.
(27V – 1.235V) • R4
1.235V
= 104.3k
The closest standard value for R5 is 105k. Now, calculate
the sense resistor, RIS, value:
RIS =
which can be handled by the CMZ5945B with a peak power
rating of 200W at 10/1000µs.
36
Next, calculate the resistive divider value to limit VIN-BOOST
to 27V during an overvoltage event:
R5 =
Select 1.21k for R1 to accommodate all conditions. With the
minimum Zener voltage at 64V, the peak current through
R1 into D1 is then calculated as:
200V – 64V
With a bypass capacitance of 0.1µF (C1), along with R1
of 1.21k, high voltage transients up to 250V with a pulse
width less than 10µs are filtered out at the VIN pin.
ΔVIS(MIN)
ILIM
=
45mV
= 11mΩ
4A
Choose 10mΩ for RIS.
Rev. A
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APPLICATIONS INFORMATION
CTMR is then chosen for 1ms between when the TMR pin
reaches 1.25V and MSG turns off:
C TMR =
1ms • 5µA
100mV
= 50nF
The closest standard value for CTMR is 47nF. Note that if
the boost controller is enabled,the value of CTMR should
be small, such as 1nF, to limit the large current during an
output overcurrent event.
The pass device, MSG, should be chosen to withstand an
output overcurrent condition with VIN = 14V. In the case
of a severe output overcurrent event where VIN-BOOST =
0V, ITMR(UP) = 57µA and the total overcurrent fault time is:
t OC =
C TMR • VTMR(G)
ITMR(UP)
=
47nF • 1.35V
57µA
= 1.11mst
The maximum power dissipation in MSG is:
P=
ΔVDS(M1) • ΔVIS(MAX)
RIS
=
14V • 33mV
= 46.2W
10mΩ
The corresponding P2t is 2.7W2s.
During an output overload or soft short, the voltage at the
IS– pin could stay at 2V or higher. The total overcurrent
fault time when VIN-BOOST = 2V is:
t OC =
47nF • 1.35V
47µA
= 1.35ms
The maximum power dissipation in MSG is:
(14V – 2V)• 55mV
P=
= 66W
10mΩ
The corresponding P2t is 5.9W2s. Both of the above
conditions are well within the safe operating area of
FDB33N25.
To select the pass device, MDG, first calculate RDS(ON) to
achieve the desired forward drop VFW at maximum load
current (5.5A). If VFW = 0.25V:
RDS(ON) ≤
VFW
ILOAD(MAX )
=
The FDB3682 offers a maximum RDS(ON) of 36mΩ at
VGS = 10V so is a good fit. Its minimum BVDSS of 100V is
also sufficient to handle VIN-BOOST transients up to 100V
during an input short-circuit event.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. Figure 15 illustrates the current waveforms present in the various branches of the 2-phase synchronous
regulators operating in the continuous mode. Check the
following in your layout:
1. Put the bottom N-channel MOSFETs MBOT1 and MBOT2
and the top N-channel MOSFETs MTOP1 and MTOP2
in one compact area with COUT.
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return
of CIN must return to the combined COUT (–) terminals.
The path formed by the bottom N-channel MOSFET
and the capacitor should have short leads and PC trace
lengths. The output capacitor (–) terminals should be
connected as close as possible to the source terminals
of the bottom MOSFETs.
3. Does the LTC3897-2 VFB pin’s resistive divider connect
to the (+) terminal of COUT? The resistive divider must
be connected between the (+) terminal of COUT and
signal ground and placed close to the VFB pin. The
feedback resistor connections should not be along the
high current input feeds from the input capacitor(s).
4. Are the SENSE+ and SENSE– leads routed together with
minimum PC trace spacing? The filter capacitor between
SENSE+ and SENSE– should be as close as possible
to the IC. Ensure accurate current sensing with Kelvin
connections at the sense resistor.
5. Is the DRVCC and decoupling capacitor connected close
to the IC, between the DRVCC and the ground pin? This
capacitor carries the MOSFET drivers’ current peaks.
0.25V
= 45.5mΩ
5.5A
Rev. A
For more information www.analog.com
37
LTC3897-2
APPLICATIONS INFORMATION
6. Keep the switching nodes (SW1, SW2), top gate (TG1,
TG2) and boost nodes (BOOST1, BOOST2) away
from sensitive small-signal nodes, especially from
the opposites channel’s voltage and current sensing
feedback pins. All of these nodes have very large and
fast moving signals and, therefore, should be kept on
the output side of the LTC3897-2 and occupy a minimal
PC trace area.
7. Use a modified “star ground” technique: a low impedance,
large copper area central grounding point on the same
side of the PC board as the input and output capacitors
with tie-ins for the bottom of the DRVCC decoupling
capacitor, the bottom of the voltage feedback resistive
divider and the GND pin of the IC.
RSENSE1
8. To achieve accurate current sensing for the IS+ and
IS– pins, use Kelvin connections to the current sense
resistor. Limit the resistance from the CS pin to the
sources of the MOSFETs to below 10Ω. The minimum
trace width for 1oz copper foil is 0.02" per amp to ensure
the trace stays at a reasonable temperature. Note that
1oz copper exhibits a sheet resistance of about 530µΩ/
square. Small resistances can cause large errors in high
current applications. Noise immunity will be improved
significantly by locating resistive dividers close to the
pins with short VIN and GND traces.
L1
SW1
VOUT
VIN
RIN
CIN
COUT
RSENSE2
BOLD LINES INDICATE
HIGH SWITCHING
CURRENT. KEEP LINES
TO A MINIMUM LENGTH.
RL
L2
SW2
38972 F15
Figure 15. BOOST Converter Branch Current Waveforms
38
Rev. A
For more information www.analog.com
LTC3897-2
APPLICATIONS INFORMATION
PC Board Layout Debugging
Start with one controller on at a time. It is helpful to use
a DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope
to the internal oscillator and probe the actual output voltage. Check for proper performance over the operating
voltage and current range expected in the application.
The frequency of operation should be maintained over the
input voltage range down to dropout and until the output
load drops below the low current operation threshold—
typically 10% of the maximum designed current level in
Burst Mode operation.
The duty cycle percentage should be maintained from cycle
to cycle in a well designed, low noise PCB implementation.
Variation in the duty cycle at a subharmonic rate can suggest noise pickup at the current or voltage sensing inputs
or inadequate loop compensation. Overcompensation of
the loop can be used to tame a poor PC layout if regulator
bandwidth optimization is not required. Only after each
controller is checked for its individual performance should
both controllers be turned on at the same time. A particularly difficult region of operation is when one controller
channel is nearing its current comparator trip point while
the other channel is turning on its bottom MOSFET. This
occurs around the 50% duty cycle on either channel due
to the phasing of the internal clocks and may cause minor
duty cycle jitter.
Reduce VIN from its nominal level to verify operation with
high duty cycle. Check the operation of the undervoltage
lockout circuit by further lowering VIN while monitoring
the outputs to verify operation.
Investigate whether any problems exist only at higher
output currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling.
An embarrassing problem which can be missed in an otherwise properly working switching regulator, results when
the current sensing leads are hooked up backwards. The
output voltage under this improper hook-up will still be
maintained, but the advantages of current mode control
will not be realized. Compensation of the voltage loop will
be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
the current sensing resistor—don’t worry, the regulator
will still maintain control of the output voltage.
Rev. A
For more information www.analog.com
39
LTC3897-2
APPLICATIONS INFORMATION
+
CINC
4.7µF
×3
CINB
56µF
DBIAS
VIN
6V TO 55V*
CINA
4.7µF
MSG
MDG
CBIAS
0.1µF
RIS
2mΩ
MBOT1
SPFB
+
CB1
0.1µF
BOOST1
CSG
10nF
IS–
IS+
DG
CS
SG
VIN
CSS, 0.1µF
CITH, 15nF
MTOP1
SENSE1+
SENSE1–
VBIAS
BG1
RC
12.1k
L1
22µH
DIN
LTC3897-2
RD
549k
RSG
10Ω
RSENSE1
6mΩ
VP
DTC
SS
RITH, 8.66k
SW1
TG1
SENSE2+
SENSE2–
BG2
BOOST2
ITH
CITHA, 15nF
RSENSE2
6mΩ
SW2
TG2
L2
22µH
INTVCC
DRVCC
DRVSET
DRVUV
FREQ
GND
VFB
SGEN
DGEN
RUN
TMR
VOUT
48V, 4A*
COUTB
4.7µF
×8
MTOP2
MBOT2
CB2
0.1µF
RB
475k
CINT, 1µF
CDRV
4.7µF
COUTA
56µF
RA
12.1k
CTMR
1nF
38972 F16
MSG: INFINEON IPB020N10N5
MDG: INFINEON BSC035N10NS
MBOT1, MBOT2, MTOP1, MTOP2: INFINEON BSC028N06NS
L1, L2: WURTH 7443632200
DIN: VISHAY ES1B-E3
DBIAS: DIODES INC DFLS1150-7
COUTA, CINB: PANASONIC EEHZA1J560P
COUTB, CINA, CINC: TDK C3225X7S2A475M
CBIAS: AVX 06035C104KAT2A
PINS NOT SHOWN IN THIS CIRCUIT:
PLLIN/MODE, ILIM, PHASMD, CLKOUT, EXTVCC
*WHEN VIN < 8V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED.
VIN OPERATES THROUGH TRANSIENTS UP TO 75V. WHEN VIN > 48V,
VOUT FOLLOWS VIN UP TO 57V.
Figure 16. High Efficiency 2-Phase 48V Boost Converter with In-Rush Current Control,
Overcurrent Protection, Input Voltage Surge Protection and Reverse Input Protection
40
Rev. A
For more information www.analog.com
LTC3897-2
APPLICATIONS INFORMATION
+
CINC
4.7µF
×3
CINB
56µF
DBIAS
VIN
6V TO 55V*
CINA
4.7µF
MSG
MDG
CBIAS
0.1µF
RIS
2mΩ
RSENSE1
5mΩ
VP
RSG
10Ω
SENSE1+
SENSE1–
VBIAS
MBOT1
BG1
SPFB
RC
12.1k
+
CB1
0.1µF
BOOST1
CSG
10nF
IS–
IS+
DG
CS
SG
VIN
CSS, 0.1µF
CITH, 4.7nF
MTOP1
DIN
LTC3897-2
RD
549k
L1
3.5µH
DTC
SS
RITH, 8.25k
SW1
TG1
SENSE2+
SENSE2–
BG2
BOOST2
ITH
CITHA, 220pF
RSENSE2
5mΩ
SW2
TG2
L2
3.5µH
INTVCC
DRVCC
DRVSET
DRVUV
FREQ
GND
VFB
SGEN
DGEN
RUN
TMR
VOUT
24V, 10A*
COUTB
4.7µF
×8
MTOP2
MBOT2
CB2
0.1µF
RB
475k
CINT, 1µF
CDRV
4.7µF
COUTA
56µF
RA
24.9k
CTMR
1nF
38972 F17
MSG: INFINEON IPB020N10N5
MDG: INFINEON BSC035N10NS
MBOT1, MBOT2, MTOP1, MTOP2: INFINEON BSC028N06NS
L1, L2: WURTH 7443556350
DIN: VISHAY ES1B-E3
DBIAS: DIODES INC DFLS1150-7
COUTA, CINB: PANASONIC EEHZA1J560P
COUTB, CINA, CINC: TDK C3225X7S2A475M
CBIAS: AVX 06035C104KAT2A
PINS NOT SHOWN IN THIS CIRCUIT:
PLLIN/MODE, ILIM, PHASMD, CLKOUT, EXTVCC
*WHEN VIN < 8V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED.
VIN OPERATES THROUGH TRANSIENTS UP TO 75V. WHEN VIN > 24V,
VOUT FOLLOWS VIN UP TO 57V.
Figure 17. High Efficiency 2-Phase 24V Boost Converter with In-Rush Current Control,
Overcurrent Protection, Input Voltage Surge Protection and Reverse Input Protection
Rev. A
For more information www.analog.com
41
LTC3897-2
TYPICAL APPLICATIONS
High Efficiency 2-Phase 24V Boost Converter
(Input Supply Down to 2.3V After Start Up)
VIN
6V TO 55V*
DOWN TO 2.3V
AFTER START-UP
+
RSENSE1
5mΩ
VP
CINA
56µF
CINB
4.7µF
×3
CBIAS
0.1µF
MBOT1
LTC3897-2
DG
CS
SG
VIN
DTC
CSS, 0.1µF
SS
RITH, 8.25k
CITHA, 220pF
BG1
CB1
0.1µF
+
BOOST1
SW1
TG1
SENSE2+
SENSE2–
BG2
BOOST2
ITH
SW2
TG2
RSENSE2
5mΩ
L2
3.5µH
INTVCC
DRVCC
DRVSET
DRVUV
FREQ
GND
VFB
SGEN
DGEN
RUN
TMR
COUTA
56µF
VOUT
24V, 10A*
COUTB
4.7µF
×8
MTOP2
MBOT2
CB2
0.1µF
RB
475k
CINT, 1µF
CDRV
4.7µF
MTOP1
SENSE1+
SENSE1–
VBIAS
SPFB
IS–
IS+
CITH, 4.7nF
L1
3.5µH
RA
24.9k
CTMR
1nF
38972 TA02
MBOT1, MBOT2, MTOP1, MTOP2: INFINEON BSC028N06NS
L1, L2: WURTH 7443556350
COUTA, CINA: PANASONIC EEHZA1J560P
COUTB, CINB: TDK C3225X7S2A475M
CBIAS: AVX 06035C104KAT2A
PINS NOT SHOWN IN THIS CIRCUIT:
PLLIN/MODE, ILIM, PHASMD, CLKOUT, EXTVCC
*WHEN VIN < 8V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED.
WHEN VIN > 24V, VOUT FOLLOWS VIN UP TO 55V.
42
Rev. A
For more information www.analog.com
LTC3897-2
TYPICAL APPLICATIONS
High Efficiency 2-Phase 48V Boost Converter with In-Rush Current Control, Input Voltage Surge Protection and Overcurrent Protection
(Ideal Diode Controller Not Used)
+
CINC
4.7µF
×3
CINB
56µF
DBIAS
VIN
6V TO 55V*
CINA
4.7µF
MSG
CBIAS
0.1µF
RIS
2mΩ
RSENSE1
6mΩ
VP
MTOP1
DIN
SENSE1+
SENSE1–
VBIAS
MBOT1
LTC3897-2
BG1
SPFB
RSG
10Ω
L1
22µH
+
CB1
0.1µF
BOOST1
CSG
10nF
CSS, 0.1µF
CITH, 15nF
RITH, 8.66k
CITHA, 220pF
IS–
IS+
DG
CS
SG
VIN
DTC
SS
SW1
TG1
SENSE2+
SENSE2–
BG2
BOOST2
ITH
SW2
TG2
RSENSE2
6mΩ
L2
22µH
CDRV
4.7µF
DRVSET
DRVUV
DGEN FREQ
COUTB
4.7µF
×8
MTOP2
CB2
0.1µF
RB
475k
VFB
RA
12.1k
SGEN
RUN
TMR
GND
VOUT
48V, 4A*
MBOT2
CINT, 1µF
INTVCC
DRVCC
COUTA
56µF
CTMR
1nF
38972 TA03
MSG: INFINEON IPB020N10N5
MBOT1, MBOT2, MTOP1, MTOP2: INFINEON BSC028N06NS
L1, L2: WURTH 7443632200
DIN: VISHAY ES1B-E3
DBIAS: DIODES INC DFLS1150-7
COUTA, CINB: PANASONIC EEHZA1J560P
COUTB, CINA, CINC: TDK C3225X7S2A475M
CBIAS: AVX 06035C104KAT2A
PINS NOT SHOWN IN THIS CIRCUIT:
PLLIN/MODE, ILIM, PHASMD, CLKOUT, EXTVCC
*WHEN VIN < 8V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED.
VIN OPERATES THROUGH TRANSIENTS UP TO 75V. WHEN VIN > 48V,
VOUT FOLLOWS VIN UP TO 57V.
Rev. A
For more information www.analog.com
43
LTC3897-2
TYPICAL APPLICATIONS
High Efficiency 2-Phase 48V Boost Converter with Reverse Input Protection
(Surge Stopper Controller Not Used)
+
CINB
56µF
MDG
SPFB
MBOT1
LTC3897-2
BG1
CINA
4.7µF
IS–
IS+
DG
CS
SG
VIN
CSS, 0.1µF
CITH, 15nF
RITH, 8.66k
CITHA, 220pF
+
CB1
0.1µF
BOOST1
SW1
TG1
RSENSE2
6mΩ
SENSE2+
SENSE2–
DTC
SS
L2
22µH
COUTA
56µF
VOUT
48V, 4A*
COUTB
4.7µF
×8
MTOP2
MBOT2
BG2
BOOST2
ITH
SW2
TG2
CB2
0.1µF
RB
475k
CINT, 1µF
CDRV
4.7µF
MTOP1
SENSE1+
SENSE1–
VBIAS
VIN
6V TO 48V*
L1
22µH
CINC
4.7µF
×3
DBIAS
CBIAS
0.1µF
RSENSE1
6mΩ
VP
INTVCC
DRVCC
VFB
DRVSET
DRVUV
SGEN FREQ
RA
12.1k
DGEN
RUN
TMR
GND
38972 TA04
MDG: INFINEON BSC035N10NS
MBOT1, MBOT2, MTOP1, MTOP2: INFINEON BSC028N06NS
L1, L2: WURTH 7443632200
DBIAS: DIODES INC DFLS1150-7
COUTA, CINB: PANASONIC EEHZA1J560P
COUTB, CINA, CINC: TDK C3225X7S2A475M
CBIAS: AVX 06035C104KAT2A
PINS NOT SHOWN IN THIS CIRCUIT:
PLLIN/MODE, ILIM, PHASMD, CLKOUT, EXTVCC
*WHEN VIN < 8V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED.
44
Rev. A
For more information www.analog.com
LTC3897-2
TYPICAL APPLICATIONS
High Efficiency 2-Phase 48V Boost Converter with Overcurrent Protection
(Ideal Diode and Surge Stopper Controllers at the Output)
RSENSE1
6mΩ
+
VIN
6V TO 48V*
SPFB
MTOP1
CINC
4.7µF
×3
CINB
56µF
SENSE1+
SENSE1–
VBIAS
CINA
4.7µF
L1
22µH
MBOT1
LTC3897-2
BG1
IS+
IS–
MSG
+
CB1
0.1µF
BOOST1
DG
CS
SG
VIN
CSS, 0.1µF
CITH, 15nF
RITH, 8.66k
CITHA, 220pF
SENSE2+
RSENSE2
6mΩ
SENSE2–
DTC
SS
L2
22µH
RIS
5mΩ
DOUT
VOUT
48V
4A*
COUTC
4.7µF
×8
RSG
10Ω
CSG
10nF
BG2
BOOST2
ITH
SW2
TG2
INTVCC
DRVCC
DRVSET
DRVUV
FREQ
MTOP2
MBOT2
CB2
0.1µF
RB
475k
CINT, 1µF
CDRV
4.7µF
COUTA
56µF
COUTB
4.7µF
×8
SW1
TG1
MDG
GND
VFB
SGEN
DGEN
RUN
TMR
RA
12.1k
CTMR
1nF
38972 TA05
MSG: INFINEON IPB020N10N5
MDG: INFINEON BSC035N10NS
MBOT1, MBOT2, MTOP1, MTOP2: INFINEON BSC028N06NS
L1, L2: WURTH 7443632200
DOUT: VISHAY ES1B-E3
DBIAS: DIODES INC DFLS1150-7
COUTA, CINB: PANASONIC EEHZA1J560P
COUTB, COUTC, CINA, CINC: TDK C3225X7S2A475M
CBIAS: AVX 06035C104KAT2A
PINS NOT SHOWN IN THIS CIRCUIT:
PLLIN/MODE, ILIM, PHASMD, CLKOUT, EXTVCC
*WHEN VIN < 8V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED.
Rev. A
For more information www.analog.com
45
LTC3897-2
TYPICAL APPLICATIONS
Nonsynchronous 107V/1.5A 2-Phase Boost Converter with In-Rush Current Control,
Overcurrent Protection, Input Voltage Surge Protection and Reverse Input Protection
+
CINC
6.8µF
×3
CINB
47µF
DBIAS
VIN
8.5V TO 36V
CINA
4.7µF
MSG
MDG
CBIAS
0.1µF
RIS
2mΩ
RSENSE1
8mΩ
VP
L1
58µH
D1
DIN
SENSE1+
SENSE1–
VBIAS
LTC3897-2
RD
549k
RSG
10Ω
SPFB
RC
12.1k
BOOST1
CSG
10nF
IS–
IS+
DG
CS
SG
VIN
CSS, 0.1µF
CITH, 15nF
MBOT1
BG1
SW1
TG1
SENSE2+
COUTB
1µF
×8
D2
MBOT2
BG2
ITH
CITHA, 220pF
L2
58µH
COUTA
100µF
VOUT
107V, 1.5A
SENSE2–
DTC
SS
RITH, 8.66k
RSENSE2
8mΩ
+
BOOST2
SW2
CINT, 1µF
RB
576k
TG2
INTVCC
DRVSET
DRVUV
CDRV
4.7µF
VFB
DRVCC
FREQ
RA
6.65k
SGEN
DGEN
RUN
GND
TMR
CTMR
1nF
38972 TA06
MSG: INFINEON IPB020N10N5
MDG: INFINEON BSC035N10NS
MBOT1, MBOT2,: INFINEON BSC360N15NS
L1, L2: PULSE PA2050-583
D1, D2: DIODES INC PDS4150
DIN: VISHAY ES1B-E3
DBIAS: DIODES INC DFLS1150-7
COUTA: PANASONIC EEV-EB2D101M
COUTB: TDK C5750X7R2E105K230KM
CINB: SUNCON 63CE47LX
COUTB, CINA: TDK C3225X7S2A475M
CINC: TDK C4532X7R1H685K
CBIAS: AVX 06035C104KAT2A
PINS NOT SHOWN IN THIS CIRCUIT:
PLLIN/MODE, ILIM, PHASMD, CLKOUT, EXTVCC
46
Rev. A
For more information www.analog.com
LTC3897-2
PACKAGE DESCRIPTION
UHG Package
44(38)-Lead Plastic QFN (5mm × 8mm)
(Reference LTC DWG # 05-08-1616 Rev Ø)
0.70 ±0.05
5.50 ±0.05
3.50 REF
4.10 ±0.05
2.65 ±0.05
5.05 ±0.05
PACKAGE
OUTLINE
1.00 BSC
6.50 REF
7.10 ±0.05
8.50 ±0.05
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
5.00 ±0.10
PIN 1 NOTCH
0.35 × 45° CHAMFER
R = 0.125
TYP
DETAIL A
0.75 ± 0.05
43 44
0.00 – 0.05
0.40 ±0.10
PIN 1
TOP MARK
(SEE NOTE 6)
1
2
0.25 ±0.05
6.50 REF
8.00 ±0.10
0.50 BSC
5.05
±0.10
1.08
1.58
2.65 ±0.10
0.325 REF
0.200 REF
(UHG44(38)) QFN 1017 REV 0
3.50 REF
BOTTOM VIEW—EXPOSED PAD
0.75 ±0.05
0.31 REF
0.00 – 0.05
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
DETAIL A
0.08 REF
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
Rev. A
For more information www.analog.com
47
LTC3897-2
Page Intentionally Left Blank
48
Rev. A
For more information www.analog.com
LTC3897-2
REVISION HISTORY
REV
DATE
DESCRIPTION
A
01/20
Minor typo corrections
PAGE NUMBER
13, 14, 18,
32, 37
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
more by
information
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49
LTC3897-2
TYPICAL APPLICATION
4-Phase 480W Single Output Boost Regulator
IIN
CIN
12V
I1
INTVCC
0°
BG1
PLLIN/MODE
TG1
PHASMD
RUN
SS LTC3897-2
VFB
ITH
180°
BG2
TG2
CLKOUT
+90°
PLLIN/MODE
PHASMD
ITH
VFB
SS
RUN
I2
I2
BOOST: 24V, 5A
BG1
TG1
90°
LTC3897-2
I3
24V, 20A
I3
90,270
I1
BOOST: 24V, 5A
COUT
ICOUT
BOOST: 24V, 5A
I4
BG2
TG2
I4
270°
I*IN
BOOST: 24V, 5A
I*COUT
* RIPPLE CURRENT CANCELLATION INCREASES THE RIPPLE
FREQUENCY AND REDUCES THE RMS INPUT/OUTPUT RIPPLE
CURRENT, THUS SAVING INPUT/OUTPUT CAPACITORS
38972 TA07
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC3897
PolyPhase Synchronous Boost Controller with
Input/Output Protection in Smaller Packages
4.5V ≤ VIN ≤ 65V, 75V Peak, VOUT Up to 60V, PLL Fixed Frequency 75kHz to
550kHz, IQ = 55µA, TSSOP-38, 5mm × 7mm QFN-38
LTC3784
Low IQ, Multiphase, Dual Channel Single
4.5V (Down to 2.5V after Start-Up) ≤ VIN ≤ 60V, VOUT Up to 60V, PLL Fixed
Output Synchronous Step-Up DC/DC Controller Frequency 50kHz to 900kHz, IQ = 28µA
LTC3769
Low IQ Synchronous Step-Up DC/DC Controller 4.5V (Down to 2.5V After Start-Up) ≤ VIN ≤ 60V, VOUT Up to 60V, IQ = 28µA, PLL
Fixed Frequency 50kHz to 900kHz, 4mm x 4mm QFN-24, TSSOP-20E
LTC3899
Low IQ, Triple Output, Buck/Buck/Boost
Synchronous Controller
4.5V (Down to 2.5V After Start-Up) ≤ VIN ≤ 60V, Buck and Boost VOUT Up to
60V, IQ = 29µA, PLL Fixed Frequency 50kHz to 900kHz, 5mm x 7mm QFN-38,
TSSOP-38E
LTC4364
Surge Stopper with Ideal Diode
4V to 80V Operation, –40V Reverse Input, –20V Reverse Output
LTC4359
Ideal Diode Controller with Reverse Input
Protection
4V to 80V Operation, –40V Input Protection, 150µA IQ
LTC4366
Floating Surge Stopper
9V to > 500V Operation, 8-Pin TSOT and 3mm × 2mm DFN Packages
LTC3862/
LTC3862-1/
LTC3862-2
Multiphase Current Mode Step-Up DC/DC
Controller
2.5V ≤ VIN ≤ 32V, 5V or 10V Gate Drive, 75kHz to 500kHz, TSSOP-24, SSOP-24,
5mm × 5mm QFN-24
LTC3788/
LTC3788-1
Multiphase Dual Output Synchronous Step-Up
Controller
4.5V (Down to 2.5V After Start-Up) ≤ VIN ≤ 38V, VOUT Up to 60V, 50kHz to 900kHz
Fixed Operating Frequency, 5mm × 5mm QFN-32, SSOP-28
LTC3787
Multiphase, Single Output Dual Channel
Synchronous Step-Up Controller
4.5 (Down to 2.5V After Start-Up) ≤ VIN ≤ 38V, VOUT Up to 60V, 50kHz to 900kHz
Fixed Operating Frequency, 4mm × 4mm QFN-28, SSOP-28
50
Rev. A
01/20
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