LTC4098-3.6
USB Compatible Switching
Power Manager/LiFePO4 Charger
with Overvoltage Protection
DESCRIPTION
FEATURES
Switching Regulator with Bat-TrackTM Adaptive
Output Control Makes Optimal Use of Limited
Power Available from USB Port to Charge Battery
and Power Application
n Charge Control Algorithm Specifically Designed
for LiFePO4 (Lithium Iron Phosphate)
n Overvoltage Protection Guards Against Damage
n Bat-Track External Step-Down Switching Regulator
Control Maximizes Efficiency from Automotive,
Firewire and Other High Voltage Input Sources
n 180mΩ Internal Ideal Diode Plus External Ideal Diode
Controller Seamlessly Provide Low Loss PowerPathTM
When Input Power Is Limited or Unavailable
n Preset 3.6V Charge Voltage with 0.5% Accuracy
n Instant-On Operation with Discharged Battery
n 700mA Maximum Load Current from USB Port
n 2A Maximum Input Current from Internal Switching
Regulator
n 1.5A Maximum Charge Current with Thermal Limiting
n 20-Lead 3mm × 4mm × 0.75mm QFN Package
n
APPLICATIONS
High Peak Power Battery-Powered Equipment
Backup Applications
n High Reliability Handhelds
n
The LTC®4098-3.6 is a high efficiency USB PowerPath
controller and full-featured LiFePO4 battery charger. It seamlessly manages power distribution from multiple sources
including USB, wall adapter, automotive, Firewire or other
high voltage DC/DC converters, and a LiFePO4 battery.
The LTC4098-3.6 charge algorithm is optimized for LiFePO4
by implementing a 1-hour float voltage termination timer
and a 0°C to 60°C NTC-based charge qualification range.
Furthermore, completely discharged batteries are charged
at the full programmed charge current.
The LTC4098-3.6’s switching regulator can automatically
limit its input current for USB compatibility. For automotive and other high voltage applications, the LTC4098‑3.6
interfaces with an external switching regulator. Both the
USB input and the auxiliary input controller feature BatTrack optimized charging to provide maximum power to
the application and reduced heat in high power density applications with input supplies from 5V to as high as 38V.
An overvoltage protection circuit guards the LTC4098-3.6
from high voltage damage on the VBUS pin with just two
external components.
The LTC4098-3.6 is available in a 20-lead 3mm × 4mm ×
0.75mm QFN surface mount package.
n
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
Bat Track and PowerPath are trademarks of Linear Technology Corporation. All other trademarks
are the property of their respective owners.
TYPICAL APPLICATION
Reduced Power Dissipation
vs Linear Battery Charger
High Efficiency USB Compatible LiFePO4 Battery Charger with Overvoltage Protection
5V/USB
VBUS
SW
10µF
6.04k
TO µC
3
OVGATE
LTC4098-3.6
SYSTEM
LOAD
VOUT
OVSENS
D0-D2
CLPROG
0.1µF
3.01k
PROG
BAT
GND BATSENS
500Ω
10µF
+
409836 TA01a
VIN = 5V
PROG = 500Ω
ICHRG = 1.1A
10x MODE
2.0
ADDITIONAL POWER
AVAILABLE FOR CHARGING
1.5
1.0
0.5
LiFePO4
LINEAR BATTERY
CHARGER
2.5
POWER DISSIPATION (W)
3.3µH
3.0
SWITCHING
BATTERY
CHARGER
0
2.70
2.85
3.00 3.15 3.30
BATTERY VOLTAGE (V)
3.45
3.60
409836 TA01b
409836f
1
LTC4098-3.6
PIN CONFIGURATION
VBUS, WALL (Transient) t < 1ms,
Duty Cycle < 1%........................................... –0.3V to 7V
VBUS, WALL (Static), BAT, BATSENS,
CHRG, NTC,.................................................. –0.3V to 6V
D0, D1, D2..........–0.3V to Max (VBUS, VOUT, BAT) + 0.3V
IOVSENS..................................................................±10mA
ICLPROG.....................................................................3mA
IPROG.........................................................................2mA
ICHRG.......................................................................50mA
IVOUT, ISW, IBAT........................................................2.25A
IACPR.......................................................................±5mA
Operating Temperature Range.................. –40°C to 85°C
Junction Temperature............................................ 125°C
Storage Temperature Range.................... –65°C to 125°C
D2
WALL
ACPR
VC
TOP VIEW
20 19 18 17
OVSENS 1
16 D1
15 D0
OVGATE 2
CLPROG 3
14 SW
21
GND
NTCBIAS 4
13 VBUS
12 VOUT
NTC 5
11 BAT
9 10
IDGATE
8
GND
7
CHRG
BATSENS 6
PROG
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 3)
UDC PACKAGE
20-LEAD (3mm × 4mm) PLASTIC QFN
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
LTC4098EUDC-3.6#PBF
LTC4098EUDC-3.6#TRPBF
LFYR
PACKAGE DESCRIPTION
TEMPERATURE RANGE
20-Lead (3mm × 4mm) Plastic QFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VBUS = 5V, BAT = 3.3V, RCLPROG = 3.01k, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input Power Supply
VBUS
Input Supply Voltage
IVBUS(LIM)
Total Input Current
1x Mode
5x Mode
10x Mode
Low Power Suspend Mode
High Power Suspend Mode
IVBUSQ (Note 4)
Input Quiescent Current
1x Mode
5x Mode
10x Mode
Low Power Suspend Mode
High Power Suspend Mode
6
15
15
0.042
0.042
mA
mA
mA
mA
mA
1x Mode
5x Mode
10x Mode
Low Power Suspend Mode
High Power Suspend Mode
230
1164
2210
11.6
60
mA/mA
mA/mA
mA/mA
mA/mA
mA/mA
hCLPROG (Note 4) Ratio of Measured VBUS Current to
CLPROG Program Current
l
4.35
l
l
l
l
l
92
445
815
0.32
1.6
5.5
96
473
883
0.39
2.05
100
500
1000
0.5
2.5
V
mA
mA
mA
mA
mA
409836f
2
LTC4098-3.6
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VBUS = 5V, BAT = 3.3V, RCLPROG = 3.01k, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
IVOUT
VOUT Current Available Before
Discharging Battery
1x Mode
5x Mode
10x Mode
Low Power Suspend Mode
High Power Suspend Mode
MIN
TYP
135
659
1231
0.32
2.04
MAX
UNITS
mA
mA
mA
mA
mA
VCLPROG
CLPROG Servo Voltage in Current Limit
1x, 5x, 10x Modes
Suspend Modes
1.188
100
V
mV
VUVLO
VBUS Undervoltage Lockout
Rising Threshold
Falling Threshold
VOUT
VOUT Voltage
3.95
4.30
4.00
4.35
V
V
1x, 5x, 10x Modes, 0V < BAT ≤ 3.6V,
IVOUT = 0mA, Battery Charger Off
3.1
BAT + 0.4
4.3
V
USB Suspend Modes, IVOUT = 250µA
3.7
3.8
3.9
V
1.96
2.25
2.65
MHz
fOSC
Switching Frequency
RPMOS
PMOS On-Resistance
0.18
Ω
RNMOS
NMOS On-Resistance
0.30
Ω
IPEAK
Peak Inductor Current Clamp
1.2
1.7
3
A
A
A
RSUSP
Suspend LDO Output Resistance
15
Ω
1x Mode
5x Mode
10x Mode
Bat-Track External Switching Regulator Control
VWALL
Absolute WALL Input Threshold
Rising Threshold
Falling Threshold
DVWALL
Differential WALL Input Threshold
WALL-BAT Rising Threshold
WALL-BAT Falling Threshold
Regulation Target
4.1
4.25
3.2
4.4
V
V
0
90
25
3.5
BAT + 0.4
V
100
µA
WALL Quiescent Current
50
mV
mV
ACPR High Voltage
IACPR = 0mA
VOUT
V
ACPR Low Voltage
IACPR = 0mA
0
V
Overvoltage Protection
VOVP
Overvoltage Protection Threshold
Rising Threshold, ROVSENS = 6.04k
VOVGATE
OVGATE Output Voltage
Input Below VOVP
Input Above VOVP
tRISE
OVGATE Time to Reach Regulation
COVGATE = 1nF
6.10
6.35
6.70
V
1.88 • VOVSENSE
0
12
V
V
2.2
ms
Battery Charger
VFLOAT
BAT Regulated Output Voltage
ICHG
Constant-Current Mode Charge Current
RPROG = 1k, 10x Mode
RPROG = 5k, 5x, 10x Modes
IBAT
Battery Drain Current
3.582
3.565
3.6
3.6
3.618
3.635
V
V
980
192
1030
206
1080
220
mA
mA
VBUS > VUVLO, PowerPath Switching
Regulator On, Battery Charger Off,
IVOUT = 0µA
3.7
5
µA
VBUS = 0V, IVOUT = 0µA (Ideal Diode
Mode)
25
35
µA
0°C ≤ TA ≤ 85°C
VPROG
PROG Pin Servo Voltage
1.000
V
hPROG
Ratio of IBAT to PROG Pin Current
1030
mA/mA
VRECHRG
Recharge Battery Threshold Voltage
Threshold Voltage Relative to VFLOAT
–80
–100
–120
mV
409836f
3
LTC4098-3.6
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VBUS = 5V, BAT = 3.3V, RCLPROG = 3.01k, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
tTERM
Safety Timer Termination Period
Timer Starts When BAT = VFLOAT
0.85
1
1.15
Hour
tBADBAT
Bad Battery Termination Time
BAT < VTRKL
0.43
0.5
0.58
Hour
hC/10
End of Charge Indication Current Ratio
(Note 5)
0.09
0.1
0.11
mA/mA
VCHRG
CHRG Pin Output Low Voltage
ICHRG = 5mA
65
100
mV
ICHRG
CHRG Pin Input Current
BAT = 4.5V, VCHRG = 5V
0
1
µA
RON_CHG
Battery Charger Power FET
On-Resistance (Between VOUT and BAT)
IBAT = 200mA
TLIM
Junction Temperature in ConstantTemperature Mode
0.18
Ω
110
°C
NTC
VCOLD
Cold Temperature Fault Threshold
Voltage
Rising Threshold
Hysteresis
75.0
76.5
2.9
78.0
%NTCBIAS
%NTCBIAS
VHOT
Hot Temperature Fault Threshold
Voltage
Falling Threshold
Hysteresis
18.4
19.9
1.9
21.4
%NTCBIAS
%NTCBIAS
VDIS
NTC Disable Threshold Voltage
Falling Threshold
Hysteresis
0.5
1.3
50
2.3
%NTCBIAS
mV
INTC
NTC Leakage Current
NTC = 5V
–50
50
nA
VFWD
Forward Voltage Detection
IVOUT = 10mA
RDROPOUT
Internal Diode On-Resistance, Dropout
IVOUT = 200mA
IMAX
Diode Current Limit
Ideal Diode
15
mV
0.18
Ω
2
A
Logic (D0, D1, D2)
VIL
Input Low Voltage
VIH
Input High Voltage
IPD
Static Pull-Down Current
0.4
1.2
VPIN = 1V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC4098E-3.6 is tested under pulsed load conditions such
that TJ ≈ TA. The LTC4098E-3.6 is guaranteed to meet performance
specifications from 0°C to 85°C. Specifications over the – 40°C to 85°C
operating temperature range are assured by design, characterization and
correlation with statistical process controls.
V
V
2
µA
Note 3: The LTC4098E-3.6 includes overtemperature protection that is
intended to protect the device during momentary overload conditions.
Junction temperature will exceed 125°C when overtemperature protection
is active. Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
Note 4: Total input current is:
IVBUSQ + (VCLPROG/RCLPROG) • (hCLPROG + 1)
Note 5: hC/10 is expressed as a fraction of measured full charge current
with a 5k PROG resistor.
409836f
4
LTC4098-3.6
TYPICAL PERFORMANCE CHARACTERISTICS
Ideal Diode Resistance
vs Battery Voltage
Ideal Diode V-I Characteristics
DIODE RESISTANCE (Ω)
INTERNAL IDEAL
DIODE ONLY
0.2
0.15
0.10
0.05
0
0.04
0.12
0.16
0.08
FORWARD VOLTAGE (V)
0
2.7
0.20
409836 G01
VOUT Voltage vs VOUT Current
(Battery Charger Disabled)
4.00
BAT = 3.6V
3.75
BAT = 3.3V
3.50
VBUS = 5V
5x USB SETTING
0
550
2.7
4.2
200
600
400
OUTPUT CURRENT (mA)
3.3
3.6
409836 G03
Battery Charge Current vs VOUT
Current (Battery Charger Enabled)
600
3.25
120
VBUS = 5V
RCLPROG = 3.01k
1x USB SETTING
BATTERY VOLTAGE (V)
409836 G07
0
800
–300
600
120
500
400
300
VBUS = 5V
RPROG = 1k
RCLPROG = 3.01k
5x USB SETTING
0
2.7
3.0
BATTERY VOLTAGE (V)
800
409836 G06
100
80
60
40
20
3.3
200
600
400
OUTPUT CURRENT (mA)
0
USB Limited Battery Charge
Current vs Battery Voltage
140
200
VBUS = 5V
BAT = 3V
RCLPROG = 3.01k
RPROG = 2k
5x USB SETTING
409836 G05
700
100
3.6
150
USB Limited Battery Charge
Current vs Battery Voltage
CHARGE CURRENT (mA)
130
300
–150
200
600
400
OUTPUT CURRENT (mA)
0
409836 G04
140
3.3
VBUS = 5V
BAT = 3V
RCLPROG = 3.01k
RPROG = 2k
5x USB SETTING
3.00
2.75
800
150
3.0
3.0
BATTERY VOLTAGE (V)
409836 G02
3.50
USB Compliant Load Current
Available Before Discharging Battery
110
2.7
600
450
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
3.6
3.9
3.3
BATTERY VOLTAGE (V)
650
VBUS = 5V
RCLPROG = 3.01k
5x USB SETTING
3.75
3.25
LOAD CURRENT (mA)
3.0
700
VOUT Voltage vs VOUT Current
(Battery Charger Enabled)
4.25
3.00
INTERNAL IDEAL DIODE
WITH SUPPLEMENTAL
EXTERNAL VISHAY
Si2333 PMOS
CHARGE CURRENT (mA)
0
INTERNAL IDEAL
DIODE
CHARGE CURRENT (mA)
DIODE CURRENT (A)
0.20
0.6
0.4
750
0.25
INTERNAL IDEAL DIODE
WITH SUPPLEMENTAL
EXTERNAL VISHAY
Si2333 PMOS
0.8
USB Compliant Load Current
Available Before Discharging Battery
LOAD CURRENT (mA)
1.0
TA = 25°C, unless otherwise noted.
3.6
409836 G08
VBUS = 5V
RPROG = 1k
RCLPROG = 3.01k
1x USB SETTING
0
2.7
3.0
3.3
BATTERY VOLTAGE (V)
3.6
409836 G09
409836f
5
LTC4098-3.6
TYPICAL PERFORMANCE CHARACTERISTICS
Battery Drain Current
vs Battery Voltage
30
IVOUT = 0µA
25
Battery Charging Efficiency vs
Battery Voltage with No External
Load (PBAT/PVBUS)
PowerPath Switching Regulator
Efficiency vs Output Current
100
VBUS = 0V
100
BAT = 3.3V
5x, 10x MODE
90
10
60
3.0
3.3
BATTERY VOLTAGE (V)
40
0.01
3.6
3.75
OUTPUT VOLTAGE (V)
VBUS CURRENT (µA)
2.5
20
3.60
3.45
SUSPEND LOW
4
VBUS VOLTAGE (V)
3
5
3.00
6
0.5
409836 G13
600
100
500
CHARGE CURRENT (mA)
120
80
60
40
1.5
2.0
1.0
OUTPUT CURRENT (mA)
3.2
3.3
3.4
OUTPUT VOLTAGE (V)
3.5
409836 G16
0
2.5
0.5
1.5
2.0
1.0
OUTPUT CURRENT (mA)
2.5
409836 G15
1.003
400
THERMAL REGULATION
300
200
0
0
Normalized Battery Charger Float
Voltage vs Temperature
RPROG = 2k
0
–40 –20
SUSPEND LOW
409836 G14
100
20
SUSPEND HIGH
1.0
Battery Charge Current
vs Temperature
Automatic Battery Charge Current
vs Output Voltage
0
3.1
0
1.5
0.5
VBUS = 5V
BAT = 3.3V
RCLPROG = 3.01k
3.15
3.6
409836 G12
VBUS = 5V
BAT = 3.3V
RCLPROG = 3.01k
2.0
3.30
3.3
VBUS Current vs VOUT Current
in Suspend (Includes OVP)
SUSPEND HIGH
40
3.0
BATTERY VOLTAGE (V)
409836 G11
3.90
60
2
60
2.7
1
VOUT Voltage vs VOUT Current
in Suspend
BAT = 3.3V
IVOUT = 0mA
1
0.1
OUTPUT CURRENT (A)
409836 G10
80
0
1x CHARGING
EFFICIENCY
50
VBUS Current vs VBUS Voltage
(Suspend Mode—Includes OVP)
100
5x CHARGING
EFFICIENCY
80
70
VBUS = 5V
(SUSPEND MODE)
2.7
70
VBUS CURRENT (mA)
0
EFFICIENCY (%)
EFFICIENCY (%)
15
80
NORMALIZED FLOAT VOLTAGE
BATTERY CURRENT (µA)
20
RCLPROG = 3.01k
RPROG = 1k
IVOUT = 0mA
90
1x MODE
5
% PROGRAMMED CHARGE CURRENT
TA = 25°C, unless otherwise noted.
20 40 60 80
TEMPERATURE (°C)
100 120
409836 G17
1.002
1.001
1.000
0.999
0.998
0.997
–40
–15
35
10
TEMPERATURE (°C)
60
85
409836 G18
409836f
6
LTC4098-3.6
TYPICAL PERFORMANCE CHARACTERISTICS
Low Battery (Instant-On,
Charger Disabled) Output
Voltage vs Temperature
Oscillator Frequency
vs Temperature
3.54
3.52
–15
35
60
10
TEMPERATURE (°C)
85
110
20
17
2.30
QUIESCENT CURRENT (mA)
OSCILLATOR FREQUENCY (MHz)
3.56
2.25
2.20
2.15
2.10
–40
–15
409836 G19
35
10
TEMPERATURE (°C)
60
42
36
33
30
10
35
TEMPERATURE (°C)
60
8
2
–40
85
100
39
–15
11
1x MODE
–15
–10
35
TEMPERATURE (°C)
60
85
409836 G21
CHRG Pin Current vs Voltage
(Pull-Down State)
VBUS = 5V
IVOUT = 0µA
27
–40
5x MODE
14
409836 G20
Quiescent Current in Suspend
vs Temperature
45
VBUS = 5V
IVOUT = 0µA
5
CHRG PIN CURRENT (mA)
3.50
–40
VBUS Quiescent Current
vs Temperature
2.35
BAT = 2.7V
IVOUT = 100mA
5x MODE
QUIESCENT CURRENT (µA)
OUTPUT VOLTAGE (V)
3.58
TA = 25°C, unless otherwise noted.
85
80
60
40
20
0
409836 G22
Suspend LDO Transient Response
(500µA to 1.5mA)
IOUT
500µA/DIV
VBUS = 5V
BAT = 3.8V
0
1
3
4
2
CHRG PIN VOLTAGE (V)
5
409836 G23
OVP Connection Waveform
VBUS
5V/DIV
0mA
OVGATE
5V/DIV
VOUT
20mV/DIV
AC-COUPLED
OVP INPUT VOLTAGE
0V TO 5V STEP
5V/DIV
500µs/DIV
409836 G24
500µs/DIV
409836 G25
409836f
7
LTC4098-3.6
TYPICAL PERFORMANCE CHARACTERISTICS
OVP Protection Waveform
TA = 25°C, unless otherwise noted.
OVP Reconnection Waveform
VBUS
5V/DIV
VBUS
5V/DIV
OVGATE
5V/DIV
OVGATE
5V/DIV
OVP INPUT VOLTAGE
10V TO 5V STEP
5V/DIV
OVP INPUT VOLTAGE
5V TO 10V STEP
5V/DIV
409836 G26
500µs/DIV
OVSENS Quiescent Current
vs Temperature
Rising Overvoltage Threshold
vs Temperature
12
OVSENS CONNECTED
TO INPUT THROUGH
10 6.04k RESISTOR
33
31
OVGATE VOLTAGE (V)
6.275
35
6.270
6.265
6.260
29
27
–40
OVGATE vs OVSENS
6.280
VOVSENS = 5V
OVP THRESHOLD (V)
QUIESCENT CURRENT (µA)
37
–15
35
10
TEMPERATURE (°C)
60
85
409836 G28
6.255
–40
409836 G27
500µs/DIV
8
6
4
2
–15
35
10
TEMPERATURE (°C)
60
85
409836 G29
0
0
2
4
6
INPUT VOLTAGE (V)
8
409836 G30
409836f
8
LTC4098-3.6
PIN FUNCTIONS
OVSENS (Pin 1): Overvoltage Protection Sense Input.
OVSENS should be connected through a 6.04k resistor
to the input power connector and the drain of an external
N-channel MOSFET pass transistor. When the voltage on
this pin exceeds a preset level, the OVGATE pin will be
pulled to GND to disable the pass transistor and protect
downstream circuitry. If overvoltage protection is not
desired, connect OVSENS to GND.
OVGATE (Pin 2): Overvoltage Protection Gate Output.
Connect OVGATE to the gate pin of an external N-channel MOSFET pass transistor. The source of the transistor
should be connected to VBUS and the drain should be
connected to the product’s DC input connector. This pin is
connected to an internal charge pump capable of creating
sufficient overdrive to fully enhance the pass transistor. If
an overvoltage condition is detected, OVGATE is brought
rapidly to GND to prevent damage to downstream circuitry.
OVGATE works in conjunction with OVSENS to provide
this protection. If overvoltage protection is not desired,
leave OVGATE open.
CLPROG (Pin 3): USB Current Limit Program and Monitor
Pin. A 1% resistor from CLPROG to ground determines
the upper limit of the current drawn from the VBUS pin.
A precise fraction of the input current, hCLPROG, is sent
to the CLPROG pin when the high side switch is on. The
switching regulator delivers power until the CLPROG
pin reaches 1.188V. Therefore, the current drawn from
VBUS will be limited to an amount given by hCLPROG and
RCLPROG. There are several ratios for hCLPROG available,
two of which correspond to the 500mA and 100mA USB
specifications. A multilayer ceramic averaging capacitor
is also required at CLPROG for filtering.
NTCBIAS (Pin 4): NTC Thermistor Bias Output. If NTC
operation is desired, connect a bias resistor between
NTCBIAS and NTC, and an NTC thermistor between NTC
and GND. To disable NTC operation, connect NTC to GND
and leave NTCBIAS open.
NTC (Pin 5): Input to the NTC Thermistor Monitoring
Circuits. The NTC pin connects to a negative temperature
coefficient thermistor which is typically co-packaged with
the battery pack to determine if the battery is too hot or too
cold to charge. If the battery’s temperature is out of range,
charging is paused until the battery temperature re-enters
the valid range. A low drift bias resistor is required from
NTCBIAS to NTC and a thermistor is required from NTC
to ground. If the NTC function is not desired, the NTC pin
should be grounded.
BATSENS (Pin 6): Battery Voltage Sense Input. For proper
operation, this pin must always be connected to BAT. For
best performance, connect BATSENS to BAT physically
close to the LiFePO4 cell.
PROG (Pin 7): Charge Current Program and Charge Current Monitor Pin. Connecting a 1% resistor from PROG
to ground programs the charge current. If sufficient input
power is available in constant-current mode, this pin servos
to 1V. The voltage on this pin always represents the actual
charge current by using the following formula:
IBAT =
VPROG
• 1030
RPROG
CHRG (Pin 8): Open-Drain Charge Status Output. The
CHRG pin indicates the status of the battery charger. Four
possible states are represented by CHRG: charging, not
charging, unresponsive battery and battery temperature
out of range. CHRG is modulated at 35kHz and switches
between a low and a high duty cycle for easy recognition
by either humans or microprocessors. CHRG requires a
pull-up resistor and/or LED to provide indication.
GND (Pin 9, Exposed Pad Pin 21): The exposed pad and
pin must be soldered to the PCB to provide a low electrical
and thermal impedance connection to ground.
IDGATE (Pin 10): Ideal Diode Amplifier Output. This pin
controls the gate of an external P-channel MOSFET transistor used to supplement the internal ideal diode. The source
of the P-channel MOSFET should be connected to VOUT
and the drain should be connected to BAT.
BAT (Pin 11): Single-Cell LiFePO4 Battery Pin. Depending
on available power and load, a LiFePO4 battery on BAT will
either deliver system power to VOUT through the ideal diode
or be charged from the battery charger. The LTC4098-3.6
will charge to a float voltage of 3.600V.
VOUT (Pin 12): Output Voltage of the Switching PowerPath
Controller and Input Voltage of the Battery Charger. The
409836f
9
LTC4098-3.6
PIN FUNCTIONS
majority of the portable product should be powered from
VOUT . The LTC4098-3.6 will partition the available power
between the external load on VOUT and the internal battery
charger. Priority is given to the external load and any extra
power is used to charge the battery. An ideal diode from
BAT to VOUT ensures that VOUT is powered even if the load
exceeds the allotted power from VBUS or if the VBUS power
source is removed. VOUT should be bypassed with a low
impedance multilayer ceramic capacitor.
VBUS (Pin 13): Input Voltage for the Switching PowerPath
Controller. VBUS will usually be connected to the USB port
of a computer or a DC output wall adapter. VBUS should
be bypassed with a low impedance multilayer ceramic
capacitor.
SW (Pin 14): The SW pin delivers power from VBUS to
VOUT via the step-down switching regulator. An inductor
should be connected from SW to VOUT . See the Applications Information section for a discussion of inductance
value and current rating.
D0 (Pin 15): Mode Select Input Pin. D0, in combination
with the D1 pin and the D2 pin, controls the current limit
and battery charger functions of the LTC4098-3.6 (see
Table 1). This pin is pulled low by a weak current sink.
D1 (Pin 16): Mode Select Input Pin. D1, in combination
with the D0 pin and the D2 pin, controls the current limit
and battery charger functions of the LTC4098-3.6 (see
Table 1). This pin is pulled low by a weak current sink.
D2 (Pin 17): Mode Select Input Pin. D2, in combination
with the D0 pin and D1 pin, controls the current limit and
battery charger functions of the LTC4098-3.6 (see Table 1).
This pin is pulled low by a weak current sink.
WALL (Pin 18): External Power Source Sense Input. WALL
should be connected to the output of the external high
voltage switching regulator and to the drain of an external P-channel MOSFET transistor. It is used to determine
when power is applied to the external regulator. When
power is detected, ACPR is driven low and the USB input
is automatically disabled.
ACPR (Pin 19): External Power Source Present Output
(Active Low). ACPR indicates that the output of the external
high voltage step-down switching regulator is suitable
for use by the LTC4098-3.6. It should be connected to
the gate of an external P-channel MOSFET transistor
whose source is connected to VOUT and whose drain is
connected to WALL. ACPR has a high level of VOUT and
a low level of GND.
VC (Pin 20): Bat-Track External Switching Regulator
Control Output. This pin drives the VC pin of a Linear
Technology external step-down switching regulator. In
concert with WALL and ACPR, it will regulate VOUT to
maximize battery charger efficiency.
409836f
10
TO USB
OR WALL
ADPAPTER
T NTC
5
4
3
13
0.1V
NTC
NTCBIAS
1.188V
CLPROG
ISWITCH /N ILDO /M
VBUS
OVGATE
+
–
+
–
+
–
2
+
–
1
AVERAGE INPUT
CURRENT LIMIT
CONTROLLER
NTC ENABLE
OVERTEMP
UNDERTEMP
VOUT
+
–
SUSPEND
LDO
100mV
×2
OVERVOLTAGE PROTECTION
– +
NTC FAULT
OSC
3.8V
Q
D0
15
D1
16
LOGIC
D2
17
NONOVERLAP
AND DRIVE
LOGIC
AVERAGE OUTPUT
VOLTAGE LIMIT
CONTROLLER
PWM
R
S
+–
6V
20
+
+
–
+
–
OVSENS
VC
GND
9
3.5V
GND
21
+–
0.4V
HVOK
VOUT
ISENSE
SW
1V
7
PROG
18
BAD CELL
NTC
100mV
VOUT
3.6V
BAT + 0.4V
IBAT/1030
CONSTANT-CURRENT
CONSTANT-VOLTAGE
BATTERY CHARGER
+
–
VC
LT3653
+
+
–
VIN
PWM
–
+
15mV
0V
IDEAL
DIODE
4.3V
WALL
+
–
+
–
TO AUTOMOTIVE,
FIREWIRE, ETC.
+
–
8
11
6
10
12
14
19
409836 BD
CHRG
BAT
BATSENS
IDGATE
VOUT
SW
ACPR
+
SINGLE-CELL
LiFePO4
OPTIONAL
EXTERNAL
IDEAL DIODE
PMOS
TO SYSTEM
LOAD
LTC4098-3.6
BLOCK DIAGRAM
409836f
11
LTC4098-3.6
OPERATION
Introduction
The LTC4098-3.6 is a high efficiency power management
and LiFePO4 charger solution designed to make optimal
use of the power available from a variety of sources, while
minimizing power dissipation and easing thermal budgeting
constraints. The innovative PowerPath architecture ensures
that the application is powered immediately after external
voltage is applied, even with a completely dead battery, by
prioritizing power to the application over the battery.
The LTC4098-3.6 includes a Bat-Track monolithic stepdown switching regulator for USB, wall adapters and other
5V sources. Designed specifically for USB applications,
the switching regulator incorporates a precision average
input current limit for USB compatibility. Because power
is conserved, the LTC4098-3.6 allows the load current
on VOUT to exceed the current drawn by the USB port,
making maximum use of the allowable USB power for
battery charging.
The switching regulator and battery charger communicate
to ensure that the average input current never exceeds the
USB specifications.
For automotive, Firewire, and other high voltage applications, the LTC4098-3.6 provides Bat-Track control of
an external LTC step-down switching regulator to
maximize battery charger efficiency and minimize heat
production.
When power is available from both the USB and high
voltage inputs, the high voltage input is prioritized and
the USB input is automatically disabled.
The LTC4098-3.6 features an overvoltage protection circuit
which is designed to work with an external N-channel
MOSFET to prevent damage to its inputs caused by accidental application of high voltage.
The LTC4098-3.6 contains both an internal 180mW ideal
diode and an ideal diode controller designed for use with
an external P-channel MOSFET. The ideal diodes from BAT
to VOUT guarantee that ample power is always available
to VOUT even if there is insufficient or absent power at
VBUS or WALL.
Finally, to prevent battery drain when a device is connected
to a suspended USB port, an LDO from VBUS to VOUT
provides either low power or high power USB suspend
current to the application.
Bat-Track Input Current Limited Step Down Switching
Regulator
The power delivered from VBUS to VOUT is controlled
by a 2.25MHz constant-frequency step-down switching
regulator. To meet the USB maximum load specification,
the switching regulator contains a measurement and
control system that ensures that the average input current remains below the level programmed at CLPROG.
VOUT drives the combination of the external load and the
battery charger.
If the combined load does not cause the switching
power supply to reach the programmed input current
limit, VOUT will track approximately 0.4V above the
battery voltage. By keeping the voltage across the battery charger at this low level, power lost to the battery
charger is minimized. Figure 1 shows the power path
components.
If the combined external load plus battery charge
current is large enough to cause the switching power
supply to reach the programmed input current limit,
the battery charger will reduce its charge current by
precisely the amount necessary to enable the external
load to be satisfied. Even if the battery charge current is
programmed to exceed the allowable USB current, the
USB specification for average input current will not be
violated; the battery charger will reduce its current as
needed. Furthermore, if the load current at VOUT exceeds
the programmed power from VBUS, load current will be
drawn from the battery via the ideal diodes even when
the battery charger is enabled.
The current at CLPROG is a precise fraction of the VBUS
current. When a programming resistor and an averaging
capacitor are connected from CLPROG to GND, the voltage
on CLPROG represents the average input current of the
switching regulator. As the input current approaches the
programmed limit, CLPROG reaches 1.188V and power
delivered by the switching regulator is held constant.
Several ratios of current are available which can be set
to correspond to USB low and high power modes with a
single programming resistor.
409836f
12
FROM USB
OR WALL
ADAPTER
3
13
2
1
CLPROG
VBUS
OVGATE
1.188V
ISWITCH /N
×2
+–
PWM AND
GATE DRIVE
AVERAGE INPUT
CURRENT LIMIT
CONTROLLER
+
–
OVERVOLTAGE PROTECTION
20
VC
3.5V
+–
0.4V
CONSTANT-CURRENT
CONSTANT-VOLTAGE
BATTERY CHARGER
VOUT
ISENSE
SW
18
4.3V
WALL
15mV
OmV
IDEAL
DIODE
+
–
Bat-Track HV CONTROL
VOUT
3.6V
BAT + 0.4V
Figure 1. Simplified Power Flow Diagram
AVERAGE OUTPUT
VOLTAGE LIMIT
CONTROLLER
6V
+
+
–
+
–
OVSENS
HVOK
VC
LT3653
+
–
+
+
–
VIN
+
–
TO AUTOMOTIVE,
FIREWIRE, ETC.
6
11
10
12
14
40981 F01
19
USB INPUT
BATTERY POWER
HV INPUT
BATSENS
BAT
IDGATE
VOUT
SW
ACPR
+
SINGLE-CELL
LiFePO4
OPTIONAL EXTERNAL
IDEAL DIODE PMOS
3.1V TO
(BAT + 0.4V)
TO SYSTEM
LOAD
LTC4098-3.6
OPERATION
409836f
13
LTC4098-3.6
OPERATION
The input current limit is programmed by various combinations of the D0, D1 and D2 pins as shown in Table 1.
The switching input regulator can also be deactivated
(USB suspend).
The average input current will be limited by the CLPROG
programming resistor according to the following
expression:
IVBUS = IVBUSQ +
VCLPROG
• (hCLPROG + 1)
RCLPROG
where IVBUSQ is the quiescent current of the LTC4098‑3.6,
VCLPROG is the CLPROG servo voltage in current limit,
RCLPROG is the value of the programming resistor and
hCLPROG is the ratio of the measured current at VBUS to
the sample current delivered to CLPROG. Refer to the
Electrical Characteristics table for values of hCLPROG,
VCLPROG and IVBUSQ. Given worst-case circuit tolerances,
the USB specification for the average input current in 1x
or 5x mode will not be violated, provided that RCLPROG is
3.01k or greater.
Notice that when D0 is high and D1 is low, the switching
regulator is set to a higher current limit for increased
charging and power availability at VOUT. These modes will
typically be used when there is line power available from
a wall adapter.
While not in current limit, the switching regulator’s
Bat-Track feature will set VOUT to approximately 400mV
above the voltage at BAT. However, if the voltage at BAT
is below 3.1V, and the load requirement does not cause
the switching regulator to exceed its current limit, VOUT
will regulate at a fixed 3.5V, as shown in Figure 2. This
instant-on operation will allow a portable product to run
immediately when power is applied without waiting for
the battery to charge.
If the load does exceed the current limit at VBUS, VOUT
will range between the no-load voltage and slightly below
the battery voltage, indicated by the shaded region of
Figure 2.
4.0
3.8
Table 1 shows the available settings for the D0, D1 and
D2 pins.
D2
0
0
0
0
1
1
1
1
D1
0
0
1
1
0
0
1
1
D0
0
1
0
1
0
1
0
1
CHARGER
STATUS
IBUS(LIM)
On
100mA (1x)
On
1A (10x)
On
500mA (5x)
Off
500µA (Susp Low)
Off
100mA (1x)
Off
1A (10x)
Off
500mA (5x)
Off
2.5mA (Susp High)
VOUT (V)
Table 1. Controlled Input Current Limit
3.6
NO LOAD
3.4
3.2
400mV
3.0
2.8
2.6
2.4
2.4
2.7
3.0
BAT (V)
3.3
3.6
409836 F02
Figure 2. VOUT vs BAT
409836f
14
LTC4098-3.6
OPERATION
For very low battery voltages, the battery charger acts like
a load and, due to limited input power, its current will tend
to pull VOUT below the 3.5V instant-on voltage. To prevent
VOUT from falling below this level, an undervoltage circuit
automatically detects that VOUT is falling and reduces the
battery charge current as needed. This reduction ensures
that load current and voltage are always prioritized while
allowing as much battery charge current as possible. Refer
to Overprogramming the Battery Charger in the Applications Information section.
The voltage regulation loop compensation is controlled by
the capacitance on VOUT. An MLCC capacitor of 10µF is
required for loop stability. Additional capacitance beyond
this value will improve transient response.
An internal undervoltage lockout circuit monitors VBUS and
keeps the switching regulator off until VBUS rises above
the rising UVLO threshold (4.3V). If VBUS falls below the
falling UVLO threshold (4V), system power at VOUT will
be drawn from the battery via the ideal diodes.
Bat-Track High Voltage External Switching Regulator
Control
The WALL, ACPR and VC pins can be used in conjunction
with an external high voltage step-down switching regulator
such as the LT3653 or LT3480 to minimize heat production
when operating from higher voltage sources, as shown in
Figures 3 and 4. Bat-Track control circuitry regulates the
external switching regulator’s output voltage to the larger
of BAT + 400mV or 3.6V. This maximizes battery charger
efficiency while still allowing instant-on operation when
the battery is deeply discharged.
When using the LT3480, the feedback network should be
set to generate an output voltage between 4.5V and 5.5V.
When high voltage is applied to the external regulator, WALL
will rise toward this programmed output voltage. When
WALL exceeds approximately 4.3V, ACPR is brought low
and the Bat-Track control of the LTC4098-3.6 overdrives
the local VC control of the external high voltage step-down
switching regulator. Therefore, once the Bat-Track control
is enabled, the output voltage is set independent of the
switching regulator feedback network.
Bat-Track control provides a significant efficiency advantage
over the simple use of a 5V switching regulator output to
drive the battery charger. With a 5V output driving VOUT,
battery charger efficiency is approximately:
VBAT
η
=
η
•
TOTAL
BUCK
5V
where hBUCK is the efficiency of the high voltage switching
regulator and 5V is the output voltage of the switching
regulator. With a typical switching regulator efficiency of
87% and a typical battery voltage of 3.4V, the total battery
charger efficiency is approximately 59%. Assuming a 1A
charge current, well over 2W of power is dissipated just
to charge the battery!
With Bat-Track, battery charger efficiency is approximately:
ηTOTAL = ηBUCK •
SW
SW
LT3480
LT3653
VC
HVOK
ISENSE
VOUT
VC
VC
WALL
ACPR
VC
LTC4098-3.6
BAT
BAT + 0.4V
VOUT
SYSTEM
LOAD
409836 F03
Figure 3. LT3653 Typical Interface
FB
WALL
LTC4098-3.6
ACPR
VOUT
SYSTEM
LOAD
409836 F04
Figure 4. LT3480 Typical Interface
409836f
15
LTC4098-3.6
OPERATION
With the same assumptions as previously stated, the total
battery charger efficiency is approximately 78%. This
example works out to just over 1W of power dissipation,
or almost 50% less heat.
The charge pump output on OVGATE has limited output
drive capability. Care must be taken to avoid leakage on
this pin, as it may adversely affect operation.
See the Typical Applications section for complete circuits
using the LT3653 and LT3480 with Bat-Track control.
See the Applications Information section for examples of
multiple input protection, reverse input protection, and a
table of recommended components.
Overvoltage Protection
Ideal Diode from BAT to VOUT
The LTC4098-3.6 can protect itself from the inadvertent
application of excessive voltage to VBUS or WALL with just
two external components: an N-channel MOSFET and a
6.04k resistor. The maximum safe overvoltage magnitude
will be determined by the choice of the external N-channel
MOSFET and its associated drain breakdown voltage.
The LTC4098-3.6 has an internal ideal diode as well as a
controller for an external ideal diode. Both the internal and
the external ideal diodes are always on and will respond
quickly whenever VOUT drops below BAT.
In an overvoltage condition, the OVSENS pin will be
clamped at 6V. The external 6.04k resistor must be
sized appropriately to dissipate the resultant power. For
example, a 1/10W 6.04k resistor can have at most
√PMAX • 6.04k = 24V applied across its terminals. With the
6V at OVSENS, the maximum overvoltage magnitude that
this resistor can withstand is 30V. A 1/4W 6.04k resistor
raises this value to 44V. WALL’s absolute maximum current rating of 10mA imposes an upper protection limit
of 66V.
2200
VISHAY Si2333
EXTERNAL
IDEAL DIODE
2000
1800
1600
CURRENT (mA)
The overvoltage protection module consists of two pins.
The first, OVSENS, is used to measure the externally applied voltage through an external resistor. The second,
OVGATE, is an output used to drive the gate pin of an
external FET. The voltage at OVSENS will be lower than
the OVP input voltage by (IOVSENS • 6.04k) due to the
OVP circuit’s quiescent current. The OVP input will be
200mV to 400mV higher than OVSENS under normal
operating conditions. When OVSENS is below 6V, an internal charge pump will drive OVGATE to approximately
1.88 • OVSENS. This will enhance the N-channel MOSFET
and provide a low impedance connection to VBUS or WALL
which will, in turn, power the LTC4098-3.6. If OVSENS
should rise above 6V (6.35V OVP input) due to a fault or
use of an incorrect wall adapter, OVGATE will be pulled to
GND, disabling the external FET to protect downstream
circuitry. When the voltage drops below 6V again, the
external MOSFET will be reenabled.
If the load current increases beyond the power allowed
from the switching regulator, additional power will be
pulled from the battery via the ideal diodes. Furthermore,
if power to VBUS (USB or wall power) is removed, then
all of the application power will be provided by the battery via the ideal diodes. The ideal diodes will be fast
enough to keep VOUT from drooping with only the storage capacitance required for the switching regulator. The
internal ideal diode consists of a precision amplifier that
activates a large on-chip MOSFET transistor whenever
the voltage at VOUT is approximately 15mV (VFWD) below
the voltage at BAT. Within the amplifier’s linear range, the
small-signal resistance of the ideal diode will be quite low,
keeping the forward drop near 15mV. At higher current
levels, the MOSFET will be in full conduction. If additional
conductance is needed, an external P-channel MOSFET
1400
LTC4098-3.6
IDEAL DIODE
1200
1000
800
600
ON
SEMICONDUCTOR
MBRM120LT3
400
200
0
0
60 120 180 240 300 360 420 480
FORWARD VOLTAGE (mV) (BAT – VOUT)
409836 F05
Figure 5. Ideal Diode V-I Characteristics
409836f
16
LTC4098-3.6
OPERATION
transistor may be added from BAT to VOUT. The IDGATE pin
of the LTC4098-3.6 drives the gate of the external P-channel MOSFET transistor for automatic ideal diode control.
The source of the external P-channel MOSFET should be
connected to VOUT and the drain should be connected to
BAT. Capable of driving a 1nF load, the IDGATE pin can
control an external P-channel MOSFET transistor having
an on-resistance of 30mΩ or lower. Figure 5 shows the
decreased forward voltage compared to a conventional
Schottky diode.
Suspend LDO
The LTC4098-3.6 provides a small amount of power to VOUT
in suspend mode by including an LDO from VBUS to VOUT.
This LDO will prevent the battery from running down when
the portable product has access to a suspended USB port.
Regulating at 3.8V, this LDO only becomes active when the
switching converter is disabled. In accordance with the
USB specification, the input to the LDO is current limited so
that it will not exceed the low power or high power suspend
specification. If the load on VOUT exceeds the suspend current limit, the additional current will come from the battery
via the ideal diodes. The suspend LDO sends a scaled copy
of the VBUS current to the CLPROG pin, which will servo to
approximately 100mV in this mode. Thus, the high power
and low power suspend settings are related to the levels
programmed by the same resistor for 1x and 5x modes.
Battery Charger
The LTC4098-3.6 includes a constant-current/constantvoltage battery charger with automatic recharge, automatic
termination by safety timer and thermistor sensor input
for out-of-temperature charge pausing.
The charger begins charging in full power constant-current mode. The current delivered to the battery will try to
reach 1030V/RPROG. Depending on available input power
and external load conditions, the battery charger may or
may not be able to charge at the full programmed rate.
The external load will always be prioritized over the battery charge current. The USB current limit programming
will always be observed and only additional power will be
available to charge the battery. When system loads are
light, battery charge current will be maximized.
Charge Termination
The battery charger has a built-in safety timer. Once the
voltage on the battery reaches the preprogrammed float
voltage of 3.600V, the charger will regulate the battery voltage there and the charge current will decrease naturally.
Once the charger detects that the battery has reached
3.600V, the 1-hour safety timer is started. After the safety
timer expires, charging of the battery will discontinue and
no more current will be delivered.
Automatic Recharge
Once the battery charger terminates, it will remain off
drawing only microamperes of current from the battery.
If the portable product remains in this state long enough,
the battery will eventually self discharge. To ensure that
the battery is always topped off, a charge cycle will automatically begin when the battery voltage falls below
VRECHRG (typically 3.5V). In the event that the safety timer
is running when the battery voltage falls below VRECHRG, it
will reset back to zero. To prevent brief excursions below
VRECHRG from resetting the safety timer, the battery voltage
must be below VRECHRG for more than 1.5ms. The charge
cycle and safety timer will also restart if the VBUS UVLO
cycles low and then high (e.g., VBUS is removed and then
replaced) or if the charger is momentarily disabled using
the D2 pin.
Charge Current
The charge current is programmed using a single resistor
from PROG to ground. 1/1030th of the battery charge current is delivered to PROG, which will attempt to servo to
1.000V. Thus, the battery charge current will try to reach
1030 times the current in the PROG pin. The program
resistor and the charge current are calculated using the
following equations:
RPROG =
1030 V
1030 V
, ICHG =
ICHG
RPROG
In either the constant-current or constant-voltage charging modes, the voltage at the PROG pin will be proportional to the actual charge current delivered to the
battery. The charge current can be determined at any time
409836f
17
LTC4098-3.6
OPERATION
by monitoring the PROG pin voltage and using the following equation:
IBAT =
VPROG
• 1030
RPROG
In many cases, the actual battery charge current, IBAT, will
be lower than the programmed current, ICHG, due to limited
input power available and prioritization to the system load
drawn from VOUT.
Charge Status Indication
The CHRG pin indicates the status of the battery charger.
Four possible states are represented by CHRG which include
charging, not charging (or float charge current less than
programmed end of charge indication current), unresponsive battery and battery temperature out of range.
The signal at the CHRG pin can be easily recognized as
one of the above four states by either a human or a microprocessor. An open-drain output, the CHRG pin can
drive an indicator LED through a current limiting resistor
for human interfacing or simply a pull-up resistor for
microprocessor interfacing.
To make the CHRG pin easily recognized by both humans
and microprocessors, the pin is either a DC signal of ON
for charging, OFF for not charging or it is switched at
high frequency (35kHz) to indicate an NTC fault. While
switching at 35kHz, its duty cycle is modulated at a slow
rate that can be recognized by a human.
When charging begins, CHRG is pulled low and remains
low for the duration of a normal charge cycle. When charge
current drops to 1/10th the value programmed by RPROG,
the CHRG pin is released (Hi-Z). The CHRG pin does not
respond to the C/10 threshold if the LTC4098-3.6 is in VBUS
current limit. This prevents false end-of-charge indications
due to insufficient power available to the battery charger. If
a fault occurs while charging, the pin is switched at 35kHz.
While switching, its duty cycle is modulated between a high
and low value at a very low frequency. The low and high
duty cycles are disparate enough to make an LED appear
to be on or off thus giving the appearance of “blinking.”
Each of the two faults has its own unique “blink” rate for
human recognition as well as two unique duty cycles for
machine recognition.
Table 2 illustrates the four possible states of the CHRG
pin when the battery charger is active.
Table 2. CHRG Signal
STATUS
FREQUENCY
MODULATION
(BLINK) FREQUENCY
DUTY
CYCLES
Charging
0Hz
0Hz (Low Z)
100%
IBAT < C/10
0Hz
0Hz (Hi-Z)
0%
NTC Fault
35kHz
1.5Hz at 50%
6.25% or 93.75%
Bad Battery
35kHz
6.1Hz at 50%
12.5% or 87.5%
Notice that an NTC fault is represented by a 35kHz pulse
train whose duty cycle toggles between 6.25% and 93.75%
at a 1.5Hz rate. A human will easily recognize the 1.5Hz
rate as a “slow” blinking which indicates the out of range
battery temperature while a microprocessor will be able
to decode either the 6.25% or 93.75% duty cycles as an
NTC fault.
If a battery is found to be unresponsive to charging (i.e.,
its voltage remains below 2.85V for 1/2 hour), the CHRG
pin gives the battery fault indication. For this fault, a human
would easily recognize the frantic 6.1Hz “fast” blink of the
LED while a microprocessor would be able to decode either
the 12.5% or 87.5% duty cycles as a bad cell fault.
Because the LTC4098-3.6 is a 3-terminal PowerPath
product, system load is always prioritized over battery
charging. Due to excessive system load, there may not
be sufficient power to charge the battery beyond the badcell threshold voltage within the bad-cell timeout period.
In this case the battery charger will falsely indicate a bad
cell. System software may then reduce the load and reset
the battery charger to try again.
Although very improbable, it is possible that a duty cycle
reading could be taken at the bright-dim transition (low
duty cycle to high duty cycle). When this happens the
duty cycle reading will be precisely 50%. If the duty cycle
reading is 50%, system software should disqualify it and
take a new duty cycle reading.
409836f
18
LTC4098-3.6
OPERATION
NTC Thermistor
Thermal Regulation
The battery temperature is measured by placing a negative temperature coefficient (NTC) thermistor close to
the battery pack. The NTC circuitry is shown in the Block
Diagram.
To prevent thermal damage to the LTC4098-3.6 or surrounding components, an internal thermal feedback loop
will automatically decrease the programmed charge current
if the die temperature rises to approximately 110°C. Thermal regulation protects the LTC4098-3.6 from excessive
temperature due to high power operation or high ambient thermal conditions, and allows the user to push the
limits of the power handling capability with a given circuit
board design without risk of damaging the LTC4098-3.6
or external components. The benefit of the LTC4098-3.6
thermal regulation loop is that charge current can be set
according to actual conditions rather than worst-case
conditions for a given application with the assurance
that the charger will automatically reduce the current in
worst-case conditions.
To use this feature, connect the NTC thermistor, RNTC,
between the NTC pin and ground and a bias resistor, RNOM,
from NTCBIAS to NTC. RNOM should be a 1% resistor with
a value equal to the value of the chosen NTC thermistor
at 25°C (R25).
The LTC4098-3.6 will pause charging when the resistance
of the NTC thermistor drops to 0.25 times the value of R25
or approximately 25k (for a Vishay curve 1 thermistor, this
corresponds to approximately 60°C). If the battery charger
is in constant-voltage (float) mode, the safety timer also
pauses until the thermistor indicates a return to a valid
temperature. As the temperature drops, the resistance of
the NTC thermistor rises. The LTC4098-3.6 is also designed
to pause charging when the value of the NTC thermistor
increases to 3.26 times the value of R25. For a Vishay
curve 1 thermistor, this resistance, 326k, corresponds to
approximately 0°C. The hot and cold comparators each
have approximately 3°C of hysteresis to prevent oscillation about the trip point. Grounding the NTC pin disables
all NTC functionality.
Figure 6 is a flow chart representation of the battery charger
algorithm employed by the LTC4098-3.6.
Shutdown Mode
The USB switching regulator is enabled whenever VBUS is
above the UVLO voltage and the LTC4098-3.6 is not in one
of the two USB suspend modes (500µA or 2.5mA). When
power is available from both the USB and high voltage
inputs, the high voltage regulator is prioritized and the
USB switching regulator is disabled.
The ideal diode is enabled at all times and cannot be
disabled.
409836f
19
LTC4098-3.6
OPERATION
POWER ON/
ENABLE CHARGER
CLEAR EVENT TIMER
ASSERT CHRG LOW
NTC OUT OF RANGE
YES
INHIBIT CHARGING
NO
PAUSE EVENT TIMER
BAT < 2.85V
BATTERY STATE
BAT > VFLOAT – ε
2.85V < BAT < VFLOAT – ε
CHRG CURRENTLY
Hi-Z
CHARGE WITH
FIXED VOLTAGE
(VFLOAT)
CHARGE AT
1030V/RPROG RATE
YES
NO
PAUSE EVENT TIMER
RUN EVENT TIMER
NO
INDICATE
NTC FAULT
AT CHRG
RUN EVENT TIMER
TIMER > 30 MINUTES
TIMER > 1 HOUR
YES
NO
YES
INHIBIT CHARGING
STOP CHARGING
IBAT < C/10
NO
YES
BAT RISING
THROUGH
VRECHRG
INDICATE BATTERY
FAULT AT CHRG
YES
CHRG HIGH-Z
CHRG Hi-Z
NO
BAT > 2.85V
YES
NO
BAT FALLING
THROUGH
VRECHRG
NO
YES
BAT < VRECHRG
NO
YES
40981 F06
Figure 6. Battery Charger State Diagram
409836f
20
LTC4098-3.6
APPLICATIONS INFORMATION
CLPROG Resistor and Capacitor
VBUS and VOUT Bypass Capacitors
As described in the Bat-Track Input Current Limited Step
Down Switching Regulator section, the resistor on the
CLPROG pin determines the average input current limit
in each of the five current limit modes. The input current will be comprised of two components, the current
that is used to drive VOUT and the quiescent current of
the switching regulator. To ensure that the total average
input current remains below the USB specification, both
components of input current should be considered. The
Electrical Characteristics table gives the typical values for
quiescent currents in all settings as well as current limit
programming accuracy. To get as close to the 500mA or
100mA specifications as possible, a precision resistor
should be used.
The style and value of capacitors used with the
LTC4098‑3.6 determine several important parameters
such as regulator control loop stability and input voltage ripple. Because the LTC4098-3.6 uses a step-down
switching power supply from VBUS to VOUT, its input
current waveform contains high frequency components.
It is strongly recommended that a low equivalent series
resistance (ESR) multilayer ceramic capacitor be used
to bypass VBUS. Tantalum and aluminum capacitors are
not recommended because of their high ESR. The value
of the capacitor on VBUS directly controls the amount
of input ripple for a given load current. Increasing the
size of this capacitor will reduce the input ripple. The
USB specification allows a maximum of 10µF to be connected directly across the USB power bus. If additional
capacitance is required for noise performance, it may
be connected directly to the VBUS pin when using the
OVP feature of the LTC4098-3.6. This extra capacitance
will be soft-connected over several milliseconds to limit
inrush current and avoid excessive transient voltage
drops on the bus.
An averaging capacitor is required in parallel with the
resistor so that the switching regulator can determine
the average input current. This capacitor also provides
the dominant pole for the feedback loop when current
limit is reached. To ensure stability, the capacitor on
CLPROG should be 0.1µF or larger.
Choosing the Inductor
To prevent large VOUT voltage steps during transient
load conditions, it is also recommended that a ceramic
capacitor be used to bypass VOUT. The output capacitor
is used in the compensation of the switching regulator. At
least 10µF with low ESR are required on VOUT. Additional
capacitance will improve load transient performance
and stability.
Because the input voltage range and output voltage range
of the PowerPath switching regulator are both fairly narrow,
the LTC4098-3.6 was designed for a specific inductance
value of 3.3µH. Some inductors which may be suitable
for this application are listed in Table 3.
Table 3. Recommended Inductors for the LTC4098-3.6
INDUCTOR TYPE
L
(µH)
MAX IDC MAX DCR
(A)
(Ω)
SIZE IN mm
(L × W × H)
LPS4018
3.3
2.2
0.08
3.9 × 3.9 × 1.7
Coilcraft
www.coilcraft.com
D53LC
DB318C
3.3
3.3
2.26
1.55
0.034
0.070
5×5×3
3.8 × 3.8 × 1.8
Toko
www.toko.com
WE-TPC Type M1
3.3
1.95
0.065
4.8 × 4.8 × 1.8
Würth Elektronik
www.we-online.com
CDRH6D12
CDRH6D38
3.3
3.3
2.2
3.5
0.0625
0.020
6.7 × 6.7 × 1.5
7×7×4
Sumida
www.sumida.com
MANUFACTURER
409836f
21
LTC4098-3.6
APPLICATIONS INFORMATION
Multilayer ceramic chip capacitors typically have exceptional ESR performance. MLCCs combined with a tight
board layout and an unbroken ground plane will yield very
good performance and low EMI emissions.
There are several types of ceramic capacitors available each having considerably different characteristics.
For example, X7R ceramic capacitors have the best voltage
and temperature stability. X5R ceramic capacitors have
apparently higher packing density but poorer performance
over their rated voltage and temperature ranges. Y5V
ceramic capacitors have the highest packing density,
but must be used with caution, because of their extreme
nonlinear characteristic of capacitance versus voltage. The
actual in-circuit capacitance of a ceramic capacitor should
be measured with a small AC signal and DC bias as is
expected in-circuit. Many vendors specify the capacitance
versus voltage with a 1VRMS AC test signal and, as a result,
over state the capacitance that the capacitor will present
in the application. Using similar operating conditions as
the application, the user must measure or request from
the vendor the actual capacitance to determine if the
selected capacitor meets the minimum capacitance that
the application requires.
MN1
V1
WALL
OVGATE
LTC4098-3.6
V2
D1
D2
MN2
VBUS
C1
R1
Overprogramming the Battery Charger
The USB high power specification allows for up to 2.5W
to be drawn from the USB port. The switching regulator
transforms the voltage at VBUS to just above the voltage
at BAT with high efficiency, while limiting power to less
than the amount programmed at CLPROG. The charger
should be programmed (with the PROG pin) to deliver the
maximum safe charging current without regard to the USB
specifications. If there is insufficient current available to
charge the battery at the programmed rate, it will reduce
charge current until the system load on VOUT is satisfied
and the VBUS current limit is satisfied. Programming the
charger for more current than is available will not cause
the average input current limit to be violated. It will merely
allow the battery charger to make use of all available
power to charge the battery as quickly as possible, and
with minimal power dissipation within the charger.
Overvoltage Protection
It is possible to protect both VBUS and WALL from overvoltage damage with several additional components, as
shown in Figure 7. Schottky diodes D1 and D2 pass the
larger of V1 and V2 to R1 and OVSENS. If either V1 or V2
exceeds 6V plus VF(SCHOTTKY), OVGATE will be pulled to
GND and both the WALL and USB inputs will be protected.
Each input is protected up to the drain-source breakdown,
BVDSS, of MN1 and MN2. R1 must also be rated for the
power dissipated during maximum overvoltage. See the
Operations section for an explanation of this calculation.
Table 4 shows some N-channel MOSFETs that may be
suitable for overvoltage protection.
Table 4. Recommended OVP MOSFETs
OVSENS
409836 F07
Figure 7. Dual Input Overvoltage Protection
N-CHANNEL
MOSFET
BVDSS
RON
PACKAGE
Si2302ADS
20V
70mW
SOT-23
IRLML2502
20V
35mW
SOT-23
Si1472DH
30V
65mW
SC70-6
NTLJS4114N
30V
20mW
2mm × 2mm DFN
FDN372S
30V
45mW
SOT-23
409836f
22
LTC4098-3.6
APPLICATIONS INFORMATION
Reverse Voltage Protection
The LTC4098-3.6 can also be easily protected against the
application of reverse voltage, as shown in Figure 8. D1
and R1 are necessary to limit the maximum VGS seen by
MP1 during positive overvoltage events. D1’s breakdown
voltage must be safely below MP1’s BVGS. The circuit
shown in Figure 8 offers forward voltage protection up
to MN1’s BVDSS and reverse voltage protection up to
MP1’s BVDSS.
USB/WALL
ADAPTER
MP1
MN1
D1
VBUS
adjustment resistor, both the upper and the lower temperature trip points can be independently programmed with
the constraint that the difference between the upper and
lower temperature thresholds cannot decrease. Examples
of each technique follow.
NTC thermistors have temperature characteristics which
are indicated on resistance-temperature conversion tables.
The Vishay-Dale thermistor NTHS0603N011-N1003F, used
in the following examples, has a nominal value of 100k
and follows the Vishay curve 1 resistance-temperature
characteristic.
In the explanation below, the following notation is used.
C1
R25 = Value of the thermistor at 25°C
LTC4098-3.6
R1
R2
RNTC|COLD = Value of thermistor at the cold trip point
OVGATE
OVSENS
VBUS POSITIVE PROTECTION UP TO BVDSS OF MN1
VBUS NEGATIVE PROTECTION UP TO BVDSS OF MP1
RNTC|HOT = Value of thermistor at the hot trip point
409836 F08
aCOLD = Ratio of RNTC|COLD to R25
aHOT = Ratio of RNTC|HOT to R25
Figure 8. Dual-Polarity Voltage Protection
RNOM = Primary thermistor bias resistor (see Figure 9a)
Alternate NTC Thermistors and Biasing
The LTC4098-3.6 provides temperature-qualified charging
if a grounded thermistor and a bias resistor are connected
to NTC and NTCBIAS. By using a bias resistor whose
value is equal to the room temperature resistance of the
thermistor (R25) the upper and lower temperatures are
preprogrammed to approximately 60°C and 0°C, respectively (assuming a Vishay curve 1 thermistor).
The upper and lower temperature thresholds can be adjusted by either a modification of the bias resistor value
or by adding a second adjustment resistor to the circuit.
If only the bias resistor is adjusted, then either the upper
or the lower threshold can be modified but not both. The
other trip point will be determined by the characteristics
of the thermistor. Using the bias resistor in addition to an
R1 = Optional temperature range adjustment resistor
(see Figure 9b)
The trip points for the LTC4098-3.6’s temperature qualification are internally programmed at 0.199 • NTCBIAS
for the hot threshold and 0.765 • NTCBIAS for the cold
threshold.
Therefore, the hot trip point is set when:
RNTC|HOT
+
RNOM RNTC|HOT
• NTCBIAS = 0.199 • NTCBIAS
and the cold trip point is set when:
RNTC|COLD
RNOM + RNTC|COLD
• NTCBIAS = 0.765 • NTCBIAS
409836f
23
LTC4098-3.6
APPLICATIONS INFORMATION
Solving these equations for RNTC|COLD and RNTC|HOT
results in the following:
RNTC|HOT = 0.25 • RNOM
and
RNTC|COLD = 3.26 • RNOM
By setting RNOM equal to R25, the previous equations
result in aHOT = 0.25 and aCOLD = 3.26. Referencing
these ratios to the Vishay Resistance-Temperature curve
1 chart gives a hot trip point of about 60°C and a cold trip
point of about 0°C. The difference between the hot and
cold trip points is approximately 60°C.
NTCBIAS
By using a bias resistor, RNOM, different in value from
R25, the hot and cold trip points can be moved in either
direction. The temperature span will change somewhat due
to the nonlinear behavior of the thermistor. The following
equations can be used to easily calculate a new value for
the bias resistor:
RNOM =
αHOT
• R25
0.25
RNOM =
α COLD
• R25
3.26
where aHOT and aCOLD are the resistance ratios at the
desired hot and cold trip points. Note that these equations
NTCBIAS
LTC4098-3.6 NTC BLOCK
0.765 • NTCBIAS
RNOM
100k
0.765 • NTCBIAS
RNOM
102k
RNTC
100k
0.199 • NTCBIAS
+
5
R1
8.06k
–
TOO_HOT
–
0.199 • NTCBIAS
+
T
–
TOO_COLD
NTC
+
5
T
–
TOO_COLD
NTC
LTC4098-3.6 NTC BLOCK
4
4
RNTC
100k
TOO_HOT
+
+
+
NTC_ENABLE
NTC_ENABLE
0.1V
–
0.1V
–
409836 F09b
409836 F09a
(9a)
(9b)
Figure 9. NTC Circuits
409836f
24
LTC4098-3.6
APPLICATIONS INFORMATION
are linked. Therefore, only one of the two trip points can
be chosen, the other is determined by the default ratios
designed in the IC. Consider an example where a 70°C
hot trip point is desired.
From the Vishay curve 1 R-T characteristics, aHOT is
0.1753 at 70°C. Using the previous equation, RNOM should
be set to 70.4k. With this value of RNOM, the cold trip point
is 7°C. Notice that the span is now 63°C rather than the
previous 60°C. This is due to the decrease in temperature
gain of the thermistor as absolute temperature increases.
The upper and lower temperature trip points can be independently programmed by using an additional bias resistor
as shown in Figure 9b. The following formulas can be used
to compute the values of RNOM and R1:
α
– αHOT
RNOM = COLD
• R25
3.01
R1 = 0.25 • RNOM – αHOT • R255
For example, to set the trip points to 0°C and 70°C with
a Vishay curve 1 thermistor choose:
RNOM =
USB Inrush Limiting
The USB specification allows at most 10µF of downstream
capacitance to be hot-plugged into a USB hub. In most
LTC4098-3.6 applications, 10µF should be enough to
provide adequate filtering on VBUS.
If more capacitance is required, the OVP circuit will provide
adequate soft-connect time to prevent excessive inrush
currents. An additional 22µF on the VBUS pin will generally contribute less than 100mA to the hot-plug inrush
current.
Voltage overshoot on VBUS may sometimes be observed
when connecting the LTC4098-3.6 to a lab power supply.
This overshoot is caused by long leads from the power
supply to VBUS. Twisting the wires together from the supply to VBUS can greatly reduce the parasitic inductance
of these long leads, and keep the voltage at VBUS to safe
levels. USB cables are generally manufactured with the
power leads in close proximity, and thus fairly low parasitic
inductance.
3.26 – 0.1753
• 100k = 102.5k
3.01
the nearest 1% value is 102k:
R1 = 0.25 • 102k – 0.1753 • 100k = 7.97k
the nearest 1% value is 8.06k. The final circuit is shown
in Figure 9b and results in an upper trip point of 70°C and
a lower trip point of 0°C.
409836f
25
LTC4098-3.6
APPLICATIONS INFORMATION
Board Layout Considerations
The exposed pad on the backside of the LTC4098-3.6 package must be securely soldered to the PC board ground.
This is the primary ground pin in the package and it serves
as the return path for both the control circuitry and the
synchronous rectifier.
Furthermore, due to its high frequency switching circuitry,
it is imperative that the input capacitor, inductor, and
output capacitor be as close to the LTC4098-3.6 as possible and that there be an unbroken ground plane under
the LTC4098-3.6 and all of its external high frequency
components. High frequency currents, such as the input
current on the LTC4098-3.6, tend to find their way on the
ground plane along a mirror path directly beneath the
incident path on the top of the board. If there are slits or
cuts in the ground plane due to other traces on that layer,
the current will be forced to go around the slits. If high
frequency currents are not allowed to flow back through
their natural least-area path, excessive voltage will build up
and radiated emissions will occur (see Figure 10). There
should be a group of vias directly under the grounded
backside leading directly down to an internal ground
plane. To minimize parasitic inductance, the ground plane
should be as close as possible to the top plane of the PC
board (layer 2).
409836 F10
Figure 10. Ground Currents Follow Their Incident Path
at High Speed. Slices in the Ground Plane Cause High
Voltage and Increased Emissions
The IDGATE pin for the external ideal diode controller has
extremely limited drive current. Care must be taken to
minimize leakage to adjacent PC board traces. 100nA of
leakage from this pin will introduce an additional offset to
the ideal diode of approximately 10mV. To minimize leakage,
the trace can be guarded on the PC board by surrounding
it with VOUT connected metal, which should generally be
less than one volt higher than IDGATE.
Battery Charger Stability Considerations
The LTC4098-3.6’s battery charger contains both a constant-voltage and a constant-current control loop. The
constant-voltage loop is stable without any compensation
when a battery is connected with low impedance leads.
Excessive lead length, however, may add enough series
inductance to require a bypass capacitor of at least 1µF
from BAT to GND.
High value, low ESR multilayer ceramic chip capacitors
reduce the constant-voltage loop phase margin, possibly
resulting in instability. Ceramic capacitors up to 22µF may
be used in parallel with a battery, but larger ceramics should
be decoupled with 0.2Ω to 1Ω of series resistance.
Furthermore, a 100µF MLCC in series with a 0.3Ω resistor
or a 100µF OS-CON capacitor from BAT to GND is required
to prevent oscillation when the battery is disconnected.
In constant-current mode, the PROG pin is in the feedback loop rather than the battery voltage. Because of the
additional pole created by any PROG pin capacitance,
capacitance on this pin must be kept to a minimum. With
no additional capacitance on the PROG pin, the charger
is stable with program resistor values as high as 25k.
However, additional capacitance on this node reduces the
maximum allowed program resistor. The pole frequency at
the PROG pin should be kept above 100kHz. Therefore, if
the PROG pin has a parasitic capacitance, CPROG, the following equation should be used to calculate the maximum
resistance value for RPROG:
RPROG ≤
1
2π • 100kHz • CPROG
409836f
26
LTC4098-3.6
TYPICAL APPLICATIONS
High Efficiency USB/2A Automotive Battery Charger with Overvoltage
Protection and Low Battery Start-Up
4
AUTOMOTIVE,
FIREWIRE, ETC.
C1
C7
4.7µF 68nF
R10
40.2k
R11
150k
5
10
C6
0.47µF
2
VIN
BOOST
3
SW
LT3480
RUN/SS
PG
VC
7
C4
22µF
BD
GND
9
R9
R8
499k 100k
D3
8
FB
RT
L2
10µH
11
1
M1
L1
3.3µH
M3
USB
13
C2
10µF
0805 2
R3
6.04k
TO µC
1
3
15-17
8
TO µC
4
M1, M2: VISHAY-SILICONIX Si2333CDS
M3: ON SEMICONDUCTOR NTLJS4114N
R5: VISHAY-DALE NTHS0603N011-N1003F
R4
100k
R5
T
100k
5
20
VBUS
18
VC WALL
19
ACPR SW
OVGATE
VOUT
OVSENS
IDGATE
D0-D2
SYSTEM
LOAD
14
BAT
LTC4098-3.6
12
10
M2
11
CHRG
C5
10µF
0805
NTCBIAS
NTC
CLPROG
C3
0.1µF
0603
PROG GND BATSENS
3
7
R6
3.01k
R7
681Ω
9, 21
6
+
LiFePO4
409836 TA02
409836f
27
LTC4098-3.6
TYPICAL APPLICATIONS
USB/Wall Adapter Battery Charger with Dual Overvoltage Protection,
Reverse-Voltage Protection and Low Battery Start-Up
M1
5V WALL ADAPTER
M3
C1
10µF
0805
D3
R1
M5
R2
L1
3.3µH
D4
13
USB
M2
C2
10µF
0805
M4
D1
D2
R3
6.04k
1
3
TO µC
15-17
8
TO µC
4
M1, M2, M5, M6: VISHAY-SILICONIX Si2333CDS
M3, M4: FAIRCHILD SEMI FDN372S
R5: VISHAY-DALE NTHS0603N011-N1003F
D1, D2: NXP BAT54C
D3, D4: ON SEMICONDUCTOR MNBZ5232BLT1G
R4
100k
T
5
R5
100k
2
VBUS
18
OVGATE
19
WALL
ACPR SW
VOUT
IDGATE
OVSENSE
D0-D2
SYSTEM
LOAD
14
BAT
LTC4098-3.6
12
10
M6
11
CHRG
C4
10µF
0805
NTCBIAS
NTC
CLPROG
C3
0.1µF
0603
PROG
GND BATSENS
3
7
R6
3.01k
R7
681Ω
9, 21
6
+
LiFePO4
409836 TA03
USB/Automotive Switching Battery Charger with
Automatic Current Limiting on Both Inputs
1
AUTOMOTIVE,
FIREWIRE, ETC.
C1
4.7µF
7
BOOST
VIN
R1
27.4k
M1
6
GND
13
C3
10µF
0805 2
R6
6.04k
TO µC
1
3
15-17
8
TO µC
4
M1: ON SEMICONDUCTOR NTLJS4114N
R3: VISHAY-DALE NTHS0603N011-N1003F
R2
100k
R3
T
100k
5
L1
4.7µH
D1
LT3653
ILIM
VC
9
USB
WALL ADAPTER
8
SW
4
C2
0.1µF
10V
3
2
20
VBUS
ISENSE
5
VOUT
HVOK
18
VC
L2
3.3µH
19
14
OVGATE
VOUT
OVSENS
IDGATE
D0-D2
C5
10µF
0805
WALL ACPR SW
BAT
LTC4098-3.6
12
10
11
SYSTEM
LOAD
CHRG
NTCBIAS
NTC
CLPROG
C4
0.1µF
0603
PROG GND BATSENS
3
7
R4
3.01k
R5
681Ω
9, 21
6
+
LiFePO4
409836 TA04
409836f
28
LTC4098-3.6
TYPICAL APPLICATIONS
Low Component Count USB and Automotive High Efficiency Power Manager
1
AUTOMOTIVE,
FIREWIRE, ETC.
C1
4.7µF
7
BOOST
VIN
SW
4
R1
27.4k
ILIM
C3
10µF
0805
2
1
TO µC
TO µC
3
D1
VC
VBUS
ISENSE
5
VOUT
HVOK
3
2
20
18
VC
L2
3.3µH
19
8
4
5
SYSTEM
LOAD
14
WALL ACPR SW
OVGATE
VOUT
OVSENS
IDGATE
LTC4098-3.6
15-17
L1
4.7µH
6
GND
13
8
LT3653
9
USB
WALL ADAPTER
C2
0.1µF
10V
BAT
12
10
11
D0-D2
CHRG
NTCBIAS
NTC CLPROG
C4
0.1µF
0603
PROG
C5
10µF
0805
GND BATSENS
3
7
R2
3.01k
R3
681Ω
9, 21
6
+
LiFePO4
409836 TA05
409836f
29
LTC4098-3.6
TYPICAL APPLICATIONS
High Efficiency USB Automotive Battery Charger
with Overvoltage Protection and Low Battery Start-Up
1
AUTOMOTIVE,
FIREWIRE, ETC.
C1
4.7µF
50V
BOOST
VIN
SW
4
R2
27.4k
M2
13
R4
6.04k
TO µC
1
3
15-17
8
TO µC
4
M1: VISHAY-SILICONIX Si2333CDS
M2: ON SEMICONDUCTOR NTLJS4114N
R6: VISHAY-DALE NTHS0603N011-N1003F
R5
100k
T
R6
100k
5
L1
4.7µH
D2
6
GND
C3
10µF
0805 2
C2
0.1µF, 10V
LT3653
ILIM
VC
9
USB
7
8
VBUS
HVOK
3
2
20
18
VC
ISENSE
5
VOUT
19
VOUT
LTC4098-3.6
D0-D2
SYSTEM
LOAD
14
WALL ACPR SW
OVGATE
OVSENS
L2
3.3µH
IDGATE
BAT
12
10
M1
11
CHRG
C5
10µF
0805
NTCBIAS
NTC CLPROG
C4
0.1µF
0603
PROG
GND BATSENS
3
7
R7
3.01k
R8
681Ω
9, 21
6
+
LiFePO4
409836 TA06
409836f
30
LTC4098-3.6
PACKAGE DESCRIPTION
UDC Package
20-Lead Plastic QFN (3mm × 4mm)
(Reference LTC DWG # 05-08-1742 Rev Ø)
0.70 ±0.05
3.50 ± 0.05
2.10 ± 0.05
2.65 ± 0.05
1.50 REF
1.65 ± 0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
2.50 REF
3.10 ± 0.05
4.50 ± 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
3.00 ± 0.10
0.75 ± 0.05
1.50 REF
19
R = 0.05 TYP
PIN 1 NOTCH
R = 0.20 OR 0.25
× 45° CHAMFER
20
0.40 ± 0.10
1
PIN 1
TOP MARK
(NOTE 6)
4.00 ± 0.10
2
2.65 ± 0.10
2.50 REF
1.65 ± 0.10
(UDC20) QFN 1106 REV Ø
0.200 REF
0.00 – 0.05
R = 0.115
TYP
0.25 ± 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
409836f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
31
LTC4098-3.6
TYPICAL APPLICATION
1.5A Standalone LiFeP04 Charger
L1
3.3µH
13
WALL ADAPTER
C1
10µF
0805
2
1
15
R1
2k
ON OFF
8
17
16
20
VBUS
VC
18
19
WALL
ACPR
14
SW
OVGATE
VOUT
OVSENS
IDGATE
D0
BAT
LTC4098-3.6
BATSENS
CHRG
NTCBIAS
D2
D1
NTC
CLPROG
C2
0.1µF
0603
PROG
GND
3
7
R2
2k
R3
681Ω
9, 21
12
10
11
SYSTEM
LOAD
6
4
5
C3
10µF
0805
R4
100k
T R5
100k
+
LiFePO4
409836 TA07
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PART NUMBER
DESCRIPTION
COMMENTS
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