LTC4268-1
High Power PD With
Synchronous No-Opto
Flyback Controller
Description
Features
Robust 35W PD Front End
IEEE 802.3af Compliant
n Rugged 750mA Power MOSFET With Precision Dual
Level Current Limit
n High Performance Synchronous Flyback Controller
n IEEE Isolation Obtained Without an Opto-Isolator
n Adjustable Frequency from 50kHz to 250kHz
n Tight Multi-Output Regulation With Load
Compensation
n Onboard 25k Signature Resistor
n Programmable Classification Current to 75mA
n Complete Thermal and Over-Current Protection
n Available in Compact 32-Pin 7mm × 4mm DFN
Package
The LTC®4268-1 is an integrated Powered Device (PD)
controller and switching regulator intended for IEEE 802.3af
and high power PoE applications up to 35W. By including
a precision dual current limit, the LTC4268-1 keeps inrush
below IEEE 802.3af current limit levels to ensure interoperability success while enabling high power applications
with a 750mA operational current limit.
Applications
The oversized power path and high performance flyback
controller of the LTC4268-1 combine to make the ultimate
solution for power hungry PoE applications such as WAPs,
PTZ security cameras, RFID readers and ultra-efficient
802.3af applications running near the 12.95W limit.
n
n
n
n
n
n
n
n
n
The LTC4268-1 synchronous, current-mode, flyback
controller generates multiple supply rails in a single
conversion providing for the highest system efficiency
while maintaining tight regulation across all outputs. The
LTC4268-1 includes Linear Technology’s patented No-Opto
feedback topology to provide full IEEE 802.3af isolation
without the need of opto-isolator circuitry.
VoIP Phones With Advanced Display Options
Dual-Radio Wireless Access Points
PTZ Security Cameras
RFID Readers
Industrial Controls
Magnetic Card Readers
High Power PoE Systems
The LTC4268-1 is available in a space saving 32-pin DFN
package.
L, LT, LTC, LTM and SwitcherCAD are registered trademarks and LTPoE++ and ThinSOT are
trademarks of Linear Technology Corporation. All other trademarks are the property of their
respective owners. Protected by U.S. Patents including 5841643.
Typical Application
35W High Efficiency PD Solution
BAS21
47k
SMAJ58A
DF1501S
–54V FROM
DATA PAIR
~ +
~ –
~ +
~ –
3.01k
1%
≥5µF
+
RCLASS
•
56Ω
Si4490DY
3.3V
470µF
×4
47Ω
T1
B0540W
FMMT618
Si7336ADP
FMMT718
1µF
0.02Ω
SHDN
VPORTN
+
•
100pF
FB PG SENSE+
VCC
VPORTP PWRGD PWRGD UVLO ILIM_EN
SENSE–
LTC4268-1
RCLASS
T1: PA1477NL
T2: PA0184
T1
•
47µF
0.1µF
DF1501S
–54V FROM
SPARE PAIR
20Ω
100k
28.7k
1%
SG
VNEG PGDLY
12k
tON SYNC RCMP ENDLY
169k
VCMP
OSC GND SFST CCMP
100k
47pF
15Ω
330Ω
2.2nF
0.1µF
T2
10nF
20k
•
•
10k
BAT54
42681 TA01a
0.033µF
42681fc
1
LTC4268-1
Absolute Maximum Ratings
Pin Configuration
(Notes 1, 2)
VPORTN Voltage........................................... 0.3V to –90V
VNEG Voltage...................VPORTN + 90V to VPORTN –0.3V
VCC to GND Voltage (Note 3)
Low Impedance Source.......................... –0.3V to 18V
Current Fed...........................................30mA into VCC
RCLASS, ILIM_EN Voltage...VPORTN + 7V to VPORTN – 0.3V
SHDN Voltage................ VPORTN + 90V to VPORTN – 0.3V
PWRGD Voltage (Note 3)
Low Impedance Source..... VNEG + 11V to VNEG – 0.3V
Current Fed...........................................................5mA
PWRGD Voltage............. VPORTN + 80V to VPORTN – 0.3V
PWRGD Current......................................................10mA
RCLASS Current.....................................................100mA
SENSE–, SENSE+ Voltage......................... –0.5V to +0.5V
UVLO, SYNC Voltage....................................–0.3V to VCC
FB Current...............................................................±2mA
VCMP Current.......................................................... ±1mA
Operating Ambient Temperature Range (Notes 4, 5)
LTC4268-1C.............................................. 0°C to 70°C
LTC4268-1I...........................................–40°C to 85°C
Junction Temperature (Note 5).............................. 150°C
Storage Temperature Range................... –65°C to 150°C
TOP VIEW
SHDN
1
32 VPORTP
NC
2
31 NC
RCLASS
3
30 PWRGD
ILIM_EN
4
29 PWRGD
VPORTN
5
28 VNEG
VPORTN
6
27 VNEG
VPORTN
7
26 VNEG
NC
8
SG
9
33
25 NC
24 PG
VCC 10
23 PGDLY
tON 11
22 RCMP
ENDLY 12
21 CCMP
SYNC 13
20 SENSE+
SFST 14
19 SENSE–
OSC 15
18 UVLO
FB 16
17 VCMP
DKD32 PACKAGE
32-LEAD (7mm × 4mm) PLASTIC DFN
TJMAX = 150°C,θJA = 49°C/W, θJC = 4.7°C/W
EXPOSED PAD (PIN 33) MUST BE SOLDERED TO
HEAT SINKING PLANE THAT IS ELECTRICALLY CONNECTED TO GND
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4268CDKD-1#PBF
LTC4268IDKD-1#PBF
LTC4268CDKD-1#TRPBF
LTC4268IDKD-1#TRPBF
42681
42681
32-Lead (7mm × 4mm) Plastic DFN
32-Lead (7mm × 4mm) Plastic DFN
0°C to 70°C
–40°C to 85°C
LEAD BASED FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4268CDKD-1
LTC4268IDKD-1
LTC4268CDKD-1#TR
LTC4268IDKD-1#TR
42681
42681
32-Lead (7mm × 4mm) Plastic DFN
32-Lead (7mm × 4mm) Plastic DFN
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
42681fc
2
LTC4268-1
Electrical
Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 14V, SG open, VCMP = 1.5V, VSENSE = 0V, RCMP = 1k, RtON = 90k,
RPGDLY = 27.4k, RENDLY = 90k, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
VPORT
Supply Voltage
Voltage With Respect to VPORTP Pin
(Notes 6, 7, 8, 9, 10)
IEEE 802.3af System
Signature Range
Classification Range
UVLO Turn-On Voltage
UVLO Turn-Off Voltage
MIN
TYP
MAX
UNITS
V
V
V
V
V
l
l
l
l
l
–1.5
–12.5
–37.7
–29.8
–38.9
–30.6
–57
–10.1
–21
–40.2
–31.5
16.6
V
VTURNON
VCC Turn-On Voltage
Voltage With Respect to GND
l
14
15.3
VTURNOFF
VCC Turn-Off Voltage
Voltage With Respect to GND
l
8
9.7
11
V
VHYST
VCC Hysteresis
VTURNON – VTURNOFF
l
4
5.6
7.2
V
VCLAMP
VCC Shunt Regulator Voltage
IVCC = 15mA, VUVLO = 0V, Voltage With
Respect to GND
l
19.5
20.2
IVCC
VCC Supply Current
VCMP = Open (Note 11)
l
4
6.4
10
mA
IVCC_START
VCC Start-Up Current
VCC = 10V
l
180
400
µA
VFB
Feedback Regulation Voltage
1.237
1.251
V
IFB_BIAS
Feedback Pin Input Bias Current
gm
l
1.22
RCMP Open
V
200
nA
Feedback Amplifier
Transconductance
l
700
1000
1400
A/V
IFB
Feedback Amplifier Source or Sink
Current
l
25
55
90
µA
VFBCLAMP
Feedback Amplifier Clamp Voltage
VFB = 0.9V
VFB = 1.4V
%VREF
Reference Voltage Line Regulation
12V ≤ VCC ≤ 18V
2.56
0.84
0.005
l
AV
Feedback Amplifier Voltage Gain
VCMP = 1.2V to 1.7V
ISFST
Soft-Start Charging Current
VSFST = 1.5V
16
20
ISFST
Soft-Start Discharge Current
VSFST = 1.5V, VUVLO = 0V
0.8
1.3
VCMP_THLD
Control Pin Threshold (VCMP)
Duty Cycle = Min
VPG_HIGH,
VSG_HIGH
PG, SG, Output High Level
l
VPG_LOW,
PG, SG, Output Low Level
V
V
0.02
1500
V/V
25
µA
mA
1
6.6
%/V
V
7.4
8
V
l
0.01
0.05
V
l
1.4
2.3
V
VSG_LOW
VPG_SHDN,
VSG_SHDN
PG, SG, Output Shutdown Strength
VUVLO = 0V; IPG, ISG = 20mA
tPG_RISE,
tSG_RISE
PG, SG Rise Time
CPG, CSG = 1nF
15
ns
tPG_FALL,
tSG_FALL
PG, SG Fall Time
CPG, CSG = 1nF
15
ns
VSENSE_LIM
Switch Current Threshold at Maximum
VCMP
Measured at VSENSE+
DVSENSE/DVCMP
Sense Threshold vs VCMP
VSENSE_OC
Sense Pin Overcurrent Fault Voltage
VSENSE+, VSFST < 1V
l
VIH_SHDN
Shutdown High Level Input Voltage
With Respect to VPORTN
High Level = Shutdown (Note 12)
l
VIL_SHDN
Shutdown Low Level Input Voltage
With Respect to VPORTN
l
l
88
100
110
0.07
205
3
mV
V/V
230
mV
57
V
0.45
V
42681fc
3
LTC4268-1
Electrical
Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 14V, SG open, VCMP = 1.5V, VSENSE = 0V, RCMP = 1k, RtON = 90k,
RPGDLY = 27.4k, RENDLY = 90k, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
RINPUT_SHDN
Shutdown Input Resistance
With Respect to VPORTN
l
MIN
100
VIH_ILIM
ILIM_EN High Level Input Voltage
With Respect to VPORTN (Note 13)
High Level Enables Current Limit
l
4
VIL_ILIM
ILIM_EN Low Level Input Voltage
With Respect to VPORTN (Note 13)
l
1
V
IVPORTN
VPORTN Supply Current
VPORTN = –54V
l
3
mA
IIN_CLASS
IC Supply Current During Classification
VPORTN = –17.5V, VNEG Tied to VPORTP
(Note 14)
l
0.70
mA
DICLASS
Current Accuracy During Classification
10mA < ICLASS < 75mA
–12.5V ≤ VPORTN ≤ –21V (Notes 15, 16)
l
±3.5
%
RSIGNATURE
Signature Resistance
–1.5V ≤ VPORTN ≤ –10.1V, SHDN Tied
to VPORTN, IEEE 802.3af Two-Point
Measurement (Notes 8, 9)
l
26
kW
RINVALID
Invalid Signature Resistance
–1.5V ≤ VPORTN ≤ –10.1V, SHDN Tied
to VPORTP , IEEE 802.3af Two-Point
Measurement (Notes 8, 9)
11.8
kW
VPWRGD_OUT
Active Low Power Good Output Voltage
I = 1mA, VPORTN = –54V, PWRGD
Referenced to VPORTN
l
0.5
V
IPWRGD_LEAK
Active Low Power Good Output Leakage VPORT = 0V, VPWRGD = 57V
l
1
µA
VPWRGD_OUT
Active High Power Good Output Voltage
I = 0.5mA, VPORTN = –52V, VNEG = –4V
PWRGD Referenced to VNEG (Note 17)
l
0.35
V
VPWRGD_VCLAMP
Active High Power Good Voltage
Limiting Clamp
I = 2mA, VNEG = 0V, PWRGD Referenced
to VNEG (Note 3)
l
16.5
V
IPWRGD_LEAK
Active High Power Good Output Leakage VPWRGD = 11V With Respect to VNEG,
VNEG = VPORTN = –54V
l
1
µA
RON
On-Resistance
I = 700mA, VPORTN = –48V, Measured
from VPORTN to VNEG (Note 16)
l
0.6
0.8
W
W
IOUT_LEAK
VOUT Leakage
VPORTN = –57V, VPORTP = SHDN = VNEG =
0V (Note 15)
l
1
µA
ILIM_HI
Input Current Limit, High Level
VPORTN = –54V, VNEG = –53V ILIM_EN
Floating (Notes 18, 19)
l
700
750
800
mA
ILIM_LO
Input Current Limit, Low Level
VPORTN = –54V, VNEG = –53V
(Notes 18, 19)
l
250
300
350
mA
ILIM_DISA
Safeguard Current Limit When ILIM is
Disabled
VPORTN = –54V,
VNEG = –52.5V ILIM_EN Tied to VPORTN
(Notes 18, 19, 20)
1.2
1.45
1.65
A
fOSC
Oscillator Frequency
COSC = 100pF
84
100
110
kHz
COSC
Oscillator Capacitor Value
(Note 21)
200
pF
tON(MIN)
Minimum Switch on Time
200
ns
tENDLY
Flyback Enable Delay Time
265
ns
tPGDLY
PG Turn-On Delay Time
200
ns
DCON(MAX)
Maximum Switch Duty Cycle
l
VSYNC
SYNC Pin Threshold
l
RSYNC
SYNC Pin Input Resistance
0.55
TYP
V
0.62
10
l
14
0.5
33
85
UNITS
kW
23.25
12
MAX
88
1.53
40
%
2.1
V
kW
42681fc
4
LTC4268-1
Electrical
Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 14V, SG open, VCMP = 1.5V, VSENSE = 0V, RCMP = 1k, RtON = 90k,
RPGDLY = 27.4k, RENDLY = 90k, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
ILCOMP
Feedback Pin Load Compensation
Current
VRCMP With VSENSE+ = 0V
MIN
20
µA
VLCOMP
Load Comp to VSENSE Offset Voltage
VSENSE+ = 20mV, VFB = 1.23V
1
mV
VUVLO
UVLO Pin Threshold
IUVLOL
IUVLOH
UVLO Pin Bias Current
l
VUVLO = 1.2V
VUVLO = 1.3V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltages are with respect to VPORTP pin unless otherwise noted.
Note 3: Active High PWRGD internal clamp circuit self-regulates to 14V
with respect to VNEG. VCC has internal 20V clamp with respect to GND.
Note 4: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 5: TJ is calculated from the ambient temperature TA and power
dissipation PDIS according to the formula:
TJ = TA + (PDIS • 49°C/W)
Note 6: The LTC4268-1 operates with a negative supply voltage in the
range of –1.5V to –57V. To avoid confusion, voltages in this data sheet
are referred to in terms of absolute magnitude. Terms such as “maximum
negative voltage” refer to the largest negative voltage and a “rising
negative voltage” refers to a voltage that is becoming more negative.
Note 7: In IEEE 802.3af systems, the maximum voltage at the PD jack is
defined to be –57V.
Note 8: The LTC4268-1 is designed to work with two polarity protection
diodes in series with the input. Parameter ranges specified in the Electrical
Characteristics are with respect to LTC4268-1 pins and are designed to
meet IEEE 802.3af specifications when the drop from the two diodes is
included. See Applications Information.
Note 9: Signature resistance is measured via the two-point DV/DI method
as defined by IEEE 802.3af. The LTC4268-1 signature resistance is offset
from 25k to account for diode resistance. With two series diodes, the total
PD resistance will be between 23.75k and 26.25k and meet IEEE 802.3af
specifications. The minimum probe voltages measured at the LTC4268-1
pins are –1.5V and –2.5V. The maximum probe voltages are –9.1V and
–10.1V.
Note 10: The LTC4268-1 includes hysteresis in the UVLO voltages to
preclude any start-up oscillation. Per IEEE 802.3af requirements, the
LTC4268-1 will power up from a voltage source with 20Ω series resistance
on the first trial.
TYP
MAX
UNITS
1.215
1.237
1.265
V
–0.25
–4.50
0
–3.4
0.25
–2.5
µA
µA
Note 11: Supply current does not include gate charge current to the
MOSFETs. See Application Information.
Note 12: To disable the 25k signature, tie SHDN to VPORTP (±0.1V) or hold
SHDN high with respect to VIN. See Applications Information.
Note13: ILIM_EN pin is pulled high internally and for normal operation
should be left floating. To disable current limit, tie ILIM_EN to VIN. See
Applications Information.
Note 14: IIN_CLASS does not include classification current programmed at
Pin 3. Total supply current in classification mode will be IIN_CLASS + ICLASS
(See Note 15).
Note 15: ICLASS is the measured current flowing through RCLASS. ∆ICLASS
accuracy is with respect to the ideal current defined as ICLASS = 1.237/
RCLASS. TCLASSRDY is the time for ICLASS to settle to within ±3.5% of ideal.
The current accuracy specification does not include variations in RCLASS
resistance. The total classification current for a PD also includes the IC
quiescent current (IIN_CLASS). See Applications Information.
Note 16: This parameter is assured by design and wafer level testing.
Note 17: Active high power good is referenced to VNEG and is valid for
VPORTP – VNEG ≥ 4V.
Note 18: The LTC4268-1 includes a dual current limit. At turn on, before
C1 is charged, the LTC4268-1 current level is set to ILIMIT_LOW. After C1 is
charged and with ILIM_EN floating, the LTC4268-1 switches to ILIMIT_HIGH.
With ILIM_EN pin tied low, the LTC4268-1 switches to ILIMIT_DISA. The
LTC4268-1 stays in ILIMIT_HIGH or ILIMIT_DISA until the input voltage drops
below the UVLO turn-off threshold or a thermal overload occurs.
Note 19: The LTC4268-1 features thermal overload protection. In the event
of an over temperature condition, the LTC4268-1 will turn off the power
MOSFET, disable the classification load current, and present an invalid
power good signal. Once the LTC4268-1 cools below the over temperature
limit, the LTC4268-1 current limit switches to ILIMIT_LOW and normal
operation resumes.
Note 20: ILIMIT_DISA is a safeguard current limit that is activated when the
normal input current limit (ILIMIT_HIGH) is defeated using the ILIM_EN pin.
Currents at or near ILIMIT_DISA will cause significant package heating and
may require a reduced maximum ambient operating temperature in order
to avoid tripping the thermal overload protection.
Note 21: Component value range guaranteed by design.
42681fc
5
LTC4268-1
Typical Performance Characteristics
Input Current vs Input Voltage
25k Detection Range
0.5
Input Current vs Input Voltage
100
TA = 25°C
0.2
0.1
CLASS 5*
60
CLASS 4
40
CLASS 3
CLASS 2
CLASS 1
20
0
–2
–4
–6
INPUT VOLTAGE (V)
–8
0
–10
42681 G01
CLASS 1 OPERATION
11.5
INPUT CURRENT (mA)
0.3
0
TA = 25°C
80
INPUT CURRENT (mA)
INPUT CURRENT (mA)
0.4
Input Current vs Input Voltage
12.0
85°C
10.5
–40°C
10.0
9.5
CLASS 0
0
11.0
–50
–20
–30
–40
INPUT VOLTAGE (V)
*OPTIONAL CLASS 5 CURRENT
–10
9.0
–12
–60
–14
–20
–18
–16
INPUT VOLTAGE (V)
42681 G03
42681 G02
Signature Resistance
vs Input Voltage
Class Operation vs Time
RESISTANCE = ∆V = V2 – V1
∆I I2 – I1
27 DIODES: DF1501S
TA = 25°C
IEEE UPPER LIMIT
On Resistance vs Temperature
TA = 25°C
INPUT
VOLTAGE
10V/DIV
0.8
26
25
LTC4268-1 + 2 DIODES
CLASS
CURRENT
20mA/DIV
24
LTC4268-1 ONLY
IEEE LOWER LIMIT
–3
–4
–7
–5
–8
–6
INPUT VOLTAGE (V)
0.4
0
–50
TIME (10µs/DIV)
–9
–10
42681 G04
75
0
25
50
–25
JUNCTION TEMPERATURE (°C)
Active High PWRGD: Output Low
Voltage vs Current
1.0
TA = 25°C
Current Limit vs Input Voltage
800
TA = 25°C
GND – VNEG = 4V
–40°C
85°C
PWRGD – VNEG (V)
2
1
CURRENT LIMIT (mA)
0.8
3
100
42681 G06
42681 G05
Active Low PWRGD: Output Low
Voltage vs Current
4
0.6
0.2
23
22
V1: –1
V2: –2
VPWRGD_OUT – VPORTN (V)
1.0
RESISTANCE (Ω)
SIGNATURE RESISTANCE (kΩ)
28
–22
0.6
0.4
HIGH CURRENT MODE
600
400
–40°C
0.2
LOW CURRENT MODE
85°C
0
0
2
6
8
4
INPUT CURRENT (mA)
10
42681 G07
0
0
1
0.5
1.5
INPUT CURRENT (mA)
2
42681 G08
200
–40
–55
–45
–50
INPUT VOLTAGE (V)
–60
42681 G09
42681fc
6
LTC4268-1
Typical Performance Characteristics
VCC(ON) and VCC(OFF)
vs Temperature
VCC Start-Up Current
vs Temperature
16
10
300
VCC(ON)
15
9
250
14
11
150
8
–50 –25
0
50
75
25
TEMPERATURE (°C)
100
4
0
–50 –25
125
50
25
75
0
TEMPERATURE (°C)
42681 G10
100
98
96
94
104
205
200
195
–25
0
50
75
25
TEMPERATURE (°C)
90
–50
125
1.237
VFB (V)
1.236
1.235
1.234
1.233
1.232
1.231
100
125
42681 G16
50
25
0
75
TEMPERATURE (°C)
100
125
VFB Reset vs Temperature
1.04
RCMP OPEN
1.03
250
1.02
200
VFB RESET (V)
FEEDBACK PIN INPUT BIAS (nA)
1.239
1.238
–25
42681 G15
Feedback Pin Input Bias
vs Temperature
300
50
25
0
75
TEMPERATURE (°C)
100
42681 G14
VFB vs Temperature
–25
98
92
42681 G13
1.230
–50
100
94
180
–50
1.240
102
96
190
90
–50
125
COSC = 100pF
106
185
100
108
210
92
50
25
0
75
TEMPERATURE (°C)
110
fOSC (kHz)
102
125
Oscillator Frequency
vs Temperature
SENSE = VSENSE+
–
215 WITH VSENSE = 0V
104
100
42681 G12
220
FB = 1.1V
SENSE = VSENSE+
WITH VSENSE– = 0V
–25
125
SENSE Fault Voltage
vs Temperature
SENSE VOLTAGE (mV)
SENSE VOLTAGE (mV)
106
100
VCC = 14V
3
50
–50 –25
25
75
0
TEMPERATURE (°C)
42681 G11
SENSE Voltage vs Temperature
108
STATIC PART CURRENT
5
50
9
110
6
100
VCC(OFF)
10
7
IVCC (mA)
IVCC (µA)
VCC (V)
12
DYNAMIC CURRENT CPG = 1nF,
CSG = 1nF, fOSC = 100kHz
8
200
13
VCC Current vs Temperature
150
100
1.01
1.00
0.99
0.98
50
0
–50 –25
0.97
50
25
75
0
TEMPERATURE (°C)
100
125
42681 G17
0.96
–50
–25
0
50
75
25
TEMPERATURE (°C)
100
125
42681 G18
42681fc
7
LTC4268-1
Typical Performance Characteristics
70
125°C
25°C
50
65
IVCMP (µA)
–10
1050
1000
55
50
–30
950
45
–50
–70
1100
SINK
CURRENT
VFB = 1.4V
60
10
Feedback Amplifier gm
vs Temperature
SOURCE CURRENT
VFB = 1.1V
–40°C
30
IVCMP (µA)
Feedback Amplifier Source and
Sink Current vs Temperature
gm (µmho)
70
Feedback Amplifier Output
Current vs VFB
0.9
1
1.1
1.2
VFB (V)
1.3
40
–50
1.5
1.4
–25
50
25
75
0
TEMPERATURE (°C)
100
42681 G19
3.6
1550
3.5
UVLO (V)
AV (V/V)
1350
1300
IUVLO (µA)
1.240
1400
1.235
1.230
1.225
–25
75
50
25
TEMPERATURE (°C)
0
100
125
1.220
–50 –25
50
25
75
0
TEMPERATURE (°C)
100
42681 G22
22
70
21
60
20
50
TIME (ns)
SFST CHARGE CURRENT (µA)
80
19
18
100
125
42681 G24
16
10
100
125
42681 G25
TA = 25°C
FALL TIME
30
20
75
50
25
TEMPERATURE (°C)
50
25
75
0
TEMPERATURE (°C)
40
17
0
3.0
–50 –25
PG, SG Rise and Fall Times
vs Load Capacitance
23
–25
125
42681 G23
Soft-Start Charge Current
vs Temperature
15
–50
3.3
3.1
1150
1100
–50
3.4
3.2
1250
1200
125
3.7
1.245
1500
100
IUVLO Hysteresis vs Temperature
UVLO vs Temperature
1650
1450
75
0
25
50
TEMPERATURE (°C)
42681 G21
1.250
1600
–25
42681 G20
Feedback Amplifier Voltage Gain
vs Temperature
1700
900
–50
125
0
RISE TIME
0
1
2
3 4 5 6 7
CAPACITANCE (nF)
8
9
10
42681 G26
42681fc
8
LTC4268-1
Typical Performance Characteristics
VCC Clamp Voltage
vs Temperature
21.5
Minimum PG On Time
vs Temperature
340
ICC = 10mA
RtON(MIN) = 158k
330
21.0
tON(MIN) (ns)
320
VCC (V)
20.5
20.0
310
300
290
280
19.5
270
19.0
–50
–25
50
0
75
25
TEMPERATURE (°C)
100
260
–50
125
–25
0
50
75
25
TEMPERATURE (°C)
Enable Delay Time
vs Temperature
PG Delay Time vs Temperature
325
300
250
RENDLY = 90k
305
RPGDLY = 27.4k
285
tENDLY (ns)
200
tPGDLY (ns)
125
42681 G28
42681 G27
150
RPGDLY = 16.9k
100
265
245
225
50
0
–50
100
–25
25
0
75
50
TEMPERATURE (°C)
100
125
42681 G29
205
–50 –25
50
25
75
0
TEMPERATURE (°C)
100
125
42681 G30
42681fc
9
LTC4268-1
Pin Functions
SHDN (Pin 1): Shutdown Input. Used to command the
LTC4268-1 to present an invalid signature and remain
inactive. Connecting SHDN to VPORTP lowers the signature
resistance to an invalid value and disables the LTC4268-1
PD interface operations. If unused, tie SHDN to VPORTN.
NC (Pin 2): No Internal Connection.
RCLASS (Pin 3): Class Select Input. Used to set the current
the LTC4268-1 maintains during classification. Connect a
resistor between RCLASS and VPORTN. (See Table 2.)
ILIM_EN (Pin 4): Input Current Limit Enable. Used for
controlling the LTC4268-1 current limit behavior during
powered operation. For normal operation, float ILIM_EN to
enable ILIMIT_HIGH current. Tie ILIM_EN to VPORTN to disable
input current limit. Note that the inrush current limit will
always be active. See Applications Information.
VPORTN (Pins 5, 6, 7): Power Input. Tie to the PD Input
through the diode bridge. Pins 5, 6 and 7 must be electrically tied together.
SYNC (Pin 13): External Sync Input. This pin is used to
synchronize the internal oscillator with an external clock.
The positive edge of the clock causes the oscillator to discharge causing PG to go low (off) and SG high (on). The
sync threshold is typically 1.5V. Tie to ground if unused.
See Applications Information for details.
SFST (Pin 14): Soft-Start. This pin, in conjunction with a
capacitor (CSFST) to GND, controls the ramp-up of peak
primary current through the sense resistor. It is also used
to control converter inrush at start-up. The SFST clamps
the VCMP voltage and thus limits peak current until softstart is complete. The ramp time is approximately 70ms
per µF of capacitance. Leave SFST open if not using the
soft-start function.
OSC (Pin 15): Oscillator. This pin in conjunction with an
external capacitor (COSC) to GND defines the controller
oscillator frequency. The frequency is approximately
100kHz • 100/COSC (pF).
SG (Pin 9): Secondary Gate Driver Output. This pin provides an output signal for a secondary-side synchronous
switch. Large dynamic currents may flow during voltage
transitions. See the Applications Information for details.
FB (Pin 16): Feedback Amplifier Input. Feedback is usually
sensed via a third winding and enabled during the flyback
period. This pin also sinks additional current to compensate
for load current variation as set by the RCMP pin. Keep the
Thevenin equivalent resistance of the feedback divider at
roughly 3k.
VCC (Pin 10): Converter Voltage Supply. Bypass this pin
to GND with 4.7µF or greater. This pin has a 20V clamp
to ground. VCC has an undervoltage lockout function that
turns on when VCC is approximately 15.3V and off at 9.7V.
In a conventional “trickle-charge” bootstrapped configuration, the VCC supply current increases significantly during
turn-on causing a benign relaxation oscillation action on
the VCC pin if the part does not start normally.
VCMP (Pin 17): Frequency Compensation Control. VCMP is
used for frequency compensation of the switcher control
loop. It is the output of the feedback amplifier and the input
to the current comparator. Switcher frequency compensation components are normally placed on this pin to GND.
The voltage on this pin is proportional to the peak primary
switch current. The feedback amplifier output is enabled
during the synchronous switch on time.
NC (Pin 8): No Internal Connection.
tON (Pin 11): Primary Switch Minimum On Time Control.
A programming resistor (RTon) to GND sets the minimum
time for each cycle. See Applications Information for details.
ENDLY (Pin 12): Enable Delay Time Control. The enable
delay time is set by a programming resistor (RENDLY) to GND
and disables the feedback amplifier for a fixed time after
the turn-off of the primary-side MOSFET. This allows the
leakage inductance voltage spike to be ignored for flyback
voltage sensing. See Applications Information for details.
UVLO (Pin 18): Undervoltage Lockout. A resistive divider
from VIN to this pin sets an undervoltage lockout based
upon VIN level (not VCC). When the UVLO pin is below its
threshold, the gate drives are disabled, but the part draws
its normal quiescent current from VCC. The VCC undervoltage lockout supersedes this function so VCC must be great
enough to start the part. The bias current on this pin has
hysteresis such that the bias current is sourced when UVLO
threshold is exceeded. This introduces a hysteresis at the
pin equivalent to the bias current change times the imped42681fc
10
LTC4268-1
Pin Functions
ance of the upper divider resistor. The user can control
the amount of hysteresis by adjusting the impedance of
the divider. Tie the UVLO pin to VCC if you are not using
this function. See the Applications Information for details.
This pin is used for the UVLO function of the switching
regulator. The PD interface section has an UVLO defined
by the IEEE 802.3af specification.
SENSE–, SENSE+ (Pins 19, 20): Current Sense Inputs.
These pins are used to measure primary side switch current through an external sense resistor. Peak primary side
current is used in the converter control loop. Make Kelvin
connections to the sense resistor RSENSE to reduce noise
problems. SENSE– connects to the GND side. At maximum
current (VCMP at its maximum voltage) SENSE pins have
100mV threshold. The signal is blanked (ignored) during
the minimum turn-on time.
CCMP (Pin 21): Load Compensation Capacitive Control.
Connect a capacitor from CCMP to GND in order to reduce
the effects of parasitic resistances in the feedback sensing
path. A 0.1µF ceramic capacitor suffices for most applications. Short this pin to GND in less demanding applications.
RCMP (Pin 22): Load Compensation Resistive Control.
Connect a resistor from RCMP to GND in order to compensate for parasitic resistances in the feedback sensing
path. In less demanding applications, this resistor is not
needed and this pin can be left open. See Applications
Information for details.
PGDLY (Pin 23): Primary Gate Delay Control. Connect an
external programming resistor (RPGDLY) to set delay from
synchronous gate turn-off to primary gate turn-on. See
Applications Information for details.
NC (Pin 25): No Internal Connection.
VNEG (Pins 26, 27, 28): System Negative Rail. Tie to the
GND pin to supply power to the flyback controller through
the internal power MOSFET. VNEG is high impedance until
the input voltage rises above the UVLO turn-on threshold.
The output is then connected to VPORTN through a currentlimited internal MOSFET switch. Pins 26, 27 and 28 must
be electrically tied together.
PWRGD (Pin 29): Active High Power Good Output,
Open-Collector. Signals to the flyback controller that the
LTC4268-1 MOSFET is on and that the flyback controller
can start operation. High impedance indicates power is
good. PWRGD is referenced to VNEG and is low impedance during inrush and in the event of a thermal overload.
PWRGD is clamped to 14V above VNEG.
PWRGD (Pin 30): Active Low Power Good Output, OpenDrain. Signals to the DC/DC converter that the LTC4268-1
MOSFET is on and that the converter can start operation.
Low impedance indicates power is good. PWRGD is referenced to VPORTN and is high impedance during detection, classification and in the event of a thermal overload.
PWRGD has no internal clamps.
NC (Pin 31): No Internal Connection.
VPORTP (Pin 32): Positive Power Input. Tie to the input
port power return through the input diode bridge.
GND (Pin 33): Ground. This is the negative rail connection for both signal ground and gate driver grounds. This
pin should be connected to VNEG. Careful attention must
be paid to layout. See the Applications Information for
details.
PG (Pin 24): Primary Gate Drive. PG is the gate drive pin
for the primary side MOSFET Switch. Large dynamic currents flow during voltage transitions. See the Applications
Information for details.
42681fc
11
LTC4268-1
Block Diagram
CLASSIFICATION
CURRENT LOAD
SHDN
1
VPORTP
+
1.237V
16k
2 NC
–
RCLASS
3
NC
PWRGD
ILIM_EN
4
1400mA
750mA
300mA
INPUT
CURRENT
LIMIT
+
PWRGD
14V
–
VPORTN
6
VNEG
VNEG
VPORTN
7
VNEG
BOLD LINE INDICATES
HIGH CURRENT PATH
VCC
CLAMPS
20V
0.7
+
–
1.237V
REFERENCE
(VFB)
FB
1.3
–
INTERNAL
REGULATOR
VCMP
+
3V
S
Q
R
Q
–
UVLO
+
–
CURRENT
COMPARATOR
IUVLO
28
27
26
10
16
17
COLLAPSE DETECT
+
UVLO
29
ERROR AMP
TSD
SFST
1V
14
OVERCURRENT
FAULT
–
VCC UVLO
–
–
18
30
+
+
15.3V
31
CONTROL
CIRCUITS
VPORTN
5
32
25k
SENSE–
19
CURRENT
SENSE AMP
–
+
+
CURRENT TRIP
SENSE+
SLOPE COMPENSATION
15
13
11
23
12
OSC
OSCILLATOR
RCMPF
50k
ENABLE
SET
+
SYNC
CCMP
ENDLY
21
–
LOAD
COMPENSATION
tON
PGDLY
20
LOGIC
BLOCK
RCMP
TO FB
PGATE
GATE DRIVE
22
VCC
PG
24
SGATE
+
–
3V
VCC
GATE DRIVE
SG
GND
9
33
42681 BD
42681fc
12
LTC4268-1
Applications Information
Overview
OPERATION
Power over Ethernet (PoE) continues to gain popularity
as an increasing number of products are taking advantage
of having DC power and high speed data available from a
single RJ45 connector. As PoE is becoming established in
the marketplace, Powered Device (PD) equipment vendors
are running into the 12.95W power limit established by the
IEEE 802.3af standard. To solve this problem and expand
the application of PoE, the LTC4268-1 breaks the power
barrier by allowing custom PoE applications to deliver up to
35W for power hungry PoE applications such as dual band
access points, RFID readers and PTZ security cameras.
Note: Please refer to the simplified application circuit
(Figure 1) for voltage naming conventions used in this
data sheet.
The LTC4268-1 is designed to be a complete solution for
PD applications with power requirements up to 35W. The
LTC4268-1 interfaces with custom Power Sourcing Equipment (PSE) using a high efficiency flyback topology for
maximum power delivery without the need for opto-isolator
feedback. Off-the-shelf high power PSEs are available today
from a variety of vendors for use with the LTC4268-1 to
allow quick implementation of a custom system.
RJ45
1
2
3
6
4
TX+
8
SERIES DIODES
The IEEE 802.3af-defined operating modes for a PD reference the input voltage at the RJ45 connector on the PD.
In this data sheet port voltage is normally referenced to
the pins of the LTC4268-1. Note that the voltage ranges
specified in the LTC4268-1 Electrical Specifications are
referenced with respect to the IC pins.
16 T1 1
15
2
TX–
14
3
RX+
11
6
10
7
9
8
RX–
SPARE+
~
SPARE–
+
+
VPORT
TO PHY
~
VIN
•
•
+
VOUT
–
VPORTP
VCC
~
+
5
7
The LTC4268-1 high power PD interface controller and
switching regulator has several modes of operation depending on the applied VPORT voltage as shown in Figure 2 and
summarized in Table 1. These various modes satisfy the
requirements defined in the IEEE 802.3af specification. The
input voltage is applied to the VPORTN pin with reference
to the VPORTP pin and is always negative.
PG
LTC4268-1
GND
~
PD FRONT END
–
VPORTN VNEG
SWITCHING REGULATOR
ISOLATED OUTPUT
42681 F01
Figure 1. Simplified Application Circuit With Voltage Naming Conventions
42681fc
13
LTC4268-1
Applications Information
DETECTION V1
–10
VPORTN (V)
TIME
DETECTION V2
CLASSIFICATION
–20
UVLO
TURN-ON
–30
–40
UVLO
TURN-OFF
–50
TIME
τ = RLOAD C1
–10
UVLO
OFF
VIN (V)
–20
UVLO
ON
UVLO
OFF
–30
–40
dV =ILIMIT_LOW
dt
C1
–50
The PD must be able to handle power received in either
polarity. For this reason, it is common to install diode
bridges between the RJ45 connector and the LTC4268-1
(Figure 3). The diode bridges introduce an offset that
affects the threshold points for each range of operation.
The LTC4268-1 meets the IEEE 802.3af-defined operating
modes by compensating for the diode drops in the threshold
points. For the signature, classification, and the UVLO
thresholds, the LTC4268-1 extends two diode drops below
the IEEE 802.3af specifications. The LTC4268-1 threshold
points support the use of either traditional or Schottky
diode bridges.
TIME
RJ45
1
PWRGD (V)
–10
POWER
BAD
–20
POWER
GOOD
POWER
BAD
2
–30
3
–40
PWRGD TRACKS
VIN
–50
PWRGD – VIN (V)
20
6
4
POWER
BAD
10
POWER
GOOD
POWER
BAD
7
8
ILIMIT_HIGH
LOAD, ILOAD
(UP TO ILIMIT_HIGH)
ILIMIT_LOW
ICLASS
CLASSIFICATION
DETECTION I1
I1 =
V1 – 2 DIODE DROPS
V2 – 2 DIODE DROPS
I2 =
25kΩ
25kΩ
ICLASS DEPENDENT ON RCLASS SELECTION
ILIMIT_LOW = 300mA, ILIMIT_HIGH = 750mA
ILOAD =
VIN
RLOAD
LTC4268-1
IIN
PSE VPORT R
CLASS
RCLASS VPORTP
PWRGD
PWRGD
VPORTN
VNEG
RLOAD
+
BR1
RX+
TO PHY
RX–
VPORTP
SPARE+
BR2
D3
0.1µF
100V
SPARE–
LTC4268-1
VPORTN
42681 F03
Figure 3. PD Front End Using Diode Bridges on
Main and Spare Inputs
DETECTION
TIME
DETECTION I2
T1
TX–
5
TIME
PD CURRENT
POWERED
DEVICE (PD)
INTERFACE
AS DEFINED
BY IEEE 802.3af
TX+
VIN
C1
During detection, the PSE will apply a voltage in the range
of –2.8V to –10V on the cable and look for a 25k signature
resistor. This identifies the device at the end of the cable
as a PD. With the PSE voltage in the detection range, the
LTC4268-1 presents an internal 25k resistor between the
VPORTP and VPORTN pins. This precision, temperaturecompensated resistor provides the proper characteristics
to alert the PSE that a PD is present and requests power
to be applied.
42681 F02
Figure 2. VIN Voltage, PWRGD, PWRGD and PD Current
as a Function of Port Voltage
42681fc
14
LTC4268-1
Applications Information
tie SHDN to VPORTP. Alternately, the SHDN pin can be
driven high with respect to VPORTN. When SHDN is high,
all functions are disabled. For normal operation tie SHDN
to VPORTN.
Table 1. LTC4268-1 Operational Mode as a Function
of VPORT Voltage
VPORT
MODE OF OPERATION
0V to –1.4V
Inactive
–1.5V to –10.1V
25k Signature Resistor Detection
–10.3V to –12.4V
Classification Load Current Ramps Up from 0%
to 100%
–12.5V to UVLO*
Classification Load Current Active
UVLO* to –57V
Power Applied to PD Load
*UVLO includes hysteresis.
Rising input threshold @ –38.9V
Falling input threshold @ –30.6V
The IEEE 802.3af specification requires the PSE to use
a DV/DI measurement technique to keep the DC offset
voltage of the diode bridge from affecting the signature
resistance measurement. However, the diode resistance
appears in series with the signature resistor and must
be included in the overall signature resistance of the PD.
The LTC4268-1 compensates for the two series diodes
in the signature path by offsetting the internal resistance
so that a PD built with the LTC4268-1 meets the IEEE
802.3af specification.
In some designs that include an auxiliary power option,
such as an external wall adapter, it is necessary to control whether or not the PD is detected by a PSE. With the
LTC4268-1, the 25k signature resistor can be enabled or
disabled with the SHDN pin (Figure 4). Taking the SHDN
pin high will reduce the signature resistor to 10k which is
an invalid signature per the IEEE 802.3af specifications.
This will prevent a PSE from detecting and powering the
PD. This invalid signature is present in the PSE probing
range of –2.8V to –10V. When the input rises above –10V,
the signature resistor reverts to 25k to minimize power
dissipation in the LTC4268-1. To disable the signature,
CLASSIFICATION
Once the PSE has detected a PD, the PSE may optionally
classify the PD. Classification provides a method for more
efficient allocation of power by allowing the PSE to identify
lower-power PDs and assign the appropriate power level
to these devices. For each class, there is an associated
load current that the PD asserts onto the line during classification probing. The PSE measures the PD load current
in order to assign the proper PD classification. Class 0 is
included in the IEEE 802.3af specification to cover PDs
that do not support classification. Class 1-3 partition PDs
into three distinct power ranges as shown in Table 2.
Table 2. Summary of IEEE 802.3af Power Classifications and
LTC4268-1 RCLASS Resistor Selection
USAGE
MAXIMUM
POWER LEVELS
AT INPUT OF PD
(W)
0
Default
0.44 to 13.0
UVLO*
ON
*UVLO INCLUDES HYSTERESIS
RISING INPUT THRESHOLD ≅ –38.9V
FALLING INPUT THRESHOLD ≅ –30.6V
CURRENT-LIMITED
TURN ON
Figure 7. LTC4268-1 Undervoltage Lockout
42681fc
17
LTC4268-1
Applications Information
During the inrush event as C1 is being charged, a large
amount of power is dissipated in the MOSFET. The
LTC4268-1 is designed to accept this load and is thermally
protected to avoid damage to the onboard power MOSFET.
If a thermal overload does occur, the power MOSFET turns
off, allowing the die to cool. Once the die has returned to
a safe temperature, the LTC4268-1 automatically switches
to ILIMIT_LOW, and load capacitor C1 charging resumes.
The LTC4268-1 has the option of disabling the normal
operating input current limit, ILIMIT_HIGH, for custom
high power PoE applications. To disable the current limit,
connect ILIM_EN to VPORTN. To protect the LTC4268-1
from damage when the normal current limit is disabled, a
safeguard current limit, ILIMIT_DISA keeps the current below
destructive levels, typically 1.4A. Note that continuous
operation at or near the safeguard current limit will rapidly
overheat the LTC4268-1, engaging the thermal protection
circuit. For normal operations, float the ILIM_EN pin. The
LTC4268-1 maintains the ILIMIT_LOW inrush current limit
for charging the load capacitor regardless of the state of
LTC4268-1
ILIM_EN. The operation of the ILIM_EN pin is summarized
in Table 3.
Table 3. Summary of IEEE 802.3af Power Classifications and
LTC4268-1 RCLASS Resistor Selection
STATE OF ILIM_EN
INRUSH CURRENT
LIMIT
OPERATING INPUT
CURRENT LIMIT
Floating
ILIMIT_LOW
ILIMT_HIGH
Tied to VPORTN
ILIMIT_LOW
ILIMIT_DISA
POWER GOOD
The LTC4268-1 includes complementary power good
outputs (Figure 8) to simplify connection to any DC/DC
converter. Power Good is asserted at the end of the inrush
event when load capacitor C1 is fully charged and the
DC/DC converter can safely begin operation. The power
good signal stays active during normal operation and is
de-asserted at power off when the port drops below the
UVLO threshold or in the case of a thermal overload event.
For PD designs that use a large load capacitor and also
30 PWRGD
UVLO
THERMAL SD
CONTROL
CIRCUIT
INRUSH COMPLETE
AND NOT IN THERMAL SHUTDOWN
29 PWRGD
REF
VPORTN 5
28 VNEG
VPORTN 6
27 VNEG
VPORTN 7
26 VNEG
BOLD LINE INDICATES HIGH CURRENT PATH
POWER
NOT
GOOD
POWER
GOOD
VPORT < UVLO OFF
OR THERMAL SHUTDOWN
42681 F08
Figure 8. LTC4268-1 Power Good Functional and State Diagram
42681fc
18
LTC4268-1
Applications Information
consume a lot of power, it is important to delay activation
of the DC/DC converter with the power good signal. If
the converter is not disabled during the current-limited
turn-on sequence, the DC/DC converter will rob current
intended for charging up the load capacitor and create a
slow rising input, possibly causing the LTC4268-1 to go
into thermal shutdown.
The active high PWRGD pin features an internal,
open‑collector output referenced to VNEG. During inrush,
the active high PWRGD pin becomes valid when C1 reaches
–4V and pulls low until the load capacitor is fully charged.
At that point, PWRGD becomes high impedance, indicating
the switching regulator may begin running. The active
high PWRGD pin interfaces directly to the UVLO pin of
the LTC4268-1 with the aid of an external pull-up resistor
to Vcc. The PWRGD pin includes an internal 14V clamp to
VNEG. During a power supply ramp down event, PWRGD
becomes low impedance when VPORT drops below the 30V
PD UVLO turn-off threshold, then goes high impedance
when the VPORT voltages fall to within the detection voltage
range. Figure 11 shows a typical connection scheme for
the active high PWRGD pin.
The LTC4268-1 also includes an active low PWRGD pin
for system level use. PWRGD is referenced to the VPORTN
pin and when active will be near the VPORTN potential. The
negative rail (GND) of the internal switching regulator will
typically be referenced to VNEG and care must be taken to
ensure that the difference in potential of the PWRGD pin
does not cause a problem for the switcher.
THERMAL PROTECTION
The LTC4268-1 includes thermal overload protection in
order to provide full device functionality in a miniature
package while maintaining safe operating temperatures.
At turn-on, before load capacitor C1 has charged up, the
instantaneous power dissipated by the LTC4268-1 can be
as high as 20W. As the load capacitor charges, the power
dissipation in the LTC4268-1 will decrease until it reaches
a steady-state value dependent on the DC load current.
The LTC4268-1 can also experience device heating after
turn-on if the PD experiences a fast input voltage rise. For
example, if the PD input voltage steps from –37V to –57V,
the instantaneous power dissipated by the LTC4268-1 can
be as high as 16W. The LTC4268-1 protects itself from
damage by monitoring die temperature. If the die exceeds
the overtemperature trip point, the power MOSFET and
classification transistors are disabled until the part cools
down. Once the die cools below the overtemperature trip
point, all functions are enabled automatically. During
classification, excessive heating of the LTC4268-1 can
occur if the PSE violates the 75ms probing time limit.
In addition, the IEEE 802.3af specification requires a PD
to withstand application of any voltage from 0V to 57V
indefinitely. To protect the LTC4268-1 in these situations,
the thermal protection circuitry disables the classification
circuit and the input current if the die temperature exceeds
the overtemperature trip point. When the die cools down,
classification and input current are enabled.
Once the LTC4268-1 has charged up the load capacitor and
the PD is powered and running, there will be some residual
heating due to the DC load current of the PD flowing through
the internal MOSFET. In some high current applications,
the LTC4268-1 power dissipation may be significant. The
LTC4268-1 uses a thermally enhanced DFN package that
includes an exposed pad which should be soldered to the
GND plane for heat sinking on the printed circuit board.
MAXIMUM AMBIENT TEMPERATURE
The LTC4268-1 ILIM_EN pin allows the PD designer to
disable the normal operating current limit. With the normal
current limit disabled, it is possible to pass currents
as high as 1.4A through the LTC4268-1. In this mode,
significant package heating may occur. Depending on
the current, voltage, ambient temperature, and waveform
characteristics, the LTC4268-1 may shut down. To avoid
nuisance trips of the thermal shutdown, it may be necessary
to limit the maximum ambient temperature. Limiting the
die temperature to 125°C will keep the LTC4268-1 from
hitting thermal shutdown. For DC loads the maximum
ambient temperature can be calculated as:
TMAX = 125 – qJA • PWR (°C)
where TMAX is the maximum ambient operating temperature, qJA is the junction-to-ambient thermal resistance
(49°C/W), and PWR is the power dissipation for the
LTC4268-1 in Watts (IPD2 • RON).
42681fc
19
LTC4268-1
Applications Information
EXTERNAL INTERFACE AND COMPONENT SELECTION
Table 4. Power over Ethernet Transformer Vendors
VPORT
Transformer
Nodes on an Ethernet network commonly interface to
the outside world via an isolation transformer (Figure
9). For powered devices, the isolation transformer must
include a center tap on the media (cable) side. Proper
termination is required around the transformer to provide correct impedance matching and to avoid radiated
and conducted emissions. For high power applications
beyond IEEE 802.3af limits, the increased current levels
increase the current imbalance in the magnetics. This
imbalance reduces the perceived inductance and can
interfere with data transmission. Transformers specifically designed for high current applications are required.
Transformer vendors such as Bel Fuse, Coilcraft, Halo,
Pulse, and Tyco (Table 4) can provide assistance with
selection of an appropriate isolation transformer and
proper termination methods. These vendors have transformers specifically designed for use in high power PD
applications.
RJ45
1
2
3
6
4
TX+
16 T1 1
15
2
TX–
14
3
RX+
11
6
10
7
9
8
RX–
5
7
8
Bel Fuse Inc.
206 Van Vorst Street
Jersey City, NJ 07302
Tel: 201-432-0463
www.belfuse.com
Coilcraft Inc.
1102 Silver Lake Road
Gary, IL 60013
Tel: 847-639-6400
www.coilcraft.com
Halo Electronics
1861 Landings Drive
Mountain View, CA 94043
Tel: 650-903-3800
www.haloelectronics.com
Pulse Engineering
12220 World Trade Drive
San Diego, CA 92128
Tel: 858-674-8100
www.pulseeng.com
Tyco Electronics
308 Constitution Drive
Menlo Park, CA 94025-1164
Tel: 800-227-7040
www.circuitprotection.com
IEEE 802.3af allows power wiring in either of two configurations on the TX/RX wires, and power can be applied to
the PD via the spare wire pair in the RJ45 connector. The
BR1
HD01
TO PHY
PULSE H2019
SPARE+
SPARE–
MODE OF OPERATION
10Ω
BR2
HD01
D3
SMAJ58A
TVS
8
C14
0.1µF
100V
4
C1
VPORTP
LTC4268-1
VPORTN VNEG
5
VOUT
42681 F09
Figure 9. PD Front-End Isolation Transformer, Diode Bridges, Capacitors and TVS
42681fc
20
LTC4268-1
Applications Information
PD is required to accept power in either polarity on both
the data and spare inputs; therefore it is common to install
diode bridges on both inputs in order to accommodate the
different wiring configurations. Figure 9 demonstrates an
implementation of the diode bridges to minimize heating.
The IEEE 802.3af specification also mandates that the
leakage back through the unused bridge be less than 28µA
when the PD is powered with 57V.
The LTC4268-1 has several different modes of operation
based on the voltage present between the VPORTN and
VPORTP pins. The forward voltage drop of the input diodes
in a PD design subtracts from the input voltage and will
affect the transition point between modes.
The input diode bridge of a PD can consume over 4% of
the available power in some applications. Schottky diodes
can be used in order to reduce power loss. The LTC4268‑1
is designed to work with both standard and Schottky
diode bridges while maintaining proper threshold points
for IEEE 802.3af compliance.
Input Capacitor
The IEEE 802.3af/at standard includes an impedance
requirement in order to implement the AC disconnect
function. A 0.1µF capacitor (C14 in Figure 9) is used to
meet the AC impedance requirement.
Input Series Resistance
Linear Technology has seen the customer community cable
discharge requirements increase by nearly 500,000 times
the original test levels. The PD must survive and operate
reliably not only when an initially charged cable connects
and dissipates the energy through the PD front end, but
also when the electrical power system grounds are subject
to very high energy events (e.g., lightning strikes).
In these high energy events, adding 10Ω series resistance
into the VPORTP pin greatly improves the robustness of
the LTC4268-1 based PD (see Figure 9). The TVS limits
the voltage across the port while the 10Ω and 0.1µF capacitance reduces the edge rate the LT4268-1 encounters
across its pin. The added 10Ω series resistance does not
operationally affect the LTC4268-1 PD Interface, nor does
it affect its compliance with the IEEE 802.3 standard.
Transient Voltage Suppressor
The LTC4268-1 specifies and absolute maximum voltage of 100V and is designed to tolerate brief overvoltage
events. However, the pins that interface to the outside
world can routinely see excessive peak voltages. To protect the LTC4268-1, install a transient voltage suppressor
(D3) between the input diode bridge and the LTC4268-1,
as shown in Figure 9. An SMAJ58A is recommended for
typical PD applications. However, an SMBJ58A may be
preferred in applications where the PD front end must
absorb higher energy discharge events.
Auxiliary Power Source
In some applications, it may be necessary to power the
PD from an auxiliary power source such as a wall adapter.
The auxiliary power can be injected into the PD at several
locations and various trade-offs exist. Figure 10 demonstrates four methods of connecting external power to a PD.
Option 1 in Figure 10 inserts power before the LTC4268-1
interface controller. In this configuration, it is necessary
for the wall adapter to exceed the LTC4268-1 UVLO turnon requirement. This option provides input current limit
for the adapter, provides a valid power good signal and
simplifies power priority issues. As long as the adapter
applies power to the PD before the PSE, it will take priority
and the PSE will not power up the PD because the external
power source will corrupt the 25k signature. If the PSE
is already powering the PD, the adapter power will be in
parallel with the PSE. In this case, priority will be given to
the higher supply voltage. If the adapter voltage is higher,
the PSE may remove the port voltage since no current will
be drawn from the PSE. On the other hand, if the adapter
voltage is lower, the PSE will continue to supply power to
the PD and the adapter will not be used. Proper operation
will occur in either scenario.
Option 2 applies power directly to the DC/DC converter.
In this configuration the adapter voltage does not need
to exceed the LTC4268-1 turn-on UVLO requirement and
can be selected based solely on the PD load requirements.
It is necessary to include diode D9 to prevent the adapter
from applying power to the LTC4268-1. Power priority
issues require more intervention. If the adapter voltage
is below the PSE voltage, then the priority will be given
42681fc
21
LTC4268-1
Applications Information
OPTION 1: AUXILIARY POWER INSERTED BEFORE LTC4268-1
RJ45
1
2
3
6
TX+
T1
~
TX–
RX+
TO PHY
BR1
~
RX–
D3
SMAJ58A
TVS
+
+
C14
0.1µF
100V
C1
–
VIN
VPORTP
SPARE+
4
~
5
+
• 42V ≤ VWW ≤ 57V
• NO POWER PRIORITY ISSUES
• LTC4268-1 CURRENT LIMITS FOR BOTH PoE AND VWW
LTC4268-1
BR2
7
SPARE–
8
~
+
–
VPORTN VNEG
D8
S1B
ISOLATED
WALL
VWW
TRANSFORMER
–
OPTION 2: AUXILIARY POWER INSERTED AFTER LTC4268-1 WITH SIGNATURE DISABLED
RJ45
1
2
3
6
TX+
T1
~
TX–
RX+
TO PHY
+
BR1
~
RX–
D3
SMAJ58A
TVS
+
C14
0.1µF
100V
–
VIN
VPORTP
4.7k
SPARE+
4
~
5
+
SPARE–
8
~
+
BSS63
100k
BR2
7
C1
LTC4268-1
D9
S1B
SHDN
–
VPORTN VNEG
• VWW ANY VOLTAGE BASED ON PD LOAD
• REQUIRES EXTRA DIODE
• SEE APPS REGARDING POWER PRIORITY
D10
S1B
ISOLATED
VWW
WALL
TRANSFORMER
–
OPTION 3: AUXILIARY POWER APPLIED TO LTC4268-1 AND PD LOAD
RJ45
1
2
3
6
TX
+
T1
~
TX–
RX+
TO PHY
+
BR1
~
RX–
D3
SMAJ58A
TVS
+
C14
0.1µF
100V
C1
–
VIN
VPORTP
SPARE+
4
~
5
+
LTC4268-1
–
VPORTN VNEG
• 42V ≤ VWW ≤ 57V
• NO POWER PRIORITY ISSUES
• NO LTC4268-1 CURRENT LIMITS FOR VWW
BR2
7
SPARE–
8
~
+
D10
S1B
ISOLATED
WALL
VWW
TRANSFORMER
–
OPTION 4: AUXILIARY POWER APPLIED TO ISOLATED LOAD
RJ45
1
2
3
6
4
TX+
T1
~
TX–
RX+
TO PHY
BR1
~
RX–
8
D3
SMAJ58A
TVS
C14
0.1µF
100V
+
C1
ISOLATED DC/DC CONVERTER
–
DRIVE
LOAD
VPORTP
SPARE+
~
5
7
+
+
BR2
SPARE–
+
~
PG
LTC4268-1
SHDN
–
GND
• VWW ANY VOLTAGE BASED ON PD LOAD
• SEE APPS REGARDING POWER PRIORITY
• BEST ISOLATION
VPORTN VNEG
ISOLATED
VWW
WALL
TRANSFORMER
–
Figure 10. Interfacing Auxiliary Power Source to the PD
42681fc
22
LTC4268-1
Applications Information
to the PSE power. The PD will draw power from the PSE
while the adapter will remain unused. This configuration is
acceptable in a typical PoE system. However, if the adapter
voltage is higher than the PSE voltage, the PD will draw
power from the adapter. In this situation, it is necessary to
address the issue of power cycling that may occur if a PSE
is present. The PSE will detect the PD and apply power. If
the PD is being powered by the adapter, then the PD will
not meet the minimum load requirement and the PSE may
subsequently remove power. The PSE will again detect the
PD and power cycling will start. With an adapter voltage
above the PSE voltage, it is necessary to either disable the
signature as shown in option 2, or install a minimum load
on the output of the LTC4268-1 to prevent power cycling.
A 3k, 1W resistor connected between VPORTP and VNEG
will present the required minimum load.
Option 3 applies power directly to the DC/DC converter
bypassing the LTC4268-1 and omitting diode D9. With
the diode omitted, the adapter voltage is applied to the
LTC4268-1 in addition to the DC/DC converter. For this
reason, it is necessary to ensure that the adapter maintain
the voltage between 42V and 57V to keep the LTC4268-1
in its normal operating range. The third option has the
advantage of corrupting the 25k signature resistance when
the external voltage exceeds the PSE voltage and thereby
solving the power priority issue.
Option 4 bypasses the entire PD interface and injects
power at the output of the low voltage power supply. If
the adapter output is below the low voltage output there
are no power priority issues. However, if the adapter is
above the internal supply, then option 4 suffers from the
same power priority issues as option 2 and the signature
should be disabled or a minimum load should be installed.
Shown in option 4 is one method to disable to the signature
while maintaining isolation.
If employing options 1 through 3, it is necessary to ensure
that the end-user cannot access the terminals of the auxiliary power jack on the PD since this would compromise
IEEE 802.3af isolation requirements and may violate local
safety codes. Using option 4 along with an isolated power
supply addresses the isolation issue and it is no longer
necessary to protect the end-user from the power jack.
The above power cycling scenarios have assumed the
PSE is using DC disconnect methods. For a PSE using
AC disconnect, a PD with less than minimum load will
continue to be powered.
Wall adapters have been known to generate voltage spikes
outside their expected operating range. Care should be
taken to ensure no damage occurs to the LTC4268-1
or any support circuitry from extraneous spikes at the
auxiliary power interface.
Classification Resistor Selection (RCLASS)
The IEEE 802.3af specification allows classifying PDs into
four distinct classes with class 4 being reserved for future
use (Table 2). The LTC4268-1 supports all IEEE classes
and implements an additional Class 5 for use in custom
PoE applications. An external resistor connected from
RCLASS to VPORTN (Figure 6) sets the value of the load
current. The designer should determine which class the
PD is to advertise and then select the appropriate value of
RCLASS from Table 2. If a unique load current is required,
the value of RCLASS can be calculated as:
RCLASS = 1.237V/(ILOAD – IIN_CLASS)
IIN_CLASS is the LTC4268-1 IC supply current during
classification given in the electrical specifications. The
RCLASS resistor must be 1% or better to avoid degrading
the overall accuracy of the classification circuit. Resistor power dissipation will be 100mW maximum and is
transient so heating is typically not a concern. In order
to maintain loop stability, the layout should minimize
capacitance at the RCLASS node. The classification circuit
can be disabled by floating the RCLASS pin. The RCLASS pin
should not be shorted to VPORTN as this would force the
LTC4268-1 classification circuit to attempt to source very
large currents. In this case, the LTC4268-1 will quickly go
into thermal shutdown.
42681fc
23
LTC4268-1
Applications Information
Power Good Interface
The LTC4268-1 provides complimentary power good
signals to simplify the DC/DC converter interface. Using
the power good signal to delay converter operation until
the load capacitor is fully charged is recommended as this
will help ensure trouble free start-up.
The active high PWRGD pin is controlled by an open collector transistor referenced to VNEG while the active low
PWRGD pin is controlled by a high voltage, open-drain
MOSFET referenced to VPORTN. The PWRGD pin is designed to interface directly to the UVLO pin with the aid
of a pull-up resistor to Vcc. An example interface circuit
is shown in Figure 11.
ACTIVE-HIGH ENABLE
VPORTP
4k
LTC4268-1
100k
PWRGD
–54V
VPORTN
Shutdown Interface
To disable the 25k signature resistor, connect SHDN to
the VPORTP pin. Alternately, the SHDN pin can be driven
high with respect to VPORTN. Examples of interface circuits
that disable the signature and all LTC4268-1 functions are
shown in Figure 10, options 2 and 4. Note that the SHDN
input resistance is relatively large and the threshold voltage is fairly low. Because of high voltages present on the
printed circuit board, leakage currents from the VPORTP pin
could inadvertently pull SHDN high. To ensure trouble-free
operation, use high voltage layout techniques in the vicinity
of SHDN. If unused, connect SHDN directly to VPORTN.
Load Capacitor
VCC
TO
PSE
the pin voltage and thus creating hysteresis. As the pin
voltage drops below this threshold, the current is disabled,
further dropping the UVLO pin voltage. If not used, the
UVLO pin can be disabled by tying to VCC.
UVLO
42681 F11
Figure 11. Power Good Interface Example
Port Voltage Lockout
PoE applications require the PD interface to turn on below
42V and turn off above 30V. The LTC4268-1 includes an
internal port voltage lockout circuit to implement this basic
chip on/off control. Additionally, the LTC4268-1 includes
an enable/lockout function for the DC/DC converter that
is controlled by the UVLO pin and is intended to be driven
by PWRGD to ensure proper start-up. (Refer to Power
Good Interface.) Users have the ability to implement
higher turn-on voltages if necessary by connecting the
UVLO pin to an external resistive divider between VPORTP
and VPORTN. The UVLO pin also includes a bias current
allowing implementation of hysteresis. When UVLO is
below 1.24V, gate drivers are disabled and the converter
sits idle. When the pin rises above the lockout threshold
a small current is sourced out of the UVLO pin, increasing
The IEEE 802.3af specification requires that the PD maintain
a minimum load capacitance of 5µF. It is permissible to
have a much larger load capacitor and the LTC4268-1 can
charge very large load capacitors before thermal issues
become a problem. However, the load capacitor must not
be too large or the PD design may violate IEEE 802.3af
requirements. If the load capacitor is too large, there can
be a problem with inadvertent power shutdown by the PSE.
For example, if the PSE is running at –57V (IEEE 802.3af
maximum allowed) and the PD is detected and powered
up, the load capacitor will be charged to nearly –57V. If
for some reason the PSE voltage is suddenly reduced to
–44V (IEEE 802.3af minimum allowed), the input bridge
will reverse bias and the PD power will be supplied by the
load capacitor. Depending on the size of the load capacitor
and the DC load of the PD, the PD will not draw any power
from the PSE for a period of time. If this period of time
exceeds the IEEE 802.3af 300ms disconnect delay, the
PSE will remove power from the PD. For this reason, it
is necessary to evaluate the load current and capacitance
to ensure that inadvertent shutdown cannot occur. Refer
also to Thermal Protection in this data sheet for further
discussion on load capacitor selection.
42681fc
24
LTC4268-1
Applications Information
MAINTAIN POWER SIGNATURE
In an IEEE 802.3af system, the PSE uses the maintain
power signature (MPS) to determine if a PD continues to
require power. The MPS requires the PD to periodically
draw at least 10mA and also have an AC impedance less
than 26.25k in parallel with 0.05µF. If either the DC current
is less than 10mA or the AC impedance is above 26.25k,
the PSE may disconnect power. The DC current must be
less than 5mA and the AC impedance must be above 2M
to guarantee power will be removed. The PD application
circuits shown in this data sheet present the required AC
impedance necessary to maintain power.
IEEE 802.3at Interoperability
In anticipation of the IEEE 802.3at standard release, the
LTC4268-1 can be combined with a simple external circuit
to be fully interoperable with an IEEE 802.3at-compliant
PSE. For more information, please contact Linear Technology’s Application Engineering.
SWITCHING REGULATOR OVERVIEW
The LTC4268-1 includes a current mode converter designed
specifically for use in an isolated flyback topology employing
synchronous rectification. The LTC4268-1 operation is
similar to traditional current mode switchers. The major
difference is that output voltage feedback is derived via
sensing the output voltage through the transformer. This
precludes the need of an opto-isolator in isolated designs
greatly improving dynamic response and reliability. The
LTC4268-1 has a unique feedback amplifier that samples a
transformer winding voltage during the flyback period and
uses that voltage to control output voltage. The internal
blocks are similar to many current mode controllers.
The differences lie in the feedback amplifier and load
compensation circuitry. The logic block also contains
circuitry to control the special dynamic requirements of
flyback control. For more information on the basics of
current mode switcher/controllers and isolated flyback
converters see Application Note 19.
Feedback Amplifier—Pseudo DC Theory
For the following discussion refer to the simplified Flyback
Amplifier diagram(Figure 12). When the primary side
MOSFET switch MP turns off, its drain voltage rises above
the VPORTP rail. Flyback occurs when the primary MOSFET
is off and the synchronous secondary MOSFET is on.
During flyback the voltage on nondriven transformer pins
is determined by the secondary voltage. The amplitude of
this flyback pulse as seen on the third winding is given as:
VFLBK =
(
VOUT + ISEC • ESR + R DS(ON)
N SF
RDS(ON) = on resistance of the synchronous MOSFET MS
ISEC = transformer secondary current
ESR = impedance of secondary circuit capacitor, winding
and traces
NSF = transformer effective secondary-to-flyback winding
turns ratio (i.e., NS/NFLBK)
T1
VFLBK
FLYBACK
LTC4268-1 FEEDBACK AMP
R1
FB
1V
R2
+
16
–
VFB
1.237V
•
VCMP
+
)
17
CVC
VIN
PRIMARY
•
SECONDARY
•
+
COUT
ISOLATED
OUTPUT
MP
COLLAPSE
DETECT
MS
R
ENABLE
S
Q
42681 F12
Figure 12. LTC4268-1 Switching Regulator Feedback Amplifier
42681fc
25
–
LTC4268-1
Applications Information
The flyback voltage is scaled by an external resistive
divider R1/R2 and presented at the FB pin. The feedback
amplifier compares the voltage to the internal bandgap
reference. The feedback amp is actually a transconductance
amplifier whose output is connected to VCMP only during
a period in the flyback time. An external capacitor on
the VCMP pin integrates the net feedback amp current to
provide the control voltage to set the current mode trip
point. The regulation voltage at the FB pin is nearly equal
to the bandgap reference VFB because of the high gain in
the overall loop. The relationship between VFLBK and VFB
is expressed as:
VFLBK =
R1+ R2
• VFB
R2
Combining this with the previous VFLBK expression yields
an expression for VOUT in terms of the internal reference,
programming resistors and secondary resistances:
(
R1+ R2
VOUT =
• VFB • NSF −ISEC • ESR + RDS(ON)
R2
)
The effect of nonzero secondary output impedance is
discussed in further detail; see Load Compensation Theory.
The practical aspects of applying this equation for VOUT
are found in the Applications Information.
PRIMARY SIDE
MOSFET DRAIN
VOLTAGE
Feedback Amplifier Dynamic Theory
So far, this has been a pseudo-DC treatment of flyback
feedback amplifier operation. But the flyback signal is a
pulse, not a DC level. Provision is made to turn on the
flyback amplifier only when the flyback pulse is present
using the enable signal as shown in the timing diagram
(Figure 13).
Minimum Output Switch On Time (tON(MIN))
The LTC4268-1 affects output voltage regulation via
flyback pulse action. If the output switch is not turned on,
there is no flyback pulse and output voltage information
is not available. This causes irregular loop response and
start-up/latch-up problems. The solution is to require
the primary switch to be on for an absolute minimum
time per each oscillator cycle. To accomplish this the
current limit feedback is blanked each cycle for tON(MIN).
If the output load is less than that developed under these
conditions, forced continuous operation normally occurs.
See Applications Information for further details.
Enable Delay Time (ENDLY)
The flyback pulse appears when the primary side switch
shuts off. However, it takes a finite time until the transformer
primary side voltage waveform represents the output
voltage. This is partly due to rise time on the primary
VFLBK
0.8 • VFLBK
VIN
PG VOLTAGE
SG VOLTAGE
tON(MIN)
ENABLE
DELAY
MIN ENABLE
PG DELAY
42681 F13
FEEDBACK
AMPLIFIER
ENABLED
Figure 13. LTC4268-1 Switching Regulator Timing Diagram
42681fc
26
LTC4268-1
Applications Information
side MOSFET drain node but, more importantly, is due
to transformer leakage inductance. The latter causes a
voltage spike on the primary side, not directly related to
output voltage. Some time is also required for internal
settling of the feedback amplifier circuitry. In order to
maintain immunity to these phenomena, a fixed delay is
introduced between the switch turn-off command and the
enabling of the feedback amplifier. This is termed “enable
delay.” In certain cases where the leakage spike is not
sufficiently settled by the end of the enable delay period,
regulation error may result. See Applications Information
for further details.
through the synchronous MOSFET RDS(ON) and real life
nonzero impedances of the transformer secondary and
output capacitor. This was represented previously by
the expression “ISEC • (ESR + RDS(ON)).” However, it is
generally more useful to convert this expression to effective
output impedance. Because the secondary current only
flows during the off portion of the duty cycle (DC), the
effective output impedance equals the lumped secondary
impedance divided by off time DC.
Collapse Detect
Once the feedback amplifier is enabled, some mechanism
is then required to disable it. This is accomplished by a
collapse detect comparator, which compares the flyback
voltage (FB) to a fixed reference, nominally 80% of VFB.
When the flyback waveform drops below this level, the
feedback amplifier is disabled.
where:
Minimum Enable Time
The feedback amplifier, once enabled, stays on for a fixed
minimum time period termed “minimum enable time.”
This prevents lockup, especially when the output voltage
is abnormally low; e.g., during start-up. The minimum
enable time period ensures that the VCMP node is able to
“pump up” and increase the current mode trip point to
the level where the collapse detect system exhibits proper
operation. This time is set internally.
Effects of Variable Enable Period
The feedback amplifier is enabled during only a portion of
the cycle time. This can vary from the fixed minimum enable
time described to a maximum of roughly the “off” switch
time minus the enable delay time. Certain parameters of
feedback amp behavior are directly affected by the variable
enable period. These include effective transconductance
and VCMP node slew rate.
Load Compensation Theory
The LTC4268-1 uses the flyback pulse to obtain
information about the isolated output voltage. An error
source is caused by transformer secondary current flow
Since the off time duty cycle is equal to 1 – DC then:
RS(OUT) =
ESR + RDS(ON)
1− DC
RS(OUT) = effective supply output impedance
DC = duty cycle
RDS(ON) and ESR are as defined previously
This impedance error may be judged acceptable in less
critical applications, or if the output load current remains
relatively constant. In these cases the external FB resistive
divider is adjusted to compensate for nominal expected
error. In more demanding applications, output impedance
error is minimized by the use of the load compensation
function. Figure 14 shows the block diagram of the load
compensation function. Switch current is converted to
a voltage by the external sense resistor, averaged and
VFLBK
R1
•
FB
Q1 Q2
16
R2
T1
VFB
VPORTP
•
LOAD
COMP I
•
+
Q3
A1
–
22 RCMP
MP
RCMPF
+
50k SENSE
20
21 CCMP
RSENSE
42681 F13
Figure 14. Load Compensation Diagram
42681fc
27
LTC4268-1
Applications Information
lowpass filtered by the internal 50k resistor RCMPF and
the external capacitor on CCMP. This voltage is impressed
across the external RCMP resistor by op amp A1 and
transistor Q3 producing a current at the collector of Q3 that
is subtracted from the FB node. This effectively increases
the voltage required at the top of the R1/R2 feedback
divider to achieve equilibrium.
The average primary side switch current increases to
maintain output voltage regulation as output loading
increases. The increase in average current increases RCMP
resistor current which affects a corresponding increase
in sensed output voltage, compensating for the IR drops.
Assuming relatively fixed power supply efficiency, Eff,
power balance gives:
POUT = Eff • PIN
VOUT • IOUT = Eff • VIN • IIN
Average primary side current is expressed in terms of
output current as follow:
IIN = K1•IOUT
where:
K1=
K1•
ESR + RDS(ON)
RSENSE
• R1• NSF =
RCMP
1− DC
Solving for RCMP gives:
RCMP = K1•
RSENSE • (1− DC)
• R1• NSF
ESR + RDS(ON)
The practical aspects of applying this equation to determine
an appropriate value for the RCMP resistor are found in the
Applications Information.
Transformer Design
Transformer design/specification is the most critical part of
a successful application of the LTC4268-1. The following
sections provide basic information about designing the
transformer and potential trade-offs. If you need help, the
LTC Applications group is available to assist in the choice
and/or design of the transformer.
Turns Ratios
VOUT
VIN • Eff
So the effective change in VOUT target is:
DVOUT = K1•
Nominal output impedance cancellation is obtained by
equating this expression with RS(OUT):
RSENSE
• R1• NSF
RCMP
thus:
DVOUT
R
= K1• SENSE • R1• NSF
DIOUT
RCMP
where:
K1 = dimensionless variable related to VIN,
VOUT and efficiency as explained above
RSENSE = external sense resistor
The design of the transformer starts with determining
duty cycle (DC). DC impacts the current and voltage stress
on the power switches, input and output capacitor RMS
currents and transformer utilization (size vs power). The
ideal turns ratio is:
NDEAL =
VOUT 1− DC
•
VIN
DC
Avoid extreme duty cycles as they, in general, increase
current stresses. A reasonable target for duty cycle is 50%
at nominal input voltage.
For instance, if we wanted a 48V to 5V converter at 50%
DC then:
NDEAL =
5 1− 0.5 1
•
=
48 0.5
9.6
42681fc
28
LTC4268-1
Applications Information
In general, better performance is obtained with a lower
turns ratio. A DC of 45.5% yields a 1:8 ratio. Note the
use of the external feedback resistive divider ratio to set
output voltage provides the user additional freedom in
selecting a suitable transformer turns ratio. Turns ratios
that are the simple ratios of small integers; e.g., 1:1, 2:1,
3:2 help facilitate transformer construction and improve
performance. When building a supply with multiple
outputs derived through a multiple winding transformer,
lower duty cycle can improve cross regulation by keeping
the synchronous rectifier on longer, and thus, keep
secondary windings coupled longer. For a multiple output
transformer, the turns ratio between output windings is
critical and affects the accuracy of the voltages. The ratio
between two output voltages is set with the formula VOUT2
= VOUT1 • N21 where N21 is the turns ratio between the
two windings. Also keep the secondary MOSFET RDS(ON)
small to improve cross regulation. The feedback winding
usually provides both the feedback voltage and power for
the LTC4268-1. Set the turns ratio between the output and
feedback winding to provide a rectified voltage that under
worst-case conditions is greater than the 11V maximum
VCC turn-off voltage.
NSF >
VOUT
11+ VF
where:
VF = Diode Forward Voltage
5
1
=
For our example: NSF >
11+ 0.7 2.34
1
We will choose
3
Leakage Inductance
Transformer leakage inductance (on either the primary or
secondary) causes a spike after the primary side switch
turn-off. This is increasingly prominent at higher load
currents, where more stored energy is dissipated. Higher
flyback voltage may break down the MOSFET switch if it
has too low a BVDSS rating. One solution to reducing this
spike is to use a snubber circuit to suppress the voltage
excursion. However, suppressing the voltage extends the
flyback pulse width. If the flyback pulse extends beyond
the enable delay time, output voltage regulation is affected.
The feedback system has a deliberately limited input range,
roughly ±50mV referred to the FB node. This rejects higher
voltage leakage spikes because once a leakage spike is
several volts in amplitude; a further increase in amplitude
has little effect on the feedback system. Therefore, it is
advisable to arrange the snubber circuit to clamp at as
high a voltage as possible, observing MOSFET breakdown,
such that leakage spike duration is as short as possible.
Application Note 19 provides a good reference on snubber
design.
As a rough guide, leakage inductance of several percent
(of mutual inductance) or less may require a snubber, but
exhibit little to no regulation error due to leakage spike
behavior. Inductances from several percent up to perhaps
ten percent cause increasing regulation error.
Avoid double digit percentage leakage inductances. There
is a potential for abrupt loss of control at high load current.
This curious condition potentially occurs when the leakage
spike becomes such a large portion of the flyback waveform
that the processing circuitry is fooled into thinking that
the leakage spike itself is the real flyback signal! It then
reverts to a potentially stable state whereby the top of the
leakage spike is the control point, and the trailing edge of
the leakage spike triggers the collapse detect circuitry. This
typically reduces the output voltage abruptly to a fraction,
roughly one-third to two-thirds of its correct value. Once
load current is reduced sufficiently, the system snaps
back to normal operation. When using transformers with
considerable leakage inductance, exercise this worst-case
check for potential bistability:
1. Operate the prototype supply at maximum expected
load current.
2. Temporarily short-circuit the output.
3. Observe that normal operation is restored.
If the output voltage is found to hang up at an abnormally
low value, the system has a problem. This is usually evident
by simultaneously viewing the primary side MOSFET drain
voltage to observe firsthand the leakage spike behavior.
A final note—the susceptibility of the system to bistable
behavior is somewhat a function of the load current/
voltage characteristics. A load with resistive—i.e., I = V/R
42681fc
29
LTC4268-1
Applications Information
behavior—is the most apt to be bistable. Capacitive loads
that exhibit I = V2/R behavior are less susceptible.
Secondary Leakage Inductance
As a general rule, keep X in the range of 20% to 40%
(i.e., X = 0.2 to 0.4). Higher values of ripple will increase
conduction losses, while lower values will require larger
cores.
Leakage inductance on the secondary forms an inductive
divider on the transformer secondary, reducing the size
of the flyback pulse. This increases the output voltage
target by a similar percentage. Note that unlike leakage
spike behavior; this phenomenon is independent of load.
Since the secondary leakage inductance is a constant
percentage of mutual inductance (within manufacturing
variations), the solution is to adjust the feedback resistive
divider ratio to compensate.
Ripple current and percentage ripple is largest at minimum
duty cycle; in other words, at the highest input voltage.
LP is calculated from:
Winding Resistance Effects
DCMIN is the DC at maximum input voltage
Primary or secondary winding resistance acts to reduce
overall efficiency (POUT/PIN). Secondary winding resistance
increases effective output impedance, degrading load
regulation. Load compensation can mitigate this to some
extent but a good design keeps parasitic resistances low.
Bifilar Winding
A bifilar or similar winding is a good way to minimize
troublesome leakage inductances. Bifilar windings also
improve coupling coefficients and thus improve cross
regulation in multiple winding transformers. However,
tight coupling usually increases primary-to-secondary
capacitance and limits the primary-to-secondary
breakdown voltage, so it isn’t always practical.
Primary Inductance
The transformer primary inductance, LP, is selected
based on the peak-to-peak ripple current ratio (X) in the
transformer relative to its maximum value.
LP
(V
=
IN(MAX) • DCMIN
) = (V
2
fOSC • XMAX • PIN
IN(MAX) • DCMIN
)
2
• Eff
fOSC • XMAX • POUT
where:
fOSC is the oscillator frequency
XMAX is ripple current ratio at maximum input voltage
Using common high power PoE values a 48V (41V < VIN
< 57V) to 5V/5.3A Converter with 90% efficiency, POUT=
26.5W and PIN = 29.5W Using X = 0.4 N = 1/8 and fOSC
= 200kHz:
DCMIN =
LP =
1+
1
=
N • VIN(MAX)
VOUT
(57V • 0.412)2
200kHz • 0.4 • 26.5W
1
= 41.2%
1 57
1+ •
8 5
= 260µH
Optimization might show that a more efficient solution
is obtained at higher peak current but lower inductance
and the associated winding series resistance. A simple
spreadsheet program is useful for looking at trade-offs.
42681fc
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LTC4268-1
Applications Information
Transformer Core Selection
Once LP is known, the type of transformer is selected.
High efficiency converters use ferrite cores to minimize
core loss. Actual core loss is independent of core size for
a fixed inductance, but decreases as inductance increases.
Since increased inductance is accomplished through more
turns of wire, copper losses increase. Thus transformer
design balances core and copper losses. Remember that
increased winding resistance will degrade cross regulation
and increase the amount of load compensation required.
The main design goals for core selection are reducing
copper losses and preventing saturation. Ferrite core
material saturates hard, rapidly reducing inductance
when the peak design current is exceeded. This results
in an abrupt increase in inductor ripple current and,
consequently, output voltage ripple. Do not allow the core
to saturate! The maximum peak primary current occurs
at minimum VIN:
PIN
X
IPK =
• 1+ MIN
VIN(MIN) • DCMAX
2
1+
XMIN
(V
=
1
=
N • VIN(MIN )
VOUT
IN(MIN) • DCMAX
fOSC • LP • PIN
)
1
= 49.4%
1 41
1+ •
8 5
2
=
( 41• 49.4%)2
200kHz • 260µH • 29.5W
= 0.267
Using the example numbers leads to:
IPK =
Setting Feedback Resistive Divider
The expression for VOUT developed in the Operation section
is rearranged to yield the following expression for the
feedback resistors:
(
)
V +I • ESR + R
OUT
SEC
DS(ON)
R1= R2
− 1
VFB • NSF
Continuing the example, if ESR + RDS(ON) = 8mW, R2 =
3.32k, then:
5 + 5.3 • 0.008
R1= 3.32k
− 1 = 37.28k
1.237 • 1/ 3
choose 37.4k.
It is recommended that the Thevenin impedance of the
resistive divider (R1||R2) is roughly 3k for bias current
cancellation and other reasons.
now :
DCMAX =
activity on all the secondary windings. Thus load regulation
is affected by each winding’s load. Take care to minimize
cross regulation effects.
29.5W 0.267
• 1+
= 1.65A
41• 0.494
2
Multiple Outputs
One advantage that the flyback topology offers is that
additional output voltages can be obtained simply by adding
windings. Designing a transformer for such a situation is
beyond the scope of this document. For multiple windings,
realize that the flyback winding signal is a combination of
Current Sense Resistor Considerations
The external current sense resistor is used to control peak
primary switch current, which controls a number of key
converter characteristics including maximum power and
external component ratings. Use a noninductive current
sense resistor (no wire-wound resistors). Mounting the
resistor directly above an unbroken ground plane connected
with wide and short traces keeps stray resistance and
inductance low.
The dual sense pins allow for a full Kelvin connection. Make
sure that SENSE+ and SENSE– are isolated and connect
close to the sense resistor.
Peak current occurs at 100mV of sense voltage VSENSE. So
the nominal sense resistor is VSENSE/IPK. For example, a
peak switch current of 10A requires a nominal sense resistor
of 0.010Ω Note that the instantaneous peak power in the
sense resistor is 1W, and that it is rated accordingly. The
use of parallel resistors can help achieve low resistance,
low parasitic inductance and increased power capability.
42681fc
31
LTC4268-1
Applications Information
Size RSENSE using worst-case conditions, minimum LP,
VSENSE and maximum VIN. Continuing the example, let us
assume that our worst-case conditions yield an IPK of 40%
above nominal so IPK = 2.3A. If there is a 10% tolerance
on RSENSE and minimum VSENSE = 88mV, then RSENSE •
110% = 88mV/2.3A and nominal RSENSE = 35mW. Round
to the nearest available lower value, 33mW.
The suggested empirical method is as follows:
Selecting the Load Compensation Resistor
DVOUT/DIOUT = RS(OUT).
The expression for RCMP was derived in the Operation
section as:
RCMP = K1•
RSENSE • (1− DC)
• R1• NSF
ESR + RDS(ON)
Continuing the example:
V
5
K1= OUT =
= 0.116
VIN • Eff 48 • 90%
1
1
DC=
=
= 45.5%
1 48
N•VIN(NOM)
1+ •
1+
8 5
VOUT
If ESR + RDS(ON) = 8mW
RCMP = 0.116 •
= 3.25k
33mW • (1− 0.455)
1
• 37.4kW •
8mW
3
This value for RCMP is a good starting point, but empirical
methods are required for producing the best results. This is
because several of the required input variables are difficult
to estimate precisely. For instance, the ESR term above
includes that of the transformer secondary, but its effective
ESR value depends on high frequency behavior, not simply
DC winding resistance. Similarly, K1 appears as a simple
ratio of VIN to VOUT times efficiency, but theoretically
estimating efficiency is not a simple calculation.
1. Build a prototype of the desired supply including the
actual secondary components.
2. Temporarily ground the CCMP pin to disable the load
compensation function. Measure output voltage while
sweeping output current over the expected range.
Approximate the voltage variation as a straight line.
3. Calculate a value for the K1 constant based on VIN, VOUT
and the measured efficiency.
4. Compute:
RCMP = K1•
RSENSE
• R1• NSF
RS(OUT)
5. Verify this result by connecting a resistor of this value
from the RCMP pin to ground.
6. Disconnect the ground short to CCMP and connect a 0.1µF
filter capacitor to ground. Measure the output impedance RS(OUT) = DVOUT/DIOUT with the new compensation
in place. RS(OUT) should have decreased significantly.
Fine tuning is accomplished experimentally by slightly
altering RCMP. A revised estimate for RCMP is:
RS(OUT)CMP
R′CMP = RCMP • 1+
RS(OUT)
where R′CMP is the new value for the load compensation
resistor. RS(OUT)CMP is the output impedance with RCMP
in place and RS(OUT) is the output impedance with no
load compensation (from step 2).
42681fc
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LTC4268-1
Applications Information
Setting Frequency
Selecting Timing Resistors
The switching frequency of the LTC4268-1 is set by an
external capacitor connected between the OSC pin and
ground. Recommended values are between 200pF and
33pF, yielding switching frequencies between 50kHz and
250kHz. Figure 15shows the nominal relationship between
external capacitance and switching frequency. Place the
capacitor as close as possible to the IC and minimize OSC
trace length and area to minimize stray capacitance and
potential noise pickup.
There are three internal “one-shot” times that are
programmed by external application resistors: minimum on
time, enable delay time and primary MOSFET turn-on delay.
These are all part of the isolated flyback control technique,
and their functions are previously outlined in the Theory
of Operation section. The following information should
help in selecting and/or optimizing these timing values.
You can synchronize the oscillator frequency to an external
frequency. This is done with a signal on the SYNC pin. Set
the LTC4268-1 frequency 10% slower than the desired
external frequency using the OSC pin capacitor, then use
a pulse on the SYNC pin of amplitude greater than 2V
and with the desired frequency. The rising edge of the
SYNC signal initiates an OSC capacitor discharge forcing
primary MOSFET off (PG voltage goes low). If the oscillator
frequency is much different from the sync frequency,
problems may occur with slope compensation and system
stability. Keep the sync pulse width greater than 500ns.
Minimum on time is the programmable period during which
current limit is blanked (ignored) after the turn on of the
primary side switch. This improves regulator performance
by eliminating false tripping on the leading edge spike in
the switch, especially at light loads. This spike is due to
both the gate/source charging current and the discharge of
drain capacitance. The isolated flyback sensing requires a
pulse to sense the output. Minimum on time ensures that
the output switch is always on a minimum time and that
there is always a signal to close the loop. The LTC4268-1
does not employ cycle skipping at light loads. Therefore,
Minimum Output Switch On Time (tON(MIN))
300
fOSC (kHz)
200
100
50
30
100
COSC (pF)
200
42681 F15
Figure 15. fOSC vs OSC Capacitor Values
42681fc
33
LTC4268-1
Applications Information
minimum on time along with synchronous rectification
sets the switch over to forced continuous mode operation.
The tON(MIN) resistor is set with the following equation
R tON(MIN) (kW ) =
tON(MIN) (ns ) − 104
1.063
Keep RtON(MIN) greater than 70k. A good starting value
is 160k.
Enable Delay Time (ENDLY)
Enable delay time provides a programmable delay between
turn-off of the primary gate drive node and the subsequent
enabling of the feedback amplifier. As discussed earlier, this
delay allows the feedback amplifier to ignore the leakage
inductance voltage spike on the primary side. The worst-case
leakage spike pulse width is at maximum load conditions.
So set the enable delay time at these conditions.
While the typical applications for this part use forced
continuous operation, it is conceivable that a secondary
side controller might cause discontinuous operation at
light loads. Under such conditions the amount of energy
stored in the transformer is small. The flyback waveform
becomes “lazy” and some time elapses before it indicates
the actual secondary output voltage. The enable delay time
should be made long enough to ignore the “irrelevant”
portion of the flyback waveform at light loads.
Even though the LTC4268-1 has a robust gate drive, the
gate transition time slows with very large MOSFETs. Increase delay time as required when using such MOSFETs.
The enable delay resistor is set with the following equation:
RENDLY (kW ) =
tENDLY (ns ) − 30
2.616
Primary Gate Delay Time (PGDLY)
Primary gate delay is the programmable time from the
turn-off of the synchronous MOSFET to the turn-on of
the primary side MOSFET. Correct setting eliminates
overlap between the primary side switch and secondary
side synchronous switch(es) and the subsequent current
spike in the transformer. This spike will cause additional
component stress and a loss in regulator efficiency.
The primary gate delay resistor is set with the following
equation:
RPGDLY (kW ) =
tPGDLY (ns ) + 47
9.01
A good starting point is 27k.
Soft-Start Function
The LTC4268-1 contains an optional soft-start function that
is enabled by connecting an external capacitor between
the SFST pin and ground. Internal circuitry prevents the
control voltage at the VCMP pin from exceeding that on
the SFST pin. There is an initial pull-up circuit to quickly
bring the SFST voltage to approximately 0.8V. From there it
charges to approximately 2.8V with a 20µA current source.
The SFST node is discharged to 0.8V when a fault occurs.
A fault occurs when VCC is too low (undervoltage lockout),
current sense voltage is greater than 200mV or the IC’s
thermal (over temperature) shutdown is tripped. When
SFST discharges, the VCMP node voltage is also pulled low
to below the minimum current voltage. Once discharged
and the fault removed, the SFST charges up again. In this
manner, switch currents are reduced and the stresses in
the converter are reduced during fault conditions.
The time it takes to fully charge soft-start is:
Keep RENDLY greater than 40k. A good starting point is 56k.
t ss =
CSFST • 1.4V
= 70kW • CSFST ( µF )
20µA
42681fc
34
LTC4268-1
Applications Information
Converter Start-Up
If CTR is undersized, VCC reaches the VCC turn-off threshold
before stabilization and the LTC4268-1 turns off. The VCC
node then begins to charge back up via RTR to the turn‑on
threshold, where the part again turns on. Depending upon
the circuit, this may result in either several on-off cycles
before proper operation is reached, or permanent relaxation
oscillation at the VCC node.
The standard topology for the LTC4268-1 utilizes a third
transformer winding on the primary side that provides
both feedback information and local VCC power for the
LTC4268-1 (see Figure 16). This power “bootstrapping”
improves converter efficiency but is not inherently selfstarting. Start-up is affected with an external “trickle charge”
resistor and the LTC4268-1’s internal VCC undervoltage
lockout circuit. The VCC undervoltage lockout has wide
hysteresis to facilitate start-up.
RTR is selected to yield a worst-case minimum charging
current greater than the maximum rated LTC4268-1 startup current, and a worst-case maximum charging current
less than the minimum rated LTC4268-1 supply current.
In operation, the “trickle charge” resistor RTR is connected
to VIN and supplies a small current, typically on the order
of 1mA to charge CTR. Initially the LTC4268-1 is off and
draws only its start-up current. When CTR reaches the
VCC turn-on threshold voltage the LTC4268-1 turns on
abruptly and draws its normal supply current.
VIN(MIN) − VCC(ON _ MAX)
R TR(MAX) <
ICC(ST _ MAX)
and
Switching action commences and the converter begins to
deliver power to the output. Initially the output voltage is
low and the flyback voltage is also low, so CTR supplies
most of the LTC4268-1 current (only a fraction comes
from RTR.) VCC voltage continues to drop until after some
time, typically tens of milliseconds, the output voltage
approaches its desired value. The flyback winding then
provides the LTC4268-1 supply current and the VCC
voltage stabilizes.
R TR(MIN) >
VIN(MAX) − VCC(ON _ MIN)
ICC(MIN)
Make CTR large enough to avoid the relaxation oscillatory
behavior described above. This is complicated to determine theoretically as it depends on the particulars of the
secondary circuit and load behavior. Empirical testing is
recommended. Note that the use of the optional soft-start
function lengthens the power-up timing and requires a
correspondingly larger value for CTR.
VIN
RTR
+
•
VIN
CTR
•
IVCC
•
VCC
LTC4268-1
PG
GND
VON THRESHOLD
VVCC
IVCC
0
VPG
42681 F16
Figure 16. Typical Power Bootstrapping
42681fc
35
LTC4268-1
Applications Information
The LTC4268-1 has an internal clamp on VCC of approximately 20V. This provides some protection for the part
in the event that the switcher is off (UVLO low) and the
VCC node is pulled high. If RTR is sized correctly the part
should never attain this clamp voltage.
Slope Compensation
The LTC4268-1 incorporates current slope compensation.
Slope compensation is required to ensure current loop
stability when the DC is greater than 50%. In some switching
regulators, slope compensation reduces the maximum peak
current at higher duty cycles. The LTC4268-1 eliminates
this problem by having circuitry that compensates for
the slope compensation so that maximum current sense
voltage is constant across all duty cycles.
Control Loop Compensation
Loop frequency compensation is performed by connecting a capacitor network from the output of the feedback
amplifier (VCMP pin) to ground as shown in Figure 17.
Because of the sampling behavior of the feedback amplifier,
compensation is different from traditional current mode
controllers. Normally only CVCMP is required. RVCMP can
be used to add a “zero” but the phase margin improvement traditionally offered by this extra resistor is usually
already accomplished by the nonzero secondary circuit
impedance. CVCMP2 can be used to add an additional high
frequency pole and is usually sized at 0.1 times CVCMP.
Minimum Load Considerations
At light loads, the LTC4268-1 derived regulator goes into
forced continuous conduction mode. The primary side
switch always turns on for a short time as set by the
tON(MIN) resistor. If this produces more power than the
load requires, power will flow back into the primary during
the “off” period when the synchronization switch is on.
This does not produce any inherently adverse problems,
although light load efficiency is reduced.
In further contrast to traditional current mode switchers,
VCMP pin ripple is generally not an issue with the LTC4268‑1.
The dynamic nature of the clamped feedback amplifier
forms an effective track/hold type response, whereby the
VCMP voltage changes during the flyback pulse, but is then
“held” during the subsequent “switch on” portion of the
next cycle. This action naturally holds the VCMP voltage
stable during the current comparator sense action (current
mode switching).
Maximum Load Considerations
The current mode control uses the VCMP node voltage and
amplified sense resistor voltage as inputs to the current
comparator. When the amplified sense voltage exceeds the
VCMP node voltage, the primary side switch is turned off.
In normal use, the peak switch current increases while
FB is below the internal reference. This continues until
VCMP reaches its 2.56V clamp. At clamp, the primary side
MOSFET will turn off at the rated 100mV VSENSE level. This
repeats on the next cycle. It is possible for the peak primary
switch currents as referred across RSENSE to exceed the
Application Note 19 provides a method for empirically
tweaking frequency compensation. Basically it involves
introducing a load current step and monitoring the
response.
VCMP
17
CVCMP2
RVCMP
CVCMP
42681 F17
Figure 17. VCMP Compensation Network
42681fc
36
LTC4268-1
Applications Information
max 100mV rating because of the minimum switch on
time blanking. If the voltage on VSENSE exceeds 205mV
after the minimum turn-on time, the SFST capacitor is
discharged, causing the discharge of the VCMP capacitor.
This then reduces the peak current on the next cycle and
will reduce overall stress in the primary switch.
Short-Circuit Conditions
Loss of current limit is possible under certain conditions
such as an output short circuit. If the duty cycle exhibited
by the minimum on time is greater than the ratio of
secondary winding voltage (referred-to-primary) divided
by input voltage, then peak current is not controlled at
the nominal value. It ratchets up cycle-by-cycle to some
higher level. Expressed mathematically, the requirement
to maintain short-circuit control is
DCMIN = t ON(MIN) • fOSC <
(
I SC • R SEC + R DS(ON)
VIN • N SP
)
where:
tON(MIN) is the primary side switch minimum on-time
ISC is the short-circuit output current
NSP is the secondary-to-primary turns ratio (NSEC/NPRI)
(Other variables as previously defined)
Trouble is typically encountered only in applications with a
relatively high product of input voltage times secondary to
primary turns ratio and/or a relatively long minimum switch
on time. Additionally, several real world effects such as
transformer leakage inductance, AC winding losses, and
output switch voltage drop combine to make this simple
theoretical calculation a conservative estimate. Prudent
design evaluates the switcher for short-circuit protection
and adds any additional circuitry to prevent destruction
for these losses.
Output Voltage Error Sources
The LTC4268-1’s feedback sensing introduces additional
minor sources of errors. The following is a summary list.
• The internal bandgap voltage reference sets the reference
voltage for the feedback amplifier. The specifications
detail its variation.
• The external feedback resistive divider ratio directly
affects regulated voltage. Use 1% components.
• Leakage inductance on the transformer secondary
reduces the effective secondary-to-feedback winding
turns ratio (NS/NF) from its ideal value. This increases
the output voltage target by a similar percentage. Since
secondary leakage inductance is constant from part to
part (within a tolerance) adjust the feedback resistor
ratio to compensate.
• The transformer secondary current flows through the
impedances of the winding resistance, synchronous
MOSFET RDS(ON) and output capacitor ESR. The DC
equivalent current for these errors is higher than the
load current because conduction occurs only during
the converter’s “off” time. So divide the load current
by (1 – DC).
If the output load current is relatively constant, the feedback
resistive divider is used to compensate for these losses.
Otherwise, use the LTC4268-1 load compensation circuitry.
(See Load Compensation.) If multiple output windings are
used, the flyback winding will have a signal that represents
an amalgamation of all these windings impedances. Take
care that you examine worst-case loading conditions when
tweaking the voltages.
42681fc
37
LTC4268-1
Applications Information
Power MOSFET Selection
The power MOSFETs are selected primarily on the criteria of
“on” resistance RDS(ON), input capacitance, drain-to‑source
breakdown voltage (BVDSS), maximum gate voltage (VGS)
and maximum drain current (ID(MAX)).
For the primary-side power MOSFET, the peak current is:
IPK(PRI) =
PIN
VIN(MIN) • DCMAX
X
• 1+ MIN
2
IOUT
1− DCMAX
X
• 1+ MIN
2
Select a primary-side power MOSFET with a BVDSS greater
than:
BVDSS ≥IPK
Primary side power MOSFET RMS current is given by:
PIN
IRMS(PRI) =
VIN(MIN) DCMAX
For each secondary-side power MOSFET RMS current is
given by:
where XMIN is peak-to-peak current ratio as defined
earlier. For each secondary-side power MOSFET, the peak
current is:
IPK(SEC) =
Choose the primary side MOSFET RDS(ON) at the nominal
gate drive voltage (7.5V). The secondary side MOSFET
gate drive voltage depends on the gate drive method.
IRMS(SEC) =
IOUT
1− DCMAX
Calculate MOSFET power dissipation next. Because the
primary-side power MOSFET operates at high VDS, a
transition power loss term is included for accuracy. CMILLER
is the most critical parameter in determining the transition
loss, but is not directly specified on the data sheets.
CMILLER is calculated from the gate charge curve included
on most MOSFET data sheets (Figure 17).
VOUT(MAX)
LLKG
+ VIN(MAX) +
CP
NSP
where NSP reflects the turns ratio of that secondary-to
primary winding. LLKG is the primary-side leakage inductance and CP is the primary-side capacitance (mostly from
the drain capacitance (COSS) of the primary-side power
MOSFET). A snubber may be added to reduce the leakage
inductance as discussed.
For each secondary-side power MOSFET, the BVDSS should
be greater than:
BVDSS ≥ VOUT + VIN(MAX) • NSP
The flat portion of the curve is the result of the Miller
(gate-to-drain) capacitance as the drain voltage drops.
The Miller capacitance is computed as:
CMILLER =
QB − Q A
VDS
The curve is done for a given VDS. The Miller capacitance
for different VDS voltages are estimated by multiplying the
computed CMILLER by the ratio of the application VDS to
the curve specified VDS.
MILLER EFFECT
VGS
a
b
QA
QB
GATE CHARGE (QG)
42681 F18
Figure 18. Gate Charge Curve
42681fc
38
LTC4268-1
Applications Information
With CMILLER determined, calculate the primary-side power
MOSFET power dissipation:
PD(PRI) =IRMS(PRI)2 • RDS(ON) (1+ d ) +
VIN(MAX) •
PIN(MAX)
DCMIN
• RDR •
CMILLER
•f
VGATE(MAX) − VTH OSC
where:
RDR is the gate driver resistance (≈10W)
VTH is the MOSFET gate threshold voltage
fOSC is the operating frequency
VGATE(MAX) = 7.5V for this part
(1 + d) is generally given for a MOSFET in the form of a
normalized RDS(ON)vs temperature curve. If you don’t have
a curve, use d = 0.005/°C • DT for low voltage MOSFETs.
The secondary-side power MOSFETs typically operate
at substantially lower VDS, so you can neglect transition
losses. The dissipation is calculated using:
ringing at the expense of slightly slower rise and fall times
and poorer efficiency.
The LTC4268-1 gate drives will clamp the max gate voltage
to roughly 7.5V, so you can safely use MOSFETs with
maximum VGS of 10V and larger.
Synchronous Gate Drive
There are several different ways to drive the synchronous
gate MOSFET. Full converter isolation requires the synchronous gate drive to be isolated. This is usually accomplished
by way of a pulse transformer. Usually the pulse driver is
used to drive a buffer on the secondary as shown in the
application on the front page of this data sheet.
However, other schemes are possible. There are gate drivers
and secondary side synchronous controllers available that
provide the buffer function as well as additional features.
Capacitor Selection
PDIS(SEC) = IRMS(SEC)2 • RDS(ON)(1 + d)
In a flyback converter, the input and output current flows
in pulses, placing severe demands on the input and output
filter capacitors. The input and output filter capacitors are
selected based on RMS current ratings and ripple voltage.
With power dissipation known, the MOSFETs’ junction
temperatures are obtained from the equation:
Select an input capacitor with a ripple current rating
greater than:
TJ = TA + PDIS • qJA
where TA is the ambient temperature and qJA is the MOSFET
junction to ambient thermal resistance.
IRMS(PRI) =
PIN
1− DCMAX
DCMAX
VIN(MIN)
Once you have TJ iterate your calculations recomputing
d and power dissipations until convergence.
Continuing the example:
Gate Drive Node Consideration
The PG and SG gate drivers are strong drives to minimize
gate drive rise and fall times. This improves efficiency
but the high frequency components of these signals can
cause problems. Keep the traces short and wide to reduce
parasitic inductance.
Keep input capacitor series resistance (ESR) and
inductance (ESL) small, as they affect electromagnetic
interference suppression. In some instances, high ESR can
also produce stability problems because flyback converters
exhibit a negative input resistance characteristic. Refer
to Application Note 19 for more information. The output
capacitor is sized to handle the ripple current and to ensure
acceptable output voltage ripple.
The parasitic inductance creates an LC tank with the
MOSFET gate capacitance. In less than ideal layouts, a
series resistance of 5Ω or more may help to dampen the
IRMS(PRI) =
29.5W
41V
1− 49.4%
= 0.728A
49.4%
42681fc
39
LTC4268-1
Applications Information
The output capacitor should have an RMS current rating
greater than:
IRMS(SEC) =IOUT
DCMAX
1− DCMAX
ESRCOUT ≤ 1% •
VOUT • (1− DCMAX )
IOUT
The other 1% is due to the bulk C component, so use:
Continuing the example:
IRMS(SEC) = 5.3A
to the total ripple voltage, the ESR of the output capacitor
is determined by:
49.4%
= 5.24A
1− 49.4%
COUT ≥
This is calculated for each output in a multiple winding
application.
ESR and ESL along with bulk capacitance directly affect the
output voltage ripple. The waveforms for a typical flyback
converter are illustrated in Figure 19.
The maximum acceptable ripple voltage (expressed as a
percentage of the output voltage) is used to establish a
starting point for the capacitor values. For the purpose
of simplicity we will choose 2% for the maximum output
ripple, divided equally between the ESR step and the
charging/discharging DV. This percentage ripple changes,
depending on the requirements of the application. You
can modify the equations below. For a 1% contribution
PRIMARY
CURRENT
In many applications the output capacitor is created from
multiple capacitors to achieve desired voltage ripple,
reliability and cost goals. For example, a low ESR ceramic
capacitor can minimize the ESR step, while an electrolytic
capacitor satisfies the required bulk C.
Continuing our example, the output capacitor needs:
5V • (1− 49.4%)
= 4mW
5.3A
5.3A
COUT ≥
= 600µF
1% • 5 • 200kHz
ESRCOUT ≤ 1% •
These electrical characteristics require paralleling several
low ESR capacitors possibly of mixed type.
IPRI
SECONDARY
CURRENT
IPRI
N
RINGING
DUE TO ESL
∆VCOUT
OUTPUT VOLTAGE
RIPPLE WAVEFORM
IOUT
1% • VOUT • fOSC
∆VESR
42681 F19
Figure 19. Typical Flyback Converter Waveforms
42681fc
40
LTC4268-1
Applications Information
Most capacitor ripple current ratings are based on 2000
hour life. This makes it advisable to derate the capacitor
or to choose a capacitor rated at a higher temperature
than required.
there will be any user accessible connection to the PD,
then an isolated DC/DC converter is necessary to meet
the isolation requirements. If user connections can be
avoided, then it is possible to meet the safety requirement
by completely enclosing the PD in an insulated housing.
In all PD applications, there should be no user accessible
electrical connections to the LTC4268-1 or support circuitry
other than the RJ-45 port.
One way to reduce cost and improve output ripple is to use
a simple LC filter. Figure 20 shows an example of the filter.
The design of the filter is beyond the scope of this data
sheet. However, as a starting point, use these general
guidelines. Start with a COUT 1/4 the size of the nonfilter
solution. Make C1 1/4 of COUT to make the second filter
pole independent of COUT. C1 may be best implemented
with multiple ceramic capacitors. Make L1 smaller than
the output inductance of the transformer. In general, a
0.1µH filter inductor is sufficient. Add a small ceramic
capacitor (COUT2) for high frequency noise on VOUT. For
those interested in more details refer to “Second-Stage
LC Filter Design,” Ridley, Switching Power Magazine, July
2000 p8-10.
LAYOUT CONSIDERATIONS FOR THE LTC4268-1
The LTC4268-1’s PD front end is relatively immune to
layout problems. Place C14 (Figure 9) as close as physically
possible to the LTC4268-1. Place the series 10Ω resistor
close to C14. Excessive parasitic capacitance on the RCLASS
pin should be avoided. Include a PCB heat sink to which
the exposed pad on the bottom of the package can be
soldered. This heat sink should be electrically connected
to GND. For optimum thermal performance, make the
heat sink as large as possible. Voltages in a PD can be
as large as –57V for PoE applications, so high voltage
layout techniques should be employed. The SHDN pin
should be separated from other high voltage pins, like
VPORTP, VOUT, to avoid the possibility of leakage shutting
down the LTC4268-1. If not used, tie SHDN to VPORTN.
The load capacitor connected between VPORTP and VOUT
of the LTC4268-1 can store significant energy when fully
charged. The design of a PD must ensure that this energy
is not inadvertently dissipated in the LTC4268-1. The
polarity-protection diodes prevent an accidental short
on the cable from causing damage. However if, VPORTN
is shorted to VPORTP inside the PD while capacitor C1
is charged, current will flow through the parasitic body
diode of the internal MOSFET and may cause permanent
damage to the LTC4268-1.
Circuit simulation is a way to optimize output capacitance
and filters, just make sure to include the component
parasitic. LTC SwitcherCAD® is a terrific free circuit
simulation tool that is available at www.linear.com. Final
optimization of output ripple must be done on a dedicated
PC board. Parasitic inductance due to poor layout can
significantly impact ripple. Refer to the PC Board Layout
section for more details.
ISOLATION
The 802.3 standard requires Ethernet ports to be electrically
isolated from all other conductors that are user accessible.
This includes the metal chassis, other connectors and
any auxiliary power connection. For PDs, there are two
common methods to meet the isolation requirement. If
L1
0.1µH
FROM
SECONDARY
WINDING
+
C1
47µF
×3
VOUT
+
COUT
470µF
COUT2
1µF
RLOAD
42681 F20
Figure 20. LC Filter
42681fc
41
LTC4268-1
Applications Information
the MOSFET node voltages with an oscilloscope. If it is
breaking down either choose a higher voltage device, add
a snubber or specify an avalanche-rated MOSFET.
In order to minimize switching noise and improve output
load regulation, connect the GND pin of the LTC4268-1
directly to the ground terminal of the VCC decoupling
capacitor, the bottom terminal of the current sense resistor
and the ground terminal of the input capacitor, using a
ground plane with multiple vias. Place the VCC capacitor
immediately adjacent to the VCC and GND pins on the IC
package. This capacitor carries high di/dt MOSFET gate
drive currents. Use a low ESR ceramic capacitor. Take care
in PCB layout to keep the traces that conduct high switching
currents short, wide and with minimal overall loop area.
These are typically the traces associated with the switches.
This reduces the parasitic inductance and also minimizes
magnetic field radiation. Figure 21 outlines the critical paths.
Keep electric field radiation low by minimizing the length
and area of traces (keep stray capacitances low). The drain
of the primary side MOSFET is the worst offender in this
category. Always use a ground plane under the switcher
circuitry to prevent coupling between PCB planes. Check
that the maximum BVDSS ratings of the MOSFETs are not
exceeded due to inductive ringing. This is done by viewing
Place the small-signal components away from high
frequency switching nodes. This allows the use of a pseudoKelvin connection for the signal ground, where high di/
dt gate driver currents flow out of the IC ground pin in
one direction (to the bottom plate of the VCC decoupling
capacitor) and small-signal currents flow in the other
direction. Keep the trace from the feedback divider tap
to the FB pin short to preclude inadvertent pickup. For
applications with multiple switching power converters
connected to the same input supply, make sure that the
input filter capacitor for the LTC4268-1 is not shared with
other converters. AC input current from another converter
could cause substantial input voltage ripple and this could
interfere with the LTC4268-1 operation. A few inches of PC
trace or wire (L @100nH) between the CIN of the LTC4268-1
and the actual source VIN is sufficient to prevent current
sharing problems.
T1
VCC
•
VIN
CVCC
•
GATE
TURN-ON
VCC
PG
MP
+
•
CVIN
GATE
TURN-OFF
OUT
RSENSE
+
VCC
CR
VCC
SG
•
T2
+
Q4
COUT
GATE
TURN-ON
MS
•
Q3
GATE
TURN-OFF
42681 F21
Figure 21. Layout Critical High Current Paths
42681fc
42
RJ45
8
7
5
4
6
3
2
1
J1
XFMR
SPARE–
SPARE+
R5
75Ω
8
10
9
7
11
RX–
3
6
14
2
RX+
15
TX–
TX+
T3
ETH1–230LD
16
1
–54V IN FROM
HIGH POWER PSE
C14
0.01µF
200V
TO
PHY
R4
75Ω
C16
0.01µF
200V
R7
75Ω
R6
75Ω
C15
0.01µF
200V
J3
D6
24V 30W
AUX POWER IN
C13
0.01µF
200V
D7
C44
0.001µF D2
2kV
D3
D9
D8
D5
D4
0.1µF
100V
B2100X8
VPORTP
R18
100k
R14
4.7k
R21
20k
Q5
FMMT723
D1
SMAJ58A
10Ω
C1A
12µF
100V
PWRGD
100k
PWRGD
C1B
2.2µF
100V
RCLASS
S2B
+
RPGDLY
15k
SYNC
OSC
R10
91Ω
D11
BAS21
RENDLY COSC
150k 33pF
ENDLY
R9
20k
1/4W
RCMP
2.1k
RCMP
VCC
C19
0.1µF
ILIM_EN
RtON
100k
tON
LTC4268-1
UVLO
C18
22µF
16V
RCLASS
VPORTN VPORTN VPORTN VNEG VNEG VNEG PGDLY
SHDN
VPORTP
C8
0.1µF
100V
+
L2
4.7µH
PG
C7
1000pF
100V
CCMP
R27
10k
GND
VCMP
SG
SENSE–
SENSE+
CSFST CCMP
0.033µF 0.1µF
SFST
FB
R20
3.01k
1%
R13
29.4k
1%
R2
10Ω
30W High Efficiency Triple Output PD Supply (Order Demo Circuit DC1080A)
C26
680pF
C33
3300pF
RSENSE
0.015Ω
1/8W
1%
Q3
Si4488DY
•
•
C28
2200pF
C11
220pF
C4
1500pF
42681 TA02
R28
10k
R22
15Ω
Q6
FMMT618
D14
BAT54
Q7
FMMT718
Q4
Si4362DY
•
Q2
Si4488DY
•
Q1
Si4470EY
•
C23
4700pF
250VAC
T2
PA0184
R17
330Ω
C27
0.1µF
•
•
T1
PA1558NL
+
C24
1µF
R15
47Ω
R13
B0540W
R8
10Ω
1/4W
R3
10Ω
1/4W
+
C21
47µF
×2
L3
0.33µH
C5
47µF
L1
0.33µH
+
+
+
C22
100µF
C10
22µF
×2
C6
100µF
3.3V
4A
11.8V
0.27A
5V
2.4A
LTC4268-1
typical Application
42681fc
43
LTC4268-1
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
DKD Package
32-Lead Plastic DFN (7mm × 4mm)
(Reference LTC DWG # 05-08-1734 Rev A)
0.70 ±0.05
4.50 ±0.05
6.43 ±0.05
2.65 ±0.05
3.10 ±0.05
PACKAGE
OUTLINE
0.20 ±0.05
0.40 BSC
6.00 REF
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
7.00 ±0.10
17
R = 0.115
TYP
32
R = 0.05
TYP
0.40 ±0.10
6.43 ±0.10
4.00 ±0.10
2.65 ±0.10
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45° CHAMFER
PIN 1
TOP MARK
(SEE NOTE 6)
16
0.75 ±0.05
0.40 BSC
BOTTOM VIEW—EXPOSED PAD
0.200 REF
0.20 ±0.05
1
6.00 REF
(DKD32) QFN 0707 REV A
0.00 – 0.05
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WXXX)
IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
42681fc
44
LTC4268-1
Revision History
(Revision history begins at Rev C)
REV
DATE
DESCRIPTION
C
08/12
Simplified Overview section, including removal of Figure 1A and 1B which caused renumbering of all figures in
data sheet
PAGE NUMBER
Changed maximum power levels for class 0 and class 3 to 13.0W
Added 10Ω resistor to VPORTP pin on schematic to make solution more robust to current surges
13, 14
15
20, 43
Added Input Capacitor, Input Series Resistance and Transient Voltage Supressor sections
21
Added C14 and 10Ω resistor layout recommendation
41
42681fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
45
LTC4268-1
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42681fc
46 Linear Technology Corporation
LT 0812 REV C • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 l FAX: (408) 434-0507
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