LTC4291-1/LTC4292
4-Port IEEE 802.3bt
PoE PSE Controller
FEATURES
DESCRIPTION
Four PSE Ports
nn Two Power Channels per Port
nn Fully Compliant IEEE 802.3bt Type 3 and 4 PSE
nn Compliant Support for Type 1, 2, 3, and 4 PDs
nn Low Power Path Dissipation per Channel
nn 150mΩ Sense Resistance
nn 30mΩ or Lower MOSFET R
DS(ON)
nn Chipset Provides Electrical Isolation
nn Eliminates Optos and Isolated 3.3V Supply
nn Very High Reliability Multipoint PD Detection
nn Connection Check Distinguishes SingleSignature and Dual-Signature PDs
nn Continuous, Dedicated Per-Port Power and Current
Monitoring
nn Per-Port Power Policing
nn 1MHz I2C Compatible Serial Control Interface
nn Pin or I2C Programmable PD Power Up to 71.3W
nn Available in a 40-Lead 6mm × 6mm (LTC4292) and
24-Lead 4mm × 4mm (LTC4291-1) QFN Packages
The LTC®4291-1/LTC4292 chipset is a 4-port power
sourcing equipment (PSE) controller designed for use in
IEEE 802.3bt Type 3 and 4 compliant Power over Ethernet
(PoE) systems. The LTC4291-1/LTC4292 is designed to
power compliant 802.3af, 802.3at, and 802.3bt PDs. The
LTC4291-1/LTC4292 chipset delivers lowest-in-industry heat dissipation by utilizing low RDS(ON) external
MOSFETs and 0.15Ω sense resistance per power channel.
A transformer-isolated communication protocol replaces
expensive opto-couplers and complex isolated 3.3V supply, resulting in significant BOM cost savings.
nn
Advanced power management features include per-port
14‑bit current monitoring, programmable current limit,
and versatile fast shutdown of preselected ports. Advanced
power management host software is available under a nocost license. PD detection uses a proprietary multipoint
detection mechanism ensuring excellent immunity from
false PD identification. Autoclass and 5-event physical
classification are supported. The LTC4291-1/LTC4292
includes an I2C serial interface operable up to 1MHz. The
LTC4291-1/LTC4292 is pin or I2C programmable to negotiate PD delivered power up to 71.3W.
APPLICATIONS
nn
nn
PoE PSE Switches/Routers
PoE PSE Midspans
All registered trademarks and trademarks are the property of their respective owners.
TYPICAL APPLICATION
AGNDP
10Ω
0.1µF
GP0
3.3V
>47µF
VEE
VDD
DGND
CAP1
4
S1B
5
7
0.22µF
2nF
2kV
6
TX3
S1B
GATEnB
DNA
1µF
VEE
OUTnB
100Ω
DND
0.22µF
100V
LTC4292
VEE
100Ω
SDAOUT
VSSKn
TX2
AGNDP
100Ω
3.3V
SDAIN
AD0
AD1
AD2
AD3
DPA
100Ω
SCL
0.15Ω
SENSEnA
CNA
LTC4291-1 DPD
2
3
100Ω
CND
TX1
S1B
S1B
GATEnA
VEE
100Ω
MSD
0.22µF
100V
100Ω
3.3V
RESET
AGNDP
AGNDP
OUTnA
CPA
100Ω
AUTO
INT
PWRMD1
CPD
4PVALID
(NO I2C
ISOLATION
REQUIRED)
PWRMD0
ISOLATION
GP1
1
1µF
100V
CAP2
VEE
VEE
0.15Ω
SENSEnB
VSSKn
VSSKn
TX4
VEE
8
1000BASE-T
0.22μF, 100V
0.15Ω
(1 OF 4 PORTS)
RJ45
42911 TA01a
AGNDP
VSSKn
Rev 0
Document Feedback
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1
LTC4291-1/LTC4292
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 4)
(Note 1)
LTC4292
Supply Voltages
AGNDP – VEE.......................................... –0.3V to 80V
VSSK12, VSSK34 (Note 7).... VEE – 0.3V to VEE + 0.3V
Digital Pins
PWRMD0, PWRMD1......... VEE – 0.3V to CAP2 + 0.3V
Analog Pins
SENSEnM, GATEnM, OUTnM .VEE – 0.3V to VEE + 80V
CAP2 (Note 13) ....................... VEE – 0.3V to VEE + 5V
CPA, CNA, DPA, DNA...............VEE – 0.3V to VEE + 0.3
Operating Ambient Temperature Range
LTC4292I..............................................–40°C to 85°C
Junction Temperature (Note 2)............................. 125°C
Storage Temperature Range................... –65°C to 150°C
LTC4291-1
Supply Voltages
VDD – DGND.......................................... –0.3V to 3.6V
Digital Pins
SCL, SDAIN, SDAOUT, INT, RESET, MSD, ADn, AUTO,
4PVALID, GPn ..................DGND – 0.3V to VDD + 0.3V
Analog Pins
CAP1 (Note 13)............................–0.3V to DGND + 2V
CPD, CND, DPD, DND.......DGND – 0.3V to VDD + 0.3V
Operating Ambient Temperature Range
LTC4291I-1...........................................–40°C to 85°C
Junction Temperature (Note 2)............................. 125°C
Storage Temperature Range................... –65°C to 150°C
PIN CONFIGURATION
LTC4291-1
VEE
VSSK12 5
24 GATE3B
OUT2A 8
23 OUT3B
GATE2B 9
22 GATE3A
PWRMD1
SENSE4B
SENSE4A
SENSE3B
SENSE3A
SENSE2B
SENSE2A
SENSE1B
SENSE1A
PWRMD0
2
CAP1
VDD
15 INT
DGND 5
14 RESET
4PVALID 6
11 12 13 14 15 16 17 18 19 20
UJ PACKAGE
40-LEAD (6mm × 6mm) PLASTIC QFN
TJMAX = 125°C, θJC = 2°C/W, θJA = 33°C/W
EXPOSED PAD (PIN 41) IS VEE, MUST BE SOLDERED TO PCB
16 SDAOUT
25
DGND
AD3 4
21 OUT3A
OUT2B 10
17 SDAIN
AD2 3
25 AGNDP
GATE2A 7
18 SCL
AD1 2
26 VSSK34
41
VEE
CAP2 6
AD0 1
13 DNC
7
8
9 10 11 12
VDD
27 OUT4A
AUTO
OUT1B 4
24 23 22 21 20 19
DND
28 GATE4A
GP0
GATE1B 3
MSD
29 OUT4B
NC
OUT1A 2
CPD
30 GATE4B
GP1
TOP VIEW
40 39 38 37 36 35 34 33 32 31
GATE1A 1
DPD
NC
VEE
NC
NC
DNA
DPA
CNA
CPA
VEE
TOP VIEW
CND
LTC4292
UF PACKAGE
24-LEAD (4mm × 4mm) PLASTIC QFN
TJMAX = 125°C, θJC = 4°C/W, θJA = 47°C/W
EXPOSED PAD (PIN 25) IS DGND, MUST BE SOLDERED TO PCB
Rev 0
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LTC4291-1/LTC4292
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4291IUF-1#PBF
LTC4291IUF-1#TRPBF
42911
24-Lead (4mm × 4mm) Plastic QFN
–40°C to 85°C
LTC4292IUJ#PBF
LTC4292IUJ#TRPBF
LTC4292UJ
40-Lead (6mm × 6mm) Plastic QFN
–40°C to 85°C
Contact the factory for parts specified with wider operating temperature ranges.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
ELECTRICAL
CHARACTERISTICS
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AGNDP – VEE = 54V and VDD – DGND = 3.3V unless otherwise noted.
(Notes 3 and 4)
SYMBOL
PARAMETER
CONDITIONS
Main PoE Supply Voltage
AGNDP – VEE
For IEEE Type 3 Compliant Output
For IEEE Type 4 Compliant Output
l
l
51
53
Undervoltage Lock-Out
AGNDP – VEE
l
20
VDD Supply Voltage
VDD – DGND
l
3.0
Undervoltage Lock-Out
VDD – DGND
2.7
V
VCAP1
Internal Regulator Supply Voltage
VCAP1 – DGND
1.84
V
VDD
MIN
VCAP2
Internal Regulator Supply Voltage
VCAP2 – VEE
IEE
VEE Supply Current
(AGNDP – VEE) = 55V
l
REE
VEE Supply Resistance
(AGNDP – VEE) < 15V
l
IDD
VDD Supply Current
(VDD – DGND) = 3.3V
l
Forced Current
First Point, AGNDP – VOUTnM = 9V
Second Point, AGNDP – VOUTnM = 3.5V
l
l
Forced Voltage
AGNDP – VOUTnM, 5µA ≤ IOUTnM ≤ 500µA
First Point
Second Point
l
l
Detection/Connection Check Current
Compliance
AGNDP – VOUTnM = 0V
Detection/Connection Check Voltage
Compliance
Detection/Connection Check Voltage
Slew Rate
TYP
MAX
UNITS
57
57
V
V
25
30
V
3.3
3.6
4.3
9
V
V
15
mA
12
kΩ
10
15
mA
220
143
240
160
260
180
µA
µA
7
3
8
4
9
5
V
V
l
0.8
0.9
mA
AGNDP – VOUTnM, Open Port
l
10.4
12
V
AGNDP – VOUTnM, CPORT = 0.15µF (Note 7)
l
Detection/Connection Check
VOC
0.01
V/µs
Min. Valid Signature Resistance
l
15.5
17
18.5
kΩ
Max. Valid Signature Resistance
l
27.5
29.7
32
kΩ
Rev 0
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3
LTC4291-1/LTC4292
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AGNDP – VEE = 54V and VDD – DGND = 3.3V unless otherwise noted.
(Notes 3 and 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Classification Voltage
AGNDP – VOUTnM, 0mA ≤ IOUTnM ≤ 50mA
l
16.0
Classification Current Compliance
VOUTnM = AGNDP
l
53
61
67
mA
Classification Threshold Current
Class Signature 0 – 1
Class Signature 1 – 2
Class Signature 2 – 3
Class Signature 3 – 4
Class Signature 4 – Overcurrent
l
l
l
l
l
5.5
13.5
21.5
31.5
45.2
6.5
14.5
23
33
48
7.5
15.5
24.5
34.9
50.8
mA
mA
mA
mA
mA
Classification Mark State Voltage
AGNDP – VOUTnM, 0.1mA ≤ ICLASS ≤ 5mA
l
7.5
9
10
V
Mark State Current Compliance
VOUTnM = AGNDP
l
53
61
67
mA
GATE Pin Pull-Down Current
Port Off, VGATEnM = VEE + 5V
Port Off, VGATEnM = VEE + 1V
l
l
0.4
0.08
0.12
mA
mA
GATE Pin Fast Pull-Down Current
VGATEnM = VEE + 5V
30
mA
GATE Pin On Voltage
VGATEnM – VEE, IGATEnM = 1µA
l
8
12
14
V
Power Good Threshold Voltage
VOUTnM – VEE
l
2
2.4
2.8
V
OUT Pin Pull-Up Resistance to AGNDP
0V ≤ (AGNDP – VOUTnM) ≤ 5V
l
300
500
700
kΩ
Overcurrent Sense Voltage,
Single-Signature PD
VSENSEnM – VSSKn
Class 1, CUTn[6:0] = 45h
Class 2, CUTn[6:0] = 48h
Class 3, CUTn[6:0] = 52h
Class 4, CUTn[6:0] = 62h
Class 5, CUTn[6:0] = 5Fh
Class 6, CUTn[6:0] = 67h
Class 7, CUTn[6:0] = 6Ch
Class 8, CUTn[6:0] = 74h (Note 12)
l
l
l
l
l
l
l
l
13.5
21.6
47.5
92.0
84.0
105
119
140
14.1
22.5
50.5
96.0
87.0
110
124
146
14.6
23.4
53.5
100.0
91.0
114
129
152
mV
mV
mV
mV
mV
mV
mV
mV
Overcurrent Sense Voltage,
Dual-Signature PD
VSENSEnM – VSSKn
Class 1, CUTn[6:0] = 45h
Class 2, CUTn[6:0] = 48h
Class 3, CUTn[6:0] = 52h
Class 4, CUTn[6:0] = 62h
Class 5, CUTn[6:0] = 74h (Note 12)
l
l
l
l
l
13.5
21.6
47.5
92.0
140
14.1
22.5
50.5
96.0
146
14.6
23.4
53.5
100.0
152
mV
mV
mV
mV
mV
Active Current Limit,
Single-Signature PD
VOUTnM – VEE < 10V
Class 1 – Class 3, LIMn = 80h
Class 4 – Class 6, LIMn = C0h
Class 7, LIMn = D0h
Class 8, LIMn = E9h (Note 12)
l
l
l
l
61.2
122
153
168
63.6
128
159
175
67.3
135
169
185
mV
mV
mV
mV
Active Current Limit,
Dual-Signature PD
VOUTnM – VEE < 10V
Class 1 – Class 3, LIMn = 80h
Class 4, LIMn = C0h
Class 5, LIMn = E9h (Note 12)
l
l
l
61.2
122
168
63.6
128
175
67.3
135
185
mV
mV
mV
Active Current Limit, Inrush
AGNDP – VOUTnM > 30V (Note 17)
LIMn = 80h
LIMn = 08h
l
l
61.2
30.6
63.6
31.8
67.3
33.7
mV
mV
VSENSEnM – VSSKn
CUTn[7] (Dis) Bit = 0
CUTn[7] (Dis) Bit = 1 (Note 12)
l
l
0.31
0.76
0.53
1.13
0.74
1.49
mV
mV
Classification
VCLASS
VMARK
20.5
V
Gate Driver
Output Voltage Sense
VPG
Current Sense
VCUT-2P
VLIM-2P
VINRUSH-2P
VHOLD-2P
4
DC Disconnect Sense Voltage
Rev 0
For more information www.analog.com
LTC4291-1/LTC4292
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AGNDP – VEE = 54V and VDD – DGND = 3.3V unless otherwise noted.
(Notes 3 and 4)
SYMBOL
PARAMETER
CONDITIONS
VSC
Short-Circuit Sense
VSENSEnM – VEE – VLIM
l
MIN
TYP
MAX
20
50
80
UNITS
mV
Port Current Readback
Full-Scale Range
(Notes 7, 15, 16)
1.018
LSB Weight
VSENSEnM – VSSKn, VSSKn = VEE (Note 15)
Averaging Period
FILTER_TYPE Bit = 1
FILTER_TYPE Bit = 0 (Note 7)
100
1000
ms
ms
Update Interval
(Note 7)
100
ms
Full-Scale Range
(Notes 7, 15, 16)
83.8
V2
LSB Weight
(VSENSEnM – VSSKn) × (AGNDP – VEE)
VSSKn = VEE (Note 15)
Averaging Period
FILTER_TYPE Bit = 1
FILTER_TYPE Bit = 0 (Note 7)
100
1000
ms
ms
Update Interval
(Note 7)
100
ms
l
61.0
62.1
V
63.5
µV/LSB
Port Power Readback
l
4.992
5.115
5.235
mV2/LSB
System Voltage Readback
Full-Scale Range
(Note 7)
LSB Weight
AGNDP – VEE
82
Averaging Period
FILTER_TYPE Bit = 1
FILTER_TYPE Bit = 0 (Note 7)
100
1000
ms
ms
Update Interval
(Note 7)
100
ms
Digital Input Low Voltage
ADn, RESET, MSD, GPn, AUTO, 4PVALID (Note 6)
l
0.8
V
I2C Input Low Voltage
SCL, SDAIN (Note 6)
l
1.0
V
Digital Input High Voltage
(Note 6)
l
Digital Output Voltage Low
ISDAOUT = 3mA, IINT = 3mA
ISDAOUT = 5mA, IINT = 5mA
l
l
Internal Pull-Up to VDD
ADn, RESET, MSD, GPn
50
kΩ
Internal Pull-Down to DGND
AUTO, 4PVALID
50
kΩ
PWRMD Digital Input Low Voltage
VPWRMDn – VEE
l
PWRMD Digital Input High Voltage
VPWRMDn – VEE
l
Internal Pull Up to CAP2
PWRMD0, PWRMD1
l
9.8
10.1
V
10.3
mV/LSB
Digital Interface
VILD
VIHD
2.2
V
0.4
0.7
V
V
PWRMD
0.8
3.4
V
V
50
kΩ
PSE Timing Characteristics (Note 7)
tDET
Detection Time
tCLASS_RESET
Classification Reset Duration
Beginning to End of Detection
l
15
tCEV
Class Event Duration
l
6
CPORT = 0.6µF
320
l
tCEVON
Class Event Turn On Duration
tLCE
Long Class Event Duration
l
88
tCLASS
Class Event ICLASS Measurement Timing
l
6
tCLASS_LCE
Long Class Event ICLASS Measurement
Timing
l
6
tCLASS_ACS
Autoclass ICLASS Measurement Timing
l
88
l
500
ms
ms
12
20
ms
0.1
ms
105
ms
75
ms
ms
ms
Rev 0
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5
LTC4291-1/LTC4292
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AGNDP – VEE = 54V and VDD – DGND = 3.3V unless otherwise noted.
(Notes 3 and 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
tME1
Mark Event Duration (Except Last Mark
Event)
(Note 11)
l
6
8.6
12
tME2
Last Mark Event Duration
(Note 11)
l
6
20
tPON
Power On Delay, Auto Mode
From End of Valid Detect to End of Valid Inrush
(Note 14)
l
tAUTO_PSE1
Autoclass Power Measurement Start
From End of Inrush to Beginning of Autoclass
Power Measurement
l
tAUTO_PSE2
Autoclass Power Measurement End
From End of Inrush to End of Autoclass Power
Measurement
tAUTO_WINDOW
Autoclass Average Power Sliding
Window
tED
Fault Delay
tSTART
tCUT
UNITS
ms
ms
400
ms
1.4
1.6
s
l
3.1
3.5
s
l
0.15
0.2
0.3
s
l
1.0
1.3
1.5
s
Maximum Current Limit Duration
During Inrush
l
52
59
66
ms
Maximum Overcurrent Duration After
Inrush
l
52
59
66
ms
Maximum Overcurrent Duty Cycle
l
5.8
6.3
6.7
%
l
l
10
6
12
8
14
10
ms
ms
3.6
ms
380
ms
6.5
µs
3
s
From Power On Fault to Next Detect
Maximum Current Limit Duration After
Inrush
(Note 12)
Type 3, tLIMn = 8h
Type 4, tLIMn = 5h
tMPS
Maintain Power Signature (MPS) Pulse
Width Sensitivity
Current Pulse Width to Reset Disconnect Timer
(Note 8)
l
1.6
tDIS
Maintain Power Signature (MPS)
Dropout Time
(Note 5)
l
320
350
tMSD
Masked Shut Down Delay
l
1.5
2
Minimum Pulse Width for Masked Shut
Down
l
3
µs
Minimum Pulse Width for RESET
l
4.5
µs
tLIM
I2C Watchdog Timer Duration
I2C Timing (Note 7)
fSCLK
Clock Frequency
1
l
MHz
t1
Bus Free Time
Figure 5 (Note 9)
l
480
ns
t2
Start Hold Time
Figure 5 (Note 9)
l
240
ns
t3
SCL Low Time
Figure 5 (Note 9)
l
480
ns
t4
SCL High Time
Figure 5 (Note 9)
l
240
ns
t5
SDAIN Data Hold Time
Figure 5 (Note 9)
l
60
ns
t5
Data Clock to SDAOUT Valid
Figure 5 (Note 9)
l
t6
Data Set-Up Time
Figure 5 (Note 9)
l
80
ns
t7
Start Set-Up Time
Figure 5 (Note 9)
l
240
ns
t8
Stop Set-Up Time
Figure 5 (Note 9)
l
240
tr
SCL, SDAIN Rise Time
Figure 5 (Note 9)
l
tf
SCL, SDAIN Fall Time
Figure 5 (Note 9)
Fault Present to INT Pin Low
(Notes 9, 10)
Stop Condition to INT Pin Low
(Notes 9, 10)
6
130
ns
ns
120
ns
l
60
ns
l
150
ns
l
1.5
µs
Rev 0
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LTC4291-1/LTC4292
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AGNDP – VEE = 54V and VDD – DGND = 3.3V unless otherwise noted.
(Notes 3 and 4)
SYMBOL
PARAMETER
CONDITIONS
ARA to INT Pin High Time
(Note 9)
SCL Fall to ACK Low
(Note 9)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. With the exception of (VDD –
DGND), exposure to any Absolute Maximum Rating condition for extended
periods may affect device reliability and lifetime.
Note 2: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 140ºC when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 3: All currents into device pins are positive; all currents out of device
pins are negative.
Note 4: The LTC4292 operates with a negative supply voltage (with
respect to AGNDP). To avoid confusion, voltages in this data sheet are
referred to in terms of absolute magnitude.
Note 5: tDIS is the same as tMPDO defined by IEEE 802.3.
Note 6: The LTC4291-1 digital interface operates with respect to DGND. All
logic levels are measured with respect to DGND.
Note 7: Guaranteed by design, not subject to test.
Note 8: The IEEE 802.3 specification allows a PD to present its
Maintain Power Signature (MPS) on an intermittent basis without being
disconnected. In order to stay powered, the PD must present the MPS for
tMPS within any tMPDO time window.
MIN
TYP
MAX
UNITS
l
1.5
µs
l
130
ns
Note 9: Values Measured at VILD and VIHD.
Note 10: If a fault condition occurs during an I2C transaction, the INT pin
will not be pulled down until a stop condition is present on the I2C bus.
Note 11: Load characteristics of the LTC4292 during Mark: 7V <
(AGNDP – VOUTnM) < 10V or IOUTnM < 50µA.
Note 12: See the LTC4291 Software Programming documentation for
information on serial bus usage and device configuration and status
registers.
Note 13: Do not source or sink current from CAP1 and CAP2.
Note 14: For single-signature PDs, tPON is measured from end of valid
detect on either power channel. For dual-signature PDs, tPON is measured
from the end of valid detect on the same power channel.
Note 15: Port current and port power measurements depend on sense
resistor value (0.15Ω typical). See External Component Selection for
details.
Note 16: The full-scale range for each power channel is half of the port
full-scale range.
Note 17: See Inrush Control for details on inrush threshold selection.
Rev 0
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7
LTC4291-1/LTC4292
TYPICAL PERFORMANCE CHARACTERISTICS
802.3bt Single–Signature
802.3bt Single–Signature
Classification
andPower
Power
Classification and
On On
PowerOn
OnSequence
Sequence
Power
802.3bt Dual–Signature
Power
OnSequence
Sequence
Power On
0
0
0
CLASS 8
–10
–20
–30
CLASSIFICATION
–40
OUT1A
OUT1B
–50
POWER
ON
–20
–30
–40
OUT1A
OUT1B
802.3bt Single–Signature
Class
Probeand
andDemotion
Demotion
Class Probe
PROBE CLASS CLASS 3
CLASS 8 RESET DEMOTION
AGND
OUT1A
5V/DIV
POWER
ON
VEE
–60
42911 G04
30ms/DIV
POWER
ON
VEE
42911 G03
200ms/DIV
Classification Current Compliance
CLASSIFICATION VOLTAGE (V)
–20
–50
OUT1A
OUT1B
0
AGND
OUT1A
OUT1B
CLASSIFICATION
–40
Open Circuit Detection
OUT1B
5V/DIV
–40
–30
–60
42911 G02
CLASS 8
–30
DETECTION /
CONNECTION
CHECK
–20
–50
40ms/DIV
–10
CHANNEL VOLTAGE (V)
POWER
ON
VEE
–60
42911 G01
200ms/DIV
0
CLASSIFICATION
–50
VEE
–60
–10
CHANNEL VOLTAGE (V)
DETECTION /
CONNECTION
CHECK
CHANNEL VOLTAGE (V)
CHANNEL VOLTAGE (V)
–10
–8
–12
–16
–20
42911 G05
50ms/DIV
–4
0
10
20
30
40
50
60
CLASSIFICATION CURRENT (mA)
70
42911 G06
1333
175
150
200
1167
175
1000
150
175
1000
150
833
125
833
100
667
75
500
ILIM-2P (mA)
1167
ILIM–2P (mA)
125
CLASS 1 TO 3
CLASS 4
CLASS 5
RSENSE = 0.15Ω
1333
100
667
75
500
333
167
75
500
50
333
50
333
50
25
167
25
167
25
11
22
33
OUTnM – V EE (V)
44
55
0
42911 G07
8
0
0
11
22
33
OUTnM – VEE (V)
44
55
0
42911 G08
1000
833
667
0
1167
125
100
0
1333
LIMn = 80h
LIMn = 08h
RSENSE = 0.15Ω
0
0
11
22
33
OUTnM – V EE (V)
44
55
IINRUSH–2P (mA)
CLASS 1 TO 3
CLASS 4 TO 6
CLASS 7
CLASS 8
RSENSE = 0.15Ω
Inrush
CurrentLimits
Limits(Note
(Note
Inrush Current
17)17)
200
VLIM-2P (mV)
200
VLIM–2P (mV)
Power On Current Limits
Dual–Signature
Dual–Signature
VINRUSH–2P (mV)
Power On Current Limits
Single–Signature
0
42911 G09
Rev 0
For more information www.analog.com
LTC4291-1/LTC4292
TYPICAL PERFORMANCE CHARACTERISTICS
ILIM-2P
LIM–2P vs Temperature
1180
150
ICUT-2P
CUT–2P vs Temperature
1013
CUTn = 74h
RSENSE = 0.15Ω
1170
1160
174
173
993
148
973
146
144
1150
953
172
142
171
–40
–20
0
20
40
60
TEMPERATURE (°C)
1140
100
80
140
–40
–20
0
20
40
60
TEMPERATURE (°C)
80
42911 G10
5529
2446
5518
2441
5507
2436
5496
2431
2426
2416
5452
2411
5441
0
20
40
60
TEMPERATURE (°C)
80
5430
–40
100
1642
1630
1626
1622
1618
–20
0
20
40
60
TEMPERATURE (°C)
80
100
1614
–40
–20
0
20
40
60
TEMPERATURE (°C)
80
100
42911 G14
Temporary Short Circuit on
Channel 1B
Powering Up into 180µF Load
CHAN 1B
CURRENT
2A/DIV
OUT1A
20V/DIV
VEE
GATE1A
10V/DIV
1634
42911 G13
42911 G12
CHANNEL
CURRENT
200mA/DIV
AGNDP – VEE = 55V
SENSEnM – VSSKn = 151mV
1638
5474
5463
–20
1646
AGNDP – VEE = 55V
5485
2421
2406
–40
Power Readback ADC vs
Temperature
vs
Temperature
ADC CODE
5540
SENSEnM – VSSKn = 151mV
ADC CODE
ADC CODE
2451
933
100
42911 G11
Voltage Readback ADC vs
Temperature
Current Readback ADC vs
Temperature
2456
ICUT–2P (mA)
175
ILIM–2P (mA)
VLIM–2P (mV)
LIMn = E9h
RSENSE = 0.15Ω
176 OUTnM = V
EE
152
VCUT–2P (mV)
177
LOAD FULLY CHARGED
FOLDBACK
VEE
OUT1B
50V/DIV
CURRENT
LIMIT
OUT1A
50V/DIV
FET ON
5ms/DIV
GATE1B
10V/DIV
42911 G15
AGND
VEE
100µs/DIV
42911 G16
Rev 0
For more information www.analog.com
9
LTC4291-1/LTC4292
TYPICAL PERFORMANCE CHARACTERISTICS
9.5
IEE SUPPLY CURRENT (mA)
18
85°C
25°C
–40°C
9.0
8.5
8.0
7.5
7.0
6.5
6.0
16
15
14
13
12
11
5.5
5.0
85°C
25°C
–40°C
17
IDD SUPPLY CURRENT (mA)
10.0
VDD Supply Current vs
Temperature
VEE Supply Current vs Voltage
10
2.9
30 33 36 39 42 45 48 51 54 57 60
AGNDP – VEE (V)
3
3.1 3.2 3.3 3.4 3.5
VDD SUPPLY VOLTAGE (V)
42911 G017
3.6
42911 G18
TEST TIMING DIAGRAMS
CONNECTION
CHECK
DETECTION
TURN ON
CLASSIFICATION
tDET
FORCED-CURRENT
VOUTnM
FORCEDVOLTAGE
VOC
0V
2.8V
tME1
tME1
VMARK
tME2
15.5V
VCLASS
20.5V
tLCE
tLCE
tCEV
PD
CONNECTED
tCEV
tCEVON
tCLASS_RESET
VEE
tSTART
tPON
INT
42911 F01
Figure 1. Detect, Class and Turn-On Timing in Auto or Semi-Auto Modes
10
Rev 0
For more information www.analog.com
LTC4291-1/LTC4292
TEST TIMING DIAGRAMS
VLIM-2P
VCUT-2P
VSENSEnM TO VEE
0V
tSTART, tCUT
INT
42911 F02
Figure 2. Current Limit Timing
VSENSEnM
TO VEE
VMIN
INT
tMPS
tDIS
42911 F03
Figure 3. DC Disconnect Timing
VGATEnM
VEE
tMSD
MSD
42911 F04
Figure 4. Shut Down Delay Timing
t3
tr
t4
tf
SCL
t2
t5
t6
t7
t8
SDA
t1
42911 F05
Figure 5. I2C Interface Timing
Rev 0
For more information www.analog.com
11
LTC4291-1/LTC4292
I2C TIMING DIAGRAMS
SCL
SDA
0
1
0
AD3 AD2 AD1 AD0 R/W ACK A7
START BY
MASTER
A6
A5
A4
A3
A2
ACK BY
SLAVE
FRAME 1
SERIAL BUS ADDRESS BYTE
A0 ACK D7
A1
D6
D5
D4
D3
D2
ACK BY
SLAVE
D1
D0 ACK
STOP BY
MASTER
ACK BY
SLAVE
FRAME 2
REGISTER ADDRESS BYTE
FRAME 3
DATA BYTE
42911 F06
Figure 6. Writing to a Register
SCL
SDA
0
1
0
AD3 AD2 AD1 AD0 R/W ACK A7
START BY
MASTER
A6
A5
A4
A3
A2
ACK BY
SLAVE
FRAME 1
SERIAL BUS ADDRESS BYTE
A1
0
A0 ACK
ACK BY
SLAVE
1
0
AD3 AD2 AD1 AD0 R/W ACK D7
REPEATED
START BY MASTER
D6
D4
D3
ACK BY
SLAVE
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
REGISTER ADDRESS BYTE
D5
D2
D1
D0 ACK
NO ACK BY
MASTER
FRAME 2
DATA BYTE
STOP BY
MASTER
42911 F07
Figure 7. Reading from a Register
SCL
SDA
0
1
0
AD3 AD2 AD1 AD0 R/W ACK D7
START BY
MASTER
D6
D5
D4
D3
ACK BY
SLAVE
D2
D1
D0 ACK
STOP BY
MASTER
NO ACK BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
DATA BYTE
42911 F08
Figure 8. Reading the Interrupt Register (Short Form)
SCL
SDA
0
0
0
1
1
0
0
R/W ACK
START BY
MASTER
0
1
0
AD3 AD2 AD1 AD0
ACK BY
SLAVE
FRAME 1
ALERT RESPONSE ADDRESS BYTE
1
NO ACK BY
MASTER
FRAME 2
SERIAL BUS ADDRESS BYTE
ACK
STOP BY
MASTER
42911 F09
Figure 9. Reading from Alert Response Address
12
Rev 0
For more information www.analog.com
LTC4291-1/LTC4292
PIN FUNCTIONS
LTC4292
VEE (Pins 31, 33, 40, Exposed Pad Pin 41): Main PoE
Supply Input. Connect to a –51V to –57V supply, relative
to AGNDP. Voltage depends on PSE Type (Type 3 or 4).
GATEnM (Pins 1, 3, 7, 9, 22, 24, 28, 30): Gate Drive,
Port n, Channel M. Connect GATEnM to the gate of
the external MOSFET for port n, channel M. When the
MOSFET is turned on, the gate voltage is driven to
12V (typ) above VEE. During a current limit condition, the
voltage at GATEnM will be reduced to maintain constant
current through the external MOSFET. If the fault timer
expires, GATEnM is pulled down, turning the MOSFET off
and raising a port n fault event. If the channel is unused,
the GATEnM pin must be floated.
OUTnM (Pins 2, 4, 8, 10, 21, 23, 27, 29): Output Voltage
Monitor, Port n, Channel M. Connect OUTnM to the output
channel. A current limit foldback circuit limits the power
dissipation in the external MOSFET by reducing the current limit threshold when the drain-to-source voltage
exceeds 10V. The port n power good event is raised when
the voltage from OUTnM to VEE drops below 2.4V (typ).
A 500k resistor is connected internally from OUTnM to
AGNDP when the channel is idle. If the channel is unused,
the OUTnM pin must be floated.
AGNDP (Pin 25): Analog Ground. Connect AGNDP to the
return for the VEE supply through a 10Ω resistor.
DNA (Pin 36): Data Transceiver Negative Input Output
(Analog). Connect to DND through a data transformer.
DPA (Pin 37): Data Transceiver Positive Input Output
(Analog). Connect to DPD through a data transformer.
CNA (Pin 38): Clock Transceiver Negative Input Output
(Analog). Connect to CND through a data transformer.
CPA (Pin 39): Clock Transceiver Positive Input Output
(Analog). Connect to CPD through a data transformer.
VSSK12 (Pin 5): Kelvin Sense to VEE. Connect to sense
resistor common node for ports 1 and 2 through a 0.15Ω
resistor. Connect to AGNDP through a 0.22μF, 100V
capacitor. Do not connect directly to VEE plane. See Layout
Requirements.
VSSK34 (Pin 26): Kelvin Sense to VEE. Connect to sense
resistor common node for ports 3 and 4 through a 0.15Ω
resistor. Connect to AGNDP through a 0.22μF, 100V
capacitor. Do not connect directly to VEE plane. See Layout
Requirements.
Common Pins
CAP2 (Pin 6): Analog Internal 4.3V Power Supply Bypass
Capacitor. Connect a 0.22µF ceramic cap to VEE.
NC, DNC (LTC4291-1 Pins 7, 13; LTC4292 Pins 32, 34,
35): All pins identified with “NC” or “DNC” must be left
unconnected.
PWRMDn (Pins 11, 20): Maximum Power Mode Input.
Logic input signals between VEE and VEE + 4.3V for configuration of maximum output power per-port in auto mode.
See Auto Mode Maximum PSE Power section. Internally
pulled up to CAP2.
LTC4291-1
AD0 (Pin 1): Address Bit 0. Tie the address pins high or
low to set the I2C serial address to which the LTC4291-1
responds. The address will be (010A3A2A1A0)b. Internally
pulled up to VDD.
SENSEnM (Pins 12, 13, 14, 15, 16, 17, 18, 19): Current
Sense Input, Port n, Channel M. SENSEnM monitors
the external MOSFET current via a 0.15Ω sense resistor
between SENSEnM and VSSKn. Whenever the voltage
across the sense resistor exceeds the overcurrent detection
threshold VCUT-2P, the current limit fault timer counts up. If
the voltage across the sense resistor reaches the current
limit threshold VLIM-2P, the GATEnM pin voltage is lowered
to maintain constant current in the external MOSFET. See
Applications Information for further details. If the channel
is unused, the SENSEnM pin must be tied to VEE.
AD1 (Pin 2): Address Bit 1. See AD0.
AD2 (Pin 3): Address Bit 2. See AD0.
AD3 (Pin 4): Address Bit 3. See AD0.
4PVALID (Pin 6): 4-Pair Valid Input, Active Low. When
low, the LTC4291-1/LTC4292 will not apply power to a
port unless both pairsets present a valid signature. When
high, the LTC4291-1/LTC4292 will power any pairset presenting a valid signature, regardless of the other pairset.
Internally pulled down to DGND.
Rev 0
For more information www.analog.com
13
LTC4291-1/LTC4292
PIN FUNCTIONS
CPD (Pin 8): Clock Transceiver Positive Input Output
(Digital). Connect to CPA through a data transformer.
CND (Pin 9): Clock Transceiver Negative Input Output
(Digital). Connect to CNA through a data transformer.
DPD (Pin 10): Data Transceiver Positive Input Output
(Digital). Connect to DPA through a data transformer.
DND (Pin 11): Data Transceiver Negative Input Output
(Digital). Connect to DNA through a data transformer.
VDD (Pins 12, 20): VDD IO Power Supply. Connect to
a 3.3V power supply relative to DGND. VDD must be
bypassed to DGND near the LTC4291-1 with at least a
0.1μF capacitor.
RESET (Pin 14): Reset Input, Active Low. When RESET is
low, the LTC4291-1/LTC4292 is held inactive with all ports
off and all internal registers reset. When RESET is pulled
high, the LTC4291-1/LTC4292 begins normal operation.
RESET can be connected to an external capacitor or RC
network to provide a power turn-on delay. Internal filtering
of RESET prevents glitches less than 1μs wide from resetting the LTC4291-1/LTC4292. Internally pulled up to VDD.
INT (Pin 15): Interrupt Output, Open Drain. INT will pull
low when any one of several events occur in the LTC42911. It will return to a high impedance state when bits 6 or
7 are set in the Reset PB register (1Ah). The INT signal
can be used to generate an interrupt to the host processor, eliminating the need for continuous software polling.
Individual INT events can be disabled using the INT Mask
register (01h). See LTC4291 Software Programming
documentation for more information. INT is only updated
between I2C transactions.
SDAOUT (Pin 16): Serial Data Output, Open Drain Data
Output for the I2C Serial Interface Bus. The LTC4291-1
uses two pins to implement the bidirectional SDA function to simplify opto isolation of the I2C bus. To implement a standard bidirectional SDA pin, tie SDAOUT and
SDAIN together. See Applications Information for more
information.
14
SDAIN (Pin 17): Serial Data Input. High impedance data
input for the I2C serial interface bus. The LTC4291-1
uses two pins to implement the bidirectional SDA function to simplify opto isolation of the I2C bus. To implement a standard bidirectional SDA pin, tie SDAOUT and
SDAIN together. See Applications Information for more
information.
SCL (Pin 18): Serial Clock Input. High impedance clock
input for the I2C serial interface bus. The SCL pin should
be connected directly to the I2C SCL bus line. SCL must
be tied high if the I2C serial interface bus is not used.
CAP1 (Pin 19): Core Power Supply Bypass Capacitor.
Connect a 1µF capacitance to DGND for the internal 1.8V
regulator bypass. Do not use other capacitor values.
AUTO (Pin 21): Auto Mode Input, Active High. When high,
the LTC4291-1 detects, classifies and powers up valid
PDs without host interaction. AUTO determines the state
of the internal registers when the LTC4291-1 is reset or
comes out of UVLO (see LTC4291 Software Programming
documentation). The state of these register bits can subsequently be changed via the I2C interface. Internally
pulled down to DGND.
GP1 (Pin 22): General Purpose Digital Input Output for
customer applications. Referenced to DGND.
GP0 (Pin 23): General Purpose Digital Input Output for
customer applications. Referenced to DGND.
MSD (Pin 24): Maskable Shutdown Input, Active Low.
When pulled low, all ports that have their corresponding
mask bit set in the mconf register (17h) will be reset.
Internal filtering of the MSD pin prevents glitches less
than 1μs wide from resetting ports. The MSD Pin Mode
register can configure the MSD pin polarity. Internally
pulled up to VDD.
DGND (Pin 5, Exposed Pad Pin 25): Digital Ground. DGND
should be connected to the return from the VDD supply.
Rev 0
For more information www.analog.com
LTC4291-1/LTC4292
APPLICATIONS INFORMATION
OVERVIEW
Power over Ethernet, or PoE, is a standard protocol for
sending DC power over copper Ethernet data wiring.
The IEEE group that administers the 802.3 Ethernet data
standards added PoE powering capability in 2003. This
original PoE standard, known as 802.3af, allowed for 48V
DC power at up to 13W. 802.3af was widely popular, but
13W was not adequate for some applications. In 2009,
the IEEE released a new standard, known as 802.3at or
PoE+, increasing the voltage and current requirements to
provide 25.5W of delivered power.
The IEEE standard also defines PoE terminology. A device
that provides power to the network is known as a PSE,
or power sourcing equipment, while a device that draws
power from the network is known as a PD, or powered
device. PSEs come in two types: Endpoints (typically network switches or routers), which provide data and power;
and Midspans, which provide power but pass through
data. Midspans are typically used to add PoE capability to existing non-PoE networks. PDs are typically IP
phones, wireless access points, security cameras, and
similar devices.
PoE++ Evolution
Even during the development of the IEEE 802.3at (PoE+)
25.5W standard, it became clear there was a significant
and increasing need for more than 25.5W of delivered
power. In 2013, the 802.3bt task force was formed to
develop a standard capable of increasing delivered PD
power.
The primary objective of the task force is to use all four
pairs of the Ethernet cable as opposed to the two pair
power utilized by 802.3at. Using all four pairs allows for
at least twice the delivered power over existing Ethernet
cables. Further, the amount of current per two pairs
(known as a pairset) has been increased while maintaining the Ethernet data signal integrity. 802.3bt increases
PD delivered power from 25.5W to 71.3W, enabling IEEEcompliant high power PD applications.
The LTC4291-1/LTC4292 delivers power over two power
channels. Each pairset is driven by a dedicated power
channel. In this data sheet, the term “channel” refers to
the PSE circuitry assigned to a corresponding pairset. For
the purposes of this document, the terms channel and
pairset may be considered interchangeable.
In addition, IEEE 802.3bt enables substantially lower
Maintain Power Signature (MPS) currents, resulting in
significantly lower standby power consumption. This
allows new and emerging government or industry standby
regulations to be met using standard PoE components.
LTC4291-1/LTC4292 Product Overview
The LTC4291-1/LTC4292 is a fifth generation PSE controller that implements four PSE ports in either an Endpoint
or Midspan application. Virtually all necessary circuitry
is included to implement an IEEE 802.3bt compliant PSE
design, requiring a pair of external power MOSFETs and
sense resistors per port; these minimize power loss compared to alternative designs with onboard MOSFETs, and
increase system reliability.
The LTC4291-1/LTC4292 chipset implements a proprietary isolation scheme for inter-chip communication. This
architecture substantially reduces BOM cost by replacing
expensive opto-isolators and isolated power supplies with
a single low-cost transformer.
The LTC4291-1/LTC4292 offers advanced fifth generation PSE features including a configurable interrupt signal triggered by per-port events, per-channel power on
control and fault telemetry, per-port current monitoring,
VEE monitoring, one second rolling current, voltage, and
port power averaging, and two general purpose input/
output pins.
Rev 0
For more information www.analog.com
15
LTC4291-1/LTC4292
APPLICATIONS INFORMATION
VEE and port current measurements are performed simultaneously, providing fully coherent port power calculations. The reported port power calculations enable coherent and precise per-port power monitoring.
PoE BASICS
PD presents the same valid signature resistor to both
pairsets simultaneously. A dual-signature PD presents two fully independent valid detection signatures,
one to each pairset.
n
Common Ethernet data connections consist of two or
four twisted pairs of copper wire (commonly known
as Ethernet cable), transformer-coupled at each end to
avoid ground loops. PoE systems take advantage of this
coupling arrangement by applying voltage between the
center-taps of the data transformers to transmit power
from the PSE to the PD without affecting data transmission. Figures 10 and 11 show high level PoE system
schematics.
To avoid damaging legacy data equipment that does not
expect to see DC voltage, the PoE standard defines a
protocol that determines when the PSE may apply and
remove power. Valid PDs are required to have a specific
25k common-mode resistance at their input. When such
a PD is connected to the cable, the PSE detects this signature resistance and applies power. When the PD is
later disconnected, the PSE senses the open circuit and
removes power. The PSE also removes power in the event
of a current fault or short circuit.
When a PD is detected, the PSE looks for a classification
signature that tells the PSE the maximum power the PD
will draw. The PSE can use this information to allocate
power among several ports, to police the current consumption of the PD, or to reject a PD that will draw more
power than the PSE has available.
n
n
n
n
n
n
n
New in 802.3bt
The 802.3bt draft introduces several new features:
n
n
n
Type 3 and Type 4 PSEs may provide power over all
four pairs (both pairsets), depending on connected
PD characteristics.
Type 3 and Type 4 PDs are required to be capable of
receiving power over all four pairs (both pairsets).
Type 3 and 4 PDs can be formed as either a singlesignature PD or dual-signature PD. A single-signature
16
n
Type 3 single-signature PDs request exactly one of six
possible power levels: 3.84W, 6.49W, 13W, 25.5W,
40W, or 51W.
Type 3 dual-signature PDs request exactly one of four
possible power levels on each pairset: 3.84W, 6.49W,
13W, or 25.5W. The total PD requested power is the
sum of the requested power on both pairsets.
Type 3 PD Classes overlap with Type 1 and 2 Classes
in order to provide additional Type 3 feature sets at
lower power levels.
Type 4 single-signature PDs request exactly one of
two possible power levels: 62W or 71.3W.
Type 4 dual-signature PDs request exactly 35.6W on
at least one pairset and one of five possible power levels on the other pairset: 3.84W, 6.49W, 13W, 25.5W,
or 35.6W. The total PD requested power is the sum
of the requested power on both pairsets.
Classification is extended to a possible maximum
of five class events. The additional events allow for
unique identification of existing and new PD Classes.
Type 3 and 4 PSEs issue a long first class event to
advertise Type 3 and 4 feature support to attached PDs.
Lower standby power is enabled by shortening the
length of the maintain power signature pulse (short
MPS). The PD duty cycle drops from ~23% to ~2%. A
PD is allowed to present short MPS if the PSE issues
a long first class event.
Power management is augmented by Autoclass, an
optional feature for 802.3bt PSEs and PDs. In an
Autoclass system the maximum PD power is measured and reported to the PSE host, enabling the PSE
to reclaim output power not used by the PD application and losses in the Ethernet cabling (Table 1).
See Autoclass section and LTC4291 Software
Programming documentation for details.
Rev 0
For more information www.analog.com
LTC4291-1/LTC4292
APPLICATIONS INFORMATION
1
AGNDP
1
TX1
TX1
2
2
DATA PAIRS
3
GATEnA
I2C
3
–54V TX2
1/4
LTC4291-1/LTC4292
TX2
6
6
4
4
TX3
+
PD
VOUT
PD1
VOUT
PD2
VOUT
–
TX3
5
5
DATA PAIRS
7
GATEnB
7
–54V TX4
TX4
8
VEE
42911 F10
1000BASE-T
8
RJ45
RJ45
1000BASE-T
–54V
Figure 10. Power over Ethernet Single-Signature PD System Diagram
1
AGNDP
1
TX1
2
3
GATEnA
I2C
2
DATA PAIRS
TX2
6
6
4
4
TX3
7
5
DATA PAIRS
TX4
8
42911 F11
1000BASE-T
–
7
–54V TX4
VEE
+
TX3
5
GATEnB
–
3
–54V TX2
1/4
LTC4291-1/LTC4292
+
TX1
RJ45
8
RJ45
1000BASE-T
–54V
Figure 11. Power over Ethernet Dual-Signature PD System Diagram
Rev 0
For more information www.analog.com
17
LTC4291-1/LTC4292
APPLICATIONS INFORMATION
Table 1. IEEE-Specified Power Allocations, Single-Signature PD
PD CLASS
PSE OUTPUT
POWER
ALLOCATED
CABLING LOSS
PD INPUT
POWER
1
4W
0.16W
3.84W
2
6.7W
0.21W
6.49W
3
14W
1W
13W
4
30W
4.5W
25.5W
5
45W
5W
40W
6
60W
9W
51W
7
75W
13W
62W
8
90W
18.7W
71.3W
Special Compatibility Mode Notes
n
n
n
As with prior generations, each I2C address provides
status and control for four PoE ports. Each port register slice provides port control and status as well as
channel A vs B control and status.
Certain status registers, e.g. Port Status and Power
Status, relate to a channel state, as opposed to port
state and are split into three copies; a generalized port
state, channel A state and channel B state.
Certain command registers, e.g., Power-on pushbutton,
likewise are bifurcated to allow per-channel control.
BACKWARD COMPATIBILITY
The LTC4291-1/LTC4292 may be configured as an
802.3bt-compliant PSE, either Type 3 or Type 4. While
802.3bt PSEs cannot identify as an 802.3at Type 1 or
Type 2 PSE, there is no loss in PSE functionality; all
802.3bt-compliant PSEs are fully backwards compatible
with existing 802.3at Type 1 and Type 2 PDs as shown
in Table 2. In addition to full compatibility, 802.3bt PSEs
extend support for lower standby power, enhanced current limit timing, and dynamic power management to all
PD Types (as supported by the PD application).
Table 3. Operating Modes
MODE
802.3at
PD
802.3bt
AUTO
DETECT/
PIN OPMD CLASS
802.3at
802.3bt
TYPE
1
2
3
4
1
13W
13W
13W
13W
2
13W*
25.5W
25.5W
25.5W
3
13W*
25.5W*
51W
51W
4
13W*
25.5W*
51W*
71.3W
*Indicates PD allocated less power than requested.
Software register map compatibility with LTC4266 and
LTC4271-based PSEs has been maintained to the extent
possible. LTC4291-based PSEs utilize two channels to
control a single PSE port. This multiplicity of channel
status and control requires extensions to the existing
register map.
For register map details please contact Analog Devices
to request the LTC4291 Software Programming
documentation.
POWER-UP
AUTOMATIC
THRESHOLD
ASSIGNMENT
1
11b
Enabled
at Reset
Automatically
Yes
0
11b
Host
Enabled
Automatically
Yes
Semi-auto
0
10b
Host
Enabled
Upon Request
No
Manual
0
01b
Once
Upon
Request
Upon Request
No
Shutdown
0
00b
Disabled
Disabled
No
PSE
STANDARD
18
The LTC4291-1/LTC4292 includes four independent
ports, each of which can operate in one of three modes:
manual, semi-auto, or auto. A fourth mode, shutdown,
disables the port (see Table 3).
Auto
Table 2. PSE Maximum Delivered Power, Per-Port
DEVICE
OPERATING MODES
In manual mode, the port waits for instructions from the
host system before taking any action. It runs a single
detection, or detection and classification cycle when commanded to by the host, and reports the result in its Port
Status register. The host system can command the port
to apply or remove power at any time.
In semi-auto mode, the port repeatedly attempts to detect
and classify any PD attached to it. It reports the status of
these attempts back to the host, and waits for a command
from the host before applying power to the port. The host
must enable detection and classification.
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Auto mode operates the same as semi-auto mode except
it will automatically apply power to the port if detection and classification are successful. Auto mode will
autonomously set the ICUT-2P, ILIM-2P, and PCUT-4P values
based on the Class result. This operational mode may
be entered by setting AUTO high at reset or by changing
the OPMD state to Auto. See Auto Mode Maximum PSE
Power section.
In shutdown mode the port is disabled and will not detect
or power a PD.
Regardless of which mode it is in, the LTC4291-1/
LTC4292 will remove power automatically from any port
and/or channel, as appropriate, that generates a fault. It
will also automatically remove power from any port/channel that generates a disconnect event if disconnect detection is enabled. The host controller may also command
the port to remove power at any time.
Reset and the AUTO Pin
The initial LTC4291-1/LTC4292 configuration depends on
the state of AUTO during reset. Reset occurs at power-up,
whenever RESET is pulled low, or when the global Reset
All bit is set. Changing the state of AUTO after powerup will not change the port behavior of the LTC4291-1/
LTC4292 until a reset occurs.
Although typically actively managed by a host controller,
the LTC4291-1/LTC4292 may alternatively be configured
for autonomous operation by setting AUTO high. With
AUTO high, each port will detect and classify repeatedly
until a PD is discovered, set ICUT-2P, ILIM-2P, and PCUT-4P
according to the PSE assigned Class, apply power to valid
PDs, and remove power when a PD is disconnected.
Tables 4 and 5 show the ICUT-2P, ILIM-2P, and PCUT-4P values that will be automatically set in auto mode, based on
the PD requested Class.
Table 4. Typical Auto Mode Power On Thresholds,
Single‑Signature PD
PER-CHANNEL
PER-PORT
CLASS
ICUT-2P
ILIM-2P
PCUT-4P
1
94mA
425mA
5.43W
2
150mA
425mA
8.69W
3
338mA
425mA
19.5W
4
638mA
850mA
36.4W
5
581mA
850mA
52.7W
6
731mA
850mA
70.0W
7
825mA
1063mA
87.4W
8
975mA
1167mA
96.6W
Table 5. Typical Auto Mode Power On Thresholds,
Dual‑Signature PD
PER-CHANNEL
CLASS
ICUT-2P
ILIM-2P
PCUT-2P*
1
94mA
425mA
5.43W
2
150mA
425mA
8.69W
3
338mA
425mA
19.5W
4
638mA
850mA
36.4W
5
975mA
1167mA
48.3W
*A per-port PCUT-4P threshold holds the sum of PCUT-2P for each
powered channel.
CONNECTION CHECK
Connection Check Overview
IEEE 802.3bt introduces a new detection subroutine known
as connection check. A connection check is required to
determine whether the attached PD is a single-signature
PD, a dual-signature PD or an invalid result.
In 802.3at, only one PD configuration was described;
this is known as a single-signature PD and is shown in
Figure 10. A single-signature PD presents the same 25k
detection resistor to both the pairsets in parallel.
New in 802.3bt is the dual-signature PD as shown in
Figure 11. A dual-signature PD presents two fully independent 25k detection signature resistors, one to each pairset.
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LTC4291-1/LTC4292
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The PD configuration (single or dual) determines how the
PD is managed during subsequent detection, classification and power on procedures. Throughout the remainder
of this data sheet attention will be called to the different
treatment of single-signature and dual-signature PDs.
Multipoint Detection
Connection check is performed with two current measurements, at the same forced voltage, on the first channel.
The second channel is tested for aggressor behavior by
introducing a forced current on the second channel during
the second measurement. Comparison of the two resulting current measurements on the first channel allows
for the connected device to be categorized as a singlesignature PD, a dual-signature PD, or an invalid result.
Initially, two test currents are forced onto the channel (via
the OUTnM pin) and the resulting voltages are measured.
The detection circuitry subtracts the two V-I points to
determine the resistive slope while removing offset caused
by series diodes or leakage at the port (see Figure 13). If
the forced current detection yields a valid signature resistance, two test voltages are then forced onto the channel
and the resulting currents are measured and subtracted.
Both methods must report valid resistances to report a
valid detection. PD signature resistances between 17k
and 29k (typically) are detected as valid and reported as
Detect Good in the corresponding Port Status register or
Channel Status register, as appropriate. Values outside
this range, including open and short circuits, are also
reported. If the channel measures less than 1V during
any forced current test, the detection cycle will abort and
Short Circuit will be reported. Tables 6 and 7 show the
possible detection results.
DETECTION
Detection Overview
To avoid damaging network devices that were not designed
to tolerate DC voltage, a PSE must determine whether the
connected device is a valid PD before applying power.
The IEEE specification requires that a valid PD have a
common-mode resistance of 25k ±5% at any channel
voltage below 10V. The PSE must accept resistances that
fall between 19k and 26.5k, and it must reject resistances
above 33k or below 15k (shaded regions in Figure 12).
The PSE may choose to accept or reject resistances in
the undefined areas between the must-accept and mustreject ranges. In particular, the PSE must reject standard
computer Network Interface Cards (NICs), many of which
have 150Ω common-mode termination resistors that will
be damaged if power is applied to them (the black region
at the left of Figure 12).
RESISTANCE 0Ω
PD
PSE
10k
20k
150Ω (NIC)
15k
240
CURRENT (µA)
An invalid connection check result is reported when a
device is added or removed during connection check.
The LTC4291-1/LTC4292 uses a multipoint method to
detect PDs. False-positive detections are minimized by
checking for signature resistance with both forced current
and forced voltage measurements.
25kΩ SLOPE
160
23.75k
26.25k
26.5k
0V-2V
OFFSET
SECOND
DETECTION
POINT
VOLTAGE
42911 F13
Figure 13. PD Detection
30k
19k
VALID PD
FIRST
DETECTION
POINT
33k
42911 F12
Figure 12. IEEE 802.3 Signature Resistance Ranges
20
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Table 6. Port Detection Status
MEASURED PD SIGNATURE
(TYPICAL)
PORT DETECTION RESULT
Incomplete or Not Yet Tested
Detect Status Unknown
VPD < 1V
Short Circuit
RPD < 17k
RSIG Too Low
17k < RPD < 29k
Detect Good, Single-Signature PD
RPD > 29k
RSIG Too High
RPD > 50k
Open Circuit
VPD > 10V
Port Voltage Outside Detect Range
Connection Check = INVALID
Connection Check Invalid
Connection Check = DUAL or
Channel Detection Results Differ
Refer to Channel Detect Results
Table 7. Channel Detection Status
MEASURED PD SIGNATURE
(TYPICAL)
CHANNEL DETECTION RESULT
Incomplete or Not Yet Tested
Detect Status Unknown
VPD < 1V
Short Circuit
CPD > 2.7μF
CPD Too High
RPD < 17k
RSIG Too Low
17k < RPD < 29k
Detect Good, Dual-Signature PD
RPD > 29k
RSIG Too High
RPD > 50k
Open Circuit
VPD > 10V
Channel Voltage Outside Detect Range
Connection Check = INVALID
Connection Check Invalid
Connection Check = SINGLE or
Channel Detection Results Match
Refer to Port Detect Result
the PD and report that result as well. The port will then
wait for at least 100ms, and will repeat the detection cycle
to refresh the data in the Port Status registers.
The port will not turn on in response to a power-on command unless the current detect result is Detect Good. Any
other detect result will generate a tSTART fault if a power-on
command is received.
Behavior in auto mode is similar to semi-auto; however,
after Detect Good is reported and the port is classified, it
is automatically powered on without host intervention. In
auto mode the ICUT-2P, ILIM-2P, and PCUT-4P thresholds are
automatically set; see the Reset and the AUTO Pin section
for more information.
Detection is disabled for a port when the LTC4291-1/
LTC4292 is initially powered up with AUTO low, when
the port is in shutdown mode, or when the corresponding
Detect Enable bit is cleared.
Detection of Legacy PDs
More on Operating Modes
The port’s operating mode determines when the
LTC4291-1/LTC4292 runs a detection cycle. In manual
mode, the port will idle until the host orders a detect cycle.
It will then run detection, report the result, and return to
idle to wait for another command.
In semi-auto mode the LTC4291-1/LTC4292 autonomously polls a port for PDs, but it will not apply power
until commanded to do so by the host. The Port Status
and Channel Status registers are updated at the end of
each detection/classification cycle.
In semi-auto mode, if a valid signature resistance is
detected and classification is enabled, the port will classify
Proprietary PDs that predate the original IEEE 802.3af
standard are commonly referred to today as legacy PDs.
One type of legacy PD uses a large common-mode capacitance (>10μF) as the detection signature. Note that PDs in
this range of capacitance are defined as invalid, so a PSE
that powers legacy PDs is noncompliant with the IEEE
standard. The LTC4291-1/LTC4292 can be configured to
detect this type of legacy PD. Legacy detection is disabled
by default, but can be manually enabled on a per-port
basis. When enabled, the port will report Detect Good
when it sees either a valid IEEE PD or a high-capacitance
legacy PD. With legacy mode disabled, only valid IEEE
PDs will be recognized.
If a nonstandard PD presents an invalid detection signature not included by legacy detection, the LTC4291-1/
LTC4292 may be configured to perform classification and/
or apply power regardless of detection result. To accomplish this, the LTC4291-1/LTC4292 introduces per-port
Force Power and Class Event overrides. These overrides
intentionally defeat compliance checks. See the LTC4291
Software Programming documentation for details.
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LTC4291-1/LTC4292
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Table 8. Type 1 and Type 2 PD Classification Values
Classification
802.3af Classification
A PD may optionally present a classification signature
to the PSE to indicate the maximum power it will draw
while operating. The IEEE specification defines this signature as a constant current draw when the PSE port
voltage is in the VCLASS range (between 15.5V and 20.5V)
as shown in Figure 15, with the current level indicating
one of five possible PD signatures. Figure 14 shows a
typical PD load line, starting with the slope of the 25k
signature resistor below 10V, then transitioning to the
classification signature current (in this case, Class 3)
in the VCLASS range. Table 8 shows the possible classification values.
60
PSE LOAD LINE
OVER
CURRENT
50
CURRENT (mA)
CLASS 4
30
CLASS 3
TYPICAL
CLASS 3
PD LOAD
LINE
10
33mA
0
5
CLASS 1
CLASS 0
10
15
VOLTAGE (VCLASS)
14.5mA
3.84W
Class 2
6.49W
Class 3
13W
Class 4
25.5W (Type 2)
If classification is enabled, the PSE will classify the PD
immediately after a successful detection cycle. The PSE
measures the PD classification signature by applying
VCLASS to the port via OUTnM and measuring the resulting current; it then reports the discovered class in the Port
Status or Channel Status register, as appropriate. If the
LTC4291-1/LTC4292 is in auto mode, it will additionally
use the classification result to set the ICUT-2P, ILIM-2P, and
PCUT-4P thresholds.
Introduced in 802.3at and extended by 802.3bt, the PoE
specification defines a Link Layer Discovery Protocol
(LLDP) method of classification. The LLDP method adds
extra fields to the Ethernet LLDP data protocol.
6.5mA
25
20
42911 F14
POWER ON
CLASS
VOUTnM
No Class Signature Present; Treat Like Class 3
Class 1
LLDP Classification
CLASS 2
Figure 14. PD Classification
VCLASSMIN
VMARKMAX
DETECT
VSIGMIN
Although the LTC4291-1/LTC4292 is compatible with this
classification method, it cannot perform LLDP classification directly since it does not have access to the data path.
LLDP classification allows the host to perform LLDP communication with the PD and update the PD’s power allocation. The LTC4291-1/LTC4292 supports changing the
ILIM-2P, ICUT-2P, and PCUT-4P levels dynamically, enabling
system-level LLDP support.
802.3at 2-Event Classification
VRESET
42911 F15
Figure 15. Type 1 PSE, 1-Event Class Sequence
22
Class 0
23mA
20
0
RESULT
Classification is disabled for a port when the LTC4291-1/
LTC4292 is initially powered up with the AUTO pin low,
when the port is in shutdown mode, or when the corresponding Class Enable bit is cleared.
48mA
40
CLASS
In 802.3at, 802.3af classification is named Type 1 classification. The 802.3at standard introduces an extension
of Type 1 classification: Type 2 (2-event) classification.
Type 2 PSEs are required to perform classification.
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A Type 2 PD requesting 25.5W presents class signature 4
during all class events. If a Type 2 PSE with 25.5W of
available power sees class signature 4 during the first
class event, it forces the PD to VMARK (9V typical), pauses
briefly, and issues a second class event as shown in
Figure 16. The second class event informs the PD that
the PSE has allocated 25.5W.
POWER ON
VOUTnM
1ST
CLASS
VRESET
IEEE 802.3bt defines eight PD Classes for single-signature
PDs and five PD Classes for dual-signature PDs, as shown
in Table 9.
Classification treatment of single-signature and dualsignature PDs differs. The following sections explain the
Physical Layer classification of each PD configuration
separately.
2ND
CLASS
VCLASSMIN
VMARKMAX
classification supersede Type 1 and Type 2 classification. Type 1 and Type 2 classification are described in
the preceding sections as a historical reference and to
define common terminology such as power demotion,
class events, mark events, and electrical parameters.
DETECT
Table 9. Type 3 and Type 4 PD Classifications by PD Configuration
1ST
MARK
VSIGMIN
SINGLE-SIGNATURE PDs
2ND
MARK
42911 F16
Figure 16. Type 2 PSE, 2-Event Class Sequence
Note that the second classification event only runs if
required by the IEEE classification procedure. For example, a single-signature Class 0 to 3 PD will only be issued
a single class event in all situations.
The concept of demotion is introduced in 802.3at. A
Type 2 PD may be connected to a PSE only capable of
delivering 13W, perhaps due to power management limitations. In this case, the PSE will perform a single classification event as shown in Figure 15, and note that 25.5W
is requested. Due to the limited power availability, the
PSE will not issue a second event and proceeds directly
to power on the PD. The presence of a single class event
informs the Type 2 PD it has been demoted to 13W. If
demoted, the PD is subject to power limitations and may
operate in a reduced power mode.
802.3bt Multi-Event Classification
The LTC4291-1/LTC4292 implements Type 3 and Type 4
classification, as required by 802.3bt. Type 3 and Type 4
classification are backwards-compatible with Type 1 and
Type 2 PDs.
While Type 2 (802.3at) classification extends Type 1
(802.3af) classification, Type 3 and Type 4 (802.3bt)
CLASS
PD AVAILABLE
POWER
DUAL-SIGNATURE PDs
CLASS
CHANNEL AVAILABLE
POWER*
Class 1
3.84W
Class 1
3.84W
Class 2
6.49W
Class 2
6.49W
Class 3
13W
Class 3
13W
Class 4
25.5W
Class 4
25.5W
Class 5
40W
Class 5
35.6W
Class 6
51W
Class 7
62W
Class 8
71.3W
*Dual-signature PD total available power is the sum of both channels
available power. Class signatures may differ between channels of a port,
e.g., Class 3 + Class 4 = 13W + 25.5W = 38.5W.
802.3bt Classification of Single-Signature PDs
Type 3 and Type 4 PSEs issue a single classification event
(see Figure 17) to Class 0 through 3 single-signature (SS)
PDs. A Class 0 through 3 SS PD presents its class signature to the PSE and is then powered on if sufficient power
is available. Power limited 802.3bt PSEs may also issue a
single classification event to Class 4 and higher SS PDs in
order to demote those PDs to 13W. See Figure 17.
Type 3 and 4 PSEs present three classification events
to Class 4 SS PDs (see Figure 18) if sufficient power is
available. Class 4 SS PDs present class signature 4 on
all events. The third event differentiates a Class 4 SS PD
from a higher Class SS PD. Power limited IEEE 802.3bt
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POWER ON
POWER ON
1ST
CLASS
VOUTnM
VOUTnM
1ST
CLASS
VCLASSMIN
VMARKMAX
1ST
MARK
VRESET
4TH
CLASS
DETECT
1ST
MARK
VRESET
VSIGMIN
3RD
CLASS
VCLASSMIN
VMARKMAX
DETECT
2ND
CLASS
2ND
MARK
3RD
MARK
4TH
MARK
VSIGMIN
42911 F17
Figure 17. Type 3 or 4 PSE, 1-Event Class Sequence
42911 F19
Figure 19. Type 3 or 4 PSE, 4-Event Class Sequence
POWER ON
2ND
CLASS
3RD
CLASS
1ST
CLASS
VCLASSMIN
VMARKMAX
VRESET
VSIGMIN
VOUTnM
VOUTnM
1ST
CLASS
1ST
MARK
2ND
MARK
3RD
MARK
VRESET
42911 F18
PSEs may issue three classification events to Class 5 and
higher SS PDs in order to demote those PDs to 25.5W.
Type 3 and 4 PSEs present four classification events (see
Figure 19) to Class 5 and 6 SS PDs if sufficient power is
available. Class 5 and 6 SS PDs present class signature
4 on the first two events. Class 5 and 6 SS PDs present
class signature 0 or 1, respectively, on the subsequent
events. Power limited PSEs may issue four events to Class
7 and 8 SS PDs in order to demote those PDs to 51W.
Type 4 PSEs present five classification events (see
Figure 20) to Class 7 and 8 SS PDs if sufficient power
is available. Class 7 and 8 PDs present class signature
4 on the first two events. Class 7 and 8 SS PDs present
class signature 2 or 3, respectively, on the subsequent
events.
2ND
CLASS
3RD
CLASS
4TH
CLASS
5TH
CLASS
VCLASSMIN
VMARKMAX
DETECT
Figure 18. Type 3 or 4 PSE, 3-Event Class Sequence
24
POWER ON
DETECT
1ST
MARK
2ND
MARK
3RD
MARK
4TH
MARK
5TH
MARK
VSIGMIN
42911 F20
Figure 20. Type 4 PSE, 5-Event Class Sequence
802.3bt Classification of Dual-Signature PDs
Classification and power allocations to each pairset of a
dual-signature (DS) PD are fully independent. For example, a DS PD may request Class 1 (3.84W) on one pairset
and a Class 4 (25.5W) on the second pairset for a total
PD requested power of 29.3W. As such, all classification
is performed to the pairset entity as opposed to the PD.
The terms should be considered interchangeable for the
remainder of this section.
Type 3 and Type 4 PSEs issue three classification events
(see Figure 18) to all Class 1 through 4 DS PDs.
Power limited Type 3 and Type 4 PSEs may issue a class
reset to Class 4 and 5 DS PDs in order to demote those
PDs to 13W (see Understanding 4PID section).
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Power limited Type 3 and Type 4 PSEs may issue only
three events to Class 5 DS PDs in order to demote those
PDs to 25.5W.
Type 4 PSEs present four classification events (see
Figure 19) to Class 5 DS PDs if sufficient power is available. Class 5 DS PDs present class signature 4 on the first
two events and class signature 3 on subsequent events.
An issue arises when a Class 4 or Class 5 dual-signature
PD is connected. In order to determine PD Type, three
class events are issued. Based on the class event count,
the PD has been allocated 25.5W. If the PSE desires to
both determine PD Type (3 events) and demote to 13W
(1 event), a class reset event must be issued as shown
in Figure 21.
POWER ON
Understanding 4PID
The PSE may apply 4-pair power if the PD presents a valid
detection signature on both pairsets and one or more of
the following conditions are met:
• The PD is single-signature configuration.
• The PD is Type 3 or Type 4.
• The PD presents a valid detection signature on an
unpowered pairset when power is applied over the
other pairset.
Although PD signature configuration is not defined for
Type 1 and Type 2 PDs, a Type 3 or Type 4 PSE may
identify such a PD as single-signature or dual-signature.
Single-signature PDs may receive 4-pair power regardless
of PD Type. Certain pre-802.3bt “dual-signature” PDs may
be damaged by 4-pair power.
Type 3 and Type 4 dual-signature PDs are required to
present a unique classification response from pre-802.3bt
dual-signature PDs of the same Class. For dual-signature
PDs, the LTC4291-1/LTC4292 determines and reports
both PD Class and PD Type during classification.
Type 3, Type 4, and pre-802.3bt Class 1 through Class 4
dual-signature PDs present class signature 1 through 4,
respectively, during the first and second class events.
Type 3 and Type 4 dual-signature PDs present class signature 0 for all subsequent class events. Thus, a PSE can
conclusively determine PD Type by the third class event
for all dual-signature PDs.
VOUTnM
4-pair identification (4PID) refers to a set of conditions for
determining whether a PD is capable of receiving power
over both pairsets simultaneously.
1ST
CLASS
2ND
CLASS
3RD
CLASS
1ST
CLASS
VCLASSMIN
VMARKMAX
VRESET
DETECT
1ST
MARK
2ND
MARK
CLASS
RESET
1ST
MARK
42911 F21
Figure 21. Class Reset Event Between Class Sequences
A class reset event is issued by maintaining the channel
voltage below 2.8V for at least tCLASS_RESET. The subsequent single event classification is used to demote the
PD to 13W.
In auto mode the 4PID information and the state of
4PVALID are used to automatically determine the number
of powered channels.
LLDP signaling may, at some time later, determine the
pre-bt PD is actually four pair capable and the LTC4291-1/
LTC4292 may be instructed to deliver 4-pair power.
Invalid Multi-Event Classification Combinations
The 802.3bt specification defines a set of valid class signature combinations. All PDs return the same classification signature on the first two class events. Type 3 and 4
PDs modify the classification signature on all subsequent
class events. For example, a single-signature Class 5 PD
will respond to the class events 1, 2, 3, and 4 with a class
signature of 4, 4, 0, and 0, respectively.
Any individual class signature that exceeds the class current limit is flagged as an invalid classification result. Any
sequence of class signatures that does not represent a
legal sequence based on PD configuration will likewise
be flagged as an invalid classification result.
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LTC4291-1/LTC4292
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Auto Mode Maximum PSE Power
In auto mode the LTC4291-1/LTC4292 automatically
detects, classifies and powers all connected valid PDs.
In order to do this, the PSE must be configured for its
maximum power allocation. The maximum power allocation is a reflection of the power supply and power path
capability. The PWRMD pins must be set appropriately
to reflect the PSE system’s power delivery capabilities.
These pins are sampled at reset.
Table 10. Auto Mode Maximum Delivered Power Capabilities
PWRMD1
PWRMD0
MAX PORT POWER
(SINGLE-SIGNATURE)
MAX PAIRSET POWER
(DUAL-SIGNATURE)
0
0
40W
13W
0
1
51W
25.5W
1
0
62W
25.5W
1
1
71.3W
35.6W
POWER CONTROL
The primary function of the LTC4291-1/LTC4292 is to control power delivery to the PSE port. With the LTC4291-1/
LTC4292, a PSE port is composed of two power channels; each power channel controls power delivery over a
pairset. Within this section, power delivery and control
are defined per-channel.
The LTC4291-1/LTC4292 delivers power by controlling
the gate drive voltage of an external power MOSFET while
monitoring the current (through an external sense resistor) and the output voltage (across the OUT pin).
The LTC4291-1/LTC4292 connects the VEE power supply to the PSE port in a controlled manner, meeting the
power demands of the PD while minimizing power dissipation in the external MOSFET and disturbances to the
VEE backplane.
Inrush Control
When commanded to apply power to a port, the
LTC4291-1/LTC4292 ramps up the GATE pin of one or
both channels (as commanded), raising the external
MOSFET gate voltage in a controlled manner.
26
During a typical inrush, the MOSFET gate voltage will rise
until the external MOSFET is fully enhanced or the channel
reaches the inrush current limit (IINRUSH-2P). IINRUSH-2P is
set automatically by the PSE. When the PSE is applying
4-pair power to a single-signature PD assigned Class 0
to Class 4, IINRUSH-2P is 212.5mA (typical) per channel
(LIMn = 08h). Otherwise, IINRUSH-2P is 425mA (typical)
per channel (LIMn = 80h).
The GATE pin will be servoed if channel current exceeds
IINRUSH-2P, actively limiting current to IINRUSH-2P. When
the GATE pin is not being servoed, the final VGS is 12V
(typical).
During inrush, each powered channel runs a timer (tSTART).
Each powered channel stays in inrush until tSTART expires.
When tSTART expires, the PSE inspects channel voltage
and current. When the PSE is applying power to a PD,
inrush is successful if the channel(s) are drawing current
below IINRUSH-2P, as appropriate per the PD configuration
and Class.
If inrush is not successful, power is removed and the
corresponding tSTART faults are set. Otherwise, the port
or channel, as appropriate, advances to power on and
the programmed current limiting thresholds are used as
described in the Current Limit section.
Port Power Policing
The power policing threshold (PCUT-4P) is monitored on a
per-port basis, up to 128W in 0.5W increments (typical).
When the total output power over a one second moving
average exceeds the specified threshold, power will be
removed from the port and the corresponding tCUT faults
are set.
In particular, the port policing feature may be used to
ensure delivery of PD Class power while staying below
100W Limited Power Source (LPS) requirements.
Current Cutoff and Limit
Each LTC4291-1/LTC4292 port includes two current limiting thresholds (ICUT-2P and ILIM-2P), each with a corresponding timer (tCUT and tLIM). Setting the ICUT-2P and
ILIM-2P thresholds depends on several factors: the PD
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LTC4291-1/LTC4292
APPLICATIONS INFORMATION
assigned Class, the main supply voltage (VEE), the PSE
Type (Type 3 or 4), and the MOSFET SOA.
Configuration field should be set as shown in the LTC4291
Software Programming documentation.
A single set of programmable port ICUT-2P and ILIM-2P
thresholds is shared by both channels. The thresholds
should be set based on the classification result as shown
in Table 4 and Table 5. For a dual-signature PD assigned
unequal Classes, the highest Class is used to set the
thresholds. For example, a dual-signature PD assigned
Class 1 and Class 5 would enforce ICUT-2P and ILIM-2P
based on Class 5.
ICUT-2P is typically set to a lower value than ILIM-2P,
allowing the port to tolerate minor faults without current
limiting.
Per the IEEE specification, the LTC4291-1/LTC4292 will
allow the channel current to exceed ICUT-2P for a limited
period of time before removing power from the port, or
channel, as appropriate whereas it will actively control
the MOSFET gate drive to keep the channel current below
ILIM-2P. The channel does not take any action to limit the
current when only the ICUT-2P threshold is exceeded, but
does start the tCUT timer. If the current drops below the
ICUT-2P threshold before its timer expires, the tCUT timer
counts back down, but at 1/16 the rate that it counts up. If
the tCUT timer reaches 59ms (typical), the port or channel,
as appropriate, is turned off and the corresponding tCUT
faults are set. This allows the channel to tolerate intermittent overload signals with duty cycles below about 6%;
longer duty cycle overloads will remove power from the
port or channel, as appropriate.
The ILIM-2P current limiting circuit is always enabled and
actively limiting channel current. The tLIM timer is enabled
only when the tLIM Timer Configuration field is set to a
non-zero value. This allows tLIM to be set to a shorter value
than tCUT to provide more aggressive MOSFET protection
and turn off a port before MOSFET damage can occur. The
tLIM timer starts when the ILIM-2P threshold is exceeded.
When the tLIM timer reaches 1.7ms (typical) times the
value in the tLIM Timer Configuration field, the port or
channel, as appropriate, is turned off and the appropriate
tLIM faults are set. When the tLIM Timer Configuration field
is set to 0, tLIM behaviors are tracked by the tCUT timer,
which counts up during both ILIM-2P and ICUT-2P events.
To maintain IEEE compliance, the programmed tLIM Timer
To maintain IEEE compliance, the programmed ILIM-2P
should be set as shown in Tables 4 and 5. The programmed ILIM-2P setting is automatically applied following the completion of inrush.
The tCUT and tLIM timers are maintained on a per channel
basis. When a tCUT or tLIM fault occurs a determination is
made to turn off one or both channels. See the Port Fault
vs Channel Fault section for details.
ILIM-2P Foldback
The LTC4291-1/LTC4292 ILIM-2P threshold is implemented as a two-stage foldback circuit that reduces the
channel current if the channel voltage falls below the normal operating voltage. This keeps MOSFET power dissipation at safe levels. Current limit and foldback behavior are
programmable on a per-port basis.
The LTC4291-1/LTC4292 supports current levels well
beyond the maximum values in the 802.3bt specification. Large values of ILIM-2P may require larger external
MOSFETs, additional heat sinking, and setting the tLIM
Timer Configuration field to a lower value.
MOSFET Fault Detection
LTC4291-1/LTC4292 PSE ports are designed to tolerate
significant levels of abuse, but in extreme cases it is possible for an external MOSFET to be damaged. A failed
MOSFET may short source to drain, which will make the
port appear to be on when it should be off; this condition
may also cause the sense resistor to fuse open, turning
off the port but causing SENSE to rise to an abnormally
high voltage. A failed MOSFET may also short from gate to
drain, causing GATE to rise to an abnormally high voltage.
OUT, SENSE and GATE are designed to tolerate up to 80V
faults without damage.
Rev 0
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27
LTC4291-1/LTC4292
APPLICATIONS INFORMATION
If the LTC4291-1/LTC4292 sees a power good condition
on either channel of an unpowered port (neither channel
powered), it disables all port functionality, reduces the
gate drive pull-down current for the port and reports a FET
Bad fault. This is typically a permanent fault, but the host
can attempt to recover by resetting the port, or by resetting the entire chip if a port reset fails to clear the fault.
If the MOSFET is in fact bad, the fault will quickly return,
and the port will disable itself again. The remaining ports
of the LTC4291-1/LTC4292 are unaffected.
An open or missing MOSFET will not trigger a FET Bad
fault, but will cause a tSTART fault if the LTC4291-1/
LTC4292 attempts to turn on the port.
Disconnect
The LTC4291-1/LTC4292 monitors powered channels to
ensure the PD continues to draw the minimum specified current. The IHOLD-2P threshold, monitored as the
VHOLD-2P threshold across the 0.15Ω sense resistor, is
used to determine if a PD has been disconnected.
The IHOLD-2P threshold is set automatically in auto mode
and is set by the user in semi-auto and manual modes.
When powering a single-signature PD assigned Class 0 to
Class 4 over a single channel, set the IHOLD-2P threshold
to 7.5mA (typ) via the Disconnect Configuration bit. In all
other cases, set the IHOLD-2P threshold to 3.5mA (typ).
A disconnect timer (tDIS) counts up whenever channel
current is below the IHOLD-2P threshold, indicating that the
PD has been disconnected. If the appropriate tDIS timer(s)
expire, the port or channel (Table 11) will be turned off
and the corresponding tDIS faults are set. If the current
increases above IHOLD-2P before the tDIS timer expires, the
timer(s) reset. As long as the PD exceeds the minimum
current level before tDIS expires, it will remain powered.
Although not recommended, the DC disconnect feature can be disabled by clearing the corresponding DC
Disconnect Enable bits. Disabling the DC disconnect feature forces the LTC4291-1/LTC4292 out of compliance
with the IEEE standard. A powered port will stay powered
after the PD is removed; the still-powered port may be
28
subsequently connected to a non-PoE data device, potentially causing damage.
The LTC4291-1/LTC4292 does not include AC disconnect circuitry. AC disconnect is not a supported feature
of 802.3bt.
Port Fault vs Channel Fault
The tCUT, tLIM and tDIS timers are maintained on a perchannel basis. When any channel timer expires, a determination is made to remove power from both, one, or
neither channel of the port.
Optional behavior is allowed by the 802.3bt standard
when faults occur on single-signature PDs. This option
allows a single-signature PD to remain powered on pairset X, even if a fault occurs on pairset Y. The FAULT2Pn bit,
when set, enables this optional behavior. This behavior is
not recommended for normal operation, as a fault in the
PD or cabling is indicative of imminent PD or cable failure.
Table 11. Channel Fault Effect on Port/Channel State
PD CONFIGURATION
FAULT RESULT:
TURN OFF PORT OR CHANNEL
FAULT2Pn
tCUT**
tLIM
0
Port
Port
1
Channel
Channel
x
Channel
Channel
Single
Dual
tDIS
Port*
Channel
*If tDIS Expires on Both Channels
**Port power policing (PCUT-4P) raises a tCUT event. When enabled, port
power policing removes power from the port regardless of FAULT2Pn
configuration.
Fault Telemetry
As discussed in the preceding sections, faults may occur
on one or both channels, resulting in power removal on
one or both channels. The fault event registers have traditionally been implemented at the port level. In order to
trace faults to the offending channel, a second layer of fault
registers have been added to the LTC4291-1/LTC4292:
the Fault Telemetry registers. See the LTC4291 Software
Programming documentation for additional information.
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LTC4291-1/LTC4292
APPLICATIONS INFORMATION
Autoclass
IEEE 802.3bt introduces a new optional feature, Autoclass.
Autoclass enables the PSE to reclaim power budget from
single-signature PDs requesting more power than needed
under worst-case operating conditions. 802.3bt does not
specify Autoclass for dual-signature PDs. The LTC4291-1/
LTC4292 fully supports Autoclass.
Prior versions of the 802.3 PoE standard specify minimum PSE output power for worst-case IR drop across
the Ethernet cable and minimum PSE output voltage.
However, a method for the PSE to reclaim over-allocated
power is not specified. When a shorter Ethernet cable is
used, or when the guaranteed PSE output voltage is above
the specified minimum, the specified minimum PSE output power substantially over-allocates power to the PD.
An example PoE system is shown in two versions.
Figure 22 shows a 100W four port PSE servicing three
25.5W PDs over 100m cables. Such a system requires
the PSE to allocate 25.5W per PD and a further 4.5W for
each 100m cable’s IR drop.
The total power allocation is:
Figure 23 shows a 100W four port PSE servicing three
25.5W PDs over 10m cables. Such a system requires the
PSE to allocate 25.5W per PD and a further ~0.5W for
each 10m cable’s IR drop.
Without Autoclass, the total power allocation is:
3 ports • (4.5W + 25.5W) = 90W
If an additional 13W PD is plugged into the fourth PSE
port, only 10W is available and the PD cannot be powered
even though the IR drop is much less than in the prior
example.
Assuming the system in Figure 23 is Autoclass-enabled,
the recovered power budget can be used to power additional ports. During classification, the PSE observes the
PD’s Autoclass request. After power on is completed, the
PD draws its maximum power while the PSE performs
an Autoclass measurement, as specified by 802.3bt. The
PSE in Figure 23 will measure and report 26W of power
consumption for each of the three 25.5W PDs. This result
allows the host to revise the PSE available power budget.
With Autoclass, the total power allocation for Figure 23 is:
3 Ports • 26W (Measured) = 78W
3 Ports • (4.5W + 25.5W) = 90W
If an additional 13W PD is plugged into the fourth PSE
port, only 10W is available and the PD cannot be powered.
If an additional 13W PD is plugged into the fourth PSE
port, a full 22W is now available and the PD can be successfully powered.
13W PD
100m CABLE
4.5W IR DROP
100W PSE
100m CABLE
4.5W IR DROP
100m CABLE
4.5W IR DROP
13W PD
10m CABLE
~0.5W IR DROP
25.5W PD
100W PSE
25.5W PD
10m CABLE
~0.5W IR DROP
10m CABLE
~0.5W IR DROP
25.5W PD
42911 F22
25.5W PD
25.5W PD
25.5W PD
42911 F23
Figure 22. 100W PoE System with 100m Cables
Figure 23. 100W PoE System with 10m Cables
Rev 0
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29
LTC4291-1/LTC4292
APPLICATIONS INFORMATION
Autoclass Negotiation Procedure
A PSE may receive an Autoclass request from the PD by
Physical Layer classification or LLDP (by way of the PSE
host). For Physical Layer requests, the Autoclass negotiation procedure listed below is shown in Figure 24.
1. PSE begins issuing the long first class event. The PD
class signature is allowed to settle during this time.
2. The PD responds with a class signature corresponding to its Class. The class signature during this time
period is unrelated to the Autoclass negotiation.
3. The PSE measures the PD class signature during this
time and uses the result for the normal Multi-event
Classification.
4. The PD continues presenting its class signature.
5. The PSE continues the long class event and does not
measure the class signature current at this time.
6. The PD, if requesting Autoclass, transitions to class
signature 0. If the PD is not requesting Autoclass it
continues presenting its class signature.
tLCE_MAX
tLCE_MIN
VOUTnM
VCLASS
1
3
5
7
VMARK
tCLASS_MIN
t
tCLASS_LCE_MAX
tCLASS_ACS_MIN
IOUTnM
tCLASS_PD_MAX (5ms)
CLASS_SIG_4
2
4
6
8
CLASS_SIG_0
tACS_MIN (75.5ms)
t
tACS_MAX (87.5ms)
42911 F24
8. The PD continues holding the class signature selected
in step 6 until the end of the first class event.
Following the Autoclass negotiation procedure, PSE and
PD continue Physical Layer classification and power up
as normal. Regardless of Autoclass, the PD is required
to operate below the negotiated power allocation corresponding to PD assigned Class.
Autoclass Measurement Procedure
Autoclass measurements may be requested by the PD
through Physical Layer classification or, following power
on, through LLDP. Although the LTC4291-1/LTC4292 is
compatible with LLDP-based Autoclass requests, it cannot receive LLDP Autoclass requests directly since it does
not have access to the data path.
If the PSE is commanded to perform an Autoclass measurement following a Physical Layer request, the measurement typically begins tAUTO_PSE1 (1.5s typical) after
port inrush is successfully completed. For LLDP-based
Autoclass requests, the measurement begins immediately.
The Autoclass measurement period is tAUTO_PSE2 – tAUTO_
PSE1 (1.8s typical) using a sliding window of tAUTO_WINDOW
(0.2s typical). During the Autoclass measurement period,
the PSE continuously monitors IPORT and VEE, calculating maximum average power. Following the Autoclass
measurement period, the Autoclass measurements are
reported in the Port Parametric registers.
See the LTC4291 Software Programming documentation for details on enabling Autoclass, the status of
the Autoclass negotiation, reading Autoclass measurement results and dynamically requesting an Autoclass
measurement.
Port Current Readback
Figure 24. Autoclass Negotiation, Voltage and Current
30
7. The PSE measures the Autoclass response of the PD.
If class signature 0 is measured, the PD is requesting
Autoclass. When the measurement is complete the
first class event is ended.
The LTC4291-1/LTC4292 measures the current at each
power channel with per-channel A/D converters. The total
port current (sum of both channels) is reported. Port
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current is only valid when at least one power channel of a
port is on and reads zero at all other times. The converter
has two modes:
• 100ms mode: Samples are taken continuously and
the measured value is updated every 100ms
• 1s mode: Samples are taken continuously; a moving
1 second average is updated every 100ms
VEE Readback
The LTC4291-1/LTC4292 continuously measures the
VEE voltage with a dedicated A/D converter. This global
VEE measurement is fully synchronized to all port current
measurements.
Port Power Readback
The LTC4291-1/LTC4292 provides fully continuous and
synchronized port power measurements. The LTC4291-1/
LTC4292 calculates the port power by multiplying the port
current and VEE measurements.
PPORT = IPORT × VEE
The Port Power measurements replace the Port Voltage
measurements provided in prior ADI PSEs. Port voltage
may be characterized and extrapolated from the VEE measurement in a user-defined manner.
Masked Shutdown
The LTC4291-1/LTC4292 provides a low latency port
shedding feature to quickly reduce the system load when
required. By allowing a pre-determined set of ports to be
turned off, the current on an overloaded main power supply
can be reduced rapidly while keeping high priority devices
powered. Each port can be configured to high or low priority; all low-priority ports will shut down within 6.5μs after
MSD is pulled low, high priority ports will remain powered.
If a port is turned off via MSD, the corresponding Detection
and Classification Enable bits are cleared, so the port will
remain off until the host explicitly re-enables detection.
In the LTC4291-1/LTC4292 chipset, the active level of
MSD is register configurable as active high or low. The
default behavior is active low.
General Purpose IO
Two general purpose IO pins, GP0 and GP1 are available
on the LTC4291-1. These fully bidirectional IO pins use
3.3V CMOS logic.
Code Download
The LTC4291-1 includes a default firmware image,
enabling 802.3bt-compliant operation with no user intervention required. In addition, the LTC4291-1 firmware is
field-upgradable by downloading and executing firmware
images. Firmware images are volatile and must be redownloaded after each VDD power cycle, but will remain
valid during reset and VEE power events.
The LTC4291-1 is intended for use with Analog Devices
firmware images only. Contact Analog Devices for code
download procedures and firmware images.
SERIAL DIGITAL INTERFACE
Overview
The LTC4291-1 communicates with the host using a
standard SMBus/I2C 2-wire interface. The LTC4291-1
is a slave-only device, and communicates with the host
master using standard SMBus protocols. Interrupts
are signaled to the host via INT. The Timing Diagrams
(Figure 5 through Figure 9) show typical communication
waveforms and their timing relationships. More information about the SMBus data protocols can be found at
www.smbus.org.
The LTC4291-1 requires both the VDD and VEE supply rails
to be present for the serial interface to function.
Bus Addressing
The LTC4291-1’s primary 7-bit serial bus address is
010A3A2A1A0b, with the lower four bits set by AD3 – AD0;
this allows up to 16 LTC4291-1s on a single bus. Sixteen
LTC4291-1s are equivalent to 64 ports. All LTC4291-1s
also respond to the broadcast address 0110000b, allowing the host to write the same command (typically
configuration commands) to multiple LTC4291-1s in a
single transaction.
Rev 0
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31
LTC4291-1/LTC4292
APPLICATIONS INFORMATION
If the LTC4291-1 is asserting INT, it will also respond to
the alert response address (0001100b) per the SMBus
specification.
Each LTC4291-1/LTC4292 is logically composed of a
single four port quad, packed into a single I2C address.
Interrupts and SMBAlert
Most port events can be configured to trigger an interrupt, asserting INT and alerting the host to the event. This
removes the need for the host to poll the LTC4291-1,
minimizing serial bus traffic and conserving host CPU
cycles. Multiple LTC4291-1s can share a common INT
line, with the host using the SMBAlert protocol (ARA) to
determine which LTC4291-1 caused an interrupt.
Register Description
For information on serial bus usage and device configuration and status, refer to the LTC4291 Software
Programming documentation. Contact Analog Devices
to request this document.
ISOLATION REQUIREMENTS
IEEE 802.3 Ethernet specifications require that network
segments (including PoE circuitry) be electrically isolated
from the chassis ground of each network interface device.
However, network segments are not required to be isolated from each other, provided that the segments are
connected to devices residing within a single building on
a single power distribution system.
For simple devices, such as small PoE switches, the isolation requirement can be met by using an isolated main
power supply for the entire device. This strategy can be
used if the device has no electrically conducting ports
other than twisted-pair Ethernet. In this case, the SDAIN
and SDAOUT pins can be tied together and will act as a
standard I2C/SMBus SDA pin.
If the device is part of a larger system, contains additional
external non-Ethernet ports, or must be referenced to protective ground for some other reason, the PoE subsystem
must be electrically isolated from the rest of the system.
32
The LTC4291-1/LTC4292 chipset simplifies PSE isolation
by allowing the LTC4291-1 chip to reside on the nonisolated side. There it can receive power from the main
logic supply and connect directly to the I2C/SMBus bus.
Isolation between the LTC4291-1 and LTC4292 is implemented using a proprietary transformer-based communication protocol. Additional details are provided in the
Serial Bus Isolation section of this data sheet.
EXTERNAL COMPONENT SELECTION
Power Supplies
The LTC4291-1/LTC4292 requires two supply voltages to
operate. VDD requires 3.3V (nominally) relative to DGND.
VEE requires a negative voltage of between –51V to –57V
for Type 3 PSEs, or –53V to –57V for Type 4 PSEs, relative to AGNDP.
Digital Power Supply
VDD provides digital power for the LTC4291-1 processor.
A ceramic decoupling cap of at least 0.1μF should be
placed from VDD to DGND, as close as practical to each
LTC4291-1. A 1.8V core voltage supply is generated internally and requires a 1µF ceramic decoupling cap between
the CAP1 pin and DGND.
In the LTC4291-1, VDD should be delivered by the host
controller’s non-isolated 3.3V supply. To maintain required
isolation, LTC4292 AGNDP and LTC4291-1 DGND must
not be connected in any way.
Main PoE Power Supply
VEE is the main isolated PoE supply that provides power
to the PDs. Because it supplies a relatively large amount
of power and is subject to significant current transients,
it requires more design care than a simple logic supply.
For minimum IR loss and best system efficiency, set VEE
near maximum amplitude (57V), leaving enough margin
to account for transient over or undershoot, temperature
drift, and the line regulation specifications of the particular
power supply used.
Rev 0
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Bypass capacitance between AGNDP and VEE is very
important for reliable operation. If a short circuit occurs
at one of the output ports it can take as long as 1μs for
the LTC4292 to begin regulating the current. During this
time the current is limited only by the small impedances
in the circuit; a high current spike typically occurs, causing a voltage transient on the VEE supply and possibly
causing the LTC4291-1/LTC4292 to reset due to a UVLO
fault. A 1μF, 100V X7R capacitor placed near the VEE and
AGNDP pins along with an electrolytic bulk capacitor of at
least 47µF across the supply is recommended to minimize
spurious resets.
transformers do not have common-mode chokes. These
transformers typically provide 1500V of isolation between
the LTC4291-1 and the LTC4292. For proper operation,
strict layout guidelines must be met.
External MOSFET
Careful selection of the power MOSFET is critical to system reliability. Choosing a MOSFET requires extensive
analysis and testing of the MOSFET SOA curve against the
various PSE current limit conditions. ADI recommends
the PSMN075-100MSE for PSEs configured to deliver
up to 51W maximum port power (single-signature) or
25.5W maximum pairset power (dual-signature). For
PSEs configured to power up to 71.3W maximum port
power (single-signature) or 35.6W maximum pairset
power (dual-signature), ADI recommends the PSMN040100MSE. These MOSFETs are selected for their proven
reliability in PoE applications. Contact ADI Applications
before using a MOSFET other than one of these recommended parts.
Serial Bus Isolation
The LTC4291-1/LTC4292 chipset uses transformers to
isolate the LTC4291-1 from the LTC4292 (see Figure 25).
In this case, the SDAIN and SDAOUT pins can be shorted
to each other and tied directly to the I2C/SMBus bus.
The transformers should be 10BASE-T or 10/100BASE-T
with a 1:1 turns ratio. It is optimal that the selected
10Ω
3.3V
GP0
GP1
NO ISOLATION
REQUIRED ON
I2C INTERFACE
SCL
SDAIN
SDAOUT
ISOLATION
AGNDP
VDD
CPD
4PVALID
RESET
MSD
AUTO
INT
CPA
100Ω
3.3V
•
•
100Ω
PWRMD1
100Ω
PWRMD0
VEE
100Ω
CND
OUTnB
CNA
LTC4292
LTC4291-1
DPD
DPA
100Ω
3.3V
AD0
AD1
AD2
AD3
AGNDP
•
•
100Ω
GATEnB
SENSEnB
100Ω
PORTn
VEE
OUTnA
GATEnA
100Ω
DND
SENSEnA
DNA
VEE
DGND
42911 F25
2nF 2kV
VEE
Figure 25. LTC4291-1/LTC4292 Proprietary Isolation
Rev 0
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33
LTC4291-1/LTC4292
APPLICATIONS INFORMATION
Sense Resistors
The LTC4291-1/LTC4292 is designed for a low 0.15Ω current sense resistance per channel. Two parallel 0.3Ω resistors must be laid out as shown in the Layout Requirements
section. In order to meet the IHOLD-2P, ICUT-2P, and ILIM-2P
accuracy required by the IEEE specification, the sense
resistors should have ±1% tolerance or better, and no
more than ±200ppm/°C temperature coefficient.
Port Output Cap
Each port requires a 0.22μF cap across OUTnM to AGNDP
(see Figure 25) to keep the LTC4292 stable while in current limit during startup or overload. Common ceramic
capacitors often have significant voltage coefficients; this
means the capacitance is reduced as the applied voltage
increases. To minimize this problem, X7R ceramic capacitors rated for at least 100V are recommended and must
be located close to the LTC4292.
Surge Protection
Ethernet ports can be subject to significant cable surge
events. To keep PoE voltages below a safe level and protect the application against damage, protection components, as shown in Figure 26, are required at the main
supply, at the LTC4292 supply pins, and at each port.
Bulk transient voltage suppression (TVSBULK) and bulk
capacitance (CBULK) are required across the main PoE
supply and should be sized to accommodate system level
surge requirements.
Each LTC4292 requires a 10Ω, 0805 resistor (R1) in series
from supply AGND to the LTC4292 AGNDP pin. Across
R1
10Ω
CBULK
Finally, each port requires a pair of S1B clamp diodes: one
from OUTnM to supply AGND and one from OUTnM to
supply VEE. The diodes at the ports steer harmful surges
into the supply rails where they are absorbed by the surge
suppressors and the VEE bypass capacitance. The layout
of these paths must be low impedance.
LAYOUT REQUIREMENTS
Strict adherence to board layout, parts placement and
routing requirements is critical for IEEE compliance, parametric measurement accuracy, system robustness and
thermal dissipation. Refer to the DC2685A demo kit for
example layout references.
Sense Resistor Block Layout Requirements
A channel sense resistor may be affected by currents
flowing in other channels. To ensure IEEE parametric
compliance, the sense resistor layout is strictly defined
and must be adhered to. In addition, the sense resistor
block’s common VEE plane connections and layout are
specified.
Figure 33 shows the component names for ports 1 and 2
as referenced in the remainder of this section. The sense
resistors (RST1 to RST4 and RSU1 to RSU4) for channels
1A, 1B, 2A, and 2B must be grouped together in a sense
resistor block. The same requirements apply to channel
3A, 3B, 4A, and 4B sense resistors and VSSK34.
AGNDP
C1
1µF
100V
+
the LTC4292 AGNDP pin and VEE pin is a SMAJ58A 58V
TVS (D1) and a 1µF, 100V bypass capacitor (C1). These
components must be placed close to the LTC4292 pins.
AGNDP
D1
SMAJ58A
LTC4292
VEE
VSSKn SENSEnM GATEnM OUTnM
Cn
0.22µF
X7R
100V
AGNDP
TVSBULK
VEE
RSENSEnM
QnM
S1B
S1B
VEE
OUTnM
TO
PORT
42911 F26
Figure 26. LTC4292 Surge Protection
34
Rev 0
For more information www.analog.com
LTC4291-1/LTC4292
APPLICATIONS INFORMATION
Figure 27 shows the top layer PCB placement of sense
resistors RST1 to RST4. Each bottom layer sense resistor,
RSU1 to RSU4, is placed directly underneath its paired
top layer sense resistor. The VEE–facing side of the sense
resistors connect to a common VEE copper area on the
solder pad top edge with a 5mil to 10mil overlap.
copper area and connect the common copper in this area
on all four layers. The power vias must be sized to a 17mil
drill and 30mil diameter annular ring.
Figure 28 shows the top component layer common VEE
area copper requirements. On the top layer, the common
VEE area copper is extended at the bottom center down
to the length of the sense resistor pads to allow copper
to flow between the two center sense resistors and bottom center power via. A 10mil keepout is placed around
the common VEE copper area and VEE pads of the sense
resistors. These instructions for the top component layer
are repeated for the bottom component layer.
Kelvin Sense
Figure 29 shows the inner layer 2 (VEE plane) common
VEE copper area requirements. A 10mil keepout is placed
around the common VEE copper area; the exception is the
bottom center where the common VEE area copper opens
up to the VEE plane. The common VEE copper area only
connects to VEE on layer 2.
Figure 30 shows the inner layer 3 (AGND plane and routing) common VEE area copper requirements. A 10mil
keepout is placed around the common VEE copper area
to separate it from the surrounding AGND plane.
Figure 31 shows the common VEE copper area power via
placement. There are 15 power vias in the common VEE
Figure 32 is the PCB layer structure defining the copper
thickness requirements for each layer.
Proper Kelvin sensing must be implemented in the layout.
VSSK12 connects to a series resistor RK1 in Figure 33.
From RK1 (Figure 28), a Kelvin sense small signal trace
connects to VEE only on layer 3 at the centroid top of
the sense resistors (RST1 to RST4 and RSU1 to RSU4)
common VEE copper area (Figure 30). A 10mil keepout
must be placed around the RK1 solder pad that leads to
VEE (Figure 28); around the trace from RK1 to the centroid (Figures 28 and 30); on all layers around any vias
that connect the trace to different layers (Figures 28, 29,
and 30).
At each of the sense resistors, on the side facing
SENSEnM, a power via is placed as close to the respective solder pads as allowed by the layout DRC. This power
via connects the top and bottom sense resistor pair for
a channel. A Kelvin sense small signal trace connects
SENSEnM directly to the respective sense resistor pair
via shown in Figure 30. A separate power path wide trace
connects from the sense resistor pair to the MOSFET.
SENSEnM must not connect to anywhere else on the
power path between the sense resistor and the MOSFET.
RK1
RK1
VSSK12 VIA
300Mil
90Mil
RST1
RST2
RST3
RST1
RST4
RST2
RST3
RST4
110Mil
250Mil
NOTES: DRAWING NOT TO SCALE.
VSSK12 VIA ISOLATED ON TOP AND BOTTOM LAYERS.
42911 F27
Figure 27. Top Component Layer Sense Resistors Placement
NOTES: DRAWING NOT TO SCALE.
RK1 ONLY ON TOP LAYER.
42911 F28
Figure 28. Top and Bottom Layer Sense Resistor Block Layout
Rev 0
For more information www.analog.com
35
LTC4291-1/LTC4292
APPLICATIONS INFORMATION
300Mil
(VEE PLANE)
300Mil
90Mil
A
B
SE
E1
NS
NS
E2
B
SE
E1
SE
130Mil
NS
NS
E2
SE
A
90Mil
(AGND PLANE)
NOTES: DRAWING NOT TO SCALE.
VSSK12 VIA ISOLATED.
42911 F29
NOTES: DRAWING NOT TO SCALE.
VSSK12 VIA CONNECTS VEE.
Figure 29. Inner Layer 2 Sense Resistor Block Layout
(VEE Plane)
42911 F30
Figure 30. Inner Layer 3 Sense Resistor Block Layout
(AGND/Signal Plane)
RK1
240Mil
160Mil
80Mil
40Mil
25Mil
NOTE: DRAWING NOT TO SCALE.
40Mil
42911 F31
Figure 31. Sense Resistor Block Via Specifications
Figure 32. PCB Layer Structure
36
Rev 0
For more information www.analog.com
LTC4291-1/LTC4292
TYPICAL APPLICATION
Figure 33. Alternative A (MDI-X) and Alternative B(S), 1000BASE-T, IEEE 802.3bt, Type 3 or Type 4 PSE, Ports 1 and 2 Shown
10Ω
AGNDP
AGNDP
AGNDP
S1B
0.22μF
100V
S1B
GATE1A
T1
VEE
Q1
75Ω
CT1
SENSE1A
RST1
0.3Ω
CPA
RSU1
0.3Ω
75Ω
DPA
DATA SOURCE
CNA
VEE
DNA
AGNDP
0.22μF
100V
PORT 1
DATA AND
POWER OUT
CT2
75Ω
CT3
75Ω
CT4
1
2
3
4
5
6
7
8
OUT1B
GATE1B
Q2
RJ45
SENSE1B
RST2
0.3Ω
1000pF
2kV
RSU2
0.3Ω
AGNDP
LTC4292
VSSK12
S1B
VEE
0.22μF
100V
S1B
0.15Ω
PWRMD0
PWRMD1
0
0
VEE
VEE
AGNDP
0
1
1
0
1
1
Q1 TO Q4
NEXPERIA
PSMN075-100MSE
NEXPERIA
PSMN040-100MSE
S1B
0.22μF
100V
T2
OUT2A
S1B
GATE2A
Q3
75Ω
VEE
CT5
SENSE2A
RST3
0.3Ω
RSU3
0.3Ω
VEE
PWRMD0
PWRMD1
75Ω
DATA SOURCE
TO LTC4291-1 THROUGH ISOLATION INTERFACE
OUT1A
AGNDP
0.22μF
100V
CT6
75Ω
CT7
75Ω
CT8
OUT2B
GATE2B
Q4
PORT 2
DATA AND
POWER OUT
1
2
3
4
5
6
7
8
SENSE2B
RST4
0.3Ω
VEE
1000pF
2kV
RSU4
0.3Ω
S1B
42911 F33
VEE
RJ45
VEE
S1B
T1, T2: WURTH 749022016
COILCRAFT ETH-460L
CT1-CT8: 0.01μF, 200V
VEE
Rev 0
For more information www.analog.com
37
LTC4291-1/LTC4292
PACKAGE DESCRIPTION
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697 Rev B)
0.70 ±0.05
4.50 ±0.05
2.45 ±0.05
3.10 ±0.05 (4 SIDES)
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
4.00 ±0.10
(4 SIDES)
BOTTOM VIEW—EXPOSED PAD
R = 0.115
TYP
0.75 ±0.05
PIN 1 NOTCH
R = 0.20 TYP OR
0.35 × 45° CHAMFER
23 24
PIN 1
TOP MARK
(NOTE 6)
0.40 ±0.10
1
2
2.45 ±0.10
(4-SIDES)
(UF24) QFN 0105 REV B
0.200 REF
0.00 – 0.05
0.25 ±0.05
0.50 BSC
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
38
Rev 0
For more information www.analog.com
LTC4291-1/LTC4292
PACKAGE DESCRIPTION
UJ Package
40-Lead Plastic QFN (6mm × 6mm)
(Reference LTC DWG # 05-08-1728 Rev Ø)
0.70 ±0.05
6.50 ±0.05
5.10 ±0.05
4.42 ±0.05
4.50 ±0.05
(4 SIDES)
4.42 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
6.00 ±0.10
(4 SIDES)
0.75 ±0.05
R = 0.10
TYP
R = 0.115
TYP
39 40
0.40 ±0.10
PIN 1 TOP MARK
(SEE NOTE 6)
1
4.50 REF
(4-SIDES)
4.42 ±0.10
2
PIN 1 NOTCH
R = 0.45 OR
0.35 × 45°
CHAMFER
4.42 ±0.10
(UJ40) QFN REV Ø 0406
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
0.25 ±0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
Rev 0
For more information www.analog.com
39
LTC4291-1/LTC4292
TYPICAL APPLICATION
Figure 34. IEEE 802.3bt Type 3 or Type 4 PSE, Alternative A (MDI-X) and Alternative B(S), 1000BASE-T, 1 of 4 Ports Shown
GP0
D1
VEE
VDD
>47µF
ISOLATION
PWRMD1
CPD
4PVALID
CNA
LTC4291-1 DPD
DPA
100Ω
3.3V
SDAIN
DGND
CAP1
0.22µF
100V
QnB
GATEnB
VEE
6
4
TX3
S1B
5
7
S1B
0.15Ω
0.22µF
2nF
2kV
3
TX2
OUTnB
DNA
1µF
2
S1B
VSSKn
LTC4292
100Ω
DND
S1B
AGNDP
VEE
100Ω
SDAOUT
AD0
AD1
AD2
AD3
100Ω
100Ω
TX1
0.15Ω
SENSEnA
CND
SCL
QnA
GATEnA
VEE
100Ω
MSD
0.22µF
100V
100Ω
3.3V
RESET
1
AGNDP
AGNDP
OUTnA
CPA
100Ω
AUTO
INT
1µF
100V
D2
PWRMD0
GP1
(NO I2C
ISOLATION
REQUIRED)
AGNDP
10Ω
QnA, QnB: PSMN040-100MSE
D1: SMCJ58A
D2: SMAJ58A 0.1µF 3.3V
CAP2
VEE
SENSEnB
VSSKn
VSSKn
TX4
VEE
8
1000BASE-T
0.22μF, 100V
VEE
0.15Ω
RJ45
(1 OF 4 PORTS)
42911 F34
AGNDP
VSSKn
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40
Rev 0
D17158-0-10/18(0)
www.analog.com
For more information www.analog.com
ANALOG DEVICES, INC. 2018
