LTC4371IMS#PBF

LTC4371 Dual Negative Voltage Ideal Diode-OR Controller and Monitor Description Features Controls N-Channel MOSFETs to Replace Power Schottky Diodes nn Low 15mV Forward Voltage Minimizes Dissipation nn Withstands > ±300V Transients nn Fast Turn-Off:  5mA, no VDD bypassing is required. Note that a shorted gate will demand a continuous current of 5mA whenever ∆VSD is large. The LTC4371 attempts to servo the forward drop across the MOSFET (∆VSD) to 15mV by controlling the gate, and flags a fault if the drop exceeds 200mV when the MOSFET is driven fully on. Thus an upper bound for RDS(ON) is set by: The 5mA pull-up is enabled when VZ is biased to >11.8V in its normal shunt regulator mode, or when VZ is  250V Applications with 5mA Gate Pull-Up Current Disabled MOSFET Selection The LTC4371 drives N-channel MOSFETs to conduct the load current. The important features of the MOSFETs are threshold voltage, VGS(TH); maximum drain-source voltage, BVDSS; and on-resistance, RDS(ON). Full gate drive for the MOSFETs (∆V GATE ) is VDD + 100mV/–200mV. When used in shunt regulated circuits such as shown in Figure 2, full gate drive lies in 10 ∆VSD(FLT) Where ∆VSD(FLT) is 150mV minimum. VDD VZ RDS(ON) < The gate amplifiers are compensated by the input capacitance of the external MOSFETs. No further compensation components are necessary except in the case of very small MOSFETs. If CISS is less than 500pF, add a 1nF capacitor across the MOSFET gate and source terminals. High Voltage Transient Protection Although the LTC4371 drain pins, DA and DB are designed to handle voltages ranging from –40V to 100V with respect to VSS, they may be subjected to much higher voltages, even in –48V systems. DA and DB are directly exposed to 4371f For more information www.linear.com/LTC4371 LTC4371 Applications Information all voltages appearing at the input. Spikes and transients may arise from various conditions including lightning induced surges, electrostatic discharge, switching of adjacent loads, and input short circuits. The positive spike at the input is clamped to BVDSS relative to VOUT by MOSFET avalanche. BVDSS is inadequate protection for the DA and DB pins, as shall be discussed later. Although the energy stored in parasitic inductance during input short circuit faults is at least two orders of magnitude smaller than the avalanche energy rating of most MOSFETs, the peak current may exceed the avalanche current rating of the MOSFET. In this case and if positivegoing transient energy from other external sources exceeds the MOSFET’s avalanche energy rating, add TVS clamps across each MOSFET as shown in Figure 6. The dynamic behavior of an active ideal diode entering reverse bias is most accurately characterized by a delay, followed by a period of reverse recovery. During the delay phase some reverse current is built up, limited by parasitic resistance and inductance. During the reverse recovery phase, energy stored in the parasitic inductance is transferred to other elements in the circuit. Externally applied input transients in the negative direction are clamped by the body diodes of the MOSFETs to –700mV with respect to VOUT, if not connected directly through RDS(ON) to VOUT, and pose no particular hazard for the DA and DB pins. Negative input transients couple directly to the output which increases the RTN to VOUT voltage. Although the shunt resistor, RZ, limits the current into VZ to a safe level of less than 10mA, an output capacitor or TVS clamp may be required to protect downstream circuitry from negative input transients. Current slew rates during reverse recovery may reach 100A/μs or higher. High slew rates coupled with parasitic inductance in series with the input and output can cause destructive transients to appear at the drain, source and VSS pins of the LTC4371 during reverse recovery. A zero impedance short circuit directly across the input and return is especially troublesome because it permits the highest possible reverse current to build up during the delay phase. When the MOSFET finally interrupts the reverse current, the MOSFET drain and the LTC4371 drain pins experience a positive-going voltage spike, while the MOSFET source and the LTC4371 source and VSS pins spike in the negative direction. To protect the circuit biasing VDD, clamp or bypass VOUT as close as possible to the junction of the MOSFET sources and VSS and the point where the VDD bias circuit connects to return. 100V BVDSS(MIN) MOSFETs are commonly used in –48V applications, but BVDSS(MAX) is not guaranteed and cannot be relied upon to protect the DA and DB pins from exceeding their absolute maximum rating of 100V. Nevertheless, the 100V absolute maximum rating for DA and DB may be safely exceeded if certain precautions are taken. The internal 130V clamps shown in the Block Diagram tolerate RTN RZ 30k 33k VDD VZ INPUT SHORT LTC4371 DA VA –36V TO –72V VB –36V TO –72V INPUT PARASITIC INDUCTANCE – + 20k DB GA CLOAD FAULTB GB SA GREEN LED = MOSFETS GOOD SB VSS 20k 2.2μF OPT. OUTPUT PARASITIC INDUCTANCE – + VOUT REVERSE RECOVERY CURRENT INPUT PARASITIC INDUCTANCE + – OPT. Figure 6. Input Short Circuit Parasitics and Protection Against High Voltage Transients For more information www.linear.com/LTC4371 4371 F06 4371f 11 LTC4371 Applications Information up to 10mA for 6ms in breakdown. For protection against transients exceeding 100V, add series resistors RDA and RDB according to: RDA , RDB > VIN(PK) – VBVD(MIN) where VIN(PK) is the peak input voltage measured with respect to VSS, and VBVD(MIN) is the minimum drain pin breakdown voltage (100V). Because their presence incurs no particular performance penalty, a minimum value of 20kΩ is prudent and protects the DA and DB pins against transients up to 300V, as shown in Figure 7. A practical limit for RDA and RDB is 100kΩ, beyond which their resistance interferes with the operation of the gate amplifier. Some speed penalty is incurred for values greater than 20kΩ, as shown in Figure  8. If the speed penalty is unacceptable, add a resistor and capacitor across RDA and RDB as shown in Figure 9 to restore the response time. LTC4371 GA SA VSS RDA 20k VA DA GA VOUT M1 4371 F07 C1 100pF VA tOFF (ns) 4371 F08 Figure 9. High Voltage Drain Pin Protection with C1 and R1 Maintaining Fast Turn-Off Time High Voltage DC Applications An extra blocking device is necessary to protect the DA and DB pins in applications where the DC input voltage exceeds 100V. Even in –48V applications the equivalent DC input voltage may exceed 100V, as a result of a reverse connected supply feed that can impress up to double the maximum operating voltage across the inputs. Because the 130V DA and DB pin clamps are limited to clamping short-term spikes, some other means of limiting the maximum applied voltage is necessary in DC applications. The N-channel cascode shown in Figure 10 extends the DC input operating voltage to 600V. It safely clamps the drain pin to about 2V less than VZ, yet introduces only 500Ω series resistance when the input is in the vicinity of VOUT; fast turn-off time is maintained. RZ VDD = 12.4V ∆VSD = 0.1V TO –0.4V CGATE = 3.3nF VZ 450 LTC4371 DA 300 GA SA VSS D1 IN4148W 150 M2 BSS127 VA 0 20 40 60 80 DRAIN PIN RESISTANCE (kΩ) 100 4371 F09 Figure 8. Reverse Response Time vs. Drain Pin Resistance 12 VOUT M1 Drain Pin Resistance 0 VSS RDA 100k R1 10k Figure 7. 300V Drain Pin Protection 600 SA (8) 10mA DA LTC4371 M1 VOUT 4371 F10 Figure 10. Drain Protection for Applications Up to –600V 4371f For more information www.linear.com/LTC4371 LTC4371 Applications Information Fuse and Open MOSFET Detection The LTC4371 monitors ∆VSD of each channel as measured across SA – DA and SB – DB. If ∆VSD of either channel exceeds 200mV and the associated gate pin is driven fully on, FAULTB pulls low to indicate a fault. Conditions leading to high ∆VSD include excessive load current (ILOAD × RDS(ON) > 200mV), an open circuit MOSFET or an open fuse placed in series with the MOSFET. A high ∆VSD fault is detected on only the highest voltage input supply, i.e. the path that should be supplying power is, as a result of one of the aforementioned conditions, unable to do so. Temporary conditions, such as the initial 700mV drop experienced when an input first rises to the point of supplying current but before the gate has been driven on, are masked since the gate must also be high for fault detection. Figure 12 shows a protection method that extends DA and DB pin operation to ±600V. The drain pins are clamped by an 82V Zener diode. As shown, the DA pin is clamped at 82V with respect to VSS in the positive direction, and 700mV below VSS in the negative direction. When a high input voltage of either polarity is present, back-to-back depletion mode N-channel MOSFETs limit the current in the Zener diode to VGS(TH)/RDA (100μA for RDA = 20kΩ), a value that is indefinitely sustainable. LTC4371 DA DB GA GB SA SB VSS D1 1N4148W D2 1N4148W RDA 20k VA –36V TO –72V VB –36V TO –72V RDB 20k F1 VOUT M1 F2 M2 4371 F11 Figure 11. Fuse and Open MOSFET Detection VSS RDA 20k M2* VA M1 *M2, M3: BSP135 (600V) DEPLETION NMOS VOUT 4371 F12 Figure 12. Back-to-Back Drain Pin Limiter for ±600V FAULTB Pin The open drain FAULTB pin pulls low when the ∆VSD of either channel exceeds 200mV, while its gate is driven fully on. FAULTB can sink 5mA to drive an LED for visual indication, or an opto isolator to communicate across an isolation barrier. The FAULTB pin voltage is limited to 17V absolute maximum with respect to VSS in the high state and cannot be pulled up to return except in low voltage applications. LTC4371 DA SA M3* The ∆VSD monitor can be used to detect open fuses, as shown in Figure 11. An open fuse gives the same signature as an open MOSFET: ∆VSD increases beyond 200mV when the affected input surpasses the opposing channel. The connection shown in Figure  11 introduces a new problem: an open fuse and open MOSFET exposes the DA and DB pins to high negative voltage with respect to VSS. Diodes D1 and D2 clamp the DA, DB pins from exceeding the absolute maximum of –40V with respect to VSS. GA 82V In Figure 13, the FAULTB pin is used to shunt current away from a green LED; the LED indicates (illuminates when) no fault condition is present. The operating voltage is limited at the low end by the minimum acceptable LED current, and at the high end by the FAULTB pin’s 5mA capability. Figure 14 shows a simple implementation driving a red LED; the LED indicates a fault condition is present. While this simple configuration works well in –48V applications, the maximum operating voltage is limited to 100V, the LED 4371f For more information www.linear.com/LTC4371 13 LTC4371 Applications Information current varies widely with operating voltage, and dissipation in the 20kΩ resistor reaches ≈250mW at 72V input. These shortcomings are eliminated by the slightly more complex circuit shown in Figure 15. A cascode shields the FAULTB pin from the high input voltage and dissipates no power under normal conditions, while the LED current remains constant regardless of input voltage when indicating a fault. At 600V, cascode dissipation reaches 600mW maximum. RTN LTC4371 R1 33k FAULTB VSS D1 GREEN LED = MOSFETS GOOD 4371 F13 VOUT Figure 13. FAULTB Drives a Green LED in Shunt Mode RTN R1 20k 500mW Layout Considerations A sample layout for the LTC4371 DFN package and PGHSOF-8 MOSFET package is shown in Figure 16. The VDD bypass capacitor C1 provides AC current to the device; place it as close to VDD and VSS pins as possible. Connect the gate amplifier input pins, DA, DB, SA and SB, directly to the MOSFETs’ drain and source terminals using Kelvin connections for good accuracy. Place the MOSFET sources as close together as possible, with VSS connecting at their intersection. Keep the traces to the MOSFET drains and common source wide and short. A good rule-of-thumb for minimizing self-heating effects in the copper traces is to allow at least 1-inch trace width per 50 amperes, for a surface layer of 1-ounce copper. This current density corresponds to a selfheating effect of about 1.3W per square inch. The traces associated with the power path through the MOSFETs must have low resistance to maintain good efficiency and low drop. The resistance of 1-ounce copper is approximately 500μΩ per square. D1 RED LED = MOSFET BAD LTC4371 R2 3.9k FAULTB VB VSS M2 4371 F14 VOUT Figure 14. FAULTB Drives a Red LED in Series Mode RTN RDB D1 RED LED = MOSFET BAD M2 BSP125 VDD LTC4371 C1 VOUT RDA R2 10k LTC4371 FAULTB VSS 4371 F15 VA VOUT M1 –600V MAX Figure 15. FAULTB Driving an LED in a High Voltage Application 4371 F16 Figure 16. Recommended PCB Layout for M1, M2 and C1 14 4371f For more information www.linear.com/LTC4371 LTC4371 Applications Information Design Example The following design example demonstrates the calculations involved for selecting external components. Consider a –48V application with a –36V to –72V operating range, 200V peak transient and 25A maximum load current (see Figure 17). The simplest configuration is chosen to power VDD, since this arrangement easily handles the operating conditions found in a –48V telecom power system. The bias resistor, RZ, is calculated from Equation 1: RZ < 36V – 11.8V = 32.2kΩ 750µA (9) ∆VSD = 25A • 2mΩ = 50mV (11) which is well below the 150mV minimum ∆VSD fault threshold. From Equation 7, the maximum power dissipation in the MOSFET is: PD(MOSFET) = 25A 2 • 2mΩ = 1.25W (12) a reasonable value for the proposed package. The minimum recommended value of 20kΩ is chosen for RDA and RDB. 20kΩ protects the DA and DB pins to 300V. The worst case power dissipation in RZ: The maximum voltage drop across the MOSFET is: The nearest lower 5% value is 30kΩ. PD(RZ) = Next, choose the N-channel MOSFET. The 100V, IPT020N10N3 in a PG-HSOF-8 package with RDS(ON) = 2mΩ (max) offers a good solution. (72V – 11.8V)2 = 166mW (10) 30k A 30kΩ 0.25W resistor is selected for RZ. The maximum VZ current is confirmed from Equation 3 as a safe value of 2mA. A –200V transient pushes this to 6.3mA, safely below the maximum allowable VZ current of 10mA. The LED, D1, requires at least 1mA of current to turn on fully; therefore, R1 is set to 33k to accommodate the minimum input supply voltage of –36V. The maximum current is 2mA at –72V, but excursions to 200V give 6mA, slightly beyond the FAULTB pin’s 5mA capability. This means that if there is a fault present, a brief glitch might cause a “no fault” indication during a 200V transient. Since D1 is a visual indicator, we’ll accept the remote chance of a dim flash in exchange for the simple circuit solution. RTN RZ 30k VZ R1 33k FAULTB LTC4371 DA RDA 20k VA –36V TO –72V VB –36V TO –72V DB GA C1 2.2μF VDD GB SA RDB 20k M1 IPT020N10N3 M2 IPT020N10N3 SB VSS D1 GREEN LED = MOSFETS GOOD VOUT 25A LOAD 4371 F17 Figure 17. –36V to –72V/25A Ideal Diode-OR 4371f For more information www.linear.com/LTC4371 15 LTC4371 Applications Information mum IDD of 9.5mA (LTC4371) + 1mA (LED) = 10.5mA, Equation 4 gives: As a second design example, consider modifying the circuit of Figure 17 to handle 300V transients and to drive a red LED, which illuminates when a fault is present (see Figure 18). RDA and RDB are sized to handle transients to 300V, so no change in their value is necessary. Modifications are necessary to drive the red LED. 10.5mA = 525µA 20 36V – 11.8V RZ < = 44k 10mA 50uA+ 20 IBASE = A PZTA42, a 300V NPN with a minimum β = 20 is chosen to supply both the LED and the VDD pin. With a maxi- (13) The nearest lower 5% value is 43k. To produce 1mA LED current with variations in the circuit, R1 is chosen to be 8.2k. RTN RZ 43k VZ Q1 PZTA42 VDD FAULTB LTC4371 DA DB RDA 20k VA –36V TO –72V VB –36V TO –72V GA R1 8.2k D1 RED LED = MOSFET BAD GB SA RDB 20k M1 IPT020N10N3 SB VSS C1 0.1μF VOUT 25A LOAD M2 IPT020N10N3 4371 F18 Figure 18. –36V to –72V/25A Ideal Diode-OR 16 4371f For more information www.linear.com/LTC4371 LTC4371 Typical Applications RTN RZ 30k R1 33k VZ VDD FAULTB LTC4371 DA DB GA GB SA SB VSS 2.2µF D1 GREEN LED = MOSFETS GOOD RD 20k VA –36V TO –72V VOUT 100A LOAD M1 – M4 IPT020N10N3 4371 F19 Figure 19. –36V to –72V Single Channel Parallel Application with 2× Gate Drive RTN R2 100Ω LTC4371 DA DB C1 2.2µF VDD VZ R1 33k FAULTB GB SA SB VSS GA D1 GREEN LED = MOSFETS GOOD M1 VA –12V VOUT 100A LOAD M2 *3×PSMN0R9-3YLD VB –12V M3 M1– M3 PSMN0R9-3YLD M4 4371 F20 M5 M6 M4 – M6 PSMN0R9-3YLD Figure 20. –12V/100A Application with 5mA Gate Pull-Up Enabled 4371f For more information www.linear.com/LTC4371 17 LTC4371 Typical Applications RTN RZ 120k R1 100k LTC4371 DA DB D2 1N4148 C1 2.2μF VDD VZ GA FAULTB GB SA SB VSS D1 GREEN LED = MOSFETS GOOD D3 1N4148 M3 BSP89 M4 BSP89 VA –100V TO –240V VOUT 5A LOAD M1 IPB200N25N3 VB –100V TO –240V M2 IPB200N25N3 4371 F21 Figure 21. –100V to –240V/5A Ideal Diode-OR Controller RTN RZ 172k Q1 PZTA42 VDD VZ LTC4371 DA C1 0.1μF DB GA R1 100k FAULTB GB SA SB VSS D2 MMSZ5268BTIG D1 GREEN LED = FUSES/MOSFETS GOOD D3 MMSZ5268BTIG VA –100V TO –240V VB –100V TO –240V M3 BSP129 M5 BSP129 RDA 20k RDB 20k M4 BSP129 M6 BSP129 F1 M1 IPB200N25N3 VOUT 5A LOAD F2 M2 IPB200N25N3 4371 F22 Figure 22. –100V to –240V/5A Ideal Diode-OR Controller with Open Fuse and MOSFET Detection 18 4371f For more information www.linear.com/LTC4371 LTC4371 Typical Applications + RZ 10k LTC4371 DA 48V CT VA RDA 20k DB C1 2.2μF VDD VZ GA R1 22k 24VDC 4A FAULTB GB SA SB VSS RDB 20k + D1 GREEN LED = MOSFETS GOOD CL 4×1000μF SUNCON ME-WX – M1 IPT020N10N3 117VAC VB M2 IPT020N10N3 4371 F23 Figure 23. Full Wave Center Tap Rectifier 4371f For more information www.linear.com/LTC4371 19 LTC4371 Package Description Please refer to http://www.linear.com/product/4371#packaging for the most recent package drawings. MS Package 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1661 Rev F) 0.889 ±0.127 (.035 ±.005) 5.10 (.201) MIN 3.20 – 3.45 (.126 – .136) 3.00 ±0.102 (.118 ±.004) (NOTE 3) 0.50 0.305 ±0.038 (.0197) (.0120 ±.0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) 10 9 8 7 6 3.00 ±0.102 (.118 ±.004) (NOTE 4) 4.90 ±0.152 (.193 ±.006) DETAIL “A” 0.497 ±0.076 (.0196 ±.003) REF 0° – 6° TYP GAUGE PLANE 1 2 3 4 5 0.53 ±0.152 (.021 ±.006) DETAIL “A” 0.18 (.007) SEATING PLANE 0.86 (.034) REF 1.10 (.043) MAX 0.17 – 0.27 (.007 – .011) TYP 0.50 (.0197) BSC NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 20 0.1016 ±0.0508 (.004 ±.002) MSOP (MS) 0213 REV F 4371f For more information www.linear.com/LTC4371 LTC4371 Package Description Please refer to http://www.linear.com/product/4371#packaging for the most recent package drawings. DD Package 10-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1699 Rev C) 0.70 ±0.05 3.55 ±0.05 1.65 ±0.05 2.15 ±0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 2.38 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 3.00 ±0.10 (4 SIDES) R = 0.125 TYP 6 0.40 ±0.10 10 1.65 ±0.10 (2 SIDES) PIN 1 NOTCH R = 0.20 OR 0.35 × 45° CHAMFER PIN 1 TOP MARK (SEE NOTE 6) 0.200 REF 0.75 ±0.05 0.00 – 0.05 5 1 (DD) DFN REV C 0310 0.25 ±0.05 0.50 BSC 2.38 ±0.10 (2 SIDES) BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 4371f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. For more information www.linear.com/LTC4371 21 LTC4371 Typical Application –48V Ideal Diode-OR with Fuse and Open MOSFET Detection RTN RZ 30k LTC4371 DA C1 2.2μF VDD VZ DB GA R1 33k FAULTB GB SA SB VSS D1 GREEN LED = FUSES/MOSFETS GOOD D2 1N4148W D3 1N4148W RDA 20k RDB 20k F1 VA –36V TO –72V VOUT 25A LOAD M1 IPT020N10N3 F2 VB –36V TO –72V M2 IPT020N10N3 4371 TA02 Related Parts PART NUMBER DESCRIPTION COMMENTS LTC4354 Negative Voltage Diode-OR Controller and Monitor Controls Two N-Channel MOSFETs, 1.2µs Turn-Off, –80V Operation LTC4355 Positive Voltage Diode-OR Controller and Monitor Controls Two N-Channel MOSFETs, 0.4µs Turn-Off, 80V Operation LTC4357 Positive Voltage Ideal Diode Controller Controls Single N-Channel MOSFET, 0.5µs Turn-Off, 80V Operation LT®4250 –48V Hot Swap Controller Active Current Limiting, Supplies from –20V to –80V LTC4251/LTC4251-1/ LTC4251-2 –48V Hot Swap Controllers in SOT-23 Fast Active Current Limiting, Supplies from –15V LTC4252-1/LTC4252-2/ LTC4252-A1/LTC4252-A2 –48V Hot Swap Controllers in MS8/MS10 Fast Active Current Limiting, Supplies from –15V, Drain Accelerated Response LTC4261/LTC4261-2 Negative Voltage Hot Swap Controllers with ADC and I2C Monitoring 10-Bit ADC, Floating Topology, Adjustable Inrush 22 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC4371 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC4371 4371f LT 0216 • PRINTED IN USA  LINEAR TECHNOLOGY CORPORATION 2016