LTC4372/LTC4373
Low Quiescent Current Ideal Diode Controller
FEATURES
DESCRIPTION
Reduces Power Dissipation by Replacing a Power
Schottky Diode
n Low Quiescent Current: 5µA Operating
n Wide Operating Voltage Range: 2.5V to 80V
n Reverse Supply Protection to –28V
n No TVS Input Clamps Required
n High Side External N-Channel MOSFET Drive
n Drives Back-to-Back MOSFETs for Inrush Control and
Load Switching
n Shutdown Input for ON/OFF Control
n Fast Reverse Current Turn-Off within 1.5µs
n 8-Lead MSOP and 3mm × 3mm DFN Packages
The LTC®4372/LTC4373 are positive high voltage ideal
diode controllers that drive an external N-channel MOSFET
to replace a Schottky diode. They control the forward voltage drop across the MOSFET to ensure current delivery
or current transfer from one path to the other even at
light loads.
APPLICATIONS
The LTC4372’s SHDN pin keeps the MOSFET off and
reduces the quiescent current to 3.5µA. The LTC4373 has
a UV pin for undervoltage monitoring while the UVOUT
pin provides hysteresis adjustment and status information. During undervoltage, the back-to-back MOSFETs are
cut off and quiescent current reduces to 0.5μA.
n
Automotive Battery Protection
Redundant Power Supplies
n Portable Instrumentation
n Solar Powered Systems
n Energy Harvesting Applications
n Supply Holdup
n
n
A 5µA operating current achieves high efficiency for intermittent load applications or always-on backup power supplies. If a power source fails or is shorted, a fast turnoff minimizes reverse current transients. The LTC4372/
LTC4373 control back-to-back N-channel MOSFETs for
inrush current control and load switching.
All registered trademarks and trademarks are the property of their respective owners.
TYPICAL APPLICATION
Power Dissipation vs Load Current
12V, 20A Reverse Battery Protection
VOUT
12V
20A
BSC026N08NS5
VIN = 12V
IN
2UPU
GND
SOURCE
GATE
OUT
10μF
LTC4372
SHDN
INTVCC
43723 TA01a
POWER DISSIPATION (W)
10
100nF
8
SCHOTTKY DIODE (SBG2040CT)
6
POWER
SAVED
4
2
MOSFET (BSC026N08NS5)
0
0
5
10
15
20
CURRENT (A)
43723 TA01b
Rev. A
Document Feedback
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1
LTC4372/LTC4373
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
IN, SOURCE................................................–28V to 100V
OUT...............................................................–2V to 100V
IN – OUT ..................................................–100V to 100V
IN – SOURCE................................................–1V to 100V
SOURCE – OUT.........................................–100V to 100V
GATE – SOURCE (Note 3)........................... –0.3V to 10V
SHDN, UV, 2UPU, UVOUT......................... –0.3V to 100V
INTVCC.......................................................... –0.3V to 6V
Operating Ambient Temperature Range
LTC4372C, LTC4373C............................... 0°C to 70°C
LTC4372I, LTC4373I.............................–40°C to 85°C
LTC4372H, LTC4373H........................ –40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 Sec)
MSOP Package.................................................. 300°C
PIN CONFIGURATION
LTC4372
LTC4372
TOP VIEW
OUT
1
GATE
2
SOURCE
3
IN
4
TOP VIEW
8 SHDN
9
OUT
GATE
SOURCE
IN
7 2UPU
6 GND
5 INTVCC
LTC4373
TOP VIEW
OUT
1
GATE
2
SOURCE
3
IN
4
TOP VIEW
8 UV
9
OUT
GATE
SOURCE
IN
7 UVOUT
6 GND
5 INTVCC
DD PACKAGE
8-LEAD (3mm × 3mm) PLASTIC DFN
TJMAX = 150°C, θJA = 43°C/W
EXPOSED PAD (PIN 9) PCB CONNECTION TO GND IS OPTIONAL
2
SHDN
2UPU
GND
INTVCC
MS8 PACKAGE
8-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 163°C/W
DD PACKAGE
8-LEAD (3mm × 3mm) PLASTIC DFN
TJMAX = 150°C, θJA = 43°C/W
EXPOSED PAD (PIN 9) PCB CONNECTION TO GND IS OPTIONAL
LTC4373
8
7
6
5
1
2
3
4
1
2
3
4
8
7
6
5
UV
UVOUT
GND
INTVCC
MS8 PACKAGE
8-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 163°C/W
Rev. A
For more information www.analog.com
LTC4372/LTC4373
ORDER INFORMATION
TUBE
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4372CDD#PBF
LTC4372CDD#TRPBF
LHGR
8-Lead (3mm × 3mm) Plastic DFN
0°C to 70°C
LTC4372IDD#PBF
LTC4372IDD#TRPBF
LHGR
8-Lead (3mm × 3mm) Plastic DFN
–40°C to 85°C
LTC4372HDD#PBF
LTC4372HDD#TRPBF
LHGR
8-Lead (3mm × 3mm) Plastic DFN
–40°C to 125°C
LTC4372CMS8#PBF
LTC4372CMS8#TRPBF
LTHGS
8-Lead Plastic MSOP
0°C to 70°C
LTC4372IMS8#PBF
LTC4372IMS8#TRPBF
LTHGS
8-Lead Plastic MSOP
–40°C to 85°C
LTC4372HMS8#PBF
LTC4372HMS8#TRPBF
LTHGS
8-Lead Plastic MSOP
–40°C to 125°C
LTC4373CDD#PBF
LTC4373CDD#TRPBF
LHMQ
8-Lead (3mm × 3mm) Plastic DFN
0°C to 70°C
LTC4373IDD#PBF
LTC4373IDD#TRPBF
LHMQ
8-Lead (3mm × 3mm) Plastic DFN
–40°C to 85°C
LTC4373HDD#PBF
LTC4373HDD#TRPBF
LHMQ
8-Lead (3mm × 3mm) Plastic DFN
–40°C to 125°C
LTC4373CMS8#PBF
LTC4373CMS8#TRPBF
LTHMR
8-Lead Plastic MSOP
0°C to 70°C
LTC4373IMS8#PBF
LTC4373IMS8#TRPBF
LTHMR
8-Lead Plastic MSOP
–40°C to 85°C
LTC4373HMS8#PBF
LTC4373HMS8#TRPBF
LTHMR
8-Lead Plastic MSOP
–40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. IN = SOURCE =12V, SHDN = 0V, UV = 2V unless otherwise noted.
SYMBOL
PARAMETER
VIN
Input Supply Voltage Range
VIN(UVL)
Input Supply Undervoltage Lockout
∆VIN(HYST)
Input Supply Undervoltage Lockout Hysteresis
VINTVCC
Internal Regulator Voltage
IINTVCC = 0 to –10µA
l
IQ
Total Supply Current
Diode Control: IGATE = –0.1µA
Single or Back-to-Back MOSFETs (Note 4)
(C-Grade, I-Grade)
(H-Grade)
IQ = IIN + ISOURCE + IOUT
CONDITIONS
IN Rising
MIN
l
2.5
l
1.9
TYP
MAX
80
V
2.1
2.45
V
80
2.5
UNITS
mV
3.5
4.5
V
l
l
5
5
10
20
µA
µA
Shutdown: SHDN = 2V, UV = 0V
Single MOSFET
Back-to-Back MOSFETs
l
l
3.5
0.5
10
2.5
µA
µA
Reverse Current: ∆VSD = –0.1V, IN = 12V
Single MOSFET
Back-to-Back MOSFETs
l
l
20
10
30
20
µA
µA
IOUT
OUT Current
IN – OUT = 4V
IN – OUT = –4V
l
l
–0.5
1.8
–10
5
µA
µA
INEG
IN + SOURCE Current During
Reverse Battery
IN = SOURCE = –24V, OUT = 24V
l
–1
–5
mA
IOUT(NEG)
OUT Current During Reverse Battery
IN = SOURCE = –24V, OUT = 24V
l
0.3
0.5
mA
∆VSD(T)
Source-Drain Threshold (IN-OUT)
Low to High. Activates IGATE(UP)
l
20
30
45
mV
∆VGATE(H)
Maximum GATE Drive (GATE-SOURCE)
IN ≤ 5V, ∆VSD = 0.1V, IGATE = 0, –1µA
IN > 5V, ∆VSD = 0.1V, IGATE = 0, –1µA
l
l
4.5
10
6.5
11.7
10
16
V
V
IGATE(UP)
GATE Pull-Up Current
GATE = IN, ∆VSD = 0.1V
l
–15
–20
–25
µA
Rev. A
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3
LTC4372/LTC4373
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. IN = SOURCE =12V, SHDN = 0V, UV = 2V unless otherwise noted.
SYMBOL
PARAMETER
IGATE(DOWN) GATE Pull-Down Current
VGATE(NEG)
GND-GATE clamp
VSOURCE(TH) Reverse SOURCE Threshold for GATE Off
CONDITIONS
MIN
TYP
MAX
Shutdown: SHDN = 2V, UV = 0V, ∆VGATE = 5V
l
0.5
1
3
mA
Reverse Current: ∆VSD = –0.1V, ∆VGATE = 5V
l
70
130
230
mA
Reverse Battery: IN = SOURCE = –7V, GATE = –3V
l
70
130
230
mA
IGATE = 10mA (Note 3)
l
–28
–32
–35
V
GATE = 0V (Note 5)
l
–0.9
–1.8
–2.7
V
0.5
1.5
µs
tOFF
Gate Turn-Off Delay Time
ΔVSD = Step 0.1V to –0.8V, CGATE = 0pF, ΔVGATE 4.5V,
CGATE = 0pF, SHDN = 2V to 0V, UV = 0V to 1.25V
UNITS
l
100
500
1200
µs
l
–1
–2
–3
µA
l
1
1.2
1.4
V
l
2
15
40
mV
±1
±50
nA
V
LTC4372
I2UPU
2UPU Pull-Up Current
VSHDN
SHDN Threshold
SHDN Falling
VSHDN(HYST) SHDN Threshold Hysteresis
SHDN Leakage Current
SHDN = 1.2V
l
VUV
UV Threshold
UV Falling
l
1.174
1.191
1.208
VUV(HYST)
UV Threshold Hysteresis
l
2
IUV(LK)
UV Leakage Current
IUVOUT(LK)
UVOUT Leakage Current
ISHDN
LTC4373
15
40
mV
UV = 1.2V
l
±1
±50
nA
UV = 2V, UVOUT = 1.2V
(C-Grade, I-Grade)
(H-Grade)
l
l
±1
±1
±50
±200
nA
nA
I = 2mA
l
RUVOUT#
UVOUT Output Low Resistance
tUV
Under Voltage Detect to UVOUT Assert Low UV = Step 1.25V to 1.1V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into device pins are positive; all currents out of
device pins are negative. All voltages are referenced to GND unless
otherwise specified.
Note 3: An internal clamp limits the GATE pin to a minimum of 10V above
SOURCE or 100V above GND. A second internal clamp limits the GATE pin
to a minimum of 28V below GND. Driving this pin to voltages beyond the
clamp may damage the device.
4
l
10
140
500
Ω
50
300
µs
Note 4: When testing the single MOSFET configuration, IN is connected to
SOURCE. When testing the back-to-back MOSFET configuration, SOURCE
is left unconnected.
Note 5: SOURCE ≤ –1.8V triggers a 130mA pull-down current from GATE
to SOURCE. An internal clamp limits the GATE pin to a minimum of 28V
below GND. Driving SOURCE to voltages beyond the clamp may damage
the device.
Rev. A
For more information www.analog.com
LTC4372/LTC4373
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C. IN = SOURCE = 12V, SHDN = 0V,
UV = 2V unless otherwise noted.
6.0
Total Supply Current
vs Load Current
Total Supply Current vs VIN
Total Supply Current vs
Temperature
8
40
NFET = IPB107N20N3G
CLOAD = 10µF
7 IGATE = –0.1µA
NFET = IPB107N20N3G
CLOAD = 10µF, ILOAD = 50mA
IGATE = –0.1µA
5.5
NFET = IPB107N20N3G
CLOAD = 10µF, ILOAD =100mA
IGATE = –0.1µA
30
5.0
IQ (µA)
IQ (µA)
IQ (µA)
6
5
20
4
4.5
10
3
4.0
0
10
20
30
40 50
VIN (V)
60
70
2
80
1µ
10µ 100µ
1m 10m 100m
ILOAD (A)
43723 G01
Total Supply Current
vs
GATECurrent
Leakage
Supply
vs GATE leakage
0.60
1k
1
0
–50 –25
10
0
25 50 75 100 125 150
TEMPERATURE (°C)
43723 G02
43723 G03
Total Supply Current (Shutdown)
vs VIN
Total Supply Current (Shutdown)
vs Temperature
8
SHDN = 2V, UV = 0V
BACK-TO-BACK MOSFETs
SHDN = 2V, UV = 0V
7 BACK-TO-BACK MOSFETs
0.55
6
100
IQ (µA)
IQ (µA)
IQ (µA)
5
0.50
4
3
10
0.45
2
1
1
0.01
0.1
1
10
–IGATE (µA)
100
0.40
10
20
43723 G4
IN Current
60
0
30
40 50
VIN (V)
60
70
0
–50 –25
80
IN = SOURCE
OUT = 12V
OUT = 75V
50
IN = SOURCE
43723 G06
OUT Current
3.0
OUT = 12V
OUT = 75V
10
25 50 75 100 125 150
TEMPERATURE (°C)
43723 G05
SOURCE Current
12
0
IN = SOURCE = 12V
IN = SOURCE = 75V
2.5
2.0
30
20
8
IOUT (µA)
ISOURCE (µA)
IIN (µA)
40
6
4
1.5
1.0
0.5
0
10
0
2
0
10
20
30
40 50
VIN (V)
60
70
80
43723 G07
0
–0.5
0
10
20
30 40 50
VSOURCE (V)
60
70
80
43723 G08
–1.0
0
10
20
30
40 50
VOUT (V)
60
70
80
43723 G09
Rev. A
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5
LTC4372/LTC4373
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C. IN = SOURCE = 12V, SHDN = 0V,
UV = 2V unless otherwise noted.
Pin
Pin Current
Current at
at Shutdown
Shutdown
Pin Current at Negative Input
–1000
10
IN = SOURCE, OUT = 50V
ISOURCE
IIN
CURRENT (µA)
IOUT (µA)
IOUT
–400
0.01
ISOURCE
SHDN = 2V/UV = 0V
0
10
20
30 40 50
VOLTAGE (V)
60
70
0
80
GATE Current
vs Forward Voltage Drop
–25
100
50
0
–5
–10
–15
–20
VIN (V)
–25
1000
IN = SOURCE = 5V
12
∆VGATE (V)
–10 ∆VSD HIGH TO LOW
–5
15 20 25
∆VSD (mV)
30
35
8
IN = SOURCE = 2.5V
6
0
40
0
–5
–10
–15
IGATE (µA)
–20
VUV (V)
t OFF (µs)
2
10
6
–1
4
6
CGATE (nF)
8
10
43723 G15
Load Current vs VFWD
FDMS86101
Si4190ADY
8
1.19
–0.8
2
VUV LOW TO HIGH
VUV HIGH TO LOW
–0.4
–0.6
FINAL ∆VSD (V)
0
43723 G14
1.20
1
–0.2
0
–25
1.22
∆VSD = 50mV STEP TO FINAL ∆VSD
0
IN = SOURCE = 12V
∆VSD = 50mV STEP TO –0.8V
500
UV Threshold
vs Temperature
1.21
0
–30
43723 G12
250
43723 G13
GATE Turn-Off Time
vs Forward Overdrive
3
–25
750
CURRENT (A)
10
–15
–20
VIN (V)
2
∆VSD LOW TO HIGH
5
–10
10
4
0
–5
GATE Turn-Off Time
vs GATE Capacitance
14
–15
0
0
43723 G11
16
IN = SOURCE = 12V
GATE = SOURCE + 3V
–5
0
–30
∆VGATE (Average)
vs GATE Leakage
–20
5
150
–200
43723 G10
IGATE (µA)
200
–600
TOFF (ns)
CURRENT (µA)
IIN
0.1
IN = SOURCE
OUT = 50V
250
–800
1
0.001
OUT Current at Negative Input
300
1.18
–50 –25
6
IPB107N20N3G
4
2
0
25 50 75 100 125 150
TEMPERATURE (°C)
43723 G16
43723 G17
0
0
25
50
∆VSD (mV)
75
100
43723 G18
Rev. A
For more information www.analog.com
LTC4372/LTC4373
PIN FUNCTIONS
Exposed Pad (DD Package Only) : Exposed pad may be
left open or connected to device ground.
GATE: MOSFET Gate Drive Output. The LTC4372/LTC4373
control the gate of the MOSFET to maintain the voltage
drop between 0mV to 30mV using a pulsed control
method. If reverse current flows, a fast pull-down circuit connects GATE to SOURCE within 0.5μs, turning off
the MOSFET.
GND: Device Ground.
IN: Voltage Sense and Supply Voltage. IN is the anode of
the ideal diode. The voltage sensed at this pin is used to
control the MOSFET gate for forward voltage regulation
and reverse current turn-off. The positive supply input
ranges from 2.5V to 80V for normal operation. It can go
below GND by up to 28V during a reverse battery condition without damaging the part.
INTVCC: Internal 3V Supply Decoupling Output. Connect
a 0.1μF or larger capacitor to this pin. An external load of
less than 10µA can be connected at this pin.
OUT: MOSFET Drain Voltage Sense. OUT is the cathode
of the ideal diode and the common output when multiple
LTC4372/LTC4373’s are configured as an ideal diode-OR.
It connects to the drain of the N-channel MOSFET. The
voltage sensed at this pin is used to control the MOSFET
gate for forward voltage regulation and reverse current
turn-off. OUT is used as the supply to hold the MOSFET
off when IN is not available (below UVLO). Connect a 10µF
or larger capacitor to this pin.
SHDN (LTC4372): Shutdown Control Input. The LTC4372
can be shut down to a low current mode by pulling SHDN
above 1.215V. Connect to GND if unused.
SOURCE: MOSFET Source Connection. SOURCE is the
return path of the GATE fast pull-down. Connect this
pin as close as possible to the source of the external
N-channel MOSFET.
2UPU (LTC4372): 2μA Pull-Up Output. This pin has a
2μA pull-up to INTVCC. It can be connected to SHDN to
facilitate on/off control of the LTC4372 by a microcontroller’s open-drain output. If unused, leave open or connect
to INTVCC.
UVOUT (LTC4373): UV Status Output. Open Drain output
that pulls low when UV goes below 1.191V (VUV) and goes
high impedance when UV exceeds 1.191V. UVOUT can be
used to adjust hysteresis for the UV monitor. This pin may
be left open or connected to GND if unused.
UV (LTC4373): Undervoltage Detection Input. The
LTC4373 goes into a low current shutdown mode when
UV is below 1.191V. Connect to INTVCC if unused.
Rev. A
For more information www.analog.com
7
LTC4372/LTC4373
BLOCK DIAGRAM
IN
LTC4372
SOURCE
OUT
GATE
11.7V
32V
–
+
–
INTVCC
REGULATOR
+
–
INTVCC
IN
HYSTERETIC
GATE DRIVER
REVERSE
CURRENT
–
+
+
–1.8V
CHARGE
PUMP
f = 2MHz
NEGATIVE
COMP
+
–
30mV
30mV
2μA
2UPU
SHDN
+
–
1.2V
SHDN
COMP
GND
IN
LTC4373
SOURCE
OUT
GATE
11.7V
32V
–
REVERSE
CURRENT
UV
+
–
INTVCC
REGULATOR
1.191V
+
–
INTVCC
HYSTERETIC
GATE DRIVER
30mV
IN
–
+
+
–1.8V
CHARGE
PUMP
f = 2MHz
NEGATIVE
COMP
+
–
30mV
UV
COMP
+
–
UVOUT
+
–
C1
1.191V
GND
43723 BD
8
Rev. A
For more information www.analog.com
LTC4372/LTC4373
OPERATION
Blocking diodes are commonly placed in series with supply inputs for ORing redundant supplies and protecting
against supply reversal. The LTC4372/LTC4373 replace
the diodes such as in portable equipment and automotive applications with N-channel MOSFETs acting as ideal
diodes. The forward voltage drop reduces as shown in
Figure 1, a feature that is readily appreciated at low input
voltages where headroom is tight.
20
CURRENT (A)
15
MOSFET
(BSC026N08NS5)
10
SCHOTTKY DIODE
(SBG2040CT)
5
0
0.0
0.1
0.2
0.3
VOLTAGE (V)
0.4
0.5
43723 F01
Figure 1. Forward Voltage Drop Comparison Between MOSFET
and Schottky Diode
As a result of this lower forward voltage drop, there is a
dramatic reduction in power loss achieved in a practical
application as shown in the Typical Application curve on
Page 1. This represents significant savings in board area
by greatly reducing heat sinking requirements of the pass
device. In addition to these two desirable properties, the
LTC4372/LTC4373 feature a low operating current (5µA)
and shutdown current (0.5µA). This increases efficiency
in applications where the ideal diode is used for intermittent loads or always on standby channels, making the
LTC4372/LTC4373 suitable for battery powered applications in the portable instrumentation, automotive and
renewable energy fields.
The source of the external MOSFET is connected to IN
and SOURCE while its drain is connected to OUT. The
LTC4372/LTC4373 control the gate of the MOSFET to
regulate the voltage drop across the pass transistor to
less than 30mV.
In the event of a rapid drop in input voltage, such as an
input short-circuit fault or negative-going voltage spike,
reverse current temporarily flows through the MOSFET.
This current is provided by any load capacitance and
by other supplies or batteries that feed the output in
diode-OR applications. The reverse current comparator
quickly responds to this condition by turning the MOSFET
off in 500ns. This fast turn-off prevents the reverse current from ramping up to a damaging level, thus minimizing the disturbance to the output bus.
IN, SOURCE and GATE are protected against reverse
inputs of up to –28V. The negative comparator detects
negative input potentials at SOURCE and quickly connects
GATE to SOURCE, turning off the MOSFET and isolating
the load from the negative input.
For the LTC4372, driving SHDN high pulls the MOSFET
gate down to SOURCE with a 1mA pull-down. IQ reduces
to 0.5μA for a back-to-back MOSFET configuration and
GATE is held low with a 3μA pull-down to GND. When
SHDN goes low, the LTC4372 ramps GATE up to turn on
the external MOSFET. 2UPU has a 2μA pull-up to INTVCC
which can be connected to SHDN to facilitate on/off control by a microcontroller’s open-drain output.
The LTC4373 can monitor the input voltage via an external resistive voltage divider to UV. When UV goes below
1.191V, GATE pulls down to SOURCE with a 1mA pulldown and UVOUT pulls low. IQ reduces to 0.5μA for a
back-to-back MOSFET configuration and GATE is held low
with a 3μA pull down to GND. When UV recovers above
VUV + VUV(HYST), the LTC4373 ramps GATE up to turn on
the external MOSFET. An optional resistor can be connected between UV and UVOUT to configure an external
hysteresis to override VUV(HYST).
Rev. A
For more information www.analog.com
9
LTC4372/LTC4373
APPLICATIONS INFORMATION
The LTC4372/LTC4373 operate from 2.5V to 80V and
withstands an absolute maximum range of –28V to 100V
without damage. In automotive applications the LTC4372/
LTC4373 can operate through load dump, cold crank and
two-battery jump starts, and survive reverse battery connections while protecting the load.
A 12V/20A ideal diode application is shown in Figure 2.
The following sections cover power-on, ideal diode operation, shutdown and various faults that the LTC4372/
LTC4373 detect and act upon.
M1
BSC026N08NS5
VIN = 12V
IN
2UPU
GND
SOURCE
GATE
OUT
COUT
10μF
IN
12V
IN, OUT
20mV/DIV
OUT
GATE
IN, GATE
5V/DIV
12V
IN
50ms/DIV
VOUT
12V
20A
LTC4372
SHDN
Figure 5 shows a typical OUT ripple at an ILOAD of 16A for
the circuit shown in Figure 2.
IGATE(LEAKAGE) = 100nA
Figure 3. Regulating ΔVSD at Low ILOAD = 1µA
INTVCC
43723 F02
12V
IN, OUT
20mV/DIV
C1
100nF
43723 F03
IN
OUT
Figure 2. 12V/20A Ideal Diode with Reverse Input Protection
Power-On and Ideal Diode Operation
When power is applied, the initial load current flows
through the body diode of the MOSFET M1. When IN
exceeds the UVLO level of 2.1V and SHDN is low or UV is
high, the LTC4372/LTC4373 begin operation. An internal
charge pump asserts a 20µA pull-up on GATE to enhance
the MOSFET. To achieve a low supply current, the LTC4372/
LTC4373 employ a pulsed control style of operation where
the internal charge pump is not always on. Instead, the
charge pump periodically wakes up to recharge GATE after
it droops from leakage to keep ∆VSD ≤ 30mV. This pulsed
control creates a voltage ripple at OUT even with a stable
DC load. The amplitude of this ripple is dependent on gate
leakage, GATE capacitance, the load condition and the size
of the bypass capacitance at OUT. At low load or no-load
condition, this ripple can increase to 30mVPK–PK. Figure 3
shows a typical OUT ripple at an ultralight ILOAD of 1µA
for the circuit shown in Figure 2.
With a moderate DC load, the ripple amplitude is about
10mVpk-pk. Figure 4 shows a typical OUT ripple at a moderate ILOAD of 2A for the circuit shown in Figure 2.
10
GATE
IN, GATE
5V/DIV
12V
IN
5ms/DIV
43723 F04
IGATE(LEAKAGE) = 100nA
Figure 4. Regulating ΔVSD at Moderate ILOAD = 2A
IN
12V
IN, OUT
20mV/DIV
OUT
GATE
IN, GATE
5V/DIV
12V
IN
10ms/DIV
43723 F05
IGATE(LEAKAGE) = 100nA
Figure 5. Regulating ΔVGATE at High ILOAD = 16A
Rev. A
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LTC4372/LTC4373
APPLICATIONS INFORMATION
As the load current increases, GATE is driven higher and
higher until a point is reached where ∆VGATE reaches
the maximum overdrive that the internal charge pump is
capable of (∆VGATE(H)) but ∆VSD is still above 30mV. In
this situation, the internal charge pump will periodically
turn on to recharge GATE as needed to keep ∆VGATE
between ∆VGATE(H) and ∆VGATE(H) – 0.7V. ∆VSD is then
equal to RDS(ON) • ILOAD. There is now insignificant
ripple on OUT as the 0.7Vpk-pk ripple on ∆VGATE has
little effect on the MOSFET RON.
Achieving Low Average IQ
To lower average IQ in diode control mode when GATE
is high, the LTC4372/LTC4373 operate by turning on
the charge pump periodically. When in charge pump
sleep mode, the IQ is 3.5μA. Once the charge pump is
turned on to deliver a current pulse to GATE, IQ goes up
to 300μA. The average IQ will depend on how often the
charge pump is turned on and this is affected by GATE
leakage, GATE capacitance, OUT bypass capacitance and
ILOAD. To achieve the lowest possible average IQ, minimize GATE leakage and ensure that GATE has a moderate
capacitance (>1nF). If the CGS of the MOSFET does not
already exceed this, add a 1nF capacitor between GATE
and SOURCE. CLOAD may be placed nearer to the load but
an OUT bypass capacitance of at least 10μF low ESR and
ESL electrolytic or ceramic is required close to the drain
pin of MOSFET M1 (see Figure 6a). Average IQ for Diode
Control mode can be estimated by Equation 1.
AVERAGE IQ = 3.5 +
IGATE(LEAKAGE)
IGATE(UP)
• 300µA
(1)
The Typical Performance Characteristics section shows
relationship of IQ with IGATE(LEAKAGE) and ILOAD.
MOSFET Selection
The LTC4372/LTC4373 drive N-channel MOSFETs to
conduct the load current. The important characteristics of the MOSFET are the gate threshold voltage
VGS(TH), the maximum drain-source voltage BVDSS and
on-resistance RDS(ON).
Gate drive is compatible with 4.5V logic-level MOSFETs
over the entire operating range of 2.5V to 80V. In applications with supply voltages above 5V, standard 10V threshold MOSFETs may be used. An internal clamp limits the
gate drive to 16V maximum between GATE and SOURCE.
The maximum allowable drain-source voltage, BVDSS,
must be higher than the power supply voltage. If the input
is grounded, the full supply voltage will appear across the
MOSFET. If a reverse battery is possible and the output
is held up by a charged capacitor, battery or power supply, then the sum of the input and output voltages will
appear across the MOSFET and BVDSS must be higher
than VOUT+|VIN|.
The MOSFET’s on-resistance, RDS(ON), directly affects
the forward voltage drop and power dissipation during a
heavy load. Desired forward voltage drop (VFWD) should
be less than that of a diode for reduced power dissipation; 50mV is a good starting point. Since the LTC4372/
LTC4373 drop at least 30mV across the MOSFET, a very
low RDS(ON) may be wasted. Choose a MOSFET using
Equation 2.
RDS(ON) <
VFWD
ILOAD
(2)
The resulting power dissipation is shown in Equation 3.
Pd = ILOAD2 • RDS(ON)
(3)
Input Short-Circuit Faults
Input short-circuits that cause reverse current to flow can
occur in many ways. Some examples include PCB traces
getting accidentally shorted or bypass capacitors in the
upstream power supply failing shorted. The LTC4372/
LTC4373 utilize the external MOSFETs to add rugged input
short-circuit protection without using large TVS clamps
or capacitors.
Figure 6a models a low impedance input short with a
switch. When the short-circuit switch closes, reverse current builds up in LIN, LOUT and M1 in the direction shown.
The LTC4372/LTC4373 detect the reverse current quickly
and activate the internal 130mA GATE to SOURCE pulldown current to turn M1 off. The reverse current build up
Rev. A
For more information www.analog.com
11
LTC4372/LTC4373
APPLICATIONS INFORMATION
REVERSE CURRENT
VIN
LS
SOURCE
PARASITIC
INDUCTANCE
+
–
LIN
INPUT
PARASITIC
INDUCTANCE
+
–
INPUT
SHORT
LOUT
OUTPUT
PARASITIC
INDUCTANCE
+
–
M1
BSC026N08NS5
IN
SOURCE
GATE
OUT
VOUT
CLOAD
COUT
10μF
LTC4372
GND
D1
SMAJ33A
(OPTIONAL)
GATE
GATE, IN
GND
10V/DIV
IN
GND
0V
I(M1)
20A/DIV
0A
SHDN
43723 F06a
RGND
D4
1N4148W
(FOR VIN > 13.2V)
500ns/DIV
43723 F06b
COUT = 10μF
(a)
(b)
Figure 6. Reverse Recovery Produces Inductive Spikes at IN, SOURCE and OUT. The Polarity of
Inductive Spike is Shown Across Parasitic Inductances
in LIN and LOUT is interrupted and this causes IN to spike
negative and OUT to spike positive. At OUT, COUT clamps
the positive going spike caused by LOUT and commutates
I(LOUT) to zero. At IN, the internal GND – GATE clamp
asserts and holds GATE to 32V below GND, this causes M1
to turn back on as IN/SOURCE undershoots below GATE.
The current in LIN is diverted by M1 to COUT and safely
commutates to zero as shown in the short-circuit transient
of Figure 6b. If these transients cause too large of a ∆V at
OUT, increase the capacitance of COUT or add a TVS D1.
If a low source resistance power supply drives VIN, large
currents can build up in LS during the short-circuit.
When the short-circuit goes away, I(LS) can cause IN and
SOURCE to spike positive until it is held by M1 body diode
to COUT. This fast slew rate at SOURCE can cause a large
shoot-through current to flow into the part from SOURCE
to GND potentially causing damage. Adding an external
RGND will limit this current to a safe level.
For applications where IN ≤ 13.2V, a 0805 size 100Ω for
RGND is sufficient. For applications where IN > 13.2V, a
larger value RGND, 1k, is necessary. To keep GND from
going too negative when the GND – GATE clamp turns
on, a fast recovery diode like the 1N4148W is placed in
parallel with the 1k RGND.
For back-to-back MOSFET applications where SOURCE
is not driven by VIN, RGND is not needed. RGND can also
be omitted for a single MOSFET application driven by a
12
power supply with a large source impedance. VIN collapses during the short-circuit and cannot build up current in LS. SOURCE will not see fast slew rates when the
short-circuit goes away.
Using the external MOSFETs to commutate the parasitic
inductor currents during an input short-circuit is feasible
with input voltages up to 33V. This ensures that during
the transient, the IN – OUT Absolute Maximum Voltage of
±100V is not exceeded. During the short-circuit transient,
the MOSFET VDS sees |VGND|+|VGATE(NEG)|+VTH(M1)+VOUT.
Choose the MOSFET BVDSS accordingly. For other techniques to protect the LTC4372/LTC4373 during input
short-circuits see the Design Examples section.
Reverse Input Protection
Negative voltages at IN can also occur if a battery
is plugged in backwards or a negative supply is inadvertently connected. Figure 7 shows the waveforms when the
application circuit in Figure 2 is hot plugged to –24V. Due
to the parasitic inductance in between input and IN/
SOURCE, the voltages at the pins can ring significantly
below –24V. Similar to the input short-circuit situation,
the GND – GATE clamp causes M1 to divert the current
in the parasitic inductances to COUT. The GND – GATE
clamp limits the maximum DC negative voltage that the
Figure 2 application can handle to –28V.
For more information www.analog.com
Rev. A
LTC4372/LTC4373
APPLICATIONS INFORMATION
I(M1)
2A/DIV
5V
INA, INB
50mV/DIV
SOURCE
20V/DIV
GATE
20V/DIV
GATEA,
GATEB
2V/DIV
5V
VGATE-SOURCE
10V/DIV
OUT
1V/DIV
43723 F07
1μs/DIV
Multiple LTC4372/LTC4373’s can be used to combine the
outputs of two or more supplies for redundancy or for
droop sharing, as shown in Figure 8. For redundant supplies, the supply with the highest output voltage sources
most or all of the load current. Figure 9a and Figure 9b
show the load transition between the two redundant
power supplies.
INA
POWER
SUPPLY
A
+
–
IN
SOURCE GATE
GND
SHDN
OUT
INTVCC
C1A
100nF
COUT
100µF
RGNDA
100Ω
POWER
SUPPLY
B
+
–
IN
SOURCE GATE
OUT
U1B
LTC4372
2UPU
GND
SHDN
43723 F09a
I(M1A)
0.5A/DIV
0A
I(M1B)
0.5A/DIV
0A
5V
OUT
50mV/DIV
50ms/DIV
43723 F09b
IGATEA(LEAKAGE)= IGATEB(LEAKAGE) =100nA
(b)
INTVCC
C1B
100nF
RGNDB
100Ω
Figure 8. Redundant Power Supplies
supply (INA) from the supply ramping higher (INB). The
reverse current may cause INA to rise, with the amount
of voltage rise dependent on the input supply's impedance. The safest course of action is to use capacitors on
the input supply whose voltage rating is higher than the
highest voltage in the system, or to consider protecting
these capacitors with a TVS, for example.
If the higher supply’s input is shorted to ground while
delivering load current, the flow of current temporarily
reverses and flows backwards through the higher supply’s MOSFET. The LTC4372/LTC4372 sense this reverse
current and activate a fast pull-down to quickly turn off
the MOSFET.
M1B
Si4190ADY
INB
GATEB
Figure 9. Load Transition of Redundant Power Supplies
U1A
LTC4372
2UPU
GATEA
(a)
Depending on INA and INB’s supply impedances,
slew rates and the transient response of the LTC4372/
LTC4373, a transient reverse current might flow into lower
M1A
Si4190ADY
INB
50ms/DIV
Figure 7. LTC4372/LTC4373 Handling Reverse Input
Paralleling Supplies
INA
43723 F08
If all the load current was supplied by the channel that suffered the short, the output will fall until the body diode of the
next MOSFET conducts. Meanwhile, the LTC4372/LTC4372
charge the MOSFET gate with 20μA until the forward drop
Rev. A
For more information www.analog.com
13
LTC4372/LTC4373
APPLICATIONS INFORMATION
is reduced to 30mV. If this supply was sharing load current at the time of the fault, its associated ORing MOSFET
was already servoed to less than 30mV drop. In this case,
the LTC4372/LTC4372 will simply drive the MOSFET gate
higher to maintain a drop of 30mV at full load.
Load sharing can be accomplished if both power supply output voltages and source impedances are nearly
equal. The 30mV regulation technique allows load sharing
between outputs. The degree of sharing is a function of
MOSFET RDS(ON), the source impedance of the supplies
and their initial output voltages.
Using the LTC4372’s SHDN and 2UPU
When SHDN goes high, the LTC4372 enters shutdown
and asserts a 1mA pull-down between GATE and SOURCE
to turn off the external MOSFET. It also turns off most of
the internal circuitry, reducing IIN to 0.5μA. GATE is held
low with a 3μA pull-down to GND. If IN and SOURCE are
connected together, IQ = 3.0μA + 0.5μA = 3.5μA.
Shutting down the part does not interrupt forward current
flow as a path is still present through M1’s body diode. A
second MOSFET may be added to block the forward path (see
Figure 10). In this case, GATE and SOURCE are pulled to GND
during shutdown. The 3μA pull-down on GATE is pinched off
and IQ = 0.5μA. With back-to-back MOSFETs, SHDN serves
as an on/off control for the forward path, as well as enabling
the diode function. When SHDN is driven low, the LTC4372
exits shutdown and re-enters ideal diode operation.
M2
BSC026N08NS5
VIN
24V
D3
SMAJ28A
28V
M1
BSC026N08NS5
COUT
10µF
R2
1k
R1
10Ω
VOUT
24V
10A
C2
10nF
D2
SMAJ33A
33V
IN
SOURCE
SHDN
OUT
LTC4372
GND
OFF ON
GATE
2UPU
M3
BSS138N
INTVCC
43723 F10
C1
100nF
Figure 10. 24V Load Switch and Ideal Diode with Inrush Control
and Reverse Input Protection
14
If SHDN is not needed, connect it to GND. SHDN may
be driven with a 3.3V or 5V logic signal. It can also be
driven with an open-drain or collector output with SHDN
tied to 2UPU. 2UPU provides an internal pull up current
of 2μA to INTVCC. For higher pull-up currents, connect a
resistor from SHDN to INTVCC (capable of supplying up
to 10μA) or IN.
Load Switching and Inrush Control
By adding a second MOSFET as shown in Figure 10, the
LTC4372/LTC4373 can be used to control power flow in
the forward direction while retaining ideal diode behavior in the reverse direction. The body diodes of M1 and
M2 prohibit current flow when the MOSFETs are off. M1
serves as the ideal diode while M2 acts as a switch to
control forward power flow. ON/OFF control is provided
by SHDN or UV. C2 and R2 may be added to further reduce
inrush current. While C2 and R2 may be omitted if soft
starting is not needed. R1 is necessary to prevent MOSFET
parasitic oscillations and must be placed close to M2.
When SHDN is driven low or UV driven high and
∆VDS > 30mV, GATE sources 20μA and gradually charges
C2, pulling up both MOSFET gates. M2 operates as a
source follower as shown in Equation 4.
IINRUSH =
COUT
• 20µA
C2
(4)
If ∆VDS ≤ 30mV, the LTC4372/LTC4373 stay activated but
holds M1 and M2 off until the input exceeds the output by
30mV. In this way normal diode behavior of the circuit is
preserved, but with soft starting when the diode turns on.
When SHDN is driven high or UV driven low, GATE pulls
the MOSFET gates down quickly to SOURCE with a 1mA
pull-down. Both forward and reverse paths are cut off and
IQ is reduced to 0.5μA.
Configuring LTC4373’s UV and UVOUT for Voltage
Monitoring
With back-to-back MOSFETs, the LTC4373 can implement voltage monitoring at IN. Connect a resistive voltage
divider between IN and ground to bias UV. UV has a high
to low threshold of 1.191V with 15mV of hysteresis. The
UV hysteresis is around 1.3% referred to VUV.
Rev. A
For more information www.analog.com
LTC4372/LTC4373
APPLICATIONS INFORMATION
When UV ramps high to low, the LTC4373 enters undervoltage mode and asserts a 1mA pull-down between GATE
and SOURCE to turn off the external MOSFETs. It also turns
off most of the internal circuitry, reducing IQ to 0.5μA.
When UV ramps low to high, the LTC4373 exits undervoltage mode and goes back into ideal diode operation.
Figure 11 demonstrates how UV can be used to monitor
IN. For the UV pin, the maximum input leakage current
is 50nA. For a maximum error of 1% due to leakage currents, the resistive voltage divider current IRVD should be
at least 100 times the sum of the leakage currents, or 5μA.
The IN Undervoltage threshold (VH2L) is used to calculate
the value of R4, R5 and Undervoltage Recovery threshold
(VL2H) as shown in Equation 5.
VH2L = VUV •
(
R4 + R5
R4
VL2H = VUV + VUV(HYST)
)
(5)
R4 + R5
•
R4
For applications that require a higher and more accurate
hysteresis, UVOUT can be used to program an external
hysteresis to override the default hysteresis. Comparator
C1 in the Block Diagram controls an internal 140Ω switch
pulling down on UVOUT. When UV ramps below 1.191V
and trips C1, the switch pulls UVOUT low. When UV ramps
above 1.191V and un-trips C1, the switch turns off and
UVOUT goes high impedance. By connecting R6 between
UV and UVOUT, R4 and R5 implements VH2L and VL2H.
VIN
COUT
10µF
R5
IN
SOURCE
GATE
OUT
UV
R4
LTC4373
R6
(OPTIONAL)
UVOUT
GND
INTVCC
43723 F11
Figure 11. Configuration for Monitoring IN
C1
100nF
Obtain R4 and R5 from Equation 5 and calculate R6 using
Equation 6.
R4 + R5
R4
R5 + Rpa
VL2H = VUV •
Rpa
R4 • R6
where Rpa = R4 //R6 =
R4 + R6
VH2L = VUV •
(6)
As long as the external hysteresis to be implemented
exceeds 5% of VH2L, Equation 6 can disregard the default
UV hysteresis without affecting accuracy.
With UVOUT connected to the resistive voltage divider, the
leakage current error needs to be re-visited. For the UVOUT
pin, the maximum input leakage current below 85°C is 50nA.
While IN ramps high to low, the resistive voltage divider sees
the leakage currents from both UV and UVOUT. This gives a
total of 100nA of leakage currents. With 5μA through R4 and
R5, this will add 2% inaccuracy to VH2L. While IN ramps low
to high, UVOUT is pulled low. The resistive voltage divider
sees only the 50nA of leakage current from UV. With 5μA
through R4 and R5, this will add 1% inaccuracy to VL2H. To
lower the leakage current error, increase IRVD.
Layout Considerations
Connect IN, SOURCE and OUT as close as possible to
the MOSFET source and drain pins. Keep the drain and
source traces to the MOSFET wide and short to minimize resistive losses as shown in Figure 12. Place COUT
close to the drain pin of MOSFET and keep the trace from
LTC4372/LTC4373 GATE pin to MOSFET gate short and
thin to minimize parasitic inductance and capacitance.
This practice will reduce the chance of MOSFET parasitic
oscillations. Place any surge suppressors and necessary
transient protection components close to the LTC4372/
LTC4373 using short lead lengths.
For the DFN package, pin spacing may be a concern at
voltages greater than 30V. Check creepage and clearance
guidelines to determine if this is an issue. To increase the
effective pin spacing between high voltage and ground
pins, leave the exposed pad connection open. Use
no-clean flux to minimize PCB contamination.
Rev. A
For more information www.analog.com
15
LTC4372/LTC4373
APPLICATIONS INFORMATION
1 S
VIN
D 8
VOUT
2 S MOSFET D 7
3 S
D 6
4 G
D 5
GATE
1
2
3
4
IN, SOURCE
OUT
COUT
LTC4372
DD8
GND
VIN
2 S
D 8
MOSFET
VOUT
D 7
3 S
D 6
4 G
D 5
D2
SMAJ70A
70V
1
2
3
4
OUT
SOURCE
GATE
VOUT
48V
5A
OUT
COUT
10μF
LTC4372
2UPU
SHDN
INTVCC
C1
100nF
RGND
1k
COUT
43723 F13
LTC4372
MS8
GND
IN
GND
GATE
IN, SOURCE
M1
FDMS86101
VIN = 48V
8
7
6
5
1 S
and ground to clamp IN and SOURCE when they spike negative. During the input short-circuit transient, D2 diverts the
reverse recovery current in the input parasitic inductances
to ground while COUT does the same for the output parasitic inductances. The 100V, FDMS86101 with RDS(ON) =
8mΩ(max) can handle both the 5A load current as well as
the input short-circuit voltage transients.
8
7
6
5
43723 F12
Figure 12. Layout, MS8 and DD8 Package
Design Examples
The following design example demonstrates the considerations involved in selecting components for a 12V system with 20A maximum load current (see Figure 2). First,
choose the N-channel MOSFET. The 80V BSC026N08NS5
with RDS(ON) = 2.6mΩ(max) offers a good solution. The
maximum voltage drop across is:
ΔVSD = 20A • 2.6mΩ = 52mV
The maximum power dissipation in the MOSFET is:
P = 20A • 52mV = 1.04W
Figure 13. 48V Ideal Diode without Reverse Input Protection
Figure 14 shows a high voltage application with reverse
battery protection. To handle a potential worst-case
situation of –48V at the input side and 48V at the output side, the BVDSS of the external MOSFET must be
greater than 48V + 48V = 96V with allowance. Choose
the 200V, IPB107N20N3G in the TO-263 package with
RDS(ON) = 10.7mΩ(max).
When IN is –48V and OUTPUT is 48V, D3 breaks down
and clamps IN – GND at about –6V. The MOSFET is held
off and isolates the load from the negative input. D1 and
R7 clamps OUT – GND to about 70V. The combination of
D1, D2, D3 and R7 clamps IN – OUT to about 76V.
During input short-circuit voltage transients, using the
GND – GATE clamp to hold GATE should keep IN, SOURCE,
GATE and OUT within their Absolute Maximum Ratings. If
there is a problem with SOURCE to GND shoot through
current during input short-circuits, add a RGND of 100Ω.
During an input short-circuit, M1 drain spikes positive
and IN spikes negative. D2, D3 and D4 commutates the
reverse recovery current in the input parasitic inductances
while COUT does the same for the output parasitic inductances. D1, D2, D3, D4, R7 and R8 clamp IN, SOURCE,
OUT and GND to within their Absolute Maximum Ratings.
Figure 13 shows a high voltage application. For the 48V
system, using the GND – GATE clamp to hold GATE during
input short-circuit voltage transients can exceed IN – OUT’s
–100V absolute maximum voltage. D2 is added between IN
During normal ideal diode operation with GATE high, D4,
C3 and C4 help to handle IQ pulsating between 300μA
(charging GATE) and 3.5μA (charge pump sleep mode)
while D1, D2 and D3 draw no current.
16
Rev. A
For more information www.analog.com
LTC4372/LTC4373
APPLICATIONS INFORMATION
M1
IPB107N20N3G
VIN = ±48V
D3
SMAJ5A
5V
R7
2k
IN
SOURCE
OUT
LTC4372
2UPU
D2
SMAJ70A
70V
GATE
GND
SHDN
C3
1nF
VOUT
48V
5A
D1
SMAJ70A
70V
COUT
10μF
INTVCC
C1
100nF
RGND
1k
R8
10k
C4
100nF
100V
D4
SMAJ70A
70V
43723 F14
Figure 14. 48V Ideal Diode with Reverse Input Protection
Rev. A
For more information www.analog.com
17
LTC4372/LTC4373
APPLICATIONS INFORMATION
D5*
SMAJ60A
60V
QUIESCENT CURRENT < 22µA FOR I-GRADE TEMPERATURE
RSNS
20mΩ
M2
IRLR2908
M1
FDMS86101
VIN
12V
WITHSTANDS
–28V TO 60V DC
COUT
10µF
D1
SMAJ60A
60V
R1
10k
CL
22µF
R3 R2
10Ω 33Ω
RDRN
100k
VOUT
12V/2A
OUTPUT
CLAMPED
AT 27V
C3
47nF
IN
SOURCE
2UPU
GATE
OUT
DRN GATE
VCC
LTC4372
GND
SOURCE
C2
4.7µF
INTVCC
SHDN
ON
OUT
LTC4380-2
GND
TMR
C1
100nF
RGND
1k
SNS
SEL
CTMR
220nF
43723 F15
D4
1N4148W
*D5 IS NEEDED TO CLAMP TRANSIENTS IN CASE INPUT SHORT-CIRCUIT OCCURS AT VIN > 33V
Figure 15. Micropower 12V Surge Stopper with Ideal Diode
M1
BSC026N08NS5
VIN
12V
COUT
10µF
M2
BSS138N
IN
SOURCE
GATE
VOUT
12V
10A
OUT
2UPU
SHDN
LTC4372
GND
OFF ON
M3
BSS138N
INTVCC
43723 F16
C1
100nF
Figure 16. 12V Ideal Diode with Shutdown ICC of 0.5μA (Nominal)
18
Rev. A
For more information www.analog.com
LTC4372/LTC4373
PACKAGE DESCRIPTION
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698 Rev C)
0.70 ±0.05
3.5 ±0.05
1.65 ±0.05
2.10 ±0.05 (2 SIDES)
PACKAGE
OUTLINE
0.25 ±0.05
0.50
BSC
2.38 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
3.00 ±0.10
(4 SIDES)
R = 0.125
TYP
5
0.40 ±0.10
8
1.65 ±0.10
(2 SIDES)
0.75 ±0.05
4
0.25 ±0.05
1
(DD8) DFN 0509 REV C
0.50 BSC
2.38 ±0.10
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
Rev. A
For more information www.analog.com
19
LTC4372/LTC4373
PACKAGE DESCRIPTION
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660 Rev G)
0.889 ±0.127
(.035 ±.005)
5.10
(.201)
MIN
3.20 – 3.45
(.126 – .136)
3.00 ±0.102
(.118 ±.004)
(NOTE 3)
0.65
(.0256)
BSC
0.42 ± 0.038
(.0165 ±.0015)
TYP
8
7 6 5
0.52
(.0205)
REF
RECOMMENDED SOLDER PAD LAYOUT
0.254
(.010)
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
4.90 ±0.152
(.193 ±.006)
DETAIL “A”
0° – 6° TYP
GAUGE PLANE
0.53 ±0.152
(.021 ±.006)
DETAIL “A”
1
2 3
4
1.10
(.043)
MAX
0.86
(.034)
REF
0.18
(.007)
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
TYP
0.65
(.0256)
BSC
0.1016 ±0.0508
(.004 ±.002)
MSOP (MS8) 0213 REV G
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
20
Rev. A
For more information www.analog.com
LTC4372/LTC4373
REVISION HISTORY
REV
DATE
DESCRIPTION
A
12/21
Revised bullets and SHDN pin description.
PAGE NUMBER
1
Revised Paralleling Supplies section.
13
Revised Equations 5 and 6.
15
Added new application.
18
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
more by
information
www.analog.com
21
LTC4372/LTC4373
TYPICAL APPLICATION
VIN
28V
UNDERVOLTAGE CUTOFF = 24V
UNDERVOLTAGE RECOVERY = 28V
M2
BSC026N08NS5
R5A
3650k
R6
2150k
M1
BSC026N08NS5
VOUT
28V
10A
R1
10Ω
R5B
200k
IN
UV
R4
200k
UVOUT
COUT
100µF
SOURCE
GATE
OUT
U1
LTC4373
GND
INTVCC
C1
100nF
M3
BSC026N08NS5
VBACKUP
23V
IN
R9
100k
SOURCE
2UPU
GATE
OUT
U2
LTC4372
SHDN
GND
INTVCC
C2
100nF
RGND
1k
43723 F17
D4
1N4148W
Figure 17. 28V Supply with Voltage Monitoring and Backup Channel
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22
Rev. A
12/21
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For more information www.analog.com
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