LTC4381
Low Quiescent Current eFuse
with Surge Protection
FEATURES
DESCRIPTION
Withstands Surge Voltages Up to 100V
n Internal 9mΩ N-Channel MOSFET
n Guaranteed Safe Operating Area: 20ms at 70V, 1A
n Low Quiescent Current: 6µA Operating
n Operates Through Automobile Cold Crank
n Wide Operating Voltage Range: 4V to 72V
n No Input TVS needed
n Overcurrent Protection
n Selectable Internal 28.5V/47V or Adjustable Output
Clamp Voltage (Table 1)
n Reverse Input Protection to –60V
n Adjustable Turn-On Threshold
n Adjustable Fault Timer with MOSFET Stress
Acceleration
n Latchoff and Retry Options (Table 1)
n Low Retry Duty Cycle During Faults (Table 1)
n 32-Lead DFN (7mm × 5mm) Package
The LTC®4381 is an integrated solution for low quiescent
current eFuse with an internal 9mΩ N-Channel MOSFET.
Overvoltage protection is provided by clamping the gate
voltage of an internal 9mΩ N-channel MOSFET to limit the
output voltage to a safe value during overvoltage events
such as load dump in automobiles. The MOSFET safe
operating area is production tested and guaranteed for
the stresses during high voltage transients. Fixed output clamp voltages are selectable for 12V and 24V/28V
systems. For systems of any voltage up to 80V, use the
adjustable clamp versions.
n
Overcurrent protection is also provided. An internal multiplier generates a TMR pin current proportional to VDS
and ID, so that operating time in both overcurrent and
overvoltage conditions is limited in accordance with
MOSFET stress.
The GATE pin can drive back-to-back MOSFETs for
reverse input protection, eliminating the voltage drop
and dissipation of a Schottky diode solution. A low 6µA
operating current permits use in always-on and battery
powered applications.
APPLICATIONS
Automotive 12V, 24V and 48V System
Avionic/Industrial Surge Protection
n Hot Swap/Live Insertion
n High Side Switch for Battery Powered Systems
n Automotive Load Dump Protection
n
n
All registered trademarks and trademarks are the property of their respective owners.
TYPICAL APPLICATION
12V System with 100V/0.5A/400ms Load Dump Overvoltage Protection
VIN
12V
(100VPK)
20k
0.1µF
200k
68V
CMHZ5266B
IN
SRC
DRN
SNS
VCC
OUT
ON
GFET
LTC4381-2
12V/0.5A
OUTPUT
CLAMPED
AT 28.5V
80mΩ
22µF
10Ω
GATE
SEL
FLT
TMR
GND
10µF
4381 TA01a
12V, 0.5A with 100V Overvoltage Protection
100V INPUT SURGE
ILOAD = 0.5A
VIN
20V/DIV
12V
33Ω
47nF
VOUT 12V
20V/DIV
100ms/DIV
4381 TA01b
Rev. A
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1
LTC4381
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
IN (Note 5)................................................ –0.3V to 100V
VCC, ON, SEL................................................ –60V to 80V
DRN (Note 3), SNS, OUT, SRC
LTC4381-1/LTC4381-2............................ –0.3V to 53V
LTC4381-3/LTC4381-4............................ –0.3V to 80V
SNS to OUT...................................................... –5V to 5V
GATE, GFET (Note 4)
LTC4381-1/LTC4381-2............................ –0.3V to 53V
LTC4381-3/LTC4381-4............................ –0.3V to 86V
GATE to OUT, GATE to VCC,
GFET to SRC (Note 4)............................. –0.3V to 10V
TMR.............................................................. –0.3V to 5V
FLT.............................................................. –0.3V to 80V
IDRN........................................................................2.5mA
Operating Junction Temperature Range
LTC4381A........................................... –40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
TOP VIEW
TMR
ON
GND
DRN
NC
VCC
IN
SRC
SRC
SRC
SRC
SRC
SRC
SRC
SRC
SRC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
33
IN
SEL
FLT
OUT
SNS
NC
GATE
GFET
IN
SRC
SRC
SRC
SRC
SRC
SRC
SRC
SRC
DKE PACKAGE
32-LEAD (7mm × 5mm) PLASTIC DFN
TJMAX = 150°C, θJA = 23°C/W
EXPOSED PAD (PIN 33) IS IN
ORDER INFORMATION
TUBE
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4381ADKE-1#PBF
LTC4381ADKE-1#TRPBF
43811
32-Lead (7mm × 5mm) Plastic DFN
–40°C to 125°C
LTC4381ADKE-2#PBF
LTC4381ADKE-2#TRPBF
43812
32-Lead (7mm × 5mm) Plastic DFN
–40°C to 125°C
LTC4381ADKE-3#PBF
LTC4381ADKE-3#TRPBF
43813
32-Lead (7mm × 5mm) Plastic DFN
–40°C to 125°C
LTC4381ADKE-4#PBF
LTC4381ADKE-4#TRPBF
43814
32-Lead (7mm × 5mm) Plastic DFN
–40°C to 125°C
Contact ADI Sales for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
2
Rev. A
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LTC4381
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = OUT = SNS = DRN = 12V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DC Characteristics
VIN
Input Voltage Range
(Note 7)
l
4
80
V
VCC
Operating Voltage Range
LTC4381-1/LTC4381-2 (Note 7)
LTC4381-3/LTC4381-4 (Note 7, 8)
l
l
4
4
80
72
V
V
VOUT
Operating Voltage Range
VCC = OUT = SNS = DRN = 12V
l
72
V
IQ
Total Supply Current, ON
(Note 6)
C-Grade and I-Grade
H-Grade
l
l
6
12
20
µA
µA
VCC = OUT = SNS = DRN = 4V
l
18
35
µA
VCC Current, Shutdown
ON = OUT = SNS = 0V
l
5
10
µA
VCC Current, ON
VCC = OUT = SNS = DRN = 12V
l
4
12
µA
VCC = OUT = SNS = DRN = 4V
l
16
30
µA
IIN
IN pin Leakage Current
VIN = 24V, VGFET = VSRC = 0V, ON = 0V
l
10
µA
IR
Reverse Input Current
VCC = –60V, ON Open, SEL = 0V
VCC = ON = SEL = –60V
l
l
0
–1
–2
–5
mA
mA
RON
MOSFET On-Resistance
IN = VCC = 8V, 12V, ISRC = –1A, IGATE = –1µA
9
13
28
mΩ
mΩ
ICC
l
SOA
MOSFET Safe Operating Area
VIN – VSRC = 70V, 1A, 10W√s
IAL
MOSFET Avalanche Current
(Note 9)
20
ms
82
A
SNS, OUT, SEL, ON, DRN
ISNS
SNS Current, ON
l
0.5
1.4
µA
IOUT, ON
OUT Current, ON
IOUT, SD
OUT Current, Shutdown
C-Grade and I-Grade
H-Grade
l
1.5
5.5
µA
l
l
6
12
80
µA
µA
∆VSNS
Current Limit Sense Voltage
(SNS – OUT)
VCC = 12V, 24V, OUT = 6V, 12V
VCC = 12V, 24V, OUT = 0V
l
l
50
62
55
95
mV
mV
ISEL
SEL Input Current
SEL = 0V to 80V
l
VSEL
SEL Input Threshold
±0.1
µA
3
V
l
45
40
0.4
ION
ON Input Current
VON = 1V
l
–1
–2
–4
µA
VON
ON Input Threshold
ON Rising
l
0.99
1.05
1.1
V
VON(HYST)
ON Input Hysteresis
∆VDRN
DRN Voltage (DRN – OUT)
IDRN = 0.1mA
VDS(MAX)
Overvoltage VDS Threshold
(DRN – OUT)
TMR = 0.8V, IDRN = 2µA
45
mV
l
0.7
2.25
2.6
V
0.7
l
0.58
0.3
0.8
1.0
V
V
SRC, GATE, FLT, TMR
VSRC
SRC Voltage Output Clamp
VIN = VCC = 80V, SEL = 0V, IOUT = –10mA, LTC4381-1/LTC4381-2
VIN = VCC = 80V, SEL = VCC, IOUT = –10mA, LTC4381-1/LTC4381-2
VIN = 80V, VCC = 12V, IOUT = –10mA, LTC4381-3/LTC4381-4
VIN = 80V, VCC = 24V, IOUT = –10mA, LTC4381-3/LTC4381-4
l
l
l
l
25.5
43.5
19.0
31.0
28.5
47.0
22.5
34.5
31.5
50.5
26.0
38.0
V
V
V
V
VGFET(TH)
MOSFET Threshold
ISRC = –10mA
l
1
3
4.6
V
∆VGATE
GATE Drive (GATE – OUT)
SEL = SNS = OUT = VCC, 8V ≤ VCC ≤ 30V
l
10
11.1
14
V
∆VCLAMP
GATE Clamp to VCC (GATE – VCC)
SNS = OUT = 20V, IGATE = 0µA
l
12
13.5
15.5
V
Rev. A
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3
LTC4381
ELECTRICAL
CHARACTERISTICS l denotes the specifications which apply over the full operating
The
temperature range, otherwise specifications are at TA = 25°C. VCC = OUT = SNS = DRN = 12V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VGATE
GATE Clamp to GND
VCC = 30V, SEL = 0V, LTC4381-1/LTC4381-2
VCC = 60V, SEL = VCC, LTC4381-1/LTC4381-2
l
l
30
47.5
31.5
50
33
52.5
V
V
IGATE(UP)
GATE Pull-Up Current
VCC = GATE = OUT = 12V, 24V
l
–8.5
–20
–35
µA
IGATE(DN)
GATE Pull-Down Current
Overcurrent
Shutdown
Input UV
Fault Time Out
∆VSNS = 200mV, GATE = 12V, OUT = 0V
ON = 0V, GATE = 20V
VCC = 1.5V, GATE = 10V
TMR = 2V, GATE = 10V
l
l
l
l
50
0.3
2
1.5
100
5
5
3.5
IFLT
FLT Leakage Current
FLT = 80V
l
VFLT(LOW)
FLT Output Low
ISINK = 0.1mA
ISINK = 3mA
l
l
ITMR(DN)
TMR Pull-Down Current
TMR = 0.8V
l
TMR = 2V
l
2
µA
0.1
1
0.5
4
V
V
1.2
1.6
2.75
µA
–1
–2
–3
µA
l
–0.7
–1.6
–2.4
µA
l
l
l
l
–3.5
–13
–10
–60
–6.7
–30
–20
–120
–12
–61
–30
–180
µA
µA
µA
µA
TMR Pull-Up Current, Overcurrent TMR = 0.8V
IDRN = 0mA, OUT = 11V
IDRN = 0mA, OUT = 0V
Small OV, Light Load
IDRN = 0.1mA, OUT = 11V
High OV, Light Load
IDRN = 1mA, OUT = 11V
Small OV, Heavy Load
IDRN = 0.1mA, OUT = 0V
High OV, Heavy Load
IDRN = 1mA, OUT = 0V
l
l
l
l
l
l
–3
–16
–16
–80
–35
–130
–6
–24
–27
–142
–50
–170
–9
–36
–38
–206
–60
–220
µA
µA
µA
µA
µA
µA
TMR Gate Off Threshold
l
1.178
1.215
1.251
V
ITMR(UP, COOL) TMR Pull-Up Current, Cool Down
ITMR(OV)
ITMR(OC)
ITMR(SC)
VTMR
mA
mA
mA
mA
TMR Pull-Up Current, Overvoltage TMR = 0.8V, OUT = 11V, VDS = 1.1V, ∆VSNS = 0mV
OUT = 28V, TMR = 0.8V
Small OV, Light Load
IDRN = 0.1mA, ∆VSNS = 10mV
High OV, Light Load
IDRN = 1mA, ∆VSNS = 10mV
Small OV, Heavy Load
IDRN = 0.1mA, ∆VSNS = 40mV
High OV, Heavy Load
IDRN = 1mA, ∆VSNS = 40mV
TMR Rising
AC Characteristics
D
Retry Duty Cycle; Overvoltage,
LTC4381-2/LTC4381-4
∆VSNS = 40mV, IDRN = 5µA, OUT = 28V, VCC = 29V
l
2.8
4.2
%
∆VSNS = 40mV, IDRN = 500µA, OUT = 28V, VCC = 80V
l
0.1
0.2
%
Retry Duty-Cycle; Overcurrent,
LTC4381-2/LTC4381-4
IDRN = 500µA
OUT = 0V
OUT = 6V
l
l
0.1
0.35
0.2
0.7
%
%
tON(ON)
Turn-On Propagation Delay
ON Steps from 0V to 1.5V, OUT = SNS = 0V
l
7.5
25
ms
tOFF(ON)
Turn-Off Propagation Delay
ON Steps from 1.5V to 0V, OUT = SNS = VCC
l
1
5
µs
tOFF(OC)
Overcurrent Turn-Off
Propagation Delay
∆VSNS Steps from 0V to 250mV, OUT = 6V
l
2
4
µs
∆VSNS Steps from 0V to 250mV, OUT = 0V
l
2
4
µs
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into device pins are positive; all currents out of
device pins are negative. All voltages are referenced to GND unless
otherwise specified.
Note 3: Internal clamps limit the DRN pin to a minimum of 10V above the
OUT and SNS pins.
4
Note 4: Internal clamps limit the GATE pin to a minimum of 10V above the
OUT pin or VCC pin, or 50V (SEL = VCC) or 31.5V (SEL = GND) above the
GND pin (LTC4381-1/LTC4381-2). Driving this pin to voltages beyond the
clamp may damage the device.
Note 5: IN ABS MAX is rated at 25°C to 125°C only.
Note 6: Total supply current is the sum of the current into the VCC, OUT,
SNS and DRN pins.
Note 7: The LTC4381 can operate through the cold crank down to 4V in
automotive applications, wheres VCC is powered with a 12V supply initially
and stays above 8V during the cold crank period.
Note 8: Operating voltage is limited by the maximum GATE voltage of 86V.
Note 9: Not tested in production.
Rev. A
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LTC4381
TYPICAL PERFORMANCE CHARACTERISTICS
Total Supply Current (IQ)
vs Input Voltage
30
VCC = 12V, unless otherwise noted.
Total Supply Current (IQ)
vs Gate Leakage
Total Supply Current (IQ)
vs Temperature
100
SEL = VCC
100
IQ (µA)
IQ (µA)
IQ (µA)
20
10
10
10
0
IGATE = 0
SHUTDOWN
0
10
20
VIN (V)
1
–0.001
30
–0.01
4381 G01
Supply Current (ICC)
vs Supply Voltage
–0.1
IGATE (µA)
–1
1
–50 –25
–10
100
25 50 75 100 125 150
TEMPERATURE (°C)
4381 G03
10
SNS = OUT = VCC
SNS = OUT= SEL = VCC
0
4381 G02
Supply Current (ICC)
vs Temperature
30
IGATE = 0
IGATE = –1µA
SHUTDOWN
ISNS vs Temperature
SNS = OUT = VCC
ISNS (µA)
ICC (µA)
ICC (µA)
20
10
1
10
0
0
10
20
VCC (V)
1
–50 –25
30
VCC = 4V
VCC = 12V
0
0.1
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
4381 G04
0
25 50 75 100 125 150
TEMPERATURE (°C)
4381 G05
4381 G06
Reverse Current
vs Reverse Voltage
Output Pin Current
vs Temperature
10
1k
Gate Pull-Up Current
vs Temperature
–35
SEL = ON = VCC
SNS = OUT = VCC
–30
ON
SHUTDOWN
IGATE(UP) (µA)
10
IGND (mA)
IOUT (µA)
100
1
–25
–20
1
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
4381 G07
0.1
–10
–20
–30
–40 –50
VCC (V)
–60
–70
–80
4381 G08
–15
–50 –25
GATE = 0V
GATE = 12V
0
25 50 75 100 125 150
TEMPERATURE (°C)
4381 G09
Rev. A
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5
LTC4381
TYPICAL PERFORMANCE CHARACTERISTICS
Gate Drive vs Pull-Up Current
VCC = 12V, unless otherwise noted.
Gate Drive vs Temperature
14
15
Gate Drive vs Supply Voltage
15
IGATE = –1µA
IGATE = –1µA
SEL = VCC
12
8
6
5
4
2
38
VCC = 12V
VCC = 4V
0
–5
–10
–15
IGATE (µA)
–20
0
–50 –25
–25
VCC = 4V
VCC = 12V
0
–60
VCC = 24V
ITMR(OC) (µA)
33
–120
–45
–40
–35
–20
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
0
–20
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
0
25 50 75 100 125 150
TEMPERATURE (°C)
4381 G14
Current Limit vs Output Voltage
4381 G15
DRN Voltage vs Current
70
4.0
60
3.5
ON Pin Current vs Voltage
–4.0
∆VDRN = VDRN – VOUT
–3.5
–3.0
50
3.0
40
30
–2.5
ION (µA)
∆VDRN (V)
∆VSNS (mV)
∆VSNS = 40mV
∆VSNS = 10mV
–80
–40
OUT = 0V
OUT = 6V
4381 G13
2.5
–2.0
–1.5
2.0
20
–1.0
1.5
10
0
1
2
3
4
VOUT (V)
6
–100
–60
–25
0
IDRN = 1mA
–140
–30
32
30
4381 G12
–160
IDRN = 0.1mA
–50
31
–50 –25
20
TMR Pin Current vs Temperature,
Overvoltage Fault
–55
34
10
VCC (V)
TMR Pin Current vs Temperature,
Overcurrent Fault
VSRC vs Temperature
35
0
4381 G11
36
0
0
25 50 75 100 125 150
TEMPERATURE (°C)
4381 G10
37
VSRC (V)
5
ITMR(OV) (µA)
0
10
∆VGATE (V)
10
∆VGATE (V)
∆VGATE (V)
10
5
6
7
8
4381 G16
1.0
–0.5
1
10
100
IDRN (µA)
1k
4381 G17
0
0
1
2
3
VON (V)
4
5
4381 G18
Rev. A
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LTC4381
TYPICAL PERFORMANCE CHARACTERISTICS
24
RON vs Temperature
20
VCC = 12V, unless otherwise noted.
25
VCC = 4V
VCC = 12V
RON vs VCC
20
RON (mΩ)
12
15
10
8
5
4
0
–50 –25
0
0
25 50 75 100 125 150
TEMPERATURE (°C)
0
4381 G19
4
8
VCC (V)
12
16
4381 G20
MOSFET SOA Curve
1k
TA = 25°C
SINGLE PULSE
100
IOUT (A)
RON (mΩ)
16
100μs
10
1ms
1
10ms
100ms
0.1
1
10
VIN–VSRC (V)
100 200
4381 G21
Rev. A
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7
LTC4381
PIN FUNCTIONS
DRN: MOSFET Drain-Source Sense. The DRN pin voltage
tracks the OUT pin. The resulting DRN pin current through
external resistor RDRN is proportional to the MOSFET VDS.
The DRN pin current and ΔVSNS (SNS – OUT) are multiplied internally to produce a TMR pin current approximately proportional to the MOSFET’s power dissipation.
This reduces the SOA requirement of the MOSFET by timing out faster during more severe faults. Choose RDRN to
limit the current to 1mA at the peak input voltage. Connect
to OUT if unused.
FLT: Fault Output. This open-drain logic output pin pulls
low after the voltage at the TMR pin has reached the fault
threshold of 1.215V. It indicates that the MOSFET is off
because either the supply voltage has stayed at an elevated level for an extended period of time (voltage fault)
or the device is in an overcurrent condition (current fault).
The fault output is capable of sinking up to 3mA. Leave
open or tie to GND if unused.
GATE: Gate Drive for Internal N-Channel MOSFET. The
GATE pin is pulled up by an internal 20µA charge pump
that is regulated to 11.5V above the OUT pin. An amplifier
controls the GATE pin to limit the current through the
MOSFET. A minimum of 47nF of capacitance and 33Ω
series resistor at the pin is necessary to compensate the
current limit amplifier. To avoid damaging the MOSFET
during an output short, GATE is also clamped internally
to 17V above OUT.
GFET: Gate of Internal N-Channel MOSFET. Connect this
pin to the GATE pin through a 10Ω resistor.
GND: Device Ground.
IN: Input of MOSFET. This is the drain terminal of the internal MOSFET. Connect this pin to the supply input.
8
ON: Turn-On Control Input. The LTC4381 can be turned
on by pulling this pin above 1.05V or by leaving it open to
allow an internal 1MΩ resistor to turn the part on. Pulling
the pin below the threshold puts the part in shutdown
mode and reduces the supply current to 5µA. Limit the ON
leakage current to less than 1µA if no external pull-up is
used. The ON pin can be pulled up to 80V or below GND
by 60V without damage.
OUT: Output Voltage Sense. This pin senses the output
voltage at the output terminal of the current sense resistor.
An internal clamp limits the voltage in between the GATE
and OUT pins to 17V. Bypass the OUT pin with a minimum
of 22µF as close to the pin as possible.
SEL: Output Clamp Voltage Select for LTC4381-1 and
LTC4381-2. Connect the SEL pin to GND to set the internal
output clamp voltage to 28.5V. Connect it to VCC or OUT
for a 47V output clamp voltage. The SEL pin can be pulled
up to 80V or below GND by 60V without damage. The SEL
pin has no effect on the LTC4381-3 and LTC4381-4, it can
be tied to GND or VCC or OUT.
SNS: Current Sense Input. Connect to the input terminal
of the current sense resistor. The current limit amplifier
controls the GATE pin to limit the current sense voltage
to 50mV. This voltage increases to 62mV in a severe fault
when OUT is below 1.5V. A fixed 6µA is added to the TMR
pin current during an overcurrent condition to shorten the
turn-off time. In a severe short condition when the output
voltage is below 1.5V, the extra current increases to 24µA
to reduce the power dissipation in the MOSFET. ∆VSNS
(SNS – OUT) must be limited to less than ±5V. Connect
to OUT if unused.
Rev. A
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LTC4381
PIN FUNCTIONS
SRC: Output of MOSFET. This is the source terminal of the
internal MOSFET, connect this pin to the sense resistor.
The SRC pin and output is indirectly clamped through
GATE pin during an overvoltage event. The LTC4381-1/
LTC4381-2 SRC pin is clamped at 28.5V above GND with
SEL = 0 V, or 47V above GND when SEL = VCC. It is also
clamped at 10.5V above VCC if the VCC voltage is low.
The LTC4381-3/LTC4381-4 SRC pin does not have the
28.5V/47V clamp to GND, it is only clamped at 10.5V
above VCC.
TMR: Fault Timer Input. Connect a capacitor between this
pin and ground to set the fault turn-off time and cool
down period. The charging current during fault conditions
varies depending on the power dissipation of the MOSFET.
When TMR reaches 1.215V, the MOSFET turns off and
FLT pulls low. Upon gate off, the part immediately enters
a cool down period with a 2µA current pull up and pull
down on the TMR pin. After the cool down period has
concluded, the LTC4381-2 and LTC4381-4 immediately
restart, while the LTC4381-1and LTC4381-3 remain off
until the ON pin is pulled low momentarily for more than
100µs or power is cycled. A 10V rated X7R capacitor is
recommended for CTMR.
VCC: Positive Supply Voltage Input. The positive supply
input ranges from 4V to 80V. For applications where the
input voltage is expected to exceed 80V, the VCC pin may
be protected by a Zener diode clamp or, in the case of
short duration spikes, by a simple RC filter. Clamping the
VCC pin with a Zener diode can also be used as a means of
adjusting the output clamp voltage to a value less than the
internal 28.5V/47V clamps for the LTC4381-1/LTC4381‑2.
For the adjustable versions, LTC4381-3/LTC4381-4,
which have no internal clamp, a Zener diode at the VCC
pin is the only way to limit the voltage at the output. The
VCC pin can also be powered separately from the VIN pin.
Rev. A
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9
LTC4381
BLOCK DIAGRAM
RSNS
INPUT
VCC
GATE
GFET
IN
SRC
OUTPUT
SNS
OUT
9mΩ
RDRN
17V
31.5V*
+
SEL
+
–
13.5V
CHARGE PUMP
REGULATED TO
VOUT + 11.5V
20µA
(250kHz)
IA
18.5V*
50mV/62mV
3.5V
–
1M
+
SNS
ON
VCC
+
IMULT
2.2V
UV
OUT
3.5V
3.4V
6µA, 24µA
–
VMAX RST GOFF
+
OVERCURRENT
4µA
3.6µA
3.5V
0.1V
+
FLT
–
OVERVOLTAGE
+
2µA
1.215V
–
TMR
GND
4381 BD
*ONLY IN LTC4381-1/LTC4381-2
10
1V
CONTROL
LOGIC
MULTIPLIER
COOL
DOWN
–
–
DRN
3.5V
ON
Rev. A
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LTC4381
OPERATION
The LTC4381 is a low quiescent current eFuse that drives
an internal 9mΩ N-channel MOSFET as the pass device.
In normal operation, a 20µA charge pump (see Block
Diagram) drives MOSFET M1 fully on, providing a low
impedance path from input to the load. The MOSFET gate
is clamped to ground by a Zener stack. If the input voltage
rises to the point where the output approaches the gate
clamp, the output is effectively limited to one threshold
voltage (typically 3V) below the gate clamp and the input
surge is blocked from reaching the load.
For the LTC4381-1 and LTC4381-2 versions, two output
clamping voltages to ground are available: 28.5V for use
in 12V systems, and 47V for use in 24V and 28V systems. The clamping voltage is selectable using the SEL
pin. Besides the output to ground clamp, the output is
also limited to 10.5V above the VCC pin.
There is no GATE clamp to ground for the LTC4381-3
and LTC4381-4 versions and the output is only limited
to 10.5V above the voltage at the VCC pin. A Zener diode
clamp connected from the VCC pin to ground thus clamps
the voltages at both the VCC and SRC pins during overvoltage events.
Load current is limited by a current limit amplifier (IA),
using a sense resistor in series with the MOSFET source
to monitor the current. The current limit threshold is
50mV, rising to 62mV when the output is less than 1.5V.
MOSFET stress is monitored by a timer, whose current is a
function of MOSFET’s VDS as well as ID. VDS is monitored
by RDRN at the DRN pin, while ID is monitored by sensing the voltage drop across RSNS. The timer allows the
load to continue functioning during short transient events
while protecting the MOSFET from being damaged by a
sustained overvoltage, such as load dump in vehicles, or
an output overload or short circuit.
A multiplier sets the timer period depending on the power
dissipation in the MOSFET. Higher power dissipation corresponds to a shorter timer period, helping to keep the
MOSFET within its safe operating area (SOA).
The timer responds to stresses at start-up and during
voltage and current limiting. TMR pin current is integrated
on timing capacitor CTMR and if TMR charges to 1.215V,
the MOSFET is turned off. At this point, the LTC4381-1
and LTC4381-3 latch off, and can be reset by cycling
power or by pulling the ON pin low for at least 100µs.
For the LTC4381-2 and LTC4381-4, the TMR pin enters a
cool down phase, allowing time for the MOSFET temperature to equalize with its surroundings before automatically
restarting. The TMR pin slowly charges up and down in
between 3.4V and 1.215V for 15 times and discharges to
ground at the last cycle. When the TMR pin has reached
the 100mV threshold, the MOSFET is turned back on. The
cool down interval can be curtailed by pulling the ON pin
low for at least 10ms/µF of CTMR.
In addition to resetting the timer, the ON pin is used for
on/off control and for undervoltage detection. The ON pin
threshold is 1.05V.
The open drain FLT pin pulls low whenever the timer is
faulted off and goes high again when reset by a power
cycle, by pulling the ON pin low for at least 100µs or in
the case of the LTC4381-2 and LTC4381-4, when the TMR
pin discharges to 100mV.
Table 1. LTC4381 Options
PART NUMBER
OUTPUT CLAMP
FAULT BEHAVIOR
LTC4381-1
Internal 28.5V/47V to GND
Latchoff
LTC4381-2
Internal 28.5V/47V to GND
Auto Retry
LTC4381-3
Externally Adjustable
Latchoff
LTC4381-4
Externally Adjustable
Auto Retry
Rev. A
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11
LTC4381
APPLICATIONS INFORMATION
The LTC4381 limits the voltage and current delivered
to the load during supply transient or output overload
events. The N-channel MOSFET provides a low resistance
path from the input to the load during normal operation. In
overvoltage conditions it limits the output to a threshold
voltage below the clamped gate voltage. The total fault
timer period is set to ride through short-duration faults,
while longer events cause the output to shut off and protect the MOSFET from damage.
Start-Up
Figure 1 shows a 12V, 1A application which limits the
output to approximately 28.5V. When power is first
applied with VCC ≥ 4V and ON ≥ 1.05V, there is a delay of
about 10ms before the GATE pin begins charging C2 and
MOSFET’s gate terminal with a fixed 20µA current source.
The internal MOSFET operates as a source follower, ramping the output up at a rate of IGATE(UP)/C2. Inrush current
in the load capacitance COUT is given by Equation 1.
IINRUSH = IGATE(UP) •
COUT
C2
(1)
where IGATE(UP) is typically 20µA.
Eventually, the GATE pin charges to the point where VIN ≈
VOUT and stops only when ΔVGATE (VGATE – VOUT) reaches
its regulation point of 11.5V, fully enhancing the MOSFET.
Overcurrent Fault Protection
The LTC4381 features an adjustable current limit that protects against short circuits and excessive load current.
During an overcurrent event, the GATE pin is regulated to
limit the current sense voltage across the SNS and OUT
pins (ΔVSNS) to 50mV when OUT is above 3V. In the case
of a severe short at the output, where OUT is less than
1.5V, the current sense voltage is 62mV. Output current is
thereby limited to ΔVSNS/RSNS. Current limit may control
the startup ramp rate in extreme cases, such as if COUT
is unusually large or if current limit is set to an unusually
low value, and artificially reduces COUT’s inrush current
below the value previously calculated.
12
Overvoltage Fault Protection
The LTC4381 limits the voltage at the output during an
overvoltage at the input. For the LTC4381-1/LTC4381-2
illustrated in Figure 1, an internal clamp limits the output
to either 28.5V or 47V, depending on the state of the SEL
pin. With the SEL pin grounded as shown, the output
is clamped at 28.5V. Tying the SEL pin high causes the
output to clamp at 47V.
The GATE pin may also be limited by the compliance of
the internal 20µA current source, to VCC + 13.5V. In the
LTC4381-3/LTC4381-4 the GATE pin clamp is entirely
disconnected, leaving only the VCC + 13.5V compliance
limit. This arrangement allows the output to be effectively
clamped at any voltage from 14.5V to 72V, by clamping
VCC to between 4V and 61.5V.
VCC Pin
The LTC4381 can withstand an input surge voltage of up to
100V. If the maximum expected surge voltage is less than
80V, the VCC pin can be connected directly to the input
supply. If the surge voltage is between 80V to 100V, the
VCC pin must be protected by filtering or clamping since
its operating range is from 4V to 80V for LTC4381-1/
LTC4381-2 and 4V to 72V for LTC4381-3/LTC4381-4.
For short duration spikes and transients exceeding 80V,
filtering is the most sensible means of protecting the VCC
pin. R1 and C1 provide filtering in Figure 1. Owing to the
LTC4381’s low ICC, values up to 100k may be used for R1
without seriously impairing the lower end of the operating
voltage range. For long duration surges such as automotive load dump, C1 becomes prohibitively large and
Zener D1 is the most effective means of limiting the VCC
voltage. Using a 68V Zener assures that D1 will not override the internal GATE pin clamp in the LTC4381-1 and
LTC4381-2 devices. For the LTC4381-3 and LTC4381-4,
the VCC operating range extends from 4V to 72V. Since
the SRC pin is regulated to VCC + 10.5V, D1 is chosen to
achieve the desired output clamping effect while at the
same time keeping the VCC pin within its 4V to 72V range.
The LTC4381 can operate through the cold crank down
to 4V in automotive applications, wheres VCC is powered
with a 12V supply initially and stays above 8V during the
cold crank period.
Rev. A
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LTC4381
APPLICATIONS INFORMATION
VIN
12V
RDRN
100k
R1
10k
IN
ON
OUT
LTC4381-2
SEL
GFET
GATE
FLT
GND
TMR
D1
68V
CMHZ5266B
12V/1A OUTPUT
CLAMPED
AT 28.5V
SNS
DRN
VCC
C1
4.7µF
SRC
RSNS
40mΩ
CTMR
220nF
4381 F01
COUT
22µF
R3
10Ω
R2
33Ω
C2
47nF
Figure 1. 12V/1A, Output Limited to 28.5V
Fault Timer Overview
Overvoltage and overcurrent conditions, and high VDS
conditions in MOSFET are limited in duration by an adjustable fault timer. A capacitor at the TMR pin (CTMR) sets
the delay time before a fault condition is reported at the
FLT pin and MOSFET is turned off. CTMR also sets the cool
down time before MOSFET is permitted to turn back on
for the LTC4381-2 and LTC4381-4 auto retry versions.
The LTC4381-1 and LTC4381-3 versions simply latch off
at the end of the timer delay. A 10V or higher rated X7R
capacitor is recommended for CTMR to minimize temperature and voltage sensitivity.
Fault timing starts as soon as the input power is applied
with the part in the on condition, or when the part turns
on after application of power. A 1.5µA current is generated to pull up the TMR pin when the voltage across the
MOSFET is higher than 0.7V. The timer speeds up with
an additional current that varies with the power dissipated
in the MOSFET. The power dissipation is the product of
the voltage across the MOSFET (VDS) and the current
flowing through it (ID). VDS is inferred from the voltage
drop across the drain pin resistor, RDRN, while ΔVSNS represents ID.
At initial power-up, the 1.5µA pilot current charges the
TMR pin capacitor because the input supply is, at least
for a short time, more than 0.7V above the output voltage.
When the output rises to within 0.7V of the input supply
voltage, the pull-up current disappears and an internal
2µA current source discharges the TMR pin capacitor. The
capacitor must be sized to ride through the initial start-up
interval for successful power-up.
In the presence of a sustained fault, the timer current
charges the TMR pin to 1.215V. At this point, the FLT pin
pulls low to indicate a fault condition and the GATE pin
pulls low, shutting off the MOSFET. After faulting off, the
timer enters the cool down phase. At the end of the cool
down period, the LTC4381-1/LTC4381-3 remain off until
manually reset, while the LTC4381-2/LTC4381-4 automatically restart.
Fault Timer Operation in Overvoltage or Large VDS
During start-up or an overvoltage condition, where the
MOSFET’s VDS exceeds 0.7V, the TMR pin charges from
0V to 1.215V with a current that varies principally as a
function of VDS and ID. VDS is inferred from the current
flowing in the DRN pin resistor, RDRN, while the voltage
difference between the SNS and OUT pins (∆VSNS) represents the MOSFET current, ID.
The TMR pin current is given by Equation 2.
ITMR(OV) = 0.0917
A
• ∆V
SNS • IDRN 70µA (2)
V
where 0.0917√A/V is the gain term of the multiplier. If
IDRN is less than 70µA (for example during start-up), use
ITMR of 1.5µA.
Substituting for ∆VSNS and IDRN is given by Equation 3.
ITMR(OV) = 0.0917
V
A
• ID • RSNS • DS
V
RDRN
70µA (3)
If IDRN is less than 70µA (for example during start-up),
use ITMR of 1.5µA.
When TMR reaches 1.215V, the FLT pin pulls low and the
MOSFET is turned off and allowed to cool for an extended
period. The total elapsed time between the onset of output
clamping and turning off is given by Equation 4.
t TMR = VTMR •
CTMR
ITMR
(4)
Because ITMR is a function of VDS and ID, the exact time
spent in overvoltage before turning off depends upon the
input waveform and the load current.
Rev. A
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13
LTC4381
APPLICATIONS INFORMATION
Fault Timer Operation in Overcurrent
TMR pin behavior in overcurrent is substantially the same
as in overvoltage. In the presence of an overcurrent condition when the LTC4381 regulates the output current, the
TMR pin charges from 0V to 1.215V with a current that
varies principally as a function of the power dissipated in
the MOSFET. In addition to the variable current, an additional 24µA hastens timeout in a low impedance short
where the output is less than 1.5V. This additional current
is reduced to 6µA when VOUT is above 3V.
The TMR pin current with VOUT less than 1.5V is given
by Equation 5.
ITMR(SC) = 0.0917
V
A
• I D • RSNS • DS
V
RDRN
70µA (5)
24µA
where 24μA is the extra TMR current during VOUT short circuit condition. If IDRN is less than 70µA, use ITMR of 24µA.
And with VOUT above 3V given by Equation 6.
ITMR(OC) = 0.0917
V
A
• ID • RSNS • DS
V
RDRN
70µA (6)
6µA
where 6μA is the extra TMR current during overcurrent
condition. If IDRN is less than 70µA, use ITMR of 6µA.
When TMR reaches 1.215V, the FLT pin pulls low and the
MOSFET is turned off and allowed to cool for an extended
period. The total elapsed time between the onset of output
clamping and turning off is given by Equation 7.
t TMR = VTMR •
CTMR
ITMR
(7)
Because ITMR is a function of VDS and ID, the exact time
spent in overcurrent before turning off depends upon the
input waveform, the output voltage and the time required
for the output current to come into regulation.
Cool Down Phase
Cool down behavior is the same whether initiated by overvoltage or overcurrent. During the cool down phase, the
timer continues to charge from 1.215V to 3.4V with 2µA,
14
and then discharge back down to 1.215V with 2µA. This
cycle repeats 14 times and at the 15th cycle the TMR pin
is pulled all the way to ground. The total cool down time
is given by Equation 8.
tCOOL = CTMR •
15 • 4.37V + (1.215V – 0.1V)
2µA
s
= CTMR • 33.3
µF
(8)
where CTMR is in µF.
Up to this point the operation of the LTC4381-1/LTC4381-3
and LTC4381-2/LTC4381-4 is the same. Behavior at the
end of the cool down phase is entirely different.
At the end of the cool down phase, when TMR crosses
the 100mV reset threshold, the LTC4381-1/LTC4381-3
remain latched off and FLT remains low. They may be
restarted by pulling the ON pin low for at least 100µs or
by cycling the power supply. The cool down phase may
be interrupted at anytime by pulling the ON pin low for at
least 10ms/µF of CTMR; the LTC4381-1/LTC4381-3 will
restart when ON goes high. The LTC4381-2/LTC4381-4
will automatically retry at the end of the cool down phase
without cycling the ON pin and the cool down phase
may be interrupted by pulling the ON pin low for at least
10ms/µF of CTMR.
For both versions, the FLT pin goes high in shutdown and
is cleared high when power is first applied to VCC. If FLT
is set low, it can be reset during the cool down phase by
pulling the ON pin low for at least 10ms/µF of CTMR.
Supply Transient Protection
During a short-circuit condition, the large change in current flowing through power supply traces and associated
wiring can cause large inductive voltage transients. If this
voltage transient is higher than the junction breakdown
voltage of the LTC4381 internal MOSFET, the junction
conducts and absorb this avalanche current. No TVS is
required at the IN pin. On the other hand, the VCC pin is
guaranteed to be safe from damage up to 80V only. The
VCC pin cannot be tied directly to the IN pin if Avalanche
breakdown is expected. An RC filter at the VCC pin is an
effective measure against this voltage spike.
Rev. A
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LTC4381
APPLICATIONS INFORMATION
Another way to limit transients to less than 80V at the VCC
pin is to use a small Zener diode and a resistor, D1 and R1
in Figure 1. The Zener diode limits the voltage at the pin
while the resistor limits the current through the diode to a
safe level during the surge. However, D1 can be omitted if
the filtered voltage at the VCC pin, due to R1 and C1, stays
below 80V. The inclusion of R1 in series with the VCC pin
modestly increases the minimum required voltage at VIN
due to the extra voltage drop across it from the small VCC
current of the LTC4381 and the leakage current of D1.
A total bulk capacitance of at least 22µF low ESR electrolytic or ceramic is required close to the OUT pin.
type and rises to infinity under DC operating conditions.
Destruction mechanisms other than bulk die temperature
distort the lines of an accurately drawn SOA graph so that
P√t is not the same for all combinations of ID and VDS.
In particular P√t tends to degrade as VDS approaches
the maximum rating, rendering some devices useless for
absorbing energy above a certain voltage. The LTC4381
internal MOSFET has a guaranteed SOA of 20ms at 70V
and 1A, which gives a P√t of 10W√s. To survive a longer
overvoltage transient, reduce the load current according
to this P√t spec.
VPK
Transient Stress in the MOSFET
τ
During an overvoltage event, the LTC4381 clamps the
gate of the pass MOSFET to limit the output voltage at an
acceptable level. The load circuitry may continue operating throughout this interval, but only at the expense of
dissipation in the MOSFET pass device. MOSFET dissipation or stress is a function of the input voltage waveform,
output voltage and load current.
Most transient event specifications use the prototypical waveshape shown in Figure 2, comprising a linear
ramp of rise time tr, reaching a peak voltage of VPK and
exponentially decaying back to VIN with a time constant
of τ. A common automotive transient specification has
constants of tr = 10µs, VPK = 80V and τ = 1ms. A surge
condition known as load dump commonly has constants
of tr = 5ms, VPK = 60V and τ = 200ms.
MOSFET stress is the result of power dissipated within
the device. For long duration surges of 100ms or more,
stress is increasingly dominated by heat transfer out of
the package; this is a matter of device packaging and
mounting and heat sink thermal mass. This is best analyzed by simulation using the MOSFET thermal model.
For short duration transients of less than 100ms, MOSFET
survival is a matter of safe operating area (SOA), an
intrinsic property of the MOSFET. SOA quantifies the
time required at any given condition of VDS and ID to
raise the junction temperature of the MOSFET to its rated
maximum. MOSFET SOA can be expressed in units of
watt-root-seconds (P√t), which is essentially constant
for intervals of less than 100ms for any given device
VIN
tr
4381 F02
Figure 2. Prototypical Transient Waveform
VPK
τ
VREG
VIN
tr
4381 F03
Figure 3. Safe Operating Area Required to Survive
Prototypical Transient Waveform
Calculating Transient Stress
P√t for a prototypical transient waveform is calculated
using Equation 9 and Figure 3.
Let
a = VREG – VIN
b = VPK – VIN
(VIN = Nominal Input Voltage)
Rev. A
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15
LTC4381
APPLICATIONS INFORMATION
Limiting Inrush Current and GATE Pin Compensation
Then
P t = ILOAD •
(9)
3
1 (b – a ) 1
b
tr
+
2a2 ln + 3a2 + b2 – 4ab
3
2
a
b
For the transient conditions of VPK = 100V, VIN = 12V, VREG
= 28.5V, tr = 10µs, τ = 1ms, and a load current of 1A, P√t is
1.4W√s which can be handled by the MOSFET. The P√t of
other transient waveshapes is evaluated by integrating the
MOSFET power over root of time. LTspice® can be used to
simulate timer behavior for more complex transients and
cases where overvoltage and overcurrent faults coexist, as
well as the peak temperature rise of the MOSFET.
Calculating Short-Circuit Stress
SOA stress must also be calculated for a short-circuit
condition. Short-circuit P√t is given by Equation 10.
⎛
ΔV ⎞
P t = ⎜ ΔVDS • SNS ⎟ • t TMR
RSNS ⎠
⎝
(10)
where ∆VDS is the voltage across the MOSFET, ∆VSNS is
the current limit threshold and tTMR is the overcurrent
timer interval, given by Equation 5 and Equation 6.
For VIN = 15V, ∆VDS = 12V (VOUT = 3V), ∆VSNS = 50mV,
RSNS = 12mΩ, RDRN = 100kΩ and CTMR = 68nF, P√t is
2.32W√s – somewhat higher than the transient SOA calculated in the previous example.
ITMR(OC) = 0.0917 • (50mV)
•
12V
70 • 10–6
100k
The LTC4381 limits the inrush current to any load capacitance by controlling the GATE pin voltage slew rate.
Connect an external capacitor, C2, from GATE to ground
to reduce the inrush current at the expense of slower
turn-off time. The gate capacitor is set using Equation 11.
C2 = IGATE(UP) •
Automobile Cold Crank Ride Through
During cold crank, the battery potential drops from the
12V nominal to as low as 3V for up to 40ms. The LTC4381
needs at least 8V at the VCC pin to function normally.
The part can operate at 4V if the load current is low. At
VCC = 4V, the RON of the internal MOSFET is high and
this may heat up the MOSFET at high load current. The
low quiescent current requirement of the part allows
an RC filter with reasonable values to be placed at the
VCC pin to ride through cold crank as shown in Figure 4.
VIN
12V
(NOMINAL 3V
AT COLD
CRANK)
(68nF • 1.215V)
38.4µA
t TMR = 2.15ms
50mV
•
12m
2.15ms = 2.32W s
P t = (15V – 3V) •
16
RDRN
R1
10k 100k
SRC
IN
C1
6.8µF
(10a)
OUT
LTC4381-2
GND
CTMR
220nF
(10c)
GFET
GATE
SEL
TMR
(10b)
RSNS
40mΩ
12V/1A
OUTPUT
CLAMPED
AT 28.5V
COUT
22µF
SNS
DRN
VCC
ON
+ 6 • 10 –6
(11)
IINRUSH
The LTC4381 needs a minimum of 47nF capacitance (C2)
and a 33Ω (R2) resistor in series at the GATE pin to stabilize the current limit amplifier during an overcurrent event.
C2 also limits self enhancement of the MOSFET. A 10Ω
resistor, R3, is connected to the gate of the MOSFET to
suppress parasitic oscillations.
ITMR(OC) = 38.4µA
t TMR =
COUT
FLT
4381 F04
R3
10Ω
R2
33Ω
C2
47nF
Figure 4. Automotive Cold Crank Ride Through
Ignoring the supply current (ICC), the VCC potential at the
end of cold crank is given by Equation 12.
VCC = (VIN(NOM) – VIN(LOW) ) • e
–t
(12)
R1•C1 + V
IN(LOW)
Rev. A
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LTC4381
APPLICATIONS INFORMATION
where VIN(NOM) is the input voltage before the cold crank
starts, VIN(LOW) is the lowest input voltage during cold
crank, and t is the duration of the cold crank.
SRC
With the combination of R1 (10kΩ) and C1 (6.8µF), VCC
drops to 8V after the input voltage drops from 12V to 3V
for 40ms. During this time GATE stays high, keeping the
MOSFET on to continue providing current to the output.
OUT
IN
Shutdown
The LTC4381 can be shut down to a lower current mode
by pulling the ON pin below the shutdown threshold of
1.05V. The quiescent current drops down to 5µA. An
external Zener diode from the input supply to the ON pin
can be used to implement undervoltage lockout, as illustrated in Figure 7. The UV threshold is the Zener voltage
plus 1.05V.
The ON pin can be pulled up to 80V or below GND by up
to 60V without damage. Leaving the pin open allows an
internal resistor to pull it up and turn on the part. The leakage current at the pin should be limited to no more than
1µA if no pull-up device is used to help turn on the part.
Layout Considerations
To achieve accurate current sensing, use Kelvin connections to the current sense resistor (RSNS in Figure 5).
The minimum trace width for 1oz copper foil is 0.02" per
amp to ensure the trace stays at a reasonable temperature. 0.03" per amp or wider is recommended. Note that
1oz copper exhibits a sheet resistance of about 530µΩ/
square. Small resistances can cause large errors in high
current applications. During an overvoltage event, the
LTC4381 clamps the gate of the pass MOSFET to limit
the output voltage at an acceptable level. The load circuitry
may continue operating throughout this interval, but only
at the expense of dissipation in the MOSFET pass device.
The power dissipated in the MOSFET could be as high as
140W. To remove this heat, solder the IN exposed pad to
a copper trace that contains vias underneath the pad. The
SRC pins also conduct substantial heat from the MOSFET.
Connect all the SRC pins to a plane of 1oz or 2oz copper.
SRC
4381 F05
Figure 5. Recommended PCB Layout
Design Example 1
As a design example, take an application with the following specifications: VIN = 10V to 14VDC with a transient
of 100V and duration of 2ms, VOUT ≤ 20V and cold crank
to 3V for 40ms. Maximum load of 1A.
To clamp VOUT to less than 20V, the required VCC clamp
is given by Equation 13.
VCC (Clamp) = VOUT – 10.5V
= 20V – 10.5V = 9.5V
(13)
The selection of a 8.2V Zener diode for D1 limits the voltage at the VOUT to less than 20V during a 100V surge.
The minimum required voltage at the VCC pin is 8V when
VIN is at 10V; the VCC pin input current is less than 30μA.
The maximum value for R1 to ensure proper operation is
given by Equation 14.
R1=
Min VIN – Min VCC 10V – 8V
=
= 66.7k (14)
Supply Current
30µA
We used R1 of 68.1k.
The maximum current through R1 into D1 during transients is then calculated using Equation 15.
ID1 =
100V – 8.2V
= 1.35mA (15)
68.1kΩ
Rev. A
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17
LTC4381
APPLICATIONS INFORMATION
VIN
12V
IN
RDRN
82.5k
R1
68.1k
RSNS
40mΩ
SRC
12V/1A OUTPUT
CLAMPED AT 18.7V
SNS
DRN
OUT
VCC
LTC4381-4
ON
C1
0.47µF
COUT
22µF
R3
10Ω
GFET
GATE
SEL
R2
33Ω
FLT
TMR
D1
8.2V
GND
CTMR
220nF
C2
47nF
4381 F06
Figure 6. Design Example 1: 12V/1A Application Survives 100V, 2ms OV Transient
VIN
100VPK
R1
100k
RDRN
100k
IN
RSNS
40mΩ
SRC
SNS
DRN
OUT
VCC
LTC4381-4
ON
COUT
22µF
R3
10Ω
GFET
GATE
SEL
FLT
D1
68V
CMZ5945B
VOUT
CLAMPED
AT 56.7V/1A
TMR
R6
332k
R2
100Ω
GND
4381 F07
Q2
MMBT5551-7-F
CTMR
4.7µF
C2
47nF
R7
10k
D2
56V
CMZ5943B
R8
1k
Figure 7. Surge Stopper with Output Clamped Below 60V with 100V/1A/400ms Overvoltage Protection
CMHZ5237B can handle 500mW indefinitely and 1W for
1 second. Maintaining a VCC of 8V during cold crank will
require a very large C1 since D1 clamps voltage across
C1 at 8.2V when VCC=12V. We therefore use VCC of > 4V
during cold crank to calculate C1. The load current should
remain low during cold crank to avoid heating up the internal MOSFET. The VCC pin needs at least 4V to operate
through cold crank from 12V down to 3V for 40ms. The
value of C1 can be calculated by Equation 16.
VCC = [VIN(NOM) – VIN(LOW)] • e
–40ms
4V = [ 8.2V – 3V] •
18
RDRN is chosen to produce a current into the DRN pin of
1mA, during the maximum overvoltage transient event
(Equation 17). VOUT is clamped to 8.2V + 10.5V or 18.7V.
–t
R1• C1 + V
e 68.1k • C1 + 3V
C1 = –40ms/(68.1k • In
0.47μF is chosen to accommodate for the supply current
of the part and other conditions. With C1 = 0.47μF and
R1 = 68.1kΩ, high voltage transients up to 100V with a
pulse width of less than 2ms are filtered out at the VCC
pin. Longer surges are suppressed by D1.
IN(LOW)
(16)
(4V – 3V)
) = 0.357µF
(8.2V – 3V)
RDRN =
100V – 18.7V
= 81.3kΩ
1mA
(17)
82.5kΩ is chosen as the next bigger value. The GATE pin
pull-up current is 20µA typically, it takes a while to pull
the GATE pin high during input transient. So the MOSFET
sees a larger VDS initially and the worst case P√t occur
when VIN is minimum and load current is at its maximum
when the input transient occur (Equation 18).
Rev. A
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LTC4381
APPLICATIONS INFORMATION
P t = ILOAD • VDS •
t
(18)
P t = (1A) • (100V – 10V) • 2ms
P t = 4.02W s
Next calculate the sense resistor (RSNS) value with a current
limit of greater than 1A with 10% tolerance (Equation 19).
RSNS =
45mV
= 40.9mΩ
1.1• 1A
ITMR(OV) = 0.0917
ITMR(SC) = 0.0917 • (62mV)
(19)
•
We will use 40mΩ, which gives a current limit of 1.25A. Next
we select CTMR to shut off the MOSFET if the 100V transient
is longer than 2ms at maximum load of 1A (Equation 20).
VDS
A
ITMR(OV) = 0.0917
• ID •RSNS •
V
RDRN
Next, we need to check to make sure that in the case of a
severe output short where VOUT = 0V, the power dissipation in the MOSFET is also within the safe operating area
(Equation 24a & 24b).
70 [µA]
A
100V – 10V
• 1A • 0.04 •
70 [µA]
82.5k
V
(20)
(24a)
14V
70 • 10–6 + 24 • 10 –6
82.5k
ITMR(SC) = 80.8µA
tTMR = 0.22µF •
1.215V
= 3.31ms
80.8µA
(24b)
The power dissipation in the MOSFET is given by
Equation 25.
62mV
P = 14V •
= 21.7W
(25)
40mΩ
Next the value is calculated using Equation 21 to achieve
P t = 1.248W s
a fault time of greater than 2ms:
t
During an output overload or soft short, the voltage at the
CTMR = ITMR(OV) • TMR
(21)
VTMR
OUT pin could stay at 3V or higher. The total overcurrent
CTMR = 0.193µF
fault time when VOUT = 3V is given by Equation 26a & 26b.
So we choose a CTMR = of 0.22μF. Next, we need to make
ITMR(OC) = 0.0917 • (50mV)
sure that the chosen CTMR allow enough time to power up
the output (Equation 22).
(26a)
11V
•
70 • 10–6 + 6 • 10–6
ITMR(UP) • tINRUSH
82.5k
(22)
CTMR =
V
TMR
ITMR(OC) = 42.5µA
where (Equation 23).
1.215V
tTMR = 0.22µF •
= 6.29ms (26b)
VIN • COUT
42.5µA
tINRUSH =
IINRUSH
The power dissipation in the MOSFET is given by
V • C2
= IN
Equation 27.
IGATE(UP)
50mV
(23)
P = (14V – 3V) •
= 13.75W
14V • 47nF
=
= 32.9ms
(27)
40mΩ
20µA
P t = 1.09W s
ITMR(UP) ≈ 1.5µA at power up:
These conditions are within the 10W√s safe operating
32.9ms
VTMR = 1.5µA •
≈ 0.224V,
area of the MOSFET.
0.22µF
= 117.2µA
which is much lower than the 1.215V trip off threshold.
Rev. A
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19
LTC4381
APPLICATIONS INFORMATION
Design Example 2
A second design example has the following specifications:
VIN = 24VDC with a transient of 100V peak and a duration of
400ms like a load dump waveform, VOUT ≤ 60V, load of 1A.
There are a few methods to clamp VOUT to less than 60V,
we can use the LTC4381-2 by connecting SEL pin to IN to
clamp VOUT to 47V. Or we can use a LTC4381-4 and clamp
VCC to 500V Operation, Floating Topology, TSOT-8 and DFN-8 Packages
LTC4367
OV, UV and Reverse Input Protection Controller
2.5V to 60V Operation, –40V to 100V Protection, DFN-8 and MSOP-8 Packages
LTC7860
Switching Surge Stopper
3.5V to 60V Operation, >100V Protection, MSOPE-12 Package
LTC4380
Low Quiescent Current Surge Stopper
4V to 72V Operation, –60V to >100V Protection, DFN-10 and MSOP-10 Packages
26
Rev. A
07/22
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