LTC4556
Smart Card Interface
with Serial Control
Description
Features
Electrical Specifications Are ISO7816-3 and EMV
Compatible
n Control/Status Serial Port May be Daisy-Chained
for Multicard Applications
n Automatic Shutdown on Electrical Faults
n Buck Boost Charge Pump Generates 5V, 3V or 1.8V
Outputs (Smart Card Classes A, B and C)
n Automatic Level Translation
n Dynamic Pull-Ups Deliver Fast Signal Rise Times
n Supervisory Functions Prevent Smart Card Faults
n Low Operating Current: 250µA Typical
n V : 2.7V to 5.5V
IN
n Ultralow Shutdown Current
n >10kV ESD on Smart Card Pins
n Small 24-Lead 4mm × 4mm QFN Package
n
Applications
n
n
n
n
n
n
Handheld Payment Terminals
Pay Telephones
ATM Machines
POS Terminals
Computer Keyboards
Multiple S.A.M. Sockets
The LTC®4556 provides all necessary power control, level
translation and supervisory functions for a smart card or
S.A.M. card interface. The part contains a low noise charge
pump plus LDO for generating VCC power, as well as all
necessary level shifting circuitry.
The card voltage can be set to either 1.8V, 3V or 5V. The
LTC4556 includes a card detection channel with automatic
debounce circuitry. To reduce wiring costs, the LTC4556
interfaces to a microcontroller via a simple 4‑wire serial
interface. Multiple devices may be connected in daisy-chain
fashion so that the number of wires to the card socket
board is independent of the number of sockets. Status
data is returned over the same interface.
Extensive security features ensure proper deactivation
sequencing in the event of a supply fault or a smart card
electrical fault. The smart card pins can withstand greater
than 10kV ESD in-situ with no additional components.
The LTC4556 is available in a small, low profile (0.75mm),
4mm × 4mm QFN package.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners. Protected by U.S. Patents, including 6356140, 6411531.
Typical Application
240k
180k
20
1
INPUT
POWER
10
0.1µF
1µF
8
6
21
4-WIRE
COMMAND
INTERFACE
22
23
24
2
4-WIRE
CARD
INTERFACE
3
4
5
UNDERV
PRES
DVCC
Deactivation Sequence
19
VBATT
LTC4556
C8
GND
C4
I/O
FAULT
RST
DIN
CLK
DOUT
VCC
SCLK
18
RST
5V/DIV
17
16
15
CLK
5V/DIV
14
SMART CARD
13
1µF
LD
4556 TA01
VCC
5V/DIV
DATA
RIN
10µs/DIV
SYNC
ASYNC
C+ C–
11
I/O
5V/DIV
9
4556 G11.eps
CPO
12
1µF
1µF
4556fb
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1
LTC4556
Pin Configuration
VBATT, DVCC, CPO, FAULT,
UNDERV to GND........................................ –0.3V to 6.0V
PRES, DATA, RIN, SYNC, ASYNC,
LD, DIN, SCLK to GND................. –0.3V to (DVCC + 0.3V)
I/O, CLK.........................................–0.3V to (VCC + 0.3V)
ICC (Note 5).............................................................65mA
VCC Short-Circuit Duration................................ Indefinite
Operating Temperature Range (Note 4)....– 40°C to 85°C
Storage Temperature Range................... –65°C to 125°C
PRES
UNDERV
DIN
DOUT
SCLK
LD
TOP VIEW
24 23 22 21 20 19
DVCC 1
18 C8
DATA 2
17 C4
RIN 3
16 I/O
25
SGND
SYNC 4
15 RST
ASYNC 5
14 CLK
FAULT 6
13 VCC
CPO
C+
9 10 11 12
VBATT
8
C–
7
NC
(Note 1)
GND
Absolute Maximum Ratings
UF PACKAGE
24-LEAD (4mm × 4mm) PLASTIC QFN
TJMAX = 125°C, θJA = 160°C/W
EXPOSED PAD (PIN #) IS GND, MUST BE SOLDERED TO PCB
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4556EUF#PBF
LTC4556EUF#TRPBF
4556
24-Lead (4mm x 4mm) Plastic QFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
Electrical
Characteristics
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VBATT = 3.3V, DVCC = 3.3V unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input Power Supply
VBATT Operating Voltage
l
IVBATT Operating Current
VCC = 5V, ICC = 0µA
l
IVBATT Shutdown Current
No Card Present, VCPO = 0V
l
2.7
5.5
V
250
400
µA
0.5
1.75
µA
5.5
V
DVCC Operating Voltage
l
1.7
IDVCC Operating Current
l
5
25
µA
IDVCC Shutdown Current
l
0.2
1.5
µA
Charge Pump
ROLCP 5V Mode Open-Loop
Output Resistance
VBATT = 3.075V, ICPO = ICC = 60mA, (Note 3)
l
8.2
17
Ω
CPO Turn On Time
ICC = 0mA, 10% to 90%
l
0.6
1.5
ms
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LTC4556
Electrical
Characteristics
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VBATT = 3.3V, DVCC = 3.3V unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
4.65
2.75
1.65
5.0
3.0
1.8
5.35
3.25
1.95
V
V
V
Smart Card Supply
VCC Output Voltage
5V Mode, 0 < ICC < 60mA
3V Mode, 0 < ICC < 50mA
1.8V Mode, 0 < ICC < 30mA
l
l
l
VCC Turn On-Time
ICC = 0mA, 10% to 90%
l
0.8
1.5
ms
Undervoltage Detection
Relative to Nominal Output
l
–9
–5
–2.5
%
l
60
110
150
mA
l
15
32
60
ms
Overcurrent Detection
Smart Card Detection
Debounce Time (
PRES to
D7)
VPRES = 0
l
1
2.5
µA
ICC = 0mA, CVCC = 1µF
l
100
250
µs
Sink Current = –200µA
l
0.2
V
High Level Output Voltage (VOH), (Note 2)
Source Current = 200µA
l
Rise/Fall Time, (Note 2)
Loaded with 50pF, 10% to 90%
l
16
ns
PRES Pull-Up Current
Deactivation Time (
RST to VCC = 0.4V)
CLK (Non-Bidirectional Modes)
Low Level Output Voltage (VOL), (Note 2)
CLK Frequency, (Note 2)
l
VCC – 0.2
V
10
MHz
RST, C4, C8
Low Level Output Voltage (VOL), (Note 2)
Sink Current = –200µA
l
High Level Output Voltage (VOH), (Note 2)
Source Current = 200µA
l
Rise/Fall Time, (Note 2)
Loaded with 50pF, 10% to 90%
l
0.2
V
100
ns
VCC – 0.2
V
I/O, CLK (CLK Specifications in Bidirectional Mode Only)
Low Level Output Voltage (VOL), (Note 2)
Sink Current = –1mA (VDATA = 0V or VSYNC = 0V)
l
High Level Output Voltage (VOH), (Note 2)
Source Current = 20µA (VDATA = VDVCC or
VSYNC = VDVCC)
l
Rise/Fall Time, (Note 2)
Loaded with 50pF, 10% to 90%
l
Short Circuit Current, (Note 2)
VDATA = 0V or VSYNC = 0V
l
0.3
0.85 • VCC
V
V
5
500
ns
10
mA
0.3
V
DATA, SYNC (SYNC Specifications in Bidirectional Mode Only)
Low Level Output Voltage (VOL)
Sink Current = –500µA (VI/O = 0V or VCLK = 0V)
l
High Level Output Voltage (VOH)
Source Current = 20µA (VI/O = VCC or VCLK = VCC)
l
Rise/Fall Time
Loaded with 50pF
l
500
ns
0.15 • DVCC
V
0.8 • DVCC
V
RIN, DIN, SCLK, LD, SYNC, ASYNC (SYNC Specifications for Non-Bidirectional Mode)
Low Input Threshold (VIL)
l
High Input Threshold (VIH)
l 0.85 • DVCC
Input Current (IIH/IIL)
l
V
–1
1
µA
0.3
V
DOUT
Low Level Output Voltage (VOL)
Sink Current = –200µA
l
High Level Output Voltage (VOH)
Source Current = 200µA
l
DVCC – 0.3
l
1.17
V
UNDERV
Threshold
Leakage Current
VUNDERV = 3.3V
l
1.23
1.29
V
50
nA
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3
LTC4556
Electrical
Characteristics
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VBATT = 3.3V, DVCC = 3.3V unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
0.005
0.3
V
1
µA
FAULT
Low Level Output Voltage (VOL)
Sink Current = –200µA
l
Leakage Current
VFAULT = 5.5V
l
Serial Port Timing
tDS DIN Valid to SCLK Setup
8
ns
tDH DIN Valid to SCLK Hold
8
ns
tDD DOUT Output Delay
CLOAD = 15pF
15
60
ns
tL
SCLK Low Time
50
ns
tH
SCLK High Time
50
ns
tCL
SCLK to LD
50
ns
tLC
LD to SCLK
0
ns
tLFC
LD Falling to SCLK
50
ns
Note 3: ROLCP ≡ (2VBATT – VCPO)/ICPO; VCPO will depend upon total load
(ICC) and minimum supply voltage VBATT. See Figure 6.
Note 4: The LTC4556E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the – 40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 5: Based on long term current density limitation.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: This specification applies to all three smart card voltage classes:
1.8V, 3V and 5V.
Typical Performance Characteristics
No Load Supply Current vs VBATT
VCC = 5V
300
VCC = 3V
200
VCC = 1.8V
100
0
2.7
3.1
3.5
3.9 4.3 4.7 5.1
VBATT SUPPLY VOLTAGE (V)
5.5
4556 G01
5.5
10
VBATT = 2.7V
VCPO = 4.9V
CLK
5.0
I/O
4.5
4.0
3.5
–40
Charge Pump Open-Loop Output
Resistance vs Temperature
(2VBATT – VCPO) / ICPO
DVCC = VBATT = 3.3V
VCC = 5V
OUTPUT RESISTANCE (Ω)
SUPPLY CURRENT (µA)
400
6.0
TA = 25°C
ICC = 0µA
SHORT-CIRCUIT CURRENT (mA)
500
I/O and CLK Short-Circuit Current
vs Temperature
(CLK in Bidirectional Mode)
–15
10
35
TEMPERATURE (°C)
60
85
4556 G02
9
8
7
6
–40
–15
10
35
TEMPERATURE (°C)
60
85
4556 G03
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LTC4556
Typical Performance Characteristics
VCC Overcurrent Shutdown
Threshold vs Temperature
140
50
Card Detection Debounce Time vs
VBATT Supply Voltage
Bidirectional Channel (I/O) Low
Output Level vs Temperature
200
VDATA = VSYNC = 0V
IOL = –1mA
VBATT = 3V
VCC = 5V, CPO = 5.5V
110
VCC = 3V, CPO = 5.5V
100
45
TA = 85°C
40
TA = 25°C
TA = –40°C
35
30
90
80
–40
–15
10
35
TEMPERATURE (°C)
60
25
2.7
85
3.1
4556 G04
Extra Input Current vs
Load Current (IBATT – 2ICC)
125
0.1
1
10
LOAD CURRENT (mA)
100
0.8
TA = –40°C
2.0
TA = 25°C
1.5
1.0
TA = 85°C
3.1
3.5
3.9 4.3 4.7 5.1
VBATT SUPPLY VOLTAGE (V)
5.5
TA = 85°C
0
2.7
3.1
3.5 3.9 4.3 4.7 5.1
VDVCC SUPPLY VOLTAGE (V)
5.5
4556 G09
Data – I/O Channel
I/O
2V/DIV
CLK
5V/DIV
I/O
5V/DIV
I/O
5V/DIV
TA = –40°C
Deactivation Sequence
RST
5V/DIV
VCC
5V/DIV
0.4
4556 G08
4556 G07
VCPO
5V/DIV
TA = 25°C
0.6
0.2
0
2.7
Charge Pump and LDO Activation
85
VBATT = VDVCC
0.5
1
60
1.0
2.5
2
10
35
TEMPERATURE (°C)
DVCC Shutdown Current vs Supply
Voltage
VDVCC = VBATT
3
–15
4556 G06
3.0
4
0
0.01
VCC = 3V, 5V
100
–40
5.5
VCC = 1.8V
150
VBATT Shutdown Current vs
Supply Voltage
VBATT = 3.3V
TA = 25°C
5
3.9 4.3 4.7 5.1
VBATT SUPPLY VOLTAGE (V)
175
4556 G05
SUPPLY CURRENT (µA)
EXTRA INPUT CURRENT (mA)
6
3.5
SUPPLY CURRENT (µA)
120
VCC = 1.8V, CPO = 4V
DEBOUNCE TIME (ms)
LOAD CURRENT (mA)
130
I/O LOW OUTPUT VOLTAGE (mV)
VBATT = 3.3V
DATA
2V/DIV
VCC
5V/DIV
1ms/DIV
4556 G10
10µs/DIV
4556 G11
100ns/DIV
4556 G12
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5
LTC4556
Pin Functions
DVCC (Pin 1): Power. Reference voltage for the control logic.
DATA (Pin 2): Input/Output. Microcontroller side data I/O
pin. The DATA pin provides the bidirectional communica‑
tion path to the smart card. The card may be selected to
communicate via the DATA pin. If several LTC4556s are
connected in parallel, the DATA pin can be made high
impedance by selecting neither card socket. The C4 and
C8 synchronous card pins can be selected to connect to
the DATA pin via the serial port (see Table 4).
RIN (Pin 3): Input. The RIN pin supplies the RST signal to
the smart card. It is level shifted and transmitted directly
to the RST pin of a selected card. When the card is dese‑
lected, the RST pin is latched at its current state.
SYNC (Pin 4): Input-Input/Output. The SYNC pin provides
the clock input for synchronous smart cards. When a
synchronous card is selected, its CLK pin follows SYNC
directly. When a synchronous card is deselected, the CLK
pin is latched at its current state. In bidirectional mode,
the SYNC pin becomes an input/output with the smart
card CLK pin.
ASYNC (Pin 5): Input. The ASYNC pin provides the clock
input for asynchronous cards and should be connected
to a free running clock. The clock signal to the smart card
can be a ÷1, ÷2, ÷4 or ÷8 version of the signal on ASYNC.
Asynchronous cards can also be placed in clock stop mode
with the clock stopped either high or low.
FAULT (Pin 6): Output. The FAULT pin can be used as an
interrupt to a microcontroller to indicate when a fault has
occurred. It is an open drain output, which is logically
equivalent to D4 . (See Table 1)
NC (Pin 7): No Connection to chip. May be grounded.
GND (Pin 8): Ground. Power ground for the chip. This
pin should be connected directly to a low impedance
ground plane.
C –, C+ (Pins 9, 11): Charge Pump. Charge pump flying
capacitor pins. A 1µF X5R or X7R ceramic capacitor should
be connected from C+ to C–.
VBATT (Pin 10): Power. Supply voltage for analog and power
sections of the LTC4556.
CPO (Pin 12): Charge Pump. CPO is the output of the charge
pump. When the smart card requires power, the charge
pump will charge CPO to either 3.7V or 5.35V depending
on what smart card voltage is required. A low impedance
1µF X5R or X7R ceramic capacitor is required on CPO.
VCC (Pin 13): Card Socket. The VCC pin should be connected
to the VCC pin of the smart card socket. The activation of
the VCC pin is controlled by the serial port (see Tables 1
and 2) and can be set to 0V, 1.8V, 3V or 5V.
CLK (Pin 14): Card Socket. The CLK pin should be con‑
nected to the CLK pin of the smart card socket. The CLK
signal can be derived from either the SYNC input or the
ASYNC input depending on which type of card is being
accessed. The card type is selected via the serial port
(see Tables 1 and 3). In bidirectional mode, the CLK pin
becomes an input/output with the microcontroller side
SYNC pin.
RST (Pin 15): Card Socket. This pin should be connected
to the RST pin of the smart card socket. The RST signal
is derived from the RIN pin. When the card is selected,
its RST pin follows RIN. When the card is deselected, the
RST pin holds the current value on RIN.
I/O (Pin 16): Card Socket. The I/O pin connects to the
I/O pin of the smart card socket. When the smart card is
selected, its I/O pin connects to the DATA pin. When the
smart card is deselected, its I/O pin returns to the idle
state (H).
C4, C8 (Pins 17, 18): Card Socket. These pins connect to
the C4 and C8 pins of synchronous memory cards on the
smart card socket. The signal for these pins is unidirec‑
tional and can only be sent to the card. Data for C4 and
C8 is transmitted via the DATA pin and may be selected in
place of I/O via the serial port (see Table 4). When either
C4 or C8 is selected, it will follow the DATA pin. When it
is deselected, it will remain latched at its current state.
PRES (Pin 19): Card Socket. The PRES pin is used to detect
the presence of a smart card. It should be connected to a
normally open detection switch on the smart card accep‑
tor’s socket. This pin has a pull-up current source on-chip
so no external components are required.
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LTC4556
Pin Functions
UNDERV (Pin 20): Input. The UNDERV pin provides secu‑
rity by supplying a precision undervoltage threshold for
external supply monitoring. An external resistive voltage
divider programs the desired undervoltage threshold. Once
UNDERV falls below 1.23V, the LTC4556 automatically
begins the deactivation sequence.
If external supply monitoring is not required, the UNDERV
pin should be connected to either VBATT or DVCC.
SCLK. DOUT can be connected directly to a microcontroller
or the DIN pin of another LTC4556 or LTC1955 for daisy
chained operation.
SCLK (Pin 23): Input. The SCLK pin clocks the serial port.
Each new data bit is received on the rising edge of SCLK.
SCLK should be left high during idle times and should not
be clocked when LD is low.
DIN (Pin 21): Input. Input for the serial port. Command
data is shifted into DIN synchronously with SCLK. DIN can
be connected directly to a microcontroller or the DOUT
pin of another LTC4556 or LTC1955 for daisy chained
operation.
LD (Pin 24): Input. The falling edge of this pin loads the
current state of the shift register into the command regis‑
ter. Command changes to the smart card will be updated
on the falling edge of LD. The rising edge of LD latches
status information into the shift register for the next read/
write cycle.
DOUT (Pin 22): Output. Output for the serial port. Smart
card status data is shifted out of DOUT synchronously with
SGND (Pin 25): Exposed Pad. Must be soldered to PCB
Ground.
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7
LTC4556
Block Diagram
CHARGE PUMP
C+
C–
GND
VBATT
CPO
11
9
8
10
12
CHARGE
PUMP
13 VCC
LDO
16 I/O
17 C4
DATA 2
ASYNC 5
SMART
CARD
COMMUNICATIONS
SYNC 4
RIN 3
SMART
CARD
SOCKET
18 C8
CLOCK
CONTROL
LOGIC
14 CLK
RESET
CONTROL
LOGIC
15 RST
τ
19 PRES
6
FAULT
STATUS DATA
DIN 21
SERIAL PORT
COMMAND/STATUS
DATA
DOUT 22
SCLK 23
1 DVCC
SHIFT REGISTER
DIGITAL
SUPPLY
LD 24
–
20 UNDERV
COMMAND LATCH
+
1.23V
+
–
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LTC4556
Operation
Serial Port
• Clock mode of the card (synchronous, asynchronous
or bidirectional)
The microcontroller compatible serial port provides all of
the command and control inputs for the LTC4556 as well
as the status of the smart card. Data on the DIN input is
loaded on the rising edge of SCLK. D7 is loaded first and
D0 last. At the same time the command bits are being
shifted into the DIN input, the status bits are being shifted
out of the DOUT output. The status bits are presented to
DOUT on the rising edge of SCLK. Once all bits have been
clocked into the shift register, the command data is loaded
into the command latch by bringing LD low. At this time
the command latch is updated and the LTC4556 will begin
to act on the new command set. The status data is latched
into the shift register on the rising edge of LD. SCLK should
be low when LD is brought low and should be high when
LD is brought high. This requires a 9th clock cycle per
transaction. Figure 2 shows the recommended operation
of the serial port.
• Operating mode of asynchronous cards (clock stop
high, low, ÷1, ÷2, ÷4 or ÷8)
• Selection of the I/O, C4 or C8 pins
The serial port provides the following status data:
• It indicates the presence or absence of the smart card.
• It indicates the readiness of the smart card VCC supply.
Communication with the smart card is disabled until its
power supply voltage has reached the final value.
• It indicates fault status. In the event of an electrical or
ATR fault, the fault is reported. For electrical faults, the
LTC4556 will automatically deactivate the smart card.
Table 1 illustrates the command inputs and status outputs
associated with each bit of the serial data word.
Three voltage options are available from the LTC4556:
5V, 3V and 1.8V. Bits D0, D1 determine which voltage is
selected. Setting both control bits to 0 deactivates the
card and sets the smart card supply voltage to 0V. Table 2
shows the operation of the supply control bits.
Multiple LTC4556s may be daisy chained together by
connecting the DOUT pin of one LTC4556 to the DIN pin of
another. Figure 7 shows an example of an LTC4556 daisy
chained together with LTC1955s.
The maximum clock rate for the serial port is 10MHz.
The CLK pin to the smart card can be programmed for
various modes. Both synchronous and asynchronous
cards are supported. There are several options available
with asynchronous cards. Table 3 shows how all clock
options are obtained using bits D5–D7.
The serial port controls the following parameters of the
smart card socket:
• Selection/deselection of the smart card
• VCC voltage level of the card (5V/3V/1.8V/0V)
READ/WRITE CYCLE
tLC
tDS
tDH
tH
tDD
tL
tCL
tLFC
tCL
SCLK
DIN
X
D7
D6
D2
D1
D0
X
LD
DOUT
D7
D6
D5
D1
D0
D7 FROM
INPUT
D7
4556 F02
Figure 2. Serial Port Timing Diagram
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9
LTC4556
Operation
current passes from the receiving side of the channel to the
transmitting side. The low output voltage of the receiving
side will be dependent upon the voltage at the transmitting
side plus the IR drop of the pass transistor.
Table 1. Serial Port Commands
STATUS OUTPUT
BIT
COMMAND INPUT
0
D0
VCC Options
0
D1
(See Table 2)
0
D2
Card Select/Deselect
0
D3
Card Communications
Card Electrical Fault
D4
Options (See Table 4)
Card ATR Fault
D5
Card Clock Options
Card VCC Ready
D6
(See Table 3)
Card Present
D7
When a card socket is selected, it becomes a candidate to
drive data on the DATA pin and likewise receive data from
the DATA pin. When a card socket is deselected, the volt‑
age on its I/O pin will return to the idle state (H) and the
DATA side of that channel will become high impedance.
The LTC4556 includes provision for unidirectional com‑
munication with the C4 and C8 pins of the smart card.
The C4, C8 and I/O pins are individually multiplexed to
the DATA pin using bits D3 and D4 as shown in Table 4.
Table 2. VCC and Shutdown Options
D1
D0
STATUS
0
0
VCC = 0V (Shutdown)
0
1
VCC = 1.8V
Table 4. Communications Options
1
0
VCC = 3V
D4
D3
COMMUNICATION MODE
1
1
VCC = 5V
0
0
Nothing Selected
0
1
C4 Connected to DATA Pin
1
0
C8 Connected to DATA Pin
1
1
I/O Connected to DATA Pin
Table 3. Clock Options
D7
D6
D5
CLOCK MODE
0
0
0
Synchronous Mode
0
0
1
Bidirectional Mode
0
1
0
Asynchronous Stop Low
0
1
1
Asynchronous Stop High
1
0
0
Asynchronous ÷1
1
0
1
Asynchronous ÷2
1
1
0
Asynchronous ÷4
1
1
1
Asynchronous ÷8
Dynamic Pull-Up Current Sources
To receive status data from the serial port, a read/write
operation must be performed. When polling for the pres‑
ence of a smart card, the input word may be set to $00
since this is the shutdown command for the LTC4556.
Data Channel
The data channel is level shifted to the appropriate VCC
voltages at the I/O pin.
An NMOS pass transistor performs the level shifting. The
gate of the NMOS transistor is biased such that the transis‑
tor is completely off when both sides have relinquished
the channel. If one side of the channel asserts an L, then
the transistor will convey the L to the other side. Note that
The current sources on the bidirectional pins (DATA, I/O)
are dynamically activated to achieve a fast rise time with
a relatively small static current. Once a bidirectional pin
is relinquished, a small start up current begins to charge
the node. An edge rate detector determines if the pin is
released by comparing its slew rate with an internal refer‑
ence value. If a valid transition is detected, a large pull-up
current enhances the edge rate on the node. The higher
slew rate corroborates the decision to charge the node
thereby affecting a dynamic form of hysteresis.
LOCAL
SUPPLY
+
ISTART
BIDIRECTIONAL
PIN
VREF
–
dv
dt
4556 F03
Figure 3. Dynamic Pull-Up Current Sources
4556fb
10
For more information www.linear.com/LTC4556
LTC4556
Operation
As described in the section Serial Port, the LTC4556 sup‑
ports both synchronous and asynchronous smart cards.
When bits D5-D7 are set to 0s, the clock channel is in
synchronous mode.
In synchronous mode, the CLK pin follows the SYNC pin for
a channel that is selected. If the channel is deselected (via
the serial port) the CLK line is latched at its current value.
When control bits D7, D6 and D5 are set to 0, 0 and 1
respectively, the clock channel is in bidirectional mode.
This mode permits clock stretching when communicating
with bidirectional cards. The bidirectional level translation
circuit is identical to the I/O-DATA circuit. A low can be
asserted from either the SYNC pin or the CLK pin and the
other pin will follow. The low can be “handed off” to affect
clock stretching if both sides assert at the same time. It
will not run as fast as the unidirectional synchronous or
asynchronous modes but does employ accelerating pull-up
sources on both sides for maximum clock rate.
In asynchronous mode the CLK pin follows either the
ASYNC pin (÷1 mode) or a divided version of this pin. The
CLK pin can also be stopped high or low. The available di‑
vider ratios include ÷2, ÷4 and ÷8. When switching between
divider ratios, the internal selection circuitry ensures that
no spikes or glitches appear on the CLK pin. Consequently,
it may take up to 8 clock pulses for the clock frequency
change command to take affect. Synchronization circuitry
ensures that no glitches occur when entering or exiting
one of the stop modes. For example, when entering Stop
Low mode, the selection circuitry waits for the next falling
edge of the CLK signal to make the change. Likewise if
Stop High is selected it will occur on the next rising edge.
Deselection of an asynchronous card does not affect its
CLK pin. Its clock can be started, stopped or its divider
ratio changed at any time.
To clean up the duty cycle of the incoming clock in asyn‑
chronous applications, any of the clock divider modes ÷2,
÷4 or ÷8 will yield a very nearly 50% duty cycle.
Additional synchronization circuitry prevents glitches from
occurring when switching between synchronous mode and
asynchronous mode. Because of this circuitry, two edges
(a falling edge followed by a rising edge) are necessary
at the CLK pin to switch modes from asynchronous to
synchronous. For example, if clock stop mode is engaged,
the clock channel will not change modes until clock stop
mode is disengaged.
Both SYNC and ASYNC inputs are independently level
shifted to the appropriate voltage for the CLK pin (5V, 3V,
1.8V).
Reset Channel
When the card is selected, the reset channel provides a
level shifted path from the RIN pin to the RST pin. When
the card is deselected its RST pin is latched at the current
value of RIN.
Smart Card Detection Circuit
The PRES pin is used to detect the presence of a smart
card. An automatic debounce circuit waits until a smart
card has been present for a continuous period of typically
32ms. Once a valid card indication exists, the status bit
is updated and may be polled by cycling data through the
serial port. The DOUT pin (equivalent to D7) of the serial
port can be used to indicate the presence of a card in real
time if LD is held low.
The PRES pin has a built-in pull-up current source so no
external components are required for switch detection.
The pull-up current source is designed to have a small
current when the pin voltage is below approximately 1V
but somewhat higher current when the pin voltage reaches
1V. This helps maintain low power dissipation when a card
is present and yet fast response time to a card removal.
Activation/Deactivation
For maximum flexibility, the activation sequencing of the
smart card is left to the application programmer. However,
deactivation can be achieved either manually or automati‑
cally. An electrical fault condition will trigger the automatic
deactivation.
4556fb
For more information www.linear.com/LTC4556
11
LTC4556
Operation
The built-in deactivation sequence can be executed via the
serial port simply by setting the control bits D0 and D1
to 0. The deactivation sequence is outlined below.
1. The RST pin is immediately brought low.
2. The deactivation of the CLK pin depends upon which
type of card is used:
If the smart card was set to asynchronous mode then
the CLK pin will be latched low on its next falling edge.
If no falling edges occur within 5µs (min) then the CLK
line is forced low.
If the smart card was set to synchronous mode then
the CLK pin is immediately latched at its current value
(either high or low) and then forced low after a duration
of 5µs (min). During the 5µs timeout period, changes
on SYNC will be ignored.
3. The I/O, C4 and C8 pins are brought low.
4. The VCC pin is brought low.
Upon activation, to comply with relevant smart card stan‑
dards, none of the smart card signal pins will be allowed
to go high before the smart card supply voltage (VCC) has
reached its final value.
Electrical Fault Detection
Several types of faults are detected by the LTC4556. They
include VCC undervoltage, VCC overcurrent, CLK, RST, C8,
C4 short circuit, card removal during a transaction, failed
answer to reset (ATR), supply undervoltage or UNDERV
and chip overtemperature. To prevent false errors from
plaguing the microcontroller, the electrical faults are acted
upon only after a 5µs (min) timeout period. Card removal
during transaction faults initiate the deactivation sequence
immediately.
VCC undervoltage faults are determined by comparing the
actual output voltage with the internal reference voltage.
If the output is more than ~5% below its set point for
the entire timeout period, the fault is reported and the
deactivation sequence is initiated.
VCC overcurrent faults are detected by comparing the output
current of the LDOs with an internal reference level. If the
current of the LDO is more than 110mA (typ) for the entire
timeout period, the fault is reported and the deactivation
sequence is initiated.
CLK and RST faults are detected by comparing the outputs
of these pins with their expected signals. If the signal on
a pin is incorrect for the entire timeout period, the fault is
reported and the deactivation sequence is initiated.
The clock channel is a special case. Since it can have a free
running clock, the error indication is accumulated over a
longer period of time without being cleared. Even though
the clock may be running, an error will still be detected.
An overtemperature fault is detected by sensing the
junction temperature of the IC. If the junction tempera‑
ture exceeds approximately 150°C for the entire timeout
period, the fault is reported by setting the fault bit (D4)
and the deactivation sequence is initiated.
A card removal fault is determined as soon as the PRES
pin is high. Once this occurs the fault is reported and the
deactivation sequence is initiated.
If no card is present, and the application software attempts
to power up a card socket, an automatic fault will result.
Short circuits on the I/O line will not be detected by the
fault detection hardware; however, a short circuit from I/O
to VCC will be compliant with the maximum current limits
set by applicable standards (
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