LTC4558EUD

LTC4558 Dual SIM/Smart Card Power Supply and Interface FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTION Power Management and Control for Two SIM Cards or Smart Cards Independent 1.8V/3V VCC Control for Both Cards Supports Simultaneous Powering of Both Cards Fast Channel Switching Automatic Level Translation Dynamic Pull-Ups Deliver Fast Signal Rise Times* Built-In Fault Protection Circuitry Automatic Activation/Deactivation Sequencing Circuitry Low Operating/Shutdown Current > 10kV ESD on SIM Card Pins Meets EMV Fault Tolerance Requirements Low Profile 20-Lead (3mm × 3mm) QFN Package The LTC®4558 provides the power conversion and signal level translation needed for advanced cellular telephones to interface with 1.8V or 3V subscriber identity modules (SIMs). The device meets all requirements for 1.8V and 3V SIMs and contains LDO regulators to power 1.8V or 3V SIM cards from a 2.7V to 5.5V input. The output voltages can be set using the two voltage selection pins and up to 50mA of load current can be supplied. A channel select pin determines which channel is open for communication. Separate enable pins for each channel allow both cards to be powered at once and allow for faster transition from one channel to the other. Internal level translators allow controllers operating with supplies as low as 1.4V to interface with 1.8V or 3V Smart Cards. Battery life is maximized by a low operating current of 65μA and a shutdown current of less than 1μA. Board area is minimized by the low profile 3mm × 3mm × 0.75mm leadless QFN package. APPLICATIONS ■ ■ ■ GSM, TD-SCDMA and other 3G+ Cellular Phones Wireless Point-of-Sale Terminals Multiple SIM Card Interfaces , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. *Protected by U.S. Patents, including 6356140. TYPICAL APPLICATION DVCC VBATT 1.4V TO 4.4V 3V TO 6V DVCC DVCC μCONTROLLER Deactivation Sequence 0.1μF 0.1μF VBATT CLKIN I/OA RSTIN RSTA DATA CLKA CLKRUNA VCCA C7 C2 I/O RST C3 CLK C1 VCC 1μF CLKRUNB 1μF ENABLEB VCCB CSEL CLKB VSELA RSTB VSELB LTC4558 I/OB C1 C3 C2 C7 VCC CLK RST RSTX 5V/DIV CLKX 5V/DIV GND C5 GND ENABLEA 1.8V/3V SIM CARD A 1.8V/3V SIM CARD B I/OX 5V/DIV VCCX 2V/DIV CVCCX = 1μF 10μs/DIV 4558 TA02 I/O GND C5 4558 TA01 4558fa 1 LTC4558 ABSOLUTE MAXIMUM RATINGS PACKAGE/ORDER INFORMATION (Note 1) VSELB ENABLEB I/OB CLKB RSTB TOP VIEW VBATT, DVCC, DATA, RSTIN, CLKIN, CLKRUNA, CLKRUNB, ENABLEA, ENABLEB, CSEL, VSELA, VSELB to GND ............................................. –0.3V to 6V I/OA, CLKA, RSTA ........................ –0.3V to VCCA + 0.3V I/OB, CLKB, RSTB ........................ –0.3V to VCCB + 0.3V ICCA,B (Note 4) .......................................................80mA VCCA,B Short-Circuit Duration ........................... Indefinite Operating Temperature Range (Note 3) ...–40°C to 85°C Storage Temperature Range...................–65°C to 125°C 20 19 18 17 16 15 CLKRUNB VCCB 1 14 CLKRUNA DVCC 2 13 CSEL 21 VBATT 3 12 VSELA VCCA 4 11 ENABLEA 7 8 9 10 I/OA DATA RSTIN CLKIN 6 RSTA CLKA 5 UD PACKAGE 20-LEAD (3mm × 3mm) PLASTIC QFN TJMAX = 125°C, θJA = 68°C/W, θJC = 4.2°C/W EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB ORDER PART NUMBER UD PART MARKING LTC4558EUD LCSH Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VBATT = 3.3V, DVCC = 1.8V, CA = CB = 1μF, unless otherwise specified. PARAMETER CONDITIONS MIN TYP MAX UNITS Input Power Supply ● VBATT Operating Voltage IVBATT Operating Current VCCA = 3V, VCCB = 0V, ICCA = 0μA VCCA = 1.8V, VCCB = 0V, ICCA = ICCB = 0μA 2.7 ● 65 65 5.5 V 100 100 μA μA 5.5 V DVCC Operating Voltage ● IDVCC Operating Current ● 6 15 μA IDVCC Shutdown Current ● 0.1 1 μA DVCC = 0V ● 0.1 1 μA VCCA,B Output Voltage 3V Mode, 0mA < ICCA,B < 50mA 1.8V Mode, 0mA < ICCA,B < 30mA ● ● 3.00 1.8 3.15 1.89 V V VCCA,B Turn-On Time ICCA,B = 0mA, ENABLEA,B ● 0.8 1.5 ms Channel Switching Time ENABLEA = ENABLEB = RSTIN = DVCC CSEL to RSTB ● 1 IVBATT Shutdown Current 1.4 SIM Card Supplies to VCCA,B at 90% Selected Voltage 2.85 1.71 μs 4558fa 2 LTC4558 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VBATT = 3.3V, DVCC = 1.8V, CA = CB = 1μF, unless otherwise specified. PARAMETER CONDITIONS MIN TYP MAX UNITS CLKA,B Low Level Output Voltage (VOL) Sink Current = – 200μA (Note 2) ● High Level Output Voltage (VOH) Source Current = 200μA (Note 2) ● Rise/Fall Time Loaded with 50pF (10% to 90%) (Note 2) ● CLKA,B Frequency (Note 2) ● Low Level Output Voltage (VOL) Sink Current = – 200μA (Note 2) ● High Level Output Voltage (VOH) Source Current = 200μA (Note 2) ● Rise/Fall Time Loaded with 50pF (10% to 90%) (Note 2) ● 100 ns Low Level Output Voltage (VOL) Sink Current = – 1mA (VDATA = 0V) (Note 2) ● 0.3 V High Level Output Voltage (VOH) Source Current = 20μA (VDATA = VDVCC) (Note 2) ● Rise/Fall Time Loaded with 50pF (10% to 90%) (Note 2) ● VDATA = 0V (Note 2) ● Low Level Output Voltage (VOL) Sink Current = – 500μA (VI/OA,B = 0V) ● High Level Output Voltage (VOH) Source Current = 20μA (VI/OA,B = VCCA,B) ● Rise/Fall Time Loaded with 50pF (10% to 90%) ● 0.2 VCCA,B –0.2 V V 16 10 ns MHz RSTA,B 0.2 VCCA,B –0.2 V V I/OA, I/OB Short-Circuit Current 0.85 • VCCA,B V 5 500 ns 10 mA 0.3 V DATA 0.8 • DVCC V 125 500 ns 0.15 • DVCC V ENABLEA, ENABLEB, RSTIN, CLKIN, CSEL, VSELA, VSELB, CLKRUNA, CLKRUNB Low Input Threshold (VIL) ● High Input Threshold (VIH) ● 0.85 • DVCC Input Current (IIH/IIL) ● –1 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: This specification applies to both Smart Card classes. V 1 μA Note 3: The LTC4558E is guaranteed to meet performance specifications from 0°C to 85°C. Specifications over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 4: Based on long-term current density limitations. 4558fa 3 LTC4558 TYPICAL PERFORMANCE CHARACTERISTICS I/OX Short-Circuit Current vs Temperature 7.0 VBATT SUPPLY CURRENT (μA) SHORT-CIRCUIT CURRENT (mA) TA = 25°C ICCA = ICCB = 0μA 95 90 85 DROPOUT 80 75 VCCX = 3V 70 65 VCCX = 1.8V 60 6.5 VBATT Quiescent Current (IVBATT – ICC) vs Load Current 250 VDVCC = VBATT = 5.5V VCCX = 3V I/OX SHORTED TO VCCX VBATT QUIESCENT CURRENT (μA) No Load Supply Current vs VBATT 100 TA = 25°C unless otherwise noted. 6.0 5.5 5.0 4.5 TA = 25°C VBATT = 3.1V 200 150 100 50 55 4.0 –40 50 2.7 3.1 3.9 4.3 4.7 5.1 VBATT SUPPLY VOLTAGE (V) 3.5 5.5 0 –15 35 10 TEMPERATURE (°C) 60 VBATT Shutdown Current vs Supply Voltage DVCC SHUTDOWN CURRENT (μA) VBATT SHUTDOWN CURRENT (μA) TA = –40°C 3.0 2.5 2.0 TA = 85°C 1.0 0.5 0 2.7 3.1 100000 4557 G03 0.6 VDVCC = 1.8V 1.5 100 1000 10000 LOAD CURRENT (μA) DVCC Shutdown Current vs Supply Voltage 3.5 TA = 25°C 10 4557 G02 4557 G01 4.0 85 5.1 4.7 3.5 3.9 4.3 VBATT SUPPLY VOLTAGE (V) 5.5 4557 G04 0.5 VBATT = 5.5V TA = –40°C TO 85°C 0.4 0.3 0.2 0.1 0 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6 DVCC SUPPLY VOLTAGE (V) 4557 G05 4558fa 4 LTC4558 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise noted. Data – I/O Channel, CL = 40pF I/0X 1V/DIV DATA 1V/DIV 200ns/DIV 4557 G06 Deactivation Sequence, CVCCX = 1μF RSTX 5V/DIV CLKX 5V/DIV I/OX 5V/DIV VCCX 2V/DIV 20μs/DIV 4557 G07 4558fa 5 LTC4558 PIN FUNCTIONS DVCC (Pin 2): Power. Reference voltage for the control logic. VBATT (Pin 3): Power. Supply voltage for the analog sections of the LTC4558. VCCA,VCCB (Pins 4, 1): Card Socket. The VCCA,VCCB pins should be connected to the VCC pins of the respective card sockets. The activation of the VCCA,VCCB pins are controlled by ENABLEA and ENABLEB. They can be set to 1.8V or 3V via the VSELA and VSELB inputs. CLKA,CKLB (Pins 5, 20): Card Socket. The CLKA,CKLB pins should be connected to the CLK pins of the respective card sockets. The CLKA,CKLB signals are derived from the CLKIN pin. They provide a level shifted CLKIN signal to the selected card. The CLKA,CKLB pins are gated off until VCCA,VCCB attain their correct values. When a card socket is deselected, its CLK pin may be left active or brought LOW using the CLKRUNA, CLKRUNB pins. RSTA,RSTB (Pins 6, 19): Card Socket. The RSTA,RSTB pins should be connected to the RST pins of the respective card sockets. The RSTA,RSTB signals are derived from the RSTIN pin. When a card is selected, its RST pin follows RSTIN. The RSTA,RSTB pins are gated off until VCCA,VCCB attain their correct values. When a card socket is deselected, the state of its RST pin is latched to its current state. I/OA,I/OB (Pins 7, 18): Card Socket. The I/OA,I/OB pins should be connected to the I/O pins of the respective card sockets. When a card is selected, its I/O pin transmits/receives data to/from the DATA pin. The I/OA,I/OB pins are gated off until VCCA,VCCB attain their correct values. DATA (Pin 8): Input/Output. Microcontroller side data I/O pin. The DATA pin provides the bidirectional communication path to both cards. One of the cards may be selected to communicate via the DATA pin at a time. The pin possesses a weak pull-up current source, allowing the controller to use an open drain output and maintain a HIGH state during shutdown, as long as DVCC is powered. RSTIN (Pin 9): Input. The RSTIN pin supplies the reset signal to the cards. It is level shifted and transmitted directly to the RST pin of the selected card. CLKIN (Pin 10): Input. The CLKIN pin supplies the clock signal to the cards. It is level shifted and transmitted directly to the CLK pin of the selected card. If CLKRUNA,B is HIGH, the clock signal will be transmitted to the CLKA,B pin, regardless of whether that card is selected, as long as that card socket is enabled. ENABLEA, ENABLEB (Pins 11, 17): Inputs. The ENABLEA and ENABLEB pins enable or disable channel A and channel B, respectively. VSELA, VSELB (Pins 12, 16): Inputs. The VSELA and VSELB pins select the voltage level of each set of SIM/ Smart Card pins. Bringing either of these pins HIGH will set the output level of its respective channel to 3V. Bringing either of these pins LOW will set the output level of its respective channel to 1.8V. CSEL (Pin 13): Input. The CSEL pin selects which set of SIM/Smart Card pins are active. CLKRUNA, CLKRUNB (Pins 14, 15): Inputs. The CLKRUNA and CLKRUNB inputs are used to select whether the clock signal is always sent to card sockets that are enabled or whether the clock is gated with the CSEL pin. Exposed Pad (Pin 21): Ground. This ground pad must be soldered directly to a PCB ground plane. 4558fa 6 LTC4558 BLOCK DIAGRAM VCCA 4 DVCC VBATT 2 3 LDOA 1 VCCB LDOB DVCC I/OA 7 18 I/OB RSTA 6 19 RSTB CLKA 5 20 CLKB CLKRUNA 14 15 CLKRUNB DVCC DATA 8 RSTIN 9 21 13 GND CSEL 12 11 16 VSELA ENABLEA VSELB 17 4558 BD CONTROL LOGIC CLKIN 10 ENABLEB 4558fa 7 LTC4558 OPERATION The LTC4558 features two independent SIM/Smart Card channels. Only one of these channels may be open for communication at a time however both channels can be enabled and made ready for communication using the ENABLEA and ENABLEB pins. This allows faster transition from one channel to the other. Each channel is able to produce two voltage levels, 1.8V and 3V. The channel selection and voltage selection are controlled by the CSEL, VSELA and VSELB pins as shown in the table below: Table 1. Channel and Voltage Truth Table CSEL VSELA VSELB SELECTED CARD VOLTAGES A B 0 0 0 A 1.8V 1.8V 0 0 1 A 1.8V 3V 0 1 0 A 3V 1.8V 0 1 1 A 3V 3V 1 0 0 B 1.8V 1.8V 1 0 1 B 1.8V 3V 1 1 0 B 3V 1.8V 1 1 1 B 3V 3V Dynamic Pull-Up Current Sources The current sources on the bidirectional pins (DATA,I/OA,B) are dynamically activated to achieve a fast rise time with a relatively small static current. Once a bidirectional pin is relinquished, a small start-up current begins to charge the node. An edge rate detector determines if the pin is released by comparing its slew rate with an internal reference value. If a valid transition is detected, a large pull-up current enhances the edge rate on the node. The higher slew rate corroborates the decision to charge the node thereby affecting a dynamic form of hysteresis. LOCAL SUPPLY + VREF ISTART – dv dt 4558 F01 BIDIRECTIONAL PIN Figure 1. Dynamic Pull-Up Current Source Bidirectional Channels Reset Channels The bidirectional channels are level shifted to the appropriate VCCA,B voltages at the I/OA,B pins. An NMOS pass transistor performs the level shifting. The gate of the NMOS transistor is biased such that the transistor is completely off when both sides have relinquished the channel. If one side of the channel asserts a LOW, then the transistor will convey the LOW to the other side. Note that current passes from the receiving side of the channel to the transmitting side. The low output voltage of the receiving side will be dependent upon the voltage at the transmitting side plus the IR drop of the pass transistor. When a card is selected, the reset channel provides a level shifted path from the RSTIN pin to the RST pin of the selected card. When a card is deselected, the last state of the RSTA,B pin is latched. This allows a deselected card to remain active, and therefore eliminates delays associated with card initialization. When a card socket is selected, it becomes a candidate to drive data on the DATA pin and likewise receive data from the DATA pin. When a card socket is deselected, its I/O pin will be pulled HIGH and communication with the DATA pin will be disabled. If both channels are disabled, a weak pull-up ensures that the DATA pin is held HIGH, as long as DVCC is powered. Clock Run Mode Various SIM/Smart Cards may have different requirements for the state of the clock pin when the channel is not open for communication. The CLKRUNA,B pins allow the user to select whether the clock is brought LOW after the channel is deselected or allowed to run. If a channel is enabled, bringing its CLKRUN pin HIGH will transmit the clock to the corresponding card socket, whether or not the channel is selected using the CSEL. 4558fa 8 LTC4558 OPERATION Activation/Deactivation Fault Detection Activation and deactivation sequencing is handled by builtin circuitry. Each channel may be activated or deactivated independently of the other. The activation sequence for each channel is initiated by bringing the ENABLEA,B pin HIGH. The activation sequence is outlined below: The VCCA,B, I/OA,B, RSTA,B, CLKA,B and DATA pins are all protected against short-circuit faults. While there are no logic outputs to indicate that a fault has occurred, these pins will be able to tolerate the fault condition until it has been removed. 1. The RSTA,B, CLKA,B and I/OA,B pins are held LOW. The VCCA,B, I/OA,B, and RSTA,B pins possess fault protection circuitry which will limit the current available to the pins. Each VCC pin is capable of supplying approximately 90mA (typ) before the output voltage is reduced. 2. VCCA,B is enabled. 3. After VCCA,B is stable at its selected level, the I/OA,B and RSTA,B channels are enabled. 4. The clock channel is enabled on the rising edge of the second clock cycle after the I/OA,B pin is enabled. The deactivation sequence is initiated by bringing the ENABLEA,B pin LOW. The deactivation sequence is outlined below: 1. The reset channel is disabled and RSTA,B is brought LOW. The CLKA,B pins are designed to tolerate faults by reducing the current drive capability of their output stages. After a fault is detected by the internal fault detection logic, the logic waits for a fault detection delay to elapse before reducing the current drive capability of the output stage. The reduced current drive allows the LTC4558 to detect when the fault has been removed. 2. The clock channel is disabled and the CLKA,B pin is brought LOW two clock cycles after ENABLEA,B is brought LOW. If the clock is not running, the clock channel will be disabled approximately 9μs after the ENABLEA,B pin is brought LOW. 3. The I/O channel is disabled and the I/OA,B pin is brought LOW approximately 9μs after the ENABLEA,B pin is brought LOW. 4. VCCA,B will be depowered after the I/OA,B pin is brought LOW. The activation or deactivation sequences will take place every time a card channel is enabled or disabled. When a channel is deselected using the CSEL pin, the RSTA,B state is latched, the I/OA,B channel becomes high impedance and CLKA,B is brought LOW after a maximum of two clock cycles. 4558fa 9 LTC4558 APPLICATIONS INFORMATION 10kV ESD Protection All Smart Card pins (CLKA,B, RSTA,B, I/OA,B, VCCA,B and GND) can withstand over 10kV of human body model ESD in-situ. In order to ensure proper ESD protection, careful board layout is required. The GND pin should be tied directly to a ground plane. The VCCA,B capacitors should be located very close to the VCCA,B pins and tied immediately to the ground plane. packing density but poor performance over their rated voltage or temperature ranges. Under certain voltage and temperature conditions Y5V, X5R and X7R ceramic capacitors can be compared directly by case size rather than specified value for a desired minimum capacitance. The VCCA,B outputs should be bypassed to GND with a 1μF capacitor. A low ESR ceramic capacitor is recommended on each VCC pin to ensure ESD compliance. VBATT and DVCC should be bypassed with 0.1μF ceramic capacitors. Capacitor Selection A total of four capacitors is required to operate the LTC4558. An input bypass capacitor is required at VBATT and DVCC. Output bypass capacitors are required on each of the Smart Card VCC pins. There are several types of ceramic capacitors available, each having considerably different characteristics. For example, X7R ceramic capacitors have excellent voltage and temperature stability but relatively low packing density. Y5V and X5R ceramic capacitors have apparently higher Compliance Testing Inductance due to long leads on type approval equipment can cause ringing and overshoot that leads to testing problems. Small amounts of capacitance and damping resistors can be included in the application without compromising the normal electrical performance of the LTC4558 or Smart Card system. Generally a 100Ω resistor and a 20pF capacitor will accomplish this, as shown in Figure 2. 1μF LTC4558 VCCA,B CLKA,B 20pF 100Ω 20pF 100Ω RSTA,B SMART CARD SOCKET 20pF 100Ω I/OA,B 20pF 4558 F02 Figure 2. Additional Components for Improved Compliance Testing 4558fa 10 LTC4558 PACKAGE DESCRIPTION UD Package 20-Lead Plastic QFN (3mm × 3mm) (Reference LTC DWG # 05-08-1720 Rev A) 0.70 ±0.05 3.50 ± 0.05 (4 SIDES) 1.65 ± 0.05 2.10 ± 0.05 PACKAGE OUTLINE 0.20 ±0.05 0.40 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 3.00 ± 0.10 (4 SIDES) BOTTOM VIEW—EXPOSED PAD R = 0.115 TYP 0.75 ± 0.05 R = 0.05 TYP PIN 1 TOP MARK (NOTE 6) PIN 1 NOTCH R = 0.20 TYP OR 0.25 × 45° CHAMFER 19 20 0.40 ± 0.10 1 2 1.65 ± 0.10 (4-SIDES) (UD20) QFN 0306 REV A 0.200 REF 0.00 – 0.05 NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.20 ± 0.05 0.40 BSC 4558fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 11 LTC4558 TYPICAL APPLICATION DVCC VBATT 1.4V TO 4.4V 3V TO 6V DVCC C3 0.1μF μCONTROLLER DVCC VBATT CLKIN I/OA RSTIN RSTA DATA CLKA CLKRUNA VCCA C4 0.1μF C7 C2 RST C3 CLK C1 C1 1μF CLKRUNB I/O VCC ENABLEB VCCB CSEL CLKB VSELA RSTB I/OB VSELB LTC4558 C2 1μF GND C5 GND ENABLEA 1.8V/3V SIM CARD A C1 C3 C2 C7 VCC CLK RST 1.8V/3V SIM CARD B I/O GND C5 4558 TA01a RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1555L/ LTC1555L-1.8 1MHz, SIM Power Supply and Level Translator for 1.8V/3V/5V SIM Cards VIN: 2.6V to 6.6V, VOUT = 1.8V/3V/5V, IQ = 32μA, ISD < 1μA, SSOP16 LTC1555/LTC1556 650kHz, SIM Power Supply and Level Translator for 3V/5V SIM Cards VIN: 2.7V to 10V, VOUT = 3V/5V, IQ = 60μA, ISD < 1μA, SSOP16, SSOP20 LTC1755/LTC1756 850kHz, Smart Card Interface with Serial Control for 3V/5V Smart Card Applications VIN: 2.7V to 7V, VOUT = 3V/5V, IQ = 60μA, ISD < 1μA, SSOP16, SSOP24 LTC1955 Dual Smart Card Interface with Serial Control for 1.8V/3V/5V Smart Card Applications VIN: 3V to 5.5V, VOUT = 1.8V/3V/5V, IQ = 200μA, ISD < 1μA, QFN32 LTC1986 900kHz, SIM Power Supply for 3V/5V SIM Cards VIN: 2.6V to 4.4V, VOUT = 3V/5V, IQ = 14μA, ISD < 1μA, ThinSOT LTC4555 SIM Power Supply and Level Translator VIN: 3V to 6V, VOUT = 1.8V/3V, IQ = 40μA, ISD < 1μA, QFN16 for 1.8V/3V SIM Cards LTC4556 Smart Card Interface with Serial Control VIN: 2.7V to 5.5V, VOUT = 1.8V/3V/5V, IQ = 250μA, ISD < 1μA, 4 × 4 QFN24 LTC4557 Dual SIM/Smart Card Power Supply and Level Translator for 1.8V/3V Cards VIN: 2.7V to 5.5V, VOUT = 1.8V/3V, IQ = 250μA, ISD < 1μA, QFN16 ThinSOT is a trademark of Linear Technology Corporation. 4558fa 12 Linear Technology Corporation LT 0407 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2007