LTC6417
1.6GHz Low Noise High Linearity
Differential Buffer/16-Bit ADC
Driver with Fast Clamp
Description
Features
1.6GHz –3dB Small Signal Bandwidth
n Low Distortion Driving 50Ω Load, 2.4V
P-P Out
–100dBc/–69dBc HD2/HD3 at 140MHz
–80dBc IM3 and 46dBm OIP3 at 140MHz
–100dBc/–66dBc HD2/HD3 at 380MHz
–68dBc IM3 and 39dBm OIP3 at 380MHz
n 1.5nV/√Hz Output Noise
n 4.3pA/√Hz Input Current Noise
n Programmable High Speed, Fast Recovery
Output Clamping
n 4.28V
P-P Maximum Output Swing on a 50Ω
Differential Load
n DC-Coupled Signal Path
n Operates on Single 4.75V to 5.25V Supply
n Power: 615mW on 5V, Can Be Reduced to 370mW,
Shutdown Mode 120mW
n 3mm × 4mm 20-Lead QFN Package
The LTC®6417 is a differential unity gain buffer that can
drive a 50Ω load with extremely low noise and excellent
linearity. It is well suited for driving high speed 14- and
16-bit pipeline ADCs with input signals from DC to beyond
600MHz. Differential input impedance is 18.5kΩ, allowing
1:4 and 1:8 transformers to be used at the input providing
additional system gain in 50Ω systems.
Applications
The LTC6417 features fast, adjustable output voltage clamping to help protect subsequent circuitry. The CLHI pin sets
the maximum swing, while a symmetric minimum swing
is set up internally. LTC6417 VOR pin will signal overrange
when the clamps limit output voltage.
n
n
Differential ADC Driver
CCD Buffer
Cable Driver
50Ω Buffer
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Supply current is typically 123mA and the LTC6417 operates
on supply voltages ranging from 4.75V to 5.25V. Power
consumption can be reduced to 74mA via the PWRADJ
pin. The LTC6417 also has a hardware shutdown feature
which reduces current consumption to 24mA.
The LTC6417 is packaged in a 20-lead 3mm × 4mm QFN
package. Pinout is optimized for placement directly adjacent
to Linear Technology’s high speed 14- and 16-bit ADCs.
Typical Application
LTC6417 Driving LTC2209
16-Bit ADC 32K Point FFT,
fIN = 140MHz, –1dBFS, PGA = 0
LTC6417 Driving an LTC2209 16-Bit ADC at 140MHz IF
3.3V
5V
680pF
T1
WBC4-14LB
4
3
2
50Ω
+
–
6
•
•
0.01µF
1
0
2.2µF
0.1µF
1,6,
11,16
100Ω
100Ω
0.01µF
8
9
C43
27pF
E1
51nH
E3
75nH
C45
18pF
HD2 = –88dBc
HD3 = –94dBc
SFDR = 88dBc
SNR = 75.4dB
SEE FIGURE 1/TABLE 1
1:4 BALUN
fS = 153.6Msps
DEMO BOARD DC1685A
–10
–20
–30
5
V+
PWRADJ
IN+
R36
60.4Ω
2
CLHI
LTC6417
19
C41
12pF
OUT+
OUT –
V
IN–
18
VCM OR
14
SHDN
15
GND
12
1k
3, 7,10,
17, 20, 21
2.2µF
R12
60.4Ω
C44
27pF
E2
51nH
R42
300Ω
E5
51nH
C40
12pF
C10
12pF
10Ω
AIN+
R53
120Ω
R43
300Ω
E3
75nH
–
10Ω
LTC2209
16
AIN
VCM PGA = 0
C46
18pF
AMPLITUDE (dBFS)
n
n
n
With no external biasing or gain setting components and
a flow-through pinout, the LTC6417 is very easy to use. It
can be DC-coupled and has a common mode output offset
of –60mV. The LTC6417 input pins are internally biased to
provide an output common mode voltage that is set by
the voltage on the VCM pin for AC-coupled applications.
–40
–50
–60
–70
–80
–90
–100
–110
CLOCK
(153.6MHz)
6417 TA01a
–120
0
10
20
30 40 50 60
FREQUENCY (MHz)
70
80
6417 TA01b
6417f
1
LTC6417
Absolute Maximum Ratings
Pin Configuration
(Note 1)
GND
OUT–
GND
OUT+
TOP VIEW
Total Supply Voltage (V+ to GND)..............................5.5V
Input Current (CLHI, VCM)..................................... ±10mA
Input Current (IN+, IN–).........................................±30mA
Output Current (OUT+, OUT–).............................. ±100mA
Output Current (VOR)............................................ ±10mA
Operating Temperature Range
(TC) (Note 2)........................................... –40°C to 105°C
Specified Temperature Range
(TC) (Note 3)........................................... –40°C to 105°C
Storage Temperature Range................... –65°C to 150°C
Junction Temperature (TJMAX)............................... 150°C
20 19 18 17
V+
1
16 V+
CLHI
2
15 VCM
GND
3
NC
4
PWRADJ
5
12 SHDN
+
6
11 V+
IN+
13 NC
9 10
GND
8
IN–
7
GND
V
14 VOR
21
GND
UDC PACKAGE
20-LEAD (3mm × 4mm) PLASTIC QFN
TJMAX = 150°C, θJA = 52°C/W, θJC = 6.8°C/W
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC6417CUDC#PBF
LTC6417CUDC#TRPBF
LFVN
20-Lead (3mm × 4mm) Plastic QFN
0°C to 70°C
LTC6417IUDC#PBF
LTC6417IUDC#TRPBF
LFVN
20-Lead (3mm × 4mm) Plastic QFN
–40°C to 105°C (TC)
*Temperature grades are identified by a label on the shipping container.
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
DC
Electrical Characteristics + l denotes the specifications which apply over the full operating
The
+
temperature range, otherwise specifications are at TA = 25°C. V = 5V, GND = 0V, No RLOAD, CLOAD = 6pF. VCM = 1.25V, CLHI = V ,
PWRADJ = V+, SHDN = 0V unless otherwise noted. VINCM is defined as (IN+ + IN–)/2. VOUTCM is defined as (OUT+ + OUT–)/2. VINDIFF is
defined as (IN+ – IN–). VOUTDIFF is defined as (OUT+ – OUT–). See DC test circuit schematic.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
–0.15
–0.2
–0.1
0
0
UNITS
Input/Output Characteristics
GDIFF
Differential Gain
VINDIFF = ±1.2V Differential
l
TCGDIFF
Differential Gain Temperature
Coefficient
VSWINGDIFF
Differential Output Voltage Swing
l
VOUTDIFF, VINDIFF = ±2.3V
l
VSWINGMIN
Output Voltage Swing Low
Single-Ended Measurement of OUT+, OUT–
l
VINDIFF = ±2.3V
VSWINGMAX
Output Voltage Swing High
Single-Ended Measurement of OUT+, OUT–
l
VINDIFF = ±2.3V
4
3.3
0.0002
dB/°C
4.28
VP-P
VP-P
0.19
2.25
2.05
dB
dB
2.33
0.28
0.4
V
V
V
V
6417f
2
LTC6417
DC Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+ = 5V, GND = 0V, No RLOAD, CLOAD = 6pF. VCM = 1.25V, CLHI = V+,
PWRADJ = V+, SHDN = 0V unless otherwise noted. VINCM is defined as (IN+ + IN–)/2. VOUTCM is defined as (OUT+ + OUT–)/2. VINDIFF is
defined as (IN+ – IN–). VOUTDIFF is defined as (OUT+ – OUT–). See DC test circuit schematic.
SYMBOL
PARAMETER
CONDITIONS
IOUT
Output Current Drive (Notes 1, 4)
Single-Ended Measurement of OUT+, OUT–
VOS
Differential Input Offset Voltage
IN+ = IN– = 1.25V, VOS = VOUTDIFF/GDIFF
TCVOS
Differential Input Offset Voltage Drift
VIOCM
Common Mode Offset Voltage, Input
to Output
VOUTCM – VINCM
IVRMIN
Input Voltage Range, IN+, IN–
(Minimum) (Single-Ended)
Defined by Output Voltage Swing Test
l
IVRMAX
Input Voltage Range IN+, IN–
(Maximum) (Single-Ended)
Defined by Output Voltage Swing Test
l
2.4
IB
Input Bias Current, IN+, IN–
IN+ = IN– = 1.25V
–13
–18
2
l
13
18
µA
µA
12
11
18.5
l
25
27.5
kΩ
kΩ
9.25
l
5.8
5
13
15
kΩ
kΩ
63
60
91
l
RINDIFF
Differential Input Resistance
MIN
–0.1
l
–3.2
–4
–120
–140
–60
VINDIFF = ±1.2V
Differential Input Capacitance
Input Common Mode Resistance
IN+ = IN– = 0.65V to 1.85V
CMRR
Common Mode Rejection Ratio
IN+ = IN– = 0.65V to 1.85V,
CMRR = (VOUTDIFF/GDIFF/1.2V)
3.2
4
±100
l
RINCM
MAX
l
UNITS
mA
1
l
CINDIFF
TYP
mV
mV
µV/°C
–10
0
mV
mV
0.1
V
V
1
pF
dB
dB
ROUTDIFF
Differential Output Resistance
eN
Input Noise Voltage Density
f = 100kHz
1.5
3
nV/√Hz
Ω
iN
Input Noise Current Density
f = 100kHz
4.3
pA/√Hz
V/V
V/V
Output Common Mode Voltage Control
GCM
VINCMDEFAULT
VOS (VCM – VINCM)
VOUTCMDEFAULT
VOS (VCM – VOUTCM)
VOUTCMMIN
VOUTCMMAX
VCMDEFAULT
RVCM
VCM Pin Common Mode Gain
Default Input Common Mode Voltage
Offset Voltage, VCM to VINCM
VCM = 0.65V to 1.85V
0.82
0.8
0.92
l
1.15
1.1
1.25
l
1.35
1.4
V
V
–85
–90
15
l
115
135
mV
mV
1.1
1
1.2
l
1.3
1.35
V
V
–50
–45
75
l
200
230
mV
mV
0.29
0.63
0.65
V
V
VINCM. IN+, IN–, VCM Pin Floating
VCM – VINCM, VCM = 1.25V
Default Output Common Mode Voltage Inputs Floating, VCM Pin Floating
Offset Voltage, VCM to VOUTCM
VCM – VOUTCM, VCM = 1.25V
Output Common Mode Voltage Range
(Minimum)
VCM = 0.1V
Output Common Mode Voltage Range
(Maximum)
VCM = 2.4V
l
2
1.85
2.25
l
1.15
1.1
1.25
l
1.35
1.4
V
V
2
1.9
2.7
l
3.4
3.7
kΩ
kΩ
VCM Pin Default Voltage
VCM Pin Input Resistance
CVCM
VCM Pin Input Capacitance
IBVCM
VCM Pin Bias Current
VCM = 0.65V to 1.85V
V
V
1
VCM = 1.25V
l
–15
–27.5
1
pF
15
27.5
µA
µA
6417f
3
LTC6417
DC Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+ = 5V, GND = 0V, No RLOAD, CLOAD = 6pF. VCM = 1.25V, CLHI = V+,
PWRADJ = V+, SHDN = 0V unless otherwise noted. VINCM is defined as (IN+ + IN–)/2. VOUTCM is defined as (OUT+ + OUT–)/2. VINDIFF is
defined as (IN+ – IN–). VOUTDIFF is defined as (OUT+ – OUT–). See DC test circuit schematic.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
2.4
2.35
2.48
l
2.55
2.6
V
V
–60
–85
20
l
80
85
mV
mV
VCLHI = 2.0V, VCM = 1.25V, IN+ = 2.4V,
IN– = 0.1V
–100
–110
10
l
100
110
mV
mV
Low Side Clamp Gain with Respect to
CLHI Pin
VCLHI = 2.0V, VCM = 1.25V, IN+ = 2.4V,
IN– = 0.1V
–1.2
–1.25
–1
l
–0.8
–0.75
V/V
V/V
Low Side Clamp Gain with Respect to
CM Pin
VCLHI = 2.0V, VCM = 1.25V, IN+ = 2.4V,
IN– = 0.1V
1.65
1.5
1.9
l
2.2
2.25
V/V
V/V
CLHI Pin Input Resistance
VCLHI = 1.5V to 2.5V
3.4
3.1
4.8
l
5.7
6
kΩ
kΩ
–12
–12.5
3
l
18
18.5
µA
µA
l
4.75
5.25
V
100
95
123
l
140
145
mA
mA
65
63
72
l
17
15
24
l
DC Clamping Characteristics
VCLHIDEFAULT
Default Output Clamp Voltage, High
VOS (CLHI – VOUTCM) Offset Voltage, CLHI to VOUTCM
VOS (CLLO – VOUT)
GLOHI
GLOCM
RCLHI
IBCLHI
Offset Voltage, CLLO to VOUT
CLHI Pin Bias Current
VCLHI = 2.5V
Power Supply
VS
Supply Voltage Range
IS
Supply Current
PSRR
Power Supply Rejection Ratio
VS = 4.75V to 5.25V
dB
dB
SHDN Pin
ISSHDN
Shutdown Current
VSHDN = 5V
29
35
mA
mA
VSHDNDEFAULT
Default Shutdown Voltage
l
0.1
V
VIL,SHDN
SHDN Input Low Voltage
l
2
V
VIH,SHDN
SHDN Input High Voltage
l
3.5
IIL,SHDN
SHDN Input Low Current
–1.6
–2
0
l
1.6
2
µA
µA
275
250
380
l
450
475
µA
µA
10.5
l
6
5
14
15
kΩ
kΩ
1.5
1.45
1.65
1.8
1.85
V
V
45
40
74
l
105
110
mA
mA
–145
–165
–120
l
–80
–75
µA
µA
210
200
240
l
290
300
µA
µA
IIH,SHDN
SHDN Input High Current
CSHDN
SHDN Pin Input Capacitance
RSHDN
SHDN Pin Input Resistance
SHDN = 0V
SHDN = 5V
V
1
SHDN = 2.5V to 5V
pF
PWRADJ Pin
VPWRADJDEFAULT
Default PWRADJ Voltage
PWRADJ Floating
ISL
Supply Low Current
PWRADJ = 0V
IIL,PWRADJ
IIH,PWRADJ
CPWRADJ
PWRADJ Input Low Current
PWRADJ Input High Current
PWRADJ Pin Input Capacitance
PWRADJ = 0V
PWRADJ = 5V
1
pF
6417f
4
LTC6417
DC Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+ = 5V, GND = 0V, No RLOAD, CLOAD = 6pF. VCM = 1.25V, CLHI = V+,
PWRADJ = V+, SHDN = 0V unless otherwise noted. VINCM is defined as (IN+ + IN–)/2. VOUTCM is defined as (OUT+ + OUT–)/2. VINDIFF is
defined as (IN+ – IN–). VOUTDIFF is defined as (OUT+ – OUT–). See DC test circuit schematic.
SYMBOL
PARAMETER
CONDITIONS
RPWRADJ
PWRADJ Pin Input Resistance
PWRADJ = 2.5V to 5.0V
MIN
TYP
MAX
UNITS
10.5
10
14.5
l
19
20
3.25
3.2
3.35
l
3.55
3.6
V
V
–900
–1150
–770
l
–650
–500
µA
µA
1
1.5
2
µA
µA
kΩ
kΩ
VOR Pin
VOR(HI)
IOR(DEFAULT)
IOR(MAX)
Maximum Voltage on VOR Pin
Default Pull-Down Current on VOR Pin
Maximum Pull-Down Current Both
Clamps are Active
VCL = 5.0V, VCM = 1.25V
VCL = 50V, VCM = 1.25V
VCL = 2.0V, VCM = 1.25V, IN+ = 2.4V,
IN– = 0.1V
l
AC Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+ = 5V unless otherwise noted, GND = 0V, RLOAD = 500Ω,CLOAD = 6pF.
VCM = 1.25V, CLHI = V+, PWRADJ = VCC, SHDN = 0V unless otherwise noted. VINCM is defined as (IN+ + IN–)/2. VOUTCM is defined as
(OUT+ + OUT–)/2. VINDIFF is defined as (IN+ – IN–). VOUTDIFF is defined as (OUT+ – OUT–). See DC test circuit schematic.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Differential AC Characteristics
–3dBBW
–3dB Bandwidth
200mVP-P,OUT Differential
1.6
GHz
0.1dBBW
±0.1dB Bandwidth
200mVP-P,OUT Differential
0.18
GHz
0.5dBBW
±0.5dB Bandwidth
200mVP-P,OUT Differential
0.45
GHz
1/f
1/f Noise Corner
25
kHz
SR
Slew Rate
Differential
10
V/ns
tS1%
1% Settling Time
2VP-P,OUT
0.8
ns
tOFF
Shutdown Time
SHDN = 0V to 5V
40
ns
tON
Enable Time
SHDN = 5V to 0V
15
ns
tPWRADJ,OFF
PWRADJ Off Time
PWRADJ = 5V to 0V
10
ns
tPWRADJ,ON
PWRADJ On Time
PWRADJ = 0V to 5V
5
ns
= 1.25V, IN+ = 1.625V to 1.25V,
tCL,OFF 10%
Clamp Release Time
CLHI = 1.5V, VCM
IN– = 1.25V to 0.875V
1
ns
tCL,ON 10%
Clamp Engage Time
CLHI = 1.5V, VCM = 1.25V, IN+ = 1.25V to 1.625V,
IN– = 1.25V to 0.875V
5
ns
Common Mode AC Characteristics (VCM Pin)
–3dBBW
VCM Pin Small Signal –3dB BW
VCM = 0.1VP-P, Measured Single-Ended at Output
10
MHz
SRCM
Common Mode Slew Rate
Measured Single-Ended at Output
2
V/µs
Overrange AC Characteristics (VOR Pin)
–3dBBW
VOR Pin Small Signal –3dB BW
VOR = 0.1VP-P, CLHI = 2V, IN+ = 2.4V, IN– = 0.1V,
RVOR = 1k, Measured Single-Ended at Output
200
MHz
SRVOR
Overrange Slew Rate
Measured Single-Ended at Output
40
V/µs
1.9VP-P,OUT
2
ns
AC Clamping Characteristics
tOVDR
Overdrive Recovery Time
6417f
5
LTC6417
AC Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+ = 5V unless otherwise noted, GND = 0V, RLOAD = 500Ω,CLOAD = 6pF.
VCM = 1.25V, CLHI = V+, PWRADJ = VCC, SHDN = 0V unless otherwise noted. VINCM is defined as (IN+ + IN–)/2. VOUTCM is defined as
(OUT+ + OUT–)/2. VINDIFF is defined as (IN+ – IN–). VOUTDIFF is defined as (OUT+ – OUT–). See DC test circuit schematic.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
HD3
Third Harmonic Distortion
VOUTDIFF = 2.4VP-P, RL = 50Ω
VOUTDIFF = 2.4VP-P
–89
–93
dBc
dBc
IM3
Third Order Intermodulation Distortion
VOUTDIFF = 2.4VP-P, RL = 50Ω
VOUTDIFF = 2.4VP-P
–100
–110
dBc
dBc
OIP3
Output Third Order Intercept
VOUTDIFF = 2.4VP-P, RL = 50Ω
56
dBm
P1dB
Output 1dB Compression Point
16.1
dBm
AC Linearity
10MHz Signal
70MHz Signal
HD3
Third Harmonic Distortion
VOUTDIFF = 2.4VP-P, RL = 50Ω
VOUTDIFF = 2.4VP-P
–74
–77
dBc
dBc
IM3
Third Order Intermodulation Distortion
VOUTDIFF = 2.4VP-P, RL = 50Ω
VOUTDIFF = 2.4VP-P
–86
–96
dBc
dBc
OIP3
Output Third Order Intercept
VOUTDIFF = 2.4VP-P, RL = 50Ω
48
dBm
P1dB
Output 1dB Compression Point
15.8
dBm
140MHz Signal
HD3
Third Harmonic Distortion
VOUTDIFF = 2.4VP-P, RL = 50Ω
VOUTDIFF = 2.4VP-P
–69
–73
dBc
dBc
IM3
Third Order Intermodulation Distortion
VOUTDIFF = 2.4VP-P, RL = 50Ω
VOUTDIFF = 2.4VP-P
–80
–91
dBc
dBc
OIP3
Output Third Order Intercept
VOUTDIFF = 2.4VP-P, RL = 50Ω
P1dB
Output 1dB Compression Point
46
dBm
15.8
dBm
200MHz Signal
HD3
Third Harmonic Distortion
VOUTDIFF = 2.4VP-P, RL = 50Ω
VOUTDIFF = 2.4VP-P
–68
–71
dBc
dBc
IM3
Third Order Intermodulation Distortion
VOUTDIFF = 2.4VP-P, RL = 50Ω
VOUTDIFF = 2.4VP-P
–78
–87
dBc
dBc
OIP3
Output Third Order Intercept
VOUTDIFF = 2.4VP-P, RL = 50Ω
P1dB
Output 1dB Compression Point
44
dBm
15.8
dBm
240MHz Signal
HD3
Third Harmonic Distortion
VOUTDIFF = 2.4VP-P, RL = 50Ω
VOUTDIFF = 2.4VP-P
–67
–70
dBc
dBc
IM3
Third Order Intermodulation Distortion
VOUTDIFF = 2.4VP-P, RL = 50Ω
VOUTDIFF = 2.4VP-P
–76
–85
dBc
dBc
OIP3
Output Third Order Intercept
VOUTDIFF = 2.4VP-P, RL = 50Ω
P1dB
Output 1dB Compression Point
43
dBm
15.7
dBm
–66
–69
dBc
dBc
300MHz Signal
HD3
Third Harmonic Distortion
VOUTDIFF = 2.4VP-P, RL = 50Ω
VOUTDIFF = 2.4VP-P
6417f
6
LTC6417
AC Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+ = 5V unless otherwise noted, GND = 0V, RLOAD = 500Ω,CLOAD = 6pF.
VCM = 1.25V, CLHI = V+, PWRADJ = VCC, SHDN = 0V unless otherwise noted. VINCM is defined as (IN+ + IN–)/2. VOUTCM is defined as
(OUT+ + OUT–)/2. VINDIFF is defined as (IN+ – IN–). VOUTDIFF is defined as (OUT+ – OUT–). See DC test circuit schematic.
SYMBOL
PARAMETER
CONDITIONS
MIN
IM3
Third Order Intermodulation Distortion
VOUTDIFF = 2.4VP-P, RL = 50Ω
VOUTDIFF = 2.4VP-P
OIP3
Output Third Order Intercept
VOUTDIFF = 2.4VP-P, RL = 50Ω
P1dB
Output 1dB Compression Point
TYP
–73
–79
MAX
UNITS
dBc
dBc
41
dBm
15.6
dBm
380MHz Signal
HD3
Third Harmonic Distortion
VOUTDIFF = 2.4VP-P, RL = 50Ω
VOUTDIFF = 2.4VP-P
–66
–68
dBc
dBc
IM3
Third Order Intermodulation Distortion
VOUTDIFF = 2.4VP-P, RL = 50Ω
VOUTDIFF = 2.4VP-P
–68
–77
dBc
dBc
OIP3
Output Third Order Intercept
VOUTDIFF = 2.4VP-P, RL = 50Ω
P1dB
Output 1dB Compression Point
36
39
dBm
15.3
dBm
VOUTDIFF = 2.4VP-P, RL = 50Ω
VOUTDIFF = 2.4VP-P
–65
–68
dBc
dBc
400MHz Signal
HD3
Third Harmonic Distortion
IM3
Third Order Intermodulation Distortion
VOUTDIFF = 2.4VP-P, RL = 50Ω
–68
dBc
OIP3
Output Third Order Intercept
VOUTDIFF = 2.4VP-P, RL = 50Ω
39
dBm
P1dB
Output 1dB Compression Point
15.3
dBm
500MHz Signal
HD3
Third Harmonic Distortion
VOUTDIFF = 2.4VP-P, RL = 50Ω
VOUTDIFF = 2.4VP-P
–65
–67
dBc
dBc
IM3
Third Order Intermodulation Distortion
VOUTDIFF = 2.4VP-P, RL = 50Ω
–64
dBc
OIP3
Output Third Order Intercept
VOUTDIFF = 2.4VP-P, RL = 50Ω
P1dB
Output 1dB Compression Point
37
dBm
15.0
dBm
600MHz Signal
HD3
Third Harmonic Distortion
VOUTDIFF = 2.4VP-P, RL = 50Ω
–60
dBc
IM3
Third Order Intermodulation Distortion
VOUTDIFF = 2.4VP-P, RL = 50Ω
–58
dBc
OIP3
Output Third Order Intercept
VOUTDIFF = 2.4VP-P, RL = 50Ω
P1dB
Output 1dB Compression Point
34
dBm
14.7
dBm
700MHz Signal
HD3
Third Harmonic Distortion
VOUTDIFF = 2.4VP-P, RL = 50Ω
–55
dBc
IM3
Third Order Intermodulation Distortion
VOUTDIFF = 2.4VP-P, RL = 50Ω
–52
dBc
OIP3
Output Third Order Intercept
VOUTDIFF = 2.4VP-P, RL = 50Ω
P1dB
Output 1dB Compression Point
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC6417C/LTC6417I is guaranteed functional over the case
temperature operating range of –40°C to 105°C. θJC = 6.8°C/W.
31
dBm
14.2
dBm
Note 3: The LTC6417C is guaranteed to meet specified performance from
0°C to 70°C. It is designed, characterized and expected to meet specified
performance from –40°C and 105°C case temperature range but is not
tested or QA sampled at these temperatures. The LT6417I is guaranteed to
meet specified performance from –40°C to 105°C case temperature range.
Note 4: This parameter is pulse tested.
6417f
7
LTC6417
Typical Performance Characteristics
–50
POUT = 11dBm
–90
–40°C
25°C
6417 G01
–50
25°C
–90
–40°C
–100
0
0.5
1
1.5
105°C
25°C
–95
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
VCM (V)
6417 G04
POUT = 11dBm
–50
V+ = 4.75V
V+ = 5.0V
V+ = 5.25V
–70
–80
5
POUT = 11dBm
–60
–70
–80
25°C
105°C
–90
–100
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
VCM (V)
–40°C
–100
HD3 at 140MHz
vs VCM Over Temperature
–40
–50
HD3 (dBc)
25°C
1
1.5
POUT = 11dBm
–40
V+ = 4.75V
V+ = 5.0V
V+ = 5.25V
–60
–70
4.5
5
–50
105°C
–60
85°C
–70
–80
–80
–80
–90
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
VCM (V)
–90
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
VCM (V)
–90
6417 G08
4
POUT = 11dBm
25°C
–40°C
6417 G07
2 2.5 3 3.5
PWRADJ (V)
HD3 at 140MHz
vs PWRADJ Over Temperature
HD3 (dBc)
POUT = 11dBm
85°C
0.5
6417 G06
HD3 at 140MHz vs VCM Over V+
105°C
0
6417 G05
–50
HD3 (dBc)
4.5
HD3 at 70MHz
vs PWRADJ Over Temperature
–90
–70
4
6417 G03
–40°C
–60
2 2.5 3 3.5
PWRADJ (V)
85°C
–85
–40
85°C
105°C
–80
HD3 at 70MHz vs VCM Over V+
–60
85°C
HD3 (dBc)
HD3 (dBc)
–75
–70
6417 G02
POUT = 11dBm
–65
–80
–100
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
VCM (V)
HD3 at 70MHz
vs VCM Over Temperature
–55
–70
POUT = 11dBm
–60
–90
–100
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
VCM (V)
–45
–50
V+ = 4.75V
V+ = 5.0V
V+ = 5.25V
HD3 (dBc)
85°C
105°C
–80
POUT = 11dBm
–60
HD3 (dBc)
HD3 (dBc)
–60
–70
HD3 at 30MHz
vs PWRADJ Over Temperature
HD3 at 30MHz vs VCM Over V+
HD3 (dBc)
–50
HD3 at 30MHz
vs VCM Over Temperature
–40°C
0
0.5
1
1.5
2 2.5 3 3.5
PWRADJ (V)
4
4.5
5
6417 G09
6417f
8
LTC6417
Typical Performance Characteristics
HD3 at 240MHz
vs VCM Over Temperature
–35
–40
POUT = 11dBm
POUT = 11dBm
–50
105°C
–45
HD3 at 240MHz
vs PWRADJ Over Temperature
HD3 at 240MHz vs VCM Over V+
–40
V+ = 4.75V
V+ = 5.0V
V+ = 5.25V
POUT = 11dBm
–50
105°C
85°C
–65
–70
–60
–40°C
–75
–80
–80
–85
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
VCM (V)
–90
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
VCM (V)
–90
HD3 at 380MHz
vs VCM Over Temperature
–30
POUT = 11dBm
–35
–65
1
1.5
2 2.5 3 3.5
PWRADJ (V)
4
4.5
25°C
–30
V+ = 4.75V
V+ = 5.0V
V+ = 5.25V
–50
–60
5
HD3 at 380MHz
vs PWRADJ Over Temperature
POUT = 11dBm
–40
HD3 (dBc)
85°C
HD3 (dBc)
–55
POUT = 11dBm
–40
105°C
0.5
6417 G12
HD3 at 380MHz vs VCM Over V+
–45
0
6417 G11
6417 G10
–25
25°C
–70
25°C
–40°C
HD3 (dBc)
–60
HD3 (dBc)
HD3 (dBc)
HD3 (dBc)
85°C
–55
–50
105°C
–60
–70
–70
–80
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
VCM (V)
–80
85°C
25°C
–40°C
–40°C
–75
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
VCM (V)
6417 G13
0.5
1
1.5
2 2.5 3 3.5
PWRADJ (V)
4
–30
POUT = 11dBm
–40
5
HD3 at 500MHz
vs PWRADJ Over Temperature
HD3 at 500MHz vs VCM Over V+
POUT = 11dBm
4.5
6417 G15
6417 G14
HD3 at 500MHz
vs VCM Over Temperature
–30
0
–30
V+ = 4.75V
V+ = 5.0V
V+ = 5.25V
POUT = 11dBm
–40
–40
105°C
–60
–70
25°C
–50
HD3 (dBc)
HD3 (dBc)
HD3 (dBc)
85°C
–50
–60
–50
105°C
–60
–70
–70
–80
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
VCM (V)
–80
85°C
25°C
–40°C
–40°C
–80
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
VCM (V)
6417 G16
6417 G17
0
0.5
1
1.5
2 2.5 3 3.5
PWRADJ (V)
4
4.5
5
6417 G18
6417f
9
LTC6417
Typical Performance Characteristics
–30
POUT = 11dBm
POUT = 11dBm
–40
105°C
HD3 (dBc)
HD3 (dBc)
–40
–50
85°C
–60
25°C
–70
HD3 at 600MHz
vs PWRADJ Over Temperature
HD3 at 600MHz vs VCM Over V+
–30
V+ = 4.75V
V+ = 5.0V
V+ = 5.25V
–50
–60
–50
105°C
–60
85°C
25°C
–70
–70
–40°C
POUT = 11dBm
–40
HD3 (dBc)
–30
HD3 at 600MHz
vs VCM Over Temperature
–40°C
–80
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
VCM (V)
6417 G19
HD3 at 700MHz
vs VCM Over Temperature
25°C
–60
–40°C
–30
V+ = 4.75V
V+ = 5.0V
V+ = 5.25V
–50
4
4.5
–60
5
POUT = 11dBm
–50
105°C
85°C
–60
–70
–70
–80
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
VCM (V)
–80
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
VCM (V)
–80
25°C
105°C
35
POUT = 5dBm/TONE
∆FREQ = 1MHz
25
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
VCM (V)
6417 G25
OIP3 (dBm)
45
40
1
1.5
2 2.5 3 3.5
PWRADJ (V)
4
4.5
5
OIP3 at 30MHz
vs PWRADJ Over Temperature
55
55
50
50
45
45
25°C
–40°C
0.5
6417 G24
OIP3 at 30MHz vs VCM Over V+
55
85°C
0
6417 G23
OIP3 at 30MHz
vs VCM Over Temperature
30
2 2.5 3 3.5
PWRADJ (V)
–40
–70
50
1.5
–40°C
6417 G22
OIP3 (dBm)
POUT = 11dBm
HD3 (dBc)
105°C
1
HD3 at 700MHz
vs PWRADJ Over Temperature
HD3 at 700MHz vs VCM Over V+
–40
85°C
–50
0.5
6417 G21
OIP3 (dBm)
HD3 (dBc)
–30
POUT = 11dBm
–40
0
6417 G20
HD3 (dBc)
–30
–80
–80
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
VCM (V)
40
POUT = 5dBm/TONE
∆FREQ = 1MHz
35
30
V+ = 4.75V
V+ = 5.0V
V+ = 5.25V
30
6417 G26
85°C
105°C
40
35
25
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
VCM (V)
25°C
–40°C
25
POUT = 5dBm/TONE
∆FREQ = 1MHz
0
0.5
1
1.5
2 2.5 3 3.5
PWRADJ (V)
4
4.5
5
6417 G27
6417f
10
LTC6417
Typical Performance Characteristics
–40°C
25°C
45
OIP3 (dBm)
50
85°C
30
55
POUT = 5dBm/TONE
∆FREQ = 1MHz
–40°C
50
45
40
35
OIP3 at 70MHz
vs PWRADJ Over Temperature
OIP3 at 70MHz vs VCM Over V+
105°C
45
OIP3 (dBm)
50
55
OIP3 (dBm)
55
OIP3 at 70MHz
vs VCM Over Temperature
40
35
30
POUT = 5dBm/TONE
∆FREQ = 1MHz
25
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
VCM (V)
105°C
V+ = 4.75V
V+ = 5.0V
V+ = 5.25V
30
25
POUT = 5dBm/TONE
∆FREQ = 1MHz
0
0.5
1
1.5
2 2.5 3 3.5
PWRADJ (V)
4
6417 G29
OIP3 at 100MHz
vs VCM Over Temperature
55
55
–40°C
50
85°C
40
35
25
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
VCM (V)
6417 G28
25°C
50
4.5
5
6417 G30
OIP3 at 100MHz
vs PWRADJ Over Temperature
OIP3 at 100MHz vs VCM Over V+
55
POUT = 5dBm/TONE
∆FREQ = 1MHz
–40°C
50
25°C
105°C
35
35
85°C
30
POUT = 5dBm/TONE
∆FREQ = 1MHz
OIP3 at 140MHz
vs VCM Over Temperature
55
30
25
POUT = 5dBm/TONE
∆FREQ = 1MHz
0
0.5
50
OIP3 (dBm)
40
85°C
1
1.5
2 2.5 3 3.5
PWRADJ (V)
4
4.5
5
6417 G33
OIP3 at 140MHz
vs PWRADJ Over Temperature
55
POUT = 5dBm/TONE
∆FREQ = 1MHz
50
105°C
45
45
35
105°C
–40°C
45
OIP3 (dBm)
V+ = 4.75V
V+ = 5.0V
V+ = 5.25V
OIP3 at 140MHz vs VCM Over V+
POUT = 5dBm/TONE
∆FREQ = 1MHz
25°C
85°C
40
6417 G32
6417 G31
50
25°C
35
25
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
VCM (V)
25
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
VCM (V)
55
40
OIP3 (dBc)
30
OIP3 (dBm)
OIP3 (dBm)
40
45
OIP3 (dBc)
45
45
40
85°C
25°C
40
–40°C
35
35
105°C
V+ = 4.75V
V+ = 5.0V
V+ = 5.25V
30
30
25
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
VCM (V)
25
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
VCM (V)
6417 G34
6417 G35
30
25
POUT = 5dBm/TONE
∆FREQ = 1MHz
0
0.5
1
1.5
2 2.5 3 3.5
PWRADJ (V)
4
4.5
5
6417 G36
6417f
11
LTC6417
Typical Performance Characteristics
55
25°C
45
50
–40°C
105°C
30
40
55
POUT = 5dBm/TONE
∆FREQ = 1MHz
50
–40°C
25
85°C
30
0
V+ = 4.75V
V+ = 5.0V
V+ = 5.25V
55
POUT = 5dBm/TONE
∆FREQ = 1MHz
40
30
20
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
VCM (V)
25
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
VCM (V)
25
45
–40°C
50
POUT = 5dBm/TONE
∆FREQ = 1MHz
25
20
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
VCM (V)
6417 G43
1.5
2 2.5 3 3.5
PWRADJ (V)
4
4.5
OIP3 (dBc)
25°C
35
105°C
30
V+ = 4.75V
V+ = 5.0V
V+ = 5.25V
20
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
VCM (V)
6417 G44
5
–40°C
40
30
105°C
1
POUT = 5dBm/TONE
∆FREQ = 1MHz
45
35
85°C
25
0.5
OIP3 at 500MHz
vs PWRADJ Over Temperature
40
OIP3 (dBm)
OIP3 (dBm)
50
30
0
6417 G42
OIP3 at 500MHz vs VCM Over V+
POUT = 5dBm/TONE
∆FREQ = 1MHz
5
85°C
105°C
6417 G41
OIP3 at 500MHz
vs VCM Over Temperature
35
4.5
25°C
40
30
25°C
4
–40°C
25
6417 G40
2 2.5 3 3.5
PWRADJ (V)
45
35
40
1.5
POUT = 5dBm/TONE
∆FREQ = 1MHz
50
35
45
1
OIP3 at 380MHz
vs PWRADJ Over Temperature
105°C
50
0.5
6417 G39
45
OIP3 (dBm)
40
OIP3 (dBm)
30
OIP3 at 380MHz vs VCM Over V+
35
85°C
105°C
6417 G38
OIP3 at 380MHz
vs VCM Over Temperature
25°C
V+ = 4.75V
V+ = 5.0V
V+ = 5.25V
25
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
VCM (V)
6417 G37
45
25°C
40
35
30
20
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
VCM (V)
–40°C
45
35
POUT = 5dBm/TONE
∆FREQ = 1MHz
POUT = 5dBm/TONE
∆FREQ = 1MHz
50
OIP3 (dBc)
OIP3 (dBm)
OIP3 (dBm)
85°C
35
50
55
POUT = 5dBm/TONE
∆FREQ = 1MHz
45
40
25
OIP3 at 240MHz
vs PWRADJ Over Temperature
OIP3 at 240MHz vs VCM Over V+
OIP3 (dBc)
50
OIP3 at 240MHz
vs VCM Over Temperature
85°C
25
20
0
0.5
1
1.5
2 2.5 3 3.5
PWRADJ (V)
4
4.5
5
6417 G45
6417f
12
LTC6417
Typical Performance Characteristics
–40°C
35
30
85°C
25
20
30
15
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
VCM (V)
OIP3 (dBm)
45
POUT = 5dBm/TONE
∆FREQ = 1MHz
35
15
85°C
0
0.5
45
POUT = 5dBm/TONE
∆FREQ = 1MHz
30
20
15
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
VCM (V)
15
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
VCM (V)
15
10
100
130
120
120
SUPPLY CURRENT (mA)
P1 dB COMPRESSION (dBm)
SUPPLY CURRENT (mA)
300
400
500
FREQUENCY (MHz)
600
700
6417 G52
0.5
1
1.5
2 2.5 3 3.5
PWRADJ (V)
4
100
80
60
40
0
4.5
5
Supply Current vs PWRADJ
140
110
100
90
80
20
200
0
6417 G51
Supply Current vs Supply Voltage
V+ = 5.25V
V+ = 5.0V
V+ = 4.75V
12
85°C
105°C
6417 G50
Output 1dB Compression
vs Frequency and Supply Voltage
5
30
20
6417 G49
4.5
–40°C
20
14
4
25°C
35
25
16
2 2.5 3 3.5
PWRADJ (V)
POUT = 5dBm/TONE
∆FREQ = 1MHz
40
25
18
1.5
OIP3 at 700MHz
vs PWRADJ Over Temperature
105°C
20
1
6417 G48
35
30
25
V+ = 4.75V
V+ = 5.0V
V+ = 5.25V
40
25°C
–40°C
85°C
20
OIP3 at 700MHz vs VCM Over V+
OIP3 (dBm)
40
105°C
6417 G47
OIP3 at 700MHz
vs VCM Over Temperature
45
V+ = 4.75V
V+ = 5.0V
V+ = 5.25V
15
0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65
VCM (V)
6417 G46
30
25
20
POUT = 5dBm/TONE
∆FREQ = 1MHz
25°C
–40°C
35
25
105°C
POUT = 5dBm/TONE
∆FREQ = 1MHz
40
OIP3 (dBc)
OIP3 (dBm)
35
45
POUT = 5dBm/TONE
∆FREQ = 1MHz
40
25°C
OIP3 at 600MHz
vs PWRADJ Over Temperature
OIP3 at 600MHz vs VCM Over V+
OIP3 (dBc)
40
45
OIP3 (dBm)
45
OIP3 at 600MHz
vs VCM Over Temperature
0
1
2
3
4
SUPPLY VOLTAGE (V)
5
6417 G53
70
0
0.5
1
1.5
2 2.5 3 3.5
PWRADJ (V)
4
4.5
5
6417 G54
6417f
13
LTC6417
Typical Performance Characteristics
Small Signal Transient Response,
Falling Edge with Input
Small Signal Transient Response,
Falling Edge
62.5mV/
DIV
Small Signal Transient Response,
Rising Edge
62.5mV/
DIV
20mV/
DIV
62.5mV/
DIV
6417 G55
1.25ns/DIV
Differential Input Return Loss
(S11) vs Frequency
Overdrive Recovery and
Overrange Response
0
–60
R = 0Ω
R = 23.7Ω
DEMO BOARD DC1660B
–80
R = 0Ω
S12 (dB)
S11 (dB)
Differential Reverse Isolation
(S12) vs Frequency
DEMO BOARD DC1660B
–10
600mV/
DIV
6417 G57
1.25ns/DIV
6417 G56
1.25ns/DIV
–20
R = 23.7Ω
–100
–30
10mV/
DIV
–40
6417 G58
10ns/DIV
10
100
FREQUENCY (MHz)
1000
–120
10
100
FREQUENCY (MHz)
6417 G60
6417 G59
Differential Forward Gain (S21)
vs Frequency
10
Differential Output Return Loss
(S22) vs Frequency
0
0
DEMO BOARD DC1660B
R = 0Ω
LTC6417 Driving LTC2209
16-Bit ADC, 32K Point FFT,
fIN = 69.5MHz, –1dBFS, PGA = 0
–30
S22 (dB)
S21 (dB)
R = 0Ω
0
AMPLITUDE (dBFS)
–10
R = 23.7Ω
–20
R = 23.7Ω
–5
–40
–50
–60
–70
3
–80
–90
–30
2
–100
–10
10
100
FREQUENCY (MHz)
1000
6417 G61
–40
DEMO BOARD DC1660B
10
100
FREQUENCY (MHz)
1000
6417 G62
1
HDR = –92dBc
HD3 = –86dBc
SFDR = 86dBc
SNR = 76.2dB
SEE FIGURE 1/TABLE 1
1:4 BALUN
fS = 153.6Msps
DEMO BOARD DC1685A
–10
–20
5
1000
–110
–120
0
10
20
30 40 50 60
FREQUENCY (MHz)
70
80
6417 G63
6417f
14
LTC6417
Typical Performance Characteristics
–20
–30
AMPLITUDE (dBFS)
0
HD2 = –88dBc
HD3 = –94dBc
SFDR = 88dBc
SNR = 75.4dB
SEE FIGURE 1/TABLE 1
1:4 BALUN
fS = 153.6Msps
DEMO BOARD DC1685A
–40
–50
–60
–20
–30
–70
–80
2
–90
HD2 = –81dBc
HD3 = –80dBc
SFDR = 80dBc
SNR = 73.3dB
SEE FIGURE 1/
TABLE 1
1:4 BALUN
fS = 153.6Msps
DEMO BOARD
DC1685A
–10
–40
–50
–60
–70
–80
–30
2
–40
–50
–60
–90
–110
–110
–120
–120
30 40 50 60
FREQUENCY (MHz)
70
80
0
10
20
6417 G64
0
–40
–20
–30
–50
–60
–70
–80
0
–40
–20
–30
–50
–60
–70
–80
–40
–50
–90
–110
–110
–110
–120
–120
80
0
10
6417 G67
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
10
20
30 40 50 60
FREQUENCY (MHz)
70
80
6417 G70
0
10
20
30 40 50 60
FREQUENCY (MHz)
Input Referred Noise Voltage
vs Frequency and Noise Figure for
the DC1660B with 1:4 Input Balun
20
28
NOISE FIGURE PWRADJ = 5V
NOISE FIGURE PWRADJ = 0V
NOISE DENSITY PWRADJ = 5V 24
NOISE DENSITY PWRADJ = 0V
20
16
16
12
12
8
8
4
4
24
0
0.001
0.01
0.1
1
10
FREQUENCY (MHz)
100
1k
6417 G71
80
6417 G69
Input Referred Noise Voltage
vs Frequency and Noise Figure for
the DC1660B with 1:1 Input Balun
28
70
0
24
NOISE FIGURE PWRADJ = 5V
NOISE FIGURE PWRADJ = 0V
NOISE DENSITY PWRADJ = 5V 20
NOISE DENSITY PWRADJ = 0V
24
20
16
16
12
12
8
8
4
4
0
0.001
0.01
0.1
1
10
FREQUENCY (MHz)
100
1k
NOISE FIGURE (dB)
AMPLITUDE (dBFS)
–30
INPUT REFERRED NOISE VOLTAGE (nV/√Hz)
–20
–120
80
NOISE FIGURE (dB)
IM3 = –72dBc
SEE FIGURE 1/TABLE 1
1:4 BALUN
fS = 153.6Msps
DEMO BOARD DC1685A
70
INPUT REFERRED NOISE VOLTAGE (nV/√Hz)
0
30 40 50 60
FREQUENCY (MHz)
6417 G68
LTC6417 Driving LTC2209 16-Bit ADC,
64K Point FFT, fIN = 379.5MHz and
380.5MHz, –7dBFS/Tone, PGA = 0
–10
20
80
–80
–100
70
70
–70
–100
30 40 50 60
FREQUENCY (MHz)
30 40 50 60
FREQUENCY (MHz)
–60
–100
20
20
IM3 = –75dBc
SEE FIGURE 1/
TABLE 1
1:4 BALUN
fS = 153.6Msps
DEMO BOARD
DC1685A
–10
–90
10
10
LTC6417 Driving LTC2209 16-Bit ADC,
64K Point FFT, fIN = 269.5MHz and
270.5MHz, –7dBFS/Tone, PGA = 0
–90
0
0
6417 G66
IM3 = –80dBc
SEE FIGURE 1/TABLE 1
1:4 BALUN
fS = 153.6Msps
DEMO BOARD DC1685A
–10
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
–30
–120
80
LTC6417 Driving LTC2209 16-Bit ADC,
64K Point FFT, fIN = 139.5MHz and
140MHz, –7dBFS/Tone, PGA = 0
0
IM3 = –85dBc
SEE FIGURE 1/TABLE 1
1:4 BALUN
fS = 153.6Msps
DEMO BOARD DC1685A
–20
70
6417 G65
LTC6417 Driving LTC2209 16-Bit ADC,
32K Point FFT, fIN = 69.5MHz and
70.5MHz, –7dBFS/Tone, PGA = 0
–10
30 40 50 60
FREQUENCY (MHz)
AMPLITUDE (dBFS)
20
3
–80
–110
10
2
–70
–100
0
1
HD2 = –65dBc
HD3 = –74dBc
SFDR = 65dBc
SNR = 71.0dB
SEE FIGURE 1/TABLE 1
1:4 BALUN
fS = 153.6Msps
DEMO BOARD DC1685A
–20
–100
–100
LTC6417 Driving LTC2209
16-Bit ADC, 64K Point FFT,
fIN = 380MHz, –1dBFS, PGA = 0
–10
3
–90
3
0
1
AMPLITUDE (dBFS)
1
–10
AMPLITUDE (dBFS)
0
LTC6417 Driving LTC2209
16-Bit ADC, 64K Point FFT,
fIN = 270MHz, –1dBFS, PGA = 0
LTC6417 Driving LTC2209
16-Bit ADC, 64K Point FFT,
fIN = 140MHz, –1dBFS, PGA = 0
0
6417 G72
6417f
15
LTC6417
Pin Functions
V+ (Pins 1, 6, 11, 16): Positive Power Supply. Typically 5V.
Split supplies are possible as long as the voltage between
V+ and GND is 4.75V to 5.25V. Bypass capacitors of 680pF
and 0.1µF as close to the part as possible should be used
between the supplies.
CLHI (Pin 2): High Side Clamp Voltage. The voltage applied to the CLHI pin defines the upper voltage limit of
the OUT+ and OUT– pins. This voltage should be set at
least 300mV above the upper voltage range of the ADC.
On a 5V supply, the CLHI pin will float to a 2.5V default
voltage. CLHI has a Thevenin equivalent of approximately
4.8kΩ and can be overdriven by an external voltage. The
CLHI pin should be bypassed with a high quality ceramic
bypass capacitor of at least 0.01µF.
GND (Pins 3, 7, 10, 17, 20, Exposed Pad Pin 21): Negative Power Supply. Normally tied to ground. All pins and
the exposed pad must be tied to the same voltage. GND
may be tied to a voltage other than ground as long as the
voltage between V+ and GND is 4.75V to 5.25V. If the GND
pins are not tied to ground, bypass each with 680pF and
0.1µF capacitors as close to the package as possible. The
exposed pad must be soldered to the printed circuit board
ground plane for good heat transfer.
NC (Pins 4, 13): No Connection. These pins are not connected internally.
PWRADJ (Pin 5): Power Adjust Voltage. The voltage
applied to this pin scales the bias current internal to the
LTC6417. The PWRADJ pin will float to a 1.6V default
voltage. PWRADJ has a Thevenin equivalent resistance of
approximately 14.5k and can be overdriven by an external
voltage. The PWRADJ pin should be bypassed with a high
quality ceramic bypass capacitor of at least 0.01µF.
IN+, IN– (Pin 8, Pin 9): Non-inverting and inverting input
pins of the buffer, respectively. These pins are high impedance, approximately 9.5k. If AC-coupled, these pins will
self bias to the voltage applied to the VCM pin.
SHDN (Pin 12): This pin puts the LTC6417 in sleep mode
when pulled high. If no voltage is applied to the SHDN pin,
it floats down to the same potential as GND.
VOR (Pin 14): Overrange Output. This pin, by default at
3.4V, will be pulled down to GND, when one or both input
signals go beyond the minimum or maximum swing set
by the CLHI and VCM pins.
VCM (Pin 15): This pin sets the output common mode voltage seen at OUT+ and OUT– by driving IN+ and IN– through
a buffer with a high output resistance of 9.5k. The VCM
pin has a Thevenin equivalent resistance of approximately
2.7k and can be overdriven by an external voltage. If no
voltage is applied to VCM, it will float to a default voltage of
approximately 1.25V on a 5V supply. The VCM pin should
be bypassed with a high quality ceramic bypass capacitor
of at least 0.01µF.
OUT–, OUT+ (Pin 18, Pin 19): Outputs.
6417f
16
LTC6417
DC Test Circuit Schematic
V+
1, 6, 11, 16
V+
15
VCM
VCM
2
19
CLHI
CLHI
+
–
VINDIFF = IN – IN
8
OUT+
+
+
IN LTC6417
+
– IN
9
VINCM = IN + IN
–
IN–
IN–
OUT
2
5
18
PWRADJ
PWRADJ VOR
14
SHDN
VOR
12
–
OUT
CLOAD
RLOAD
6417 TC
OUT+
VOUTDIFF = OUT+ – OUT–
+
–
VOUTCM = OUT + OUT
2
3, 7, 10, 17, 20, 21
Block Diagram
LTC6417 Simplified Schematic
V+
I1
IN
QN3
QP1
×1
–
×2
OVER
RANGE
DETECT
QN1
QP3
+
CLHI
I2
VOR
OUT+
CLLO
+
VCM
×1
QN2
QP4
IN–
QN4
QP2
OUT–
PWRADJ
SHDN
GND
REFERENCE AND
BIAS CONTROL
I3
I4
6417 BD
6417f
17
LTC6417
Applications Information
Circuit Operation
Input Impedance and Matching
The LTC6417 is a low noise and low distortion fully differential unity gain ADC driver with a –3dB bandwidth
spanning DC to 1.6GHz, a differential input impedance of
18.5kΩ, and a differential output impedance of 3Ω. The
LTC6417 is composed of a fully differential buffer with
output common mode voltage control circuitry and high
speed voltage-limiting clamps at the output. Lowpass or
bandpass filters are easily implemented with just a few
external components. The LTC6417 is very flexible in
terms of I/O coupling. It can be AC- or DC-coupled at the
inputs, the outputs or both. When using the LTC6417 with
DC-coupled inputs, best performance is obtained with an
input common mode voltage between 1V and 1.5V. For
AC-coupled operation, the LTC6417 will take the voltage
applied to the VCM pin and use it to bias the inputs so
that the output common mode voltage equals VCM, thus
no external circuitry is needed. The VCM pin has been
designed to directly interface with the VCM pin found on
Linear Technology’s high speed ADC families.
The LTC6417 has a high differential input impedance of
18.5kΩ. The differential inputs may need to be terminated
to a lower value impedance, e.g. 50Ω, in order to provide
an impedance match for the source. Figure 1 shows input
matching and single-ended to differential conversion using
a 1:1 balun, while Figure 2 shows a similar circuit using
a 1:4 balun to achieve an additional 6dB of voltage gain.
These circuits provide a wideband impedance match.
The balun and matching resistors must be placed close
to the input pins in order to minimize the rejection due to
input mismatch. In Figures 1 and 2, the capacitor centertapping the two input termination resistors improves high
frequency common mode rejection. As an alternative to
this wideband approach, a narrowband impedance match
can be used at the inputs of the LTC6417 for frequency
selection and/or noise reduction.
T1
0.1µF
MABA-007159-000000
VIN
+
–
0.1µF
4
•
1:1
•
5
50Ω
IN+
19
OUT+
24.9Ω 0.1µF
1
3
8
LTC6417
0.1µF
24.9Ω
9
IN–
18
OUT–
6417 F01
Figure 1. Input Termination for Differential 50Ω Input Impedance Using a 1:1 Balun
4
50Ω
VIN
+
–
T1
TCM4-19+
3
0.1µF
1
OUT+
19
LTC6417
0.1µF
6
IN+
100Ω 0.1µF
2
0.1µF
8
100Ω
9
IN–
OUT–
18
6417 F02
Figure 2. Input Termination for Differential 50Ω Input Impedance Using a 1:4 Balun
6417f
18
LTC6417
Applications Information
The noise figure of the LTC6417 application circuit also
depends upon the input termination. For example, the
input 1:4 balun in Figure 2 improves noise figure by adding 6dB of voltage gain at the inputs. A trade-off between
gain and noise is obvious when constant noise figure circle
and constant gain circle are plotted within the same input
Smith Chart. This technique can be used to determine
the optimal source impedance for a given gain and noise
requirement.
Output Match and Filter
The LTC6417 provides an output resistance of 1.5Ω at
each output. In most cases, the LTC6417 can be used
to drive an ADC without back termination but for testing
purposes, Figure 3 shows the LTC6417 driving a differential 50Ω load impedance using a 1:1 balun. If output
8
IN+
OUT+
18
0Ω
0.1µF
matching for the 1:1 balun is desired, resistors of 23.7Ω
should be inserted in series with each LTC6417 output.
This is shown in Figure 4 where the LTC6417 is driving a
differential 100Ω load impedance.
As mentioned above, the LTC6417 can drive an ADC without external output impedance matching, but improved
performance can usually be obtained with the addition of
a few components. Figure 5 shows a 6th order bandpass
filter with a 148MHz center frequency, –3dB points of
85MHz and 210MHz used for driving the LTC2209 16-bit
ADC. In the passband the filter has less than 1 dB ripple.
This higher order filter has a sharp roll-off outside its
passband, therefore it rejects noise and suppresses distortion components in its stopband. To double the filter
center frequency, halve the capacitor and inductor values,
and maintain resistor values; this also doubles the filter
bandwidth.
T2
MABA-007159-000000
50Ω
LTC6417
IN–
OUT–
19
0Ω
•
•
9
0.1µF
6417 F03
Figure 3. LTC6417 with No Back Termination Driving a
50Ω Load Using a 1:1 Balun
8
IN+
19
OUT+
23.7Ω
0.1µF
T2
MABA-007159-000000
3
4
LTC6417
IN–
18
OUT–
23.7Ω
0.1µF
1
•
•
9
50Ω
5
6417 F04
Figure 4. Output Termination for Differential 50Ω Load
Using a 1:1 Balun
6417f
19
LTC6417
Applications Information
3.3V
5V
680pF
0.1µF
C43
27pF
2.2µF
1,6,
11,16
T1
WBC4-14LB
4
3
2
50Ω
+
–
6
•
0.01µF
•
1
100Ω
100Ω
0.01µF
8
5
V+
PWRADJ
IN+
LTC6417
19
OUT+
OUT –
V
IN–
18
VCM OR
14
SHDN
15
GND
12
1k
3,7,10,
17, 20,21
9
E3
75nH
R36
60.4Ω
2
CLHI
E1
51nH
R42
300Ω
0Ω
R12
60.4Ω
0Ω
C44
27pF
C45
18pF
C41
12pF
E5
51nH
10Ω
C40
12pF
R53
120Ω
C10
12pF
E2
51nH
R43
300Ω
E3
75nH
10Ω
AIN+
AIN–
LTC2209
VCM
C46
18pF
16
PGA = 0
CLOCK
(153.6MHz)
6417 F05
2.2µF
Figure 5. DC1685A Simplified Schematic with Suggested Bandpass Filter for Driving an LTC2209 16-Bit ADC at 140MHz
Table 1. Bandpass Filter Component Values for Different Input Frequencies
INPUT FREQUENCIES
COMPONENTS
70MHz
140MHz
270MHz
380MHz
R12 = R36
60.4Ω
60.4Ω
60.4Ω
60.4Ω
C43 = C44
56pF
27pF
15pF
12pF
E1 = E2
100nH
51nH
27nH
18nH
C41
47pF
12pF
12pF
10pF
C10 = C40
13pF
12pF
3.3pF
2.7pF
E5
100nH
51nH
27nH
18nH
R42 = R43
300Ω
300Ω
300Ω
300Ω
R53
120Ω
120Ω
120Ω
120Ω
C45 = C46
39pF
18pF
10pF
8.2pF
E3 = E4
150nH
75nH
39nH
27nH
6417f
20
LTC6417
Applications Information
Output Common Mode Adjustment
For AC-coupled applications, the output common mode
voltage is set by the VCM pin. An internal buffer, as shown
in Figure 6, couples the voltage on the VCM pin to the
inputs via high impedance resistors. Because the input
common mode voltage is approximately the same as the
output common mode voltage, both are approximately
equal to the voltage applied to the VCM pin. For DC-coupled
applications, the internal VCM is overdriven by the input
signal. The VCM pin has a Thevenin equivalent resistance
of 2.7k and can be overdriven by an external voltage. The
VCM pin floats to a default voltage of 1.25V on a 5V supply.
The output common mode voltage is capable of tracking
VCM in a range from 0.29V to 2.25V on a 5.0V supply. The
VCM pin can be floated, but it should always be bypassed
close to the LTC6417 with a 0.1µF bypass capacitor to
GND. When interfacing with A/D converters such as the
LTC22xx families, the VCM pin can be connected to the
VCM output pin of the ADC, as shown in Figure 5.
Clamping, the CLHI Pin and the VCM Pin
The CLHI pin is used to set the high side clamp voltage
of the high speed internal circuitry.
This limits the single-ended maximum and minimum
voltage excursion at each of the outputs. This feature is
extremely important in applications with input signals
having very large peak-to-average ratios such as cellular
base station receivers.
Internal circuitry generates a symmetric low side clamp
voltage with respect to the common mode voltage VCM
(Figures 7 and 8). The LTC6417 clamp control circuitry
features two additional mechanisms. First, internally imposed maximum swing of 2.5V and minimum swing of 0.2V
ensure that the transistors do not go into deep saturation.
This ensures a quick recovery after the clamps are released.
Second, if CLHI voltage is less than VCM, internal CLLO
starts to track CLHI. This limits output swing and protects
output transistors. Since the clamp response is on the
order of 5ns to clamp and 1ns to release, clamp circuit
becomes less effective at frequencies beyond 160MHz.
LTC6417
V+
IN+
1.5Ω
OUT+
1.5Ω
OUT–
x1
10.8k
9.25k
VCM
3.6k
x1
9.25k
IN–
x1
GND
6417 F06
Figure 6. LTC6417 Internal Topology Showing
the Common Mode Buffer Biasing the Inputs
LTC6417
V+
9.6k
CLHI
9.6k
x1
–
+
VCM
CLHI (INT)
CLLO (INT)
x2
GND
6417 F07
Figure 7. Internal Circuitry Generating Symmetric
Clamp Voltages with Respect to VCM
CLHI
VCM
6417 F08
CLLO
Figure 8. Symmetric High- and Low-Side Clamp
Voltages with Respect to VCM
6417f
21
LTC6417
Applications Information
If a very large signal arrives at the LTC6417, the voltages
applied to the CLHI and VCM pins will determine the maximum and minimum output swing. Once the input signal
returns to the normal operating range, the LTC6417 returns
to linear operation within 2ns. For DC-coupled operation,
the common mode of the input signals might be different
than the voltage on the VCM pin. The minimum swing will
still be set by the voltages applied to the VCM and CLHI pins.
CLHI is a high impedance input. It has an input impedance
of 4.8k. On a 5V supply, CLHI self-biases to 2.5V. To limit
the signal swing to a subsequent stage’s power supply,
e.g. an ADC such as the LTC2165, simply connect CLHI
to the positive supply pin of the LTC2165. The CLHI pin
should be bypassed with a 0.1µF capacitor as close to the
LTC6417 as possible.
The VOR Pin
The VOR, overrange pin signals an overrange condition
when one or both inputs exceed the minimum or maximum
signal swing limits set by the CLHI and VCM pins.
The LTC6417 VOR pin can be used by a control system to
limit the input power dynamically. This is very useful in
applications where the overload response of the complete
system would be too slow.
The VOR pin, as shown in Figure 9, is internally connected
to a current source sourcing 2mA, plus an internal 20k
resistor pull-down to GND. An internal clamp limits the
maximum output to 3.4V. As soon as one of the inputs
goes beyond the limits, and therefore engages one of the
clamps, the output current, hence, the VOR voltage goes
to zero. The dynamic response of the VOR pin can be adjusted with an external resistor and an optional external
capacitor. For a high speed operation, add a 50Ω resistor
from VOR to GND, resulting in a high speed signal with
100mV swing.
The PWRADJ Pin
The voltage applied to the PWRADJ pin scales the supply
current and performance of the LTC6417. This is useful
for reducing power consumption in applications where
linearity of the LTC6417 exceeds the linearity of the other
components in the system; hence LTC6417’s linearity can
be derated without effecting system performance. PWRADJ
is a high impedance input. It has an input impedance of
14.5k. On a 5V supply, PWRADJ self-biases to 1.6V. For full
power, simply connect PWRADJ to the positive supply V+.
For minimum power, short the PWRADJ pin to GND. The
PWRADJ pin should be bypassed with a 0.1µF capacitor as
close to the LTC6417 as possible. LTC6417 performance
vs PWRADJ can be found in the graphs.
LTC6417
The SHDN Pin
V+
2mA
VOR
ICL
20k
GND
6417 F09
Figure 9. LTC6417 Internal Topology Showing
VOR Pin with Pull-Down Resistor and Clamp
When pulled high, the SHDN pin puts the LTC6417 in sleep
mode, significantly reducing supply current. SHDN is a high
impedance input. It has an input impedance of 10.5kΩ. If
the SHDN pin is not driven with an external voltage, it floats
down to the same potential as GND, keeping the LTC6417
enabled. The SHDN pin should be bypassed with a 0.1µF
capacitor as close to the LTC6417 as possible.
In sleep mode, the input and output stages are turned off,
but the input and output clamps are kept alive to protect
the part against overvoltage.
The supply current in sleep mode is only 24mA, instead
of the typical 125mA. But should the clamps turn on, the
current drawn from the supply can be as high as 180mA.
6417f
22
LTC6417
Applications Information
This can be avoided by following a few precautions when
putting the LTC6417 in sleep mode:
Noise figure (NF) is calculated from the ratio of these
noise powers:
• Do not force the outputs below the inputs, this will turn
the output stages on.
• Either float CLHI or tie it to VCC. This will allow a wider
signal range at the inputs before the clamps are activated.
e2no
NF = 10log 1+ 2
e no(mR )
S
• Maintain the inputs below CLHI or 2.5V whichever is
lower, otherwise the input clamps will be activated.
• Do not short VCM or the outputs to GND, in either case
the output clamps will turn on. Current drawn from the
supply can be as high as 180mA.
1:m
TRANSFORMER
RS
LTC6417
RT
• Float the outputs if possible. The outputs will be pulled
down by internal resistors to VCM.
6417 F10
Heeding these precautions will protect the LTC6417 as
well any part it is driving, while maintaining a low current
consumption in sleep mode.
Figure 10. LTC6417 with a Transformer
Noise and Noise Figure
The LTC6417’s differential input referred voltage and current
noise densities are 1.5nV/√Hz and 4.3pA/√Hz, respectively.
Before presenting a noise model, the circuit with the
transformer in Figure 10 will be simplified. In Figure 11,
the circuit is redrawn with the source impedance reflected
to the secondary side of the transformer. The source
impedance is multiplied by the impedance ratio m of the
transformer. In Figure 12, noise sources associated with
the amplifier and resistors have been added. Based on
this noise model of the LTC6417, the total output noise
power excluding the noise contribution of the source is:
(
+ (i
e no2 = e 2ni + i ni • REQ
= e 2ni
ni
• REQ
)
)
2
mRS
LTC6417
RT
6417 F11
Figure 11. Source Resistance Referred to the Secondary
eni2
mRS
i2mRS
RT
i2RT
eno2
i2ni
LTC6417
+ i 2R T • R2EQ
2
+
4kT 2
• R EQ
RT
6417 F12
Figure 12. LTC6417 Simplified Noise Model
where R EQ = mRS ||RT is the equivalent impedance seen
at the input of the LTC6417. The output noise power due
to the noise of source resistance is given by:
e no(mRS )2 = i 2mRS • R2EQ
=
4kT
• R2EQ
mRS
6417f
23
LTC6417
Applications Information
In most cases the termination resistor will be matched to
the source resistance, e.g. RT = mRS. For the LTC6417 with
a wide-band terminated transformer, a plot of output and
input noise density and NF versus termination resistor is
shown in Figure 13. To get the best noise performance in
the system, use the LTC6417 matched to a transformer with
high impedance ratio. Although the output noise density
will be higher, noise figure will improve because of the
additional gain realized in the transformer. An impedance
ratio greater than 8 is not recommended, as the increased
termination resistance with the LTC6417 input capacitance
will limit signal bandwidth. Consult Table 2 for a quick
estimate of the LTC6417’s output noise density and NF
for different transformer impedance ratios. Measured NF
numbers will be higher as the simple noise model does
not take the insertion loss in the transformer into account.
Table 2. Output Noise Density and NF of the LTC4617 with a
Wide-Band Terminated Transformer, RS = 50Ω
TRANSFORMER TERMINATION
IMPEDANCE
RESISTOR RT
RATIO m
(Ω)
OUTPUT NOISE
DENSITY eno
(nV/√Hz)
NF
(dB)
50
1.0
1.57
11.2
2
100
1.4
1.64
8.9
4
200
2.0
1.80
7.0
8
400
2.8
2.14
5.9
2.1
1.9
10
1.7
9
1.5
8
1.3
7
1.1
6
0.9
5
0.7
50
100 150 200 250 300 350
TERMINATION RESISTANCE (Ω)
The LTC6417 has not been designed to convert singleended signals to differential signals. A single-ended input
signal can be converted to a differential signal via a balun
connected to the inputs of the LTC6417. Figure 5 shows
the LTC6417 driven by a 1:4 transformer which provides
6dB of voltage gain while also performing a single-ended
to differential conversion.
Power Supply Considerations
11
NF (dB)
eno (nV/√Hz)
12
NF
eno
eni
The LTC6417 has been specially designed to interface
directly with high speed A/D converters. It is possible
to drive the ADC directly from the LTC6417. In practice,
however, better performance may be obtained by adding
a few external components at the output of the LTC6417.
Figure 5 shows the LTC6417 driving an LTC2209 16-bit
ADC. The differential outputs of the LTC6417 are bandpass
filtered, then drive the differential inputs of the LTC2209.
In many applications, a filter like this is desirable to limit
the wideband noise of the amplifier. This is especially
true in high performance 16-bit designs. The minimum
recommended network between the LTC6417 and the ADC
is simply two 10Ω series resistors, which are used to help
eliminate resonances associated with the stray capacitance
of PCB traces and the stray inductance of the internal bond
wires at the ADC input pins and the driver output pins.
Single-Ended Signals
GAIN
(V/V)
1
2.3
Interfacing the LTC6417 to A/D Converters
4
400
6417 F13
Figure 13. LTC4617 Output and Input Noise
Density and NF vs Termination Resistance
For best linearity, the LTC6417 should have a positive
supply of V+ = 5V. For ESD protection, the LTC6417 has
an internal edge-triggered supply voltage clamp. The
timing mechanism of the clamp enables the LTC6417’s
protection circuit during ESD events. This internal clamp
can also be activated by voltage overshoot and rapid slew
rate on the positive supply V+ pin. The LTC6417 should not
be hot-plugged into a powered socket because there is a
risk of activating this internal ESD clamp circuit. Bypass
capacitors of 680pF and 0.1µF should be connected to the
V+ pin, as close as possible to the LTC6417.
Interfacing the LTC6417 with Active Mixers for
Ultrawide IF Bandwidth
The LTC6417 is an excellent interface amplifier for use with
active downconverting mixers like the LTC5567. By using
6417f
24
LTC6417
Applications Information
the LTC6417 as a post-amplifier for the LTC5567, it is possible to achieve IF bandwidths in excess of 500MHz, while
adding bandpass filtering. A key to achieving this extremely
wide IF bandwidth is the use of pre-emphasis inductors
in series with the LTC6417 inputs to compensate for the
inherent rolloff caused by the LTC6417 input capacitance
interacting with the interface impedance. In the example
seen in Figure 14, a value of 33nH for each pre-emphasis
inductor gives excellent wideband performance. Figure 15
shows performance for various values of L. For L = 33nH,
overall conversion gain remains within 1dB from 90MHz
to 590MHz, resulting in 500MHz of IF bandwidth.
demonstration circuit for the LTC6417. The board layout
and the schematic are shown in Figures 16 and 17. These
circuits include a 1:4 input balun and a 1:1 output balun
for single-ended-to-differential conversion, allowing direct
analysis using a 2-port network analyzer. Including the input
and output baluns, the –3dB bandwidth is approximately
600MHz. A 1:4 input balun before the LTC6417 inputs
provides 6dB of voltage gain, but results in better noise
figure performance compared to a 1:1 input balun. Noise
figure measurements for both input baluns can be found
in the graphs.
Test circuit B is DC1685A. It consists of an LTC6417 driving
an LTC2209 16-bit 153.6Msps ADC. It is intended for use
in conjunction with DC890B (computer interface board)
and proprietary Linear Technology evaluation software
to evaluate the performance of both parts together. Both
the DC1685A board layout and the schematic can be seen
Figures 18 and 19.
Test Circuits
Due to the fully differential design of the LTC6417 and its
usefulness in applications both with and without ADCs, two
test circuits have been used to generate the information
in this data sheet. Test circuit A is DC1660B, a two-port
LO
1.65GHz
1nF
IF+
LTC5567
249Ω
RF
1.69GHz
TO
2.39GHz
L
390n
VCC
10nF
249Ω
390n
IF–
23.2Ω
127Ω
1nF
1:1
IFOUT
50Ω
LTC6417
127Ω
L
23.2Ω
1nF
1nF
6417 F14
Figure 14
2
L = 33nH
1
L = 18nH
0
GC (dB)
–1
LPF
–2
L = 0nH
–3
–4
–5
–6
–7
40
140
240 340 440 540
IF FREQUENCY (MHz)
640
740
6417 F15
Figure 15
6417f
25
LTC6417
Applications Information
Figure 16. Demo Board DC1660B Layout
6417f
26
A
B
C
D
J2
C24
C23
OPT
0603
TCM4-19+
T1
3
2
1
V+
5
1. ALL RESISTORS AND CAPACITORS ARE 0402
R5
0
C18
680pF
C15
0.1uF
R4
0
C16
680pF
10
9
8
7
GND
IN-
IN+
GND
U1
LTC6417CUDC
CUSTOMER NOTICE
V+
C13
0.1uF
R6
100
R2
100
C4
0.1uF
GND
GND
OUT-
OUT+
GND
4
C21
0.1uF
R8
OPT
2
SCALE = NONE
DATE:
N/A
SIZE
C9
0.1uF
2
C3
0.1uF
5
DATE
09-12-11
C11
0.1uF
0603
E1
J4
J3
GND
VCM
OUT-
OUT+
V+
4.75V - 5.25V
C6
OPT
0603
E3
E2
C20
0.1uF
V+
JOHN C.
DEMO CIRCUIT 1660B
LTC6417CUDC
ADC BUFFER
1
SHEET 1
OF 1
2
REV.
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900 www.linear.com
Fax: (408)434-0507
LTC Confidential-For Customer Use Only
1
Monday, September 12, 2011
IC NO.
V+
C14
0.1uF
2
1
APPROVED
T2
C5 MABA-007159-000000
0.1uF
3
4
C2
680pF
2ND PROTOTYPE
DESCRIPTION
REVISION HISTORY
TECHNOLOGY
REV
2
JOHN C. TITLE: SCHEMATIC
LT
C22
680pF
R3
0
R7
OPT
R1
0
__
ECO
Figure 17. Demo Board DC1660B Schematic (Test Circuit A)
3
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
21
17
18
19
20
APPROVALS
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A
CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;
HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES.
VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL
APP ENG.
APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR
TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
C10
0.1uF
C7
0.1uF
V+
NOTE: UNLESS OTHERWISE SPECIFIED
OR
J5
4
5
C1
0.1uF
C17
0.1uF
C19
0.1uF
C12
0.1uF
0603
C8
OPT
0603
0.1uF
E4
SHUT E7
DOWN
IN-
IN+
J1
PWRADJ
CL HI
11
E5
6
V+
V+
5
12
NC
13
PWRADJ
3
14
OR
4
15
SHUTDOWN
4
NC
3
GND
2
CL HI
VCM
1
V+
V+
16
5
A
B
C
D
LTC6417
Applications Information
6417f
27
LTC6417
Applications Information
Figure 18. Demo Board DC1685A Layout
6417f
28
A
B
C
D
5
4
3
2
1
TECHNOLOGY
1
2
Figure 19. Demo Board DC1685A Schematic (Test Circuit B)
3
4
5
A
B
C
D
LTC6417
Applications Information
6417f
29
A
B
C
D
E
5
4
3
2
1
1
TECHNOLOGY
2
3
Figure 19 (Continued). Demo Board DC1685A Schematic (Test Circuit B)
4
30
5
A
B
C
D
E
LTC6417
Applications Information
6417f
LTC6417
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UDC Package
20-Lead Plastic QFN (3mm × 4mm)
(Reference LTC DWG # 05-08-1742 Rev Ø)
0.70 ±0.05
3.50 ± 0.05
2.10 ± 0.05
1.50 REF
2.65 ± 0.05
1.65 ± 0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
2.50 REF
3.10 ± 0.05
4.50 ± 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
3.00 ± 0.10
0.75 ± 0.05
1.50 REF
19
R = 0.05 TYP
PIN 1 NOTCH
R = 0.20 OR 0.25
× 45° CHAMFER
20
0.40 ± 0.10
1
PIN 1
TOP MARK
(NOTE 6)
4.00 ± 0.10
2
2.65 ± 0.10
2.50 REF
1.65 ± 0.10
(UDC20) QFN 1106 REV Ø
0.200 REF
0.00 – 0.05
R = 0.115
TYP
0.25 ± 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
6417f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
31
LTC6417
Typical Application
DC1685A Simplified Schematic with Suggested Output Termination for Driving an LTC2209 16-Bit ADC at 140MHz
3.3V
5V
680pF
0.1µF
2.2µF
C43
27pF
1,6,
11,16
T1
WBC4-14LB
4
3
2
50Ω
+
–
6
•
0.01µF
•
1
8
100Ω
100Ω
0.01µF
5
V+
PWRADJ
IN+
LTC6417
19
OUT+
OUT –
V
IN
18
VCM OR
14
SHDN
15
GND
12
1k
3,7,10,
17, 20,21
9
E3
75nH
R36
60.4Ω
2
CLHI
E1
51nH
R12
60.4Ω
–
C44
27pF
C45
18pF
R42
300Ω
C41
12pF
E5
51nH
E2
51nH
10Ω
C40
12pF
C10
12pF
R53
120Ω
R43
300Ω
E3
75nH
10Ω
AIN+
AIN–
LTC2209
VCM
C46
18pF
16
PGA = 0
CLOCK
(153.6MHz)
6417 TA02
2.2µF
Related Parts
PART NUMBER
DESCRIPTION
COMMENTS
Fixed Gain IF Amplifiers/ADC Drivers
LTC6400-8/LTC6400-14/ 1.8GHz Low Noise, Low Distortion Differential
LTC6400-20/LTC6400-26 ADC Drivers
LTC6420-20
Dual 1.8GHz Low Noise, Low Distortion Differential
ADC Drivers
LTC6401-8/LTC6401-14/ 1.3GHz Low Noise, Low Distortion Differential
LTC6401-20/LTC6401-26 ADC Drivers
LTC6421-20
Dual 1.3GHz Low Noise, Low Distortion Differential
ADC Drivers
IF Amplifiers/ADC Drivers with Variable Gain
LTC6412
800MHz, 31dB Range Analog-Controlled VGA
LT5554
High Dynamic Range 7-Bit Digitally Controlled IF
VGA/ADC Driver
LT5514
Ultra-Low Distortion IF Amplifier/ADC Driver with
Digitally Controlled Gain
LT5524
Low Distortion IF Amplifier/ADC Driver with
Digitally Controlled Gain
Baseband Differential Amplifiers
LT6416
2GHz Low Noise Differential 16-Bit ADC Buffer
LTC6409
10GHz 1.1nV√Hz ADC Driver
LTC6406
3GHz Rail-to-Rail Input Differential Amplifier/
ADC Driver
LTC6404-1/LTC6404-2/
Low Noise Rail-to-Rail Output Differential
LTC6404-4
Amplifier/ADC Driver
LTC6403-1
Low Noise Rail-to-Rail Output Differential
Amplifier/ADC Driver
ADCs
LTC2209
16-Bit 160Msps ADC
LTC2208
16-Bit 130Msps ADC
–71dBc IM3 at 240MHz 2VP-P Composite, IS = 90mA, AV = 8dB, 14dB,
20dB, 26dB
Dual Version of the LTC6400-20, AV = 8dB, 14dB, 20dB, 26dB
–74dBc IM3 at 140MHz 2VP-P Composite, IS = 50mA, AV = 8dB, 14dB,
20dB, 26dB
Dual Version of the LTC6401-20, AV = 8dB, 14dB, 20dB, 26dB
Continuously Adjustable Gain Control, –14dB to 17dB Linear-in-dB
Gain Range
OIP3 = 46dBm at 200MHz, Gain Range 1.725 to 17.6dB 0.125dB Steps
OIP3 = 47dBm at 100MHz, Gain Range 10.5dB to 33dB 1.5dB Steps
OIP3 = 40dBm at 100MHz, Gain Range 4.5dB to 37dB 1.5dB Steps
–84dBc IM3 at 160MHz 2VP-P Composite, AV = 1, en = 1.8nV/√Hz, 42mA
AC- or DC-Coupled 0MHz to 100MHz
–65dBc IM3 at 50MHz 2VP-P Composite, Rail-to-Rail Inputs,
en = 1.6nV/√Hz, 18mA
16-Bit SNR and SFDR at 10MHz, Rail-to-Rail Outputs, en = 1.5nV/√Hz,
LTC6404-1 is Unity-Gain Stable, LTC6404-2 is Gain-of-2 Stable
16-Bit SNR and SFDR at 3MHz, Rail-to-Rail Outputs, en = 2.8nV/√Hz
77.3dBFS Noise Floor, 100dB SFDR
78dBFS Noise Floor, 100dB SFDR
6417f
32 Linear Technology Corporation
LT 0712 • PRINTED IN USA
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●
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