LTC6431-15
50Ω Gain Block
IF Amplifier
Features
Description
20MHz to 1700MHz Bandwidth
n 15.5dB Power Gain
n 47dBm OIP3 at 240MHz into a 50Ω Load
n NF = 3.33dB at 240MHz
n 1nV/√Hz Total Input Noise
n S11 < –15dB Up to 1.2GHz
n S22 < –15dB Up to 1.2GHz
n > 2V
P-P Linear Output Swing
n P1dB = 20.6dBm
n DC Power = 450mW
n 50Ω Single-Ended Operation
n Insensitive to V
CC Variation
n A-Grade 100% OIP3 Tested at 240MHz
n Input/Output Internally Matched to 50Ω
n Single 5V Supply
n Unconditionally Stable
The LTC®6431-15 is a gain-block amplifier with excellent
linearity at frequencies beyond 1000MHz and with low
associated output noise.
n
The unique combination of high linearity, low noise and
low power dissipation make this an ideal candidate for
many signal-chain applications. The LTC6431-15 is easy
to use, requiring a minimum of external components. It is
internally input/output matched to 50Ω and it draws only
90mA from a single 5V supply.
On-chip bias and temperature compensation maintain
performance over environmental changes.
The LTC6431-15 uses a high performance SiGe BiCMOS
process for excellent repeatability compared with similar
GaAs amplifiers. All A-grade LTC6431-15 devices are tested
and guaranteed for OIP3 at 240MHz. The LTC6431-15 is
housed in a 4mm × 4mm 24-lead QFN package with an
exposed pad for thermal management and low inductance.
Applications
Single-Ended IF Amplifier
ADC Driver
n CATV
n
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
n
Typical Application
Single-Ended IF Amplifier
OIP3 vs Frequency
50
5V
1000pF
48
RF
CHOKE,
560nH
46
1000pF
LTC6431-15
RSOURCE
50Ω
RLOAD
50Ω
643115 TA01a
OIP3 (dBm)
VCC = 5V
44
42
40
VCC = 5V, T = 25°C
POUT = 2dBm/TONE
fSPACE = 1MHz
ZIN = ZOUT = 50Ω
38
36
0
200
400
600
FREQUENCY (MHz)
800
1000
643115 TA01b
643115f
1
LTC6431-15
Absolute Maximum Ratings
Pin Configuration
(Note 1)
Total Supply Voltage (VCC to GND)...........................5.5V
Amplifier Output Current (OUT)............................105mA
RF Input Power, Continuous, 50Ω (Note 2)..........15dBm
RF Input Power, 100µs Pulse, 50Ω (Note 2).........20dBm
Operating Case Temperature
Range (TCASE)...........................................–40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
Junction Temperature (TJ)..................................... 150°C
DNC
DNC
DNC
VCC
GND
IN
TOP VIEW
24 23 22 21 20 19
DNC 1
18 OUT
DNC 2
17 GND
DNC 3
16 T_DIODE
25
GND
DNC 4
15 DNC
DNC 5
14 DNC
DNC 6
DNC
DNC
DNC
DNC
9 10 11 12
VCC
8
GND
13 DNC
7
UF PACKAGE
24-LEAD (4mm × 4mm) PLASTIC QFN
TJMAX = 150°C, θJC = 54°C/W
EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC6431AIUF-15#PBF
LTC6431AIUF-15#TRPBF
43115
24-Lead (4mm × 4mm) Plastic QFN
–40°C to 85°C
LTC6431BIUF-15#PBF
LTC6431BIUF-15#TRPBF
43115
24-Lead (4mm × 4mm) Plastic QFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
DC
Electrical Characteristics
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VCC = 5V, ZSOURCE = ZLOAD = 50Ω. Typical measured DC electrical
performance using Test Circuit A.
SYMBOL PARAMETER
VS
Operating Supply Range
IS,TOT
Total Supply Current
IS,OUT
ICC,OUT
Total Supply Current to OUT Pin
Current to VCC Pin
CONDITIONS
MIN
TYP
MAX
UNITS
4.75
5.0
5.25
V
75
67
85.1
l
100
112
mA
mA
62
55
71
l
92
95
mA
mA
12
12.5
14
l
16
16.5
mA
mA
All VCC Pins Plus OUT
Current to OUT
Either VCC Pin May Be Used
643115f
2
LTC6431-15
AC
Electrical Characteristics A = 25°C (Note 3), VCC = 5V, ZSOURCE = ZLOAD = 50Ω, unless otherwise
T
noted. Measurements are performed using Test Circuit A, measuring from 50Ω SMA to 50Ω SMA without de-embedding (Note 4).
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Small Signal
BW
–3dB Bandwidth
De-Embedded to Package (Low Frequency
Cutoff 20MHz)
2000
MHz
S11
Input Return Loss, 20MHz to 2000MHz
De-Embedded to Package
–10
dB
S21
Forward Power Gain, 50MHz to 300MHz
De-Embedded to Package
15.5
dB
S12
Reverse Isolation, 20MHz to 3000MHz
De-Embedded to Package
–19
dB
S22
Output Return Loss, 20MHz to 1700MHz
De-Embedded to Package
–10
dB
15.5
dB
Frequency = 50MHz
S21
Power Gain
De-Embedded to Package
OIP3
Output Third-Order Intercept Point
POUT = 2dBm/Tone, Δf = 1MHz
A-Grade
B-Grade
46.0
45.0
dBm
dBm
IM3
Third-Order Intermodulation
POUT = 2dBm/Tone, Δf = 1MHz
A-Grade
B-Grade
–88.0
–86.0
dBc
dBc
HD2
Second Harmonic Distortion
POUT = 6dBm
–58.0
dBc
HD3
Third Harmonic Distortion
POUT = 6dBm
–88.0
dBc
P1dB
Output 1dB Compression Point
20.5
dBm
NF
Noise Figure
De-Embedded to Package
3.06
dB
15.5
dB
Frequency = 140MHz
S21
Power Gain
De-Embedded to Package
OIP3
Output Third-Order Intercept Point
POUT = 2dBm/Tone, Δf = 1MHz
A-Grade
B-Grade
47.0
46.0
dBm
dBm
IM3
Third-Order Intermodulation
POUT = 2dBm/Tone, Δf = 1MHz
A-Grade
B-Grade
–90.0
–88.0
dBc
dBc
HD2
Second Harmonic Distortion
POUT = 6dBm
–58.0
dBc
HD3
Third Harmonic Distortion
POUT = 6dBm
–88.0
dBc
P1dB
Output 1dB Compression Point
20.7
dBm
NF
Noise Figure
3.20
dB
De-Embedded to Package
Frequency = 240MHz
S21
Power Gain
De-Embedded to Package
l
14.5
14.2
15.6
16.5
16.7
dB
dB
OIP3
Output Third-Order Intercept Point
POUT = 2dBm/Tone, Δf = 8MHz
A-Grade
B-Grade
44.0
47.0
45.5
dBm
dBm
IM3
Third-Order Intermodulation
POUT = 2dBm/Tone, Δf = 8MHz
A-Grade
B-Grade
–84
–90.0
–87.0
dBc
dBc
HD2
Second Harmonic Distortion
POUT = 6dBm
–59.0
dBc
HD3
Third Harmonic Distortion
POUT = 6dBm
–88.0
dBc
P1dB
Output 1dB Compression Point
20.6
dBm
NF
Noise Figure
3.33
dB
De-Embedded to Package
643115f
3
LTC6431-15
AC
Electrical Characteristics A = 25°C (Note 3), VCC = 5V, ZSOURCE = ZLOAD = 50Ω, unless otherwise
T
noted. Measurements are performed using Test Circuit A, measuring from 50Ω SMA to 50Ω SMA without de-embedding (Note 4).
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Frequency = 300MHz
S21
Power Gain
De-Embedded to Package
OIP3
Output Third-Order Intercept Point
POUT = 2dBm/Tone, Δf = 1MHz
IM3
Third-Order Intermodulation
POUT = 2dBm/Tone, Δf = 1MHz
HD2
Second Harmonic Distortion
HD3
Third Harmonic Distortion
P1dB
Output 1dB Compression Point
NF
Noise Figure
15.5
dB
A-Grade
B-Grade
46.5
45.5
dBm
dBm
A-Grade
B-Grade
–89.0
–87.0
dBc
dBc
POUT = 6dBm
–60.0
dBc
POUT = 6dBm
–86.0
dBc
20.6
dBm
De-Embedded to Package
3.41
dB
15.4
dB
Frequency = 380MHz
S21
Power Gain
De-Embedded to Package
OIP3
Output Third-Order Intercept Point
POUT = 2dBm/Tone, Δf = 1MHz
A-Grade
B-Grade
46.0
45.0
dBm
dBm
IM3
Third-Order Intermodulation
POUT = 2dBm/Tone, Δf = 1MHz
A-Grade
B-Grade
–88.0
–86.0
dBc
dBc
HD2
Second Harmonic Distortion
POUT = 6dBm
–57.0
dBc
HD3
Third Harmonic Distortion
POUT = 6dBm
–87.0
dBc
20.6
dBm
De-Embedded to Package
3.48
dB
15.3
dB
P1dB
Output 1dB Compression Point
NF
Noise Figure
Frequency = 500MHz
S21
Power Gain
De-Embedded to Package
OIP3
Output Third-Order Intercept Point
POUT = 2dBm/Tone, Δf = 1MHz
A-Grade
B-Grade
44.5
43.5
dBm
dBm
IM3
Third-Order Intermodulation
POUT = 2dBm/Tone, Δf = 1MHz
A-Grade
B-Grade
–85.0
–83.0
dBc
dBc
HD2
Second Harmonic Distortion
POUT = 6dBm
–55.6
dBc
HD3
Third Harmonic Distortion
POUT = 6dBm
–77.0
dBc
20.6
dBm
De-Embedded to Package
3.60
dB
15.3
dB
P1dB
Output 1dB Compression Point
NF
Noise Figure
Frequency = 600MHz
S21
Power Gain
De-Embedded to Package
OIP3
Output Third-Order Intercept Point
POUT = 2dBm/Tone, Δf = 1MHz
A-Grade
B-Grade
41.5
40.5
dBm
dBm
IM3
Third-Order Intermodulation
POUT = 2dBm/Tone, Δf = 1MHz
A-Grade
B-Grade
–79.0
–77.0
dBc
dBc
HD2
Second Harmonic Distortion
POUT = 6dBm
–53.6
dBc
HD3
Third Harmonic Distortion
POUT = 6dBm
–69.0
dBc
20.6
dBm
De-Embedded to Package
3.67
dB
P1dB
Output 1dB Compression Point
NF
Noise Figure
643115f
4
LTC6431-15
AC
Electrical Characteristics A = 25°C (Note 3), VCC = 5V, ZSOURCE = ZLOAD = 50Ω, unless otherwise
T
noted. Measurements are performed using Test Circuit A, measuring from 50Ω SMA to 50Ω SMA without de-embedding (Note 4).
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Frequency = 700MHz
S21
Power Gain
De-Embedded to Package
OIP3
Output Third-Order Intercept Point
POUT = 2dBm/Tone, Δf = 1MHz
IM3
Third-Order Intermodulation
POUT = 2dBm/Tone, Δf = 1MHz
HD2
Second Harmonic Distortion
HD3
Third Harmonic Distortion
P1dB
Output 1dB Compression Point
NF
Noise Figure
15.2
dB
A-Grade
B-Grade
40.0
39.0
dBm
dBm
A-Grade
B-Grade
–76.0
–74.0
dBc
dBc
POUT = 6dBm
–51.9
dBc
POUT = 6dBm
–69.0
dBc
20.3
dBm
De-Embedded to Package
3.75
dB
15.2
dB
Frequency = 800MHz
S21
Power Gain
De-Embedded to Package
OIP3
Output Third-Order Intercept Point
POUT = 2dBm/Tone, Δf = 1MHz
A-Grade
B-Grade
39.0
38.0
dBm
dBm
IM3
Third-Order Intermodulation
POUT = 2dBm/Tone, Δf = 1MHz
A-Grade
B-Grade
–74
–72
dBc
dBc
HD2
Second Harmonic Distortion
POUT = 6dBm
–49.2
dBc
HD3
Third Harmonic Distortion
POUT = 6dBm
–65.0
dBc
20.1
dBm
De-Embedded to Package
3.83
dB
15.1
dB
P1dB
Output 1dB Compression Point
NF
Noise Figure
Frequency = 900MHz
S21
Power Gain
De-Embedded to Package
OIP3
Output Third-Order Intercept Point
POUT = 2dBm/Tone, Δf = 1MHz
A-Grade
B-Grade
38.5
37.5
dBm
dBm
IM3
Third-Order Intermodulation
POUT = 2dBm/Tone, Δf = 1MHz
A-Grade
B-Grade
–73.0
–71.0
dBc
dBc
HD2
Second Harmonic Distortion
POUT = 6dBm
–46.7
dBc
HD3
Third Harmonic Distortion
POUT = 6dBm
–63.0
dBc
19.9
dBm
De-Embedded to Package
3.90
dB
15.0
dB
P1dB
Output 1dB Compression Point
NF
Noise Figure
Frequency = 1000MHz
S21
Power Gain
De-Embedded to Package
OIP3
Output Third-Order Intercept Point
POUT = 2dBm/Tone, Δf = 1MHz
A-Grade
B-Grade
38.0
37.0
dBm
dBm
IM3
Third-Order Intermodulation
POUT = 2dBm/Tone, Δf = 1MHz
A-Grade
B-Grade
–72.0
–70.0
dBc
dBc
HD2
Second Harmonic Distortion
POUT = 6dBm
–45.0
dBc
HD3
Third Harmonic Distortion
POUT = 6dBm
–59.0
dBc
19.5
dBm
De-Embedded to Package
3.99
dB
P1dB
Output 1dB Compression Point
NF
Noise Figure
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to any Absolute Maximum
Rating condition for extended periods may affect device reliability and lifetime.
Note 2: Guaranteed by design and characterization. This parameter is not tested.
Note 3: The LTC6431-15 is guaranteed functional over the case operating
temperature range of –40°C to 85°C.
Note 4: Small-signal parameters S and noise are de-embedded to the package
pins, while large-signal parameters are measured directly from the circuit.
643115f
5
LTC6431-15
Typical
Performance Characteristics A = 25°C, VCC = 5V, ZSOURCE = ZLOAD = 50Ω, unless
T
otherwise noted. Measurements are performed using Test Circuit A, measuring from 50Ω SMA to 50Ω SMA without de-embedding (Note 4).
Stability Factor K vs Frequency
Over Temperature
10
20
9
STABILITY FACTOR K (UNITLESS)
25
15
S11
S21
S12
S22
10
MAG (dB)
5
0
–5
–10
–15
–20
8
TCASE =
100°C
85°C
60°C
35°C
25°C
0°C
–20°C
–40°C
8
7
6
5
4
0
500
1000 1500 2000
FREQUENCY (MHz)
2500
3000
6
5
2
2
1
0
1000
643115 G01
3000
4000
2000
FREQUENCY (MHz)
S11 vs Frequency Over Temperature
0
–15
TCASE =
100°C
85°C
60°C
35°C
25°C
0°C
–20°C
–40°C
10
8
–25
0
2
2500
3000
S12 vs Frequency Over Temperature
500
TCASE =
100°C
–5
85°C
60°C
35°C
–10
25°C
0°C
–20°C
–15
–40°C
2500
3000
643115 G05
TCASE =
100°C
85°C
60°C
35°C
25°C
0°C
–20°C
–40°C
–5
–20
1000 1500 2000
FREQUENCY (MHz)
S22 vs Frequency Over Temperature
0
MAG S22 (dB)
MAG S12 (dB)
0
643115 G04
0
–10
–15
–20
–25
–25
–30
643115 G03
14
12
4
1000 1500 2000
FREQUENCY (MHz)
400 600 800 1000 1200 1400
FREQUENCY (MHz)
16
6
500
200
18
–20
0
0
643115 G02
S21 vs Frequency Over Temperature
MAG S21 (dB)
MAG S11 (dB)
–10
0
5000
20
TCASE =
100°C
85°C
60°C
35°C
25°C
0°C
–20°C
–40°C
–5
4
3
3
0
TCASE =
–40°C
25°C
85°C
7
1
–25
–30
Noise Figure vs Frequency
Over Temperature
NF (dB)
S Parameters vs Frequency
0
500
1000 1500 2000
FREQUENCY (MHz)
2500
3000
643115 G06
–30
0
500
1000 1500 2000
FREQUENCY (MHz)
2500
3000
643115 G07
643115f
6
LTC6431-15
Typical
Performance Characteristics
A-Grade
TA = 25°C, VCC = 5V, ZSOURCE = ZLOAD = 50Ω, unless otherwise noted. Measurements are performed using Test Circuit A, measuring
from 50Ω SMA to 50Ω SMA without de-embedding (Note 4).
OIP3 vs Frequency Over
OIP3 vs Frequency
VCC Voltage
OIP3 vs Power Out Over Frequency
52
50
OIP3 (dBm)
46
44
42
40
46
44
42
40
38
36
VCC = 5V, T = 25°C
= 2dBm/ TONE
P
38 OUT
fSPACE = 1MHz
ZIN = ZOUT = 50Ω
36
400
200
0
FREQUENCY (MHz)
30
–10 –8 –6 –4 –2 0 2 4 6
RF POWER OUT (dBm/TONE)
1000
643115 G08
50MHz
100MHz
200MHz
240MHz
300MHz
400MHz
500MHz
600MHz
643115 G09
34
0 100 200 300 400 500 600 700 800 900 1000
FREQUENCY (MHz)
643115 G10
45
40
OIP3 (dBm)
OIP3 (dBm)
10
50
46
44
42
35
30
40
25
38
36
8
4.5V
4.75V
5V
5.25V
5.5V
OIP3 vs Frequency Over
Case Temperature
VCC = 5V, T = 25°C
POUT = 2dBm/TONE
ZIN = ZOUT = 50Ω
48
40
700MHz
800MHz
900MHz
1000MHz
OIP3 vs Tone Spacing
Over Frequency
50
42
36
32
800
44
38
34
600
T = 25°C
POUT = 2dBm/TONE
fSPACE = 1MHz
ZIN = ZOUT = 50Ω
48
OIP3 (dBm)
48
OIP3 (dBm)
50
VCC = 5V
50 POUT = 2dBm/TONE
48 fSPACE = 1MHz
ZIN = ZOUT = 50Ω
46
0
2
4
50MHz
100MHz
200MHz
240MHz
6
8
10 12 14 16 18 20
TONE SPACING (MHz)
643115 G11
300MHz
400MHz
500MHz
600MHz
20
85°C
60°C
25°C
0°C
–20°C
–30°C
–40°C
VCC = 5V
POUT = 2dBm/TONE
fSPACE = 1MHz
ZIN = ZOUT = 50Ω
0 100 200 300 400 500 600 700 800 900 1000
FREQUENCY (MHz)
643115 G12
700MHz
800MHz
900MHz
1000MHz
643115f
7
LTC6431-15
T
Typical
Performance Characteristics A = 25°C, VCC = 5V, ZSOURCE = ZLOAD = 50Ω, unless
otherwise noted. Measurements are performed using Test Circuit A, measuring from 50Ω SMA to 50Ω SMA without de-embedding (Note 4).
HD2 vs Frequency Over POUT
HD3 vs Frequency Over POUT
POUT =
6dBm
8dBm
10dBm
POUT =
6dBm
8dBm
–20
10dBm
–30
HD3 (dBc)
–30
–40
–40
–70
–80
–80
–90
–90
–100
TCASE = 25°C
0 100 200 300 400 500 600 700 800 900 1000
FREQUENCY (MHz)
643115 G14
95
98
90
96
85
ITOT (mA)
ITOT (mA)
70
VCC = 5V
92
90
88
60
4.25 4.5 4.75
5.25 5.5 5.75
VCC (V)
–20
20
12
0
–10 –8 –6 –4 –2 0 2 4
INPUT POWER (dBm)
500MHz
600MHz
700MHz
800MHz
900MHz
1000MHz
6
643115 G17
8
10
643115 G19
0
5
10
15
20
643115 G21
20
14.0
60MHz
100MHz
140MHz
200MHz
240MHz
300MHz
400MHz
13.5
13.0
12.5
12.0
–5
P1dB vs Frequency
21
14.5
–10
RF INPUT POWER (dBm)
15.5
14
2
50
–15
100
22
16
4
80
16.0
15.0
GAIN (dB)
OUTPUT POWER (dBm)
18
6
0
20
40
60
TEMPERATURE (°C)
Gain vs Output Power
Over Frequency
22
60MHz
100MHz
140MHz
200MHz
240MHz
300MHz
400MHz
65
55
Output Power vs Input Power
Over Frequency
8
70
84
643115 G16
10
75
60
–40
VCC = 5V
T = 25°C
80
86
82
6
5
0 100 200 300 400 500 600 700 800 900 1000
FREQUENCY (MHz)
643115 G15
Total Current vs RF Input Power
100
94
4
–60
–70
Total Current (ITOT)
vs Case Temperature
80
50
–50
–100
Total Current (ITOT) vs VCC
90
–40
–60
–60
100
–10
–50
–50
0 100 200 300 400 500 600 700 800 900 1000
FREQUENCY (MHz)
643115 G13
POUT =
6dBm
8dBm
–20
10dBm
–30
–10
P1dB (dBm)
HD2 (dBc)
–20
–70
0
HD4 (dBc)
–10
HD4 vs Frequency Over POUT
0
TOTAL CURRENT (mA)
0
0
5
500MHz
600MHz
700MHz
800MHz
900MHz
1000MHz
10
15
OUTPUT POWER (dBm)
19
18
17
16
20
643115 G20
0 100 200 300 400 500 600 700 800 900 1000
FREQUENCY (MHz)
643115 G21
643115f
8
LTC6431-15
Pin Functions
GND (Pins 8, 17, 23, Exposed Pad Pin 25): Ground. For
best RF performance, all ground pins should be connected
to the printed circuit board ground plane. The exposed pad
should have multiple via holes to an underlying ground
plane for low inductance and good thermal dissipation.
IN (Pin 24): Signal Input Pin. This pin has an internally
generated 2V DC bias. A DC blocking capacitor is required.
See the Applications Information section for specific
recommendations.
VCC (Pins 9, 22): Positive Power Supply. Either VCC pin
should be connected to the 5V supply. Bypass the VCC pin
with 1000pF and 0.1µF capacitors. The 1000pF capacitor
should be physically close to Pin 22.
OUT (Pin 18): Amplifier Output Pin. A choke inductor is
necessary to provide power from the 5V supply and to
provide RF isolation. For best performance select a choke
with low loss and high self-resonant frequency (SRF). A
DC blocking capacitor is also required. See the Applications Information section for specific recommendations.
DNC (Pins 1 to 7, 10 to 15, 19 to 21): Do Not Connect.
Do not connect these pins; allow them to float. Failure to
float these pins may impair operation of the LTC6431-15.
T_DIODE (Pin 16): Optional Diode. The T_DIODE can be
forward-biased to ground with 1mA of current. The measured voltage will be an indicator of chip temperature.
Block Diagram
VCC
9, 22
BIAS AND TEMPERATURE
COMPENSATION
24
IN
15dB
GAIN
OUT
T_DIODE
18
16
GND
8, 17, 23, 25 (EXPOSED PAD)
643115 BD
643115f
9
LTC6431-15
Test Circuit A
C1
60pF
C5
1nF
C6
0.1µF
OPTIONAL
STABILITY
NETWORK
L1
560nH
DNC
DNC
IN
R1
350Ω
DNC
VCC = 5V
VCC
C7
1000pF
GND
PORT
INPUT
DNC
OUT
DNC
GND
DNC
T_DIODE
DNC
DNC
DNC
DNC
DNC
VCC
GND
DNC
DNC
PORT
OUTPUT
DNC
LTC6431-15
DNC
C3
1000pF
DNC
643115 F01
Figure 1. Application, Test Circuit A
Operation
The LTC6431-15 is a highly linear, fixed-gain amplifier that
is configured to operate single ended. Its core signal path
consists of a single amplifier stage minimizing stability issues. The input is a Darlington pair for high input impedance
and high current gain. Additional circuit enhancements
increase the output impedance and minimize the effects
of internal Miller capacitance.
The LTC6431-15 starts with a classic RF gain-block topology but adds additional enhancements to achieve dramati-
cally improved linearity. Shunt and series feedback are
added to lower the input/output impedance and match them
simultaneously to the 50Ω source and load. Meanwhile,
an internal bias controller optimizes the internal operating
point for peak linearity over environmental changes. This
circuit architecture provides low noise, excellent RF power
handling capability and wide bandwidth—characteristics
that are desirable for IF signal chain applications.
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LTC6431-15
Applications Information
The LTC6431-15 is a highly linear fixed-gain amplifier
which is designed for ease of use. Implementing an RF
gain stage is often a multistep project. Typically an RF
designer must choose a bias point and design a bias
network. Next the designer needs to address impedance
matching with input and output matching networks and,
finally, add stability networks to ensure stable operation
in and out of band. These tasks are handled internally
within the LTC6431-15.
The LTC6431-15 has an internal self-biasing network
which compensates for temperature variation and keeps
the device biased for optimal linearity. Therefore, input
and output DC blocking capacitors are required.
Both the input and output are internally impedance matched
to 50Ω from 20MHz to 1700MHz. Similarly, an RF choke is
required at the output to deliver DC current to the device.
The RF choke acts as a high impedance (isolation) to
the DC supply which is at RF ground. Thus, the internal
LTC6431-15 impedance matching is unaffected by the
biasing network. The open collector output topology can
deliver much more power than an amplifier whose collector
is biased through a resistor or active load.
Choosing the Right RF Choke
Not all choke inductors are created equal. It is always
important to select an inductor with low RLOSS, as this will
drop the available voltage to the device. Also look for an
inductor with high self-resonant frequency (SRF) as this
will limit the upper frequency where the choke is useful.
Above the SRF, the parasitic capacitance dominates and
the choke impedance will drop. For these reasons, wire
wound inductors are preferred, and multilayer ceramic
chip inductors should be avoided for an RF choke. Since
the LTC6431-15 is capable of such wideband operation,
a single choke value will probably not result in optimized
performance across its full frequency band. Table 1 lists
target frequency bands and suggested corresponding
inductor values.
Table 1. Target Frequency Bands and Suggested Inductor Values
FREQUENCY BAND INDUCTOR VALUE
(MHz)
(nH)
MODEL
NUMBER
20 to 100
1500nH
0805LS
100 to 500
560nH
0603LS
500 to 1000
100nH
0603LS
1000 to 2000
51nH
0603LS
MANUFACTURER
Coilcraft
www.coilcraft.com
DC Blocking Capacitor
The role of a DC blocking capacitor is straightforward:
block the path of DC current and allow a low series impedance path for the AC signal. Lower frequencies require a
higher value of DC blocking capacitance. Generally, 1000pF
to 10000pF will suffice for operation down to 20MHz.
The LTC6431-15 is relatively insensitive to the choice of
blocking capacitor.
RF Bypass Capacitor
RF bypass capacitors act to shunt AC signals to ground
with a low impedance path. It is best to place them as close
as possible to the DC power supply pins of the device.
Any extra distance translates into additional series inductance which lowers the self-resonant frequency and
useful bandwidth of the bypass capacitor. The suggested
bypass capacitor network consists of two capacitors:
a low value 1000pF capacitor to handle high frequencies
in parallel with a larger 0.1µF capacitor to handle lower
frequencies. Use ceramic capacitors of an appropriate
physical size for each capacitance value (e.g., 0402 for
the 1000pF, 0805 for the 0.1µF) to minimize the equivalent series resistance (ESR) of the capacitor.
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LTC6431-15
Applications Information
Low Frequency Stability
Most RF gain blocks suffer from low frequency instability.
To avoid any stability issues, the LTC6431-15 has an internal
feedback network that lowers the gain and matches the
input and output impedances at frequencies above 20MHz.
This feedback network contains a series capacitor, so if at
some low frequency the feedback fails, the gain increases
and gross impedance mismatches occur—indeed a recipe
for instability. Luckily, this situation is easily resolved with
a parallel capacitor and resistor network on the input, as
seen in Figure 1. This network provides resistive loss at
low frequencies and is bypassed by the parallel capacitor within the desired band of operation. However, if the
LTC6431-15 is preceeded by a low frequency termination,
such as a choke, the input stability network is NOT required.
Test Circuit
The test circuit shown in Figure 2 is designed to allow
evaluation of the LTC6431-15 with standard single-ended
50Ω test equipment. The circuit requires a minimum of
external components. Since the LTC6431-15 is a wideband
part, the evaluation test circuit is optimized for wideband
operation. Obviously, for narrowband applications the
circuit can be further optimized. As mentioned earlier,
input and output DC blocking capacitors are required as
this device is internally biased for optimal operation. A
frequency appropriate choke and decoupling capacitors
are required to provide DC bias to the RF out node. A 5V
supply should also be applied to both of the VCC pins on
the device. A suggested parallel 60pF, 350Ω network has
been added to the input to ensure low frequency stability.
The 60pF capacitance can be increased to improve low
frequency (
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