FEATURES
LTC6563
Four-Channel
Transimpedance Amplifier
with Output Multiplexing
DESCRIPTION
600MHz –3dB Bandwidth with 0.5pF Input Capacitance
n Differential Output with Up to 2V
P-P Swing into 100Ω
Differential Load
n Built-In High-Speed ADC Driver with Output MUX
n Selectable 22.2/16.7/11.1/5.55kΩ Transimpedance Gain
n 1.8pA/3.7pA√Hz Input Current Noise Density
100MHz/600MHz (0.5pF)
n 65nA
RMS Integrated Input-Referred Current Noise
Over 600MHz (0.5pF)
n Large Linear Input Current Range 0µA to 90µA
n Large Transient Overload Current >1A Peak
n Fast Overload Recovery: 2.5ns
n Fast Channel Switching: 10ns
n Power Dissipation: 194mW to 325mW on 3.3V,
Varies with Output Mode (13mW in Shutdown)
n Output MUX allows multiple LTC6563s to Create 8,
12, 16 … 32 Channel Solutions
n 3mm × 5mm, 24-Lead QFN Package, Wettable Flanks
n AECQ-100 Grade 1 Qualified (Pending)
The LTC®6563 is a low-noise four-channel transimpedance
amplifier (TIA) with 600MHz bandwidth. The LTC6563
TIA’s low noise, wide linear range, and low power dissipation are ideal for LIDAR receivers using Avalanche photodiodes (APDs) and photodiodes (PDs). The amplifier features selectable 22.2/16.7/11.1/5.55kΩ Transimpedance
gain (RT) and 90µA linear input current range. Using an
APD with a total input capacitance of 0.5pF, the input current noise density is 1.8pA/√Hz at 100MHz and 3.7pA/√Hz
at 600MHz. The LTC6563 consumes between 194mW and
325mW on a 3.3V supply depending on output mode.
An internal 4-to-1 MUX simplifies the system design. In
addition, external multiplexing capability allows channel
expansion up to 64 channels, saving space and power.
Fast overload recovery and fast channel switchover make
the LTC6563 well suited for LIDAR receivers with multiple
APDs. The built-in high-speed differential ADC driver can
swing as much as 2VP-P while driving into 100Ω external
differential load.
APPLICATIONS
The LTC6563 is packaged in a 3mm × 5mm 24-pin
exposed pad QFN package with wettable flanks.
n
n
n
Automotive LIDAR Receiver
Industrial LIDAR Receiver
All registered trademarks and trademarks are the property of their respective owners.
TYPICAL APPLICATION
Typical Application with DC-Coupled Inputs Driving an ADC
3.3V
OFFSET
3.3V
VCCI VCCO
OMUX(2)
3.3V
TILT
OMUX
MULTIPLE LTC6563's
PWRMD
IN1
50Ω
4:1
MUX
OUTPUT
STAGE
CM
CTRL
50Ω
TIA
IN4
GND
100Ω
CHSEL1
TERM(2)
OUT(2)
TERM
0.1µF
AD9094
VCM
INPUT
20µA/DIV
OUT DIFF
250mV/DIV
100Ω
OUT
OUTPUT
CLAMPS
TIA
APD
ARRAY
Pulse Response
TERM(2)
TERM
TIA
IN3
V–
OUT
TIA
IN2
OUT(2)
LTC6563
BIAS
CTRL
CHSEL0 ADJ1
ADJ0 HI
×1
–
1ns/DIV
LO
+
×2
6563 TA01b
CM
0.1µF
6563 TA01a
Rev. 0
Document Feedback
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1
LTC6563
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
IN2
ADJ0
ADJ1
IN3
TOP VIEW
24 23 22 21
GND 1
20 GND
IN4 2
19 IN1
GND 3
18 GND
PWRMD 4
17 TILT
25
GND
VCCI 5
16 OFFSET
OMUX 6
15 CHSEL0
CM 7
14 VCCO
13 CHSEL1
HI 8
OUT
TERM
OUT
9 10 11 12
TERM
Total Supply Voltage:
VCCI to GND..........................................................3.6V
VCCO to GND.........................................................3.6V
Input Current (CHSEL0, CHSEL1, ADJ0, ADJ1,
PWRMD, OMUX, CM, HI, OFFSET, TILT).......... ±10mA
Amplifier Inputs (IN1, IN2, IN3, IN4):
Voltage................................................... –0.3V to 3.6V
Current........................................... 10µA/–400mARMS
Current (Note 5)......................................–1A Transient
Amplifier Outputs (OUT, OUT):
Voltage................................................... –0.3V to 3.6V
Current............................................................ ±100mA
Amplifier Output Termination (TERM, TERM):
Voltage................................................... –0.3V to 3.6V
Current..................................................... –72mA/6mA
Operating Temperature Range:
LTC6563I (Note 2)................................–40°C to 85°C
LTC6563H (Note 3)............................. –40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
Junction Temperature............................................ 150°C
UDDM PACKAGE
24-LEAD (3mm × 5mm) SIDE SOLDERABLE PLASTIC QFN
TJMAX = 150°C, θJC = 5°C/W
EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING* PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC6563IUDDM#PBF
LTC6563IUDDM#TRPBF
LHMH
24-Lead (3mm × 5mm) Side Solderable Plastic QFN
–40°C to 85°C
LTC6563HUDDM#PBF
LTC6563HUDDM#TRPBF
LHMH
24-Lead (3mm × 5mm) Side Solderable Plastic QFN
–40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
2
Rev. 0
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LTC6563
AC ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, ADJ0 = ADJ1 = PWRMD = OMUX = VCCI = HI = VCCO = 3.3V, TILT =
OFFSET = 0, VCM = 1.5V. All other input pins are floating unless stated otherwise. VOUTCM is defined as (OUT + OUT )/2 and VOUTDIFF is
defined as (OUT – OUT), RL_EXT = 100Ω differential, OUT connected to TERM and OUT connected to TERM.
SYMBOL
PARAMETER
CONDITIONS
BW
–3dB Bandwidth
200mVP-P,OUT and CIN,TOT = 0.5pF
MIN
600
MHz
SR
Slew Rate
CIN,TOT = 0.5pF
3000
V/us
tR/tF
Rise/Fall Time
CIN,TOT = 0.5pF
0.6
RT Differential
Small Signal Transimpedance
IIN < 2µAP-P, ADJ00
IIN < 2µAP-P, ADJ01
IIN < 2µAP-P, ADJ10
IIN < 2µAP-P, ADJ11
TCRT
Transimpedance Temperature Coefficient
IIN < 2µAP-P, ADJ00
IIN < 2µAP-P, ADJ01
IIN < 2µAP-P, ADJ10
IIN < 2µAP-P, ADJ11
RIN
Input Impedance
f = 100kHz Active Channel
f = 100kHz Inactive Channel
225
409
Ω
Ω
RTERM_DIFF
Internal Diff Termination Impedance
Measured from TERM to TERMBAR
100
Ω
In
Input Current Noise Density
f = 100MHz, CIN_TOT = 0.5pF
f = 200MHz, CIN_TOT = 0.5pF
f = 300MHz, CIN_TOT = 0.5pF
f = 400MHz, CIN_TOT = 0.5pF
f = 500MHz, CIN_TOT = 0.5pF
f = 600MHz, CIN_TOT = 0.5pF
1.8
2.3
2.5
3
3.4
3.7
pA/√Hz
pA/√Hz
pA/√Hz
pA/√Hz
pA/√Hz
pA/√Hz
Integrated Input Current Noise
f = 0.1MHz to 100MHz, CIN_TOT = 0.5pF
f = 0.1MHz to 200MHz, CIN_TOT = 0.5pF
f = 0.1MHz to 300MHz, CIN_TOT = 0.5pF
f = 0.1MHz to 400MHz, CIN_TOT = 0.5pF
f = 0.1MHz to 500MHz, CIN_TOT = 0.5pF
f = 0.1MHz to 600MHz, CIN_TOT = 0.5pF
19
27
36
45
55
65
nARMS
nARMS
nARMS
nARMS
nARMS
nARMS
tRECOVER
Overload Recovery and Pulse Extension
IIN = –4mA, CIN_TOT = 0.5pF
2.5
ns
tCH_SWITCH
Channel Switching Time
Any Channel to Any Channel
10
ns
tOMUX_SWITCH
Output MUX Switching Time
OMUX
20
ns
Isolation
Channel to Channel Isolation
400MHz, PWRMD = Logic Low, Selected Channel
to Any Unselected Channel
48
dB
4.9
9.6
14.1
18.1
TYP
5.55
11.1
16.7
22.2
MAX
UNITS
ns
6.5
12.5
18.2
23.4
–0.00125
–0.00246
–0.00403
–0.00609
kΩ
kΩ
kΩ
kΩ
kΩ/°C
kΩ/°C
kΩ/°C
kΩ/°C
DC ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, ADJ0 = ADJ1 = PWRMD = OMUX = VCCI = HI = VCCO = 3.3V, TILT =
OFFSET = 0, VCM = 1.5V. All other input pins are floating unless stated otherwise. VOUTCM is defined as (OUT + OUT )/2 and VOUTDIFF is
defined as (OUT – OUT), RL_EXT = 100Ω differential, OUT connected to TERM and OUT connected to TERM.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
IN1, IN2, IN3, IN4 Pins
VIN
Input Bias Voltage
Active Channel
Inactive Channel
0.8
0.7
V
V
IIN
DC Input Current Range
Tilt = 0V
Tilt = 3.3V
40
90
µA
µA
0.9
V
OUT and OUT Pins
VOCM_DEFAULT
Default Output Common-Mode Voltage ADJ = 00
VOOD
Differential Output Offset Voltage
IIN = 0µA
TCVOOD
Differential Output Offset Voltage
Temperature Coefficient
IIN = 0µA,
–75
±10
–0.044
75
mV
mV/°C
Rev. 0
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3
LTC6563
DC ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, ADJ0 = ADJ1 = PWRMD = OMUX = VCCI = HI = VCCO = 3.3V, TILT =
OFFSET = 0, VCM = 1.5V. All other input pins are floating unless stated otherwise. VOUTCM is defined as (OUT + OUT )/2 and VOUTDIFF is
defined as (OUT – OUT), RL_EXT = 100Ω differential, OUT connected to TERM and OUT connected to TERM.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
VSWINGDIFF
Differential Output Voltage Swing
IIN = 0 to –200µA, Tilt = 3.3V
1.13
1.03
1.50
VP-P
VP-P
IIN = 0 to –90µA, Tilt = 3.3V, RL_EXT = 75Ω SE on
Each Output with Center Grounded (see Figure 3)
2.4
VP-P
l
MAX
UNITS
VOUTLOW
Output Voltage Swing Low
Single-Ended Measurement, IIN = 0 to –200µA,
Tilt = 3.3V
1.02
V
VOUTHIGH
Output Voltage Swing High
Single-Ended Measurement, IIN = 0 to –200µA,
Tilt = 3.3V
2.2
V
VCOMPLIANCE
Output Voltage Compliance
Single-Ended Measurement, IIN = 0 to –200µA,
Tilt = 3.3V
2.0
VCCO –1
V
VCM = 1.5V to 1.7V
0.95
1
Output Common Mode Voltage Control (CM Pin)
ACM
CM Pin Voltage Gain, CM Pin to
Differential OUT
1.05
V/V
TCAVCM
ACM Temperature Coefficient
9.3
(µV/V)/°C
VCM_DEFAULT
Default CM Pin Voltage
0.9
V
VCM_OS
Common Mode Offset Voltage
VOUTCM – VCM
TCVCM_OS
Common Mode Offset Voltage
Temperature Coefficient
VOUTCM – VCM
VOUTCM_MIN
VOUTCM Minimum Voltage
VCM = 0V, ADJ00
VOUTCM_MAX
VOUTCM Maximum Voltage
VCM = 2.6V, ADJ11
2.3
V
RCM
CM Pin Input Resistance
16.3
kΩ
CCM
CM Pin Input Capacitance
1.5
pF
1.8
V
–50
10
20
–0.021
0.38
2.2
mV
mV/°C
0.43
V
Output Clamping (HI Pin) See Note 4
VHI_DEFAULT
Default HI Pin Voltage
VHI_VOS
High Side Clamp Offset Voltage
VOUT(MAX) – VHI, HI = 1.7V, IIN = –200µA
–160
–65
25
mV
VLO_VOS
Low Side Clamp Offset Voltage
VOUTBAR(MIN) –(2 • VCM – VHI), HI = 1.7V,
IIN = –200µA
–50
50
150
mV
RHI
HI Pin Input Impedance
13.6
kΩ
CHI
HI Pin Input Capacitance
1.5
pF
Input Current Cancellation (OFFSET Pin)
VOFFSET_DEFAULT Default OFFSET Pin Voltage
0
V
0
μA
ICANCEL_MIN
Minimum Input Cancellation Current
ICANCEL_MAX
Maximum Input Cancellation Current
VOFFSET = 3.3V, Tilt = 3.3V
200
240
GOFFSET
OFFSET Pin Transconductance
(OFFSET Pin Voltage to Input Offset
Current)
VOFFSET = 0.2V to 0.4V, IIN = –40µA
–145
–110
ROFFSET
OFFSET Pin Impedance
tS_OFFSET
Offset Voltage to Output Settling
VOFFSET = 0V
1% of Final Value, IIN = –40µA
μA
–75
μA/V
6.6
kΩ
100
ns
2
mV
Output Offset (TILT Pin)
VTILT_DEFAULT
Default Tilt Pin Voltage
ATILT
TILT Pin Slope, TILT to Differential Out
VTILT = 0.2V to 0.4V
TCATILT
ATILT Temperature Coefficient
VTILT = 0.2V to 0.4V
RTILT
TILT Pin Input Impedance
4
–1.25
–1
–0.7
V/V
–680
(µV/V)/°C
22.7
kΩ
Rev. 0
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LTC6563
DC ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, ADJ0 = ADJ1 = PWRMD = OMUX = VCCI = HI = VCCO = 3.3V, TILT =
OFFSET = 0, VCM = 1.5V. All other input pins are floating unless stated otherwise. VOUTCM is defined as (OUT + OUT )/2 and VOUTDIFF is
defined as (OUT – OUT), RL_EXT = 100Ω differential, OUT connected to TERM and OUT connected to TERM.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ADJ0, ADJ1, CHSEL0, CHSEL1 Pins with Internal Pull-Down Resistors
VIL
Input Low Voltage
VIH
Input High Voltage
0.8
2.4
V
V
IIL
Input Low Current
Pin Voltage = 0.8V
3.8
µA
IIH
Input High Current
Pin Voltage = 2.4V
7.2
µA
CIN
Pin Input Capacitance
1.5
pF
RIN
Pin Input Impedance
To GND
218
kΩ
OMUX, PWRMD, Pins with Internal Pull-Up Resistors
VIL
Input Low Voltage
VIH
Input High Voltage
IIL
Input Low Current
Pin Voltage = 0.8V
–12
µA
IIH
Input High Current
Pin Voltage = 2.4V
–8.6
µA
CIN
Pin Input Capacitance
1.5
pF
RIN
Pin Input Impedance
208
kΩ
0.8
2.4
To VCCI
V
V
Power Supply
VS
Operating Supply Range
IVCCI
Input Supply Current
Any Adjust Setting
3.15
3.3
3.45
V
27.8
34
39.4
40.4
mA
mA
4.5
5.5
6
mA
mA
64.5
81
82
mA
mA
51.5
64.9
65.9
mA
mA
38
48
49
mA
mA
24.5
30.8
31.8
mA
mA
0.1
0.2
0.22
mA
mA
98.5
120.4
122.4
mA
mA
85.5
104.3
106.3
mA
mA
72
87.4
89.4
mA
mA
58.5
70.2
72.2
mA
mA
4.6
5.8
6.3
mA
mA
l
IVCCI_SHUTDOWN Input Supply Current
PWRMD = OMUX = Logic Low
l
IVCCO
Output Supply Current
IVCCO_SHUTDOWN Output Supply Current
ADJ1 = Logic High, ADJ0 = Logic High
VCM = 1.50V
l
49.4
ADJ1 = Logic High, ADJ0 = Logic Low
VCM = 1.25V
l
ADJ1 = Logic Low, ADJ0 = Logic High
VCM = 1.0V
l
ADJ1 = Logic Low, ADJ0 = Logic Low
VCM = 0.75V
l
PWRMD = OMUX = Logic Low
l
IS
IS_SHUTDOWN
Total Supply Current (IS(VCCI) +
IS(VCCO))
ADJ1 = Logic High, ADJ0 = Logic High
VCM = 1.50V
l
ADJ1 = Logic High, ADJ0 = Logic High
VCM = 1.25V
l
ADJ1 = Logic Low, ADJ0 = Logic High
VCM = 1.0V
l
ADJ1 = Logic Low, ADJ0 = Logic Low
VCM = 0.75V
l
Total Supply Current (IS(VCCI) +
IS(VCCO))
PWRMD = OMUX = Logic Low
PSRR(VCCI)
Input Power Supply Rejection Ratio
(∆VOUT/∆VCCI)
VCCI = 3.15V to 3.45V, VCCO = 3.3V
33
36
dB
PSRR(VCCO)
Output Power Supply Rejection Ratio
(∆VOUT/∆VCCO)
VCCO = 3.15V to 3.45V, VCCI = 3.3V
35
38
dB
l
Rev. 0
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5
LTC6563
DC ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC6563I is guaranteed to meet specified performance from
–40°C to 85°C.
Note 3: The LTC6563H is guaranteed to meet specified performance from
–40°C to 125°C.
Note 4: HI pin voltage should be at least 0.2V higher than VCM.
Note 5: This parameter is specified by design and/or characterization and
is not tested in production.
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted specifications are at
CHSEL0 = TILT = OFFSET = 0V, HI = CHSEL1 = PWRMD = ADJ0 = ADJ1 = VCCI = VCCO = 3.3V, and CM = 1.5V. VOUTCM is defined as (OUT
+ OUT)/2 and VOUTDIFF is defined as (OUT – OUT), RL_EXT = 100Ω differential, OUT connected to TERM and OUT connected to TERM.
ISUPPLY vs VSUPPLY Over
Temperature
ISUPPLY vs VSUPPLY Over
Temperature
70
15
125°C
85°C
25°C
–40°C
40
30
0
0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6
VSUPPLY (V)
0
6563 G01
40
30
0
0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6
VSUPPLY (V)
40
ICCI (mA)
ICCI vs VCCI Over Temperature
25
PWRMD = LOGIC HI
FOR ANY ADJ SETTING
OMUX TIED TO LOGIC HI
30
10
20
PWRMD = LOGIC LO
FOR ANY ADJ SETTING
OMUX TIED TO LOGIC HI
20
125°C
85°C
25°C
–40°C
20
0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6
VSUPPLY (V)
6563 G03
ICCI vs VCCI Over Temperature
100
30
0
6563 G02
ISUPPLY vs VSUPPLY Over
Temperature
ISUPPLY = ICCI + ICCO
90 VSUPPLY = VCCI = VCCO
OMUX = LOGIC HI
80 PWRMD = LOGIC LO
70 ADJ = 11
125°C
60
85°C
50
25°C
–40°C
40
125°C
85°C
25°C
–40°C
10
ICCI (mA)
0
50
20
10
5
ISUPPLY (mA)
ISUPPLY = ICCI + ICCO
70 VSUPPLY = VCCI = VCCO
OMUX = LOGIC HI
PWRMD = LOGIC LO
60
ADJ = 10
20
10
0
80
ISUPPLY = ICCI + ICCO
VSUPPLY = VCCI = VCCO
60 OMUX = LOGIC HI
PWRMD = LOGIC LO
50 ADJ = 01
ISUPPLY (mA)
ISUPPLY = ICCI + ICCO
45 VSUPPLY = VCCI = VCCO
OMUX = LOGIC HI
40 PWRMD = LOGIC LO
35 ADJ = 00
125°C
30
85°C
25
25°C
–40°C
20
ISUPPLY (mA)
ISUPPLY (mA)
50
ISUPPLY vs VSUPPLY Over
Temperature
125°C
85°C
25°C
–40°C
15
10
5
10
0
0
0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6
VSUPPLY (V)
6563 G04
6
0
0
0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6
VCCI (V)
6563 G05
0
0
0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6
VCCI (V)
6563 G06
Rev. 0
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LTC6563
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted specifications are at
CHSEL0 = TILT = OFFSET = 0V, HI = CHSEL1 = PWRMD = ADJ0 = ADJ1 = VCCI = VCCO = 3.3V, and CM = 1.5V. VOUTCM is defined as (OUT
+ OUT)/2 and VOUTDIFF is defined as (OUT – OUT), RL_EXT = 100Ω differential, OUT connected to TERM and OUT connected to TERM.
40
OMUX TIED TO LOGIC HI
ADJ = 00
ICCO (mA)
60
OMUX TIED TO LOGIC HI
ADJ = 01
30
125°C
85°C
25°C
–40°C
20
ICCO vs VCCO Over Temperature
125°C
85°C
25°C
–40°C
20
ICCO vs VCCO Over Temperature
OMUX TIED TO LOGIC HI
ADJ = 10
50
125°C
85°C
25°C
–40°C
40
ICCO (mA)
ICCO vs VCCO Over Temperature
ICCO (mA)
30
10
30
20
10
10
0
0
0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6
VCCO (V)
0
6563 G07
350
OMUX TIED TO LOGIC HI
70 ADJ = 11
30
200
150
100
20
0.9
0
0
0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6
VCCO (V)
0
0.5
6563 G10
Output Common Mode Control
1.5
2
VOFFSET (V)
2.5
3
OUTBAR AND TERMBAR SHORTED
OUT AND TERM SHORTED
APPLIES TO ANY TILT VALUE
2.0 ADJ = 01
125°C
85°C
25°C
1.5
–40°C
1.0
0.3 0.7
1 1.3 1.7 2.0 2.3 2.7
CM PIN VOLTAGE (V)
3
6563 G13
0.3 0.7
1 1.3 1.7 2.0 2.3 2.7
CM PIN VOLTAGE (V)
3
6563 G12
Output Common Mode Control
2.5
OUTBAR AND TERMBAR SHORTED
OUT AND TERM SHORTED
APPLIES TO ANY TILT VALUE
2.2
ADJ = 11
OUTBAR AND TERMBAR SHORTED
OUT AND TERM SHORTED
APPLIES TO ANY TILT VALUE
2.0 ADJ = 10
125°C
85°C
25°C
1.5
–40°C
0.5
0
6563 G11
1.0
0
0.4
3.5
2.5
VOUTCM (V)
VOUTCM (V)
1
Output Common Mode Control
2.5
0.5
OUTBAR AND TERMBAR SHORTED
OUT AND TERM SHORTED
APPLIES TO ANY TILT VALUE
1.9 ADJ = 00
125°C
85°C
25°C
1.4
–40°C
50
10
0
VOUTCM (V)
40
2.5
125°C
25°C
–40°C
250
IOFFSET (µA)
ICCO (mA)
125°C
85°C
25°C
–40°C
Output Common Mode Control
DC CANCEL
300
0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6
VCCO (V)
6563 G09
IOFFSET vs VOFFSET
80
50
0
6563 G08
ICCO vs VCCO Over Temperature
60
0
0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6
VCCO (V)
VOUTCM (V)
0
125°C
85°C
25°C
–40°C
1.9
1.6
1.3
0
0.3 0.7
1 1.3 1.7 2.0 2.3 2.7
CM PIN VOLTAGE (V)
3
6563 G14
1.0
0
0.3 0.7
1 1.3 1.7 2.0 2.3 2.7
CM PIN VOLTAGE (V)
3
6563 G15
Rev. 0
For more information www.analog.com
7
LTC6563
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted specifications are at
CHSEL0 = TILT = OFFSET = 0V, HI = CHSEL1 = PWRMD = ADJ0 = ADJ1 = VCCI = VCCO = 3.3V, and CM = 1.5V. VOUTCM is defined as (OUT
+ OUT)/2 and VOUTDIFF is defined as (OUT – OUT), RL_EXT = 100Ω differential, OUT connected to TERM and OUT connected to TERM.
Output Tilt Control
ADJ = 11
0.5
10
RL = 50Ω TO GROUND
TERM AND TERMBAR ON EACH OUTPUT
|| 100Ω DIFF
DISCONNECTED
0
0.7
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
20
0
3.3
1.3
2.0
2.6
TILT PIN VOLTAGE (V)
ADJ = 11
2.0
40
1.5
OUT VOLTAGE
OUTBAR VOLTAGE
30
OUT CURRENT
OUTBAR CURRENT
1.0
20
0.5
10
0
TERM AND TERMBAR
TIED TO OUT AND
OUTBAR RESPECTIVELY
0
0.7
RL = 100Ω DIFF
EXTERNAL
VCM = 1.5V
550
TILT = 0V
ADJ = 00
125°C
85°C
25°C
–40°C
0
–110
–440
–40 –20
IIN (µA)
0
20
–550
–100 –80
40
VOUTDIFF vs IIN Over Temperature
VOUTDIFF (mV)
VOUTDIFF (V)
0.4
0.0
–0.2
–0.4
125°C
85°C
25°C
–40°C
–1.0
–100 –80
8
–60
0
20
–40 –20
IIN (µA)
0
20
40
6563 G22
20
6563 G18
VOUTDIFF vs IIN Over Temperature
TILT = 0V
ADJ = 10
–250
125°C
85°C
25°C
–40°C
0
20
0
20
40
6563 G21
600
40
6563 G23
TILT = 3.3V
ADJ = 01
300
0
–300
–600
–900
–40 –20
IIN (µA)
–40 –20
IIN (µA)
VOUTDIFF vs IIN Over Temperature
–125
–60
–60
6563 G20
TILT = 3.3V
ADJ = 00
–500
–100 –80
125°C
85°C
25°C
–40°C
–0.8
–100 –80
40
0
–375
–40 –20
IIN (µA)
–60
125
0.6
0
–0.2
–0.6
250
TILT = 0V
ADJ = 11
–40
–20
IIN (µA)
0.0
VOUTDIFF vs IIN Over Temperature
0.2
–60
0.2
–0.4
125°C
85°C
25°C
–40°C
6563 G19
0.8
–80
0.6
VOUTDIFF (mV)
–60
125°C
85°C
25°C
–40°C
0.4
110
–330
1.0
–0.8
TILT = 0V
ADJ = 01
–220
–400
–100 –80
–0.6
0.8
VOUTDIFF (V)
VOUTDIFF (mV)
VOUTDIFF (mV)
–300
300
–100
220
–100
600
400
330
0
700
500
VOUTDIFF vs IIN Over Temperature
440
100
–200
800
6563 G17
VOUTDIFF vs IIN Over Temperature
200
TILT = 3.3V
900
0
3.3
1.3
2.0
2.6
TILT PIN VOLTAGE (V)
6563 G16
300
1000
50
OUTPUT CURRENT (mA)
30
OUTPUT CURRENT (mA)
OUT VOLTAGE
OUTBAR VOLTAGE
OUT CURRENT
OUTBAR CURRENT
1.0
0
2.5
40
2.0
1.5
VIN vs IIN Over Temperature
Output Tilt Control
50
VIN (mV)
2.5
125°C
85°C
25°C
–40°C
–1200
–100 –80
–60
–40 –20
IIN (µA)
0
20
40
6563 G24
Rev. 0
For more information www.analog.com
LTC6563
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted specifications are at
CHSEL0 = TILT = OFFSET = 0V, HI = CHSEL1 = PWRMD = ADJ0 = ADJ1 = VCCI = VCCO = 3.3V, and CM = 1.5V. VOUTCM is defined as (OUT
+ OUT)/2 and VOUTDIFF is defined as (OUT – OUT), RL_EXT = 100Ω differential, OUT connected to TERM and OUT connected to TERM.
VOUTDIFF vs IIN Over Temperature
VOUTDIFF vs IIN Over Temperature
1.0
TILT = 3.3V
ADJ = 10
600
TILT = 3.3V
ADJ = 11
0.5
RT TRANSIMPEDANCE (kΩ)
400
RT Transimpedance vs IIN
VOUTDIFF (V)
–200
–400
0
–0.5
–600
125°C
85°C
25°C
–40°C
–800
–1000
–1200
–100 –80
–60
–1.0
–40 –20
IIN (µA)
0
20
40
–1.5
–100 –80
125°C
85°C
25°C
–40°C
15
10
5
35
30
RT TRANSIMPEDANCE (kΩ)
RT TRANSIMPEDANCE (kΩ)
TILT = 0V
ADJ = 01
0
20
–80
–60
–40
–20
IIN (µA)
0
125°C
85°C
25°C
–40°C
20
15
10
35
30
10
5
0
–100
–80
–60
–40
–20
IIN (µA)
0
20
6563 G31
RT TRANSIMPEDANCE (kΩ)
125°C
85°C
25°C
–40°C
0
20
6563 G27
TILT = 0V
ADJ = 11
125°C
85°C
25°C
–40°C
25
20
15
10
–80
–60
–40
–20
IIN (µA)
0
0
–100
20
–60
–40
–20
IIN (µA)
0
20
6563 G30
RT Transimpedance vs IIN
TILT = 3.3V
ADJ = 01
125°C
85°C
25°C
–40°C
20
15
10
5
0
–100
–80
6563 G29
RT Transimpedance vs IIN
TILT = 3.3V
ADJ = 00
–40
–20
IIN (µA)
5
6563 G28
25
–60
RT Transimpedance vs IIN
25
RT Transimpedance vs IIN
–80
6563 G26
TILT = 0V
ADJ = 10
0
–100
20
125°C
85°C
25°C
–40°C
5
0
–100
40
5
0
–100
RT TRANSIMPEDANCE (kΩ)
–40 –20
IIN (µA)
TILT = 0V
ADJ = 00
10
RT Transimpedance vs IIN
20
15
–60
6563 G25
RT Transimpedance vs IIN
25
125°C
85°C
25°C
–40°C
35
30
RT TRANSIMPEDANCE (kΩ)
VOUTDIFF (mV)
200
0
15
RT TRANSIMPEDANCE (kΩ)
800
TILT = 3.3V
ADJ = 10
125°C
85°C
25°C
–40°C
25
20
15
10
5
–80
–60
–40
–20
IIN (µA)
0
20
6563 G32
0
–100
–80
–60
–40
–20
IIN (µA)
0
20
6563 G33
Rev. 0
For more information www.analog.com
9
LTC6563
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted specifications are at
CHSEL0 = TILT = OFFSET = 0V, HI = CHSEL1 = PWRMD = ADJ0 = ADJ1 = VCCI = VCCO = 3.3V, and CM = 1.5V. VOUTCM is defined as (OUT
+ OUT)/2 and VOUTDIFF is defined as (OUT – OUT), RL_EXT = 100Ω differential, OUT connected to TERM and OUT connected to TERM.
–3dB Bandwidth vs Temperature
Over CIN,TOT
RT Transimpedance vs IIN
125°C
85°C
25°C
–40°C
40
35
30
25
20
15
10
800
800
CIN,TOT = 0.5pF
CIN,TOT = 2pF
CIN,TOT = 4pF
700
–3DB BANDWIDTH (MHz)
RT TRANSIMPEDANCE (kΩ)
TILT = 3.3V
45 ADJ = 11
–3DB BANDWIDTH (MHz)
50
–3dB Bandwidth vs Temperature
for Various ADJ Setttings
600
500
400
CIN,TOT = 0.5pF
700
ADJ 00
ADJ 01
ADJ 10
ADJ 11
600
500
300
5
–40
–20
IIN (µA)
0
200
–50
20
100
2.5
CIN,TOT = 0.5pF
CIN,TOT = 2pF
CIN,TOT = 4pF
ADJ 00
ADJ 01
ADJ 10
ADJ 11
2.0
PEAKING (dB)
300
1.5
1.0
0.5
–25
0
25
50
75
TEMPERATURE (°C)
100
CIN,TOT = 0.5pF
0
–50 –25
0
25
50
75
TEMPERATURE (°C)
125
100
125
6563 G38
Input-Referred Noise Density with
CIN,TOT = 2pF
Input-Referred Noise Density with
CIN,TOT = 4pF
FOR ANY ADJ SETTING
125°C
85°C
25°C
–40°C
10
1
10
100
FREQUENCY (MHz)
1000 3000
700
FOR ANY ADJ SETTING
125°C
85°C
25°C
–40°C
100
10
1
1
10
100
FREQUENCY (MHz)
1000 3000
6563 G40
10
–25
0
25
50
75
TEMPERATURE (°C)
100
6563 G41
125
6563 G36
200
Input-Referred Noise Density with
CIN,TOT = 0.5pF
FOR ANY ADJ SETTING
100
125°C
85°C
25°C
–40°C
10
1
1
10
100
FREQUENCY (MHz)
1000 3000
6563 G39
INTEGRATED INPUT-REFERRED NOISE (nARMS)
6563 G37
100
400
–50
125
Peaking vs Temperature for
Various ADJ Setttings
400
1
0
25
50
75
TEMPERATURE (°C)
6563 G35
500
300
–25
6563 G34
–3dB Bandwidth vs Temperature
(Tilted) Over CIN,TOT
200
–50
INPUT-REFERRED NOISE DENSITY (pA/SQRT (Hz))
–60
INPUT-REFERRED NOISE DENSITY (pA/SQRT (Hz))
–3DB BANDWIDTH (MHz)
600
–80
INPUT-REFERRED NOISE DENSITY (pA/SQRT (Hz))
0
–100
80
70
60
50
Integrated Input-Referred Noise
vs Bandwidth Over Temperature
CIN,TOT = 0.5pF
FOR ANY ADJ SETTING
125°C
85°C
25°C
–40°C
40
30
20
10
INTEGRATED STARTING FROM 100kHz
0
100
200
300
400
500
FREQUENCY (MHz)
600
6563 G79
Rev. 0
For more information www.analog.com
LTC6563
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted specifications are at
CHSEL0 = TILT = OFFSET = 0V, HI = CHSEL1 = PWRMD = ADJ0 = ADJ1 = VCCI = VCCO = 3.3V, and CM = 1.5V. VOUTCM is defined as (OUT
+ OUT)/2 and VOUTDIFF is defined as (OUT – OUT), RL_EXT = 100Ω differential, OUT connected to TERM and OUT connected to TERM.
125°C
85°C
25°C
–40°C
90
60
30
INTEGRATED STARTING FROM 100kHz
0
100
200
300
400
500
FREQUENCY (MHz)
600
FOR ANY ADJ SETTING
125°C
85°C
25°C
–40°C
200
150
100
50
0
100
INTEGRATED STARTING FROM 100kHz
200
300
400
FREQUENCY (MHz)
6563 G42
160
140
120
100
80
60
40
20
INTEGRATED STARTING FROM 100kHz
0
100
200
300
400
FREQUENCY (MHz)
500
600
INPUT-REFERRED NOISE DENSITY (pA/SQRT (Hz))
INTEGRATED INPUT-REFERRED NOISE (nARMS)
0.5pF
1pF
2pF
4pF
300
FOR ANY ADJ SETTING
0.5pF
1pF
2pF
4pF
100
10
1
1
10
100
FREQUENCY (MHz)
6563 G45
40
20
0
100
ANY SELECTED CHANNEL
TO ANY UNSELECTED CHANNEL
0
200
400
600
FREQUENCY (MHz)
800
1000
6563 G48
MAGNITUDE ISOLATION (dB)
MAGNITUDE ISOLATION (dB)
125°C
85°C
25°C
–40°C
60
100
10
1
1000 3000
100
1
10
100
FREQUENCY (MHz)
1000 3000
Integrated Input-Referred Noise
for various Tilt Voltages with
CIN,TOT = 0.5pF
FOR ANY ADJ SETTING
90
0V
0.5V
1V
3.3V
80
70
60
50
40
30
20
10
INTEGRATED STARTING FROM 100kHz
0
100
200
300
400
500
FREQUENCY (MHz)
600
6563 G47
Channel to Channel Isolation vs
Frequency Over Temperature
PWRMD = LOGIC HI
ADJ = 11
80
0V
0.5V
1V
3.3V
6563 G46
Channel to Channel Isolation vs
Frequency Over Temperature
100
FOR ANY ADJ SETTING
6563 G44
Input-Referred Noise Density for
various CIN,TOT
FOR ANY ADJ SETTING
180
600
500
6563 G43
Integrated Input-Referred Noise
vs Bandwidth for various CIN,TOT
200
500
INTEGRATED INPUT-REFERRED NOISE (nARMS)
120
250
INPUT-REFERRED NOISE DENSITY (pA/SQRT (Hz))
FOR ANY ADJ SETTING
Input-Referred Noise Density
for various Tilt Voltages with
CIN,TOT = 0.5pF
OMUX Isolation vs Frequency
Over Temperature
125°C
85°C
25°C
–40°C
80
60
40
20
0
110
PWRMD = LOGIC LO
ADJ = 11
ANY SELECTED CHANNEL
TO ANY UNSELECTED CHANNEL
0
200
400
600
FREQUENCY (MHz)
800
1000
6563 G49
MAGNITUDE ISOLATION (dB)
150
Integrated Input-Referred Noise
vs Bandwidth Over Temperature
CIN,TOT = 4pF
INTEGRATED INPUT-REFERRED NOISE (nARMS)
INTEGRATED INPUT-REFERRED NOISE (nARMS)
Integrated Input-Referred Noise
vs Bandwidth Over Temperature
CIN,TOT = 2pF
90
70
50
125°C
85°C
25°C
–40°C
ANY INPUT TO OUTPUT
WHEN OMUX = Logic LO
0
200
400
600
FREQUENCY (MHz)
800
1000
6563 G50
Rev. 0
For more information www.analog.com
11
LTC6563
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted specifications are at
CHSEL0 = TILT = OFFSET = 0V, HI = CHSEL1 = PWRMD = ADJ0 = ADJ1 = VCCI = VCCO = 3.3V, and CM = 1.5V. VOUTCM is defined as (OUT
+ OUT)/2 and VOUTDIFF is defined as (OUT – OUT), RL_EXT = 100Ω differential, OUT connected to TERM and OUT connected to TERM.
–40
–60
–80
0
600
1200
1800
2400
FREQUENCY (MHz)
3000
–20
15
–40
–60
VCCO COM MODE
VCCO DIFF MODE
VCCI COM MODE
VCCI DIFF MODE
–80
–100
0
600
1200
1800
2400
FREQUENCY (MHz)
500
750 1000
FREQUENCY (MHz)
1250
100
SEE FIGURE 1 FOR TEST CIRCUIT
10
MAGNITUDE K (UNITLESS)
MAGNITUDE S22 (dB)
–40
SEE FIGURE 1 FOR TEST CIRCUIT
0
250
500
750 1000
FREQUENCY (MHz)
1250
1500
5
0
–5
–10
–20
POTENTIALLY UNSTABLE
0
500
1000 1500 2000
FREQUENCY (MHz)
2500
–25
3000
SEE FIGURE 1 FOR TEST CIRCUIT
0
250
500
750 1000
FREQUENCY (MHz)
1500
S21ds (Gain) vs Frequency Over
Temperature
20
15
125°C
85°C
25°C
–40°C
10
100
1250
6563 G56
CIN,TOT = 2pF
SEE FIGURE 1 FOR TEST CIRCUIT
10
CIN,TOT = 4pF
125°C
85°C
25°C
–40°C
5
0
–5
–10
–15
UNCONDITIONALLY STABLE
1
0
–20
POTENTIALLY UNSTABLE
0
500
1000 1500 2000
FREQUENCY (MHz)
2500
6563 G57
12
125°C
85°C
25°C
–40°C
10
UNCONDITIONALLY STABLE
1k
–30
1500
CIN,TOT = 2pF
15
4k
CIN,TOT = 2pF
1250
6563 G53
Stability Factor K vs Frequency
Over Temperature
–20
500
750 1000
FREQUENCY (MHz)
6563 G55
S22dd vs Frequency Over
Temperature
–10
250
–15
0
1500
125°C
85°C
25°C
–40°C
SEE FIGURE 1 FOR TEST CIRCUIT
0
S21ds (Gain) vs Frequency Over
Temperature
125°C
85°C
25°C
–40°C
6563 G54
0
–20
3000
CIN,TOT = 0.5pF
1
SEE FIGURE 1 FOR TEST CIRCUIT
250
125°C
85°C
25°C
–40°C
20
1k
–30
0
–5
–15
4k
CIN,TOT = 0.5pF
–20
–40
0
Stability Factor K vs Frequency
Over Temperature
MAGNITUDE K (UNITLESS)
MAGNITUDE S22 (dB)
–10
5
6563 G52
S22dd vs Frequency Over
Temperature
125°C
85°C
25°C
–40°C
10
–10
DECOUPLING CAP ONLY ON VCCI, AND VCCO
6563 G51
0
CIN,TOT = 0.5pF
20
MAGNITUDE S21 (dB)
–100
LC FILTER ON VCCI, AND VCCO
25
MAGNITUDE S21 (dB)
–20
0
MAGNITUDE S21 (dB)
VCCO COM MODE
VCCO DIFF MODE
VCCI COM MODE
VCCI DIFF MODE
POWER SUPPLY REJECTION RATION (dB)
POWER SUPPLY REJECTION RATION (dB)
0
S21ds (Gain) vs Frequency Over
Temperature
PSRR Out to VCCI, VCCO
PSRR Out to VCCI, VCCO
3000
6563 G58
–25
SEE FIGURE 1 FOR TEST CIRCUIT
0
250
500
750 1000
FREQUENCY (MHz)
1250
1500
6563 G59
Rev. 0
For more information www.analog.com
LTC6563
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted specifications are at
CHSEL0 = TILT = OFFSET = 0V, HI = CHSEL1 = PWRMD = ADJ0 = ADJ1 = VCCI = VCCO = 3.3V, and CM = 1.5V. VOUTCM is defined as (OUT
+ OUT)/2 and VOUTDIFF is defined as (OUT – OUT), RL_EXT = 100Ω differential, OUT connected to TERM and OUT connected to TERM.
S22dd vs Frequency Over
Temperature
4k
125°C
85°C
25°C
–40°C
–20
–30
–40
250
500
750 1000
FREQUENCY (MHz)
100
SEE FIGURE 1 FOR TEST CIRCUIT
10
1250
TILT = 3.3V
0
500
1000 1500 2000
FREQUENCY (MHz)
–0.2
3000
TIME (1ns/DIV)
6563 G62
Channel Switching Time
PWRMD = LOGIC HI
IIN
VOLTAGE (0.25V/DIV)
VOUTCM
–0.3
–0.6
CH SWITCHING
VOUTDIFF
0
0
CH SWITCHING
VOUTCM
0
–0.9
VOUTDIFF
6563 G64
20ns/DIV
TIME (1ns/DIV)
6563 G65
20ns/DIV
6563 G63
OMUX Switching Time
OMUX Switching Time
PWRMD = LOGIC LO
IIN
VOUTDIFF
25ns/DIV
0
OMUX
VOUTCM
0V
6563 G66
VOUTDIFF
25ns/DIV
INPUT CURRENT (10µA/DIV)
0V
VOUTCM
INPUT CURRENT (10µA/DIV)
OMUX
0
PWRMD = LOGIC HI
IIN
VOLTAGE (0.5V/DIV)
–1.2
PWRMD = LOGIC LO
IIN
0
0.0
VOLTAGE (0.5V/DIV)
VOLTAGE (V)
0.4
INPUT CURRENT (10µA/DIV)
0.3
2500
INPUT CURRENT (10µA/DIV)
0.6
0.6
Channel Switching Time
22µA
66µA
83µA
109µA
256µA
427µA
1.2mA
2.2mA
0.9
0.8
6563 G61
Pulse Response for Various IIN
CIN,TOT = 1pF, 2ns Pulse Width
1.2
1.0
0
POTENTIALLY UNSTABLE
6563 G60
1.5
21µA
65µA
87µA
109µA
427µA
1.2mA
2.2mA
0.2
0
1500
TILT = 0V
1.2
UNCONDITIONALLY STABLE
1
SEE FIGURE 1 FOR TEST CIRCUIT
0
125°C
85°C
25°C
–40°C
1k
Pulse Response for Various IIN
CIN,TOT = 1pF, 2ns Pulse Width
1.4
VOLTAGE (0.5V/DIV)
–10
1.6
CIN,TOT = 4pF
VOLTAGE (V)
CIN,TOT = 4pF
MAGNITUDE K (UNITLESS)
MAGNITUDE S22 (dB)
0
Stability Factor K vs Frequency
Over Temperature
6563 G67
Rev. 0
For more information www.analog.com
13
LTC6563
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted specifications are at
CHSEL0 = TILT = OFFSET = 0V, HI = CHSEL1 = PWRMD = ADJ0 = ADJ1 = VCCI = VCCO = 3.3V, and CM = 1.5V. VOUTCM is defined as (OUT
+ OUT)/2 and VOUTDIFF is defined as (OUT – OUT), RL_EXT = 100Ω differential, OUT connected to TERM and OUT connected to TERM.
Pulse Stretching vs Input Current
40
FREQUENCY OF OCCURANCE (%)
2.5
2.0
1.5
1.0
125°C
85°C
25°C
–40°C
0.5
0
0.01
0.1
1
INPUT CURRENT (mA)
400
41500 UNITS FROM 3
35 WAFER LOTS
300
30
25
20
15
0
Output Response to VOFFSET
Pin Step
VOFFSET
500
200
100
400
200
300
200
100
100
0
200ns/DIV
6563 G71
–100
ICANCEL = 0µA
ICANCEL = 20µA
ICANCEL = 40µA
ICANCEL = 100µA
ICANCEL = 250µA
100
FOR ANY ADJ SETTING
10
1
14
10
100
FREQUENCY (MHz)
1000 3000
6563 G74
6563 G72
200ns/DIV
–100
Integrated Input-Referred
Noise for Various Input Current
Cancellation with CIN,TOT = 0.5pF
INTEGRATED INPUT-REFERRED NOISE (nARMS)
Input-Referred Noise Density for
Various Input Current Cancellation
with CIN,TOT = 0.5pF
500
0
225
FOR ANY ADJ SETTING
200
ICANCEL = 0µA
ICANCEL = 20µA
ICANCEL = 40µA
ICANCEL = 100µA
ICANCEL = 250µA
175
150
125
100
75
50
25
0
100
INTEGRATED STARTING FROM 100kHz
200
300
400
FREQUENCY (MHz)
500
600
6563 G75
6563 G73
200ns/DIV
Output-Referred Noise Density for
Various Input Current Cancellation
with CIN,TOT = 0.5pF
OUTPUT-REFERRED NOISE DENSITY (nV/√Hz)
–100
VOFFSET
500
300
0
VOUTDIFF
600
VOLTAGE (mV)
VOLTAGE (mV)
VOLTAGE (mV)
700
VOFFSET
VOUTDIFF
400
300
6563 G70
200ns/DIV
Output Response to VOFFSET
Pin Step
600
VOUTDIFF
400
INPUT-REFERRED NOISE DENSITY (pA/√Hz)
–100
6563 G69
Output Response to VOFFSET
Pin Step
1
100
5
6563 G68
500
200
10
0
–50 –40 –30 –20 –10 0 10 20 30 40 50
DIFF OUTPUT OFFSET (mV)
5
VOFFSET
VOUTDIFF
VOLTAGE (mV)
3.0
PULSE STRETCHING (nS)
Output Response to VOFFSET
Pin Step
Output Offset Histogram
1k
ADJ = 11
ICANCEL = 0µA
ICANCEL = 20µA
ICANCEL = 40µA
ICANCEL = 100µA
ICANCEL = 250µA
100
10
1
10
100
FREQUENCY (MHz)
1000 3000
6563 G76
Rev. 0
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LTC6563
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted specifications are at
CHSEL0 = TILT = OFFSET = 0V, HI = CHSEL1 = PWRMD = ADJ0 = ADJ1 = VCCI = VCCO = 3.3V, and CM = 1.5V. VOUTCM is defined as (OUT
+ OUT)/2 and VOUTDIFF is defined as (OUT – OUT), RL_EXT = 100Ω differential, OUT connected to TERM and OUT connected to TERM.
Low Side Clamp vs HI Pin Voltage
0.4
0.3
1.8
LIMITED BY OUTPUT
LOAD CURRENT
0.2
1.7
125°C
85°C
25°C
–40°C
1.6
1.5
1.5
1.6
RL_EXT = 100Ω 0.1
ADJ = 11
VCM = 1.5V
0
1.7 1.8 1.9 2.0 2.1 2.2 2.3
HI PIN VOLTAGE (V)
SINGLE-ENDED OUTPUT SWING LIMIT (V)
1.9
1.5
0
DOWNWARD SWING CLAMP = 2VCM – VHI
RL_EXT = 100Ω
1.4 ADJ = 11
VCM = 1.5V
–0.1
125°C
85°C
25°C –0.2
–40°C
1.3
LIMITED BY OUTPUT
LOAD CURRENT
1.2
–0.3
–0.4
1.1
1.0
1.5
1.6
1.7
6563 G77
1.8 1.9 2.0 2.1
HI PIN VOLTAGE (V)
2.2
SWING LIMIT RELATIVE TO VCM (V)
0.5
SWING LIMIT RELATIVE TO VCM (V)
SINGLE-ENDED OUTPUT SWING LIMIT (V)
High Side Clamp vs HI Pin Voltage
2.0
–0.5
2.3
6563 G78
V2
+–
VCC
VCC
V
OFFSET
TILT
OMUX
PWRMD
BIAS
CTRL
2k
IN1
R
2k
IN2
V1
2k
IN3
V
2k
IN4
OUT
TIA
CM
TIA
OUTPUT
STAGE
4:1
MUX
+
–
TERM
CM CONROL
LOOP
50Ω
50Ω
50Ω
R
50Ω
TERM
TIA
OUT
OUTPUT
CLAMPS
TIA
×1
CHSEL1
CHSEL0
IO CTRL
ADJ1
ADJ0
VCC
HI
VCC
–
LO
+
×2
CM
6563 F01
1.5V
0.1µF
Figure 1. Electrical Characterization Test Circuit
Rev. 0
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15
LTC6563
TYPICAL PERFORMANCE CHARACTERISTICS
OUT
CIN,TOT
0.5pF,
2pF,
or
4pF
R1
2k
INx
TERM
LTC6563
TERM
OUT
C2
100pF
PORT1
R2
50Ω
PORT3
S-PARAMETER MEASUREMENT
AC-COUPLED 50Ω PORTS
PORT2
PORT4
R3
50Ω
6563 F02
Figure 2. S-Parameters Test Circuit
IO CTRL
TILT
IO CTRL
OUTPUT SECTION
OMUX
PWRMD
LTC6563
BIAS
CTRL
R
CM
OUTPUT
STAGE
+
–
OUT
TERM
CM CONROL
LOOP
75Ω
50Ω
HMCAD1511
50Ω
TERM
R
75Ω
VCM
OUT
OUTPUT
CLAMPS
×1
ADJ1
ADJ0
HI
HI CTRL
VCC
–
LO
+
×2
CM
0.1µF
6563 F03
Figure 3. Driving HMCAD1511 (ADJ11, Tilt = 3.3V, CM = 0.9V, FS = 2.4VP-P)
16
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LTC6563
PIN FUNCTIONS
GND (Pins 1, 3, 18, 20, Exposed Pad Pin 25): Negative
Power Supply. Normally tied to ground. All GND pins and
the exposed pad must be tied to the same voltage. The
exposed pad (pin 25) should have multiple via holes to
the underlying ground plane for low inductance and good
heat transfer.
IN4, IN1, IN2, IN3 (Pin 2, Pin 19, Pin 21, Pin 24,): Input
pins for the transimpedance amplifier for channels 4, 1, 2,
and 3 respectively. The active channel is internally biased
to 0.8V. See the Applications Information section for specific recommendation.
PWRMD (Pin 4): Power mode is a CMOS input for controlling the power consumption. The PWRMD pin has a
208k internal pull-up resistor to VCCI. Default value is 3.3V.
VCCI (Pin 5): Positive power supply for the input
stages. Typically, 3.3V. A series ferrite bead such as the
MPZ1005A331ETD25 should be used and bypass capacitor of 680pF and 0.1µF should be placed as close to the
part as possible between VCCI and ground.
OMUX (Pin 6): Output MUX is a CMOS input for controlling the output multiplexing function. The OMUX pin
has internal 208k pull-up resistor to VCCI. Default value
is 3.3V.
CM (Pin 7): Output Common Mode Reference Voltage.
The voltage on this pin sets the output common mode
voltage level. On a 3.3V supply, the CM pin floats to a
default 0.9V. The CM pin has an input impedance of
16.3kΩ. The CM pin should be bypassed with a highquality ceramic capacitor of at least 0.01µF.
HI (Pin 8): High Side Clamp Voltage. The voltage applied
to the HI pin sets the upper voltage limit to OUT and OUT
pins. The HI voltage also limits the lower voltage swing on
both output pins to 2VCM – HI, for symmetrical clamping
around the CM voltage. On a 3.3V supply, the HI pin will
float to a default 1.8V. The HI pin has an input impedance
of 13.6kΩ. The HI pin should be bypassed with a highquality ceramic capacitor of at least 0.01µF.
OUT, OUT (Pin 9, Pin 12): Differential Output Pins. For
voltage mode output, connect OUT to TERM and OUT to
TERM. For current mode output or when using external
load resistors, float TERM and TERM.
TERM, TERM (Pin 10, Pin 11): Internal Termination.
These pins have 50Ω load resistors coupled to GND and
are intended to connect to the differential output pins.
CHSEL1, CHSEL0 (Pin 13, Pin 15): MSB and LSB for
Channel Selection. These pins are CMOS inputs with internal 218k pull-down resistors to GND.
VCCO (Pin 14): Positive power supply for the output
stage. Typically, 3.3V. VCCO can be tied to VCCI for single supply operation. A series ferrite bead such as the
MPZ1005A331ETD25 should be used and bypass capacitors of 680pF and 0.1µF should be placed as close as
possible between VCCO and ground.
OFFSET (Pin 16): Input Offset Adjust. This pin accepts a
voltage input that controls current sources on each input
pin. These current sources can be used to cancel DC currents flowing into the detector. The OFFSET pin has an
internal pull-down resistor to GND.
TILT (Pin 17): Output Differential Offset. The voltage on
this pin controls the outputs’ differential offset. The TILT
pin has an internal 22.7k pull-down resistor to GND.
ADJ0, ADJ1 (Pin 22, Pin 23): LSB and MSB for output
gain and current adjusts. The adjust pins set the output
stage quiescent current and current gain. See Applications
Information section to optimize the ADC interface. These
pins are CMOS inputs with internal 218k pull-down resistors to GND.
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17
LTC6563
BLOCK DIAGRAM
16
17
OFFSET
6
TILT
4
OMUX
PWRMD
BIAS
CTRL
19
IN1
TIA
R
21
24
2
IN2
IN3
IN4
OUT
TIA
CM
OUTPUT
STAGE
4:1
MUX
+
–
TERM
CM CONROL
LOOP
11
50Ω
50Ω
R
TERM
TIA
OUT
10
9
OUTPUT
CLAMPS
TIA
×1
CHSEL1
13
12
CHSEL0
15
ADJ1
23
ADJ0
22
–
LO
+
×2
HI
CM
8
7
LTC6563 BD
OPERATION
The LTC6563 is a four channel transimpedance amplifier with an integrated 4-to-1 multiplexer and ADC driver
stage. Each of the transimpedance amplifiers converts
an input current to an output voltage. The integrated
4:1 multiplexer simplifies the system design while saving space and power. In addition, output multiplexing is
possible by using the OMUX pin. This allows multiple
4-channel LTC6563 devices to be combined. 8, 12, 16
… 32 input channels are easily multiplexed into a single
differential output.
The LTC6563 is optimized to drive high speed differential
input analog-to-digital converters (ADCs). OUT and OUT
have single-ended swings from as low as about 180mV
to about VCCO – 1V. The LTC6563 provides four modes of
output drive for matching input swing of high-speed ADCs.
The tilt feature allows the output stage to offset to take
advantage of the full differential input range of the ADCs.
The outputs have programmable clamps that limit the
18
output swing in saturation events. These clamps provide
protection to the front end of the ADC. The HI pin sets
the maximum swing, while a symmetric minimum swing
limit is set up internally.
In typical LIDAR applications, the LTC6563 amplifies the
output current of an APD. APD are biased near breakdown
to achieve high current gain. Under intense optical illumination, they can conduct large currents, often in excess
of 1A. The LTC6563 survives and quickly recovers from
large overload currents of this magnitude. During recover,
any TIA is blinded from subsequent pulses. The LTC6563
recovers from 1mA saturation events in less than 2.5ns
without phase reversal, minimizing this form of data loss.
Ambient light is problematic for LIDAR receiver chains.
The DC current can easily saturate the linear range of any
TIA. The LTC6563 provides a control for DC cancelation to
the inputs and can cancel up to 200μA of DC current. The
DC cancelation is designed to minimizing additive noise.
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LTC6563
APPLICATIONS INFORMATION
Output Offset and Current Control
The output stage of the LTC6563 has many options. The
ADJ1 and ADJ0 pins provide four options for the output
current drive. The output voltage swing is dependent on
the adjust setting, the external differential termination
resistor, and the Tilt input. The purpose of the Tilt input is
to offset the DC output voltages, thereby increasing the
full output swing of the TIA for unipolar inputs. Output
TILT is essential for the ADC as the input from the photodetector is unipolar. To maximize the input swing of
the ADC, the DC value of OUT is offset low while the DC
value of OUT is offset high. This allows the LTC6563 to
maximize the full dynamic range of the ADC. These pins
should be connected to low noise inputs.
LTC6563 transimpedance gain (RT) consists of the overall gain from the multi-stages involved in producing the
output for a given input current. The output is differential
and ½ RT is achieved if only one of the outputs is utilized.
It is possible to change the transimpedance gain (RT)
by changing RL_EXT as shown in Table 1, and Table 2.
Also, since the ADJ pins respond in less than 100ns,
these pins can be used for on the fly gain switching if the
application needs that. An example would be to reduce
the TIA gain if an overly strong signal is received by the
LTC6563. It’s important to note the following regarding
gain adjustment:
• The linear input current range (40µA with no Tilt, 90µA
with full Tilt) is not affected by these changes.
• RLDIFF refers to the total load seen by the differential
output(s) whereas RL_EXT is the external differential
load. Refer to Figure 17 to Figure 19 to see examples
of various external single-ended load (50Ω, 75Ω, and
100Ω) illustrated.
Table 1. Output Stage when Tilt Pin = 0V, OUT Connected to TERM and OUT Connected to TERM1
IIN (µA)
ADJ1
ADJ0
OUT (mA)
OUTBAR (mA)
RT (Ω)
RL_EXT = 100Ω DIFF
RT (Ω)
RL_EXT = 200Ω DIFF
RT (Ω)
RL_EXT = OPEN
0
0
0
7
7
5.55k
7.4k
11.1k
0
1
14
14
11.1k
14.8k
22.2k
1
0
21
21
16.65k
22.2k
33.3k
1
1
28
28
22.2k
29.6k
44.4k
0
0
12
2
5.55k
7.4k
11.1k
0
1
24
4
11.1k
14.8k
22.2k
1
0
36
6
16.65k
22.2k
33.3k
1
1
48
8
22.2k
29.6k
44.4k
45
1 Output voltage compliance to be observed at higher R
L_EXT and higher ADJ settings.
Table 2. Output Stage when Tilt Pin = VCC, OUT Connected to TERM and OUT Connected to TERM1
IIN (µA)
ADJ1
ADJ0
OUT (mA)
OUTBAR (mA)
RT (Ω)
RL_EXT = 100Ω DIFF
RT (Ω)
RL_EXT = 200Ω DIFF
RT (Ω)
RL_EXT = OPEN
0
0
0
2
12
5.55k
7.4k
11.1k
0
1
4
24
11.1k
14.8k
22.2k
1
0
6
36
16.65k
22.2k
33.3k
1
1
8
48
22.2k
29.6k
44.4k
0
0
12
2
5.55k
7.4k
11.1k
0
1
24
4
11.1k
14.8k
22.2k
1
0
36
6
16.65k
22.2k
33.3k
1
1
48
8
22.2k
29.6k
44.4k
90
1 Output voltage compliance to be observed at higher R
L_EXT and higher ADJ settings.
Rev. 0
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19
LTC6563
APPLICATIONS INFORMATION
• Increasing RLDIFF slightly reduces the signal bandwidth.
• Output voltage compliance (VCOMPLIANCE) to be
observed relative to RLDIFF , ADJ settings, and CM voltage . Here is an example where output voltage compliance is violated:
RLDIFF = 100Ω, Tilt = VCC, ADJ1 = 1, ADJ0 = 0,
CM = 1.7V, IIN = 90µA
Output Voltage (max) =
IOUT – IOUTBAR RLDIFF
•
2
2
VCM +
Output Voltage (max) =
Coupling the TIA Input – AC vs DC
Although the LTC6563 can AC-couple to the detector, best
performance is achieved when DC-coupled to a negatively
biased APD. DC-coupling reduces component count while
allowing a DC current path from the APD. The LTC6563
OFFSET feature is designed to cancel DC currents. The
maximum performance for switching speeds and saturation recovery occurs in this DC-coupled configuration.
When AC-coupling to the TIA input, RB, is needed to
establish a bias point for the detector. It is worth noting
that RB is a parallel path with the TIA for the APD current
to flow through and it will impact the effective signal chain
output gain.
Referring to Table 2 to read output current values:
1.7V +
appropriate one based upon the application while minimizing power dissipation.
36mA – 6mA 100Ω
•
= 2.45V!
2
2
The maximum output voltage must remain below VCCO
– 1V (~2.3V) to comply with the VCOMPLIANCE rating.
Possible remedies are reducing output current(s) by
using lower power ADJ settings, reducing the input APD
current, reducing the differential load, or reducing the
CM voltage.
Power Considerations
This value of the biasing resistor and AC-coupling capacitor, CAC, can potentially create a long time-constant. CAC is
chosen based on the reactance at the frequency of interest. However, RB ideally should be large to avoid stealing
AC-COUPLED TIA
RB C
AC
APD
The LTC6563 has many power modes of operation. The
state of the PWRMD, OMUX and ADJ pins will dictate
the amount of current the LTC6563 will draw. Multiple
power modes are offered to allow the user to select the
DC-COUPLED TIA
APD
–HV
–HV
6563 F04
Figure 4. AC-Coupled Detector Circuit
Table 3. LTC6563 Power Dissipation Modes. X = Don’t Care
PWRMD
OMUX ADJ1
ADJ0
IVCCI (mA)
IVCCO (mA) ITOTAL (mA) DESCRIPTION
0
0
X
X
4.5
0.1
4.6
LTC6563 shutdown.
0
1
0
0
21
24.5
45.5
0
1
0
1
21
38
59
LTC6563 enabled, non-selected inputs powered down, CM pin control
disabled. This setting appropriate for a Responder device in a multi-chip/
multi-channel application.
0
1
1
0
21
51.5
72.5
0
1
1
1
21
64.5
85.5
1
0
X
X
35
0.1
35.1
LTC6563 deselected (outputs stage off), non-selected inputs powered up.
LTC6563 enabled, non-selected inputs powered up, CM pin control active
in setting output CM voltage. This setting appropriate for a Controller
device in a multi-chip/multi-channel application.
1
1
0
0
34
24.5
58.5
1
1
0
1
34
38
72
1
1
1
0
34
51.5
85.5
1
1
1
1
34
64.5
98.5
20
Rev. 0
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LTC6563
APPLICATIONS INFORMATION
current from the TIA path from APD signal. On one hand
large RB causes large RC time constants, while low RB
reduces the effective gain of the APD.
Another negative impact of this RC network is in the case
for saturation events. When a large signal is received from
the APD, this event will charge CAC. This will negatively
move the input bias of the TIAs and change the TIAs input
impedance to transimpedance 14kΩ. This 14kΩ coupled
with RB and CAC time constant will add the saturation
recover time. Practical values of 100pF CAC and RB of
2.2kΩ will have large saturation recovery times >1µs with
>50mA input signals. This effectively blinds the signal
chain for the next input signal.
Channel Selection
There are four TIA inputs to the LTC6563. The active channel is selected using two channel selection bits CHSEL0
and CHSEL1. When a channel is changed and PWRMD is
high, an output glitch takes
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