LTC6812-1
15-Cell Battery Stack Monitor
with Daisy Chain Interface
DESCRIPTION
FEATURES
Measures Up to 15 Battery Cells in Series
n 2.2mV Maximum Total Measurement Error
n Stackable Architecture for High Voltage Systems
n Built-In isoSPI™ Interface
n 1Mb Isolated Serial Communications
n Uses a Single Twisted Pair, Up to 100 Meters
n Low EMI Susceptibility and Emissions
n Bidirectional for Broken Wire Protection
n 245µs to Measure All Cells in a System
n Synchronized Voltage and Current Measurement
n 16-Bit Delta-Sigma ADC with Programmable
Noise Filter
n Engineered for ISO 26262-Compliant Systems
n Passive Cell Balancing Up to 200mA (Max) with
Programmable Pulse‑Width Modulation
n 9 General Purpose Digital I/O or Analog Inputs
n Temperature or Other Sensor Inputs
n Configurable as an I2C or SPI Master
n 6µA Sleep Mode Supply Current
n 64-Lead eLQFP Package
n AEC-Q100 Qualified for Automotive Applications
n
APPLICATIONS
The LTC®6812-1 is a multicell battery stack monitor that
measures up to 15 series connected battery cells with
a total measurement error of less than 2.2mV. The cell
measurement range of 0V to 5V makes the LTC6812-1
suitable for most battery chemistries. All 15 cells can be
measured in 245µs, and lower data acquisition rates can
be selected for high noise reduction.
Multiple LTC6812-1 devices can be connected in series,
permitting simultaneous cell monitoring of long, high
voltage battery strings. Each LTC6812-1 has an isoSPI
interface for high speed, RF immune, long distance communications. Multiple devices are connected in a daisy
chain with one host processor connection for all devices.
This daisy chain can be operated bidirectionally, ensuring
communication integrity, even in the event of a fault along
the communication path.
The LTC6812-1 can be powered directly from the battery
stack or from an isolated supply. The LTC6812-1 includes
passive balancing for each cell, with individual PWM duty
cycle control for each cell. Other features include an onboard 5V regulator, nine general purpose I/O lines and a
sleep mode, where current consumption is reduced to 6µA.
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. patents, including 8908779, 9182428, 9270133.
Electric and Hybrid Electric Vehicles
n Backup Battery Systems
n Grid Energy Storage
n High Power Portable Equipment
n
TYPICAL APPLICATION
Cell 15 Measurement Error
vs Temperature
15-Cell Monitor and Balance IC
2.0
CELL 15
CELL 14
CELL 2
CELL 1
+
+
+
•
•
•
ISOLATED
DATA WITH
WIRE BREAK
PROTECTION
LTC6812-1
+
MEASUREMENT ERROR (mV)
1.5
CELL VOLTAGE = 3.3V
5 TYPICAL UNITS
1.0
0.5
0
–0.5
–1.0
–1.5
68121 TA01a
–2.0
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
68121 TA01b
Rev. B
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1
LTC6812-1
TABLE OF CONTENTS
Features...................................................... 1
Applications................................................. 1
Typical Application ......................................... 1
Description.................................................. 1
Absolute Maximum Ratings............................... 3
Order Information........................................... 3
Pin Configuration........................................... 3
Electrical Characteristics.................................. 4
Typical Performance Characteristics.................... 9
Pin Functions............................................... 15
Block Diagram.............................................. 16
Improvements from the LTC6811-1..................... 17
Operation................................................... 18
State Diagram.......................................................... 18
Core LTC6812-1 State Descriptions......................... 18
isoSPI State Descriptions........................................ 19
Power Consumption................................................ 19
ADC Operation.........................................................20
Data Acquisition System Diagnostics......................25
Watchdog and Discharge Timer............................... 32
Reset Behaviors.......................................................34
S Pin Pulse-Width Modulation for Cell Balancing....35
Discharge Timer Monitor.........................................35
I2C/SPI Master on LTC6812-1 Using GPIOs.............36
S Pin Pulsing Using the S Pin Control Settings....... 39
S Pin Muting............................................................ 41
Serial Interface Overview......................................... 41
4-Wire Serial Peripheral Interface (SPI) Physical
Layer........................................................................ 42
2-Wire Isolated Interface (isoSPI) Physical Layer.... 42
Data Link Layer........................................................ 52
Network Layer......................................................... 52
Applications Information................................. 69
Providing DC Power.................................................69
Internal Protection and Filtering............................... 70
Cell Balancing.......................................................... 73
Discharge Control During Cell Measurements......... 74
Digital Communications...........................................77
Enhanced Applications.............................................85
Reading External Temperature Probes..................... 87
Package Description...................................... 88
Revision History........................................... 89
Typical Application........................................ 90
Related Parts............................................... 90
Rev. B
2
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LTC6812-1
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
IPB
IMB
SCK (IPA)*
CSB (IMA)*
V–
V–**
ICMP
IBIAS
WDT
ISOMD
SDO (NC)*
SDI (NC)*
DTEN
VREF1
VREF2
DRIVE
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
65
V–
VREG
GPIO9
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
C0
S1
C1
S2
C2
S3
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
V+
NC
NC
C15
S15
C14
S14
C13
S13
C12
S12
C11
S11
NC
NC
C10
S10
C9
S9
C8
S8
C7
S7
C6
S6
NC
NC
C5
S5
C4
S4
C3
Total Supply Voltage
V+ to V–.............................................................93.75V
Supply Voltage (Relative to C10)
V+ to C10...............................................................50V
Input Voltage (Relative to V–)
C0............................................................. –0.3V to 6V
C15......................... –0.3V to MIN (V+ + 5.5V, 93.75V)
C(n), S(n)........................–0.3V to MIN (8 • n, 93.75V)
IPA, IMA, IPB, IMB............ –0.3V to VREG + 0.3V, ≤ 6V
DRIVE....................................................... –0.3V to 7V
All Other Pins............................................ –0.3V to 6V
Voltage Between Inputs
C(n) to C(n–1), S(n) to C(n–1)................... –0.3V to 8V
C13 to C10.............................................. –0.3V to 21V
C8 to C5.................................................. –0.3V to 21V
C3 to C0.................................................. –0.3V to 21V
Current In/Out of Pins
All Pins Except VREG, IPA, IMA, IPB, IMB,
C(n), S(n)............................................................... 10mA
IPA, IMA, IPB, IMB..............................................30mA
Specified Junction Temperature Range
LTC6812I-1...........................................–40°C to 85°C
LTC6812H-1........................................ –40°C to 125°C
Junction Temperature............................................ 150°C
Storage Temperature Range................... –65°C to 150°C
Device HBM ESD Classification Level 1C
Device CDM ESD Classification Level C5
LWE PACKAGE
64-LEAD (10mm × 10mm) PLASTIC eLQFP
TJMAX = 150°C, θJA = 17°C/W, θJC = 2.5°C/W
EXPOSED PAD (PIN 65) IS V –, MUST BE SOLDERED TO PCB
*THE FUNCTION OF THESE PINS DEPENDS ON THE CONNECTION OF ISOMD:
ISOMD TIED TO V–: CSB, SCK, SDI, SDO
ISOMD TIED TO VREG: IPA, IMA, NC, NC
**THIS PIN MUST BE CONNECTED TO V–
ORDER INFORMATION
AUTOMOTIVE PRODUCTS**
TRAY (160PC)
TAPE AND REEL (1500PC)
PART MARKING*
PACKAGE DESCRIPTION
MSL RATING
SPECIFIED JUNCTION
TEMPERATURE
RANGE
LTC6812ILWE-1#3ZZPBF
LTC6812ILWE-1#3ZZTRPBF
LTC6812LWE-1
64-Lead Plastic eLQFP
3
–40°C to 85°C
LTC6812HLWE-1#3ZZPBF
LTC6812HLWE-1#3ZZTRPBF
LTC6812LWE-1
64-Lead Plastic eLQFP
3
–40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #3ZZ suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your
local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
these models.
Rev. B
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3
LTC6812-1
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full specified
temperature range, otherwise specifications are at TA = 25°C. The test conditions are V+ = 49.5V, VREG = 5.0V unless otherwise noted.
The ISOMD pin is tied to the V– pin, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ADC DC Specifications
Measurement Resolution
0.1
mV/Bit
0.1
mV
ADC Offset Voltage
(Note 2)
ADC Gain Error
(Note 2)
0.01
%
Total Measurement Error (TME) in
Normal Mode
C(n) to C(n–1), GPIO(n) to V– = 0
±0.2
mV
C(n) to C(n–1) = 2.0
±1.6
mV
l
±1.8
mV
C(n) to C(n–1), GPIO(n) to V– = 2.0, LTC6812H l
±2.0
mV
C(n) to C(n–1), GPIO(n) to V– = 2.0, LTC6812I
C(n) to C(n–1) = 3.3
±2.2
mV
l
±3.0
mV
C(n) to C(n–1), GPIO(n) to V– = 3.3, LTC6812H l
±3.3
mV
C(n) to C(n–1) = 4.2
±2.8
mV
±3.8
mV
±4.2
mV
C(n) to C(n–1), GPIO(n) to V– = 3.3, LTC6812I
C(n) to C(n–1), GPIO(n) to V– = 4.2, LTC6812I
l
C(n) to C(n–1), GPIO(n) to V– = 4.2, LTC6812H
l
C(n) to C(n–1), GPIO(n) to V– = 5.0
Sum of All Cells
±1
±0.05
l
Internal Temperature, T = Maximum Specified
Temperature
Total Measurement Error (TME) in
Filtered Mode
mV
±0.35
±5
%
°C
VREG Pin
l
–1
–0.15
0
%
VREF2 Pin
l
–0.05
0.05
0.20
%
Digital Supply Voltage, VREGD
l
–0.5
0.5
1.5
%
C(n) to C(n–1), GPIO(n) to V– = 0
±0.1
C(n) to C(n–1) = 2.0
C(n) to C(n–1), GPIO(n) to V– = 2.0, LTC6812I
mV
±1.6
mV
l
±1.8
mV
C(n) to C(n–1), GPIO(n) to V– = 2.0, LTC6812H l
±2.0
mV
C(n) to C(n–1) = 3.3
±2.2
mV
l
±3.0
mV
C(n) to C(n–1), GPIO(n) to V– = 3.3, LTC6812H l
±3.3
mV
C(n) to C(n–1), GPIO(n) to V– = 3.3, LTC6812I
C(n) to C(n–1) = 4.2
±2.8
mV
l
±3.8
mV
C(n) to C(n–1), GPIO(n) to V– = 4.2, LTC6812H l
±4.2
mV
C(n) to C(n–1), GPIO(n) to V– = 4.2, LTC6812I
C(n) to C(n–1), GPIO(n) to V– = 5.0
Sum of All Cells
±1
±0.05
l
Internal Temperature, T = Maximum Specified
Temperature
mV
±0.35
±5
%
°C
VREG Pin
l
–1
–0.15
0
%
VREF2 Pin
l
–0.05
0.05
0.20
%
Digital Supply Voltage, VREGD
l
–0.5
0.8
1.5
%
Rev. B
4
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LTC6812-1
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full specified
temperature range, otherwise specifications are at TA = 25°C. The test conditions are V+ = 49.5V, VREG = 5.0V unless otherwise noted.
The ISOMD pin is tied to the V– pin, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
Total Measurement Error (TME) in
Fast Mode
C(n) to C(n–1), GPIO(n) to V– = 0
MIN
UNITS
mV
C(n) to C(n–1), GPIO(n) to V– = 2.0
l
±4
mV
C(n) to C(n–1), GPIO(n) to V– = 3.3
l
±6
mV
C(n) to C(n–1), GPIO(n) to V– = 4.2
l
±8.3
mV
Sum of All Cells
±10
±0.15
l
Internal Temperature, T = Maximum Specified
Temperature
IL
MAX
±2
C(n) to C(n–1), GPIO(n) to V– = 5.0
Input Range
TYP
mV
±0.5
±5
%
°C
VREG Pin
l
–1.5
–0.15
1
%
VREF2 Pin
l
–0.18
0.05
0.32
%
Digital Supply Voltage, VREGD
l
–2.5
–0.4
2
%
C(n) n = 1 to 15
l
C(n–1)
C(n–1) + 5
V
C0
l
0
1
V
GPIO(n) n = 1 to 9
l
0
5
V
nA
Input Leakage Current When Inputs Are
Not Being Measured
C(n) n = 0 to 15
l
10
±250
GPIO(n) n = 1 to 9
l
10
±250
Input Current When Inputs Are Being
Measured (State: Core = MEASURE)
C(n) n = 0 to 15
±1
GPIO(n) n = 1 to 9
±1
Input Current During Open Wire
Detection
nA
μA
μA
l
70
100
130
μA
l
3.0
3.15
3.3
V
Voltage Reference Specifications
VREF1
VREF2
1st Reference Voltage
VREF1 Pin, No Load
1st Reference Voltage TC
VREF1 Pin, No Load
3
ppm/°C
1st Reference Voltage Thermal
Hysteresis
VREF1 Pin, No Load
20
ppm
1st Reference Voltage Long Term Drift
VREF1 Pin, No Load
20
ppm/√khr
2nd Reference Voltage
VREF2 Pin, No Load
VREF2
Pin, 5k Load to V–
l
2.993
l
2.992
3
3.007
3
3.008
V
V
2nd Reference Voltage TC
VREF2 Pin, No Load
10
ppm/°C
2nd Reference Voltage Thermal
Hysteresis
VREF2 Pin, No Load
100
ppm
2nd Reference Voltage Long Term Drift
VREF2 Pin, No Load
60
ppm/√khr
General DC Specifications
IVP
V+ Supply Current
(See Figure 1: LTC6812-1 Operation
State Diagram)
State: Core = SLEEP,
isoSPI = IDLE
VREG = 0V
VREG = 0V
l
VREG = 5V
VREG = 5V
l
11
µA
6.1
18
µA
3
5
µA
3
9
µA
l
9
6
14
14
22
28
µA
µA
l
0.4
0.375
0.55
0.55
0.8
0.825
mA
mA
l
0.65
0.6
0.95
0.95
1.35
1.4
mA
mA
State: Core = STANDBY
State: Core = REFUP
State: Core = MEASURE
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6.1
Rev. B
5
LTC6812-1
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full specified
temperature range, otherwise specifications are at TA = 25°C. The test conditions are V+ = 49.5V, VREG = 5.0V unless otherwise noted.
The ISOMD pin is tied to the V– pin, unless otherwise noted.
SYMBOL
IREG(CORE)
PARAMETER
CONDITIONS
VREG Supply Current
State: Core = SLEEP,
isoSPI = IDLE
(See Figure 1: LTC6812-1 Operation
State Diagram)
MIN
VREG = 5V
VREG = 5V
ISOMD = 1,
RB1 + RB2 = 2k
ISOMD = 0,
RB1 + RB2 = 20k
ISOMD = 1,
RB1 + RB2 = 20k
VREG
µA
9
µA
l
60
65
µA
µA
l
0.4
0.3
0.9
0.9
1.4
1.5
mA
mA
l
14
13.5
15
15
16
16.5
mA
mA
READY
l
3.6
4.5
5.2
mA
ACTIVE
l
5.6
6.8
8.1
mA
READY
l
4.0
5.2
6.5
mA
ACTIVE
l
7.0
8.5
10.5
mA
READY
l
1.0
1.8
2.4
mA
ACTIVE
l
1.3
2.3
3.3
mA
READY
l
1.6
2.5
3.5
mA
ACTIVE
l
1.8
3.1
4.8
mA
50
75
V+ Supply Voltage
TME Specifications Met
l
16
V+ to C15 Voltage
TME Specifications Met
l
–0.3
V+ to C10 Voltage
TME Specifications Met
l
V
V
40
V
C11 Voltage
TME Specifications Met
l
2.5
V
C6 Voltage
TME Specifications Met
l
1
V
VREG Supply Voltage
TME Supply Rejection < 1mV/V
l
4.5
5
5.5
V
DRIVE Output Voltage
Sourcing 1µA
l
5.4
5.2
5.7
5.7
5.9
6.1
V
V
l
5.2
5.7
6.1
V
l
2.7
3
3.6
V
4
10
Ω
Sourcing 500µA
VREGD
6
35
35
State: Core = MEASURE
Note: ACTIVE State Current
Assumes tCLK = 1µs, (Note 3)
3.1
UNITS
3.1
State: Core = STANDBY
ISOMD = 0,
RB1 + RB2 = 2k
MAX
10
6
l
State: Core = REFUP
IREG(isoSPI) Additional VREG Supply Current
if isoSPI in READY/ACTIVE States
TYP
Digital Supply Voltage
Discharge Switch ON Resistance
VCELL = 3.6V
l
Thermal Shutdown Temperature
150
°C
VOL(WDT)
Watch Dog Timer Pin Low
WDT Pin Sinking 4mA
l
0.4
V
VOL(GPIO)
General Purpose I/O Pin Low
GPIO Pin Sinking 4mA (Used as Digital Output)
l
0.4
V
Measure 15 Cells
l
2077
µs
Measure 3 Cells
l
303
407
432
µs
Measure 15 Cells and 2 GPIO Inputs
l
2049
2753
2924
µs
ADC Timing Specifications
tCYCLE
(Figure 3,
Figure 4,
Figure 6)
Measurement + Calibration Cycle Time
When Starting from the REFUP State in
Normal Mode
Measurement + Calibration Cycle Time
When Starting from the REFUP State in
Filtered Mode
Measurement + Calibration Cycle Time
When Starting from the REFUP State in
Fast Mode
1455
1956
Measure 15 Cells
l
124.9
167.8
178.2
ms
Measure 3 Cells
l
25.0
33.6
35.7
ms
Measure 15 Cells and 2 GPIO Inputs
l
174.8
234.9
249.5
ms
Measure 15 Cells
l
697
937
996
µs
Measure 3 Cells
l
151
203
215
µs
Measure 15 Cells and 2 GPIO Inputs
l
988
1328
1410
µs
Rev. B
6
For more information www.analog.com
LTC6812-1
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full specified
temperature range, otherwise specifications are at TA = 25°C. The test conditions are V+ = 49.5V, VREG = 5.0V unless otherwise noted.
The ISOMD pin is tied to the V– pin, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
tSKEW1
(Figure 6)
Skew Time. The Time Difference
Between GPIO2 and Cell 1
Measurements, Command = ADCVAX
Fast Mode
Normal Mode
tSKEW2
(Figure 3)
Skew Time. The Time Difference
Between Cell 15 and Cell 1
Measurements, Command = ADCV
tSKEW3
(Figure 6)
Skew Time. The Time Difference
Between Cell 15 and GPIO1
Measurements, Command = ADCVAX
tWAKE
Regulator Start-Up Time
Watchdog or Discharge Timer
tSLEEP
(Figure 26)
tREFUP
(Figure 3
for
example)
Reference Wake-Up Time. Added to
tCYCLE Time When Starting from the
STANDBY State. tREFUP = 0 When
Starting from Other States.
fS
ADC Clock Frequency
MIN
TYP
MAX
UNITS
l
144
194
206
µs
l
404
543
577
µs
Fast Mode
l
139
187
198
µs
Normal Mode
l
400
536
569
µs
Fast Mode
l
109
147
156
µs
Normal Mode
l
304
409
434
µs
VREG Generated from DRIVE Pin (Figure 32)
l
200
400
µs
DTEN Pin = 0 or DCTO[3:0] = 0000
l
2
2.2
sec
120
min
4.4
ms
DTEN Pin = 1 and DCTO[3:0] ≠ 0000
tREFUP is Independent of the Number of
Channels Measured and the ADC Mode
1.8
0.5
l
2.7
3.5
3.3
MHz
SPI Interface DC Specifications
VIH(SPI)
SPI Pin Digital Input Voltage High
Pins CSB, SCK, SDI
l
VIL(SPI)
SPI Pin Digital Input Voltage Low
Pins CSB, SCK, SDI
l
2.3
V
VIH(CFG)
Configuration Pin Digital Input Voltage High Pins ISOMD, DTEN, GPIO1 to GPIO9
l
VIL(CFG)
Configuration Pin Digital Input Voltage Low
Pins ISOMD, DTEN, GPIO1 to GPIO9
l
1.2
V
ILEAK(DIG)
Digital Input Current
Pins CSB, SCK, SDI, ISOMD, DTEN
l
±1
μA
VOL(SDO)
Digital Output Low
Pin SDO Sinking 1mA
l
0.3
V
2.1
V
V
1.0
mA
22
24.5
mA/mA
mA/mA
1.6
V
0.8
2.7
V
V
isoSPI DC Specifications (See Figure 17)
VBIAS
Voltage on IBIAS Pin
READY/ACTIVE State
IDLE State
l
1.9
IB
Isolated Interface Bias Current
RBIAS = 2k to 20k
l
0.1
AIB
Isolated Interface Current Gain
VA = ≤ 1.6V IB = 1mA
IB = 0.1mA
l
l
18
18
VA
Transmitter Pulse Amplitude
VA = |VIP – VIM|
l
VICMP
Threshold-Setting Voltage on ICMP Pin
2.0
0
20
20
VTCMP = ATCMP • VICMP
l
1.5
V
ILEAK(ICMP) Input Leakage Current on ICMP Pin
VICMP = 0V to VREG
l
0.2
±1
µA
ILEAK(IP/IM) Leakage Current on IP and IM Pins
IDLE State, VIP or VIM, 0V to VREG
l
±1
µA
l
0.6
V/V
ATCMP
Receiver Comparator Threshold
Voltage Gain
VCM = VREG/2 to VREG – 0.2V, VICMP = 0.2V to
1.5V
0.4
VCM
Receiver Common Mode Bias
IP/IM Not Driving
RIN
Receiver Input Resistance
Single-Ended to IPA, IMA, IPB, IMB
l
26
0.5
(VREG – VICMP/3 – 167mV)
35
45
V
kΩ
isoSPI Idle/Wake-Up Specifications (See Figure 26)
VWAKE
Differential Wake-Up Voltage
tDWELL = 240ns
l
200
mV
tDWELL
Dwell Time at VWAKE Before Wake
Detection
VWAKE = 200mV
l
240
ns
tREADY
Start-Up Time After Wake Detection
l
tIDLE
Idle Timeout Duration
l
4.3
5.5
10
µs
6.7
ms
Rev. B
For more information www.analog.com
7
LTC6812-1
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full specified
temperature range, otherwise specifications are at TA = 25°C. The test conditions are V+ = 49.5V, VREG = 5.0V unless otherwise noted.
The ISOMD pin is tied to the V– pin, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
120
150
180
ns
isoSPI Pulse Timing Specifications (See Figure 22)
t1/2PW(CS)
Chip-Select Half-Pulse Width
Transmitter
l
tFILT(CS)
Chip-Select Signal Filter
Receiver
l
70
90
110
ns
tINV(CS)
Chip-Select Pulse Inversion Delay
Transmitter
l
120
155
190
ns
tWNDW(CS)
Chip-Select Valid Pulse Window
Receiver
l
220
270
330
ns
t1/2PW(D)
Data Half-Pulse Width
Transmitter
l
40
50
60
ns
tFILT(D)
Data Signal Filter
Receiver
l
10
25
35
ns
tINV(D)
Data Pulse Inversion Delay
Transmitter
l
40
55
65
ns
tWNDW(D)
Data Valid Pulse Window
Receiver
l
70
90
110
ns
SPI Timing Requirements (See Figure 16 and Figure 25)
tCLK
SCK Period
l
1
µs
t1
SDI Setup Time before SCK Rising Edge
(Note 4)
l
25
ns
t2
SDI Hold Time after SCK Rising Edge
l
25
ns
t3
SCK Low
tCLK = t3 + t4 ≥ 1µs
l
200
ns
t4
SCK High
tCLK = t3 + t4 ≥ 1µs
l
200
ns
t5
CSB Rising Edge to CSB Falling Edge
l
0.65
µs
t6
SCK Rising Edge to CSB Rising Edge
(Note 4)
l
0.8
µs
t7
CSB Falling Edge to SCK Rising Edge
(Note 4)
l
1
µs
(Note 5)
l
60
ns
isoSPI Timing Specifications (See Figure 25)
t8
SCK Falling Edge to SDO Valid
t9
SCK Rising Edge to Short ±1 Transmit
l
50
ns
t10
CSB Transition to Long ±1 Transmit
l
60
ns
t11
CSB Rising Edge to SDO Rising
l
200
ns
375
425
ns
120
180
ns
300
ns
(Note 5)
tRTN
Data Return Delay
l
tDSY(CS)
Chip-Select Daisy-Chain Delay
l
tDSY(D)
Data Daisy-Chain Delay
l
tLAG
Data Daisy-Chain Lag (vs Chip-Select)
t5(GOV)
325
200
250
l
0
35
70
ns
Chip-Select High-to-Low Pulse
Governor
l
0.6
0.82
µs
t6(GOV)
Data to Chip-Select Pulse Governor
l
0.8
1.05
µs
tBLOCK
isoSPI Port Reversal Blocking Window
l
2
10
µs
= [tDSY(D) + t1/2PW(D)] – [tDSY(CS) + t1/2PW(CS)]
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The ADC specifications are guaranteed by the Total Measurement
Error specification.
Note 3: The ACTIVE state current is calculated from DC measurements.
The ACTIVE state current is the additional average supply current into
VREG when there is continuous 1MHz communications on the isoSPI ports
with 50% data 1’s and 50% data 0’s. Slower clock rates reduce the supply
current. See Applications Information section for additional details.
Note 4: These timing specifications are dependent on the delay through
the cable, and include allowances for 50ns of delay each direction. 50ns
corresponds to 10m of CAT5 cable (which has a velocity of propagation of
66% the speed of light). Use of longer cables would require derating these
specs by the amount of additional delay.
Note 5: These specifications do not include rise or fall time of SDO. While
fall time (typically 5ns due to the internal pull-down transistor) is not a
concern, rising-edge transition time tRISE is dependent on the pull-up
resistance and load capacitance on the SDO pin. The time constant must
be chosen such that SDO meets the setup time requirements of the MCU.
Rev. B
8
For more information www.analog.com
LTC6812-1
TYPICAL PERFORMANCE CHARACTERISTICS
Measurement Error
vs Input, Normal Mode
Measurement Error vs
Temperature
2.0
CELL VOLTAGE = 3.3V
5 TYPICAL UNITS, CELL 1
2.0
10 ADC MEASUREMENTS
AVERAGED AT EACH INPUT
1.5
MEASUREMENT ERROR (mV)
1.5
MEASUREMENT ERROR (mV)
Measurement Error
vs Input, Filtered Mode
1.0
0.5
0
–0.5
–1.0
–1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
–2.0
0.5
0
–0.5
–1.0
0
1
2
3
INPUT (V)
4
5
–2.0
10 ADC MEASUREMENTS
AVERAGED AT EACH INPUT
PEAK NOISE (mV)
0
–2
–4
1.0
1.0
0.9
0.9
0.8
0.8
0.7
0.7
0.6
0.5
0.4
0.3
0.4
0.3
0.2
0.2
0.1
0.1
–10
0
2
3
INPUT (V)
4
5
0
1
2
3
INPUT (V)
4
68121 G04
25
9
25
TA = 85°C to 25°C
20
NUMBER OF PARTS
6
5
4
3
2
1
2
3
INPUT (V)
4
5
Measurement Gain Error
Thermal Hysteresis, Cold
TA = –40°C to 25°C
20
NUMBER OF PARTS
8
7
0
68121 G06
Measurement Gain Error
Thermal Hysteresis, Hot
10
PEAK NOISE (mV)
0
5
68121 G05
Measurement Noise
vs Input, Fast Mode
5
0.5
–8
1
4
0.6
–6
0
2
3
INPUT (V)
Measurement Noise
vs Input, Filtered Mode
PEAK NOISE (mV)
10
2
1
68121 G03
Measurement Noise
vs Input, Normal Mode
4
0
68121 G02
Measurement Error vs Input,
Fast Mode
6
1.0
–1.5
68121 G01
8
10 ADC MEASUREMENTS
AVERAGED AT EACH INPUT
1.5
MEASUREMENT ERROR (mV)
2.0
MEASUREMENT ERROR (mV)
TA = 25°C, unless otherwise noted.
15
10
5
15
10
5
1
0
0
1
2
3
INPUT (V)
4
5
0
–50
–30
–10
10
30
CHANGE IN GAIN ERROR (ppm)
68121 G07
50
68121 G8
0
–75
–50
–25
0
25
50
CHANGE IN GAIN ERROR (ppm)
75
68121 G9
Rev. B
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9
LTC6812-1
TYPICAL PERFORMANCE CHARACTERISTICS
2.0
6
–10
1.5
5
4
3
2
MEASUREMENT ERROR (mV)
0
–20
–30
–40
–50
1
–60
0
–50 –25 0 25 50 75 100 125 150 175 200
CHANGE IN GAIN ERROR (ppm)
–70
10
100
0
–0.5
–1.0
–1.5
20
30
40
V+ (V)
0
–10
Measurement Error
vs Common Mode Voltage
2.0
C15–C14 = 3.3V
C15 = 49.5V
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
V+ (V)
68121 G13
–10
–20
–30
–30
–40
–50
0
–0.5
–1.0
–1.5
20
–70
68121 G16
30
35
40
C14 VOLTAGE (V)
45
50
68121 G15
0
V+DC = 49.5V
V+AC = 5Vp–p
1BIT CHANGE < –90dB
VREG GENERATED FROM
DRIVE PIN, FIGURE 32
–10
–20
–40
–50
–60
–100
100
VCM(IN) = 5Vp–p
NORMAL MODE CONVERSIONS
–30
–40
–50
–60
–70
–80
–90
10M
25
Measurement Error CMRR
vs Frequency
–80
1M
0.5
68121 G14
–70
–60
10k
100k
FREQUENCY (Hz)
1.0
–2.0
0
VREG(DC) = 5V
VREG(AC) = 0.5Vp–p
1BIT CHANGE < –70dB
1k
C15 – C14 = 3.3V
V+ = 53.3V
1.5
Measurement Error Due to a
V+ AC Disturbance
Measurement Error Due to a
VREG AC Disturbance
–80
100
–1.0
68121 G11
–2.0
46.5 47.5 48.5 49.5 50.5 51.5 52.5 53.5
50
PSRR (dB)
PSRR (dB)
–20
–0.5
68121 G12
REJECTION (dB)
10
0
14kHz
27kHz
2kHz
3kHz
7kHz
CELL15 MEASUREMENT ERROR (mV)
TOP CELL MEASUREMENT ERROR (mV)
MEASUREMENT ERROR (mV)
0.5
0
0.5
–2.0
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
VREG (V)
1M
2.0
MEASUREMENT ERROR OF
CELL1 WITH 3.3V INPUT
VREG GENERATED FROM
DRIVE PIN, FIGURE 32
1.0
1.0
Top Cell Measurement Error vs V+
2.0
–2.0
1k
10k
100k
INPUT FREQUENCY (Hz)
26Hz
422Hz
1kHz
Measurement Error vs V+
VIN = 2V
VIN = 3.3V
VIN = 4.2 V
–1.5
68121 G10
1.5
Measurement Error vs VREG
Noise Filter Response
7
NOISE REJECTION (dB)
NUMBER OF PARTS
Measurement Error Due to
IR Reflow
TA = 25°C, unless otherwise noted.
–90
1k
10k
100k
FREQUENCY (Hz)
1M
10M
68121 G17
–100
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
68121 G18
Rev. B
10
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LTC6812-1
TYPICAL PERFORMANCE CHARACTERISTICS
GPIO Measurement Error
vs Input RC Values
Cell Measurement Error Range
vs Input RC Values
Measurement Time
vs Temperature
20
0
–5
–10
100nF
10nF
1µF
–15
100
1k
INPUT RESISTANCE, R (Ω)
8
4
0
–4
–8
C = 1nF
C = 10nF
C = 100nF
C = 1µF
C = 10µF
–12
–16
1
7
6
3
5
15
25
35
45
55
V+ (V)
125°C
85°C
25°C
0°C
–40°C
65
75
10
100
1k
INPUT RESISTANCE, R (Ω)
40
30
5
15
25
35
45
55
65
14.5
5
15
25
35
45
V+ (V)
75
1.2
68121 G25
5
15
25
35
45
55
65
75
68121 G24
3.005
5 TYPICAL UNITS
5 TYPICAL UNITS
3.004
3.003
3.002
VREF2 (V)
3.155
3.150
3.145
3.130
–50
125°C
85°C
25°C
0°C
–40°C
1.3
VREF2 vs Temperature
3.001
3.000
2.999
2.998
2.997
3.135
65
1.4
68121 G23
3.140
55
125
1.5
V+ (V)
3.165
16.5
15.0
100
1.6
VREF1 vs Temperature
3.170
125°C
85°C
25°C
0°C
–40°C
0
25
50
75
TEMPERATURE (°C)
REFUP SUPPLY CURRENT =
V+ CURRENT + VREG CURRENT
1.7
1.1
75
3.160
15.5
–25
REFUP Supply Current vs V+
50
68121 G22
16.0
VREG=4.5V
VREG=5V
VREG=5.5V
68121 G21
1.8
V+ (V)
VREF1 (V)
MEASURE SUPPLY CURRENT (mA)
1.70
–50
10k
125°C
85°C
25°C
0°C
–40°C
60
20
MEASURE SUPPLY CURRENT =
V+ CURRENT + VREG CURRENT
17.0
1.80
STANDBY SUPPLY CURRENT =
V+ CURRENT + VREG CURRENT
70
Measure Supply Current vs V+
17.5
1.85
REFUP SUPPLY CURRENT (mA)
STANDBY SUPPLY CURRENT (µA)
SLEEP SUPPLY CURRENT (µA)
80
8
4
1.90
Standby Supply Current vs V+
SLEEP SUPPLY CURRENT =
V+ CURRENT + VREG CURRENT
5
1.95
68121 G20
Sleep Supply Current vs V+
9
2.00
1.75
68121 G19
10
15 CELL NORMAL MODE CONVERSIONS
2.05
12
–20
10k
2.10
TIME BETWEEN MEASUREMENTS > 3RC
16
MEASUREMENT TIME (ms)
GPIO MEASUREMENT ERROR (mV)
5
CELL MEASUREMENT ERROR (mV)
TA = 25°C, unless otherwise noted.
2.996
–25
0
25
50
75
TEMPERATURE (°C)
100
125
68121 G26
2.995
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
68121 G27
Rev. B
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11
LTC6812-1
TYPICAL PERFORMANCE CHARACTERISTICS
IL = 0.6mA
320
125°C
85°C
25°C
–40°C
240
CHANGE IN VREF2 (ppm)
100
160
60
0
–80
–160
20
0
–20
125°C
85°C
25°C
–40°C
–40
–60
–320
–80
4.75
5
5.25
VREG (V)
5.5
–100
15
25
35
45
55
65
75
V+ (V)
68121 G28
VREF2 Thermal Hysteresis, Hot
15
V+ = 49.5V
VREG = 5V
–200
–400
–600
125°C
85°C
25°C
–40°C
–800
85
95
–1000
0.01
0.1
1
IOUT (mA)
68121 G29
VREF2 Thermal Hysteresis, Cold
5
TA = –40°C to 25°C
TA = 85°C to 25°C
VREF2 Load Regulation
0
40
–240
–400
4.5
200
VREG GENERATED FROM
DRIVE PIN, FIGURE 32
80
80
15
VREF2 V+ Line Regulation
CHANGE IN VREF2 (ppm)
VREF2 VREG Line Regulation
CHANGE IN VREF2 (ppm)
400
TA = 25°C, unless otherwise noted.
10
68121 G30
VREF2 Change Due to IR Reflow
10
5
NUMBER OF PARTS
NUMBER OF PARTS
NUMBER OF PARTS
4
10
5
3
2
1
0
–75
68121 G31
5.9
VDRIVE vs Temperature
25
5 TYPICAL UNITS
NO LOAD
CHANGE IN VDRIVE (mV)
VDRIVE (V)
5.7
5.6
5.5
5.4
–50
–25
0
25
50
CHANGE IN VREF2 (ppm)
75
68121 G32
0
25
50
75
TEMPERATURE (°C)
100
125
68121 G34
–100
0
100
200
CHANGE IN VREF2 (ppm)
300
68121 G33
VDRIVE Load Regulation
125°C
85°C
25°C
0°C
–40°C
–10
–20
10
5
0
V+ = 49.5V
–30
–40
–50
–60
125°C
85°C
25°C
0°C
–40°C
–70
–80
–5
–25
–200
0
15
–10
0
–300
100
VDRIVE V+ Line Regulation
20
5.8
–50
CHANGE IN VDRIVE (mV)
0
–125–100 –75 –50 –25 0 25 50 75 100 125
CHANGE IN VREF2 (ppm)
–90
15
30
45
V+ (V)
60
75
68121 G35
–100
0.01
0.1
IOUT (mA)
1
68121 G36
Rev. B
12
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LTC6812-1
TYPICAL PERFORMANCE CHARACTERISTICS
50
ON–RESISTANCE OF INTERNAL
DISCHARGE SWITCH MEASURED
BETWEEN S(n) AND C(n–1)
16
14
12
125°C
85°C
25°C
–40°C
10
8
6
4
2
0
0
0.5
1
1.5 2 2.5 3 3.5
CELL VOLTAGE (V)
4
4.5
40
35
30
25
20
15
10
5
0
5
1 CELL DISCHARGING
6 CELL DISCHARGING
12 CELL DISCHARGING
15 CELL DISCHARGING
45
0
25 50 75 100 125 150 175 200
INTERNAL DISCHARGE CURRENT (mA/CELL)
68121 G37
VREF1
1V/DIV
VREG: CL = 1µF
VREG GENERATED FROM
DRIVE PIN
VREF1
VREF2
VREF2
1V/DIV
VDRIVE
2V/DIV
CS
4
2
0
–2
–4
–6
–8
–10
–50
6.0
VDRIVE
CS
CS
5V/DIV
68121 G40
500µs/DIV
6
–25
0
25
50
75
TEMPERATURE (°C)
100
125
isoSPI Current (READY)
vs Temperature
VREG
VREG
2V/DIV
CS
5V/DIV
5 TYPICAL UNITS
8
68121 G39
VREG and VDRIVE Power-Up
VREF1 and VREF2 Power-Up
VREF1: CL = 1µF
VREF2: CL = 1µF, RL = 5kΩ
10
Internal Die Temperature
Measurement Error vs
Temperature
68121 G38
5.0
4.5
4.0
68121 G41
50µs/DIV
IB = 1mA
5.5
isoSPI CURRENT (mA)
18
INCREASE IN DIE TEMPERATURE (°C)
DISCHARGE SWITCH ON–RESISTANCE (Ω)
20
Internal Die Temperature
Increase vs Discharge Current
TEMPERATURE MEASUREMENT ERROR (°C)
Discharge Switch On-Resistance
vs Cell Voltage
TA = 25°C, unless otherwise noted.
3.5
–50
ISOMD = V –
ISOMD = VREG
–25
0
25
50
75
TEMPERATURE (°C)
100
125
68121 G42
isoSPI Current (ACTIVE)
vs isoSPI Clock Frequency
ISOMD = VREG
IB = 1mA
8
7
IBIAS PIN VOLTAGE (V)
isoSPI CURRENT (mA)
IBIAS Voltage vs Temperature
2.02
6
5
4
IB = 1mA
3 PARTS
2.01
2.00
1.99
2.005
2.000
1.995
WRITE
READ
3
2
IBIAS Voltage Load Regulation
2.010
IBIAS PIN VOLTAGE (V)
9
0
200
400
600
800
isoSPI CLOCK FREQUENCY (kHz)
1000
68121 G43
1.98
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
68121 G44
1.990
0
200
400
600
800
IBIAS CURRENT, IB (µA)
1000
68121 G45
Rev. B
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13
LTC6812-1
TYPICAL PERFORMANCE CHARACTERISTICS
23
22
22
21
20
0
200
400
600
800
IBIAS CURRENT, IB (µA)
21
20
19
18
–50
1000
100
0.54
0.52
0.50
0.48
VICMP = 0.2V
VICMP = 1V
3
3.5
4
4.5
5
RECEIVER COMMON MODE, VCM (V)
4.5
4.0
3.5
3.0
2.5
125
IB = 100uA
IB = 1mA
0
0.5
1
1.5
PULSE AMPLITUDE, VA (V)
68121 G47
COMPARATOR THRESHOLD GAIN, ATCMP (V/V)
COMPARATOR THRESHOLD GAIN, ATCMP (V/V)
0
25
50
75
TEMPERATURE (°C)
5.0
isoSPI Comparator Threshold
Gain (Port A/Port B)
vs ICMP Voltage
0.56
0.44
2.5
–25
68121 G46
isoSPI Comparator Threshold
Gain (Port A/Port B) vs Receiver
Common Mode
0.46
IB = 100uA
IB = 1mA
5.5
0.56
3 PARTS
0.54
0.52
0.50
0.48
0.46
0.44
0
68121 G49
0.2
0.4
0.6 0.8 1 1.2
ICMP VOLTAGE (V)
2
68121 G48
isoSPI Comparator Threshold
Gain (Port A/Port B)
vs Temperature
COMPARATOR THRESHOLD GAIN, ATCMP (V/V)
18
VA = 1.6V
VA = 1V
VA = 0.5V
5.5
DRIVER COMMON MODE (V)
23
19
isoSPI Driver Common Mode
Voltage (Port A/Port B)
vs Pulse Amplitude
isoSPI Driver Current Gain
(Port A/Port B) vs Temperature
CURRENT GAIN, AIB (mA/mA)
CURRENT GAIN, AIB (mA)
isoSPI Driver Current Gain
(Port A/Port B) vs IBIAS Current
TA = 25°C, unless otherwise noted.
1.4
1.6
68121 G50
0.56
0.54
0.52
0.50
0.48
0.46
0.44
–50
VICMP = 0.2V
VICMP = 1V
–25
0
25
50
75
TEMPERATURE (°C)
100
125
68121 G51
Typical Wake-Up Pulse Amplitude
(Port A/Port B) vs Dwell Time
WAKE–UP PULSE AMPLITUDE, VWAKE (mV)
300
GUARANTEED
WAKE–UP REGION
250
200
150
100
50
0
0
100
200
300
400
500
WAKE–UP DWELL TIME, TDWELL (ns)
600
68121 G52
Rev. B
14
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LTC6812-1
PIN FUNCTIONS
C0 to C15: Cell Inputs.
Serial Port Pins
S1 to S15: Balance Inputs/Outputs. 15 internal N-MOSFETs
are connected between S(n) and C(n–1) for discharging
cells.
ISOMD = VREG
PORT B
(Pins 57, 58, 63 and 64)
V+: Positive Supply Pin.
V–: Negative Supply Pins. The V– pins must be shorted
together, external to the IC.
PORT A
(Pins 53, 54, 61 and 62)
VREF2: Buffered 2nd Reference Voltage for Driving Multiple
10k Thermistors. Bypass with an external 1μF capacitor.
VREF1: ADC Reference Voltage. Bypass with an external
1μF capacitor. No DC loads allowed.
GPIO[1:9]: General Purpose I/O. Can be used as digital
inputs or digital outputs, or as analog inputs with a measurement range from V– to 5V. GPIO[3:5] can be used as
an I2C or SPI port.
DTEN: Discharge Timer Enable. Connect this pin to VREG
to enable the Discharge Timer.
DRIVE: Connect the base of an NPN to this pin. Connect
the collector to V+ and the emitter to VREG.
VREG: 5V Regulator Input. Bypass with an external 1μF
capacitor.
ISOMD: Serial Interface Mode. Connecting ISOMD to VREG
configures pins 53, 54, 61 and 62 of the LTC6812-1 for
2-wire isolated interface (isoSPI) mode. Connecting ISOMD
to V– configures the LTC6812-1 for 4-wire SPI mode.
WDT: Watchdog Timer Output Pin. This is an open drain
NMOS digital output. It can be left unconnected or connected with a 1M resistor to VREG. If the LTC6812-1
does not receive a valid command within 2 seconds, the
watchdog timer circuit will reset the LTC6812-1 and the
WDT pin will go high impedance.
ISOMD = V–
IPB
IPB
IMB
IMB
ICMP
ICMP
IBIAS
IBIAS
(NC)
SDO
(NC)
SDI
IPA
SCK
IMA
CSB
CSB, SCK, SDI, SDO: 4-Wire Serial Peripheral Interface (SPI). Active low chip select (CSB), serial clock
(SCK) and serial data in (SDI) are digital inputs. Serial
data out (SDO) is an open drain NMOS output pin. SDO
requires a 5k pull-up resistor.
IPA, IMA: Isolated 2-Wire Serial Interface Port A. IPA (plus)
and IMA (minus) are a differential input/output pair.
IPB, IMB: Isolated 2-Wire Serial Interface Port B. IPB (plus)
and IMB (minus) are a differential input/output pair.
IBIAS: Isolated Interface Current Bias. Tie IBIAS to V–
through a resistor divider to set the interface output
current level. When the isoSPI interface is enabled, the
IBIAS pin voltage is 2V. The IPA/IMA or IPB/IMB output
current drive is set to 20 times the current, IB, sourced
from the IBIAS pin.
ICMP: Isolated Interface Comparator Voltage Threshold
Set. Tie this pin to the resistor divider between IBIAS
and V– to set the voltage threshold of the isoSPI receiver
comparators. The comparator thresholds are set to half
the voltage on the ICMP pin.
NC: All pins identified with “NC” must be left unconnected.
Exposed Pad: V–. The Exposed Pad must be soldered to
PCB.
Rev. B
For more information www.analog.com
15
LTC6812-1
BLOCK DIAGRAM
64
1
2
IPB
63
IMB
62
61
SCK
(IPA)
CSB
(IMA)
4
5
6
7
9
C14
NC
12
58
ICMP
57
IBIAS
14
15
16
WDT
55
ISOMD
54
SDO
(NC)
53
VREGD
SDI
(NC)
52
DTEN
51
VREF1
50
49
VREF2
DRIVE
VREG
POR
VREG
5-CELL
MUX
NC
16
ADC3
GPIO9
IPB
SERIAL
PORT B
–
M
C11
IMB
ICMP
GPIO8
IBIAS
C15
C10
C9
S15
6-CELL
MUX
C8
C7
C14
+
P
16
ADC2
DIGITAL
FILTERS
–
M
GPIO7
CSB (IMA)
LOGIC
AND
MEMORY
SCK (IPA)
SERIAL
PORT A
GPIO6
SDO (NC)
SDI (NC)
C6
GPIO5
S14
GPIO4
C13
C4
C2
GPIO AND
I2C
16
ADC1
6-CELL
MUX M
C3
S13
+
P
GPIO2
C1
WDT ISOMD
C0
S12
GPIO3
–
15 BALANCE FETs
TEMP
VREF2
SC
VREG
VREGD
P
S(n)
GPIO1
GPIO[9:1]
C0
AUX
MUX
C11
S1
M
C(n–1)
13
56
+
P
C13
10 C12
11
V–
C15
C5
8
59
V–
VREF1
V+
C12
3
60
S11
C1
C15
DIE
TEMPERATURE
TEMP
NC
NC
DISCHARGE
TIMER
DTEN
C10
S10
17
C9
18
S9
19
V+
LDO2
C0
C8
20
S8
21
DRIVE
V+
VREGD
POR
LDO1
C7
22
VREF2
1ST
REFERENCE
VREF1
S2
47
46
45
44
43
42
41
40
39
38
37
36
35
REGULATORS
SC
WATCH DOG
TIMER
WDT
2ND
REFERENCE
48
S7
23
C6
24
S6
25
NC
26
S3
NC
27
C2
C5
28
S5
29
C4
30
S4
31
34
33
C3
32
68121 BD
Rev. B
16
For more information www.analog.com
LTC6812-1
IMPROVEMENTS FROM THE LTC6811-1
The LTC6812-1 is an evolution of the LTC6811-1 design. The following table summarizes the feature changes and
additions in the LTC6812-1.
ADDITIONAL LTC6812-1 FEATURES
BENEFITS
RELEVANT DATA SHEET SECTION(S)
The LTC6812-1 Has 3 ADCs Operating
Simultaneously vs 2 ADCs on LTC6811-1
3 Cells Can Be Measured During Each
Conversion Cycle
ADC Operation
In Addition to the 3 ADC Digital Filters, There Is a
4th Filter Which Is Used for Redundancy
Checks That All Digital Filters are Free of Faults
ADC Conversion with Digital Redundancy for a
description and PS[1:0] bits in Table 10
Measure Cell 6 with ADC1 and ADC2
Simultaneously and then Measure Cell 11 with
ADC2 and ADC3 Simultaneously Using the
ADOL Command
Checks That ADC2 Is as Accurate as ADC1 and
Also Checks That ADC3 Is as Accurate as ADC2
Overlap Cell Measurement (ADOL Command)
A Monitoring Feature Can Be Enabled During
the Discharge Timer. The Cell Balancing Can Be
Automatically Terminated When Cell Voltages
Reach a Programmable Undervoltage Threshold
Improved Cell Balancing
Discharge Timer Monitor
The Internal Discharge MOSFETs Can Provide
200mA of Balancing Current (80mA if the die
temperature is over 95°C). The Balancing Current
Is Independent of Cell Voltage
Faster Cell Balancing, Especially for Low Cell
Voltages
Cell Balancing with Internal MOSFETs
The C0 Pin Voltage Is Allowed to Range Between
0V and 1V Without Affecting Total Measurement
Error (TME)
C0 Does Not Have to Connect Directly to V–
Input Range in Electrical Characteristics
The MUTE and UNMUTE Commands Allow the
Host to Turn Off/On the Discharge Pins (S Pins)
Without Overwriting Register Values
Greater Control of Timing Between S Pins
Turning Off and Cell Measurements
S Pin Muting
Auxiliary Measurements Have an Open-Wire
Diagnostic Feature
Improved Fault Detection
Auxiliary Open Wire Check (AXOW Command)
Four Additional GPIO Pins Have Been Added for a
Total of Nine
Increased Number of Temperature or Other
Sensors That Can Be Measured
Auxiliary (GPIO) Measurements (ADAX
Command) and Auxiliary Open Wire Check
(AXOW Command)
A Daisy Chain of LTC6812-1s Can Operate in Both
Directions (Both Ports Can Be Master or Slave)
Redundant Communication Path
Reversible isoSPI
Rev. B
For more information www.analog.com
17
LTC6812-1
OPERATION
STATE DIAGRAM
The operation of the LTC6812-1 is divided into two separate sections: the Core circuit and the isoSPI circuit. Both
sections have an independent set of operating states, as
well as a shutdown timeout.
CORE LTC6812-1 STATE DESCRIPTIONS
SLEEP State
The references and ADCs are powered down. The watchdog timer (see Watchdog and Discharge Timer) has timed
out. The discharge timer is either disabled or timed out.
The supply currents are reduced to minimum levels. The
isoSPI ports will be in the IDLE state. The DRIVE pin is
0V. All state machines are reset to their default states.
enters either the REFUP or MEASURE state. Otherwise, if
no valid commands are received for tSLEEP, the IC returns
to the SLEEP state if DTEN = 0 or enters the EXTENDED
BALANCING state if DTEN = 1.
REFUP State
To reach this state, the REFON bit in Configuration Register
Group A must be set to 1 (using the WRCFGA command,
see Table 36). The ADCs are off. The references are powered
up so that the LTC6812-1 can initiate ADC conversions
more quickly than from the STANDBY state.
If a WAKEUP signal is received (see Waking Up the Serial
Interface), the LTC6812-1 will enter the STANDBY state.
When a valid ADC command is received, the IC goes to
the MEASURE state to begin the conversion. Otherwise,
the LTC6812-1 will return to the STANDBY state when
the REFON bit is set to 0 (using WRCFGA command). If
no valid commands are received for tSLEEP, the IC returns
to the SLEEP state if DTEN = 0 or enters the EXTENDED
BALANCING state if DTEN = 1.
STANDBY State
MEASURE State
The references and the ADCs are off. The watchdog timer
and/or the discharge timer is running. The DRIVE pin
powers the VREG pin to 5V through an external transistor.
(Alternatively, VREG can be powered by an external supply).
The LTC6812-1 performs ADC conversions in this state.
The references and ADCs are powered up.
When a valid ADC command is received or the REFON bit
is set to 1 in Configuration Register Group A, the IC pauses
for tREFUP to allow for the references to power up and then
After ADC conversions are complete, the LTC6812-1 will
transition to either the REFUP or STANDBY state, depending
on the REFON bit. Additional ADC conversions can be initiated more quickly by setting REFON = 1 to take advantage
of the REFUP state.
CORE LTC6812-1
isoSPI PORT
SLEEP
WD TIMEOUT
AND DTEN=0
(tSLEEP)
WD TIMEOUT
AND DTEN=0
(tSLEEP)
REFON = 0
REFUP
WD TIMEOUT
AND DTEN=1
WAKEUP
SIGNAL
(tWAKE)
STANDBY
REFON = 1
(tREFUP) ADC
COMM
(tREFUP)
ADC
COMMAND
CONV DONE
(REFON = 1)
MEASURE
WD TIMEOUT
AND DTEN=1
WAKEUP SIGNAL
(tWAKE)
EVERY 30s
AND DTM=1
WAKEUP
SIGNAL
CONV DONE (tWAKE)
(REFON = 0)
IDLE
IDLE TIMEOUT
(tIDLE)
DCTO REACHES 0
EXTENDED
BALANCING
WAKEUP SIGNAL
(CORE = SLEEP)
(tWAKE)
WAKEUP SIGNAL
(CORE = STANDBY)
(tREADY)
READY
NO ACTIVITY ON
isoSPI PORT
CONV
DONE
DTM
MEASURE
TRANSMIT/RECEIVE
ACTIVE
NOTE: STATE TRANSITION
DELAYS DENOTED BY (tX)
68121 F01
Figure 1. LTC6812-1 Operation State Diagram
Rev. B
18
For more information www.analog.com
LTC6812-1
OPERATION
Note: Non-ADC commands do not cause a Core state transition. Only an ADC Conversion or diagnostic commands
will place the Core in the MEASURE state.
EXTENDED BALANCING State
The watchdog timer has timed out, but the discharge timer
has not yet timed out (DTEN = 1). Discharge by PWM may
be in progress. If the Discharge Timer Monitor is enabled
then the LTC6812-1 will transition to the DTM MEASURE
state every 30 seconds to measure the cell voltages. If a
WAKEUP signal is received, the LTC6812-1 will transition
from EXTENDED BALANCING state to STANDBY state.
If there is no activity (i.e., no WAKEUP signal) on Port A
or Port B for greater than tIDLE, the LTC6812-1 goes to
the IDLE state. When the serial interface is transmitting or
receiving data, the LTC6812-1 goes to the ACTIVE state.
ACTIVE State
The LTC6812-1 is transmitting/receiving data using one
or both of the isoSPI ports. The serial interface consumes maximum power in this state. The supply current
increases with clock frequency as the density of isoSPI
pulses increases.
POWER CONSUMPTION
Discharge Timer Monitor MEASURE State
The watchdog timer has timed out but background monitoring has been enabled (DTMEN =1 in Configuration Register Group B). The LTC6812-1 enters this state from the
EXTENDED BALANCING state once every 30 seconds to
measure the cell voltages. The LTC6812-1 is in the highest
core power state and an A/D conversion is in progress. If a
WAKEUP signal is received, the LTC6812-1 will transition
from DTM MEASURE state to STANDBY state.
isoSPI STATE DESCRIPTIONS
Note: The LTC6812-1 has two isoSPI ports (A and B), for
daisy-chain communication.
IDLE State
The isoSPI ports are powered down.
When isoSPI Port A or Port B receives a WAKEUP signal
(see Waking Up the Serial Interface), the isoSPI enters
the READY state. This transition happens quickly (within
tREADY) if the Core is in the STANDBY state. If the Core is
in the SLEEP state when the isoSPI receives a WAKEUP
signal, then it transitions to the READY state within tWAKE.
READY State
The LTC6812-1 is powered via two pins: V+ and VREG.
The V+ input requires voltage greater than or equal to
the top cell voltage minus 0.3V, and it provides power to
the high voltage elements of the Core circuits. The VREG
input requires 5V and provides power to the remaining
Core circuits and the isoSPI circuitry. The VREG input can
be powered through an external transistor, driven by the
regulated DRIVE output pin. Alternatively, VREG can be
powered by an external supply.
The power consumption varies according to the operational
states. Table 1 and Table 2 provide equations to approximate
the supply pin currents in each state. The V+ pin current
depends only on the Core state. However, the VREG pin
current depends on both the Core state and isoSPI state,
and can, therefore, be divided into two components. The
isoSPI interface draws current only from the VREG pin.
IREG = IREG(CORE) + IREG(isoSPI)
In the SLEEP state, the VREG pin will draw approximately
3.1μA if powered by an external supply. Otherwise, the
V+ pin will supply the necessary current.
Table 1. Core Supply Current
STATE
SLEEP
The isoSPI port(s) are ready for communication. The serial
interface current in this state depends on the status of the
ISOMD pin and RBIAS = RB1 + RB2 (the external resistors
tied to the IBIAS pin).
IVP
IREG(CORE)
VREG = 0V
6.1µA
0µA
VREG = 5V
3µA
3.1µA
STANDBY
14µA
35µA
REFUP
550µA
900µA
MEASURE
950µA
15mA
Rev. B
For more information www.analog.com
19
LTC6812-1
OPERATION
mode. The increase in speed comes from a reduction in
the oversampling ratio. This results in an increase in noise
and average measurement error.
Table 2. isoSPI Supply Current Equations
isoSPI
STATE
ISOMD
CONNECTION
IREG(isoSPI)
IDLE
N/A
0mA
VREG
2.2mA + 3 • IB
V–
1.5mA + 3 • IB
READY
VREG
ACTIVE
V–
⎛
100ns ⎞
•IB
Write: 2.5mA + ⎜ 3 + 20 •
t CLK ⎟⎠
⎝
⎛
100ns • 1.5 ⎞
•IB
Read: 2.5mA + ⎜ 3 + 20 •
t CLK ⎟⎠
⎝
⎛
100ns ⎞
•IB
1.8mA + ⎜ 3 + 20 •
t CLK ⎟⎠
⎝
ADC OPERATION
Mode 26Hz (Filtered): In this mode, the ADC digital filter
–3dB frequency is lowered to 26Hz by increasing the OSR.
This mode is also referred to as the filtered mode due to
its low –3dB frequency. The accuracy is similar to the 7kHz
(Normal) mode with lower noise.
Modes 14kHz, 3kHz, 2kHz, 1kHz and 422Hz: Modes 14kHz,
3kHz, 2kHz, 1kHz and 422Hz provide additional options to
set the ADC digital filter –3dB at 13.5kHz, 3.4kHz, 1.7kHz,
845Hz and 422Hz, respectively. The accuracy of the 14kHz
mode is similar to the 27kHz (Fast) mode. The accuracy
of 3kHz, 2kHz, 1kHz and 422Hz modes is similar to the
7kHz (Normal) mode.
There are three ADCs inside the LTC6812-1. The three ADCs
operate simultaneously when measuring fifteen cells. Only
one ADC is used to measure the general purpose inputs.
The following discussion uses the term ADC to refer to one
or all ADCs, depending on the operation being performed.
The following discussion will refer to ADC1, ADC2 and
ADC3 when it is necessary to distinguish between the
three circuits, in timing diagrams, for example.
The filter bandwidths and the conversion times for these
modes are provided in Table 3 and Table 5. If the Core is
in STANDBY state, an additional tREFUP time is required to
power up the reference before beginning the ADC conversions. The reference can remain powered up between ADC
conversions if the REFON bit in Configuration Register
Group A is set to 1 so the Core is in REFUP state after a
delay tREFUP. Then, the subsequent ADC commands will not
have the tREFUP delay before beginning ADC conversions.
ADC Modes
Table 3. ADC Filter Bandwidth and Accuracy
The ADCOPT bit (CFGAR0[0]) in Configuration Register
Group A and the mode selection bits MD[1:0] in the conversion command together provide eight modes of operation
for the ADC which correspond to different oversampling
ratios (OSR). The accuracy and timing of these modes
are summarized in Table 3. In each mode, the ADC first
measures the inputs, and then performs a calibration of
each channel. The names of the modes are based on the
–3dB bandwidth of the ADC measurement.
Mode 7kHz (Normal): In this mode, the ADC has high
resolution and low TME (Total Measurement Error). This
is considered the normal operating mode because of the
optimum combination of speed and accuracy.
–3dB
FILTER
BW
–40dB
FILTER
BW
TME SPEC
AT 3.3V,
25°C
TME SPEC
AT 3.3V,
–40°C, 125°C
27kHz
(Fast Mode)
27kHz
84kHz
±6mV
±6mV
14kHz
13.5kHz
42kHz
±6mV
±6mV
7kHz
(Normal Mode)
6.8kHz
21kHz
±2.2mV
±3.3mV
3kHz
3.4kHz
10.5kHz
±2.2mV
±3.3mV
2kHz
1.7kHz
5.3kHz
±2.2mV
±3.3mV
MODE
1kHz
845Hz
2.6kHz
±2.2mV
±3.3mV
422Hz
422Hz
1.3kHz
±2.2mV
±3.3mV
26Hz
(Filtered Mode)
26Hz
82Hz
±2.2mV
±3.3mV
Note: TME is the Total Measurement Error.
Mode 27kHz (Fast): In this mode, the ADC has maximum
throughput but has some increase in TME (Total Measurement Error). So this mode is also referred to as the fast
Rev. B
20
For more information www.analog.com
LTC6812-1
OPERATION
ADC Range and Resolution
The C inputs and GPIO inputs have the same range and
resolution. The ADC inside the LTC6812-1 has an approximate range from –0.82V to +5.73V. Negative readings are
rounded to 0V. The format of the data is a 16-bit unsigned
integer where the LSB represents 100μV. Therefore, a
reading of 0x80E8 (33,000 decimal) indicates a measurement of 3.3V.
1.0
NORMAL MODE
FILTERED MODE
0.9
PEAK NOISE (mV)
0.8
0.7
The specified range of the ADC is 0V to 5V. In Table 4,
the precision range of the ADC is arbitrarily defined as
0.5V to 4.5V. This is the range where the quantization
noise is relatively constant even in the lower OSR modes
(see Figure 2). Table 4 summarizes the total noise in this
range for all eight ADC operating modes. Also shown is
the noise free resolution. For example, 14-bit noise free
resolution in normal mode implies that the top 14 bits will
be noise free with a DC input, but that the 15th and 16th
Least Significant Bits (LSB) will flicker.
ADC Range vs Voltage Reference Value
0.6
0.5
0.4
0.3
0.2
0.1
0
For example, the total measurement noise versus input
voltage in normal and filtered modes is shown in Figure 2.
0
1
2
3
INPUT (V)
4
5
68121 F02
Figure 2. Measurement Noise vs Input Voltage
Delta-Sigma ADCs have quantization noise which depends
on the input voltage, especially at low oversampling ratios (OSR), such as in FAST mode. In some of the ADC
modes, the quantization noise increases as the input voltage
approaches the upper and lower limits of the ADC range.
Typical ADCs have a range which is exactly twice the
value of the voltage reference, and the ADC measurement error is directly proportional to the error in the
voltage reference. The LTC6812-1 ADC is not typical.
The absolute value of VREF1 is trimmed up or down to
compensate for gain errors in the ADC. Therefore, the
ADC Total Measurement Error (TME) specifications are
superior to the VREF1 specifications. For example, the
25°C specification of the Total Measurement Error when
measuring 3.300V in 7kHz (Normal) mode is ±2.2mV
and the 25°C specification for VREF1 is 3.150V ± 150mV.
Measuring Cell Voltages (ADCV Command)
The ADCV command initiates the measurement of the
battery cell inputs, pins C0 through C15. This command
has options to select the number of channels to measure
Table 4. ADC Range and Resolution
PRECISION
RANGE2
NOISE FREE
RESOLUTION3
27kHz (Fast)
±4mVP-P
10 Bits
14kHz
±1mVP-P
12 Bits
7kHz (Normal)
±250μVP-P
14 Bits
±150μVP-P
14 Bits
±100μVP-P
15 Bits
1kHz
±100μVP-P
15 Bits
422Hz
±100μVP-P
15 Bits
26Hz (Filtered)
±50μVP-P
16 Bits
3kHz
2kHz
FULL
RANGE1
SPECIFIED
RANGE
MAX NOISE
MODE
–0.8192V to
5.7344V
0V to 5V
0.5V to 4.5V
LSB
100μV
FORMAT
Unsigned
16 Bits
1. Negative readings are rounded to 0V.
2. PRECISION RANGE is the range over which the noise is less than MAX NOISE.
3. NOISE FREE RESOLUTION is a measure of the noise level within the PRECISION RANGE.
Rev. B
For more information www.analog.com
21
LTC6812-1
OPERATION
tCYCLE
tSKEW2
tREFUP
SERIAL
INTERFACE
ADCV + PEC
ADC3
MEASURE
C11 TO C10
MEASURE
C12 TO C11
MEASURE
C15 TO C14
CALIBRATE
ADC2
MEASURE
C6 TO C5
MEASURE
C7 TO C6
MEASURE
C10 TO C9
CALIBRATE
ADC1
MEASURE
C1 TO C0
MEASURE
C2 TO C1
MEASURE
C5 TO C4
CALIBRATE
t1M
t0
t2M t4M
t5M
t5C
68121 F03
Figure 3. Timing for ADCV Command Measuring All 15 Cells
Table 5. Conversion and Synchronization Times for ADCV Command Measuring All 15 Cells in Different Modes
CONVERSION TIMES (IN μs)
SYNCHRONIZATION TIME (IN μs)
MODE
t0
t1M
t2M
t4M
t5M
t5C
tSKEW2
27kHz
0
58
104
198
14kHz
0
87
163
314
244
937
187
390
1,083
303
7kHz
0
145
279
547
681
1,956
536
3kHz
0
261
2kHz
0
494
512
1,012
1,263
2,537
1,001
977
1,943
2,426
3,701
1,932
1kHz
0
960
1,908
3,805
4,753
6,028
3,794
422Hz
0
1,890
3,770
7,529
9,408
10,683
7,518
26Hz
0
29,818
59,624
119,238
149,044
167,774
119,227
tREFUP
SERIAL
INTERFACE
ADCV + PEC
ADC3
MEASURE
C14 TO C13
CALIBRATE
ADC2
MEASURE
C9 TO C8
CALIBRATE
ADC1
MEASURE
C4 TO C3
CALIBRATE
t0
t1M
t1C
68121 F04
Figure 4. Timing for ADCV Command Measuring 3 Cells
Rev. B
22
For more information www.analog.com
LTC6812-1
OPERATION
and the ADC mode. See the section on Commands for the
ADCV command format.
Figure 3 illustrates the timing of the ADCV command
which measures all fifteen cells. After the receipt of the
ADCV command to measure all 15 cells, ADC1 sequentially
measures the bottom 5 cells. ADC2 measures the middle
5 cells and ADC3 measures the top 5 cells. After the cell
measurements are complete, each channel is calibrated
to remove any offset errors.
Table 5 shows the conversion times for the ADCV command measuring all 15 cells. The total conversion time is
given by t5C which indicates the end of the calibration step.
Figure 4 illustrates the timing of the ADCV command
that measures only three cells.
Table 6 shows the conversion time for the ADCV command
measuring only 3 cells. t1C indicates the total conversion
time for this command.
Table 6. Conversion Times for ADCV Command Measuring
3 Cells in Different Modes
CONVERSION TIMES (IN μs)
MODE
t0
t1M
t1C
27kHz
0
58
203
14kHz
0
87
232
7kHz
0
145
407
3kHz
0
261
523
2kHz
0
494
756
1kHz
0
960
1,221
422Hz
0
1,890
2,152
26Hz
0
29,818
33,570
Under/Overvoltage Monitoring
Whenever the C inputs are measured, the results are compared to undervoltage and overvoltage thresholds stored
in memory. If the reading of a cell is above the overvoltage
limit, a bit in memory is set as a flag. Similarly, measurement results below the undervoltage limit cause a flag to
be set. The overvoltage and undervoltage thresholds are
stored in Configuration Register Group A. The flags are
stored in Status Register Group B and Auxiliary Register
Group D.
Auxiliary (GPIO) Measurements (ADAX Command)
The ADAX command initiates the measurement of the
GPIO inputs. This command has options to select which
GPIO input to measure (GPIO1–9) and which ADC mode
to use. The ADAX command also measures the 2nd reference. There are options in the ADAX command to measure
subsets of the GPIOs and the 2nd reference separately
or to measure all nine GPIOs and the 2nd reference in a
single command. See the section on Commands for the
ADAX command format. All auxiliary measurements are
relative to the V– pin voltage. This command can be used
to read external temperatures by connecting temperature
sensors to the GPIOs. These sensors can be powered from
the 2nd reference which is also measured by the ADAX
command, resulting in precise ratiometric measurements.
Figure 5 illustrates the timing of the ADAX command
measuring all GPIOs and the 2nd reference. All 10 measurements are carried out on ADC1 alone. The 2nd reference
is measured after GPIO5 and before GPIO6.
tCYCLE
tSKEW
tREFUP
SERIAL
INTERFACE
ADAX + PEC
ADC3
ADC2
MEASURE
GPIO1
ADC1
t0
MEASURE
GPIO2
t1M
MEASURE
GPIO5
t2M t4M
MEASURE
2ND REF
t5M
MEASURE
GPIO6
t6M
MEASURE
GPIO9
t7M t9M
CALIBRATE
t10M
t10C
68121 F05
Figure 5. Timing for ADAX Command Measuring All GPIOs and 2nd Reference
Rev. B
For more information www.analog.com
23
LTC6812-1
OPERATION
Table 7. Conversion and Synchronization Times for ADAX Command Measuring All GPIOs and 2nd Reference in Different Modes
CONVERSION TIMES (IN μs)
MODE
t0
t1M
t2M
t9M
SYNCHRONIZATION TIME (IN μs)
t10M
t10C
tSKEW
27kHz
0
58
104
431
478
1,825
420
14kHz
0
87
163
693
769
2,116
682
7kHz
0
145
279
1,217
1,350
3,862
1,205
3kHz
0
261
512
2,264
2,514
5,025
2,253
2kHz
0
494
977
4,358
4,841
7,353
4,347
1kHz
0
960
1,908
8,547
9,496
12,007
8,536
422Hz
0
1,890
3,770
16,926
18,805
21,316
16,915
26Hz
0
29,818
59,624
268,271
298,078
335,498
268,260
Measuring Cell Voltages and GPIOs (ADCVAX
Command)
Table 7 shows the conversion time for the ADAX command
measuring all of the GPIOs and the 2nd reference. t10C
indicates the total conversion time.
The ADCVAX command combines fifteen cell measurements with two GPIO measurements (GPIO1 and GPIO2).
This command simplifies the synchronization of battery
cell voltage and current measurements when current sensors are connected to GPIO1 or GPIO2 inputs. Figure 6
illustrates the timing of the ADCVAX command. See the
section on Commands for the ADCVAX command format.
The synchronization of the current and voltage measurements, tSKEW1 and tSKEW3, in Fast mode is within 194μs
and 147µs, respectively.
Auxiliary (GPIO) Measurements with Digital
Redundancy (ADAXD Command)
The ADAXD command operates similarly to the ADAX
command except that an additional diagnostic is performed using digital redundancy. PS[1:0] in Configuration
Register Group B must be set to 0 or 1 during ADAXD to
enable redundancy. See the ADC Conversion with Digital
Redundancy section.
The execution time of ADAX and ADAXD is the same.
tCYCLE
tSKEW1
tREFUP
SERIAL
INTERFACE
Table 8 shows the conversion and synchronization time
for the ADCVAX command in different modes. The total
conversion time for the command is given by t7C.
tSKEW3
ADCVAX + PEC
ADC3
MEASURE
C11 TO C10
MEASURE
C12 TO C11
MEASURE
C13 TO C12
MEASURE
C14 TO C13
MEASURE
C15 TO C14
CALIBRATE
ADC2
MEASURE
C6 TO C5
MEASURE
C7 TO C6
MEASURE
C8 TO C7
MEASURE
C9 TO C8
MEASURE
C10 TO C9
CALIBRATE
ADC1
MEASURE
C1 TO C0
MEASURE
C2 TO C1
MEASURE
C3 TO C2
MEASURE
C4 TO C3
MEASURE
C5 TO C4
CALIBRATE
t0
t1M
t2M
MEASURE
GPIO1
t3M
MEASURE
GPIO2
t4M
t5M
t6M
t7M
t7C
68121 F06
Figure 6. Timing of ADCVAX Command
Rev. B
24
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LTC6812-1
OPERATION
Table 8. Conversion and Synchronization Times for ADCVAX Command in Different Modes
CONVERSION TIMES (IN μs)
MODE
t0
t1M
t2M
t3M
t4M
t5M
SYNCHRONIZATION TIMES (IN μs)
t6M
t7M
t7C
tSKEW1
tSKEW3
27kHz
0
58
104
151
205
252
306
352
1,328
194
147
14kHz
0
87
163
238
321
397
480
556
1,531
310
235
7kHz
0
145
279
413
554
688
829
963
2,753
543
409
3kHz
0
261
512
762
1,020
1,270
1,527
1,778
3,568
1,008
758
2kHz
0
494
977
1,460
1,950
2,433
2,924
3,407
5,197
1,939
1,456
1kHz
0
960
1,908
2,857
3,812
4,761
5,717
6,665
8,455
3,801
2,853
422Hz
0
1,890
3,770
5,649
7,536
9,415
11,302
13,181
14,971
7,525
5,645
26Hz
0
29,818
59,624
89,431
119,234
89,427
119,245 149,052 178,866 208,672 234,899
DATA ACQUISITION SYSTEM DIAGNOSTICS
The battery monitoring data acquisition system is comprised of the multiplexers, ADCs, 1st reference, digital filters
and memory. To ensure long term reliable performance
there are several diagnostic commands which can be used
to verify the proper operation of these circuits.
Measuring Internal Device Parameters (ADSTAT
Command)
The ADSTAT command is a diagnostic command that
measures the following internal device parameters: Sum
of All Cells (SC), Internal Die Temperature (ITMP), Analog
Table 9 shows the conversion time of the ADSTAT command measuring all 4 internal parameters. t4C indicates
the total conversion time for the ADSTAT command.
tSKEW
tREFUP
SERIAL
INTERFACE
Power Supply (VA) and the Digital Power Supply (VD).
These parameters are described in the section below.
All the 8 ADC modes described earlier are available for
these conversions. See the section on Commands for the
ADSTAT command format. Figure 7 illustrates the timing
of the ADSTAT command measuring all 4 internal device
parameters.
tCYCLE
ADSTAT + PEC
ADC3
ADC2
MEASURE
SC
ADC1
t0
MEASURE
ITMP
t1M
MEASURE
VD
t2M t3M
CALIBRATE
SC
t4M
CALIBRATE
ITMP
t1C
CALIBRATE
VD
t2C t3C
t4C
68121 F07
Figure 7. Timing for ADSTAT Command Measuring SC, ITMP, VA, VD
Rev. B
For more information www.analog.com
25
LTC6812-1
OPERATION
Table 9. Conversion and Synchronization Times for ADSTAT Command Measuring SC, ITMP, VA, VD in Different Modes
CONVERSION TIMES (IN μs)
MODE
t0
t1M
t2M
t3M
t4M
t4C
tSKEW
27kHz
0
58
104
151
198
742
140
14kHz
0
87
163
238
314
858
227
7kHz
0
145
279
413
547
1,556
402
3kHz
0
261
512
762
1,012
2,022
751
2kHz
0
494
977
1,460
1,943
2,953
1,449
1kHz
0
960
1,908
2,857
3,805
4,814
2,845
422Hz
0
1,890
3,770
5,649
7,529
8,538
5,638
26Hz
0
29,818
59,624
89,431
119,238
134,211
89,420
Sum of All Cells Measurement: The Sum of All Cells
measurement is the voltage between C15 and C0 with a
30:1 attenuation. The 16-bit ADC value of Sum of All Cells
measurement (SC) is stored in Status Register Group
A. Any potential difference between the C0 and V– pins
results in an error in the SC measurement equal to this
difference. From the SC value, the sum of all cell voltage
measurements is given by:
Sum of All Cells = SC • 30 • 100 µV
Internal Die Temperature: The ADSTAT command can
measure the internal die temperature. The 16-bit ADC
value of the die temperature measurement (ITMP) is
stored in Status Register Group A. From ITMP, the actual
die temperature is calculated using the expression:
Internal Die Temperature (°C) =
SYNCHRONIZATION TIME (IN μs)
Digital Power Supply Measurement (VREGD) =
VD • 100 µV
The value of VREG is determined by external components.
VREG should be between 4.5V and 5.5V to maintain accuracy. The value of VREGD is determined by internal
components. The normal range of VREGD is 2.7V to 3.6V.
Measuring Internal Device Parameters with Digital
Redundancy (ADSTATD Command)
The ADSTATD command operates similarly to the ADSTAT
command except that an additional diagnostic is performed
using digital redundancy. PS[1:0] in Configuration Register Group B must be set to 0 or 1 during ADSTATD to
enable redundancy. See the ADC Conversion with Digital
Redundancy section.
The execution time of ADSTAT and ADSTATD is the same.
⎛ 100 µV ⎞
ITMP • ⎜
°C – 276°C
⎝ 7.6mV ⎟⎠
ADC Conversion with Digital Redundancy
Power Supply Measurements: The ADSTAT command is
also used to measure the Analog Power Supply (VREG)
and Digital Power Supply (VREGD). The 16-bit ADC value
of the analog power supply measurement (VA) is stored
in Status Register Group A. The 16-bit ADC value of the
digital power supply measurement (VD) is stored in Status
Register Group B. From VA and VD, the power supply
measurements are given by:
Analog Power Supply Measurement (VREG) =
VA • 100 µV
Each of the three internal ADCs contains its own digital
integration and differentiation machine. The LTC6812-1
also contains a fourth digital integration and differentiation
machine that is used for redundancy and error checking.
All of the ADC and self test commands, except ADAX and
ADSTAT, can operate with digital redundancy. This includes
ADCV, ADOW, CVST, ADOL, ADAXD, AXOW, AXST, ADSTATD,
STATST, ADCVAX and ADCVSC. When performing an ADC
conversion with redundancy, the analog modulator sends
its bit stream to both the primary digital machine and the
redundant digital machine. At the end of the conversion
Rev. B
26
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LTC6812-1
OPERATION
the results from the two machines are compared. If any
result bit mismatch is detected then a digital redundancy
fault code is stored in place of the ADC result. The digital
redundancy fault code is a value of 0xFF0X. This is detectable because it falls outside the normal result range of
0x0000 to 0xDFFF. The last four bits are used to indicate
which nibble(s) of the result values did not match.
However, the user can choose an ADC redundancy path
selection by writing to the PS[1:0] bits in Configuration
Register Group B.
Table 10 shows all possible ADC path redundancy
selections.
When the FDRF bit in Configuration Register Group B is
written to 1 it will force the digital redundancy comparison
to fail during subsequent ADC conversions.
Indication of Digital Redundancy Fault Codes
DIGITAL REDUNDANCY FAULT
CODE 4 LSBs
INDICATION
0b0XXX
No fault detected in bits 15–12
0b1XXX
Fault detected in bits 15–12
0bX0XX
No fault detected in bits 11–8
0bX1XX
Fault detected in bits 11–8
0bXX0X
No fault detected in bits 7–4
0bXX1X
Fault detected in bits 7–4
0bXXX0
No fault detected in bits 3–0
0bXXX1
Fault detected in bits 3–0
0b0000
The digital redundancy feature will
not write this value of all zeros in the
last 4 bits
Measuring Cell Voltages and Sum of All Cells
(ADCVSC Command)
The ADCVSC command combines fifteen cell measurements and the measurement of Sum of All Cells. This
command simplifies the synchronization of the individual
battery cell voltage and the total Sum of All Cells measurements. Figure 8 illustrates the timing of the ADCVSC
command. See the section on Commands for the ADCVSC
command format. The synchronization of the cell voltage
and Sum of All Cells measurements, tSKEW4 and tSKEW5, in
Fast mode is within 147μs and 101µs, respectively.
Table 11 shows the conversion and synchronization time
for the ADCVSC command in different modes. The total
conversion time for the command is given by t6C.
Since there is a single redundant digital machine, it can
apply redundancy to only one ADC at a time. By default, the
LTC6812-1 will automatically select ADC path redundancy.
Table 10. ADC Path Redundancy Selection
PS[1:0] = 00
PS[1:0] = 01
PATH SELECT
REDUNDANT
MEASURE
Cells 1, 6, 11
ADC1
Cells 2, 7, 12
PS[1:0] = 10
PS[1:0] = 11
PATH SELECT
REDUNDANT
MEASURE
Cell 1
ADC1
ADC2
Cell 7
ADC1
Cells 3, 8, 13
ADC3
Cell 13
ADC1
Cell 3
ADC2
Cell 8
ADC3
Cell 13
Cells 4, 9, 14
ADC1
Cell 4
ADC1
Cell 4
ADC2
Cell 9
ADC3
Cell 14
MEASURE
PATH SELECT
REDUNDANT
MEASURE
PATH SELECT
REDUNDANT
MEASURE
Cell 1
ADC2
Cell 6
ADC3
Cell 11
Cell 2
ADC2
Cell 7
ADC3
Cell 12
Cells 5, 10, 15
ADC2
Cell 10
ADC1
Cell 5
ADC2
Cell 10
ADC3
Cell 15
Cell 6 (ADOL)
ADC2
Cell 6
ADC1
Cell 6
ADC2
Cell 6
ADC3
N/A
Cell 11 (ADOL)
ADC2
Cell 11
ADC1
N/A
ADC2
Cell 11
ADC3
Cell 11
GPIO[n]*
ADC1
GPIO[n]
ADC1
GPIO[n]
ADC2
N/A
ADC3
N/A
2nd Reference*
ADC1
2nd Ref
ADC1
2nd Ref
ADC2
N/A
ADC3
N/A
SC*
ADC1
SC
ADC1
SC
ADC2
N/A
ADC3
N/A
ITMP*
ADC1
ITMP
ADC1
ITMP
ADC2
N/A
ADC3
N/A
VA*
ADC1
VA
ADC1
VA
ADC2
N/A
ADC3
N/A
VD*
ADC1
VD
ADC1
VD
ADC2
N/A
ADC3
N/A
*Note that the ADAX and ADSTAT commands are identical to the ADAXD and ADSTATD commands except that ADAX and ADSTAT will not apply any
digital redundancy.
Rev. B
For more information www.analog.com
27
LTC6812-1
OPERATION
tCYCLE
tREFUP
SERIAL
INTERFACE
tSKEW4
tSKEW5
ADCVSC + PEC
ADC3
MEASURE
C11 TO C10
MEASURE
C12 TO C11
MEASURE
C13 TO C12
MEASURE
C14 TO C13
MEASURE
C15 TO C14
CALIBRATE
ADC2
MEASURE
C6 TO C5
MEASURE
C7 TO C6
MEASURE
C8 TO C7
MEASURE
C9 TO C8
MEASURE
C10 TO C9
CALIBRATE
ADC1
MEASURE
C1 TO C0
MEASURE
C2 TO C1
MEASURE
C3 TO C2
MEASURE
C4 TO C3
MEASURE
C5 TO C4
CALIBRATE
t1M
t0
t2M
MEASURE
SC
t3M
t4M
t5M
t6M
t6C
68121 F08
Figure 8. Timing for ADCVSC Command Measuring All 15 Cells, SC
Table 11. Conversion and Synchronization Times for ADCVSC Command in Different Modes
CONVERSION TIMES (IN μs)
SYNCHRONIZATION TIMES (IN μs)
MODE
t0
t1M
t2M
t3M
t4M
t5M
t6M
t6C
tSKEW4
tSKEW5
27kHz
0
58
104
151
205
259
306
1,147
147
101
14kHz
0
87
163
238
321
404
480
1,322
235
159
7kHz
0
145
279
413
554
695
829
2,369
409
275
3kHz
0
261
512
762
1,020
1,277
1,527
3,067
758
508
2kHz
0
494
977
1,460
1,950
2,441
2,924
4,463
1,456
973
1kHz
0
960
1,908
2,857
3,812
4,768
5,717
7,256
2,853
1,904
422Hz
0
1,890
3,770
5,649
7,536
9,423
11,302
12,842
5,645
3,766
26Hz
0
29,818
59,624
89,431
119,245
149,059
178,866
201,351
89,427
59,621
Rev. B
28
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LTC6812-1
OPERATION
Table 12 shows the conversion time for the ADOL command.
t2C indicates the total conversion time for this command.
Overlap Cell Measurement (ADOL Command)
The ADOL command first simultaneously measures Cell 6
with ADC1 and ADC2. Then it simultaneously measures
Cell 11 with both ADC2 and ADC3. The host can compare
the results against each other to look for inconsistencies
which may indicate a fault. The result of the Cell 6 measurement from ADC2 is placed in Cell Voltage Register
Group C where the Cell 7 result normally resides. The
result from ADC1 is placed in Cell Voltage Register Group
C where the Cell 8 result normally resides. The result of
the Cell 11 measurement from ADC3 is placed in Cell Voltage Register Group E where the Cell 13 result normally
resides. The result from ADC2 is placed in Cell Voltage
Register Group E where the Cell 14 result normally resides.
Figure 9 illustrates the timing of the ADOL command. See
the section on Commands for the ADOL command format.
Accuracy Check
Measuring an independent voltage reference is the best
means to verify the accuracy of a data acquisition system.
The LTC6812-1 contains a 2nd reference for this purpose.
The ADAX command will initiate the measurement of the
2nd reference. The results are placed in Auxiliary Register
Group B. The range of the result depends on the ADC1
measurement accuracy and the accuracy of the 2nd reference, including thermal hysteresis and long term drift.
Readings outside the range 2.990V to 3.014V (2.992V
to 3.012V for LTC6812I) indicate the system is out of
its specified tolerance. ADC2 is verified by comparing it
to ADC1 using the ADOL command. ADC3 is verified by
comparing it to ADC2 using the ADOL command.
tREFUP
SERIAL
INTERFACE
ADOL + PEC
MEASURE
C11 TO C10
ADC3
ADC2
MEASURE
C6 TO C5
ADC1
MEASURE
C6 TO C5
t0
CALIBRATE
C11 TO C10
MEASURE
C11 TO C10
CALIBRATE
C6 TO C5
CALIBRATE
C11 TO C10
CALIBRATE
C6 TO C5
t1M
t2M
t1C
t2C
68121 F09
Figure 9. Timing for ADOL Command
Table 12. Conversion Times for ADOL Command
CONVERSION TIMES (IN μs)
MODE
t0
t1M
t2M
t2C
27kHz
0
58
106
384
14kHz
0
87
164
442
7kHz
0
146
281
791
3kHz
0
262
513
1,024
2kHz
0
495
979
1,490
1kHz
0
960
1,910
2,420
422Hz
0
1,891
3,772
4,282
26Hz
0
29,818
59,626
67,119
Rev. B
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29
LTC6812-1
OPERATION
This is why a delta-sigma ADC is often referred to as an
oversampling converter.
MUX Decoder Check
The diagnostic command DIAGN ensures the proper operation of each multiplexer channel. The command cycles
through all channels and sets the MUXFAIL bit to 1 in
Status Register Group B if any channel decoder fails. The
MUXFAIL bit is set to 0 if the channel decoder passes the
test. The MUXFAIL is also set to 1 on power-up (POR) or
after a CLRSTAT command.
The self test commands verify the operation of the digital
filters and memory. Figure 10 illustrates the operation
of the ADC during self test. The output of the 1-bit pulse
density modulator is replaced by a 1-bit test signal. The
test signal passes through the digital filter and is converted
to a 16-bit value. The 1-bit test signal undergoes the same
digital conversion as the regular 1-bit signal from the
modulator, so the conversion time for any self test command is exactly the same as the corresponding regular
ADC conversion command. The 16-bit ADC value is stored
in the same register groups as the corresponding regular
ADC conversion command. The test signals are designed
to place alternating one-zero patterns in the registers.
Table 13 provides a list of the self test commands. If the
digital filters and memory are working properly, then the
registers will contain the values shown in Table 13. For
more details see the Commands section.
The DIAGN command takes about 400μs to complete if the
Core is in REFUP state and about 4.5ms to complete if the
Core is in STANDBY state. The polling methods described
in the section Polling Methods can be used to determine
the completion of the DIAGN command.
Digital Filter Check
The delta-sigma ADC is composed of a 1-bit pulse density modulator followed by a digital filter. A pulse density
modulated bit stream has a higher percentage of 1s for
higher analog input voltages. The digital filter converts
this high frequency 1-bit stream into a single 16-bit word.
PULSE DENSITY
MODULATED
BIT STREAM
MUX
ANALOG
INPUT
1-BIT
MODULATOR
DIGITAL
FILTER
1
SELF TEST
PATTERN
GENERATOR
16
RESULTS
REGISTER
TEST SIGNAL
68121 F10
Figure 10. Operation of LTC6812-1 ADC Self Test
Table 13. Self Test Command Summary
OUTPUT PATTERN IN DIFFERENT ADC MODES
COMMAND
CVST
AXST
STATST
SELF TEST OPTION
27kHz
14kHz
7kHz, 3kHz, 2kHz,
1kHz, 422Hz, 26Hz
ST[1:0] = 01
0x9565
0x9553
0x9555
ST[1:0] = 10
0x6A9A
0x6AAC
0x6AAA
ST[1:0] = 01
0x9565
0x9553
0x9555
ST[1:0] = 10
0x6A9A
0x6AAC
0x6AAA
ST[1:0] = 01
0x9565
0x9553
0x9555
ST[1:0] = 10
0x6A9A
0x6AAC
0x6AAA
RESULTS REGISTER GROUPS
C1V to C15V
(CVA, CVB, CVC, CVD, CVE)
G1V to G9V, REF
(AUXA, AUXB, AUXC, AUXD)
SC, ITMP, VA, VD
(STATA, STATB)
Rev. B
30
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LTC6812-1
OPERATION
ADC Clear Commands
LTC6812-1 has 3 clear ADC commands: CLRCELL, CLRAUX
and CLRSTAT. These commands clear the registers that
store all ADC conversion results.
The CLRCELL command clears Cell Voltage Register
Groups A, B, C, D and E. All bytes in these registers are
set to 0xFF by CLRCELL command.
The CLRAUX command clears Auxiliary Register Groups A,
B, C and D. All bytes in these registers, except the last four
registers of Group D, are set to 0xFF by CLRAUX command.
The CLRSTAT command clears Status Register Groups A
and B except the REV and RSVD bits in Status Register
Group B. A read back of REV will return the revision code
of the part. RSVD bits always read back 0s. All OV and
UV flags, MUXFAIL bit, and THSD bit in Status Register
Group B and also in Auxiliary Register Group D are set
to 1 by CLRSTAT command. The THSD bit is set to 0 after
RDSTATB command. The registers storing SC, ITMP, VA
and VD are all set to 0xFF by CLRSTAT command.
Open Wire Check (ADOW Command)
The ADOW command is used to check for any open wires
between the ADCs of the LTC6812-1 and the external cells.
This command performs ADC conversions on the C pin
inputs identically to the ADCV command, except two internal current sources sink or source current into the two
C pins while they are being measured. The pull-up (PUP)
bit of the ADOW command determines whether the current
sources are sinking or sourcing 100μA.
The following simple algorithm can be used to check for
an open wire on any of the 16 C pins:
1. Run the 15-cell command ADOW with PUP = 1 at least
twice. Read the cell voltages for cells 1 through 15
once at the end and store them in array CELLPU(n).
2. Run the 15-cell command ADOW with PUP = 0 at least
twice. Read the cell voltages for cells 1 through 15
once at the end and store them in array CELLPD(n).
3. Take the difference between the pull-up and pull-down
measurements made in above steps for cells 2 to 15:
CELL∆(n) = CELLPU(n) – CELLPD(n).
4. For all values of n from 1 to 14: If CELL∆(n+1)
40) to supply the necessary supply current. The peak
VREG current requirement of the LTC6812-1 approaches
35mA when simultaneously communicating over isoSPI
and making ADC conversions. If the VREG pin is required
to support any additional load, a transistor with an even
higher Beta may be required.
bypassed with a 1µF capacitor. Larger capacitance should
be avoided since this will increase the wake-up time of the
LTC6812-1. Some attention should be given to the thermal characteristic of the NPN, as there can be significant
heating with a high collector voltage.
Improved Regulator Power Efficiency
For improved efficiency when powering the LTC6812-1
from the cell stack, VREG may be powered from a DC/DC
converter, rather than the NPN pass transistor. An ideal
circuit is based on Analog Devices LT8631 step-down
regulator, as shown in Figure 33. A 100Ω resistor is
recommended between the battery stack and the LT8631
input; this will prevent in-rush current when connecting to
the stack and it will reduce conducted EMI. The EN/UVLO
pin should be connected to the DRIVE pin, which will put
the LT8631 into a low power state when the LTC6812-1
is in the SLEEP state.
100Ω
LTC6812-1
WDT
DRIVE
DZT5551
0.1µF
VIN
18V TO
100V
100Ω
VREG
2.2µF
DTEN
VREF1
1µF
VREF2
V–
1µF
100pF
1µF
VIN
EN/UV
BST
MODE
SW
PG
IND
TR/SS
25.5k
68121 F32
Figure 32. Simple VREG Power Source Using NPN
Pass Transistor
GND
2.2µF
0.1µF
22µH
5V
VOUT
4.7pF
LT8631
RT
V–
INTVCC
1M
FB
68121 F33
VREG
22µF
191k
Figure 33. VREG Powered From Cell Stack with High
Efficiency Regulator
The NPN collector can be powered from any voltage
source that is a minimum 6V above V–. This includes the
cells that are being monitored, or an unregulated power
supply. A 100Ω/100nF RC decoupling network is recommended for the collector power connection to protect the
NPN from transients. The emitter of the NPN should be
Rev. B
For more information www.analog.com
69
LTC6812-1
APPLICATIONS INFORMATION
INTERNAL PROTECTION AND FILTERING
Filtering of Cell and GPIO Inputs
Internal Protection Features
The LTC6812-1 uses a delta-sigma ADC, which includes a
delta-sigma modulator followed by a SINC3 finite impulse
response (FIR) digital filter. This greatly relaxes input
filtering requirements. Furthermore, the programmable
oversampling ratio allows the user to determine the best
trade-off between measurement speed and filter cutoff
frequency. Even with this high order low pass filter, fast
The LTC6812-1 incorporates various ESD safeguards to
ensure robust performance. An equivalent circuit showing
the specific protection structures is shown in Figure 34.
Zener-like suppressors are shown with their nominal
clamp voltage, and the unmarked diodes exhibit standard
PN junction behavior.
64
IPB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
V+
63
62
IMB
61
SCK
CSB
60
V–
59
V–
58
57
ICMP
56
IBIAS
55
WDT
54
ISOMD SDO
53
52
SDI
51
DTEN
50
VREF1
49
VREF2
DRIVE
120V
VREG
NC
GPIO9
NC
GPIO8
C15
GPIO7
S15
GPIO6
24V
C14
GPIO5
S14
GPIO4
C13
GPIO3
LTC6812-1
S13
GPIO2
C12
GPIO1
S12
C0
C11
24V
S1
S11
C1
NC
24V
24V
24V
NC
24V
S2
C2
C10
S3
S10
C9
17
18
S9
19
C8
20
S8
21
C7
22
S7
23
C6
24
S6
25
NC
26
NC
27
C5
28
S5
29
C4
30
S4
31
C3
32
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
68121 F34
NOTE: ZENER VOLTAGE IS 8V UNLESS MARKED OTHERWISE.
Figure 34. Internal ESD Protection Structures of the LTC6812-1
Rev. B
70
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LTC6812-1
APPLICATIONS INFORMATION
transient noise can still induce some residual noise in measurements, especially in the faster conversion modes. This
can be minimized by adding an RC low pass decoupling to
each ADC input, which also helps reject potentially damaging high energy transients. Adding more than about 100Ω
to the ADC inputs begins to introduce a systematic error
in the measurement, which can be improved by raising
the filter capacitance or mathematically compensating in
software with a calibration procedure. For situations that
demand the highest level of battery voltage ripple rejection, grounded capacitor filtering is recommended. This
configuration has a series resistance and capacitors that
decouple HF noise to V–. In systems where noise is less
periodic or higher oversample rates are in use, a differential
capacitor filter structure is adequate. In this configuration
there are series resistors to each input, but the capacitors
connect between the adjacent C pins. However, the differential capacitor sections interact. As a result, the filter
response is less consistent and results in less attenuation
than predicted by the RC, by approximately a decade. Note
that the capacitors only see one cell of applied voltage (thus
smaller and lower cost) and tend to distribute transient
energy uniformly across the IC (reducing stress events
on the internal protection structure). Figure 35 shows the
two methods schematically. ADC accuracy varies with R, C
as shown in the Typical Performance curves, but error is
minimized if R = 100Ω and C = 10nF. The GPIO pins will
always use a grounded capacitor configuration because
the measurements are all with respect to V–.
100Ω
CELL2
C2
3.3k
BSS308PE
33Ω
LTC6812-1
10nF
100Ω
CELL1
S2
C1
3.3k
BSS308PE
33Ω
S1
10nF
100Ω
C0
10nF
BATTERY V–
V–
(a) Differential Capacitor Filter
100Ω
CELL2
C2
3.3k
BSS308PE
33Ω
100Ω
CELL1
LTC6812-1
C1
3.3k
BSS308PE
33Ω
S2
C *
C
100Ω
S1
*
C0
C
BATTERY V–
*
V–
*6.8V ZENERS RECOMMENDED IF C ≥ 100nF
68121 F35
(b) Grounded Capacitor Filter
Figure 35. Input Filter Structure Configurations
Rev. B
For more information www.analog.com
71
LTC6812-1
APPLICATIONS INFORMATION
Using Nonstandard Cell Input Filters
A cell pin filter of 100Ω and 10nF is recommended for all
applications. This filter provides the best combination of
noise rejection and Total Measurement Error (TME) performance. In applications that use C pin RC filters larger
than 100Ω/10nF there may be additional measurement
error. Figure 36a shows how both total TME and TME
variation increase as the RC time constant increases. The
increased error is related to the MUX settling. It is possible
to reduce TME levels to near data sheet specifications by
implementing an extra single channel conversion before
issuing a standard all channel ADCV command. Figure 37a
shows the standard ADCV command sequence. Figure 37b
and 37c show the recommended command sequence
and timing that will allow the MUX to settle. The purpose
of the modified procedure is to allow the MUX to settle
at C1/C6/C11 before the start of the measurement cycle.
The delay between the C1/C6/C11 ADCV command and
the All Channel ADCV command is dependent on the time
constant of the RC being used. The general guidance is to
wait 6τ between the C1/C6/C11 ADCV command and the All
Channel ADCV command. Figure 36b shows the expected
TME when using the recommended command sequence.
5
CELL MEASUREMENT ERROR (mV)
CELL MEASUREMENT ERROR (mV)
5
0
–5
–10
–15
100
100nF
10nF
1µF
1k
INPUT RESISTANCE, R (Ω)
0
–5
–10
–15
100
10k
100nF
10nF
1µF
1k
INPUT RESISTANCE, R (Ω)
68121 F36a
10k
68121 F36b
(a) Cell Measurement Error Range vs Input RC Values
(b) Cell Measurement Error vs Input RC Values
(Extra Conversion a nd Delay Before Measurement)
Figure 36. Cell Measurement TME
(a)
ADCV (all cells)
Delay
RDCVA-E
(b)
ADCV (C1/C6/C11)
Delay 6τ
ADCV (all cells)
CNV Time
RDCVA-E
(c)
ADCV (all cells)
CNV Time
RDCVA-E
ADCV (C1/C6/C11)
Delay 6τ
68121 F37
Figure 37. ADC Command Order
Rev. B
72
For more information www.analog.com
LTC6812-1
APPLICATIONS INFORMATION
but the filter resistor must remain small, typically around
10Ω to reduce the effect on the balance current.
CELL BALANCING
Cell Balancing with Internal MOSFETs
With passive balancing, if one cell in a series stack becomes
overcharged, an S output can slowly discharge this cell
by connecting it to a resistor. Each S output is connected
to an internal N-channel MOSFET with a maximum on
resistance of 10Ω. An external resistor should be connected in series with these MOSFETs to allow most of the
heat to be dissipated outside of the LTC6812-1 package,
as illustrated in Figure 38a.
The internal discharge switches (MOSFETs) S1 through
S15 can be used to passively balance cells as shown in
Figure 38a with balancing current of 200mA or less (80mA
or less if the die temperature is over 95°C). Balancing
current larger than 200mA is not recommended for the
internal switches due to excessive die heating. When
discharging cells with the internal discharge switches, the
die temperature should be monitored. See the Thermal
Shutdown section.
Note that the anti-aliasing filter resistor is part of the discharge path, so it should be removed or reduced. Use of
an RC for added cell voltage measurement filtering is OK
RFILTER
+
LTC6812-1
C(n)
RDISCHARGE
1k
S(n)
CFILTER
RFILTER
C(n – 1)
(a) Internal Discharge Circuit
BSS308PE
+
C(n) LTC6812-1
Cell Balancing with External Transistors
For applications that require balancing currents above
200mA or large cell filters, the S outputs can be used to
control external transistors. The LTC6812-1 includes an
internal pull-up PMOS transistor with a 1k series resistor.
The S pins can act as digital outputs suitable for driving
the gate of an external MOSFET as illustrated in Figure 38b.
Figure 35 shows external MOSFET circuits that include RC
filtering. For applications with very low cell voltages the
PMOS in Figure 38b can be replaced with a PNP. When a
PNP is used, the resistor in series with the base should
be reduced.
Choosing a Discharge Resistor
When sizing the balancing resistor, it is important to know
the typical battery imbalance and the allowable time for cell
balancing. In most small battery applications, it is reasonable for the balancing circuitry to be able to correct for a
5% SOC (State of Charge) error with 5 hours of balancing.
For example a 5AHr battery with a 5% SOC imbalance
will have approximately 250mA Hrs of imbalance. Using
a 50mA balancing current this could be corrected in 5
hours. With a 100mA balancing current, the error would
be corrected in 2.5 hours. In systems with very large
batteries, it becomes difficult to use passive balancing to
correct large SOC imbalances in short periods of time.
The excessive heat created during balancing generally
limits the balancing current. In large capacity battery applications, if short balancing times are required, an active
balancing solution should be considered. When choosing
a balance resistor, the following equations can be used to
help determine a resistor value:
Balance Current =
3.3k
%SOC_Imbalance • Battery Capacity
S(n)
RDISCHARGE
Number of Hours to Balance
Balance Resistor =
C(n – 1)
Nominal Cell Voltage
68121 F38
(b) External Discharge Circuit
Balance Current
Figure 38. Internal/External Discharge Circuits
Rev. B
For more information www.analog.com
73
LTC6812-1
APPLICATIONS INFORMATION
Active Cell Balancing
Applications that require 1A or greater of cell balancing
current should consider implementing an active balancing
system. Active balancing allows for much higher balancing
currents without the generation of excessive heat. Active
balancing also allows for energy recovery since most
of the balance current will be redistributed back to the
battery pack. Figure 39 shows a simple active balancing
implementation using Analog Devices LT8584. The LT8584
also has advanced features which can be controlled via
the LTC6812-1. See S Pin Pulsing Using the S Pin Control
Settings in this data sheet and the LT8584 data sheet for
more details.
MODULE +
2.5A AVERAGE
DISCHARGE
+
BAT 15
MODULE +
•
•
MODULE –
V+
ON OFF
LT8584
2.5A AVERAGE
DISCHARGE
+
BAT 2
S15
MODULE +
•
•
MODULE –
ON OFF
LT8584
2.5A AVERAGE
DISCHARGE
+
BAT 1
LTC6812-1
BATTERY STACK
MONITOR
S2
MODULE +
MODULE –
LT8584
If the discharge permitted (DCP) bit is high at the time of
a cell measurement command, the S pin discharge states
do not change during cell measurements. If the DCP bit
is low, S pin discharge states will be disabled while the
corresponding cell or adjacent cells are being measured.
If using an external discharge transistor, the relatively low
1kΩ impedance of the internal LTC6812-1 PMOS transistors should allow the discharge currents to fully turn off
before the cell measurement. Table 56 illustrates the ADCV
command with DCP = 0. In this table, OFF indicates that
the S pin discharge is forced off irrespective of the state
of the corresponding DCC[x] bit. ON indicates that the
S pin discharge will remain on during the measurement
period if it was ON prior to the measurement command.
In some cases, it is not possible for the automatic discharge control to eliminate all measurement error caused
by running the discharges. This is due to the discharge
transistor not turning off fast enough for the cell voltage
to completely settle before the measurement starts. For
the best measurement accuracy when running discharge,
the MUTE and UNMUTE commands should be used. The
MUTE command can be issued to temporarily disable all
discharge transistors before the ADCV command is issued.
After the cell conversion completes, an UNMUTE can be
sent to re-enable all discharge transistors that were previously ON. Using this method maximizes the measurement
accuracy with a very small time penalty.
Method to Verify Discharge Circuits
•
•
DISCHARGE CONTROL DURING CELL
MEASUREMENTS
ON OFF
S1
V–/C0
68121 F39
MODULE –
When using the internal discharge feature, the ability
to verify discharge functionality can be implemented in
software. In applications using an external discharge
MOSFET, an additional resistor can be added between
the battery cell and the source of the discharge MOSFET.
This will allow the system to test discharge functionality.
Figure 39. 15-Cell Battery Stack Module with Active Balancing
Rev. B
74
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LTC6812-1
APPLICATIONS INFORMATION
Table 56. Discharge Control During an ADCV Command with DCP = 0
CELL MEASUREMENT PERIODS
CELL CALIBRATION PERIODS
CELL
1/6/11
CELL
2/7/12
CELL
3/8/13
CELL
4/9/14
CELL
5/10/15
CELL
1/6/11
CELL
2/7/12
CELL
3/8/13
CELL
4/9/14
CELL
5/10/15
DISCHARGE PIN
t0 – t1M
t1M – t2M
t2M – t3M
t3M – t4M
t4M – t5M
t5M – t1C
t1C – t2C
t2C – t3C
t3C – t4C
t4C – t5C
S1
OFF
OFF
ON
ON
OFF
OFF
OFF
ON
ON
OFF
S2
OFF
OFF
OFF
ON
ON
OFF
OFF
OFF
ON
ON
S3
ON
OFF
OFF
OFF
ON
ON
OFF
OFF
OFF
ON
S4
ON
ON
OFF
OFF
OFF
ON
ON
OFF
OFF
OFF
S5
OFF
ON
ON
OFF
OFF
OFF
ON
ON
OFF
OFF
S6
OFF
OFF
ON
ON
OFF
OFF
OFF
ON
ON
OFF
S7
OFF
OFF
OFF
ON
ON
OFF
OFF
OFF
ON
ON
S8
ON
OFF
OFF
OFF
ON
ON
OFF
OFF
OFF
ON
S9
ON
ON
OFF
OFF
OFF
ON
ON
OFF
OFF
OFF
S10
OFF
ON
ON
OFF
OFF
OFF
ON
ON
OFF
OFF
S11
OFF
OFF
ON
ON
OFF
OFF
OFF
ON
ON
OFF
S12
OFF
OFF
OFF
ON
ON
OFF
OFF
OFF
ON
ON
S13
ON
OFF
OFF
OFF
ON
ON
OFF
OFF
OFF
ON
S14
ON
ON
OFF
OFF
OFF
ON
ON
OFF
OFF
OFF
S15
OFF
ON
ON
OFF
OFF
OFF
ON
ON
OFF
OFF
Rev. B
For more information www.analog.com
75
LTC6812-1
APPLICATIONS INFORMATION
Both circuits are shown in Figure 40. The functionality of
the discharge circuits can be verified by conducting cell
measurements and comparing measurements when the
discharge is off to measurements when the discharge is
on. The measurement taken when the discharge is on
requires that the discharge permit bit (DCP) be set. The
change in the measurement when the discharge is turned
on is calculable based on the resistor values. The following
algorithm can be used in conjunction with Figure 40 to
verify each discharge circuit:
1. Measure all cells with no discharging (all S outputs
off) and read and store the results.
2. Turn on S1, S6 and S11.
3. Measure C1–C0, C6–C5, C11–C10.
4. Turn off S1, S6 and S11.
6. Measure C2–C1, C7–C6, C12–C11.
7. Turn off S2, S7 and S12.
…
14. Turn on S5, S10 and S15.
15. Measure C5–C4, C10–C9, C15–C14.
16. Turn off S5, S10 and S15.
17. Read the Cell Voltage Register Groups to get the results
of Steps 2 thru 16.
18. Compare new readings with old readings. Each cell voltage reading should have decreased by a fixed percentage
set by RDISCHARGE and RFILTER for internal designs and
RDISCHARGE1 and RDISCHARGE2 for external MOSFET
designs. The exact amount of decrease depends on
the resistor values and MOSFET characteristics.
5. Turn on S2, S7 and S12.
LTC6812-1
C(n)
RFILTER
+
RDISCHARGE
1k
S(n)
CFILTER
RFILTER
C(n–1)
(a) Internal Discharge Circuit
RFILTER
RDISCHARGE1
+
3.3k
RDISCHARGE2
RFILTER
C(n) LTC6812-1
S(n)
C(n–1)
68121 F40
(b) External Discharge Circuit
Figure 40. Balancing Self Test Circuit
Rev. B
76
For more information www.analog.com
LTC6812-1
APPLICATIONS INFORMATION
DIGITAL COMMUNICATIONS
PEC Calculation
The Packet Error Code (PEC) can be used to ensure that
the serial data read from the LTC6812-1 is valid and has
not been corrupted. This is a critical feature for reliable
communication, particularly in environments of high noise.
The LTC6812-1 requires that a PEC be calculated for all
data being read from, and written to, the LTC6812-1. For
this reason it is important to have an efficient method for
calculating the PEC.
The C code below provides a simple implementation of a
lookup-table-derived PEC calculation method. There are
two functions. The first function init_PEC15_Table() should
only be called once when the microcontroller starts and
will initialize a PEC15 table array called pec15Table[]. This
table will be used in all future PEC calculations. The PEC15
table can also be hard coded into the microcontroller rather
than running the init_PEC15_Table() function at startup.
The pec15() function calculates the PEC and will return
the correct 15-bit PEC for byte arrays of any given length.
/************************************
Copyright 2012 Analog Devices, Inc. (ADI)
Permission to freely use, copy, modify, and distribute this software for any purpose with or
without fee is hereby granted, provided that the above copyright notice and this permission
notice appear in all copies: THIS SOFTWARE IS PROVIDED “AS IS” AND ADI DISCLAIMS ALL WARRANTIES INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL ADI BE LIABLE FOR ANY
SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM ANY USE
OF SAME, INCLUDING ANY LOSS OF USE OR DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
OTHER TORTUOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
***************************************/
int16 pec15Table[256];
int16 CRC15_POLY = 0x4599;
void init_PEC15_Table()
{
for (int i = 0; i < 256; i++)
{
remainder = i 0; --bit)
{
if (remainder & 0x4000)
{
remainder = ((remainder 7) ^ data[i]) & 0xff;//calculate PEC table address
remainder = (remainder 50m): IB = 1mA and K = 0.25
For applications with little system noise, setting IB to 0.5mA
is a good compromise between power consumption and
noise immunity. Using this IB setting with a 1:1 transformer
and RM = 100Ω, RB1 should be set to 3.01k and RB2 set
to 1k. With typical CAT5 twisted pair, these settings will
allow for communication up to 50m. For applications in
very noisy environments or that require cables longer than
50m it is recommended to increase IB to 1mA. Higher drive
current compensates for the increased insertion loss in
the cable and provides high noise immunity. When using
cables over 50m and a transformer with a 1:1 turns ratio
and RM = 100Ω, RB1 would be 1.5k and RB2 would be 499Ω.
The maximum clock rate of an isoSPI link is determined
by the length of the isoSPI cable. For cables 10m or less,
the maximum 1MHz SPI clock frequency is possible. As
the length of the cable increases, the maximum possible
SPI clock rate decreases. This dependence is a result of
the increased propagation delays that can create possible
timing violations. Figure 42 shows how the maximum data
rate reduces as the cable length increases when using a
CAT5 twisted pair.
Cable delay affects three timing specifications: tCLK, t6
and t7. In the Electrical Characteristics table, each of these
specifications is derated by 100ns to allow for 50ns of cable
RB2 = VICMP/IB
RB1 = (2/IB) – RB2
ISOLATION BARRIER
(MAY USE ONE OR TWO TRANFORMERS)
ISOMD
MASTER
SDO
SDI
SCK
CS
IPB
+
VA
IMB –
LTC6812-1
SDI
SDO
SCK
CSB
IBIAS
2V
RM
RB1
•
•
•
•
TWISTED-PAIR CABLE
WITH CHARACTERISTIC IMPEDANCE RM
+ IPA ISOMD
RM VA
LTC6812-1
– IMA
RB1
2V
VREG
IBIAS
ICMP
ICMP
RB2
RB2
68121 F41
Figure 41. isoSPI Circuit
Rev. B
78
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LTC6812-1
APPLICATIONS INFORMATION
1.2
CAT5 ASSUMED
DATA RATE (Mbps)
1.0
0.8
0.6
0.4
0.2
0
10
CABLE LENGTH (METERS)
1
100
68121 F42
Figure 42. Data Rate vs Cable Length
delay. For longer cables, the minimum timing parameters
may be calculated as shown below:
tCLK, t6 and t7 > 0.9μs + 2 • tCABLE (0.2m per ns)
Implementing a Modular isoSPI Daisy Chain
The hardware design of a daisy-chain isoSPI bus is identical for each device in the network due to the daisy-chain
point-to-point architecture. The simple design as shown in
Figure 41 is functional, but inadequate for most designs. The
termination resistor RM should be split and bypassed with
a capacitor as shown in Figure 43. This change provides
both a differential and a common mode termination, and
as such, increases the system noise immunity.
IP
49.9Ω 100µH CMC
100pF
49.9Ω
•
100pF
10nF
•
•
LTC6812-1
XFMR
•
IM
V–
a)
IP
100µH CMC
•
51Ω
10nF
IM
V–
51Ω
•
•
isoSPI LINK
•
LTC6812-1
CT XFMR
isoSPI LINK
The use of cables between battery modules, particularly
in automotive applications, can lead to increased noise
susceptibility in the communication lines. For high levels
of electromagnetic interference (EMC), additional filtering
is recommended. The circuit example in Figure 43 shows
the use of common mode chokes (CMC) to add common
mode noise rejection from transients on the battery lines.
The use of a center tapped transformer will also provide
additional noise performance. A bypass capacitor connected to the center tap creates a low impedance for
common mode noise (Figure 43b). Since transformers
without a center tap can be less expensive, they may be
preferred. In this case, the addition of a split termination
resistor and a bypass capacitor (Figure 43a) can enhance
the isoSPI performance. Large center tap capacitors
greater than 10nF should be avoided as they may prevent
the isoSPI common mode voltage from settling. Common
mode chokes similar to those used in Ethernet or CANbus
applications are recommended. Specific examples are
provided in Table 58.
An important daisy chain design consideration is the
number of devices in the isoSPI network. Both the number
of devices in a daisy chain and the length of wire between
devices determines the serial timing and affects data
latency and throughput.
For a daisy chain, it is necessary to extend minimum
required t5, the time from a rising chip select to the next
falling chip select (between commands), from 0.65μs to
2μs (see Figure 25).
This timing for t5 is set by the MCU on the SPI interface
of LTC6820 or the SPI interface of the bottom LTC6812-1
device if it is configured to operate in SPI mode. If necessary, LTC6812-1 will internally adjust the timing for t6 and
t5 while transmitting on the Master isoSPI port such that
t6 (Master port) > t6(GOV) and t5 (Master port) > t5(GOV).
This satisfies the timing requirement for the Slave port
of the next device.
10nF
68121 F43
b)
Figure 43. Daisy Chain Interface Components
Rev. B
For more information www.analog.com
79
LTC6812-1
APPLICATIONS INFORMATION
IPB
LTC6812-1
49.9Ω
10nF
49.9Ω
GNDD
IMB
IBIAS
ICMP
1k
1k
GNDD
IPA
49.9Ω
10nF
49.9Ω
V–
GNDD
GNDD
10nF*
•
IMA
•
GNDD
10nF*
GNDC
IPB
LTC6812-1
49.9Ω
10nF
49.9Ω
GNDC
IMB
IBIAS
ICMP
1k
1k
GNDC
IPA
49.9Ω
49.9Ω
V–
IMA
10nF
GNDC
GNDC
10nF*
•
GNDC
•
10nF*
GNDB
IPB
LTC6812-1
49.9Ω
49.9Ω
IMB
IBIAS
ICMP
1k
10nF
GNDB
1k
GNDB
IPA
49.9Ω
49.9Ω
V
–
IMA
10nF*
10nF
GNDB
GNDB
•
•
IP
LTC6820
49.9Ω
10nF*
GNDA
49.9Ω
IBIAS
ICMP
10nF
GNDA
IM
1k
GNDA
V–
GNDA
GNDB
* IF TRANSFORMER BEING USED HAS A CENTER TAP, IT SHOULD BE BYPASSED WITH A 10nF CAP
1k
68121 F44
Figure 44. Daisy Chain Interface Components on Single Board
Rev. B
80
For more information www.analog.com
LTC6812-1
APPLICATIONS INFORMATION
If the t5 requirement of 2μs is satisfied on the SPI interface,
there is no strict limitation on the maximum number of
devices in the daisy chain.
However, it is important to note that the serial read back
time, and the increased current consumption, might dictate
a practical limitation in the size of the network.
Connecting Multiple LTC6812-1s on the Same PCB
When connecting multiple LTC6812-1 devices on the same
PCB, only a single transformer is required between the
LTC6812-1 isoSPI ports. The absence of the cable also
reduces the noise levels on the communication lines and
often only a split termination is required. Figure 44 shows
an example application that has multiple LTC6812-1s
on the same PCB, communicating to the bottom MCU
through an LTC6820 isoSPI driver. If a transformer with
a center tap is used, a capacitor can be added for better
noise rejection. Additional noise filtering can be provided
with discrete common mode chokes (not shown) placed
to both sides of the single transformer.
On single board designs with low noise requirements,
it is possible for a simplified capacitor-isolated coupling
as shown in Figure 45 to replace the transformer. In this
circuit, the transformer is directly replaced by two 10nF
capacitors. A common mode choke (CMC) provides noise
rejection similar to application circuits using transformers. The circuit is designed to use IBIAS/ICMP settings
identical to the transformer circuit.
Connecting an MCU to an LTC6812-1 with an isoSPI
Data Link
The LTC6820 will convert standard 4-wire SPI into a
2-wire isoSPI link that can communicate directly with
the LTC6812-1. An example is shown in Figure 46. The
LTC6820 can be used in applications to provide isolation
between the microcontroller and the stack of LTC6812‑1s.
The LTC6820 also enables system configurations that
have the BMS controller at a remote location relative to
the LTC6812-1 devices and the battery pack.
Rev. B
For more information www.analog.com
81
LTC6812-1
APPLICATIONS INFORMATION
ACT45B-101-2P-TL003
49.9Ω
GNDB
IMB
IBIAS
ICMP
1k
•
49.9Ω 10nF
•
IPB
LTC6812-1
10nF
10nF
1k
GNDB
IPA
49.9Ω
10nF
49.9Ω
GNDB
IMA
IPB
LTC6812-1
ACT45B-101-2P-TL003
49.9Ω 10nF
•
GNDB
49.9Ω
GNDA
IMB
IBIAS
ICMP
1k
•
V–
10nF
10nF
1k
GNDA
IPA
49.9Ω 10nF
49.9Ω
V–
GNDA
IMA
GNDA
68121 F45
Figure 45. Capacitive Isolation Coupling for LTC6812-1s on the Same PCB
Rev. B
82
For more information www.analog.com
LTC6812-1
APPLICATIONS INFORMATION
Transformer Selection Guide
As shown in Figure 41, a transformer or pair of transformers isolates the isoSPI signals between two isoSPI ports.
The isoSPI signals have programmable pulse amplitudes
up to 1.6VP-P and pulse widths of 50ns and 150ns. To be
able to transmit these pulses with the necessary fidelity,
the system requires that the transformers have primary
inductances above 60μH and a 1:1 turns ratio. It is also
necessary to use a transformer with less than 2.5μH of
leakage inductance. In terms of pulse shape the primary
inductance will mostly affect the pulse droop of the 50ns
and 150ns pulses. If the primary inductance is too low,
the pulse amplitude will begin to droop and decay over
the pulse period. When the pulse droop is severe enough,
the effective pulse width seen by the receiver will drop
substantially, reducing noise margin. Some droop is acceptable as long as it is a relatively small percentage of
the total pulse amplitude. The leakage inductance primarily
affects the rise and fall times of the pulses. Slower rise
and fall times will effectively reduce the pulse width. Pulse
width is determined by the receiver as the time the signal
is above the threshold set at the ICMP pin. Slow rise and
fall times cut into the timing margins. Generally it is best
to keep pulse edges as fast as possible. When evaluating
transformers, it is also worth noting the parallel winding
capacitance. While transformers have very good CMRR at
low frequency, this rejection will degrade at higher frequencies, largely due to the winding to winding capacitance.
IPB
LTC6812-1
49.9Ω
•
•
•
•
When choosing a transformer, it is best to pick one with
less parallel winding capacitance when possible.
When choosing a transformer, it is equally important to
pick a part that has an adequate isolation rating for the
application. The working voltage rating of a transformer
is a key spec when selecting a part for an application.
Interconnecting daisy-chain links between LTC6812-1
devices see 400Vrms
(est)
600V (est)
80V
700V
300V (est)
250V
1600V (est)
CT
CMC
H
L
W
(W/ LEADS)
PINS
5.0mm
5.0mm
4.9mm
5.0mm
6.4mm
9mm
5.7mm
3.5mm
3.5mm
6.0mm
2.1mm
10.9mm
8.4mm
8.4mm
15.0mm
15.0mm
15.6mm
14.8mm
12.7mm
17.5mm
12.7mm
14.7mm
14.7mm
12.7mm
12.7mm
24.6mm
17.1mm
17.1mm
14.7mm
27.9mm
24.0mm
14.8mm
9.5mm
15.1mm
9.4mm
15.0mm
15.5mm
9.7mm
9.7mm
17.0mm
15.2mm
15.2mm
12SMT
12SMT
12SMT
12SMT
16SMT
12SMT
16SMT
10SMT
12SMT
16SMT
16SMT
16SMT
12SMT
12SMT
l
6.5mm
3.8mm
8.6mm
10mm
9.4mm
6.4mm
6.3mm
5.7mm
3.5mm
7mm
10mm
3.5mm
3.5mm
8.5mm
11.6mm
8.9mm
9.5mm
8.9mm
8.9mm
7.6mm
7.6mm
9mm
9.2mm
9.2mm
5.2mm
7.5mm
8.9mm
21.1mm
16.6mm
12.1mm
12.1mm
16.6mm
9.9mm
9.3mm
15.5mm
12.0mm
12.0mm
9.1mm
12.8mm
6SMT
6SMT
6TH
6SMT
6SMT
6TH
6SMT
6SMT
6SMT
4SMT
8SMT
4SMT
4SMT
l
4.0mm 8.5mm
2.9mm 3.2mm
10.6mm 10.4mm
8.8mm 6.3mm
2.2mm 4.4mm
5.0mm 10.0mm
13.8mm
4.5mm
12.6mm
8.9mm
9.1mm
19.5mm
6SMT
6SMT
8SMT
6SMT
4SMT
6SMT
l
l
l
l
l
l
l
l
l
l
l
l
l
l
–
–
l
l
l
l
l
l
l
l
l
l
–
l
l
4.3kVdc
4kVrms
5kVrms
3kVrms
3kVrms
5kVrms
4.3kVdc
4.3kVdc
4.3kVdc
2.5kVrms
2.5kVrms
3kVrms
2.5kVrms
l
l
l
l
l
l
–
–
–
–
l
l
–
l
l
l
–
–
–
–
–
3.4kVdc
~1kV
2.8kVrms
3kVrms
3kVrms
2.9kVrms
l
l
l
l
–
–
–
–
–
–
–
–
l
l
l
l
l
AEC–
Q200
–
l
l
l
–
–
l
l
–
–
–
–
–
–
–
–
l
l
–
l
l
–
–
l
l
l
l
l
–
l
Table 58. Recommended Common Mode Chokes
MANUFACTURER
PART NUMBER
TDK
ACT45B-101-2P
Murata
DLW43SH101XK2
Rev. B
84
For more information www.analog.com
LTC6812-1
APPLICATIONS INFORMATION
isoSPI Layout Guidelines
Layout of the isoSPI signal lines also plays a significant
role in maximizing the noise immunity of a data link. The
following layout guidelines are recommended:
1. The transformer should be placed as close to the
isoSPI cable connector as possible. The distance
should be kept less than 2cm. The LTC6812-1 should
be placed close to but at least 1cm to 2cm away from
the transformer to help isolate the IC from magnetic
field coupling.
2. A V– ground plane should not extend under the
transformer, the isoSPI connector or in between the
transformer and the connector.
3. The isoSPI signal traces should be as direct as possible while isolated from adjacent circuitry by ground
metal or space. No traces should cross the isoSPI
signal lines, unless separated by a ground plane on
an inner layer.
System Supply Current
The LTC6812-1 has various supply current specifications
for the different states of operation. The average supply
current depends on the control loop in the system. It is
necessary to know which commands are being executed
each control loop cycle, and the duration of the control
loop cycle. From this information it is possible to determine
the percentage of time the LTC6812-1 is in the MEASURE
state versus the low power SLEEP state. The amount of
isoSPI or SPI communication will also affect the average
supply current.
Calculating Serial Throughput
For any given LTC6812-1 the calculation to determine
communication time is simple: it is the number of bits in
the transmission multiplied by the SPI clock period being
used. The control protocol of the LTC6812-1 is very uniform
so almost all commands can be categorized as a write,
read or an operation. Table 59 can be used to determine
the number of bits in a given LTC6812-1 command.
ENHANCED APPLICATIONS
Using the LTC6812-1 with Fewer than 15 Cells
Cells can be connected in a conventional bottom (C1) to
top (C15) sequence with all unused C inputs either shorted
to the highest connected cell or left open. The unused S
pins can simply be left unconnected.
Alternatively, to optimize measurement synchronization
in applications with fewer than fifteen cells, the unused
C pins may be equally distributed between the top of the
third MUX (C15), the top of the second MUX (C10) and
the top of the first MUX (C5). See Figure 47. If the number
of cells being measured is not a multiple of three, the top
MUX(es) should have fewer cells connected. The unused
cell inputs should be tied to the other unused inputs on
the same MUX and then connected to the battery stack
through a 100Ω resistor. The unused inputs will result in
a reading of 0.0V for those cells.
Current Measurement with a Hall-Effect Sensor
The LTC6812-1 auxiliary ADC inputs (GPIO pins) may
be used for any analog signal, including active sensors
with 0V to 5V analog outputs. For battery current measurements, Hall-effect sensors provide an isolated, low
power solution. Figure 48 shows schematically a typical
Hall-effect sensor that produces two outputs that proportion to the VCC provided. The sensor in Figure 48 has two
bidirectional outputs centered at half of VCC. CH1 is a 0A
to 50A low range and CH2 is a 0A to 200A high range. The
sensor is powered from a 5V source and produces analog
outputs that are connected to GPIO pins or inputs of the
Table 59. Daisy Chain Serial Time Equations
CMD BYTES
+ CMD PEC
DATA BYTES
+ DATA PEC PER IC
TOTAL BITS
COMMUNICATION TIME
Read
4
8
(4 + (8 • #ICs)) • 8
Total Bits • Clock Period
Write
4
8
(4 + (8 • #ICs)) • 8
Total Bits • Clock Period
Operation
4
0
4 • 8 = 32
32 • Clock Period
COMMAND TYPE
Rev. B
For more information www.analog.com
85
LTC6812-1
APPLICATIONS INFORMATION
NEXT HIGHER GROUP
OF 12 CELLS
12-CELL
MODULE
NEXT HIGHER GROUP
OF 12 CELLS
V+
C15
S15
C14
S14
C13
S13
C12
S12
C11
S11
C10
S10
C9
S9
C8
S8
C7
S7
C6
S6
C5
S5
C4
S4
C3
S3
C2
S2
C1
S1
C0
V–
LTC6812-1
12-CELL
MODULE
V+
C15
S15
C14
S14
C13
S13
C12
S12
C11
S11
C10
S10
C9
S9
C8
S8
C7
S7
C6
S6
C5
S5
C4
S4
C3
S3
C2
S2
C1
S1
C0
V–
LTC6812-1
68121 F47
NEXT LOWER GROUP
OF 12 CELLS
NEXT LOWER GROUP
OF 12 CELLS
Figure 47. Cell Connection Schemes for 12 Cells
LEM DHAB
CH2
VCC
GND
CH1
A
B
C
D
ANALOG → GPIO2
5V
ANALOG_COM → V–
ANALOG0 → GPIO1
68121 F48
Figure 48. Interfacing a Typical Hall-Effect Battery Current Sensor to Auxiliary ADC Inputs
Rev. B
86
For more information www.analog.com
LTC6812-1
APPLICATIONS INFORMATION
MUX application shown in Figure 50. The use of GPIO1
and GPIO2 as the ADC inputs has the possibility of being
digitized within the same conversion sequence as the cell
inputs (using the ADCVAX command), thus synchronizing
cell voltage and cell current measurements.
100
90
Expanding the Number of Auxiliary Measurements
The LTC6812-1 has nine GPIO pins that can be used as ADC
inputs. In applications that need to measure more than nine
signals, a multiplexer (MUX) circuit can be implemented
ANALOG1
ANALOG2
ANALOG3
ANALOG4
ANALOG5
ANALOG6
ANALOG7
ANALOG8
S1
S2
S3
S4
S5
S6
S7
S8
ANALOG9
ANALOG10
ANALOG11
ANALOG12
ANALOG13
ANALOG14
ANALOG15
ANALOG16
S1
S2
S3
S4
S5
S6
S7
S8
VTEMP
NTC
10k AT 25°C
V–
VDD
GND
A0
A1
SCL
SDA
D
RESET
70
60
50
40
30
20
10
0
–40
–20
0
20
40
60
TEMPERATURE (°C)
80
68121 F49
Figure 49. Typical Temperature Probe Circuit and
Relative Output
to expand the analog measurements to sixteen different
signals (Figure 50). The GPIO1 ADC input is used for
measurement and MUX control is provided by the I2C port
on GPIO 4 and 5. The buffer amplifier was selected for
fast settling and will increase the usable throughput rate.
ADG728
VDD
GND
A0
A1
SCL
SDA
D
RESET
ADG728
VTEMPx (% VREF2)
10k
READING EXTERNAL TEMPERATURE PROBES
Figure 49 shows the typical biasing circuit for a negative
temperature coefficient (NTC) thermistor. The 10k at 25°C
is the most popular sensor value and the VREF2 output
stage is designed to provide the current required to bias
several of these probes. The biasing resistor is selected
to correspond to the NTC value so the circuit will provide
1.5V at 25°C (VREF2 is 3V nominal). The overall circuit
response is approximately –1%/°C in the range of typical
cell temperatures, as shown in the chart of Figure 49.
80
VREF2
VREG
V–
20k
20k
LTC6812-1
1µF
GPIO5
GPIO4
–
LTC6255
+
100Ω
GPIO1
10nF
68121 F50
ANALOG INPUTS: 0.04V TO 4.5V
Figure 50. MUX Circuit Supports Sixteen Additional Analog Measurements
Rev. B
For more information www.analog.com
87
LTC6812-1
PACKAGE DESCRIPTION
LWE Package
64-Lead Plastic Exposed Pad LQFP (10mm × 10mm)
(Reference LTC DWG #05-08-1982 Rev A)
10.15 – 10.25
7.50 REF
1
64
49
48
0.50 BSC
5.74 ±0.05
7.50 REF
0.20 – 0.30
10.15 – 10.25
5.74 ±0.05
16
17
PACKAGE OUTLINE
33
32
1.30 MIN
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
12.00 BSC
10.00 BSC
5.74 ±0.10
64
49
SEE NOTE: 3
1
64
49
48
48
1
12.00 BSC
10.00 BSC
A
5.74 ±0.10
A
33
16
33
16
C0.30 – 0.50
17
32
17
BOTTOM OF PACKAGE—EXPOSED PAD (SHADED AREA)
32
11° – 13°
R0.08 – 0.20
1.60
1.35 – 1.45 MAX
GAUGE PLANE
0.25
0° – 7°
LWE64 LQFP 0416 REV A
11° – 13°
0.50
BSC
0.09 – 0.20
1.00 REF
0.17 – 0.27
0.05 – 0.15
SIDE VIEW
0.45 – 0.75
SECTION A – A
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DIMENSIONS OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.25mm (10 MILS) BETWEEN THE LEADS AND
MAX 0.50mm (20 MILS) ON ANY SIDE OF THE EXPOSED PAD, MAX 0.77mm
(30 MILS) AT CORNER OF EXPOSED PAD, IF PRESENT
3. PIN-1 INDENTIFIER IS A MOLDED INDENTATION, 0.50mm DIAMETER
4. DRAWING IS NOT TO SCALE
Rev. B
88
For more information www.analog.com
LTC6812-1
REVISION HISTORY
REV
DATE
DESCRIPTION
A
10/19
Added AEC-Qualification Indicator
Order Information Updated Format
Renamed Sum of Cells to “Sum of All Cells”
Updated isoSPI related typical performance characteristics
Note added regarding pin functions denoted as “NC”
B
11/20
PAGE NUMBER
1
3
4, 5, 25-27, 65
13
15
Rewrite to section entitled “CORE LTC6812-1 STATE DESCRIPTIONS”
18–19
Rewrite to section entitled “ADC Conversion with Digital Redundancy”
27
Rewrite to section entitled “Thermal Shutdown”
31
Rewrite to section entitled “WATCHDOG AND DISCHARGE TIMER”
32
Added new section entitled “RESET BEHAVIORS”
33
Correction to Table 37, section CH[2:0], conversion times for All Cells
59
Rewrite to section entitled “Implementing a Modular isoSPI Daisy Chain”
77
Update to Table 57. Recommended Transformers
81
Rewrite to section entitled “Related Parts”
86
ADC Timing Specifications updated; all MIN tCYCLE values updated
6
ADC Timing Specifications updated; MIN tSKEW1, MIN tSKEW2, MIN tSKEW3, values updated
7
Correction to Figure 1 “LTC6812-1 Operation State Diagram”; “DTM=1” changed to “DTMEN=1”
18
Correction to section entitled, RESET BEHAVIOR; Reference to Bit[7] under Watchdog Timeout (While Discharge
Timer is Running) eliminated
34
Correction to section entitled, “Transformer Selection Guide”; links between LTC6812-1 devices see < 90V stress, not
< 60V stress.
83
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
more by
information
www.analog.com
89
LTC6812-1
TYPICAL APPLICATION
100Ω
100nF
100Ω
10Ω
100nF
33Ω
10Ω
+
C14
3.7V
CELL3
TO CELL13
CIRCUITS
+
C2
3.7V
100nF
33Ω
VREG
S15
VREF1
1μF
1μF
C14
VREF2
1μF
IPB
LTC6812-1
10Ω
100nF
33Ω
100Ω
C2
IMB
IPA
S2
100Ω
100nF
C1
3.7V
C15
NPN
S14
10Ω
+
DRIVE
•
•
C15
3.7V
V+
•
•
+
10nF
33Ω
10Ω
C1
IMA
S1
IBIAS
C0
ICMP
–
ISOMD
V
1k
1k
VREG
68121 TA02
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC6810-1/
LTC6810-2
4th Generation 6-Cell Battery Stack
Monitor and Balancing IC
Measures Cell Voltages for Up to 6 Series Battery Cells. Daisy-Chain Capability Allows
Multiple Devices to Be Connected to Measure Many Battery Cells Simultaneously. The isoSPI
Bus Can Operate Up to 1MHz and Can Be Operated Bidirectionally for Fault Conditions, Such
As a Broken Wire or Connector. Includes Internal Passive Cell Balancing of up to 150mA.
Each Cell Measurement Channel Includes Redundant Measurement Capability.
LTC6811-1/
LTC6811-2
4th Generation 12-Cell Battery Stack
Monitor and Balancing IC
Measures Cell Voltages for Up to 12 Series Battery Cells. Daisy-Chain Capability Allows
Multiple Devices to Be Connected to Measure Many Battery Cells Simultaneously Via the
Built-In 1MHz, 2-Wire Isolated Communication (isoSPI). Includes Capability for Passive Cell
Balancing.
LTC6813-1
4th Generation 18-Cell Battery Stack
Monitor and Balancing IC
Measures Cell Voltages for Up to 18 Series Battery Cells. The isoSPI Daisy-Chain
Capability Allows Multiple Devices to be Interconnected for Measuring Many Battery
Cells Simultaneously. The isoSPI Bus Can Operate Up to 1MHz and Can Be Operated
Bidirectionally for Fault Conditions, Such As a Broken Wire or Connector. Includes Internal
Passive Cell Balancing Capability of Up to 200mA.
LTC6820
isoSPI Isolated Communications
Interface
Provides an Isolated Interface for SPI Communication Up to 100 Meters, Using a Twisted
Pair. Companion to the LTC6804, LTC6806, LTC6810, LTC6811, LTC6812 and LTC6813.
Rev. B
90
11/20
www.analog.com
For more information www.analog.com
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