LTC6915
Zero Drift, Precision
Instrumentation Amplifier with
Digitally Programmable Gain
Features
Description
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The LTC®6915 is a precision programmable gain instrumentation amplifier. The gain can be programmed to 0,
1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, or 4096
through a parallel or serial interface. The CMRR is typically 125dB with a single 5V supply with any programmed
gain. The offset is below 10µV with a temperature drift of
less than 50nV/°C.
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14 Levels of Programmable Gain
125dB CMRR Independent of Gain
Gain Accuracy 0.1% (Typ)
Maximum Offset Voltage of 10µV
Maximum Offset Voltage Drift: 50nV/°C
Rail-to-Rail Input and Output
Parallel or Serial (SPI) Interface for Gain Setting
Supply Operation: 2.7V to ±5.5V
Typical Noise: 2.5µVP-P (0.01Hz to 10Hz)
16-Lead SSOP and 12-Lead DFN Packages
The LTC6915 uses charge balanced sampled data techniques to convert a differential input voltage into a single
ended signal that is in turn amplified by a zero-drift operational amplifier.
Applications
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The differential inputs operate from rail-to-rail and the
single-ended output swings from rail-to-rail. The LTC6915
can be used in single power supply applications as low as
2.7V, or with dual ±5V supplies. The LTC6915 is available
in a 16-lead SSOP package and a 12-lead DFN surface
mount package.
Thermocouple Amplifiers
Electronic Scales
Medical Instrumentation
Strain Gauge Amplifier
High Resolution Data Acquisition
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners
Typical Application
Differential Bridge Amplifier with Gain Programmed through the Serial Interface
LTC6915 SSOP PACKAGE
3 IN +
+
OUT 15
3V
2 IN
_
CS
CH
–
SENSE 14
CF
R < 10k
RESISTOR
ARRAY
REF 13
11 PARALLEL_SERIAL
MUX
µP
TO OTHER
DEVICES
6 CS(D0)
7 DIN(D1)
8 CLK(D2)
9 DOUT(D3)
4-BIT
LATCH
HOLD_THRU 5
V+
16
3V
0.1µF
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
8-BIT
SHIFT-REGISTER
SHDN
DGND
1
10
4
V–
6915 TA01
6915fb
1
LTC6915
Absolute Maximum Ratings
(Note 1)
Total Supply Voltage (V+ to V–).................................. 11V
Input Current......................................................... ±10mA
|VIN+ – VREF|.........................................................5.5V
|VIN – – VREF|.........................................................5.5V
|V+ – VDGND|.........................................................5.5V
|VDGND – V–|.........................................................5.5V
Digital Input Voltage........................................... V– to V+
Operating Temperature Range
LTC6915C............................................... –0°C to 70°C
LTC6915I..............................................–40°C to 85°C
LTC6915H........................................... – 40°C to 125°C
Junction Temperature
(GN Package)..................................................... 150°C
(DFN Package)................................................... 125°C
Storage Temperature
(GN Package)...................................... –65°C to 150°C
(DFN Package).................................... –65°C to 125°C
Lead Temperature (Soldering 10 sec)..................... 300°C
Pin Configuration
TOP VIEW
TOP VIEW
IN–
1
12 V +
IN+
2
11 OUT
V–
3
CS(D0)
4
DIN(D1)
CLK(D2)
13
V–
SHDN 1
10 REF
9
PARALLEL_SERIAL
5
8
DGND
6
7
DOUT(D3)
15 OUT
IN + 3
14 SENSE
V– 4
HOLD_THRU 5
DE12 PACKAGE
12-LEAD (4mm × 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 160°C/W
EXPOSED PAD (PIN 13) IS V–, MUST BE SOLDERED TO PCB
16 V +
IN – 2
13 REF
12 NC
CS(D0) 6
11 PARALLEL_SERIAL
DIN(D1) 7
10 DGND
CLK(D2) 8
9
DOUT(D3)
GN PACKAGE
16-LEAD NARROW PLASTIC SSOP
TJMAX = 150°C, θJA = 135°C/W
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC6915CDE#PBF
LTC6915CDE#TRPBF
6915
12-Lead (4mm × 3mm) Plastic DFN
0°C to 70°C
LTC6915IDE#PBF
LTC6915IDE#TRPBF
6915I
12-Lead (4mm × 3mm) Plastic DFN
–40°C to 85°C
LTC6915CGN#PBF
LTC6915CGN#TRPBF
6915
16-Lead Narrow Plastic SSOP
0°C to 70°C
LTC6915IGN#PBF
LTC6915IGN#TRPBF
6915I
16-Lead Narrow Plastic SSOP
–40°C to 85°C
LTC6915HGN#PBF
LTC6915HGN#TRPBF
6915H
16-Lead Narrow Plastic SSOP
–40°C to 125°C
LEAD BASED FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC6915CDE
LTC6915CDE#TR
6915
12-Lead (4mm × 3mm) Plastic DFN
0°C to 70°C
LTC6915IDE
LTC6915IDE#TR
6915I
12-Lead (4mm × 3mm) Plastic DFN
–40°C to 85°C
LTC6915CGN
LTC6915CGN#TR
6915
16-Lead Narrow Plastic SSOP
0°C to 70°C
LTC6915IGN
LTC6915IGN#TR
6915I
16-Lead Narrow Plastic SSOP
–40°C to 85°C
LTC6915HGN
LTC6915HGN#TR
6915H
16-Lead Narrow Plastic SSOP
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
6915fb
2
LTC6915
Electrical
Characteristics
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
0
0.075
%
V+ = 3V, V– = 0V, VREF = 200mV
VOS
Gain Error (Note 2)
AV = 1 (RL =10k)
l
–0.075
Gain Error (Note 2)
AV = 2 to 32 (RL = 10k)
l
–0.5
0
0.5
%
Gain Error (Note 2)
AV = 64 to 1024 (RL = 10k)
l
–0.6
–0.1
0.6
%
–1
–0.2
1.0
%
3
15
ppm
–3
±10
µV
±50
±100
nV/°C
nV/°C
Gain Error (Note 2)
AV = 2048, 4096 (RL = 10k)
l
Gain Nonlinearity
AV = 1
l
Input Offset Voltage (Note 3)
VCM = 200mV
Average Input Offset Drift (Note 3)
TA = –40°C to 85°C
TA = 85°C to 125°C
l
l
IB
Average Input Bias Current (Note 4)
VCM = 1.2V
l
5
10
nA
IOS
Average Input Offset Current (Note 4)
VCM = 1.2V
l
1.5
3
nA
en
Input Noise Voltage
DC to 10Hz
2.5
µVP-P
119
119
119
dB
dB
dB
dB
dB
V+ = 3V, V– = 0V, VREF = 200mV
CMRR
PSRR
Common Mode Rejection Ratio
AV = 1024, VCM = 0V to 3V, LTC6915C
AV = 1024, VCM = 0.1V to 2.9V, LTC6915I
AV = 1024, VCM = 0V to 3V, LTC6915I
AV = 1024, VCM = 0.1V to 2.9V, LTC6915H
AV = 1024, VCM = 0V to 2.97V, LTC6915H
l
l
l
l
l
100
100
95
100
85
Power Supply Rejection Ratio (Note 5)
VS = 2.7V to 6V
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110
116
dB
Output Voltage Swing High (Referenced to V–)
Sourcing 200µA
Sourcing 2mA
l
l
2.95
2.75
2.98
2.87
V
V
Output Voltage Swing Low (Referenced to V–)
Sinking 200µA
Sinking 2mA
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l
18
130
50
300
mV
mV
Supply Current, Parallel Mode
No Load at OUT, VCM = 200mV
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0.88
1.3
mA
Supply Current, Serial Mode (Note 6)
No Load at OUT, Capacitive Load at
DOUT (CL) = 15pF, Continuous CLK
Frequency = 4MHz, CS = LOW,
Gain Control Code = 0001
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1.1
1.65
mA
Supply Current Shutdown
VSHDN = 2.7V (Hardware Shutdown)
VSHDN = 1V, Gain Control Code = 0000
(Software Shutdown)
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1
125
4
180
µA
µA
SHDN Input High
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SHDN Input Low
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1
V
SHDN and HOLD_THRU Input Current (Note 2)
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5
µA
2.7
V
Internal Op Amp Gain Bandwidth
200
kHz
Slew Rate
0.2
V/µs
3
kHz
Internal Sampling Frequency
V+ = 5V, V– = 0V, VREF = 200mV
Gain Error (Note 2)
AV = 1 (RL = 10k)
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–0.075
0
0.075
%
Gain Error (Note 2)
AV = 2 to 32 (RL= 10k)
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–0.5
0
0.5
%
–0.6
–0.1
0.6
%
–1
–0.2
1
%
3
15
ppm
Gain Error (Note 2)
AV = 64 to 1024 (RL = 10k)
l
Gain Error (Note 2)
AV = 2048, 4096 (RL = 10k)
l
Gain Nonlinearity
AV = 1
l
6915fb
3
LTC6915
Electrical
Characteristics
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
VOS
Input Offset Voltage (Note 3)
VCM = 200mV
Average Input Offset Drift (Note 3)
TA = –40°C to 85°C
TA = 85°C to 125°C
l
–3
±10
µV
±50
±100
nV/°C
nV/°C
Average Input Bias Current (Note 4)
VCM = 1.2V
l
5
10
nA
IOS
Average Input Offset Current (Note 4)
VCM = 1.2V
l
1.5
3
nA
CMRR
Common Mode Rejection Ratio
AV = 1024, VCM = 0V to 5V, LTC6915C
AV = 1024, VCM = 0.1V to 4.9V, LTC6915I
AV = 1024, VCM = 0V to 5V, LTC6915I
AV = 1024, VCM = 0.1V to 4.9V, LTC6915H
AV = 1024, VCM = 0V to 4.97V, LTC6915H
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105
105
95
100
85
125
125
125
dB
dB
dB
dB
dB
PSRR
Power Supply Rejection Ratio (Note 5)
VS = 2.7V to 6V
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110
116
dB
Output Voltage Swing High
Sourcing 200µA
Sourcing 2mA
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l
4.95
4.80
4.99
4.93
V
V
Output Voltage Swing Low
Sinking 200µA
Sinking 2mA
l
l
17
120
50
300
mV
mV
V+ = 5V, V– = 0V, VREF = 200mV
Supply Current, Parallel Mode
No Load at OUT, VCM = 200mV
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0.95
1.48
mA
Supply Current, Serial Mode (Note 6)
No Load at OUT, Capacitive Load at
DOUT (CL) = 15pF, Continuous CLK
Frequency = 4MHz, CS = LOW,
Gain Control Code = 0001
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1.4
2
mA
Supply Current, Shutdown
VSHDN = 4.5V (Hardware Shutdown)
VSHDN = 1V, Gain Control Code = 0000
(Software Shutdown)
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2
135
10
200
µA
µA
SHDN Input High
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SHDN Input Low
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1
V
SHDN and HOLD_THRU Input Current (Note 2)
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5
µA
4.5
Internal Op Amp Gain Bandwidth
200
kHz
Slew Rate
0.2
V/µs
3
kHz
Internal Sampling Frequency
V+ = 5V, V– = –5V, V
VOS
IOS
V
REF = 0V
Gain Error (Note 2)
AV = 1 (RL = 10k)
l
–0.075
0
0.075
%
Gain Error (Note 2)
AV = 2 to 32 (RL = 10k)
l
–0.5
0
0.5
%
Gain Error (Note 2)
AV = 64 to 1024 (RL = 10k)
l
–0.6
–0.1
0.6
%
Gain Error (Note 2)
AV = 2048, 4096 (RL = 10k)
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–1
–0.2
1
%
Gain Nonlinearity
AV = 1
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3
15
ppm
5
±20
µV
±50
±100
nV/°C
nV/°C
Input Offset Voltage (Note 3)
VCM = 0mV
Average Input Offset Drift (Note 3)
TA = –40°C to 85°C
TA = 85°C to 125°C
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l
Average Input Bias Current (Note 4)
VCM = 1V
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4
10
nA
Average Input Offset Current (Note 4)
VCM = 1V
l
1.5
3
nA
6915fb
4
LTC6915
Electrical
Characteristics
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
CMRR
Common Mode Rejection Ratio
AV = 1024, VCM = –5V to 5V, LTC6915C
AV = 1024, VCM = –4.9V to 4.9V, LTC6915I
AV = 1024, VCM = –5V to 5V, LTC6915I
AV = 1024, VCM = –4.9V to 4.9V, LTC6915H
AV = 1024, VCM = –5V to 4.97V, LTC6915H
l
l
l
l
l
105
105
100
100
90
123
123
123
dB
dB
dB
dB
dB
PSRR
Power Supply Rejection Ratio (Note 5)
VS = 2.7V to 11V
l
110
116
dB
Output Voltage Swing High
Sourcing 200µA
Sourcing 2mA
l
l
4.97
4.90
4.99
4.96
V
V
Output Voltage Swing Low
Sinking 200µA
Sinking 2mA
l
l
–4.98
–4.90
–4.92
–4.70
Supply Current, Parallel Mode
No Load, VCM = 0mV
l
1.1
1.6
mA
Supply Current, Serial Mode (Note 6)
No Load at OUT, Capacitive Load at
DOUT (CL) = 15pF, Continuous CLK
Frequency = 4MHz, CS = LOW,
Gain Control Code = 0001
l
1.73
2.48
mA
Supply Current, Shutdown
VSHDN = 4V (Hardware Shutdown)
VSHDN = 1V, Gain Control Code = 0000
(Software Shutdown)
l
l
160
25
240
µA
µA
V
V
SHDN Input High
l
SHDN Input Low
l
1
V
l
5
µA
4
V
V+ = 5V, V– = –5V, VREF = 0V
SHDN and HOLD_THRU Input Current (Note 2)
Internal Op Amp Gain Bandwidth
200
kHz
Slew Rate
0.2
V/µs
3
kHz
Internal Sampling Frequency
Digital I/O, All Digital I/O Voltage Referenced to DGND
VIH
Digital Input High Voltage
l
VIL
Digital Input Low Voltage
l
2.0
V
0.8
V
V+ – 0.3
VOH
Digital Output High Voltage
Sourcing 500µA
l
VOL
Digital Output Low Voltage
Sinking 500µA
l
0.3
V
V
Digital Input Leakage
V+ = 5V, V– = –5V, VIN = 0V to 5V
l
±2
µA
Timing, V+ = 2.7V to 4.5V, V– = 0V (Note 7)
t1
DIN Valid to CLK Setup
l
60
ns
t2
DIN Valid to CLK Hold
t3
CLK Low
l
0
ns
l
100
ns
t4
CLK High
l
100
ns
t5
CS/LD Pulse Width
l
60
ns
t6
LSB CLK to CS/LD
l
60
ns
t7
CS/LD Low to CLK
l
30
t8
DOUT Output Delay
t9
CLK Low to CS/LD Low
CL = 15pF
l
ns
125
l
0
ns
ns
6915fb
5
LTC6915
Electrical
Characteristics
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
Timing, V+ = 4.5V to 5.5V, V– = 0V (Note 7)
t1
DIN Valid to CLK Setup
l
30
ns
t2
DIN Valid to CLK Hold
l
0
ns
t3
CLK Low
l
50
ns
t4
CLK High
l
50
ns
t5
CS/LD Pulse Width
l
40
ns
t6
LSB CLK to CS/LD
l
40
ns
t7
CS/LD Low to CLK
l
20
ns
t8
DOUT Output Delay
t9
CLK Low to CS/LD Low
CL = 15pF
85
l
l
0
ns
ns
Timing, Dual ±4.5V to ±5.5V Supplies (Note 7)
t1
DIN Valid to CLK Setup
l
30
ns
t2
DIN Valid to CLK Hold
l
0
ns
t3
CLK High
l
50
ns
t4
CLK Low
l
50
ns
t5
CS/LD Pulse Width
l
40
ns
t6
LSB CLK to CS/LD
l
40
ns
t7
CS/LD Low to CLK
l
20
ns
t8
DOUT Output Delay
t9
CLK Low to CS/LD Low
CL = 15pF
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: These parameters are tested at ±5V supply; at 3V and 5V supplies
they are guaranteed by design.
Note 3: These parameters are guaranteed by design. Thermocouple effects
preclude measurement of these voltage levels in high speed automatic test
systems. VOS is measured to a limit set by test equipment capability.
85
l
l
0
ns
ns
Note 4: If the total source resistance is less than 10k, no DC errors result
from the input bias current or mismatch of the input bias currents or the
mismatch of the resistances connected to IN – and IN+.
Note 5: The PSRR measurement accuracy depends on the proximity of
the power supply bypass capacitor to the device under test. Because of
this, the PSRR is 100% tested to relaxed limits at final test. However, their
values are guaranteed by design to meet the data sheet limits.
Note 6: Supply current is dependent on the clock frequency. A higher clock
frequency results in higher supply current.
Note 7: Guaranteed by design, not subject to test.
6915fb
6
LTC6915
Typical Performance Characteristics
VS = 3V
VREF = 0.2V
TA = 25°C
–4
AV = 4096
–8
AV = 256
–10
AV = 16
–12
AV = 1
–14
–16
0
–2
–6
AV = 4096
–8
AV = 256
–10
–12
AV = 16
–14
2.5
1.0
1.5
2.0
0.5
INPUT COMMON MODE VOLTAGE (V)
–18
3.0
INPUT OFFSET VOLTAGE (µV)
INPUT OFFSET VOLTAGE (µV)
0
TA = 125°C
–5
TA = 85°C
–20
TA = 70°C
2.5
1.0
1.5
2.0
0.5
INPUT COMMON MODE VOLTAGE (V)
10
5
TA = 125°C
0
–5
TA = 85°C
TA = 25°C
–10
–20
3.0
TA = 70°C
20
2
3
1
4
INPUT COMMON MODE VOLTAGE (V)
10
RS = 10k
RS = 15k
RS = 20k
–30 VS = 3V
RS
VREF = 0.2V
+
R+ = R– = RS
CIN
–40 CIN < 100pF
–
AV = 16
RS
TA = 25°C
–50
0
2.5
1.0
1.5
2.0
0.5
INPUT COMMON MODE VOLTAGE (V)
10
TA = 25°C
TA = 125°C
0
–5
TA = 85°C
–10
TA = 70°C
–15
–25
–5
5
6915 G07
–20
Error Due to Input RS vs Input
Common Mode
RS = 10k
RS = 15k
RS = 5k
RS
–10
+
10
1
3
4
2
INPUT COMMON MODE VOLTAGE (V)
5
6915 G08
VS = ±5V
VREF = 0V
R+ = R– = RS
CIN < 100pF
AV = 16
TA = 25°C
RS = 20k
RS = 10k
RS = 15k
0
RS = 5k
RS
–10
CIN
–
RS
0
5
3
–3
1
–1
INPUT COMMON MODE VOLTAGE (V)
6915 G06
RS = 20k
0
CIN
3.0
TA = –50°C
5
20
VS = 5V
VREF = 0.2V
R+ = R– = RS
CIN < 100pF
AV = 16
TA = 25°C
RS = 5k
ADDITIONAL OFFSET (µV)
ADDITIONAL OFFSET (µV)
VS = ±5V
VREF = 0V
AV = 16
–20
TA = –50°C
0
5
6915 G03
Error Due to Input RS vs Input
Common Mode
10
–20
AV = 1
–5 –4 –3 –2 –1 0 1 2 3 4
INPUT COMMON MODE VOLTAGE (V)
6915 G05
Error Due to Input RS vs Input
Common Mode
–10
–10
15
6915 G04
0
AV = 256
AV = 16
–8
20
–15
TA = –50°C
0
–6
Input Offset Voltage vs Input
Common Mode
VS = 5V
VREF = 0.2V
AV = 16
15
5
–15
AV = 4096
–4
–14
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
INPUT COMMON MODE VOLTAGE (V)
20
10
TA = 25°C
0
–2
Input Offset Voltage vs Input
Common Mode
VS = 3V
VREF = 0.2V
AV = 16
–10
2
6915 G02
Input Offset Voltage vs Input
Common Mode
15
4
–12
AV = 1
6915 G01
20
VS = ±5V
VREF = 0V
TA = 25°C
6
–4
–16
0
8
VS = 5V
VREF = 0.2V
TA = 25°C
INPUT OFFSET VOLTAGE (µV)
–6
Input Offset Voltage vs Input
Common Mode
ADDITIONAL OFFSET (µV)
INPUT OFFSET VOLTAGE (µV)
–2
2
INPUT OFFSET VOLTAGE (µV)
0
Input Offset Voltage vs Input
Common Mode
INPUT OFFSET VOLTAGE (µV)
Input Offset Voltage vs Input
Common Mode
–20
+
–
RS
–5
–3
1
3
–1
INPUT COMMON MODE VOLTAGE (V)
5
6915 G09
6915fb
7
LTC6915
Typical Performance Characteristics
Error Due to Input RS Mismatch
vs Input Common Mode
Error Due to Input RS Mismatch
vs Input Common Mode
40
0
–40
+
CIN
–60
–
R–
0
R+ = 0k, R– = 15k
10
0
R+ = 15k, R– = 0k
–10
R+
–20
2.5
1.0
1.5
2.0
0.5
INPUT COMMON MODE VOLTAGE (V)
–40
3.0
+
CIN
–30
R+ = 20k, R– = 0k
R+ = 0k, R– = 20k
–
R–
Offset Voltage vs Temperature
2
–10
R+
–20
CIN
R+ = 15k, R– = 0k
R+ = 20k, R– = 0k
+
–
R–
–5 –4 –3 –2 –1 0 1 2 3 4
INPUT COMMON MODE VOLTAGE (V)
VOS vs REF (Pin 13)
20
VIN = VIN = REF
AV = 16
TA = 25°C
+
5
6915 G12
–
VOS vs REF (Pin 13)
VIN+ = VIN– = REF
AV = 16
TA = 25°C
10
–3
VS = ±5V
0
VOS (µV)
5
VS = 5V
VS = 3V
VOS (µV)
INPUT OFFSET VOLTAGE (µV)
10
–8
–20
VS = 5V
VS = 3V
–13
VS = 10V
–10
–30
–10
–50
–25
50
25
0
75
TEMPERATURE (°C)
100
–18
125
0
0.5
1.0
1.5
2.0
2.5
VREF (V)
3.0
–40
4.0
130
SUPPLY CURRENT (mA)
1.10
1
0
–1
–2
–3
TA = 85°C
1.05
1.8
2.4
6915 G16
2
3
4
5 6
VREF (V)
7
1.00
0.95
0.85
0.80
0.70
10
9
R+ = R– = 1k
110
TA = 125°C
TA = 0°C
0.90
8
VS = 3V, 5V, ±5V
VIN = 1VP-P
120
R+ = R– = 10k
100
R+ = 10k, R– = 0k
90
TA = –50°C
R+
80
0.75
–4
1
CMRR vs Frequency
1.15
VS = ±2.5V
4 VCM = VREF = 0V
R = 10k
3 AL = 1
V
2 TA = 25°C
0
6915 G15
Supply Current vs Supply Voltage
5
–5
–2.4 –1.8 –1.2 –0.6 0
0.6 1.2
OUTPUT VOLTAGE (V)
3.5
6915 G14
6915 G13
Gain Nonlinearity at Gain = 1
(Gain Nonlinearity Decreases for
Gain > 1)
GAIN NONLINEARITY (ppm)
R+ = 0k, R– = 15k
6915 G11
15
–5
R+ = 0k, R– = 20k
0
–30
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
INPUT COMMON MODE VOLTAGE (V)
6915 G10
0
VS = ±5V
VREF = 0V
20 CIN < 100pF
AV = 16
TA = 25°C
10
R+ = 20k, R– = 0k
CMRR (db)
–80
R+ = 15k, R– = 0k
R+
30
VS = 5V
30 VREF = 0.2V
CIN < 100pF
20 AV = 16
TA = 25°C
ADDITIONAL OFFSET (µV)
VS = 3V
= 0.2V
V
60 REF
CIN < 100pF
R+ = 0k, R– = 20k
A = 16
40 V
TA = 25°C
R+ = 0k, R– = 15k
20
ADDITIONAL OFFSET (µV)
ADDITIONAL OFFSET (µV)
80
–20
Error Due to Input RS Mismatch
vs Input Common Mode
2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.5 11.5
SUPPLY VOLTAGE (V)
6915 G17
70
R–
1
+
–
R+ = 0k, R– = 10k
10
100
FREQUENCY (Hz)
1000
6915 G18
6915fb
8
LTC6915
Typical Performance Characteristics
VS = ±5V
200
VS = 5V
150
VS = 3V
100
50
0
1
10
100
1000
FREQUENCY (Hz)
2
1
0
–1
–2
–3
10000
3
VS = 3V
TA = 25°C
INPUT REFFERED NOISE VOLTAGE (µV)
250
3
AV = 16
TA = 25°C
Input Referred Noise in
10Hz Bandwidth
0
2
4
6
TIME (s)
6915 G19
5
VS = 5V, SOURCING
4
4.0
3.5
VS = 3V, SOURCING
3.0
2.5
2.0
1.5
VS = 3V, SINKING
VS = 5V, SINKING
1.0
0.5
0
0.01
1
0.1
OUTPUT CURRENT (mA)
VS = ±5V
TA = 25°C
2
1
0
–1
–2
1
0.1
OUTPUT CURRENT (mA)
10
100
GAIN (V/V)
3
1000
10000
6915 G25
0.01
0.001
SETTLING ACCURACY (%)
3.30
6915 G24
Additional Gain Error vs Load
Resistance
TA = 125°C
3.25
TA = 85°C
3.20
3.10
2.5
0.1
0.1
TA = 25°C
1
4
6915 G23
3.15
5
0
5
0
0.0001
10
3.35
10
10
8
1
SINKING
3.40
15
6
TIME (s)
VS = 5V
dVOUT = 1V
G 100
TA = 25°C
6
Internal Clock Frequency vs
Supply Voltage
20
4
2
–3
–5
0.01
10
CLOCK FREQUENCY (kHz)
SETTLING TIME (ms)
25
2
7
–4
VS = 5V
dVOUT = 1V
0.1% ACCURACY
TA = 25°C
0
8
3
Settling Time vs Gain
30
–2
Low Gain Settling Time vs
Settling Accuracy
SOURCING
6915 G22
35
–1
Output Voltage Swing vs
Output Current
OUTPUT VOLTAGE SWING (V)
OUTPUT VOLTAGE SWING (V)
4.5
0
6915 G21
SETTLING TIME (ms)
TA = 25°C
1
6915 G20
Output Voltage Swing vs
Output Current
5.0
VS = 5V
TA = 25°C
2
–3
10
8
ADDITIONAL GAIN ERROR (%)
300
Input Referred Noise in
10Hz Bandwidth
INPUT REFFERED NOISE VOLTAGE (µV)
INPUT REFERRED NOISE DENSITY (nV/√Hz)
Input Voltage Noise Density
vs Frequency
4.5
0
AV = 16
–0.1
AV = 256
–0.2
–0.3
AV = 4096
TA = –55°C
6.5
8.5
SUPPLY VOLTAGE (V)
10.5
6915 G26
–0.4
0
2
6
8
4
LOAD RESISTANCE RL (k)
10
6915 G27
6915fb
9
LTC6915
Pin Functions
(DFN/GN)
IN– (Pin 1/Pin 2): Inverting Analog Input.
SHDN (Pin 1 GN Package Only): Shutdown Pin. The IC is
shut down when SHDN is tied to V+. An internal current
source pulls this pin to V– when floating.
IN+ (Pin 2/Pin 3): Noninverting Analog Input.
V– (Pin 3/Pin 4): Negative Supply.
CS(D0) (Pin 4/Pin 6): TTL Level Input. When in serial
control mode, this pin is the chip select input (active low);
in parallel control mode, this pin is the LSB of the parallel
gain control code.
DIN(D1) (Pin 5/Pin 7): TTL Level Input. When in serial
control mode, this pin is the serial input data; in parallel mode, this pin is the second LSB of the parallel gain
control code.
HOLD_THRU (Pin 5 GN Package Only): TTL Level Input
for Parallel Control Mode. When HOLD_THRU is high, the
parallel data is latched in an internal D-latch.
CLK(D2) (Pin 6/Pin 8): TTL Level Input. When in serial
control mode, this pin is the clock of the serial interface;
in parallel mode, this pin is the third LSB of the parallel
gain control code.
DOUT(D3) (Pin 7/Pin 9): TTL Level Input. When in serial
control mode, this pin is the output of the serial data; in
parallel mode, this pin is the MSB of the 4-bit parallel
gain control code. In parallel mode operation, if the data
in to DOUT (Pin 9) is from a voltage source greater than V+
(Pin 12), then connect a resistor between the voltage source
and DOUT to limit the current into Pin 9 to 5mA or less.
DGND (Pin 8/Pin 10): Digital Ground.
PARALLEL_SERIAL (Pin 9/Pin 11): Interface Selection
Input. When tied to V+, the interface is in parallel mode,
i.e., the PGA gain is defined by the parallel codes (D3 ~
D0), i.e., CS(D0), DATA(D1), CLK(D2), and DOUT(D3).
When PARALLEL_SERIAL pin is tied to V–, the PGA gain
is set by the serial interface.
REF (Pin 10/Pin 13): Voltage Reference for PGA output.
OUT (Pin 11/Pin 15): Amplifier Output. The typical current
sourcing/sinking of the OUT pin is 1mA. For minimum
gain error, the load resistance should be 1k or greater
(refer to the Output Voltage Swing vs Output Current and
Gain Error vs Load Resistance in the Typical Performance
Characteristics section).
V+ (Pin 12/Pin 16): Positive Supply.
SENSE (Pin 14 GN Package Only): Sense Pin. When the
PGA drives a low resistance load and the interconnect
resistance between the OUT pin and the load is not negligible, tying the SENSE pin as close as possible to the
load can improve the gain accuracy.
6915fb
10
LTC6915
Block Diagrams
(GN Package Only)
IN +
3
+
CS
IN –
CH
2
–
15
14
CF
OUT
SENSE
GAIN
CONTROL
RESISTOR
ARRAY
13
PARALLEL_SERIAL
11
CS(D0)
DIN(D1)
CLK(D2)
DOUT(D3)
6
7
5
4-BIT
LATCH
MUX
1
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
8-BIT
SHIFT-REGISTER
8
16
10
4
9
REF
HOLD_THRU
SHDN
V+
DGND
V–
6915 BD01
(DFN Package Only)
IN +
2
+
CS
IN –
1
CH
–
11
CF
OUT
GAIN
CONTROL
RESISTOR
ARRAY
10
PARALLEL_SERIAL
9
MUX
CS(D0)
DIN(D1)
CLK(D2)
DOUT(D3)
4
5
6
REF
4-BIT
LATCH
DGND
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
8-BIT
SHIFT-REGISTER
12
8
3
7
V+
DGND
V–
6915 BD02
6915fb
11
LTC6915
Timing Diagram
t4
t1
t2
t6
t3
t7
CLK
t9
D3
DIN
D2
D1
D0
D7 • • • • D4
D3
t5
CS/LD
t8
DOUT
D4
D3
D2
D1
PREVIOUS BYTE
D0
D7 • • • • D4
CURRENT BYTE
D3
6915 TD
Operation
Theory of Operation (Refer to Block Diagrams)
The LTC6915 uses an internal capacitor (CS) to sample
a differential input signal riding on a DC common mode
voltage (the sampling rate is 3kHz and the input switchon resistance is 1k to 2k, depending on the power supply
voltage). This capacitor’s charge is transferred to a second internal hold capacitor (CH) translating the common
mode voltage of the input differential signal to that of
REF pin. The resulting signal is amplified by a zero-drift
op amp in the noninverting configuration. Gain control
within the amplifier occurs by switching resistors from a
matched resistor array. The LTC6915 has 14 levels of gain,
controlled by the parallel or serial interface. A feedback
capacitor CF helps to reduce the switching noise. Due to
the input sampling, an LTC6915 may produce aliasing
errors for input signals greater than 1.5kHz (one half the
3kHz sampling frequency). However, if the input signal is
bandlimited to less than 1.5kHz then an LTC6915 is useful
as instrumentation or as a differential to single-ended AC
amplifier with programmable gain.
Parallel Interface
As shown in Figure 1, connecting PARALLEL_SERIAL
to V+ allows the gain control code to be set through the
parallel lines (D3, D2, D1, D0). When HOLD_THRU is
low (referenced to DGND) or floating, the parallel gain
control bits (D3 ~ D0) directly control the PGA gain. When
HOLD_THRU is high, the parallel gain control bits are read
into and held by a 4-bit latch. Any change at D3 ~ D0 will
not affect the PGA gain when HOLD_THRU is high. Note
that the DFN12 package does not have the HOLD_THRU
pin. Instead, it is tied to DGND internally. The DOUT(D3)
pin is bidirectional (output in serial mode, input in parallel
mode). In parallel mode, the voltage at DOUT(D3) cannot
exceed V+; otherwise, large currents can be injected to V+
through the parasitic diode (see Figure 2). Connecting a
10k resistor at the DOUT(D3) pin if parallel mode is selected
(see Figure 1) is recommended for current limiting.
Serial Interface
Connecting PARALLEL_SERIAL to V– allows the gain
control code to be set through the serial interface. When
CS is low, the serial data on DIN is shifted into an 8-bit
shift-register on the rising edge of the clock, with the MSB
transferred first (see Figure 3). Serial data on DOUT is
shifted out on the clock’s falling edge. A high CS will load
the 4 LSBs of the shift-register into a 4-bit D-latch, which
are the gain control bits. The clock is disabled internally
when CS is pulled high. Note: CLK must be low before CS
is pulled low to avoid an extra internal clock pulse.
6915fb
12
LTC6915
Operation
DOUT is always active in serial mode (never tri-stated).
This simplifies the daisy chaining of the multiple devices.
DOUT cannot be “wire-or” to other SPI outputs. In addition,
DOUT does not return to zero at the end of transmission,
i.e. when CS is pulled high.
A LTC6915 may be daisy-chained with other LTC6915s
or other devices having serial interfaces by connecting
the DOUT to the DIN of the next chip while CLK and CS
remain common to all chips in the daisy chain. The serial
data is clocked to all the chips then the CS signal is pulled
high to update all of them simultaneously. Figure 4
shows an example of two LTC6915s in a daisy chained SPI
configuration.
5V
1
2
3
VIN
4
5
6
7
8
LTC6915
V+
SHDN
IN –
OUT
IN+
SENSE
V–
REF
HOLD_THRU
NC
CS(D0)
P/S
DIN(D1)
DGND
CLK(D2) DOUT(D3)
16
5V
1
0.1µF
15
2
VOUT
14
3
VIN
13
4
12
5
11
10
µP
9
D0
6
D1
7
D2
8
LTC6915
SHDN
IN–
IN+
V+
OUT
SENSE
V–
REF
HOLD_THRU
NC
CS(D0)
P/S
DIN(D1)
DGND
CLK(D2) DOUT(D3)
16
0.1µF
15
VOUT
14
13
12
11
10
10k
9
D3
PARALLEL GAIN CONTROL CODE = 1010
VOUT = 29 VIN = 512VIN
GAIN IS SET BY MICROPROCESSOR. A 10k RESISTOR
ON DOUT(D3) PROTECT THE DEVICE WHEN VD3 > V +
6915 F01
Figure 1. PGA in the Parallel Control Mode
V+
4-BIT GAIN
CONTROL CODE
4-BIT
LATCH
CS
DOUT(D3)
DGND
(INTERNAL
NODE)
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
8-BIT
SHIFT-REGISTER
DIN
V–
DOUT
6915 F02
Figure 2. Bidirectional Nature of DOUT/D3 Pin
CLK
(D3)
6915 F03
Figure 3. Diagram of Serial Interface (MSB First Out)
6915fb
13
LTC6915
Operation
1
0.1µF 2
3
VIN
4
–5V
µP
0.1µF
5
CS
6
DIN
7
CLK
8
LTC6915
SHDN #1
V+
IN–
OUT
IN+
SENSE
V–
REF
HOLD_THRU
NC
CS(D0)
P/S
DIN(D1)
DGND
CLK(D2) DOUT(D3)
16
15
1
0.1µF
0.1µF 2
VOUT
14
VIN
13
4
–5V
0.1µF
12
11
3
5
6
–5V
10
7
9
8
LTC6915
SHDN #2
V+
IN –
OUT
IN+
SENSE
V–
REF
HOLD_THRU
NC
CS(D0)
P/S
DIN(D1)
DGND
CLK(D2) DOUT(D3)
16
15
0.1µF
VOUT
14
13
12
11
–5V
10
9
DOUT
CLK
DIN
D15
D11
D10
D9
D8
D7
D3
D2
D1
D0
GAIN CODE FOR #1
GAIN CODE FOR #2
CS/LD
6915 F04
Figure 4. 2 PGAs in a Daisy Chain
The amplifier’s gain is set as follows:
D3, D2, D1, D0
Gain
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101~
1111
0
1
2
4
8
16
32
64
128
256
512
1024
2048
4096
Input Voltage Range
±5 Volt Operation
The input common mode voltage range of the LTC6915
is rail-to-rail. However, the following equation limits the
size of the differential input voltage:
When using the LTC6915 with supplies over 5.5V, care must
be taken to limit the maximum difference between any of
the input pins (IN+ or IN– ) and the REF pin to 5.5V, i.e.,
V – ≤ (VIN + – VIN –) + VREF ≤ V+ – 1.3
|VIN + – VREF| < 5.5 and |VIN– – VREF| < 5.5
Where VIN+ and VIN– are the voltage of the differential
input pins, V+ and V– are the positive and negative supply voltages respectively and VREF is the voltage of REF
pin. In addition, VIN+ and VIN– must not exceed the power
supply voltages, i.e.,
If not, the device will be damaged. For example, if railto-rail input operation is desired when the supplies are at
±5V, the REF pin should be 0, ±0.5V. As a second example,
if the V+ pin is 10V, and the V– and REF pins are at 0, the
inputs should not exceed 5.5V.
V– < VIN + < V+ and V – < VIN – < V+
6915fb
14
LTC6915
Operation
Settling Time
The sampling rate is 3kHz and the input sampling period
during which CS is charged to the input differential voltage,
VIN, is approximately 150µs. First assume that on each
input sampling period, CS is charged fully to VIN. Since
CS = CH (= 1000pF), a change in the input will settle to
N bits of accuracy at the op amp noninverting input after
N clock cycles or 333µs(N). The settling time at the OUT
pin is also affected by the internal op amp. Since the gain
bandwidth of the internal op amp is typically 200kHz, the
settling time is dominated by the switched-capacitor front
end for gains below 100 (see the Low Gain Settling Time
vs Settling Accuracy and the Settling Time vs Gain graphs
in the Typical Performance Characteristics section). In addition, the worst case settling time after a device-enable
(active low on Pin 1 of a GN package) is equal to the settling
due to the gain plus the input settling time (333µs • N).
For example, if an LTC6915 is enabled with a logic high on
Pin 1 then, the maximum settling time to 10 bits of accuracy (0.1%) and a gain equal to 100 is 8.33ms ([333µs
• 1024] + 5ms).
Input Current
Whenever the differential input VIN changes, CH must be
charged up to the new input voltage via CS. This results
in an input charging current during each input sampling
period. Eventually, CH and CS will reach VIN and ideally,
the input current would go to zero for DC inputs.
In reality, there are additional parasitic capacitors which
disturb the charge on CS every cycle even if VIN is a DC
voltage. For example, the parasitic bottom plate capacitor
on CS must be charged from the voltage on the REF pin to
the voltage on the IN– pin every cycle. The resulting input
charging current decays exponentially during each input
sampling period with a time constant equal to RSCS. If the
voltage disturbance due to these currents settles before
the end of the sampling period, there will be no errors due
to source resistance or the source resistance mismatch
between IN+ and IN–. With RS less than 10k, no DC errors
occur due to input current mismatch.
In the Typical Performance Characteristics section of this
data sheet, there are curves showing the additional error
from non-zero source resistance in the inputs. If there
are no large capacitors across the inputs, the amplifier is
less sensitive to source resistance and source resistance
mismatch. When large capacitors are placed across the
inputs, the input charging currents are placed across
the inputs. The input charging currents described above
result in larger DC errors, especially with source resistor
mismatches.
Power Supply Bypassing
In a dual supply operation, connect a 0.1µF bypass capacitor from each power supply pin (V+ and V–) to an
analog round plance surrounding an LTC6915. The bypass
capacitor trace to the supply pins must be less than
0.2 inches (an X7R or X5R capacitor type is recommended).
In single supply operation, connect the V– pin to the analog
ground plane and bypass the V+ pin.
Shutdown Modes
The IC has two shutdown modes, hardware shutdown and
software shutdown. When SHDN is tied to V+, the IC is in
hardware shutdown mode. During this shutdown mode,
the gain setting digital interface (serial or parallel) and the
main op amp are both disabled, thus the PGA dissipates
very small supply current (see the Electrical Characteristic
table). When SHDN is floating, an internal current source
will pull it down to V –. The digital interface is turned on to
read the gain setting codes. The IC is in normal amplification mode as long as the gain control code is other than
0000. If the gain control code is 0000, the IC operates in
software shutdown mode, i.e., the main op amp is turned
off so that the PGA dissipates less power. The DFN package
does not have hardware shutdown.
Setting the Voltage at the REF Pin
The current coming out of the REF pin may affect the
reference voltage at the REF pin (VREF). If VREF is set by
a resistive divider then the VREF voltage is a function of
the VOUT voltage (see Figure 5). In order to minimize the
VREF variations, the total resistance of R1 plus R2 should
be much less than 32k (5k or less) or use a voltage reference to set VREF.
LTC6915
+
OUT
–
VOUT
V+
R1
V
– VREF
IREF = OUT
32k
R = 32k
VREF
0.1µF
REF
+
R2
–
V
V
V
VREF =
+ OUT +
• (R1 R2 32k )
R1 32k R2
Figure 5
V–
6915 F05
6915fb
15
LTC6915
Typical Application
Multiplexing Two LTC6915’s
5V
5V
0.1µF
Send a gain code of 0000 to one IC to set its output to a
high impedance state and send a gain code other than 0000
to the second IC to set it for normal amplification. If both
devices are ON, the 200Ω resistors protect the outputs.
The sense pin connection maintains gain accuracy for
loads 1k or greater.
0.1µF
V+
SHDN
LTC6915
#1
IN–
OUT
VIN1
–5V
0.1µF
IN+
SENSE
V–
REF
HOLD_THRU
DATA
P
SELECT
(TTL
LEVELS) CLOCK
V+
SHDN
LTC6915
#2
IN–
OUT
200Ω
VIN2
–5V
0.1µF
NC
–5V
IN+
SENSE
V–
REF
PAR_SER
DGND
DIN
DGND
DOUT
CLK
DOUT
PAR_SER
DIN
CLK
VOUT
NC
HOLD_THRU
CS
CS
200Ω
–5V
6915 F06
Figure 6. A 2:1 Multiplexing Two LTC6915’s
with Daisy Chained Gain Control
Package Description
DE/UE Package
12-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1695 Rev D)
4.00 ±0.10
(2 SIDES)
7
0.70 ±0.05
1.70 ± 0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.40 ± 0.10
12
R = 0.05
TYP
3.30 ±0.05
3.60 ±0.05
2.20 ±0.05
R = 0.115
TYP
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
0.50 BSC
3.30 ±0.10
3.00 ±0.10
(2 SIDES)
1.70 ± 0.10
0.75 ±0.05
6
0.25 ± 0.05
1
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
(UE12/DE12) DFN 0806 REV D
0.50 BSC
2.50 REF
2.50 REF
0.00 – 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
NOTE:
1. DRAWING PROPOSED TO BE A VARIATION OF VERSION
(WGED) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
BOTTOM VIEW—EXPOSED PAD
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
16 15 14 13 12 11 10 9
.254 MIN
.009
(0.229)
REF
.150 – .165
.229 – .244
(5.817 – 6.198)
.0165 ±.0015
.150 – .157**
(3.810 – 3.988)
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
.015 ±.004
× 45°
(0.38 ±0.10)
.007 – .0098
(0.178 – 0.249)
.0532 – .0688
(1.35 – 1.75)
2 3
4
5 6
7
8
.004 – .0098
(0.102 – 0.249)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.008 – .012
(0.203 – 0.305)
TYP
.0250
(0.635)
BSC
GN16 (SSOP) 0204
6915fb
16
LTC6915
Revision History
(Revision history begins at Rev B)
REV
DATE
DESCRIPTION
PAGE NUMBER
B
6/11
Revised units for PSRR in Electrical Characteristics
5
6915fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
17
LTC6915
Typical Application
V+
V+
9
X1
4MHz 10
+ 1
V
C5
0.1µF
20
VDD
PIC16LF73
RC5/SDO
OSC1/
CLKIN RC4/SDI/SDA
RC3/SCK/SCL
OSC2/
CLKOUT RC2/CCP1
RC1/T1OSI/CCP2
BRIDGE
SENSOR
10k ZETEK
ZXM61P02F
R < 10K
16 MOSI
15 MISO
13 CS1
3
IN+
SENSE
V–
REF
6
28
LTC6915
IN –
5
12 CS2
V+
SHDN
2
4
14 SCLK
RB7
MCLR/
7
RAS/AN4/SS
VPP
6
RA4/T0CLK1
VSS
VSS
8
1
7
8
OUT
NC
HOLD_THRU
PAR_SER
CS(D0)
DGND
DIN(D1)
CLK(D2)
DOUT(D3)
C1
0.1µF
16
C2
0.1µF
15
1
14
VCC
13
2
12
11
10
1.25V
9
REF+
LTC2431
SDO
3
REF –
4
IN+
CS
5
IN –
FO
SCK
8
9
7
10
GND
19
6
0V
10k
MEASURE
STANDBY
V+
V+
CONTROL SIGNAL
4
C3
0.1µF
V+
VIN
VOUT
LT1790-1.25
GND1
1
GND2
2
6
C3
1µF
6915 F07
Figure 7. Bridge Amplifier with Programmable Gain and Analog to Digital Conversion. (Standby Current Less than 100µA)
Related Parts
PART NUMBER
DESCRIPTION
COMMENTS
LTC1043
Dual Precision Instrumentation Switched-Capacitor
Building Block
Rail-to-Rail Input, 120dB CMRR
LTC1100
Precision Zero-Drift Instrumentation Amplifier
Fixed Gains of 10 or 100, 10µV Offset, 50pA Input Bias Current
LTC1101
Precision, Micropower, Single Supply Instrumentation
Amplifier
Fixed Gain of 10 or 100, IS < 105µA
LTC1167
Single Resistor Gain Programmable, Precision
Instrumentation Amplifier
Single Gains Set Resistor, G = 1 to 10,000 Low Noise: 7.5nV/√Hz
LTC1168
Low Power Single Resistor Gain Programmable,
Precision Instrumentation Amplifiers
IS = 530µA
LTC1789-1
Single Supply, Rail-to-Rail Output, Micropower
Instrumentation Amplifier
IS = 80µA Max
LTC2050
Zero-Drift Operational Amplifier
SOT-23 Package
LTC2051
Dual Zero-Drift Operational Amplifier
MS8 Package
LTC2052
Quad Zero-Drift Operational Amplifier
GN16 Package
LTC2053
Rail-to-Rail Input and Output, Zero-Drift Instrumentation MS8 Package, 10µV Max VOS, 50nV/°C Max Drift
Amplifier with Resistor-Programmable Gain
LTC6800
Rail-to-Rail Input and Output, Instrumentation Amplifier
with Resistor-Programmable Gain
MS8 Package, 100µV Max VOS, 250nV/°C Max Drift
6915fb
18 Linear Technology Corporation
LT 0611 REV B • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
LINEAR TECHNOLOGY CORPORATION 2004
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