LTC6948
Ultralow Noise 0.37GHz to
6.39GHz Fractional-N Synthesizer
with Integrated VCO
Description
Features
Low Noise Fractional-N PLL with Integrated VCO
nn No ∆-∑ Modulator Spurs
nn 18-Bit Fractional Denominator
nn –226 dBc/Hz Normalized In-Band Phase Noise Floor
nn –274 dBc/Hz Normalized In-Band 1/f Noise
nn –157 dBc/Hz Wideband Output Phase Noise Floor
nn Excellent Integer Boundary Spurious Performance
nn Output Divider (1 to 6, 50% Duty Cycle)
nn Output Buffer Muting
nn Reference Input Frequency Up to 425MHz
nn Fast Frequency Switching
nn FracNWizard™ Software Design Tool Support
The LTC®6948 is a high performance, low noise, 6.39GHz
phase-locked loop (PLL) with a fully integrated VCO,
including a reference divider, phase-frequency detector
(PFD), ultralow noise charge pump, fractional feedback
divider, and VCO output divider.
Applications
Output Frequency Options
nn
Wireless Basestations (LTE, WiMAX, W-CDMA, PCS)
Microwave Data Links
nn Military and Secure Radio
nn Test and Measurement
O_DIV = 1
2.240 to 3.740 3.080 to 4.910 3.840 to 5.790 4.200 to 6.390
nn
O_DIV = 2
1.120 to 1.870 1.540 to 2.455 1.920 to 2.895 2.100 to 3.195
O_DIV = 3
0.747 to 1.247 1.027 to 1.637 1.280 to 1.930 1.400 to 2.130
O_DIV = 4
0.560 to 0.935 0.770 to 1.228 0.960 to 1.448 1.050 to 1.598
O_DIV = 5
0.448 to 0.748 0.616 to 0.982 0.768 to 1.158 0.840 to 1.278
O_DIV = 6
0.373 to 0.623 0.513 to 0.818 0.640 to 0.965 0.700 to 1.065
nn
The fractional divider uses an advanced, 4th order Δ∑
modulator which provides exceptionally low spurious
levels. This allows wide loop bandwidths, producing
extremely low integrated phase noise values.
The programmable VCO output divider, with a range of 1
through 6, extends the output frequency range.
LTC6948-1
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
FracNWizard is a trademark of Analog Devices, Inc. All other trademarks are the property of
their respective owners.
LTC6948-2
LTC6948-3
LTC6948-4
Typical Application
6.3GHz Wideband Receiver
1.6nF
10µH
76.8Ω
5V
15Ω
0.1µF 3.3V
1µF
LTC6948-4 Phase Noise,
fRF = 6236MHz
76.8Ω
2.4nF
–90
UNUSED OUTPUT
AVAILABLE FOR
OTHER USE
50Ω
3.3V
0.1µF
GND
CP
VCP+
VREF+
VVCO+
VRF+
3.3V
0.1µF
BB
3.3V
RF+
0.1µF
LTC6948-4
RF–
SPI BUS
GND
51.1Ω
GND
REF–
1µF
REF+
STAT
CS
SCLK
SDI
SDO
LDO
V D+
BVCO
GND
CMA
CMB
CMC
GND
TB
TUNE
3.3V
68nH
68nH 100pF
–100
0.01µF
1µF
MUTE
100MHz
56nF
0.01µF
2.2µF
1µF
R = 2, fPFD = 50MHz
N = 84 TO 127.8
LBW = 186kHz
O=1
PHASE NOISE (dBc/Hz)
1µF
–110
–120
–130
RMS NOISE = 0.412°
–140 RMS JITTER = 183fs
fPFD = 50MHz
–150 LOOP BW = 186kHz
INTN = 0
CPLE = 1
–160
1M
1k
100
10k
100k
OFFSET FREQUENCY (Hz)
10M 40M
6946 TA01b
0.01µF
100pF
fLO = 4200MHz TO 6390MHz IN 190.7Hz STEPS
RF INPUT SIGNAL
LO IF
RF
IF OUTPUT
6948 TA01a
6948fa
For more information www.linear.com/LTC6948
1
LTC6948
Absolute Maximum Ratings
Pin Configuration
(Note 1)
VVCO+
GND
VCP+
CP
REF–
VREF+
TOP VIEW
Supply Voltages
V+ (VREF+, VRF+, VD+) to GND................................3.6V
VCP+, V VCO+ to GND..............................................5.5V
Voltage on CP Pin..................GND – 0.3V to VCP+ + 0.3V
Voltage on all other Pins............GND – 0.3V to V+ + 0.3V
Operating Junction Temperature Range, TJ (Note 2)
LTC6948I............................................ –40°C to 105°C
Junction Temperature, TJMAX................................. 125°C
Storage Temperature Range................... –65°C to 150°C
28 27 26 25 24 23
REF+ 1
22 BVCO
STAT 2
21 GND
CS 3
20 CMA
19 CMB
SCLK 4
29
GND
SDI 5
18 CMC
SDO 6
17 GND
LDO 7
16 TB
VD+ 8
15 TUNE
BB
VRF
+
RF+
RF
–
GND
MUTE
9 10 11 12 13 14
UFD PACKAGE
28-LEAD (4mm × 5mm) PLASTIC QFN
TJMAX = 125°C, θJCbottom = 7°C/W
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
Order Information
http://www.linear.com/product/LTC6948#orderinfo
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
JUNCTION TEMPERATURE RANGE
LTC6948IUFD-1#PBF
LTC6948IUFD-1#TRPBF
69481
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 105°C
LTC6948IUFD-2#PBF
LTC6948IUFD-2#TRPBF
69482
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 105°C
LTC6948IUFD-3#PBF
LTC6948IUFD-3#TRPBF
69483
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 105°C
LTC6948IUFD-4#PBF
LTC6948IUFD-4#TRPBF
69484
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 105°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
Available Options
PACKAGE STYLE
OUTPUT FREQUENCY RANGE vs OUTPUT DIVIDER SETTING (GHz)
VCO FREQUENCY
RANGE (GHz)
QFN-28 (UFD28)
0 DIV = 6
0 DIV = 5
0 DIV = 4
0 DIV = 3
0 DIV = 2
0 DIV = 1
2.240 to 3.740
LTC6948IUFD-1
0.373 to 0.623
0.448 to 0.748
0.560 to 0.935
0.747 to 1.247
1.120 to 1.870
2.240 to 3.740
3.080 to 4.910
LTC6948IUFD-2
0.513 to 0.818
0.616 to 0.982
0.770 to 1.228
1.027 to 1.637
1.540 to 2.455
3.080 to 4.910
3.840 to 5.790
LTC6948IUFD-3
0.640 to 0.965
0.768 to 1.158
0.960 to 1.448
1.280 to 1.930
1.920 to 2.895
3.840 to 5.790
4.200 to 6.390
LTC6948IUFD-4
0.700 to 1.065
0.840 to 1.278
1.050 to 1.598
1.400 to 2.130
2.100 to 3.195
4.200 to 6.390
Overlapping Frequency Bands
2
6948fa
For more information www.linear.com/LTC6948
LTC6948
Electrical Characteristics
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VREF+ = VD+ = VRF+ = 3.3V, VCP+ = VVCO+ = 5V unless otherwise
specified (Note 2). All voltages are with respect to GND.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
425
MHz
Reference Inputs (REF+, REF–)
fREF
Input Frequency
VREF
Input Signal Level
Single-Ended, 1µF AC-Coupling Capacitors
Input Slew Rate
l
10
l
0.5
l
20
l
1.65
1.85
2.25
V
l
5.8
8.4
11.6
kΩ
Input Duty Cycle
2
2.7
50
Self-Bias Voltage
Input Resistance
Differential
Input Capacitance
Differential
fVCO
Frequency Range
LTC6948-1 (Note 3)
LTC6948-2 (Note 3)
LTC6948-3 (Note 3)
LTC6948-4 (Note 3)
l
l
l
l
KVCO
Tuning Sensitivity
LTC6948-1 (Notes 3, 4)
LTC6948-2 (Notes 3, 4)
LTC6948-3 (Notes 3, 4)
LTC6948-4 (Notes 3, 4)
l
l
l
l
VP-P
V/µs
%
14
pF
VCO
2.24
3.08
3.84
4.20
3.74
4.91
5.79
6.39
4.7 to 7.2
4.7 to 7.0
4.0 to 6.0
4.5 to 6.5
GHz
GHz
GHz
GHz
%Hz/V
%Hz/V
%Hz/V
%Hz/V
RF Output (RF+, RF–)
fRF
Output Frequency
O
Output Divider Range
All Integers Included
l
0.373
l
1
Output Duty Cycle
PRF-SE
6.39
GHz
6
50
%
Output Resistance
Single-Ended, Each Output to VRF
+
l
100
136
175
Ω
Output Power, Single-Ended, fRF = 900MHz
RFO[1:0] = 0, RZ = 50Ω, LC Match
RFO[1:0] = 1, RZ = 50Ω, LC Match
RFO[1:0] = 2, RZ = 50Ω, LC Match
RFO[1:0] = 3, RZ = 50Ω, LC Match
l
l
l
l
–9
–6.1
–2.9
0.1
–7.3
–4.5
–1.4
1.5
–5.5
–2.8
0.2
3
dBm
dBm
dBm
dBm
Output Power, Muted, fRF = 900MHz
RZ = 50Ω, Single-Ended, O = 2 to 6
l
–80
dBm
Mute Enable Time
l
110
ns
Mute Disable Time
l
170
ns
l
100
MHz
l
l
l
l
l
76.1
66.3
56.1
45.9
34.3
MHz
MHz
MHz
MHz
MHz
11.2
mA
±6
%
±3.5
±2
%
%
Phase/Frequency Detector
fPFD
Input Frequency
Integer mode
Fractional mode
LDOEN = 0
LDOV = 3, LDOEN = 1
LDOV = 2, LDOEN = 1
LDOV = 1, LDOEN = 1
LDOV = 0, LDOEN = 1
Charge Pump
ICP
Output Current Range
8 Settings (See Table 6)
Output Current Source/Sink Accuracy
All Settings, V(CP) = VCP+/2
Output Current Source/Sink Matching
ICP = 1.0mA to 2.8mA, V(CP) = VCP+/2
ICP = 4.0mA to 11.2mA, V(CP) = VCP+/2
Output Current vs Output Voltage Sensitivity (Note 5)
Output Current vs Temperature
V(CP) = VCP+/2
Output Hi-Z Leakage Current
ICP = 11.2mA, CPCLO = CPCHI = 0 (Note 5)
1
l
0.2
l
170
1
ppm/°C
%/V
0.03
nA
6948fa
For more information www.linear.com/LTC6948
3
LTC6948
Electrical Characteristics
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VREF+ = VD+ = VRF+ = 3.3V, VCP+ = VVCO+ = 5V unless otherwise
specified (Note 2). All voltages are with respect to GND.
SYMBOL
PARAMETER
CONDITIONS
VCLMP-LO
Low Clamp Voltage
CPCLO = 1
0.84
V
VCLMP-HI
High Clamp Voltage
CPCHI = 1, Referred to VCP+
–0.96
V
0.48
V/V
VMID
MIN
+ – GND)
Mid-Supply Output Bias Ratio
Referred to (VCP
TYP
MAX
UNITS
Reference (R) Divider
R
All Integers Included
l
1
31
Counts
All Integers Included, Integer Mode
All Integers Included, Fractional Mode
l
l
32
35
1023
1019
Counts
Counts
Numerator Range
All Integers Included
l
1
262143
Counts
Output Voltage
LDO Enabled, Four Values
LDO Disabled
External Pin Capacitance
Required for LDO Stability
l
0.047
1.55
Divide Range
VCO (N) Divider
N
Divide Range
Fractional ∆∑ Modulator
Modulator LDO
1.7 to 2.6
VD+
0.1
V
V
1
µF
Digital Pin Specifications
VIH
High Level Input Voltage
MUTE, CS, SDI, SCLK
l
VIL
Low Level Input Voltage
MUTE, CS, SDI, SCLK
l
VIHYS
Input Voltage Hysteresis
MUTE, CS, SDI, SCLK
Input Current
MUTE, CS, SDI, SCLK
V
0.8
250
+ – 400mV
IOH
High Level Output Current
SDO and STAT, VOH = VD
l
IOL
Low Level Output Current
SDO and STAT, VOL = 400mV
l
SDO Hi-Z Current
mV
±1
l
–3.3
2.0
–1.9
3.4
µA
mA
mA
±1
l
V
µA
Digital Timing Specifications (See Figure 6 and Figure 7)
tCKH
SCLK High Time
l
25
ns
tCKL
SCLK Low Time
l
25
ns
tCSS
CS Setup Time
l
10
ns
tCSH
CS High Time
l
10
ns
tCS
SDI to SCLK Setup Time
l
6
ns
tCH
SDI to SCLK Hold Time
l
6
tDO
SCLK to SDO Time
To VIH/VIL/Hi-Z with 30pF Load
ns
l
16
ns
Power Supply Voltages
VREF+ Supply Range
l
3.15
3.3
3.45
V
+ Supply Range
l
3.15
3.3
3.45
V
l
3.15
3.3
3.45
V
l
4.75
5.0
5.25
V
l
4.0
5.25
V
VD
VRF+ Supply Range
VVCO
VCP
+ Supply Range
+ Supply Range
Power Supply Currents
IDD
VD+ Supply Current
Digital Inputs at Supply Levels, Integer Mode l
l
Digital Inputs at Supply Levels, Fractional
Mode, fPFD = 66.3MHz, LDOV[1:0] = 3
18.2
1500
22
µA
mA
ICC(5V)
Sum VCP+, VVCO+ Supply Currents
ICP = 11.2mA
ICP = 1.0mA
PDALL = 1
48
26
450
60
35
1000
mA
mA
µA
4
l
l
l
6948fa
For more information www.linear.com/LTC6948
LTC6948
Electrical Characteristics
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VREF+ = VD+ = VRF+ = 3.3V, VCP+ = VVCO+ = 5V unless otherwise
specified (Note 2). All voltages are with respect to GND.
SYMBOL
ICC(3.3V)
PARAMETER
CONDITIONS
+, V
Sum VREF
+ Supply Currents
MIN
RF Muted, OD[2:0] = 1
RF Enabled, RFO[1:0] = 0, OD[2:0] = 1
RF Enabled, RFO[1:0] = 3, OD[2:0] = 1
RF Enabled, RFO[1:0] = 3, OD[2:0] = 2
RF Enabled, RFO[1:0] = 3, OD[2:0] = 3
RF Enabled, RFO[1:0] = 3, OD[2:0] = 4 to 6
PDALL = 1
RF
l
l
l
l
l
l
l
TYP
MAX
UNITS
70.4
81.1
91.3
109.2
114.8
119.6
53
80
95
105
125
135
140
250
mA
mA
mA
mA
mA
mA
µA
Phase Noise and Spurious
LVCO
VCO Phase Noise (LTC6948-1, fVCO = 3.0GHz, 10kHz Offset
fRF = 3.0GHz, OD[2:0] = 1 (Note 6))
1MHz Offset
40MHz Offset
–80
–130
–157
dBc/Hz
dBc/Hz
dBc/Hz
VCO Phase Noise (LTC6948-2, fVCO = 4.0GHz, 10kHz Offset
fRF = 4.0GHz, OD[2:0] = 1 (Note 6))
1MHz Offset
40MHz Offset
–77
–127
–156
dBc/Hz
dBc/Hz
dBc/Hz
VCO Phase Noise (LTC6948-3, fVCO = 5.0GHz, 10kHz Offset
fRF = 5.0GHz, OD[2:0] = 1 (Note 6))
1MHz Offset
40MHz Offset
–75
–126
–155
dBc/Hz
dBc/Hz
dBc/Hz
VCO Phase Noise (LTC6948-4, fVCO = 6.0GHz, 10kHz Offset
fRF = 6.0GHz, OD[2:0] = 1 (Note 6))
1MHz Offset
40MHz Offset
–73
–123
–154
dBc/Hz
dBc/Hz
dBc/Hz
VCO Phase Noise (LTC6948-3, fVCO = 5.0GHz, 10kHz Offset
fRF = 2.50GHz, OD[2 :0] = 2 (Note 6))
1MHz Offset
40MHz Offset
–81
–132
–155
dBc/Hz
dBc/Hz
dBc/Hz
VCO Phase Noise (LTC6948-3, fVCO = 5.0GHz, 10kHz Offset
fRF = 1.667GHz, OD[2 :0] = 3 (Note 6))
1MHz Offset
40MHz Offset
–84
–135
–156
dBc/Hz
dBc/Hz
dBc/Hz
VCO Phase Noise (LTC6948-3, fVCO = 5.0GHz, 10kHz Offset
fRF = 1.25GHz, OD[2 :0] = 4 (Note 6))
1MHz Offset
40MHz Offset
–87
–138
–156
dBc/Hz
dBc/Hz
dBc/Hz
VCO Phase Noise (LTC6948-3, fVCO = 5.0GHz, 10kHz Offset
fRF = 1.00GHz, OD[2 :0] = 5 (Note 6))
1MHz Offset
40MHz Offset
–89
–140
–157
dBc/Hz
dBc/Hz
dBc/Hz
VCO Phase Noise (LTC6948-3, fVCO = 5.0GHz, 10kHz Offset
fRF = 0.833GHz, OD[2 :0] = 6 (Note 6))
1MHz Offset
40MHz Offset
–90
–141
–158
dBc/Hz
dBc/Hz
dBc/Hz
LNORM(INT)
Integer Normalized In-Band Phase Noise
Floor
INTN = 1, ICP = 5.6mA (Notes 7, 8, 10)
–226
dBc/Hz
LNORM(FRAC)
Fractional Normalized In-Band Phase Noise
Floor
INTN = 0, CPLE = 1, ICP = 5.6mA
(Notes 7, 8, 10)
–225
dBc/Hz
L1/f
Normalized In-Band 1/f Phase Noise
ICP = 11.2mA (Notes 7, 11)
–274
dBc/Hz
In-Band Phase Noise Floor
Fractional Mode, CPLE = 1
(Notes 7, 9, 10, 12)
–113
dBc/Hz
Integrated Phase Noise from 100Hz to
40MHz
Fractional Mode, CPLE = 1 (Notes 9, 12)
0.14
°RMS
Spurious
Fractional Mode, fOFFSET = fPFD, PLL locked
(Notes 8, 13, 14)
–98
dBc
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC6948I is guaranteed to meet specified performance limits
over the full operating junction temperature range of –40°C to 105°C.
6948fa
For more information www.linear.com/LTC6948
5
LTC6948
Electrical Characteristics
Note 3: Valid for 1.60V ≤ V(TUNE) ≤ 2.85V with part calibrated after a
power cycle or software power-on reset (POR).
Note 4: Based on characterization.
Note 5: For 0.9V < V(CP) < (VCP+ – 0.9V).
Note 6: Measured outside the loop bandwidth, using a narrowband loop,
RFO[1:0] = 3.
Note 7: Measured inside the loop bandwidth with the loop locked.
Note 8: Reference frequency supplied by Wenzel 501-04516,
fREF = 100MHz, PREF = 10dBm.
Note 9: Reference frequency supplied by Wenzel 500-23571,
fREF = 61.44MHz, PREF = 10dBm.
Note 10: Output phase noise floor is calculated from normalized phase
noise floor by LOUT = LNORM + 10log10 (fPFD) + 20log10 (fRF/fPFD).
Note 11: Output 1/f noise is calculated from normalized 1/f phase noise by
LOUT(1/f) = L1/f + 20log10 (fRF) – 10log10 (fOFFSET).
Note 12: ICP = 5.6mA, fPFD = 61.44MHz, FILT[1:0] = 0, Loop BW = 180kHz;
fRF = 2377.7MHz, fVCO = 4755.4MHz (LTC6948-3)
Note 13: ICP = 5.6mA, fPFD = 25MHz, FILT[1:0] = 0, Loop BW = 73kHz;
fRF = 891.85MHz, fVCO = 2675Hz (LTC6948-1), fVCO = 4459MHz
(LTC6948‑2), fVCO = 5351MHz (LTC6948-3, LTC6948-4).
Note 14: Measured using DC1959.
T
Typical
Performance Characteristics A = 25°C. VREF+ = VD+ = VRF+ = 3.3V, VCP+ = VVCO+ =
5V, INTN = 0, DITHEN = 1, CPLE = 1, RFO[1:0] = 3, unless otherwise noted.
BST = 1
FILT = 0
105°C
25°C
–40°C
SENSITIVITY (dBm)
–20
–25
–30
–35
5
3
2
–40
–45
–50
0
1
–2
–3
–4
–4
0
–1
4
3
3
2
2
1
1
0
–1
–3
–3
–4
–4
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
OUTPUT VOLTAGE (V)
6948 G04
6
5
4
–2
0
0
–5
ICP = 11.2mA
CPLE = 0
105°C
25°C
–40°C
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
OUTPUT VOLTAGE (V)
6948 G05
0.5
1.0
1.5
2.0
VOLTAGE (V)
2.5
3.0
6948 G03
Charge Pump Source Current
Error vs Voltage, Output Current
5
–2
–5
–5
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
OUTPUT VOLTAGE (V)
ERROR (%)
1
0
–1
Charge Pump Sink Current Error
vs Voltage, Temperature
ERROR (%)
ERROR (%)
2
1
6948 G02
CPLE = 0
1mA
5.6mA
11.2mA
3
2
–3
Charge Pump Sink Current Error
vs Voltage, Output Current
4
3
–2
0
105°C
25°C
–40°C
4
–1
6948 G01
5
5
0
–5
50 100 150 200 250 300 350 400 450
FREQUENCY (MHz)
TUNE Current vs Voltage,
Temperature
ICP = 11.2mA
CPRST = 1
CPLE = 0
105°C
25°C
–40°C
4
CURRENT (nA)
–15
CP Hi-Z Current vs Voltage,
Temperature
CURRENT (nA)
REF Input Sensitivity vs
Frequency
CPLE = 0
1mA
5.6mA
11.2mA
0
–1
–2
–3
–4
–5
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
OUTPUT VOLTAGE (V)
6948 G06
6948fa
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LTC6948
T
Typical
Performance Characteristics A = 25°C. VREF+ = VD+ = VRF+ = 3.3V, VCP+ = VVCO+ =
5V, INTN = 0, DITHEN = 1, CPLE = 1, RFO[1:0] = 3, unless otherwise noted.
2.0
1.5
3
1.0
2
0.5
0
–1
–1.0
–1.5
–5
0
LTC6948-4
LC = 68nH
CS = 100pF
105°C
25°C
–40°C
–2.0
–2.5
–3.0
–3.5
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
OUTPUT VOLTAGE (V)
0.5
1.5
6948 G07
O=6
–10
–25
–30
O=1
–35 LTC6948-4
LC = 68nH
–40 CS = 100pF
fRF = fVCO/O
–45
4.2
4.6
5.0
O=2
O=3
–75
6.2
O=4
–95
4.2
6.6
4.6
5.0
5.4
fVCO (MHz)
6948 G10
LTC6948-1 VCO Tuning Sensitivity
5.8
2.7
2.6
2.5
O=5
2.4
O=6
2.3
6.2
2.2
6.6
LTC6948-2 VCO Tuning Sensitivity
7.5
6.5
7.0
7.0
6.0
6.5
6.0
5.5
5.0
4.5
5.5
5.0
4.0
3.5
3.5
3.0
2.8 3.0 3.2 3.4
FREQUENCY (GHz)
3.6
3.8
6948 G13
3.0
25
4.5
4.0
2.6
20
5.0
4.0
2.4
10
15
TIME (µs)
5.5
4.5
2.2
5
7.0
3.5
3.0
0
LTC6948-3 VCO Tuning Sensitivity
7.5
6.5
–5
6948 G12
8.0
6.0
126MHz STEP
fPFD = 61.44MHz
fCAL = 1.28MHz
LOOP BW = 180kHz
MTCAL = 0
O=2
6948 G11
8.0
KVCO (%/V)
KVCO (%/V)
2.8
LTC6948-4, LC = 68nH
CS = 100pF, fRF = fVCO/O
–85
5.4
5.8
fVCO (GHz)
CALIBRATION TIME
2.9
–55
–65
6948 G09
3.0
KVCO (%/V)
HD3 (dBc)
O=4
6.6
LTC6948-3 Frequency Step
Transient
O=1
O=2
–20
6.5
5.5
–45
O=5
O=3
–15
2.5
3.5
4.5
FREQUENCY (GHz)
MUTE Output Power vs fVCO and
Output Divide
(Single-Ended on RF+)
POUT AT fVCO/O (dBm)
–5
O=4
–40
O=6
–50 LTC6948-4, L = 68nH,
C
CS = 100pF , fRF = fVCO/O
–55
4.6
5.4
6.2
5.0
5.8
4.2
fVCO (GHz)
6948 G08
RF Output HD3 vs Output Divide
(Single-Ended on RF+)
O=2
O=1
–35
–45
FREQUENCY (GHz)
–4
–30
–0.5
ICP = 11.2mA
CPLE = 0
105°C
25°C
–40°C
–3
O=5
O=3
–25
HD2 (dBc)
1
–20
0
POUT (dBm)
ERROR (%)
5
4
–2
RF Output HD2 vs Output Divide
(Single-Ended on RF+)
RF Output Power vs Frequency
(Single-Ended on RF+)
Charge Pump Source Current
Error vs Voltage, Temperature
3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0
FREQUENCY (GHz)
6948 G14
2.5
3.8
4.2
4.6
5.0
FREQUENCY (GHz)
5.4
5.8
6948 G15
6948fa
For more information www.linear.com/LTC6948
7
LTC6948
T
Typical
Performance Characteristics A = 25°C. VREF+ = VD+ = VRF+ = 3.3V, VCP+ = VVCO+ =
5V, INTN = 0, DITHEN = 1, CPLE = 1, RFO[1:0] = 3, unless otherwise noted.
–222
PHASE NOISE FLOOR (dBc/Hz)
KVCO (%/V)
6.0
5.5
5.0
4.5
4.0
–222
ICP = 5.6mA
CPLE = 1
7.0
–223
PHASE NOISE FLOOR (dBc/Hz)
7.5
6.5
Normalized In-Band Phase Noise
Floor vs CP Current
Normalized In-Band Phase Noise
Floor vs fVCO
LTC6948-4 VCO Tuning Sensitivity
–224
FRACTIONAL-N
–225
INTEGER-N
–226
fVCO = 5GHz
CPLE = 1
–223
–224
FRACTIONAL-N
–225
–226
INTEGER-N
3.5
3.0
4.3
4.7
5.1
5.5
5.9
FREQUENCY (GHz)
6.3
–227
6.7
2
3
LTC6948-1 VCO Phase Noise
–110
–130
PHASE NOISE (dBc/Hz)
–70
PHASE NOISE (dBc/Hz)
–80
–90
–100
–110
–120
–130
–90
–110
–120
–130
–140
–140
–150
–150
–150
–160
–160
10k
100k
1M
10M 40M
OFFSET FREQUENCY (Hz)
10k
100k
1M
10M 40M
OFFSET FREQUENCY (Hz)
1k
–75
fRF = fVCO = 6GHz
–50
PHASE NOISE (dBc/Hz)
–80
–90
–100
–110
–120
–130
fRF = fVCO/O
O=3
–90
–95
O=6
O=4
1k
10k
100k
1M
10M 40M
OFFSET FREQUENCY (Hz)
6948 G22
8
–105
2.2
2.4
2.6
fRF = fVCO/O
O=1
–80
O=2
–85
O=3
O=4
–90
–95
O=5
2.8 3.0 3.2
fVCO (GHz)
LTC6948-2 VCO Phase Noise vs
fVCO, Output Divide
(fOFFSET = 10kHz)
–75
O=2
–150
–160
–70
O=1
–85
–100
–140
10k
100k
1M
10M 40M
OFFSET FREQUENCY (Hz)
1k
6948 G21
LTC6948-1 VCO Phase Noise vs
fVCO, Output Divide
(fOFFSET = 10kHz)
–80
–60
–70
–160
6948 G20
LTC6948-4 VCO Phase Noise
–40
3.4
6948 G18
–100
–140
1k
11
–80
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
–60
–70
–120
9
fRF = fVCO = 5GHz
–50
–60
–100
7
ICP (mA)
LTC6948-3 VCO Phase Noise
–70
–90
5
–40
–60
–80
3
1
6948 G17
fRF = fVCO = 4GHz
–50
6948 G19
PHASE NOISE (dBc/Hz)
–227
6
LTC6948-2 VCO Phase Noise
–40
fRF = fVCO = 3GHz
–50
5
fVCO (GHz)
6948 G16
–40
4
3.6
3.8
6948 G23
–100
O=6
3.0
3.3
3.6
O=5
3.9
4.2
fVCO (GHz)
4.5
4.8
6948 G24
6948fa
For more information www.linear.com/LTC6948
LTC6948
T
Typical
Performance Characteristics A = 25°C. VREF+ = VD+ = VRF+ = 3.3V, VCP+ = VVCO+ =
5V, INTN = 0, DITHEN = 1, CPLE = 1, RFO[1:0] = 3, unless otherwise noted.
–70
fRF = fVCO/O
–75
O=1
–80
O=2
–85
O=3
O=4
–90
–95
3.8
4.2
O=3
–80
4.6
5.0
fVCO (GHz)
fRF = fVCO/O
O=4
–85
O=5
O=6
5.4
–95
5.8
4.3
4.7
5.1
6948 G25
5.5
5.9
fVCO (GHz)
6.3
–120
O=3
O=4
O=6
3.3
3.6
3.9
4.2
fVCO (GHz)
O=5
4.5
O=1
–130
O=2
–135
–145
4.8
2.2
O=3
O=4
fRF = fVCO/O
4.2
O=6
O=5
O=6
3.8
O=4
4.6
5.0
fVCO (GHz)
5.4
–145
5.8
4.3
1k
1M
10k
100k
OFFSET FREQUENCY (Hz)
–120
–140
–150
10M 40M
6948 G31
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
–110
RMS NOISE = 0.141°
fPFD = 61.44MHz
O=2
INTN = 0
CPLE = 1
LOOP BW = 180kHz
NOTES 9, 12
–160
100
1k
1M
10k
100k
OFFSET FREQUENCY (Hz)
6948 G32
5.5
5.9
fVCO (GHz)
6.3
6.7
6948 G30
–110
–120
–130
–140
–150
10M 40M
5.1
O=5
Closed-Loop Phase Noise,
LTC6948-2 fRF = 3646.464MHz
–100
–130
4.7
6948 G29
–100
–160
100
6948 G27
O=1
–135
–100
–150
3.8
O=3
–90
–140
3.6
O=2
–90
RMS NOISE = 0.074°
fPFD = 25MHz
O=3
INTN = 0
CPLE = 1
fIB-SPUR = 572kHz
LOOP BW = 73kHz
NOTES 8, 13
3.4
–130
–90
–130
2.8 3.0 3.2
fVCO (GHz)
LTC6948-4 VCO Phase Noise vs
fVCO, Output Divide
(fOFFSET = 1MHz)
Closed-Loop Phase Noise,
LTC6948-3 fRF = 2377.728MHz
–120
2.6
–140
6948 G28
–110
2.4
–125
Closed-Loop Phase Noise,
LTC6948-1 fRF = 891.857MHz
PHASE NOISE (dBc/Hz)
O=6
O=5
–120
fRF = fVCO/O
–140
3.0
O=4
6948 G26
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
O=2
–145
O=3
–140
–150
6.7
LTC6948-3 VCO Phase Noise vs
fVCO, Output Divide
(fOFFSET = 1MHz)
O=1
–130
–140
O=2
–135
–145
–125
–135
O=1
–130
O=2
O=5
LTC6948-2 VCO Phase Noise vs
fVCO, Output Divide
(fOFFSET = 1MHz)
–125
fRF = fVCO/O
O=1
–90
O=6
LTC6948-1 VCO Phase Noise vs
fVCO, Output Divide
(fOFFSET = 1MHz)
–125
fRF = fVCO/O
–75
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
–70
LTC6948-4 VCO Phase Noise vs
fVCO, Output Divide
(fOFFSET = 10kHz)
PHASE NOISE (dBc/Hz)
LTC6948-3 VCO Phase Noise vs
fVCO, Output Divide
(fOFFSET = 10kHz)
RMS NOISE = 0.224°
fPFD = 61.44MHz
O=1
INTN = 0
CPLE = 1
LOOP BW = 178kHz
NOTE 9
–160
100
1k
1M
10k
100k
OFFSET FREQUENCY (Hz)
10M 40M
6948 G33
6948fa
For more information www.linear.com/LTC6948
9
LTC6948
T
Typical
Performance Characteristics A = 25°C. VREF+ = VD+ = VRF+ = 3.3V, VCP+ = VVCO+ =
5V, INTN = 0, DITHEN = 1, CPLE = 1, RFO[1:0] = 3, unless otherwise noted.
POUT (dBm)
–40
–20
–40
–60
–80
–100dBc
–103dBc
–100
–120
–140
RBW = 100Hz
VBW = 100Hz
INTN = 0
CPLE = 1
O=2
NOTES 9, 14
–80
–91dBc
–78dBc
–40
–78dBc
–96dBc
–120
–120
3.3V CURRENT (mA)
O=2
O=3
O=4
O=5
O=6
89
36
88
35
87
34
86
33
32
84
83
–40
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
OUTPUT FREQUENCY (GHz)
O = 1, MUTE = 0
RFO = 3, ICP = 5.6mA
–20
0
6948 G37
20
14
12
LDOV = 2
10
8
LDOV = 1
6
LDOV = 0
4
25
16
30
6948 G38
LDOV = 3, 65MHz
14
12
LDOV = 2, 55MHz
10
LDOV = 1, 45MHz
8
6
LDOEN = 0
15
100
LDOEN = 0, 75MHz
18
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
16
5
80
20
LDOV = 3
2
60
VD
Temperature
(INTN = 0, PDFN = 0, fPFD Noted)
TC = 25°C
18
20
40
TJ (°C)
31
+ Supply Current vs LDOV,
VD+ Supply Current vs LDOV, fPFD
(INTN = 0, PDFN = 0)
10
37
85
–75
0
38
EXCLUDES VD+
90
5V CURRENT (mA)
IB SPUR LEVEL (dBc)
39
91
O=1
–70
–80
6948 G36
92
SPUR IN BAND
–45 fPFD = 50MHz
CPLE = 1
–65
–200 –150 –100 –50 0 50 100 150 200
FREQUENCY OFFSET (MHz IN 10kHz SEGMENTS)
LTC6948-4 Supply Current
–40
–60
–140
–70dBc
–72dBc
6948 G35
Integer Boundary Spur Power vs
Output Frequency, LTC6948-3
–55
RBW = 100Hz
VBW = 100Hz
INTN = 0
CPLE = 1
O=1
NOTES 8, 14
–80
–100
–246 –184 –123–61.4 0 61.4 123 184 246
FREQUENCY OFFSET (MHz IN 10kHz SEGMENTS)
LTC6948-4 Spurious Response
fRF = 6236MHz, fREF = 100MHz,
fPFD = 50MHz, Loop BW = 152kHz
–60
–100
6948 G34
–50
0
–20
–60
–140
–100 –75 –50 –25 0 25 50 75 100
FREQUENCY OFFSET (MHz IN 10kHz SEGMENTS)
LTC6948-3 Spurious Response
fRF = 2377.73MHz, fREF = 61.44MHz,
fPFD = 61.44MHz, Loop BW = 180k
POUT (dBm)
–20
0
RBW = 10Hz
VBW = 10Hz
INTN = 0
CPLE = 1
O=3
NOTES 8, 14
POUT (dBm)
0
LTC6948-1 Spurious Response
fRF = 891.85MHz, fREF = 100MHz,
fPFD = 25MHz, Loop BW = 74kHz
35 45 55
fPFD (MHz)
65
75
4
–40
LDOV = 0, 30MHz
–20
6948 G39
0
20
40
TJ (°C)
60
80
100
6948 G40
6948fa
For more information www.linear.com/LTC6948
LTC6948
Pin Functions
REF+, REF– (Pins 1, 28): Reference Input Signals. This
differential input is buffered with a low noise amplifier,
which feeds the reference divider. They are self-biased and
must be AC-coupled with 1µF capacitors. If used singleended with VREF+ ≤ 2.7VP-P, bypass REF– to GND with a
1µF capacitor. If used single-ended with VREF+ > 2.7VP-P,
bypass REF– to GND with a 47pF capacitor.
STAT (Pin 2): Status Output. This signal is a configurable
logical OR combination of the UNLOK, LOK, ALCHI, ALCLO,
THI, and TLO status bits, programmable via the STATUS
register. See the Operation section for more details.
CS (Pin 3): Serial Port Chip Select. This CMOS input initiates a serial port communication burst when driven low,
ending the burst when driven back high. See the Operation
section for more details.
SCLK (Pin 4): Serial Port Clock. This CMOS input clocks
serial port input data on its rising edge. See the Operation
section for more details.
SDI (Pin 5): Serial Port Data Input. The serial port uses
this CMOS input for data. See the Operation section for
more details.
SDO (Pin 6): Serial Port Data Output. This CMOS threestate output presents data from the serial port during a
read communication burst. Optionally attach a resistor of
>200k to GND to prevent a floating output. See the Applications Information section for more details.
LDO (Pin 7): Δ∑ Modulator LDO Bypass Pin. This pin
should be bypassed directly to the ground plane using a
low ESR ( 0)
CPMID
CP Bias to Mid-Rail
1
REV[3:0]
Rev Code
h1
CPRST
CP Tri-State
1
RFO[1:0]
RF Output Power
h3
CPUP
Force CP Pump Up
0
RSTFN
Force Modulator Reset (Auto Clears)
0
CPWIDE
Extend CP Pulse Width
0
DITHEN
Enable Fractional Numerator Dither
1
THI
CP Clamp High Flag
FILT[1:0]
REF Input Buffer Filter
h3
TLO
CP Clamp Low Flag
Integer Mode; Fractional Modulator Placed
in Standby
0
UNLOK
PLL Unlock Flag
x[5:0]
STAT Output OR Mask
INTN
24
SEED[7:0] Modulator Dither Seed Value
h001
h11
h04
6948fa
For more information www.linear.com/LTC6948
LTC6948
Applications Information
Introduction
where the fractional value F is given by Equation 4:
A PLL is a complex feedback system that may conceptually
be considered a frequency multiplier. The system multiplies
the frequency input at REF± and outputs a higher frequency
at RF±. The PFD, charge pump, N divider, VCO and external
loop filter form a feedback loop to accurately control the
output frequency (see Figure 13).
fPFD =
fREF
R
fVCO = fPFD • (N + F)
fRF =
fVCO
O
(7)
Using the above equations, the minimum output frequency
resolution fSTEP(MIN) produced by a unit change in the
fractional numerator NUM while in fractional mode is
given by Equation 8:
fSTEP(MIN) =
fREF
(8)
R •O• 218
(3)
LOOP FILTER
(FOURTH ORDER)
LTC6948
REF±
(6)
The output frequency fRF produced at the output of the O
divider is given by Equation 7:
When the loop is locked, the frequency fVCO (in Hz)
produced at the output of the VCO is determined by the
reference frequency fREF, the R and N divider values, and
the fractional value F, given by Equation 3:
(fREF)
(5)
and fVCO may be alternatively expressed as:
Output Frequency
(4)
The PFD frequency fPFD is given by the following equation:
The R and O divider and input frequency fREF are used to
set the output frequency resolution. When in fractional
mode, the Δ∑ modulator changes the N divider’s ratio
each PFD cycle to produce an average fractional divide
ratio. This achieves a much smaller frequency resolution
for a given fPFD as compared to integer mode.
fREF • (N + F )
R
NUM
218
NUM is programmable from 1 to 262143, or 218 – 1. When
using the LTC6948 in integer mode, F = 0.
The external loop filter is used to set the PLL’s loop
bandwidth BW. Lower bandwidths generally have better
spurious performance and lower Δ∑ modulator quantization
noise. Higher bandwidths can have better total integrated
phase noise.
fVCO =
F=
R_DIV
fPFD
KPFD
ICP
CP
26
÷R
C2
L1
R1
÷(N + F)
RZ
CP
CI
N_DIV
LF(s)
∆∑
RF±
(fRF)
O_DIV
÷O
TUNE
fVCO
15
KVCO
6948 F13
Figure 13. PLL Loop Diagram
6948fa
For more information www.linear.com/LTC6948
25
LTC6948
Applications Information
Alternatively, to calculate the numerator step size NUMSTEP
needed to produce a given frequency step fSTEP(FRAC), use
Equation 9:
NUM STEP =
fSTEP(FRAC) •R •O • 218
fREF
(9)
The output frequency resolution fSTEP(INT) produced by a
unit change in N while in integer mode is given by Equation 10:
f
fSTEP(INT) = REF
R •O
(10)
A stable loop, both in integer and fractional mode,
requires that the OSR is greater than or equal to 10.
Further, in fractional mode, OSR must be high enough
to allow the loop filter to reduce modulator quantization noise to an acceptable level.
Choosing a higher order loop filter when using the Δ∑
modulator allows for a smaller OSR, and thus a larger
loop bandwidth. Linear Technology’s FracNWizard
helps choose the appropriate OSR and BW values.
3) Select loop filter component RZ and charge pump current ICP based on BW and the VCO gain factor, KVCO.
BW (in Hz) is approximated by the following equation:
BW ≅
Loop Filter Design
A stable PLL system requires care in designing the external
loop filter. The Linear Technology FracNWizard application,
available from www.linear.com, aids in design and simulation of the complete system.
The loop design should use the following algorithm:
1) Determine the output frequency fRF and frequency step
size fSTEP based on application requirements. Using
Equations 3, 5, 7, and 8, change fREF, N, R, and O until
the application frequency constraints are met. Use the
minimum R value that still satisfies the constraints.
Then calculate B using Equation 1 and Tables 8 and
9.
2) Select the open loop bandwidth BW constrained by
fPFD and oversampling ratio OSR. The OSR is the ratio
of fPFD to BW (see Equation 11):
f
OSR = PFD
BW
(11)
or
BW =
(12)
or
RZ =
2 • π • BW • N
ICP • K VCO
where KVCO is in Hz/V, ICP is in Amps, and RZ is in
Ohms. KVCO is obtained from the VCO Tuning Sensitivity
in the Electrical Characteristics. Use ICP = 5.6mA to
lower in-band noise unless component values force
a lower setting.
4) Select loop filter components CI and CP based on BW
and RZ. A reliable second-order loop filter design can
be achieved by using the following equations for the
loop capacitors (in Farads).
fPFD
OSR
ICP • RZ • K VCO
2 • π •N
CI =
3.5
2 • π • BW • RZ
(13)
1
7 • π • BW • RZ
(14)
CP =
Use FracNWizard to aid in the design of higher order
loop filters.
where BW and fPFD are in Hz.
26
6948fa
For more information www.linear.com/LTC6948
LTC6948
Applications Information
Design and Programming Example
Also, from Equation 1 and Tables 8 and 9 determine B:
This programming example uses the DC1959 with the
LTC6948-2. Assume the following parameters of interest:
B = 48 and BD[3:0] = h5
fREF = 100MHz at 7dBm into 50Ω
A calibration cycle takes 12 to 14 clock cycles of fCAL. This
gives a VCO calibration time of approximately:
fSTEP = 50kHz
fRF = 1921.650MHz
From the Electrical Characteristics table:
The next step in the algorithm is choosing the open loop
bandwidth. Select the minimum bandwidth resulting from
the below constraints.
KVCO% = 4.7%Hz/V to 7%Hz/V
Determining Divider Values
Following the loop filter design algorithm, first determine
all the divider values. The maximum fPFD while in fractional
mode is less than 100MHz, so R must be greater than 1.
R = 2
Then, using Equations 5 and 7, calculate the following
values:
fPFD = 50MHz
Then using Equation 6:
N+F =
2 •1921.650MHz
= 76.866
50MHz
Therefore:
N = 76
F = 0.866
1) The OSR must be at least 10 (sets absolute maximum
BW).
2) The integrated phase noise due to thermal noise should
be minimized, neglecting any modulator noise.
3) The loop bandwidth must be narrow enough to adequately filter the modulator’s quantization noise.
FracNWizard reports the loop bandwidths resulting from
each of the above constraints. The quantization noise constrained results vary according to the shape of the external
loop filter. FracNWizard reports an optimal bandwidth for
several filter types.
FracNWizard reports the thermal noise optimized loop
bandwidth is 211kHz. Filter 3 (fourth order response) has
a quantization noise constrained BW of 150kHz, making
it a good choice. Select Filter 3 and use the smaller of the
two bandwidths (150kHz) for optimal integrated phase
noise. Use Equation 11 to calculate OSR:
Then, from Equation 4,
NUM = 0.866 • 218 = 227017
14
B
= 14 •
= 13.4µs
fCAL
fPFD
Selecting Filter Type and Loop Bandwidth
fVCO = 3.080GHz to 4.910GHz
O = 2
tCAL ≅
OSR =
50MHz
= 333.3
150kHz
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27
LTC6948
Applications Information
Loop Filter Component Selection
Power Register Programming
Now set loop filter resistor RZ and charge pump current
ICP. Because the KVCO varies over the VCO’s frequency
range, using the KVCO geometric mean gives good results:
For correct PLL operation all internal blocks should be
enabled. OMUTE may remain asserted (or the MUTE pin
held low) until programming is complete. For OMUTE = 1:
Reg02 = h02
K VCO = 3.843 • 109 • 0.047 • 0.07
VCO ALC, AUTOCAL, and AUTORST Programming
= 220.4MHz / V
Using an ICP of 5.6mA, the FracNWizard uses Equation 12
to determine RZ:
2 • π •150k • 76
5.6m • 220.4M
R Z = 58.0Ω
RZ =
Reg03 = h7E
For the 4th order Filter 3, FracNWizard uses modified
Equations 13 and 14 to calculate CI, CP:
4.5
= 82.3nF
2 • π •150k • 58
1
CP =
= 3.5nF
10.5 • π •150k • 58
CI =
R1 = 58.0Ω
Use Table 13 and fPFD = 50MHz to determine V(LDO) and
LDOV[1:0]:
V(LDO) = 2.3V and LDOV[1:0] = 2
C2 = 2.3nF
L1 = 7.8µH
Status Output Programming
This example will use the STAT pin to alert the system
whenever the LTC6948 generates a fault condition. Program x[5], x[4], x[3], x[1], x[0] = 1 to force the STAT pin
high whenever any of the UNLOCK, ALCHI, ALCLO, THI,
or TLO flags asserts:
28
The ALC will only be active during a calibration cycle or
when the loop is unlocked, but the ALCHI and ALCLO
status conditions will be monitored continuously. The VCO
will be calibrated and the Δ∑ modulator will be reset at the
end of the SPI write communication burst (assuming an
auto-increment write is used to write all registers).
LDO Programming
FracNWizard calculates R1, L1, and C2 to be:
Reg01 = h3B
Set the ALC options (ALCMON = ALCULOK = ALCCAL = 1),
the auto reset options (AUTOCAL = AUTORST = 1), and
the Δ∑ modulator modes (DITHEN = 1, INTN = 0) at the
same time:
Use LDOV[1:0], LDOEN = 1 to enable the LDO, and the
previously determined BD[3:0] value to set Reg04. CPLE
should be set to 1 to reduce in-band noise and spurious
due to the Δ∑ modulator:
Reg04 = h5E
SEED Programming
The SEED[7:0] value is used to initialize the Δ∑ modulator
dither circuitry. Use the default value:
Reg05 = h11
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LTC6948
Applications Information
R and N Divider and Numerator Programming
Lock Detect and Charge Pump Current Programming
Program registers Reg06 to Reg0A with the previously
determined R and N divider and numerator values. Because
the AUTORST and AUTOCAL bits were previously set to
1, CAL and RSTFN do not need to be set:
Next, determine the lock indicator window from fPFD. From
Table 3 we see that LKWIN[1:0] = 0 with a tLWW of 5ns for
CPLE = 1 and fVCO = 3.843GHz. The LTC6948 will consider
the loop locked as long as the phase coincidence at the
PFD is within 90°, as calculated below.
Reg06 = h10
phase = 360° • tLWW • fPFD = 360 • 5n • 50M
Reg07 = h4C
Reg08 = h37
Reg09 = h6C
Reg0A = h90
Reference Input Settings and Output Divider
Programming
From Table 1, FILT = 0 for a 100MHz reference frequency.
Next, convert 7dBm into VP–P. For a CW tone, use the
following equation with R = 50:
(dBm – 21)/20
VP-P ≅ R • 10
(15)
This gives VP-P = 1.41V, and, according to Table 2, set
BST = 1.
Now program Reg0B, assuming maximum RF± output
power (RFO[1:0] = 3 according to Table 14) and OD[2:0] = 2:
Reg0B = h9A
= 90°
Choosing the correct COUNTS value depends upon the
OSR. Smaller ratios dictate larger COUNTS values, although
application requirements will vary. A COUNTS value of 32
will work for the OSR of 333. From Table 5, LKCT[1:0] = 1
for 32 counts.
Using Table 6 with the previously selected ICP of 5.6mA
gives CP[3:0] = 7. This gives enough information to program Reg0C:
Reg0C = h0D
Charge Pump Function Programming
This example uses the additional voltage clamp features
to allow the monitoring of fault conditions by setting
CPCHI = 1 and CPCLO = 1. If something occurs and the
system can no longer lock to its intended frequency, the
charge pump output will move toward either GND or
VCP+, thereby setting either the TLO or THI status flags,
respectively. Disable all the other charge pump functions
(CPMID, CPINV, CPRST, CPUP, and CPDN), allowing the
loop to lock:
Reg0D = hC0
The loop should now lock. Now un-mute the output by
setting OMUTE = 0 (assumes the MUTE pin is high).
Reg02 = h04
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29
LTC6948
Applications Information
Reference Source Considerations
A high quality signal must be applied to the REF± inputs as
they provide the frequency reference to the entire PLL. As
mentioned previously, to achieve the part’s in-band phase
noise performance, apply a CW signal of at least 6dBm
into 50Ω, or a square wave of at least 0.5VP-P with slew
rate of at least 40V/µs.
The LTC6948 may be driven single-ended to CMOS levels
(greater than 2.7VP-P ). Apply the reference signal at REF+,
and bypass REF– to GND with a 47pF capacitor. The BST
bit must also be set to 0, according to guidelines given
in Table 2.
The LTC6948 achieves an integer mode in-band normalized
phase noise floor LNORM(INT) = –226dBc/Hz typical, and
a fractional mode phase noise floor LNORM(FRAC) = –225
dBc/Hz typical. To calculate its equivalent input phase
noise floor LIN, use the following Equation 16.
LIN = LNORM + 10 • log10 (fREF) (16)
For example, using a 10MHz reference frequency in integer
mode gives an input phase noise floor of –156dBc/Hz.
The reference frequency source’s phase noise must be at
least 3dB better than this to prevent limiting the overall
system performance.
As can be seen from Equation 17 for a given PFD frequency
fPFD, the output in-band phase noise increases at a 20dBper-decade rate with the N divider count. So, for a given
output frequency fRF, fPFD should be as large as possible
(or N should be as small as possible) while still satisfying
the application’s frequency step size requirements.
Output Phase Noise Due to 1/f Noise
In-band phase noise at very low offset frequencies may
be influenced by the LTC6948’s 1/f noise, depending upon
fPFD. Use the normalized in-band 1/f noise L1/f of –274dBc/
Hz with Equation 18 to approximate the output 1/f phase
noise at a given frequency offset fOFFSET.
LOUT(1/f) (fOFFSET) = L1/f + 20 • log10 (fRF) (18)
– 10 • log10 (fOFFSET)
Unlike the in-band noise floor LOUT, the 1/f noise LOUT(1/f)
does not change with fPFD, and is not constant over offset
frequency. See Figure 14 for an example of integer mode
in-band phase noise for fPFD equal to 3MHz and 100MHz.
The total phase noise will be the summation of LOUT and
LOUT(1/f).
–90
The in-band phase noise floor LOUT produced at fRF may
be calculated by using Equation 17.
LOUT = LNORM + 10 • log10 (fPFD) (17)
+ 20 • log10 (fRF/fPFD)
PHASE NOISE (dBc/Hz)
In-Band Output Phase Noise
–100
TOTAL NOISE
fPFD = 100MHz
–110
–120
1/f NOISE
CONTRIBUTION
or
–130
LOUT ≈ LNORM + 10 • log10 (fPFD)
+ 20 • log10 (N/O)
where LNORM is –226dBc/Hz for integer mode and
–225dBc/Hz for fractional mode. See the Typical Performance Characteristics section for graphs showing LNORM
variation versus ICP and fVCO.
30
TOTAL NOISE
fPFD = 3MHz
10
1k
10k
100
OFFSET FREQUENCY (Hz)
100k
6948 F14
Figure 14. Theoretical Integer Mode In-Band
Phase Noise, fRF = 2500MHz
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LTC6948
Applications Information
The spur will have a relatively constant power in-band,
and be attenuated by the loop out-of-band. An example
integer boundary spur measurement is shown in Figure 15.
–40
IB SPUR LEVEL (dBc)
–50
–60
–70
RF Output Matching
–80
The RF± outputs may be used in either single-ended or differential configurations. Using both RF outputs differentially
will result in approximately 3dB more output power than
single-ended. Impedance matching to an external load in
both cases requires external chokes tied to VRF+. Measured
RF± S-parameters are shown below in Table 17 to aid in
the design of impedance matching networks.
fVCO ≈ 3GHz
–90 fPFD = 50MHz
LOOP BW = 130kHz
–100 CPLE = 1
N = 60
SWEPT NUM
–110
1k
10k
100k
1M
10M
FREQUENCY OFFSET FROM 3GHz (Hz)
6948 F15
Figure 15. Integer Boundary Spur Power vs Frequency
Offset from Boundary, LTC6948-1
Integer Boundary Spurs
Integer boundary spurs are caused by intermodulation
between harmonics of the PFD frequency fPFD and the
VCO frequency fVCO. The coupling between the frequency
source harmonics can occur either on- or off-chip. The
spurs are located at offset frequencies defined by the beat
frequency between the reference harmonics and the VCO
frequency, and are attenuated by the loop filter. The spurs
only occur while in fractional mode.
Integer boundary spurs are most commonly seen when
the fractional value F approaches either zero or one such
that the VCO frequency offset from an integer frequency
is within the loop bandwidth:
fPFD • F ≤ BW
or
fPFD • (1 – F) ≤ BW
Table 17. Single-Ended RF Output Impedance
FREQUENCY (MHz)
IMPEDANCE (Ω)
S11 (dB)
100
133.0 – j16.8
–6.7
500
110.8 – j46.1
–6.8
1000
74.9 – j57.0
–6.9
1500
49.0 – j51.3
–6.7
2000
34.4 – j41.4
–6.5
2500
27.0 – j32.1
–6.5
3000
23.2 – j24.1
–6.6
3500
21.6 – j15.9
–7.1
4000
20.9 – j7.7
–7.5
4500
20.1 – j0.2
–7.4
5000
18.1 + j7.4
–6.4
5500
16.7 + j12.5
–5.6
6000
17.1 + j16.1
–5.5
6500
20.2 + j20.1
–6.2
7000
26.9 + j24.6
–7.6
7500
38.8 + j32.3
–8.8
8000
52.9 + j43.1
–8.2
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31
LTC6948
Applications Information
VRF+
0
68nH, 100pF
180nH, 270pF
–2
RF+(–)
–4
CS
50Ω
RF–(+)
–8
–10
VRF+
LC
–6
S11 (dB)
LC
–12
–14
CS
–16
TO 50Ω
LOAD
0
1
2
3
4
5
FREQUENCY (GHz)
6948 F16
6
7
6947 F17
Figure 16. Single-Ended Output Matching Schematic
Figure 17. RF Single-Ended Return Loss
Single-ended impedance matching is accomplished using
the circuit of Figure 16, with component values found in
Table 18. Using smaller inductances than recommended
can cause phase noise degradation, especially at lower
center frequencies.
(SMT) baluns such as those produced by TDK, Anaren,
and Johanson Technology, can be attractive alternatives.
See Table 19 for recommended balun part numbers versus
frequency range.
Table 18. Suggested Single-Ended Matching Component Values
fRF (MHz)
LC (nH)
CS (pF)
350 to 1500
180
270
1000 to 5800
68
100
Return loss measured on the DC1959 using the above
component values is shown in Figure 17. A broadband
match is achieved using an {LC, CS} of either {68nH, 100pF}
or {180nH, 270pF}. However, for maximum output power
and best phase noise performance, use the recommended
component values of Table 18. LC should be a wirewound
inductor selected for maximum Q factor and SRF, such as
the Coilcraft HP series of chip inductors.
The LTC6948’s differential RF± outputs may be combined
using an external balun to drive a single-ended load. The
advantages are approximately 3dB more output power than
each output individually and better 2nd order harmonic
performance.
For lower frequencies, transmission line (TL) baluns such as
the M/A-COM MABACT0065 and the TOKO #617DB-1673
provide good results. At higher frequencies, surface mount
32
The listed SMT baluns contain internal chokes to bias RF±
and also provide input-to-output DC isolation. The pin
denoted as GND or DC FEED should be connected to the
VRF+ voltage. Figure 18 shows a surface mount balun’s
connections with a DC FEED pin.
Table 19. Suggested Baluns
fRF (MHz)
PART NUMBER
MANUFACTURER
TYPE
350 to 900
#617DB-1673
TOKO
TL
400 to 600
HHM1589B1
TDK
SMT
600 to 1400
BD0810J50200
Anaren
SMT
600 to 3000
MABACT0065
M/A-COM
TL
1000 to 2000
HHM1518A3
TDK
SMT
1400 to 2000
HHM1541E1
TDK
SMT
1900 to 2300
2450BL15B100E
Johanson
SMT
2000 to 2700
HHM1526
TDK
SMT
3700 to 5100
HHM1583B1
TDK
SMT
4000 to 6000
HHM1570B1
TDK
SMT
The listed TL baluns do not provide input-to-output DC
isolation and must be AC-coupled at the output. Figure 19
displays RF± connections using these baluns.
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LTC6948
Applications Information
Supply Bypassing and PCB Layout Guidelines
VRF+
3
RF+ 12
LTC6948
RF–
2
1
TO 50Ω
LOAD
BALUN
11
4
5
6
6948 F18
BALUN PIN CONFIGURATION
1
UNBALANCED PORT
2
GND OR DC FEED
3
BALANCED PORT
4
BALANCED PORT
5
GND
6
NC
Figure 18. Example SMT Balun Connection
VRF+
TO 50Ω
LOAD
RF+ 12
LTC6948
RF–
Care must be taken when creating a PCB layout to minimize power supply decoupling and ground inductances.
All power supply V+ pins should be bypassed directly to
the ground plane using a 0.1µF ceramic capacitor as close
to the pin as possible. Multiple vias to the ground plane
should be used for all ground connections, including to
the power supply decoupling capacitors.
The package’s exposed pad is a ground connection, and
must be soldered directly to the PCB land pattern. The
PCB land pattern should have multiple thermal vias to the
ground plane for both low ground inductance and also low
thermal resistance (see Figure 20 for an example). See
QFN Package Users Guide, page 8, on Linear Technology
website’s Packaging Information page for specific recommendations concerning land patterns and land via solder
masks. A link is provided below.
http://www.linear.com/designtools/packaging
PRI
11
SEC
6948 F19
Figure 19. Example TL Balun Connection
6948 F20
Figure 20. Example Exposed Pad Land Pattern
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33
LTC6948
Applications Information
Reference Signal Routing, Spurious, and
Phase Noise
1) Do not share power supply decoupling capacitors
between same-voltage power supply pins.
The charge pump operates at the PFD’s comparison
frequency fPFD. The resultant output spurious energy is
small and is further reduced by the loop filter before it
modulates the VCO frequency.
2) Use separate ground vias for each power supply
decoupling capacitor, especially those connected to
VREF+, VD+, LDO, VCP+, and VVCO+.
However, improper PCB layout can degrade the LTC6948’s
inherent spurious performance. Care must be taken to
prevent the reference signal fREF from coupling onto the
VCO’s tune line, or into other loop filter signals. Example
suggestions are the following.
34
3) Physically separate the reference frequency signal
from the loop filter and VCO.
4) Do not place a trace between the CMA, CMB, and CMC
pads underneath the package, as worse phase noise
could result.
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LTC6948
Typical Applications
Driving a Modulator LO for High Image Rejection and Low Noise Floor
1.8nF
10µH
66.5Ω
5V
15Ω
0.1µF 3.3V
66.5Ω
2.2nF
1µF
68nF
1µF
0.1µF
3.3V
GND
CP
VCP+
VREF+
VVCO+
VRF+
BB
3.3V
RF+
3.3V
BVCO
GND
CMA
CMB
CMC
GND
TB
TUNE
2.2µF
0.1µF
100pF
100pF
UNUSED OUTPUT
AVAILABLE FOR
OTHER USE
1Ω
4.7µF
LPF
AVAGO
VMMK-2503
50Ω
3.3V
1µF
0.01µF
10nH
68nH 100pF
R = 1, fPFD = 61.44MHz
N = 73.24 TO 84.64
LBW = 180kHz
O=2
5V
3.3V
68nH
0.1µF
3.3V
1nF
BASEBAND
I-CHANNEL
1.3Ω
MINI-CIRCUITS
LFCN-2600+
1nF
GND
GNDRF
BBPI
GND
LOP
VCC2
LOM
GNDRF
GND
RF
LTC5588-1
NC
1nF
6.8pF
RF OUTPUT, 1500MHz TO 2600MHz CARRIER
NC
0.2pF
GNDRF
LINOPT
NC
GND
GNDRF
GND
BBPQ
BBMQ
GND
100nF
GNDRF
fLO = 1500MHz TO 2600MHz IN 117.2Hz STEPS
PLO = 13.5dBm, ~
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