LTC6951
Ultralow Jitter
Multioutput Clock Synthesizer
with Integrated VCO
Description
Features
Low Noise Integer-N PLL with Integrated VCO
nn Output Jitter:
nn 90fs RMS (12kHz to 20MHz)
nn 115fs RMS (ADC SNR Method)
nn Noise Floor = –165dBc/Hz at 250MHz
nn EZSync™, ParallelSync™ Multichip Synchronization
nn SYSREF Generation for JESD204B, Subclass 1
nn Output Frequency Range:
nn 1.95MHz to 2.5GHz (LTC6951)
nn 2.1MHz to 2.7GHz (LTC6951-1)
nn –229dBc/Hz Normalized In-Band Phase Noise Floor
nn –277dBc/Hz Normalized In-Band 1/f Noise
nn Five Independent, Low Noise Outputs
nn Reference Input Frequency up to 425MHz
nn LTC6951Wizard™ Software Design Tool Support
nn –40°C to 105°C Operating Junction Temperature Range
The LTC®6951 is a high performance, low noise, Phase
Locked Loop (PLL) with a fully integrated VCO. The low
noise VCO uses no external components and is internally
calibrated to the correct output frequency with no external
system support.
Applications
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
EZSync, LTC6951Wizard and ParallelSync are trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Protected by U.S. Patents,
including 8319551 and 8819472.
nn
The clock generation section provides five outputs based
on the VCO prescaler signal with individual dividers for
each output. Four outputs feature very low noise, low skew
CML logic. The fifth output is low noise LVDS. All outputs
can be synchronized and set to precise phase alignment
using the programmable delays.
Choose the LTC6951-1 if any desired output frequency
falls in the ranges 2.5GHz to 2.7GHz, 1.66GHz to 1.8GHz,
or 1.25GHz to 1.35GHz. Choose the LTC6951 for all other
frequencies.
High Performance Data Converter Clocking
Wireless Infrastructure
nn Test and Measurement
nn
nn
Typical Application
3.3V
100MHz
REF OSC
1µF
5V
1µF
0.01µF
1µF
REF
REF
50Ω
–
VCP+
R DIVIDER
1µF
LTC6951
CMA
CMB
CMC
TB
BB
BVCO
1µF
470nF
PHASE
FREQUENCY
DETECTOR
OUT0+
D0
DELAY
1.2nF
63.4Ω
82
68nF
80
78
M0
DIV
76
0.1µF
OUT0–
100Ω
TO LTC2107
OUT1+
M1
DIV
OUT1–
0.1µF
D2
DELAY
M2
DIV
D3
DELAY
M3
DIV
D4
DELAY
M4
DIV
OUT2–
TO ADC
OR DAC
OUT3+
SERIAL
PORT
74
72
70
68
66
OUT2+
SYNC
CONTROL
CS
SDI
SNR vs Input Frequency of
LTC6951 Clocking an LTC2107,
fS = 210Msps, AIN = –3dBFS
63.4Ω
CP
820pF
P DIVIDER
STAT
SCLK
VVCO+
1µF
TUNE
D1
DELAY
SYNC
0.01µF
CHARGE
PUMP
N DIVIDER
1µF
TO/FROM
PROCESSOR
0.01µF
V+
+
10Ω
SNR (dBFS)
1µF
NOTE 12
64 LTC2107 APERTURE JITTERRMS = 45fS
LTC6951 JITTERRMS=115fS
62
0 100 200 300 400 500 600 700 800
INPUT FREQUENCY (MHz)
6951 TAO1b
OUT3–
OUT4+
SDO
GND
OUT4–
TO FPGA
6951 TAO1a
6951fa
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1
LTC6951
Absolute Maximum Ratings
Pin Configuration
(Note 1)
VCP+
CP
VREF+
REF –
REF+
STAT
SYNC
TOP VIEW
GND
Supply Voltages
V+ (VREF+, VRF+, VD+, VOUT+) to GND.........................3.6V
VCP+, V VCO+ to GND..................................................5.5V
Voltage on CP Pin..................GND – 0.3V to VCP+ + 0.3V
Voltage on all other Pins............GND – 0.3V to V+ + 0.3V
Current into OUTx+, OUTx–, (x = 0, 1, 2, 3, 4)........±25mA
Operating Junction Temperature Range, TJ (Note 2)
LTC6951I and LTC6951I-1....................... –40 to 105°C
Junction Temperature, TJMAX................................. 125°C
Storage Temperature Range.......................–65 to 150°C
40 39 38 37 36 35 34 33
VOUT+ 1
32 GND
OUT2– 2
31 VVCO+
OUT2+
30 BVCO
3
VOUT+ 4
29 GND
OUT1– 5
28 CMA
OUT1+ 6
27 CMB
41
GND
VOUT+ 7
26 CMC
OUT0– 8
25 GND
OUT0+ 9
24 TB
VOUT+ 10
23 TUNE
OUT3– 11
22 BB
21 VRF+
OUT3+ 12
SDI
SDO
SCLK
CS
VD+
OUT4+
VOUT+
OUT4–
13 14 15 16 17 18 19 20
UHF PACKAGE
40-LEAD (5mm × 7mm) PLASTIC QFN
TJMAX = 125°C, θJCbottom = 2°C/W, θJCtop = 19°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
Order Information
(http://www.linear.com/product/LTC6951#orderinfo)
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC6951IUHF#PBF
LTC6951IUHF#TRPBF
6951
40-Lead (5mm × 7mm) Plastic QFN
–40°C to 105°C
LTC6951IUHF-1#PBF
LTC6951IUHF-1#TRPBF
69511
40-Lead (5mm × 7mm) Plastic QFN
–40°C to 105°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
2
6951fa
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LTC6951
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 2). VREF+ = VD+ = VRF+ = VOUT+ = 3.3V, VCP+ = VVCO+ = 5V unless
otherwise specified. All voltages are with respect to GND.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
425
MHz
2.7
VP-P
Reference Inputs (REF+, REF–)
fREF
Input Frequency
VREF
Input Signal Level
Single-Ended
l
1
l
0.5
Minimum Input Slew Rate
2
20
Input Duty Cycle
V/µs
50
Self-Bias Voltage
l
1.65
350
Input Signal Detected
REFOK = 1, PDREFPK = 0
10MHz ≤ fREF ≤ 425MHz, Sine Wave
l
Input Signal Not Detected
REFOK = 0, PDREFPK = 0
10MHz ≤ fREF ≤ 425MHz, Sine Wave
l
Input Resistance
Differential
l
Input Capacitance
Differential
fVCO
Frequency Range
LTC6951 (Note 3)
LTC6951-1 (Note 3)
KVCO
Tuning Sensitivity
(Notes 3, 4)
2.6
1.85
%
2.25
V
mVP-P
4.2
100
mVP-P
6.1
kΩ
7
pF
VCO
l
l
4.0
4.3
5.0
5.4
2.5 to 3.7
GHz
GHz
%Hz/V
Phase/Frequency Detector (PFD)
fPFD
Input Frequency
l
100
MHz
11.2
mA
Charge Pump (CP)
ICP
Output Current Range
8 Settings (see Table 8)
1.0
Output Current Source/Sink Accuracy
All Settings, V(CP) = 2.3V
±6
%
Output Current Source/Sink Matching
ICP = 1.0mA to 1.4mA, V(CP) = 2.3V
±3.5
%
ICP = 2.0mA to 11.2mA, V(CP) = 2.3V
±2
%
Output Current vs Output Voltage Sensitivity
(Note 5)
l
0.1
Output Current vs Temperature
V(CP) = 2.3V
l
140
ppm/°C
Output Hi-Z Leakage Current
ICP = 1mA (Note 5)
0.5
nA
ICP = 11.2mA (Note 5)
VMID
Mid-Supply Output Bias Ratio
Referred to (VCP+ – GND)
0.5
%/V
5
nA
0.48
V/V
Reference Divider (R)
R
Divide Range
All Integers Included
l
1
63
Counts
All Integers Included, RAO = 0
l
32
1023
Counts
All Integers Included, RAO = 1
l
2
511
Counts
2, 2.5, 3, 3.5, 4 (see Table 14)
l
2
4
Counts
1.55
VCO Divider (N)
N
Divide Range
VCO Prescaler Divider (P)
P
Divide Range
Digital Pin Specifications
VIH
High Level Input Voltage
CS, SDI, SCLK, SYNC
l
VIL
Low Level Input Voltage
CS, SDI, SCLK, SYNC
l
VIHYS
Input Voltage Hysteresis
CS, SDI, SCLK, SYNC
V
0.8
250
Input Current
CS, SDI, SCLK, SYNC
l
IOH
High Level Output Current
SDO and STAT, VOH = VD+ – 400mV
l
IOL
Low Level Output Current
SDO and STAT, VOL = 400mV
l
–3.3
2.0
3.4
V
mV
±1
µA
–1.9
mA
mA
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3
LTC6951
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 2). VREF+ = VD+ = VRF+ = VOUT+ = 3.3V, VCP+ = VVCO+ = 5V unless
otherwise specified. All voltages are with respect to GND.
SYMBOL PARAMETER
CONDITIONS
SDO Hi-Z Current
MIN
TYP
MAX
±1
l
UNITS
µA
Digital Timing Specifications (See Figure 13 and Figure 14)
tCKH
SCLK High Time
l
25
ns
tCKL
SCLK Low Time
l
25
ns
tCSS
CS Setup Time
l
10
ns
tCSH
CS High Time
l
10
ns
tCS
SDI to SCLK Setup Time
l
6
ns
tCH
SDI to SCLK Hold Time
l
6
tDO
SCLK to SDO Time
to VIH /VIL /Hi-Z with 30pF Load
ns
16
l
ns
SYNC Timing Specifications (See Figure 31 and Figure 32)
tSYNCH
SYNC High Time
l
1
ms
tSYNCL
SYNC Low Time
l
1
ms
SYNC Skew
EZSync, Part to Part
tSS
SYNC to REF Setup Time
(See Note 6)
l
1
10
µs
ns
tSH
SYNC to REF Hold Time
(See Note 6)
l
1
ns
Output Dividers (M0, M1, M2, M3 and M4)
Mx
Output Divider Range (x = 0 to 4)
16 Settings (See Table 15)
l
1
512
Counts
Dx
Output Divider Delay (x = 0 to 4)
P Cycles, All Integers Included
l
0
255
Cycles
CML Clock Outputs (OUT0+, OUT0–, OUT1+, OUT1–, OUT2+, OUT2–, OUT3+, OUT3–), Differential Termination = 100Ω Unless Otherwise Noted
fOUT
LTC6951 Output Frequency
l
1.95
2500
MHz
fOUT/2 Subharmonic Generated,
P = 2.5, Mx = 1 (Note 16)
l
1667
2000
MHz
fOUT/2 Subharmonic Generated,
P = 3.5, Mx = 1 (Note 16)
l
1250
1333
MHz
LTC6951-1 Output Frequency
l
2.1
2700
MHz
fOUT/2 Subharmonic Generated,
P = 2.5, Mx = 1 (Note 16)
l
1800
2150
MHz
fOUT/2 Subharmonic Generated,
P = 3.5, Mx = 1 (Note 16)
l
1350
1433
MHz
Output High Voltage
VOUT+ – 0.9
V
Output Low Voltage
VOUT+ – 1.3
V
Output Differential Voltage
Output Resistance
l
350
Differential, No Termination
440
520
mVPK
100
Ω
tR
Output Rise Time, 20% to 80%
50
ps
tF
Output Fall Time, 80% to 20%
50
ps
l
45
fOUTLVDS LTC6951 Output Frequency
LTC6951-1 Output Frequency
l
l
1.95
2.1
VOD
l
300
Output Duty Cycle
P = 2, 3, 4 all Mx, P = 2.5, 3.5 Mx ≥ 2
P = 2.5, Mx = 1
P = 3.5, Mx = 1
50
40
57
55
%
%
%
800
800
MHz
MHz
450
mVPK
LVDS Clock Outputs (OUT4+, OUT4–), Differential Termination = 100Ω
4
Differential Output Voltage
380
6951fa
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LTC6951
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 2). VREF+ = VD+ = VRF+ = VOUT+ = 3.3V, VCP+ = VVCO+ = 5V unless
otherwise specified. All voltages are with respect to GND.
SYMBOL PARAMETER
|∆VOD|
Delta VOD
VOS
Output Offset Voltage
|∆VOS|
Delta VOS
tRLVDS
Output Rise Time, 20% to 80%
tFLVDS
Output Fall Time, 80% to 20%
CONDITIONS
MIN
l
TYP
MAX
5
50
1.23
5
l
Short Circuit Current to Common
Shorted to GND
Short Circuit to Complementary
V
50
M4 ≥ 2
l
45
mV
ps
200
ps
24
3.7
Output Duty Cycle
mV
200
7.4
l
UNITS
mA
mA
50
55
%
Clock Output Skews (OUT0+, OUT0–, OUT1+, OUT1–, OUT2+, OUT2–, OUT3+, OUT3–, OUT4+, OUT4–)
tSKEW1
Maximum Skew, from OUT0 to OUT1
±10
±35
ps
tSKEW2
Maximum Skew, from OUT0 to OUT2
±10
±35
ps
tSKEW3
Maximum Skew, from OUT0 to OUT3
±10
±35
ps
tSKEW4
Maximum Skew, from OUT0 to OUT4
±20
ps
Maximum Skew, All CML Outputs
One Part
±20
±40
ps
Maximum Skew, All CML Outputs
Multiple Parts, RAO = SN = SR = 1
±50
±100
ps
Power Supply Voltages
VREF+ Supply Range
l
3.15
3.3
3.45
V
+ Supply Range
l
3.15
3.3
3.45
V
l
3.15
3.3
3.45
V
l
3.15
3.3
3.45
V
l
4.75
5.0
l
4.2
VOUT
VD
+ Supply Range
VRF+ Supply Range
VVCO
+ Supply Range
VCP+ Supply Range
5.25
V
5.25
V
Power Supply Currents
IDDOUT
ICC–5V
VD+, VOUT+ Supply Current
Digital Inputs at Supply Levels, PDOUT=1
Sum VCP+, VVCO+ Supply Currents
32
l
210
254
mA
ICP = 11.2mA
l
56
70
mA
ICP = 1.0mA
l
33
43
mA
PDALL = 1
ICC–3.3V
Sum VREF+, VRF+ Supply Currents
VD
+, V
510
l
+ Supply Current Deltas
OUT
µA
Digital Inputs at Supply Levels, SYNC = 3.3V
115
µA
130
mA
PDALL = 1
140
µA
MCx[1:0] = 2 (x = 0, 1, 2, or 3)
–31
mA
MCx[1:0] = 3 (x = 0, 1, 2, or 3)
–43
mA
MC4[1:0] = 2
–21
mA
MC4[1:0] = 3
–34
mA
SYNC = VOUT+ or SSYNC = 1
11
mA
10kHz Offset
–87
dBc/Hz
100kHz Offset
–113
dBc/Hz
1MHz Offset
–135
dBc/Hz
Phase Noise and Spurious
LVCO
LTC6951 VCO Phase Noise
(fVCO = 4.0GHz, fOUT0 = 2.0GHz, P = 2, M0 = 1,
Note 7)
6951fa
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5
LTC6951
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 2). VREF+ = VD+ = VRF+ = VOUT+ = 3.3V, VCP+ = VVCO+ = 5V unless
otherwise specified. All voltages are with respect to GND.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
LTC6951 VCO Phase Noise
(fVCO = 5.0GHz, fOUT0 = 2.5GHz, P = 2, M0 = 1,
Note 7)
10kHz Offset
–83
dBc/Hz
100kHz Offset
–110
dBc/Hz
1MHz Offset
–133
dBc/Hz
LTC6951-1 VCO Phase Noise
(fVCO = 5.4GHz, fOUT0 = 2.7GHz, P = 2, M0 = 1,
Note 7)
10kHz Offset
–83
dBc/Hz
100kHz Offset
–110
dBc/Hz
1MHz Offset
–133
dBc/Hz
LTC6951-1 CML Output Noise/Jitter
(fVCO = 5.4GHz, fOUT0 = fOUT1 = fOUT2 = fOUT3 =
2.7GHz, P = 2, M0 = M1 = M2 = M3 = 1,
Notes 9, 12)
Phase Noise 10kHz Offset
–119
dBc/Hz
Phase Noise 1MHz Offset
–129
dBc/Hz
Phase Noise 40MHz Offset
–153
dBc/Hz
LTC6951 CML Output Noise/Jitter
(fVCO = 5.0GHz, fOUT0 = fOUT1 = fOUT2 = fOUT3 =
2.5GHz, P = 2, M0 = M1 = M2 = M3 = 1,
Notes 9, 12)
Jitter, 12kHz to 20MHz Integration BW
90
fsRMS
Jitter, 100Hz to fOUTx Integration BW
115
fsRMS
Phase Noise 10kHz Offset
–119
dBc/Hz
Phase Noise 1MHz Offset
–129
dBc/Hz
Phase Noise 40MHz Offset
–153
dBc/Hz
90
fsRMS
Jitter, 12kHz to 20MHz Integration BW
LTC6951 CML Output Noise/Jitter
(fVCO = 5.0GHz, fOUT0 = fOUT1 = fOUT2 = fOUT3 =
1.25GHz, P = 2, M0 = M1 = M2 = M3 = 2,
Notes 9, 12)
Jitter, 100Hz to fOUTx Integration BW
115
fsRMS
10kHz Offset
–125
dBc/Hz
1MHz Offset
–135
dBc/Hz
40MHz Offset
–156
dBc/Hz
88
fsRMS
Jitter, 12kHz to 20MHz Integration BW
LTC6951 CML Output Noise/Jitter
(fVCO = 4.0GHz, fOUT0 = fOUT1 = fOUT2 = fOUT3 =
250MHz, P = 4, M0 = M1 = M2 = M3 = 4,
Notes 9, 12)
Jitter, 100Hz to fOUTx Integration BW
115
fsRMS
10kHz Offset
–140
dBc/Hz
1MHz Offset
–150
dBc/Hz
40MHz Offset
–165
dBc/Hz
83
fsRMS
Jitter, 12kHz to 20MHz Integration BW
Jitter, 100Hz to fOUTx Integration BW
LTC6951 LVDS Output Noise/Jitter
10kHz Offset
(fVCO = 4.0GHz, fOUT4 = 250MHz, P = 4, M4 = 4, 1MHz Offset
Notes 9, 12)
40MHz Offset
Jitter, 12kHz to 20MHz Integration BW
115
fsRMS
–140
dBc/Hz
–150
dBc/Hz
–162
dBc/Hz
88
fsRMS
Jitter, 100Hz to fOUTx Integration BW
140
fsRMS
LNORM
Normalized In-Band Phase Noise Floor
ICP = 11.2mA (Notes 8, 9, 10)
–229
dBc/Hz
L1/f
Normalized In-Band 1/f Phase Noise
ICP = 11.2mA (Notes 8, 11)
–277
dBc/Hz
6
In-Band Phase Noise Floor
(Notes 8, 9, 10, 13)
–134
dBc/Hz
Integrated Phase Noise from 100Hz to 40MHz
(Notes 9, 13)
0.015
°RMS
Spurious
fOFFSET = fPFD, PLL Locked (Notes 9, 13, 14, 15)
–95
dBc
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LTC6951
Electrical Characteristics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC6951IUHF and LTC6951IUHF-1 are guaranteed to meet
specified performance limits over the full operating junction temperature
range of –40°C to 105°C. Under maximum operating conditions, air flow
or heat sinking may be required to maintain a junction temperature of
105°C or lower. It is strongly recommended that the Exposed Pad (Pin 41)
be soldered directly to the ground plane with an array of thermal vias as
described in the Applications Information section.
Note 3: Valid for 1.50V ≤ V(TUNE) ≤ 2.85V with part calibrated after a
power cycle or software power-on-reset (POR).
Note 4: Based on characterization.
Note 5: For 1.4V < V(CP) < 3.0V.
Note 6: Measurement requires RAO = 1 with SR = 1 at SYNC rising edge
and SN = 1 at SYNC falling edge. REF+ is a CMOS level signal with a 1ns
rise time and the measurement point at the 50% crossing. SYNC is a
CMOS level signal with a 1ns rise and fall time. For SYNC rising and SR
= 1, the measurement point is 1.55V. For SYNC falling and SN = 1, the
measurement point is 0.8V.
Note 7: Measured outside the loop bandwidth, using a narrowband loop.
Note 8: Measured inside the loop bandwidth with the loop locked.
Note 9: Reference frequency supplied by Wenzel 501-04516,
fREF = 100MHz, PREF = 10dBm.
Note 10: Output Phase Noise Floor is calculated from Normalized Phase
Noise Floor by LOUT = LNORM + 10log10(fPFD) + 20log10(fOUTx /fPFD).
Note 11: Output 1/f Noise is calculated from Normalized 1/f Phase Noise
by LOUT(1/f) = L1/f + 20log10(fOUTx) – 10log10(fOFFSET).
Note 12: ICP = 11.2mA, fPFD = 100MHz, FILT = 0, Loop BW = 340kHz
Note 13: ICP = 11.2mA, fPFD = 100MHz, FILT = 0, Loop BW = 340kHz;
fOUT0 = 500MHz, fVCO = 4.0GHz.
Note 14: Measured using DC2248A.
Note 15: Measured using differential LTC6951 outputs driving LTC6954.
LTC6954 provides differential to single-ended conversion for rejection of
common mode spurious signals. See the Applications Information section
for details.
Note 16: When P = 2.5 or 3.5 and Mx = 1, a subharmonic of approximately
–45dBc to –25dBc is generated at the output at fOUT/2. While most
applications are not affected by this spur, some, such as ADC and DAC
sampling, are degraded. For applications sensitive to subharmonic spurs,
these settings are not recommended unless the output frequency is further
divided by at least 2 (i.e. ADC clock divider).
Note 17: Each output can be individually powered down by setting the
output’s MCx[1:0] bits to 3. See Tables 16 and 17.
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7
LTC6951
Typical
Performance Characteristics
+
+
TA = 25°C. VREF+ = VOUT+ = VD+ = VRF+ = 3.3V,
VCP = VVCO = 5V, Unless otherwise noted.
REF Input Sensitivity vs
Frequency
Charge Pump Hi-Z Current vs
Voltage, Temperature
REF Input Signal Detected vs
Frequency, Temperature
–25
250
5
4
–30
225
–40
–45
–50
–55
BST = 1
FILT = 0
–60
–65
105°C
25°C
–40°C
NOTE 14
0
50 100 150 200 250 300 350 400 450 500
FREQUENCY (MHz)
3
2
CURRENT (nA)
SENSITIVITY (mVP-P)
SENSITIVITY (dBm)
–35
200
175
BST = 1
FILT = 0
150
125
4
4
3
3
2
2
1
1
ERROR (%)
ERROR (%)
5
0
–1
–2
–5
–5
1
1.5 2 2.5 3 3.5
OUTPUT VOLTAGE (V)
0.5
1
1.5 2 2.5 3 3.5
OUTPUT VOLTAGE (V)
4
4.5
–5
5
105°C
25°C
–40°C
0
0.5
1
1.5 2 2.5 3 3.5
OUTPUT VOLTAGE (V)
4
4.5
5
1
1
0
–1
0
–1
–2
–2
–3
–3
–4
–4
0.5
1
1.5 2 2.5 3 3.5
OUTPUT VOLTAGE (V)
4
4.5
105°C
25°C
–40°C
3
2
0
ICP = 11.2mA
4
ERROR (%)
ERROR (%)
Charge Pump Source Current
Error vs Voltage, Temperature
2
–5
5
–5
0
0.5
6951 G06
8
5
6951 G05
1mA
5.6mA
11.2mA
3
5
ICP = 11.2mA
–4
Charge Pump Source Current
Error vs Voltage, Output Current
4
4.5
0
6951 G04
5
4
–1
–3
1mA
5.6mA
11.2mA
0.5
0
6951 G03
–2
0
105°C
25°C
–40°C
–4
Charge Pump Sink Current Error
vs Temperature
5
–4
ICP = 11.2mA
CPRST=1
6951 G02
Charge Pump Sink Current Error
vs Voltage, Output Current
–3
–1
–3
50 100 150 200 250 300 350 400 450 500
FREQUENCY (MHz)
6951 G01
0
–2
105°C
25°C
–40°C
0
1
1
1.5 2 2.5 3 3.5
OUTPUT VOLTAGE (V)
4
4.5
5
6951 G07
6951fa
For more information www.linear.com/LTC6951
LTC6951
Typical
Performance Characteristics
+
+
VCP = VVCO = 5V, Unless otherwise noted.
LTC6951-1 CML Differential Output
at 2.7GHz
0.5
0.4
0.4
0.3
0.3
0.3
0.2
0.1
0.0
–0.1
–0.2
–0.3
0.2
0.1
0.0
–0.1
–0.2
–0.3
–0.4
NOTE 14
–0.5
–0.5
6951 G08
100ps/DIV
DIFFERENTIAL OUTPUT (V)
0.5
0.4
–0.4
CML Differential Output Swing vs
Frequency, Temperature
0.2
0.1
0.0
–0.1
–0.2
–0.3
–0.4
NOTE 14
–0.5
6951 G09
100ps/DIV
0.95
0.4
0.4
0.3
0.3
0.85
0.80
0.75
0.70
105°C
25°C
–40°C
0.65
NOTE 14
0
0.5
1
1.5
2
OUTPUT FREQUENCY (GHz)
2.5
0.2
0.1
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
6951 G10
0.1
0.0
–0.1
–0.2
–0.3
–0.5
6951 G12
500ps/DIV
200ps/DIV
0.2
–0.4
NOTE 14
NOTE 14
1ns/DIV
6951 G13
6951 G11
LVDS Differential Output Swing vs
Frequency, Temperature
1.00
NOTE 14
Frequency Step Transient,
RAO = 0
675
105°C
25°C
–40°C
0.95
650
0.90
0.85
0.80
0.75
600
575
525
0.65
500
0
0.2
0.4
0.6
OUTPUT FREQUENCY (GHz)
0.8
LOOP FILTER
SETTLING
TIME
550
0.70
0.60
CALIBRATION TIME
625
FREQUENCY (MHz)
0.60
DIFFERENTIAL OUTPUT (V)
0.5
DIFFERENTIAL OUTPUT (V)
0.5
0.90
NOTE 14
LVDS Differential Output at 250MHz
LVDS Differential Output at 800MHz
1.00
DIFFERENTIAL OUTPUT SWING (VP–P)
DIFFERENTIAL OUTPUT SWING (VP-P)
LTC6951 CML Differential Output
at 1.25GHz
0.5
DIFFERENTIAL OUTPUT (V)
DIFFERENTIAL OUTPUT (V)
LTC6951 CML Differential Output
at 2.5GHz
TA = 25°C. VREF+ = VOUT+ = VD+ = VRF+ = 3.3V,
475
100MHz STEP
fPFD = 100MHz
fCAL = 260.4kHz
BW = 340kHz
MCx = 0
0
6951 G14
10
20
30
40
TIME (µs)
50
60
70
6951 G15
6951fa
For more information www.linear.com/LTC6951
9
LTC6951
Typical
Performance Characteristics
+
+
VCP = VVCO = 5V, Unless otherwise noted.
Max Calibration Time (RAO = 0)
vs fPD, B Divide Value
BD = 24
BD = 32
BD = 48
BD = 64
BD = 96
75
BD = 128
BD = 192
BD = 256
BD = 384
KVCO (%Hz/V)
CALIBRATION TIME (µs)
85
65
55
45
35
4.0
4.0
3.5
3.5
3.0
3.0
2.5
2.0
1.5
REFER TO EQUATION 1 AND TABLE 10
1
10
PFD FREQUENCY (MHz)
1.0
3.9
100
4.2
4.5
4.8
VCO FREQUENCY (GHz)
–50
–70
–227
–228
–229
7
ICP (mA)
–90
–100
–110
–120
–130
11
–90
–100
–110
–120
–130
–150
1k
10k
100k
1M
OFFSET FREQUENCY (Hz)
LTC6951 Phase Noise at CML
Outputs, fVCO = 4GHz, P = 2, Mx = 4,
8 and 16
LTC6951 Phase Noise at CML
Outputs, fVCO = 5GHz, P = 2, Mx = 1,
2 and 4
–100
–160
10M 40M
–100
–120
–120
–120
–150
–160
fOUT = 500MHz
fOUT = 250MHz
fOUT = 125MHz
–170
100
1k
10k
100k
1M
OFFSET FREQUENCY (Hz)
10M 40M
6951 G22
10
PHASE NOISE (dBc/Hz)
–110
PHASE NOISE (dBc/Hz)
–110
–140
–140
–150
–160
fOUT = 2.5GHz
fOUT = 1.25GHz
fOUT = 625MHz
–170
100
1k
10k
100k
1M
OFFSET FREQUENCY (Hz)
10M 40M
6951 G23
10k
100k
1M
OFFSET FREQUENCY (Hz)
10M 40M
LTC6951-1 Phase Noise at CML
Outputs, fVCO = 4.3GHz, P = 2,
Mx = 4, 8 and 16
NOTES 9, 12
–130
1k
6951 G21
–110
–130
NOTE 7
–80
–140
6951 G20
NOTES 9, 12
–70
–150
–160
fVCO = 4.3GHz, fOUT = 2.15GHz
fVCO = 5.4GHz, fOUT = 2.7GHz
–60
–140
6951 G19
–100
PHASE NOISE (dBc/Hz)
9
–50
NOTE 7
–80
5.4
LTC6951-1 VCO Phase Noise at
CML Outputs, P = 2, Mx = 1
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
PHASE NOISE FLOOR (dBc/Hz)
–225
–226
4.5
4.8
5.1
VCO FREQUENCY (GHz)
6951 G18
fVCO = 4GHz, fOUT = 2GHz
fVCO = 5GHz, fOUT = 2.5GHz
–60
5
1.0
4.2
5.1
LTC6951 VCO Phase Noise at
CML Outputs, P = 2, Mx = 1
–224
3
2.0
6951 G17
Normalized In-Band Phase Noise
Floor vs CP Current
1
2.5
1.5
6951 G16
–230
LTC6951–1 VCO Tuning
Sensitivity
LTC6951 VCO Tuning Sensitivity
KVCO (%Hz/V)
95
TA = 25°C. VREF+ = VOUT+ = VD+ = VRF+ = 3.3V,
NOTES 9, 12
–130
–140
–150
–160
fOUT = 537.5MHz
fOUT = 268.75MHz
fOUT = 134.375MHz
–170
100
1k
10k
100k
1M
OFFSET FREQUENCY (Hz)
10M 40M
6951 G24
6951fa
For more information www.linear.com/LTC6951
LTC6951
Typical
Performance Characteristics
+
+
VCP = VVCO = 5V, Unless otherwise noted.
LTC6951-1 Phase Noise at CML
Outputs, fVCO = 5.4GHz, P = 2, Mx = 1,
2 and 4
Spurious Response
fRF = 1250MHz, fREF = 100MHz,
fPFD = 100MHz, Loop BW = 340kHz
0
–120
POUT (dBc)
PHASE NOISE (dBc/Hz)
–110
–140
–150
–160
fOUT = 2.7GHz
fOUT = 1.35GHz
fOUT = 675MHz
–170
100
1k
10k
100k
1M
OFFSET FREQUENCY (Hz)
–20
–40
–40
–60
–60
–80
–100
–140
–140
6951 G25
350
VBW = 1Hz
–20 RBW = 1Hz
NOTES 14, 15
3.3V CURRENT (mA)
–120
45
340
66
330
64
320
62
3.3V
5V
300
–40
–20
6951 G28
0
20
40
TJ (°C)
60
80
21
25
20
15
10
OUT4
OUT0 (RAO=1)
OUT0 (RAO=0), OUT1, 2, or 3
5
0
58
0
1
2
3
6951 G30
Part to Part Skew,CML Outputs,
fOUT = 1GHz
N = 120
18
NOTE 17
225
175
125
75
100
30
6951 G29
LVDS on
LVDS off
275
35
MCx VALUE
3.3V Supply Current vs
Number of Enabled CML Outputs
325
40
60
310
–40 –30 –20 –10 0 10 20 30 40
FREQUENCY OFFSET (MHz in 10kHz SEGMENTS)
50
68
NUMBER OF PARTS
–160
VOUT+ Supply Current per Output
vs MCx Value
ICP = 11.2mA
–140
CURRENT (mA)
POUT (dBc)
–100
6951 G27
5V CURRENT (mA)
–80
–400 –300 –200 –100 0 100 200 300 400
FREQUENCY OFFSET (MHz in 10kHz SEGMENTS)
Supply Current vs Temperature
RAO = 0, All Outputs Enabled
0
–60
–160
6951 G26
Spurious Response
fRF = 500MHz, fREF = 100MHz,
fPFD = 10MHz, Loop BW = 290kHz
–40
–100
–120
–400 –300 –200 –100 0 100 200 300 400
FREQUENCY OFFSET (MHz in 10kHz SEGMENTS)
VBW = 1Hz
RBW = 1Hz
NOTES 14, 15
–80
–120
–160
10M 40M
0
VBW = 1Hz
–20 RBW = 1Hz
NOTES 14, 15
POUT (dBc)
NOTES 9, 12
–130
Spurious Response
fRF = 500MHz, fREF = 100MHz,
fPFD = 100MHz, Loop BW = 340kHz
CURRENT (mA)
–100
TA = 25°C. VREF+ = VOUT+ = VD+ = VRF+ = 3.3V,
15
12
9
6
3
0
1
2
3
NUMBER OF ENABLED CML OUTPUTS
4
0
–45
6951 G31
–30
–15
0
15
SKEW (ps)
30
45
6951 G32
6951fa
For more information www.linear.com/LTC6951
11
LTC6951
Pin Functions
VOUT+, VD+ (Pins 1, 4, 7, 10, 13, 16): 3.15V to 3.45V
Positive Supply Pins for Output Dividers, SYNC Function
and Serial Port. Each pin should be separately bypassed
directly to the ground plane using a 0.01µF ceramic capacitor as close to the pin as possible. VOUT+, VD+, VRF+,
and VREF+ must all be at the same voltage.
OUT4–, OUT4+ (Pins 14, 15): LVDS Output Signals. The
M4 output divider is buffered and presented differentially
on these pins. The far end of the transmission line is typically terminated with 100Ω connected across the outputs.
See the Operation and Applications Information section
for more details.
OUT2–, OUT2+ (Pins 2, 3): 2.5V CML Output Signals.
The M2 output divider is buffered and presented differentially on these pins. The outputs are connected with
50Ω (typical) pull-up resistors tied to an internal resistive
common mode point. The far end of the transmission line
is typically terminated with 100Ω connected across the
outputs. See the Operation and Applications Information
section for more details.
CS (Pin 17): Serial Port Chip Select. This CMOS input
initiates a serial port communication burst when driven
low, ending the burst when driven back high. See the
Operation section for more details.
OUT1–, OUT1+ (Pins 5, 6): 2.5V CML Output Signals.
The M1 output divider is buffered and presented differentially on these pins. The outputs are connected with
50Ω (typical) pull-up resistors tied to an internal resistive
common mode point. The far end of the transmission line
is typically terminated with 100Ω connected across the
outputs. See the Operation and Applications Information
section for more details.
SCLK (Pin 18): Serial Port Clock. This CMOS input clocks
serial port input data on its rising edge. See the Operation
section for more details.
SDI (Pin 19): Serial Port Data Input. The serial port uses
this CMOS input for data. See the Operation section for
more details.
SDO (Pin 20): Serial Port Data Output. This CMOS threestate output presents data from the serial port during a
read communication burst. Optionally attach a resistor
of > 200kΩ to GND to prevent a floating output. See the
Applications Information section for more details.
OUT0–, OUT0+ (Pins 8, 9): 2.5V CML Output Signals.
The M0 output divider is buffered and presented differentially on these pins. The outputs are connected with
50Ω (typical) pull-up resistors tied to an internal resistive
common mode point. The far end of the transmission line
is typically terminated with 100Ω connected across the
outputs. See the Operation and Applications Information
section for more details.
VRF+ (Pin 21): 3.15V to 3.45V Positive Supply Pin for
RF Circuitry. This pin should be bypassed directly to the
ground plane using a 0.01µF ceramic capacitor as close
to the pin as possible. VOUT+, VD+, VRF+, and VREF+ must
all be at the same voltage.
OUT3–, OUT3+ (Pins 11, 12): 2.5V CML Output Signals.
The M3 output divider is buffered and presented differentially on these pins. The outputs are connected with
50Ω (typical) pull-up resistors tied to an internal resistive
common mode point. The far end of the transmission line
is typically terminated with 100Ω connected across the
outputs. See the Operation and Applications Information
section for more details.
TUNE (Pin 23): VCO Tuning Input. This frequency control
pin is normally connected to the external loop filter. See
the Applications Information section for more details.
12
BB (Pin 22): RF Reference Bypass. This output has a 6.5k
resistance and must be bypassed with a 0.47µF ceramic
capacitor to GND. Do not couple this pin to any other signal.
TB (Pin 24): VCO Bypass. This output has a 7k resistance
and must be bypassed with a 1.0µF ceramic capacitor to
GND. It is normally connected to CMA, CMB, and CMC with
a short trace. Do not couple this pin to any other signal.
6951fa
For more information www.linear.com/LTC6951
LTC6951
Pin Functions
GND (Pins 25, 29, Exposed Pad Pin 41): Negative Power
Supply (Ground). These pins should be tied directly to the
ground plane with multiple vias for each pin. The package
exposed pad must be soldered directly to the PCB land.
The PCB land pattern should have multiple thermal vias
to the ground plane for both low ground inductance and
also low thermal resistance.
CMC, CMB, CMA (Pins 26, 27, 28): VCO Bias Inputs. These
inputs are normally connected to TB with a short trace
and bypassed with a 1µF ceramic capacitor to GND. Do
not couple these pins to any other signal. For best phase
noise performance, DO NOT place a trace between these
pads underneath the package.
BVCO (Pin 30): VCO Bypass Pin. This output must be
bypassed with a 1.0µF ceramic capacitor to GND. Do not
couple this pin to any other signal.
VVCO+ (Pin 31): 4.75V to 5.25V Positive Supply Pin for
VCO Circuitry. This pin should be bypassed directly to the
ground plane using a 0.01µF ceramic capacitor as close
to the pin as possible.
GND (Pins 32, 40): Negative Power Supply (Ground).
These pins are attached directly to the Die Attach Paddle
(DAP) and should be tied directly to the ground plane.
VCP+ (Pin 33): 4.2V to 5.25V Positive Supply Pin for Charge
Pump Circuitry. This pin should be bypassed directly to
the ground plane using two ceramic capacitors of 1µF
and 0.01µF as close to the pin as possible. Additionally, a
10Ω resistor should be added in series with the 5V power
supply to reduce switching noise. The resistor should be
placed between the 5V supply rail and the two ceramic
capacitors.
CP (Pin 34): Charge Pump Output. This bidirectional current
output is normally connected to the external loop filter.
See the Applications Information section for more details.
VREF+ (Pin 35): 3.15V to 3.45V Positive Supply Pin for
Reference Input Circuitry. This pin should be bypassed
directly to the ground plane using a 0.1µF ceramic capacitor as close to the pin as possible. VOUT+, VD+, VRF+, and
VREF+ must all be at the same voltage.
REF–, REF+ (Pins 36, 37): Reference Input Signals. This
differential input is buffered with a low noise amplifier,
which feeds the reference divider. They are self-biased
and must be AC-coupled with 1µF capacitors. If used
single-ended with V(REF+) ≤ 2.7VP-P, bypass REF– to GND
with a 1µF capacitor. If used single-ended with V(REF+)
> 2.7VP-P, bypass REF– to GND with a 47pF capacitor.
STAT (Pin 38): Status Output. This signal is a configurable
logical OR combination of the UNLOCK, ALCHI, ALCLO,
LOCK, LOCK, REFOK, and REFOK status bits, programmable via the STATUS register. See the Operation section
for more details.
SYNC (Pin 39): Synchronization Input. This CMOS input
stops the output dividers when driven high and initiates
synchronization when driven back low when enabled for
each output. When using the SSYNC software synchronization bit, the SYNC pin must be held at a logic low state.
See the Operation and Applications Information section
for more details.
6951fa
For more information www.linear.com/LTC6951
13
LTC6951
Block Diagram
35
VREF+
37
36
21
40
32
VRF+
GND
GND
REF+
≤425MHz
REF –
33
31
VCP+
VVCO+
1mA TO
11.2mA
PFD
≤100MHz
R DIV
CP
34
÷1 TO 63
LOCK
PEAK
DETECTOR
B DIV
30 BVC0
N DIV
29 GND
÷2 TO 1023
28 CMA
P DIV
27 CMB
÷2, 2.5, 3, 3.5, 4
CAL, ALC
CONTROL
0
1
RAO
TUNE
LTC6951: 4GHz TO 5GHz
LTC6951-1: 4.3GHz TO 5.4GHz
VOUT+
26 CMC
25 GND
OUT0–
24 TB
D0 DELAY
SYNC
CML
0 TO 255
22 BB
39
M0 DIV
SYNC
CONTROL
OUT0+
23
7
8
9
+
VOUT
4
OUT1–
D1 DELAY
M1 DIV
CML
0 TO 255
OUT1+
5
6
+
38
17
18
19
20
16
VOUT
STAT
CS
D2 DELAY
SCLK
1
OUT2–
SERIAL
PORT
M2 DIV
CML
0 TO 255
OUT2+
3
+
SDI
VOUT
SDO
OUT3–
VD+
2
D3 DELAY
M3 DIV
CML
0 TO 255
OUT3+
VOUT+
41 EXPOSED PAD
OUT4–
D4 DELAY
M4 DIV
LVDS
0 TO 255
OUT4+
10
11
12
13
14
15
6951 BD
14
6951fa
For more information www.linear.com/LTC6951
LTC6951
Timing Diagrams
Output Skews
Differential CML Rise/Fall Times
OUT0–
OUT0+
OUT1–
OUT1+
OUT2–
80%
20%
tSKEW1
tR
6951 TD02
tSKEW2
Differential LVDS Rise/Fall Times
OUT2+
OUT3–
tSKEW3
80%
OUT3+
OUT4–
tF
20%
tSKEW4
tRLVDS
tFLVDS
6951 TD03
OUT4+
6951 TD01
Operation
The LTC6951 is a high-performance integer-N PLL, complete with a low noise VCO. Its multi-output clock generator
incorporates Linear Technology’s proprietary EZSync and
ParallelSync standards, allowing synchronization across
multiple outputs and multiple chips. The device is able
to achieve superior integrated jitter performance by the
combination of its extremely low in-band phase noise and
excellent VCO noise characteristics.
VREF+
VREF+
BIAS
LOWPASS
1.9V
REF+
2.1k
2.1k
FILT
REF –
6951 F01
BST
Reference Input Buffer
The PLL’s reference frequency is applied differentially on
pins REF+ and REF–. These high-impedance inputs are
self-biased and must be AC-coupled with 1µF capacitors
(see Figure 1 for a simplified schematic). Alternatively, the
inputs may be used single-ended by applying the reference frequency at REF+ and bypassing REF– to GND with
a 1µF capacitor. If the single-ended signal is greater than
2.7VP–P, then use a 47pF capacitor for the GND bypass.
A high quality signal must be applied to the REF± inputs
as they provide the frequency reference to the entire PLL.
To achieve the part’s in-band phase noise performance,
apply a sine wave signal of at least 6dBm into 50Ω, or a
Figure 1. Simplified REF Interface Schematic
square wave of at least 0.5VP-P with slew rate of at least
20V/µs. Figure 2 shows recommended interfaces for different reference types.
Additional options are available through serial port register
h03 to further refine the application. Bit FILT controls the
reference input buffer’s low-pass filter, and should be set
for sine wave signals based upon fREF to limit the reference’s wideband noise. The FILT bit must be set correctly
to reach the LNORM normalized in-band phase noise floor.
See Table 1 for recommended settings. Square wave inputs
will have FILT set to “0”.
6951fa
For more information www.linear.com/LTC6951
15
LTC6951
Operation
50Ω
150Ω
LVPECL
LVPECL OR
50Ω SOURCE
ZO
50Ω
REF+
50Ω
150Ω
REF+
ZO
100Ω
REF–
ZO
LTC6951
DIFFERENTIAL LVPECL
REF–
REF+
ZO
SINGLE-ENDED LVPECL OR 50Ω SOURCE
CML
100Ω
ZO
RSER
CMOS
ZO
LTC6951
REF–
DIFFERENTIAL CML
REF+
50Ω
VCMOS RSER
3.3V 200Ω
1.8V
82Ω
LTC6951
LTC6951
ZO
REF–
LVDS
100Ω
ZO
SINGLE-ENDED CMOS
REF+
LTC6951
REF–
6951 F02
DIFFERENTIAL LVDS
Figure 2. Common Reference Input Interface Configurations. All ZO Signal Traces Are 50Ω Transmission Lines and All Caps Are 1μF
Peak Detector
Table 1. FILT Programming
FILT
Sine Wave fREF
Square Wave fREF
1
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