LTC6952
Ultralow Jitter, 4.5GHz PLL
with 11 Outputs and JESD204B/JESD204C Support
FEATURES
DESCRIPTION
JESD204B/C, Subclass 1 SYSREF Signal Generation
nn Low Noise Integer-N PLL
nn Additive Output Jitter < 6fs
RMS
(Integration BW = 12kHz to 20MHz, f = 4.5GHz)
nn Additive Output Jitter 65fs
RMS (ADC SNR Method)
nn EZSync™, ParallelSync™ Multichip Synchronization
nn –229dBc/Hz Normalized In-Band Phase Noise Floor
nn –281dBc/Hz Normalized In-Band 1/f Noise
nn Eleven Independent, Low Noise Outputs with
Programmable Coarse Digital and Fine Analog Delays
nn Flexible Outputs Can Serve as Either a Device Clock
or SYSREF Signal
nn Reference Input Frequency up to 500MHz
nn LTC6952Wizard™ Software Design Tool Support
nn –40ºC to 125°C Operating Junction Temperature Range
The LTC®6952 is a high performance, ultralow jitter,
JESD204B/C clock generation and distribution IC. It
includes a Phase Locked Loop (PLL) core, consisting of
a reference divider, phase-frequency detector (PFD) with
a phase-lock indicator, ultralow noise charge pump and
integer feedback divider. The LTC6952’s eleven outputs
can be configured as up to five JESD204B/C subclass
1 device clock/SYSREF pairs plus one general purpose
output, or simply eleven general purpose clock outputs for
non-JESD204B/C applications. Each output has its own
individually programmable frequency divider and output
driver. All outputs can also be synchronized and set to
precise phase alignment using individual coarse half-cycle
digital delays and fine analog time delays.
nn
For applications requiring more than eleven total outputs,
multiple LTC6952s can be connected together using the
EZSync or ParallelSync synchronization protocols.
APPLICATIONS
High Performance Data Converter Clocking
Wireless Infrastructure
nn Test and Measurement
nn
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. Patents, including 8319551 and 8819472.
nn
TYPICAL APPLICATION
3.3V
5V
48.7Ω
VCP+
0.47µF
LTC6952
Crystek
CVCO55CC4000-4000
0.1µF
VCO–
OUT9± 12.5MHz DAC SYSREF
OUT10± 4GHz DAC CLOCK
1µF
100Ω
Pascal OCXO-E
100MHz Ref Osc
VCO+
OUT7± 12.5MHz DAC SYSREF
OUT8± 4GHz DAC CLOCK
75Ω
Vtune
1µF
OUT4± 12.5MHz FPGA SYSREF
OUT5± 125MHz FPGA CLOCK
OUT6± 100MHz FPGA MGMT CLOCK
30Ω
1µF
REF –
EZS_SRQ+
TO SYNC OUTPUTS:
TOGGLE SSYNC REGISTER BIT
EZS_SRQ –
–120
–130
–140
–150
–160
–170
0.1µF
REF+
49.9Ω
RMS JITTER = 65fs
EQUIVALENT ADC SNR METHOD
NOTES 10, 13
–110
OUT2± 12.5MHz ADC SYSREF
OUT3± 500MHz ADC CLOCK
22nF
0.1µF
–100
OUT0± 12.5MHz ADC SYSREF
OUT1± 500MHz ADC CLOCK
CP
48.7Ω
1.2µF
LTC6952 Phase Noise
PHASE NOISE (dBc/Hz)
LTC6952Wizard REGISTER VALUES:
FILE: LTC6952 EZSync STANDALONE
33nF
3.3V
VVCO+ VREF+ VD+ VOUT+
OUTx+
4GHz
500MHz
1k
10k
100k
1M
OFFSET FREQUENCY (Hz)
10M 40M
6952 TA01b
100Ω
OUTx–
0.1µF
OUTPUT TERMINATION DETAIL
6952 TA01a
Rev 0
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1
LTC6952
TABLE OF CONTENTS
Features............................................................................................................................. 1
Applications........................................................................................................................ 1
Typical Application ................................................................................................................ 1
Description......................................................................................................................... 1
Absolute Maximum Ratings...................................................................................................... 4
Order Information.................................................................................................................. 4
Pin Configuration.................................................................................................................. 4
Electrical Characteristics......................................................................................................... 5
Typical Performance Characteristics........................................................................................... 9
Pin Functions......................................................................................................................13
Block Diagram.....................................................................................................................15
Timing Diagrams.................................................................................................................16
Operation..........................................................................................................................17
Reference Input Buffer........................................................................................................................................... 17
Reference Divider (R)............................................................................................................................................ 18
Phase/Frequency Detector (PFD)........................................................................................................................... 18
Lock Indicator........................................................................................................................................................ 18
Charge Pump......................................................................................................................................................... 19
Reference Aligned Output (RAO) Mode................................................................................................................. 20
VCO Input Buffer.................................................................................................................................................... 20
VCO Divider (N)..................................................................................................................................................... 21
Output Dividers (M0 to M10)................................................................................................................................. 21
Digital Output Delays (DDEL0 to DDEL10)............................................................................................................. 21
Analog Output Delays (ADEL0 to ADEL10)............................................................................................................ 21
CML Output Buffers (OUT0 to OUT10).................................................................................................................. 22
Output Synchronization and SYSREF Generation................................................................................................... 22
Serial Port.............................................................................................................................................................. 30
Block Power-Down Control.................................................................................................................................... 36
Applications Information........................................................................................................37
Introduction........................................................................................................................................................... 37
Output Frequency.................................................................................................................................................. 37
Loop Filter Design.................................................................................................................................................. 37
Digital and Analog Output Delays........................................................................................................................... 38
Reference Input..................................................................................................................................................... 38
VCO Input.............................................................................................................................................................. 38
EZS_SRQ Input...................................................................................................................................................... 41
JESD204B/C Design Example Using EZSync Standalone....................................................................................... 41
JESD204B/C Design Example Using Ezsync Multi-Chip......................................................................................... 48
Reference Source Considerations.......................................................................................................................... 64
In-Band Output Phase Noise.................................................................................................................................. 65
Output Phase Noise Due To 1/f Noise.................................................................................................................... 65
Reference Signal Routing, Spurious, and Phase Noise.......................................................................................... 65
Supply Bypassing and PCB Layout Guidelines....................................................................................................... 66
Rev 0
2
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LTC6952
TABLE OF CONTENTS
ADC Clocking and Jitter Requirements.................................................................................................................. 67
Measuring Clock Jitter Indirectly Using ADC SNR................................................................................................. 69
ADC Sample Clock Input Drive Requirements........................................................................................................ 69
Transmission Lines and Termination...................................................................................................................... 69
Using the LTC6952 to Drive Device Clock Inputs................................................................................................... 70
Using the LTC6952 to Drive DC Coupled SYSREF Inputs...................................................................................... 70
Using The LTC6952 to Drive AC Coupled SYSREF Inputs in Continuous or Gated Mode...................................... 71
Using the LTC6952 to Drive AC Coupled SYSREF Inputs In Pulsed Mode............................................................. 71
Measuring Differential Spurious Signals Using Single-Ended Test Equipment....................................................... 72
Package Description.............................................................................................................79
Typical Application...............................................................................................................80
Related Parts......................................................................................................................80
Rev 0
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3
LTC6952
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
GND
VCP+
CP
VREF+
REF+
REF–
EZS_SRQ+
EZS_SRQ–
STAT
SCLK
SDO
TOP VIEW
SDI
Supply Voltages
V+ (VREF+, V VCO+, VD+, VOUT+) to GND......................3.6V
VCP+ to GND..............................................................5.5V
Voltage on CP Pin...................GND - 0.3V to VCP+ + 0.3V
Voltage on all other Pins............ GND - 0.3V to V+ + 0.3V
Current into OUTx+, OUTx–, (x = 0 to 10)..............±25mA
Operating Junction Temperature Range, TJ (Note 2)
LTC6952I................................................ –40°C to 125°C
Junction Temperature, TJMAX................................. 130°C
Storage Temperature Range................... –65°C to 150°C
52 51 50 49 48 47 46 45 44 43 42 41
CS 1
40 SD
VD+ 2
39 VVCO+
OUT10– 3
38 VCO–
OUT10+
4
37 VCO+
+
5
36 NC
VOUT
35 VOUT+
OUT9– 6
OUT9+
34 OUT0+
53
GND
7
VOUT+ 8
33 OUT0–
OUT8– 9
32 VOUT+
OUT8+ 10
31 OUT1+
VOUT+ 11
30 OUT1–
OUT7– 12
29 VOUT+
OUT7+
13
28 OUT2+
VOUT 14
27 OUT2–
+
VOUT
+
OUT3+
OUT3–
VOUT
+
OUT4+
OUT4–
VOUT
+
OUT5+
OUT5–
VOUT+
OUT6–
OUT6+
15 16 17 18 19 20 21 22 23 24 25 26
UKG PACKAGE
52-LEAD (7mm × 8mm) PLASTIC QFN
TJMAX = 130°C, θJA = 31°C/W, θJC = 2°C/W
EXPOSED PAD (PIN #53) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
JUNCTION TEMPERATURE RANGE
LTC6952IUKG#PBF
LTC6952IUKG#TRPBF
6952
52-Lead (7mm × 8mm) Plastic QFN
–40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
Rev 0
4
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LTC6952
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VREF+ = VD+ = VVCO+ = VOUT+ = 3.3V, VCP+ = 5V unless otherwise
specified (Note 2). All voltages are with respect to GND.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
500
2.7
MHz
VP-P
V/µs
%
V
mVP-P
Reference Inputs (REF+, REF–)
Input Frequency
Input Signal Level
Minimum Input Slew Rate
Input Duty Cycle
Self-bias Voltage
Minimum Input Signal Detected
(REFOK=1)
Maximum Input Signal Not Detected
(REFOK=0)
Input Resistance
Input Capacitance
VCO Input (VCO+, VCO–)
fVCO
Frequency Range
Input Signal Level
fREF
VREF
l
Single-Ended
l
l
PDREFPK = 0, fREF = 10MHz,
Single-Ended Sine Wave
PDREFPK = 0, fREF = 10MHz,
Single-Ended Sine Wave
Differential
Differential
l
RZ = 50Ω, Single-Ended
1
0.5
1.65
350
2
20
50
1.85
l
2.4
3.8
1.3
l
0.25
0.8
l
–8
2
2.05
l
1.6
l
l
Self-Bias Voltage
Input Common Mode Voltage
800mVP-P Differential Input
Input Duty Cycle
Minimum Input Slew Rate
Minimum Input Signal Detected
PDVCOPK = 0, fVCO = 100MHz,
Single-Ended Sine Wave
(VCOOK = 1)
Maximum Input Signal Not Detected
PDVCOPK = 0, fVCO = 100MHz,
(VCOOK = 0)
Single-Ended Sine Wave
Input Resistance
Differential
Input Capacitance
Differential
CMOS SYNC/SYSREF Request Input (EZS_SRQ+ Only)
High-level Input Voltage
EZS_SRQ– tied to GND
Low-level Input Voltage
EZS_SRQ– tied to GND
Input Voltage Hysteresis
EZS_SRQ– tied to GND
Input Current
EZS_SRQ– tied to GND
Differential SYNC/SYSREF Request Inputs (EZS_SRQ+ and EZS_SRQ–)
Input Signal Level
Self-bias Voltage
Input Common Mode Voltage
800mVP-P Differential Input
Input Resistance
Differential
Input Capacitance
Differential
Phase/Frequency Detector (PFD)
fPFD
Input Frequency
Charge Pump
ICP
Output Current Range
20 Settings (see Table 6)
Output Current Source/Sink Accuracy
ICP = 423μA to 4.0mA, V(CP) = VCP+/2
ICP = 4.72μA to 11.2mA, V(CP) = VCP+/2
Output Current Source/Sink Matching
ICP = 423µA to 4.0mA, V(CP) = VCP+/2
ICP = 4.72mA to 11.2mA, V(CP) = VCP+/2
Output Current vs Output Voltage Sensitivity
(Note 7)
2.25
100
mVP-P
5.8
kΩ
pF
4500
1.6
MHz
VP-P
8
2.7
50
100
l
250
40
l
250
1.0
l
0.6
200
±1
l
l
l
0.5
1.6
1.5
0.8
2.1
0.423
l
0.25
V
V
mV
µA
2.7
2.5
3.0
VP-P
V
V
kΩ
pF
167
MHz
11.2
±8
±6
±5
±2.5
1.0
mA
%
%
%
%
%/V
53
1
l
mVP-P
Ω
pF
1.3
l
dBm
V
V
%
V/µs
mVP-P
Rev 0
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5
LTC6952
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VREF+ = VD+ = VVCO+ = VOUT+ = 3.3V, VCP+ = 5V unless otherwise
specified (Note 2). All voltages are with respect to GND.
SYMBOL PARAMETER
Output Current vs Temperature
Output Hi-Z Leakage Current
VMID
Mid-supply Output Bias Ratio
Reference Divider (R)
R
Divide Range
VCO Divider (N)
N
Divide Range
Digital Pin Specifications
VIH
High-level Input Voltage
VIL
Low-level Input Voltage
VIHYS
Input Voltage Hysteresis
Input Current
IOH
High-level Output Current
IOL
Low-level Output Current
SDO Hi-Z Current
Digital Timing Specifications
tCKH
SCLK High Time
tCKL
SCLK Low Time
tCSS
CS Setup Time
tCSH
CS High Time
tCS
SDI to SCLK Setup Time
tCH
SDI to SCLK Hold Time
tDO
SCLK to SDO Time
EZS_SRQ Timing Specifications (See Figure 2)
tSRQH
EZS_SRQ High Time
tSRQL
EZS_SRQ Low Time
EZS_SRQ Skew, Part to Part
tSS
EZS_SRQ to REF Setup Time
CONDITIONS
+/2
MIN
TYP
MAX
UNITS
V(CP) = VCP
ICP = 423µA (Note 7)
ICP = 11.2mA (Note 7)
Referred to (VCP+ - GND)
l
All Integers Included
l
1
1023
Counts
All Integers Included
l
1
65535
Counts
CS, SDI, SCLK, SD
CS, SDI, SCLK, SD
CS, SDI, SCLK, SD
CS, SDI, SCLK, SD
SDO and STAT, VOH = VD+ - 400mV
SDO and STAT, VOL = 400mV
l
1.55
170
0.5
5
0.48
16
ns
ns
ns
ns
ns
ns
ns
250
l
l
l
l
l
l
l
l
l
2.0
–3.3
3.4
l
±1
–1.9
25
25
10
10
6
6
l
l
SRQMD = 0, PARSYNC = 0
PARSYNC = 1, CMOS EZS_SRQ
PARSYNC = 1, Differential EZS_SRQ
tSH
EZS_SRQ to REF Hold Time
PARSYNC = 1, CMOS EZS_SRQ
PARSYNC = 1, Differential EZS_SRQ
Output Dividers (M0, M1, M2, M3, M4, M5, M6, M7, M8, M9 and M10)
Mx
Output Divider Range (x = 0 to 10)
Mx = P × 2N, where
P = 1 to 32 all integers, N = 0 to 7
DDELx
Output Digital Delay (x = 0 to 10)
½ VCO Cycles (Note 3)
tADELx
Output Analog Delay Time (x = 0 to 10)
ADELx = 0
ADELx = 1, fOUTx ≤ 300MHz
ADELx = 63, fOUTx ≤ 300MHz
Output Analog Delay Time
ADELx = 1 to 31, fOUTx ≤ 300MHz
(x = 0 to 10), Step Size
ADELx = 32 to 63, fOUTx ≤ 300MHz
Output Analog Delay (x = 0 to 10)
300MHz ≤ fOUTx ≤ 2.25GHz
Maximum Output Frequency for Analog Delay
Temperature Coefficient of Analog Delay Time ADELx = 1 to 31
ADELx = 32 to 63
±1
V
V
mV
µA
mA
mA
µA
0.8
l
l
To VIH/VIL /Hi-Z with 30pF load
ppm/°C
nA
nA
V/V
1
1
10
ms
ms
µs
ns
l
1
0.5
1
0.5
l
1
4096
Counts
l
0
4095
½ Cycles
ps
l
l
l
l
l
ns
0
90
1100
11
26
Note 4
2.25
0.06
0.06
ps
GHz
%/°C
Rev 0
6
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LTC6952
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VREF+ = VD+ = VVCO+ = VOUT+ = 3.3V, VCP+ = 5V unless otherwise
specified (Note 2). All voltages are with respect to GND.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
MHz
CML Clock Outputs (OUT0+, OUT0–, OUT1+, OUT1–, OUT2+, OUT2–, …, OUT10+, OUT10–)
fOUT
VOD
tR
tF
tPD-VCO
tPD-REF
tSKEW
Output Frequency
Output Differential Voltage
Output Resistance
Output Common Mode Voltage
Output Rise Time, 20% to 80%
Output Fall Time, 80% to 20%
Output Duty Cycle
Propagation Delay from VCO± to OUT10
Propagation Delay from VCO± to OUT10,
Tem-perature Variation
Propagation Delay from REF± to OUT5
Propagation Delay from REF± to OUT5,
Temperature Variation
Skew, all Outputs (Note 20)
Additional Output Delay, Mx = Odd vs
Mx = 1 or Even
Differential Termination = 100Ω,
MODEx = 0 (Clock Mode)
Differential Termination = 100Ω,
MODEx = 1, 2, or 3 (SYSREF Modes)
Differential Termination = 100Ω
Differential
Differential Termination = 100Ω
Differential Termination = 100Ω
Differential Termination = 100Ω
Differential Termination = 100Ω
fVCO = 4500MHz, Mx = 16
fVCO = 4500MHz, Mx = 16
l
0
4500
l
0
150
l
320
l
45
RAO = 0, LOCK = 1 (Note 19)
RAO = 1, LOCK = 1 (Note 19)
RAO = 1, LOCK = 1 (Note 19)
l
One Part, All Mx the Same, Even, or 1
One Part, Any Mx
Across Multiple Parts; RAO = 1, All Mx the
Same, Even, or 1; All TJ Within ±10°C
Mx = 5, 11, 15, 17, 19, 25, or 27
Mx = 3, 7, 9, 13, 21, 23, 29, or 31
l
Power Supply Voltages
VREF+ Supply Range
VOUT+ Supply Range
VD+ Supply Range
VVCO+ Supply Range
VCP+ Supply Range
Power Supply Currents
IDDOUT
Sum VOUT+ Supply Currents
ICCCP
IDD-3.3V
l
550
55
450
20
0.2
l
±10
±30
±20
l
l
l
l
l
l
l
l
3.15
3.15
3.15
3.15
3.15
mVpk
Ω
V
ps
ps
%
ps
ps/°C
ps
ps/°C
±25
ps
±50
4
15
l
All Outputs Enabled (Note 5)
Typical JESD204B/C Application (Note 6)
PDALL = 1
VCP+ Supply Current
ICP = 11.2mA
ICP = 423µA
PDALL = 1
Sum VD+, VREF+, VVCO+ Supply Currents
Digital Inputs at Supply Levels
Digital Inputs at Supply Levels, PDALL = 1
Supply Current Deltas from Total Chip Current PDx[1:0] = 2 (x = 0 to 10), Per Output
PDx[1:0] = 3 (x = 0 to 10), Per Output
EZS_SRQ± State = 1, SSRQ = 1 or SRQMD = 1
PDPLL = 1
Mx = Odd (Not Mx = 1), Per Output
ADELx = 1 to 31, Per Output
ADELx = 32 to 63, Per Output
420
100
VOUT+-1.0
50
50
50
335
0.35
ps
3.3
3.3
3.3
3.3
3.45
3.45
3.45
3.45
5.25
V
V
V
V
V
750
570
500
37
10
500
176
500
–34
–68
+175
–113
+8.6
+3.0
+4.7
850
mA
mA
µA
mA
mA
µA
mA
µA
mA
mA
mA
mA
mA
mA
mA
45
200
Rev 0
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7
LTC6952
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VREF+ = VD+ = VVCO+ = VOUT+ = 3.3V, VCP+ = 5V unless otherwise
specified (Note 2). All voltages are with respect to GND.
SYMBOL PARAMETER
Additive Phase Noise, Jitter and Spurious (Note 8)
Output Noise/Jitter: Distribution Section Only
(fVCO = 4.5GHz, fOUTx = 4.5GHz, Mx = 1)
Output Noise/Jitter: Distribution Section Only
(fVCO = 4.5GHz, fOUTx = 2.25GHz, Mx = 2)
Output Noise/Jitter: Distribution Section Only
(fVCO = 4.5GHz, fOUTx = 1.125GHz, Mx = 4)
Output Noise/Jitter: Distribution Section Only
(fVCO = 3.2GHz, fOUTx = 200MHz, Mx = 16)
Output Noise/Jitter: Distribution Section Only
(fVCO = 3.2GHz, fOUTx = 50MHz, Mx = 64)
LNORM
L1/f
Normalized In-Band Phase Noise Floor
Normalized In-Band 1/f Phase Noise
Spurious
CONDITIONS
MIN
Phase Noise Floor
RMS Jitter, 12kHz to 20MHz Integration BW
RMS Jitter, ADC SNR Method (Note 15)
Phase Noise Floor
RMS Jitter, 12kHz to 20MHz Integration BW
RMS Jitter, ADC SNR Method (Note 15)
Phase Noise Floor
RMS Jitter, 12kHz to 20MHz Integration BW
RMS Jitter, ADC SNR Method (Note 15)
Phase Noise Floor
RMS Jitter, 12kHz to 20MHz Integration BW
RMS Jitter, ADC SNR Method (Note 15)
Phase Noise Floor
RMS Jitter, 12kHz to 20MHz Integration BW
RMS Jitter, ADC SNR Method (Note 15)
ICP = 11.2mA (Note 9, Note 10, Note 11)
ICP = 11.2mA (Note 9, Note 12)
fOFFSET = fPFD, fOUT = 4GHz, PLL Locked
(Note 10, Note 13, Note 14, Note 18)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to any Absolute Maximum
Rating condition for extended periods may affect device reliability and lifetime.
Note 2. The LTC6952 is guaranteed to meet specified performance limits
over the full operating junction temperature range of –40°C to 125°C. Under
maximum operation conditions, air flow or heat sinking may be required
to maintain a junction temperature of 125°C or lower. It is required that the
Exposed Pad (Pin 53) be soldered directly to the ground plane with an array
of thermal vias as described in the Applications Information section.
Note 3. Absolute maximum time of digital delay is limited to 100µs.
Note 4. For fOUT ≥ 300MHz, analog delay time vs ADELx varies. See
Typical Performance Characteristics plot and the Operations section.
Note 5. All outputs configured as enabled clocks: all PDx[1:0]=0,
EZS_SRQ± pin state=0, SSRQ=0, SRQMD=0, BST=1, PDALL=0,
PDVCOPK=0, PDREFPK=0.
Note 6. Configured with six enabled clock outputs and five SYSREF
outputs with output drivers disabled: PD0, PD2, PD4, PD6, PD8, and
PD10 = 0; PD1, PD3, PD5, PD7, and PD9 = 2; EZS_SRQ± pin state=0;
SSRQ=0; SRQMD=0; BST=1; PDALL=0; PDVCOPK=0; PDREFPK=0
Note 7. For 1.0V < V(CP) < VCP+ – 1.1V.
Note 8. Additive phase noise and jitter from LTC6952 distribution section
only. External VCO, reference and PLL noise is not included.
Note 9. Measured inside the loop bandwidth with the loop locked.
TYP
–154.3
6
65
–157.1
8
66
–160.2
9
65
–167.8
21
65
–173.8
41
65
–229
–281
–100
MAX
UNITS
dBc/Hz
fsRMS
fsRMS
dBc/Hz
fsRMS
fsRMS
dBc/Hz
fsRMS
fsRMS
dBc/Hz
fsRMS
fsRMS
dBc/Hz
fsRMS
fsRMS
dBc/Hz
dBc/Hz
dBc
Note 10. Reference frequency supplied by Pascal OCXO-E, fREF = 100MHz,
PREF = 6dBm.
Note 11. Output Phase Noise Floor is calculated from Normalized Phase
Noise Floor by LOUT = LNORM + 10log10(fPFD) + 20log10(fRF/fPFD).
Note 12. Output 1/f Noise is calculated from Normalized 1/f Phase Noise
by LOUT(1/f) = L1/f + 20log10(fRF) - 10log10(fOFFSET).
Note 13. ICP = 11.2mA, fPFD = 100MHz, FILTR = 0, Loop BW = 16kHz,
fVCO = 4GHz
Note 14. Measured using DC2609
Note 15. Additive RMS jitter (ADC SNR method) is calculated by integrating
the distribution section’s measured additive phase noise floor out to fCLK.
Actual ADC SNR measurements show good agreement with this method.
Note 16. Measured with 36” cables from output of DC2609 to
measurement instrument. Cable loss is NOT accounted for in this plot.
Note 17. Statistics calculated from 640 total measured parts from two
process lots.
Note 18. Measured using differential LTC6952 outputs driving LTC6955.
LTC6955 provides differential to single-ended conversion for rejection of
common mode spurious signals. See the Applications Information section
for details.
Note 19. Measured on OUT5. fREF = 100MHz, fVCO = 4400MHz, fOUT =
275MHz, RD = 1
Note 20. Skew is defined as the difference between the zero-crossing time
of a given output and the average zero-crossing time of all outputs.
Note 21. Measured VCO input power is de-embedded to the pins of the
LTC6952.
Rev 0
8
For more information www.analog.com
LTC6952
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VREF+ = VOUT+ = VD+ = VVCO+ = 3.3V,
VCP+ = 5V, unless otherwise noted.
–120
–130
–140
–150
–160
VCO OUTPUT
LTC6952 OUTPUT
–170
–180
100
1k
–120
–130
–140
–150
–160
2GHz
1GHz
500MHz
250MHz
–170
–180
10k
100k
1M
OFFSET FREQUENCY (Hz)
10M 40M
–100
VCO: CVCO55CC–4000–4000
NOTES 10, 13
–110
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
–100
VCO: CVCO55CC–4000–4000
NOTES 10, 13
–110
Total Closed Loop Phase Noise,
fVCO = 4GHz, Mx = 2, 4, 8, and 16
1k
Total Open Loop Phase Noise
FIN = 100MHz Sine Wave
PASCAL_OCXO
10dBm, FILTV=0
10dBm, FILTV=1
0dBm, FILTV=0
0dBm, FILTV=1
–10dBm, FILTV=0
–10dBm, FILTV=1
–110
PHASE NOISE (dBc/Hz)
–100
Total Closed Loop Phase Noise
fVCO= 4GHz, Mx = 1
–120
–130
–140
–150
–160
–170
10k
100k
1M
OFFSET FREQUENCY (Hz)
Mx = 1
–180
100
1k
10M 40M
10k
100k
1M
OFFSET FREQUENCY (Hz)
10M 40M
6952 G03
6952 G02
6952 G01
900
800
Mx = 1
NOTES 8, 15
600
500
400
95
ODD DIVIDER
EVEN DIVIDER
90
NOTES 8, 15
85
JITTER (fsRMS)
700
JITTER (fsRMS)
100
FILTV=0
FILTV=1
80
75
70
300
65
200
60
100
55
0
0.1
1
INPUT SLEW RATE (V/ns)
50
10
0
4
8
12 16 20 24
OUTPUT DIVIDER VALUE
28
Additive Jitter vs ADEL Value,
ADC SNR Method fVCO = 4GHz,
Mx = 2, 4, 8, and 16
500
NOTES 8, 15
400
400
350
350
300
250
200
250MHz
500MHz
1GHz
2GHz
50
0
10
20
30
40
ADEL VALUE
50
–225
–226
–227
–228
RAO = 1
–229
RAO = 0
–230
0.5
250 MHz
500 MHz
1000 MHZ
2000 MHz
4000 MHz
300
250
200
60
100
3.5
5.0 6.5
ICP (mA)
8.0
9.5
11.0
6952 G06
0.5
0.4
0.3
0.2
0.1
0.0
–0.1
–0.2
–0.3
–0.4
50
0
2.0
Differential Output at 4.5GHz
150
150
0
NOTES 8, 15
450
100
–224
Additive Jitter vs DDEL Value,
ADC SNR Method fVCO = 4GHz,
Mx = 1, 2, 4, 8, and 16
JITTER (fsRMS)
JITTER (fsRMS)
450
32
–223
6952 G05
6952 G04
500
Normalized In-Band Phase Noise
Floor vs CP Current
DIFFERENTIAL OUTPUT (V)
1000
Additive Jitter vs Divider Setting,
ADC SNR Method
PHASE NOISE FLOOR (dBc/Hz)
Additive Jitter vs Input Slew Rate,
ADC SNR Method
0
200
400
600
DDEL VALUE
800
1000
–0.5
100ps/DIV
6952 G09
6952 G08
6952 G07
Rev 0
For more information www.analog.com
9
LTC6952
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VREF+ = VOUT+ = VD+ = VVCO+ = 3.3V,
VCP+ = 5V, unless otherwise noted.
0.5
0.95
0.3
0.2
0.1
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
0.90
0.85
0.80
0.75
0.70
0.65
label1
label3
label2
125°C
25°C
–40°C
1100
1000
900
800
700
600
500
400
300
200
0.60
0.55
6952 G10
200ps/DIV
1200
125°C
25°C
–40°C
ANALOG DELAY TIME (ps)
DIFFERENTIAL OUTPUT SWING (VP-P)
0.4
DIFFERENTIAL OUTPUT (V)
Analog Delay Time
vs ADEL Value, Temperature
Differential Output Swing
vs Frequency, Temperature
Differential Output at 1GHz
100
NOTES 14, 16
0
1
2
3
OUTPUT FREQUENCY (GHz)
0
4
0
10
20
30
40
ADEL VALUE
50
60
6952 G11
1200
label1
label3
label2
125°C
–40°C
30
1000
20
10
0
–10
–20
800
700
600
NOTES 17, 20
5
500
400
0
+3σ
–5
AVERAGE
300
–10
–3σ
100
0
10
20
30
40
ADEL VALUE
50
0
60
0
10
20
30
40
ADEL VALUE
50
Expected Skew Variation Across
Multiple Parts in ParallelSync
Mode
150
NOTE 20
2
3
4 5 6
OUTPUT
7
8
RAO = 1
PARSYNC = 1
9 10
Skew Between Two Parts at
Different Temperatures
50
NOTE 17
40
TJ of Part #1 = 25°C
–10
OUT0
OUT1
OUT2
OUT3
0
20
OUT4
OUT5
OUT6
OUT7
40 60
TJ (°C)
100
SKEW (ps)
NUMBER OF PARTS
30
0
–30
–40 –20
1
6952 G15
10
–20
0
6952 G14
Skew Variation with Temperature
For a Single Typical Part
20
–15
60
6952 G13
SKEW (ps)
fvco = 4.5GHz, Mx=16
10
200
–30
–40
900
Expected Skew Variation for a
Single Part
15
100MHz
300MHz
500MHz
750MHz
1000MHz
1500MHz
1750MHz
2250MHz
1100
ANALOG DELAY TIME (ps)
TADEL TEMPERATURE VARIATION (ps)
40
Analog Delay Time vs ADEL Value
Over Multiple Output Frequencies
SKEW (ps)
Analog Delay Time Temperature
Variation from 25°C
6952 G12
50
100 120
10
0
–10
OUT8
OUT9
OUT10
80
20
–20
0
–40 –30 –20 –10 0
10
SKEW (ps)
20
30
6952 G16
40
6952 G17
–30
–40 –20
RAO = 0
RAO = 1
0
20 40 60 80
TJ OF PART #2 (°C)
100 120
6952 G18
Rev 0
10
For more information www.analog.com
LTC6952
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VREF+ = VOUT+ = VD+ = VVCO+ = 3.3V,
VCP+ = 5V, unless otherwise noted.
VCO Propagation Delay
vs Frequency, Temperature
380
Propagation Delay Variation, VCO
Input to OUT4
250
FILTV = 0
370
NUMBER OF PARTS
TPD-VCO (ps)
340
330
320
310
150
100
125°C
70°C
25°C
–40°C
300
290
0
1
2
3
FREQUENCY (GHz)
0
320
4
Closed Loop Reference to Output
Propagation Delay, RAO = 0
325
0
–60
350
50
450
480
510
tPD–REF (ps)
2
ERROR (%)
1
0
–1
–2
–6
–3
–8
–4
6952 G22
1.5 2 2.5 3 3.5
OUTPUT VOLTAGE (V)
4
4.5
–5
5
4
4
3
3
2
2
2
1
1
1
ICP = 11.2mA
125°C
25°C
–40°C
–4
–5
0
0.5
1
1.5 2 2.5 3 3.5
OUTPUT VOLTAGE (V)
4
4.5
5
1
5
423uA
5.61mA
11.2mA
1.5 2 2.5 3 3.5
OUTPUT VOLTAGE (V)
4
4.5
–1
0
–1
–2
–2
–3
–3
–4
–4
0
0.5
1
1.5 2 2.5 3 3.5
OUTPUT VOLTAGE (V)
4
4.5
6952 G25
125°C
25°C
–40°C
3
0
–5
5
ICP = 11.2mA
4
ERROR (%)
ERROR (%)
5
–3
0.5
Charge Pump Source Current
Error vs Voltage, Temperature
5
–2
0
6952 G24
Charge Pump Source Current
Error vs Voltage, Output Current
–1
423µA
5.61mA
11.2mA
6952 G23
Charge Pump Sink Current Error
vs Voltage, Temperature
0
6952 G21
3
–4
1
60
4
0
0.5
30
5
–2
0
0
TPD-REF (ps)
Charge Pump Sink Current Error
vs Voltage, Output Current
2
–10
–30
6952 G20
125°C
25°C
–40°C
4
CURRENT (nA)
NUMBER OF PARTS
345
ICP = 11.2mA
8 CPRST=1
100
ERROR (%)
330
335
340
tPD-VCO (ps)
10
6
420
50
Charge Pump Hi–Z Current
vs Voltage, Temperature
NOTES 17, 19
0
390
100
50
6952 G19
150
NOTES 17, 19
200
350
280
150
NOTE 17
NUMBER OF PARTS
360
Closed Loop Reference to Output
Propagation Delay, RAO = 1
5
6952 G26
–5
0
0.5
1
1.5 2 2.5 3 3.5
OUTPUT VOLTAGE (V)
4
4.5
5
6952 G27
Rev 0
For more information www.analog.com
11
LTC6952
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VREF+ = VOUT+ = VD+ = VVCO+ = 3.3V,
VCP+ = 5V, unless otherwise noted.
REF Input Sensitivity
vs Frequency, Temperature
REF Input Signal Detected
vs Frequency, Temperature
–25
250
–6
BST = 1
FILTR = 0
–30
225
–40
–45
–50
–55
BST = 1
–60 FILTR = 0
NOTE 14
–65
0 50 100 150 200 250 300 350 400
FREQUENCY (MHz)
200
175
150
125°C
25°C
–40°C
0
125°C
25°C
–40°C
0
1
FILTV = 0
2
3
FREQUENCY (GHz)
6952 G29
Spurious Response, fOUT = 4GHz,
fVCO = 4GHz, fREF = 100MHz,
fPFD = 100MHz, Loop BW = 16kHz
Spurious Response, fOUT = 4GHz,
fVCO = 4GHz, fREF = 100MHz,
fPFD = 10MHz, Loop BW = 5kHz
0
0
Spurious Response, fOUT = 4GHz,
fVCO = 4GHz, fREF = 100MHz,
fPFD = 10MHz, Loop BW = 5kHz
VBW = 1Hz
–20 RBW = 1Hz
NOTES 14, 18
–40
–40
–40
–60
–60
–60
–100
POUT (dBc)
VBW = 1Hz
–20 RBW = 1Hz
NOTES 14, 18
–80
–80
–100
–80
–100
–120
–120
–120
–140
–140
–140
–160
–400 –300 –200 –100 0 100 200 300 400
FREQUENCY OFFSET (MHz in 10kHz SEGMENTS)
–160
–40 –30 –20 –10 0 10 20 30 40
FREQUENCY OFFSET (MHz in 10kHz SEGMENTS)
Supply Current vs Junction
Temperature, All Outputs Enabled
900
910
34
900
890
32
5V
3.3V
20
40 60
TJ (°C)
80
100 120
800
700
CURRENT (mA)
36
0
6952 G33
1000
920
ICP = 11.2mA
NOTE 5
30
–40 –20
–400 –300 –200 –100 0 100 200 300 400
FREQUENCY OFFSET (MHz in 10kHz SEGMENTS)
3.3V Supply Current
vs Number of Disabled Outputs
3.3V CURRENT (mA)
5V CURRENT (mA)
38
–160
6952 G32
6952 G31
4
6952 G30
VBW = 1Hz
–20 RBW = 1Hz
NOTES 14, 18
POUT (dBc)
POUT (dBc)
0
–12
–16
50 100 150 200 250 300 350 400 450 500
FREQUENCY (MHz)
6952 G28
–10
–14
125°C
25°C
–40°C
125
450 500
NOTE 21
–8
SENSITIVITY (dBm)
SENSITIVITY (mVP–P)
–35
SENSITIVITY (dBm)
VCO Input Signal Detected
vs Frequency, Temperature
600
500
400
300
200
100
880
0
FULLY DISABLED (PDx=3)
DRIVER ONLY DISABLED (PDx=2)
0
1
6952 G34
2 3 4 5 6 7 8 9 10 11
NUMBER OF DISABLED OUTPUTS
6952 G35
Rev 0
12
For more information www.analog.com
LTC6952
PIN FUNCTIONS
CS (Pin 1): Serial Port Chip Select. This CMOS input initiates a serial port communication burst when driven low,
ending the burst when driven back high. See the Operation
section for more details.
VD+ (Pin 2): 3.15V to 3.45V positive supply pins for synchronization/SYSREF request functions and serial port.
This pin should be bypassed directly to the ground plane
using a 0.01µF ceramic capacitor as close to the pin as
possible.
OUT0+, OUT0– (Pins 34, 33): Output Signals. The output
divider is buffered and presented differentially on these
pins. The outputs have 50Ω (typical) output resistance per
side (100Ω differential). The far end of the transmission
line is typically terminated with 100Ω connected across the
outputs. See the Operation and Applications Information
section for more details.
OUT1+, OUT1– (Pins 31, 30): Same as OUT0.
OUT2+, OUT2– (Pins 28, 27): Same as OUT0.
OUT3+, OUT3– (Pins 25, 24): Same as OUT0.
OUT4+, OUT4– (Pins 22, 21): Same as OUT0.
OUT5+, OUT5– (Pins 19, 18): Same as OUT0.
OUT6+, OUT6– (Pins 16, 15): Same as OUT0.
OUT7+, OUT7– (Pins 13, 12): Same as OUT0.
OUT8+, OUT8– (Pins 10, 9): Same as OUT0.
OUT9+, OUT9– (Pins 7, 6): Same as OUT0.
OUT10+, OUT10– (Pins 4, 3): Same as OUT0.
VOUT+ (Pins 5, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35):
3.15V to 3.45V positive supply pins for output dividers.
Each pin should be separately bypassed directly to the
ground plane using a 0.01µF ceramic capacitor as close
to the pin as possible.
NC (Pin 36): Not Connected Internally. It is recommended
that this pin be connected to the ground pad (Pin 53).
VCO+, VCO– (Pins 37, 38): VCO Input Signals. The differential signal placed on these pins is buffered with a low
noise amplifier and fed to the internal distribution path
and feedback dividers. These self-biased inputs present
a differential 250Ω (typical) resistance to aid impedance
matching. They may also be driven single-ended by using
the matching circuit in the Applications Information section.
VVCO+ (Pins 39): 3.15V to 3.45V positive supply pin for
VCO circuitry. This pin should be bypassed directly to the
ground plane using a 0.01µF ceramic capacitor as close
to the pin as possible.
SD (Pin 40): Chip Shutdown Pin. When tied to GND, this
CMOS input disables all blocks in the chip. This is the
same function as PDALL in the serial interface.
GND (Pin 41): Negative Power Supply (Ground). This pin
should be tied directly to the ground pad (Pin 53).
VCP+ (Pin 42): 3.15V to 5.25V positive supply pin for charge
pump circuitry. This pin should be bypassed directly to
the ground plane using a 0.1µF ceramic capacitor as close
to the pin as possible.
CP (Pin 43): Charge Pump Output. This bidirectional current output is normally connected to the external loop filter.
See the Applications Information section for more details.
VREF+ (Pin 44): 3.15V to 3.45V positive supply pin for reference input circuitry. This pin should be bypassed directly
to the ground plane using a 0.1µF ceramic capacitor as
close to the pin as possible.
REF+, REF– (Pins 45, 46): Reference Input Signals. This
differential input is buffered with a low noise amplifier,
which feeds the reference divider. They are self-biased and
must be AC coupled with 1µF capacitors. If used singleended with V(REF+) ≤ 2.7VP-P, bypass REF– to GND with
a 100nF capacitor. If used single-ended with V(REF+) >
2.7VP-P, bypass REF– to GND with a 47pF capacitor.
Rev 0
For more information www.analog.com
13
LTC6952
PIN FUNCTIONS
EZS_SRQ+, EZS_SRQ– (Pins 47, 48): Synchronization
or SYSREF Request Input. Bit SRQMD defines this input
as an EZSync request or SYSREF request. It can operate
as a differential input, or EZS_SRQ– can be tied to GND
and EZS_SRQ+ driven with a single-ended CMOS signal.
See the Operation and Applications Information section
for more details.
STAT (Pin 49): Status Output. This signal is a configurable
logical OR combination of the UNLOCK, VCOOK, VCOOK,
LOCK, LOCK, REFOK, and REFOK status bits, programmable via the STATUS register. It can also be configured
to present a diode voltage for temperature measurement.
See the Operation section for more details.
SCLK (Pin 50): Serial Port Clock. This CMOS input clocks
serial port input data on its rising edge. See the Operation
section for more details.
SDO (Pin 51): Serial Port Data Output. This CMOS threestate output presents data from the serial port during a
read communication burst. Optionally attach a resistor
of > 200kΩ to GND to prevent a floating output. See the
Operation section for more details.
SDI (Pin 52): Serial Port Data Input. The serial port uses
this CMOS input for data. See the Operation section for
more details.
GND (Exposed Pad Pin 53): Negative Power Supply
(Ground). The package exposed pad must be soldered
directly to the PCB land. The PCB land pattern should
have multiple thermal vias to the ground plane for both
low ground inductance and also low thermal resistance.
Rev 0
14
For more information www.analog.com
LTC6952
BLOCK DIAGRAM
VCP+
+
44 VREF
45
46
47
48
REF+
EZS_SRQ+
EZS_SRQ–
LOCK
IND
FILTR
CHARGE PUMP
SIGNAL
DETECT
NDIV
1-65535
SYNC AND
SYSREF CTRL
51
52
1
2
40
STAT
DDEL0
0-4095
SCLK
SDO
CS
DDEL1
0-4095
M0 DIV
1-4096
ADEL0
0-1.1ns
M1 DIV
1-4096
ADEL1
0-1.1ns
VD+
DDEL2
0-4095
M2 DIV
1-4096
ADEL2
0-1.1ns
+
OUT10
OUT10–
ADEL10
0-1.1ns
M10 DIV
1-4096
DDEL10
0-4095
DDEL3
0-4095
M3 DIV
1-4096
ADEL3
0-1.1ns
+
8 VOUT
6
OUT9+
OUT9–
ADEL9
0-1.1ns
M9 DIV
1-4096
DDEL9
0-4095
9
M4 DIV
1-4096
ADEL4
0-1.1ns
OUT2–
OUT3+
OUT3–
OUT4–
OUT5+
ADEL8
0-1.1ns
M8 DIV
1-4096
DDEL8
0-4095
DDEL5
0-4095
M5 DIV
1-4096
ADEL5
0-1.1ns
OUT5–
+
VOUT
OUT7+
OUT7–
OUT2+
VOUT
14 VOUT
12
OUT1–
+
+
13
OUT1+
OUT4+
DDEL4
0-4095
OUT8+
OUT8–
39
37
38
35
34
33
31
30
29
28
27
25
24
VOUT+ 23
+
11 VOUT
10
OUT0–
36
VOUT+ 26
5 VOUT
7
OUT0+
VOUT
SD
+
3
VOUT+
+
53 GND (EXPOSED PAD)
4
VVCO+
43
VOUT+ 32
SERIAL
PORT
AND
DIGITAL
SDI
NC
VCO–
FILTV
50
CP
VCO+
TEMPO
49
GND
423µA TO
11.2mA
RDIV
1-1023
SIGNAL
DETECT
+
–
41
PFD
+
–
REF –
42
ADEL7
0-1.1ns
M7 DIV
1-4096
DDEL7
0-4095
DDEL6
0-4095
M6 DIV
1-4096
ADEL6
0-1.1ns
OUT6+
OUT6–
22
21
20
19
18
17
16
15
6952 BD
Rev 0
For more information www.analog.com
15
LTC6952
TIMING DIAGRAMS
Propagation Delay and Output Skew
VCO–
VCO+
tPD-VCO
tSKEW0
OUT0+
OUT0–
tSKEW1
OUT1+
OUT1–
tSKEW2
OUT2+
OUT2–
tSKEW3
OUT3+
OUT3–
tSKEW3
OUT10+
OUT10–
6952 TD01
AVERAGE ZERO CROSSING TIME OF ALL OUTPUTS
Differential CML Rise/Fall Times
80%
20%
tR
tF
6952 TD02
Rev 0
16
For more information www.analog.com
LTC6952
OPERATION
The LTC6952 is a high-performance integer-N PLL and
multi-output clock generator that operates up to 4.5GHz.
Utilizing Analog Devices’ proprietary EZSync and ParallelSync standards, users of the LTC6952 can synchronize
clocks across multiple outputs and multiple chips. Using
an external low-noise VCO, the device is able to achieve
superior integrated jitter performance by the combination of
its extremely low in-band phase noise and excellent output
noise floor. For JESD204B/C subclass 1 applications, the
LTC6952 also provides several convenient methods to
generate SYSREF pulses.
REFERENCE INPUT BUFFER
The PLL’s reference frequency is applied differentially on
pins REF+ and REF–. These high-impedance inputs are
self-biased and should be AC coupled with 1µF capacitors
(see Figure 1 for a simplified schematic). Alternatively, the
inputs may be used single-ended by applying the reference frequency at REF– and bypassing REF+ to GND with
a 1µF capacitor. If the single-ended signal is greater than
2.7VP-P, then use a 47pF capacitor for the GND bypass.
BIAS
VREF+
1.9V
2.1k
Table 1. FILTR Programming
FILTR
Sine Wave fREF
Square Wave fREF
1
< 20MHz
N/A
0
≥ 20MHz
All fREF
The BST bit should be set based upon the input signal level
to prevent the reference input buffer from saturating. The
BST programming is the same whether the input is a sine
wave or a square wave. See Table 2 for recommended
settings and the Applications Information section for
programming examples.
Table 2. BST Programming
BST
VREF+
VREF
1
< 1.6 VP-P
0
≥ 1.6 VP-P
Reference Peak Detector
400Ω
REF+
Additional options are available through serial port register
h02 to further refine the application. Bit FILTR controls
the reference input buffer’s low-pass filter, and should
be set for sine wave signals based upon fREF to limit the
reference’s wideband noise. The FILTR bit must be set
correctly to reach the LNORM normalized in-band phase
noise floor. See Table 1 for recommended settings. Square
wave inputs will have FILTR set to a “0”.
2.1k
FILTR
REF –
6952 F01
BST
Figure 1. Simplified REF Interface Schematic
A high quality signal must be applied to the REF± inputs
as they provide the frequency reference to the entire PLL.
To achieve the part’s in-band phase noise performance,
apply a sine wave signal of at least 6dBm into 50Ω, or a
square wave of at least 0.5VP-P, with slew rate of at least
20V/µs. See the Applications Information section for more
information on reference input signal requirements and
interfacing.
A reference input peak detection circuit is provided on the
REF± inputs to detect the presence of a reference signal
and provides the REFOK and REFOK status flags available
through both the STAT output and serial port register
h00. REFOK is the logical inverse of REFOK. The circuit
has hysteresis to prevent the REFOK flag from chattering
at the detection threshold. The reference peak detector
may be powered-down using the PDREFPK bit found in
register h02.
The peak detector approximates an RMS detector, therefore
sine and square wave inputs will give different detection
thresholds by a factor of 4/π. See Table 3 for REFOK
detection values.
Table 3. REFOK, REFOK Status Output vs REF Input
REFOK
REFOK
Sine Wave fREF
Square Wave fREF
1
0
≥ 250mVP–P
≥ 200mVP–P
0
1
< 100mVP–P
< 75mVP–P
Rev 0
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17
LTC6952
OPERATION
REFERENCE DIVIDER (R)
A 10-bit divider is used to reduce the frequency seen at
the phase/frequency detector (PFD). Its divide ratio R may
be set to any integer from 1 to 1023. Use the RD[9:0] bits
found in registers h06 and h07 to directly program the R
divide ratio. See the Applications Information section for
the relationship between R and the fREF, fPFD, fVCO, and
fOUTx frequencies.
A mode to provide synchronization of the Reference inputs
to the R divider output (R ≥ 2) using the rising edge of
the EZS_SRQ± pins is enabled when the PARSYNC bit in
register h06 is set to “1”. This synchronization is critical
for output alignment in ParallelSync Mode, as described
later in this section. The EZS_SRQ± rising edge must meet
setup and hold timing to the rising edge of the Reference
input. See Figure 2 for the timing relationships between
the Reference input, EZS_SRQ± and the R divider output.
Note that changing the R divider output edge timing will
force the PLL to lose phase lock but will return to normal
operation after several loop time constants. See Reference
Signal and EZS_SRQ Timing for ParallelSync Mode in the
Applications Information section for the timing requirements of EZS_SRQ± to REF in this mode.
EZS_SRQ±
tSS
tSH
REF
1 REF CYCLE
R DIV
6952 F02
Figure 2. EZS_SRQ± to REF Timing (PARSYNC = 1)
PHASE/FREQUENCY DETECTOR (PFD)
The phase/frequency detector (PFD), in conjunction with
the charge pump, produces source and sink current pulses
proportional to the phase difference between the outputs
of the R and N dividers. This action provides the necessary
feedback to phase-lock the loop, forcing a phase align-
ment at the PFD’s inputs. The PFD may be disabled with
the CPRST bit which prevents UP and DOWN pulses from
being produced. See Figure 3 for a simplified schematic
of the PFD.
D
Q
UP
R DIV
RST
CPRST
DELAY
D
Q
DOWN
6952 F03
N DIV
RST
Figure 3. Simplified PFD Schematic
LOCK INDICATOR
The lock indicator uses internal signals from the PFD to
measure phase coincidence between the R and N divider
output signals. It is enabled by programming LKCT[1:0]
in the serial port register h06 (see Table 5), and produces
LOCK, LOCK and UNLOCK status flags, available through
both the STAT output and serial port register h00. LOCK
is the logical inverse of LOCK.
The user sets the phase difference lock window time tLWW
for a valid LOCK condition with the LKWIN bit found in
register h06. Table 4 contains recommended settings for
different fPFD frequencies. See the Applications Information section for examples.
Table 4. LKWIN Programming
LKWIN
tLWW
fPFD
0
3ns
> 5MHz
1
10ns
≤ 5MHz
The PFD phase difference must be less than tLWW for the
COUNTS number of successive counts before the lock
indicator asserts the LOCK flag. The LKCT[1:0] bits are
used to set COUNTS depending upon the application.
Rev 0
18
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LTC6952
OPERATION
Larger values of COUNTS lead to more accurate and stable
lock indications at the expense of longer lock indication
times. Set LKCT[1:0] = 0 to disable the lock indicator. See
Table 5 for LKCT[1:0] programming and the Applications
Information section for examples.
VCP+
UP
CPUP
CPMID
VCP+/2
ICP
CP
Table 5. LKCT[1:0] Programming
LKCT[1:0]
COUNTS
0
Lock Indicator Disabled
1
32
2
256
3
2048
DOWN
CPDN
6952 F05
Figure 5. Simplified Charge Pump Schematic
When the PFD phase difference is greater than tLWW, the
lock indicator immediately asserts the UNLOCK status
flag and clears the LOCK flag, indicating an out-of-lock
condition. The UNLOCK flag is immediately de-asserted
when the phase difference is less than tLWW. See
Figure 4 below for more details.
Table 6 for programming specifics and the Applications
Information section for loop filter examples.
Table 6. CP[4:0] Programming
CP[4:0]
ICP
0
423µA
1
500µA
2
592µA
3
700µA
4
842µA
5
1.00mA
6
1.18mA
7
1.40mA
8
1.68mA
+tLWW
PHASE
DIFFERENCE
AT PFD
0
–tLWW
9
2.00mA
10
2.36mA
11
2.81mA
12
3.37mA
13
4.00mA
14
4.72mA
15
5.61mA
16
6.73mA
17
8.02mA
18
9.43mA
19
11.20mA
20 to 31
Invalid
UNLOCK FLAG
LOCK FLAG
t = COUNTS/fPFD
LOCK FLAG
6952 F04
Figure 4. UNLOCK, LOCK, and LOCK Timing
CHARGE PUMP
The charge pump, controlled by the PFD, forces sink
(DOWN) or source (UP) current pulses onto the CP pin,
which should be connected to an appropriate loop filter.
See Figure 5 for a simplified schematic of the charge pump.
The output current magnitude ICP may be set from 423µA to
11.2mA using the CP[4:0] bits found in serial port register
h0A. A larger ICP can result in lower in-band noise due to
the lower impedance of the loop filter components. See
Charge Pump Functions
The charge pump contains additional features to aid in
system startup. See Table 7 for a summary.
Rev 0
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19
LTC6952
OPERATION
in ParallelSync applications (see the ParallelSync section).
The tradeoff for using the RAO mode is slightly degraded
PLL in-band noise ( 2.25GHz
Maximum ADELx
63
31
16
12
8
0
Rev 0
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21
LTC6952
OPERATION
Figure 7 shows the approximate analog delay time (tADELx)
vs ADELx and output frequency. Note that the y-axis is
logarithmic scale, and that analog delay is zero for ADEL = 0.
See the Applications Information section for a more comprehensive method of calculating expected analog delay.
tADELx, LOG SCALE (ps)
1280
condition (PDx = 1) as shown in Table 10. See Figure 8
for circuit details.
VOUT+
33Ω
50Ω
< 300MHz
500MHz
750MHz
1GHz
1.5GHz
1.75GHz
2.25GHz
640
50Ω
OUTx+
OUTx–
6952 F08
320
160
80
Figure 8. Simplified CML Interface Schematic (All OUTx)
0
10
20
30
40
ADEL CODE
50
60
6952 F07
Figure 7. Analog Delay vs ADEL Code and Output Frequency
Use caution when using analog delay on device clocks
as this will degrade jitter. Digital delay should be used
whenever possible since it does not impact performance.
The maximum value of analog delay will never need to be
more than half of a VCO input period.
Analog delays are always enabled regardless of the value
of the SRQENx bits, and they take effect immediately upon
a write to the ADELx registers. However, changes in ADEL
can cause the output to glitch temporarily, especially
switching between ADEL=0 and ADEL≠0. See the Applications Information section for details on the use of the
analog delay settings. The LTC6952Wizard may be used
for ADEL calculation and visualization.
CML OUTPUT BUFFERS (OUT0 TO OUT10)
All of the outputs are very low noise, low skew 2.5V CML
buffers. Each output can be either AC or DC coupled, and
terminated with 100Ω differentially. If a single-ended output
is desired, each side of the CML output can be individually
AC coupled and terminated with 50Ω. The OINVx bits can
selectively invert the sense of each output to facilitate board
routing without having to cross matched length traces.
OINVx also determines the state of the output in a muted
OUTPUT SYNCHRONIZATION AND SYSREF GENERATION
The LTC6952 has circuitry to allow all outputs to be
synchronized into known phase alignments in multiple
ways to suit different applications using the EZSync and
ParallelSync Multichip Clock Edge Synchronization protocols. Synchronization can be between any combination
of outputs on the same chip (EZSync Standalone), across
multiple cascaded follower chips (EZSync Multi-Chip), or
even across multiple parallel chips on the same reference
domain (ParallelSync). Once the outputs are at the correct
frequency and synchronized, the LTC6952 also has the
ability to produce free-running, gated, or finitely pulsed
SYSREF signals as indicated by the JESD204B/C subclass 1
specification.
EZS_SRQ Input Buffer
Both synchronization and SYSREF requests are achieved
by either a software signal (bit SSRQ in register h0B) or
a voltage signal on the EZS_SRQ± pins. The voltage on
these pins may be any differential signal within the specifications in the Electrical Characteristics, or alternatively
a CMOS signal on EZS_SRQ+ while EZS_SRQ– is tied to
GND. A simplified schematic of the EZS_SRQ input is
shown in Figure 9. When using the SSRQ bit, the state of
the EZS_SRQ± pins must be a logic “0”, easily achieved
by setting both EZS_SRQ± pins to GND. Likewise, when
using the EZS_SRQ± pins, bit SSRQ must be set to “0”.
Table 12 shows the use of the EZS_SRQ± pins and SSRQ
bit vs the SRQMD and PARSYNC bits. SSRQ bit control
Rev 0
22
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LTC6952
OPERATION
is disabled when PARSYNC is “1” due to setup and hold
time requirements to the REF input.
BIAS
CMOS
VREF+
2.1V
7kΩ
+
–
28kΩ
28kΩ
0.8V
EZS_SRQ–
FILTR
CMOS
EZS_SRQ+
CMOS
CMOS
CMOS
6952 F09
Figure 9. Simplified EZS_SRQ Interface Schematic
Note that synchronization MUST be performed before a
SYSREF request. The synchronization must be repeated
only if the divider setting is changed, or if the divider is
powered down.
Table 12. Purpose of EZS_SRQ± pins and SSRQ bit
SRQMD
0
1
EZS_SRQ PINS
SSRQ BIT
PARSYNC=0
PARSYNC=1 PARSYNC=0
PARSYNC=1
Synchronization Synchronization Synchronization Disabled
Request
Request
Request
(SYNC)
(SYNC)
(SYNC)
SYSREF
Request
(SYSREQ)
SYSREF
Request
(SYSREQ)
SYSREF
Request
(SYSREQ)
Disabled
To enable synchronization on the LTC6952, the SRQMD
bit in register h0B must be set to “0”. Synchronization
begins either with the EZS_SRQ input driven to a high
state or by writing “1” to the SSRQ bit (only if PARSYNC
= 0). For any output with its SRQENx bit set to “1”, the
output divider will stop running and return to a logic “0”
state after an internal timing delay of greater than 100μs.
The EZS_SRQ input state or SSRQ bit must remain high
for a minimum of 1ms.
Additionally, if bit PARSYNC is set to “1” when the EZS_SRQ
input is driven high, the R divider for R ≥ 2 is reset as
shown in Figure 2 and explained in the Reference Divider
(R) section. This synchronizes the internal PFD reference
inputs on multiple parallel LTC6952s.
When the EZS_SRQ input is driven back low, or “0” is written
to the SSRQ bit (only if PARSYNC = 0), the synchronized
internal dividers will start after an initial latency dependent
on the settings of bits PDPLL and PARSYNC , as shown
in Table 13 and Table 14. Outputs with DDELx≠0 will be
delayed by an extra DDELx/2 VCO cycles. The behavior of
each output will be defined individually by the output’s corresponding SRQENx and MODEx bits also shown in Table
13 and Table 14. All dividers with the same DDELx delay
setting will have their output rising edge occur within the
skew times as defined in the Electrical Characteristics table.
The range of each delay is 0 to 4095 VCO half cycles and is
independent of the divide ratio setting of each divider. See
the Applications Information section for synchronization
programming examples. Additionally, the LTC6952Wizard
may be used to visualize these timing relationships.
SYSREF Generation Overview
Synchronization Overview
The goal of synchronization is to align all output dividers
on single or multiple LTC6952s (or other EZSync or ParallelSync Analog Devices clock parts) into a known phase
relationship. At initial power-up, after a power-on reset
(POR), or any time the output divide values are changed,
the outputs will not be synchronized. Any changes to the
output digital delays (DDELx) will not be reflected until after
synchronization. Although the outputs will be at the correct
frequency without synchronization, the phases will have an
unknown relationship until a synchronization event occurs.
The JESD204B/C subclass 1 specification describes a
method to align multiple data converter devices (ADCs or
DACs) in time and provide repeatable and programmable
latency across the serial link with a logic device (FPGA).
The Local Multi-Frame Clocks (LMFC) and internal clock
dividers on all devices in the system are synchronized by a
pulse (or pulse train) named SYSREF. Care must be taken
to make sure the SYSREF signal remains synchronized to
the ADC, DAC, and FPGA clocks and meets setup and hold
timing as specified by the devices.
Rev 0
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23
LTC6952
OPERATION
Table 13. Synchronization (SRQMD = 0) Output Behavior vs Device Settings for with PLL Enabled (PDPLL = 0)
SRQENx
PARSYNC
0
N/A
MODEx
0
1, 2, or 3
Internal Divider
Sync to Other
Dividers
Internal Divider
Sync to RDIV
Internal Divider Start Latency
from SYNC Signal Falling
Edge (DDELx = 0)
No
No
N/A
0
0
1
1
1 or 3
Yes
Yes
~45µs + R/fREF + 8/fVCO
Output Behavior
Free Running
Muted
Mute on SYNC High, Run on
SYNC Low
Muted
2
SYNC Signal Pass Through
0
Mute on SYNC High, Run on
SYNC Low
1 or 3
Yes
Yes
(x + R)/fREF + 8/fVCO*
2
Muted
SYNC Signal Pass Through
* Latency depends on the duration of the SYNC pulse, specifically x = floor (tSYNC × fREF - 1) mod R. All outputs will be synchronized correctly regardless of x
Table 14. Synchronization (SRQMD = 0) Output Behavior vs Device Settings for with PLL Disabled (PDPLL = 1)
SRQENx
PARSYNC
0
N/A
MODEx
0
1, 2, or 3
Internal Divider
Sync to Other
Dividers
Internal Divider
Sync to RDIV
Internal Divider Start Latency
from SYNC Signal Falling
Edge (DDELx = 0)
No
No
N/A
0
0
1
1
1 or 3
Yes
No
~45µs + 7/fVCO
Output Behavior
Free Running
Muted
Mute on SYNC High, Run on
SYNC Low
Muted
2
SYNC Signal Pass Through
0
Mute on SYNC High, Run on
SYNC Low
1 or 3
Yes
No
7/fVCO
2
Muted
SYNC Signal Pass Through
The LTC6952 supports three different methods of SYSREF
generation as described in the JESD204B/C specification:
• Free Running
• Gated On/Off by a SYSREF Request Signal
• One, Two, Four, or Eight SYSREF Pulses After the
Rising Edge of a SYSREF Request Signal
These modes are defined by each output’s individually programmable MODEx bits. In order to generate SYSREF pulses,
bit SRQMD must be set to “1” as shown in Table 12, and MPx
must be greater than 0. SYSREF requests (SYSREQ) are
applied on the EZS_SRQ± pins or by setting the SSRQ bit to
“1” (unless PARSYNC = 1). Table 15 describes the output
behavior in SYSREF generation mode. Bits SYSCT[1:0]
can be found in register h0B.
Note that synchronization MUST be completed prior to
SYSREF generation as described in the Synchronization
Overview.
Rev 0
24
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LTC6952
OPERATION
generation: EZSync Multi-Chip and ParallelSync. The
synchronization configuration is determined by bits EZMD
and PARSYNC, and their required settings are shown in
Table 16. Table 17 introduces the important attributes
of these methods and their variants, with further details
provided in the following paragraphs. Note that this table
only refers to two-stage applications. Many more outputs
are possible by using more stages.
Table 15. Output Behavior in SYSREF Generation Mode
(SRQMD = 1)
SRQENx
MODEx
0
0
Output Behavior
Free Run, Ignore SYSREQ
1, 2, or 3 Muted, Ignore SYSREQ
1
0
Free Run, Ignore SYSREQ
1
Gated pulses: Run on SYSREQ High, Mute on
Low
2
SYSREQ Pass Through
3
Output 2SYSCT Pulses After SYSREQ Goes High
Table 16. Settings of EZMD and PARSYNC for Different Synchronization Topologies
EZSync Multi-Chip
EZSync
(see Figure 11 and Figure 12)
Control
Standalone
Bit
(see Figure 10) CONTROLLER FOLLOWER
PARSYNC
0
0
0
EZMD
0
0
1
Multi-Chip Synchronization and SYSREF Generation
Using one LTC6952 in EZSync Standalone configuration
(Figure 10), up to eleven clock signals or SYSREFs can
be generated and synchronized. For applications requiring
more than eleven clock outputs, the LTC6952 supports
two methods of multi-chip synchronization and SYSREF
ParallelSync
Multi-Chip
(see Figure 13
and Figure 14)
1
0
Table 17. Parameters and Limitations of EZSync and ParallelSync (Two Stages Only)
EZSync Multi-Chip
RMS Jittera
Pin Controlled Requests
(see Figure 11)
ParallelSync Multi-Chip
Request Passthough
(see Figure 12)
EZSync
Standalone
(see Figure 10)
Controller
Follower
Controller
Follower
~75fs
~75fs
~105fs
~75fs
~105fs
General
LTC6952
Reference
Reference
Distribution
Distribution
(see Figure 13) (see Figure 14)
~75fs
~75fs
Possible Number of Followers (Nfol)
-
1 to 11
1 to 5
-
-
Possible Number of Parallel Parts
(Npar)
-
-
-
Unlimitedb
1 to 5
11 · Npar
11 · Npar
Unlimitedb
55
~tSKEWd
Total Number of Outputs
Maximum Number of Outputs
11
11 - Nfol
11 · Nfol
11
11 – 2Nfol
121
11 · Nfol
56
Maximum Skew
tSKEW
~ tSKEW + tPD
~ tSKEW + tPD
~tSKEWd
SYNC Timing
Easy
Easy
Easy
Moderate
Easy
SYSREF Request Timing
Easy
Moderate
Easy
Moderate
Easy
Number of External VCOs
Software SYNC/SYSREF Request?
c
c
1
1
1
Npar
Npar
Yes
No
Yes
No
Yes
a Assumes ADC SNR equivalent integrated PLL/VCO RMS jitter contribution of 27fs and additive jitter for distribution-only parts of 70fs.
b The only limitation is the ability to distribute the reference accurately.
c Assumes worst case skew between controller and follower outputs. Dependent on propagation delay of follower and skew of controller-to-follower routing.
d Dependent on skew of reference distribution parts, reference routing, and individual part-to-part skew.
Rev 0
For more information www.analog.com
25
LTC6952
OPERATION
EZSync Multi-Chip
When using EZSync Multi-Chip, compatible devices are
cascaded together, with the clock output of a CONTROLLER
device driving the VCO inputs of one to eleven FOLLOWER
devices as shown in Figure 11. The EZSync protocol allows for simple synchronization of all devices due to loose
timing constraints on the SYNC signal. When used in a
JESD204B/C application, SYSREF requests may need to
be retimed to a free running SYSREF output to assure all
FOLLOWERS start and stop their SYSREF signals at the
same time. It is recommended that LTC6953 be used as
any FOLLOWER device. However, LTC6952 can be used as
a FOLLOWER if necessary by disabling its PLL (PDPLL=1).
LF(s)
OUT0–
VCO±
ALL CONTROLLER TO FOLLOWER CONNECTIONS MUST BE DC COUPLED
CONTROLLER
LF(s)
100Ω
VCO
OUT1–
REF±
100Ω
OUT2+
REF
SYNC OR
SYSREF
REQUEST
OUT2–
100Ω
REF
CMOS
BUFFER
100Ω
OUT4–
EZS_SRQ–
OUT5–
EZS_SRQ–
100Ω
OUT6–
OUT8–
160Ω
OUT9–
160Ω
OUT10–
± 11 OUTPUTS
#6 OUTx
LTC6953 or LTC6952
VCO–
EZS_SRQ+
VCO+
160Ω
± 11 OUTPUTS
#7 OUTx
LTC6953 or LTC6952
VCO–
EZS_SRQ+
VCO+
160Ω
± 11 OUTPUTS
#8 OUTx
LTC6953 or LTC6952
VCO–
EZS_SRQ+
VCO+
± 11 OUTPUTS
#9 OUTx
LTC6953 or LTC6952
VCO–
EZS_SRQ+
VCO+
160Ω
100Ω
FOLLOWER-SYNCHRONOUS
OUTPUT
100Ω
FOLLOWER-SYNCHRONOUS
OUTPUT
OUT10+
100Ω
± 11 OUTPUTS
#5 OUTx
LTC6953 or LTC6952
VCO–
EZS_SRQ+
VCO+
OUT9+
100Ω
± 11 OUTPUTS
#4 OUTx
LTC6953 or LTC6952
VCO–
EZS_SRQ+
VCO+
OUT8+
100Ω
OUT10+
OUT10–
160Ω
LTC6952
EZSync
OUT7+
160Ω
CONTROLLER
OUT7–
100Ω
± 11 OUTPUTS
#3 OUTx
LTC6953 or LTC6952
VCO–
EZS_SRQ+
VCO+
OUT6+
OUT9+
OUT9–
160Ω
OUT5+
OUT5–
100Ω
OUT8+
OUT8–
OUT4–
± 11 OUTPUTS
#2 OUTx
LTC6953 or LTC6952
VCO–
EZS_SRQ+
VCO+
OUT4+
EZS_SRQ+
100Ω
OUT7+
OUT7–
OUT3–
CMOS
BUFFER
OUT6+
OUT6–
160Ω
OUT3+
OUT5+
LTC6952
OUT1–
OUT2–
SYNC or
SYSREF
REQUEST
OUT4+
EZS_SRQ+
OUT0–
± 11 OUTPUTS
#1 OUTx
LTC6953 or LTC6952
VCO–
EZS_SRQ+
VCO+
OUT2+
OUT3+
OUT3–
FOLLOWERS
OUT0+
OUT1+
REF±
OUT1+
VCO
CP
VCO±
OUT0+
CP
To simplify both SYNC and/or SYSREF requests down to
a simple software write to the CONTROLLER’s SSRQ bit,
the devices may be connected as shown in Figure 12,
where an additional CONTROLLER output drives each
FOLLOWER’s EZS_SRQ pins (only available for LTC6952
or LTC6953 FOLLOWERs). This request passthrough
configuration reduces the system complexity at the cost
of fewer possible FOLLOWERs (a maximum of 5). Note
that MPx for the CONTROLLER’s passthrough output must
be set greater than 0.
6952 F10
6952 F11
Figure 10. EZSync Standalone
Figure 11. EZSync Multi-Chip Synchronization
(Nine Followers Shown) Max Eleven Possible
Rev 0
26
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LTC6952
OPERATION
ALL CONTROLLER TO FOLLOWER
CONNECTIONS MUST BE DC COUPLED
CONTROLLER
LF(s)
CP
VCO±
VCO
OUT0+
OUT0–
VCO+
160Ω
OUT1+
REF±
REF
OUT1–
100Ω
OUT2+
SYNC OR
SYSREF
REQUEST:
TOGGLE PIN
OR WRITE
SSRQ BIT
OUT2–
160Ω
EZS_SRQ+
EZS_SRQ–
100Ω
160Ω
100Ω
160Ω
OUT8+
100Ω
100Ω
REF±
LTC6952
CP
VCO
11 OUTPUTS
LF(s)
VCO±
OUTx±
#3
REF±
CP
VCO
11 OUTPUTS
LF(s)
VCO±
OUTx±
EZS_SRQ±
OUTx±
VCO
11 OUTPUTS
11 OUTPUTS
LTC6952
VCO–
EZS_SRQ
DISTRIBUTION
EZS_SRQ–
OUTx±
11 OUTPUTS
EZS_SRQ MAY BE
SINGLE-ENDED OR DIFFERENTIAL
#N
CP
LF(s)
VCO±
OUTx±
VCO
11 OUTPUTS
6952 F13
Figure 13. ParallelSync Multi-Chip Synchronization
VCO–
#4
LTC6953 or LTC6952
EZS_SRQ+
EZS_SRQ–
OUTx±
REF±
EZS_SRQ±
11 OUTPUTS
VCO–
EZS_SRQ–
OUT10+
OUT10–
#2
11 OUTPUTS
#5
LTC6953 or LTC6952
EZS_SRQ+
OUT9+
OUT9–
OUTx±
LF(s)
EZS_SRQ–
VCO+
160Ω
OUTx±
EZS_SRQ±
LTC6952
CP
VCO±
EZS_SRQ±
VCO–
VCO+
LTC6952
EZSYNC
OUT7+
100Ω
CONTROLLER
OUT7–
OUT8–
EZS_SRQ–
#3
LTC6953 or LTC6952
EZS_SRQ+
OUT6+
OUT6–
REFERENCE
DISTRIBUTION
REFERENCE MAY BE
SINGLE-ENDED OR DIFFERENTIAL
EZS_SRQ+
VCO+
OUT5+
OUT5–
11 OUTPUTS
#1
REF±
#2
LTC6953 or LTC6952
EZS_SRQ+
OUT4+
OUT4–
OUTx±
VCO– #1
LTC6953 or LTC6952
VCO+
OUT3+
OUT3–
LTC6952
FOLLOWERS
For all cases of EZSync synchronization, the CONTROLLER must be programmed to output seven pre-pulses to
each FOLLOWER before the FOLLOWER outputs or any
follower-synchronous CONTROLLER outputs start clocking. Additionally, a CONTROLLER must have bit EZMD set
to “0” and a FOLLOWER must have both EZMD and PDPLL
set to “1”. See the Applications Information section for a
programming example. Additionally, the LTC6952Wizard
provides programming guidance.
FOLLOWER-SYNCHRONOUS OUTPUT
ParallelSync
6952 F12
Figure 12. EZSync Multi-Chip Synchronization
with Request Passthrough
In a ParallelSync application, multiple ParallelSync compatible devices are connected in parallel with a shared distributed REF signal as shown in Figure 13. The advantage of
parallel connection is improved jitter performance, as the
clock signals do not propagate through two or more cascaded devices. However, synchronization requires tighter
control of the SYNC and SYSREF request (SRQ) signals’
timing because of the need to have the SYNC/SRQ edges
fall within the same REF cycle for all connected devices.
See Reference Signal and EZS_SRQ Timing for PARSYNC
Mode in the Applications Information section for the timing
requirements of EZS_SRQ to REF in this mode.
Rev 0
For more information www.analog.com
27
LTC6952
OPERATION
The SYNC/SRQ timing for ParallelSync can be simplified
to a single software bit write by using an LTC6953 (or an
LTC6952 configured as a reference clean-up loop) as the
reference and EZS_SRQ distribution block, as shown in
Figure 14. In this application, the EZS_SRQ outputs of the
reference distribution part should be set to transition on the
falling edge of its corresponding reference clock output.
To achieve this, first synchronize the reference distribution
part using the settings given in Table 18, where DDELREF
can be any valid DDEL value.
Just before sending a SYNC or SYSREF request to the parallel parts, set the reference distribution part’s SRQMD bit
to “1”. This will automatically retime the passed-through
requests to the reference clocks. After the request is done,
set the SRQMD bit back to “0” to save supply current
from the reference distribution part. See the Applications
Information section for a programming example.
Depending on the user’s system requirements, many
simplifications or additions can be made for multiple chip
synchronization. For example, the above applications only
assume a maximum of two stages, even though more
stages can be added to increase the number of outputs.
However, these applications are beyond the scope of this
data sheet. Please contact the factory.
EZS_SRQ CONNECTIONS
MUST BE DC COUPLED
OUT0+
REF IN
VCO±
OUT0–
100Ω
OUT1+
SYNC OR
SYSREF
REQUEST:
TOGGLE PIN
OR WRITE
SSRQ BIT
OUT1–
100Ω
OUT2+
OUT2–
OUT3–
EZS_SRQ+
REF CLK
Divide
REF CLK
DDEL
EZS_SRQ
Divide
EZS_SRQ
DDEL
1
2
DDELREF
DDELREF
2
2
DDELREF+1
DDELREF+2
3
DDELREF
3
DDELREF+3
4
DDELREF
4
DDELREF+4
OUT5–
REF Divide >4
DDELREF
=REF Divide
DDELREF
OUT6+
EZS_SRQ–
100Ω
100Ω
OUT6–
LTC6953 or
LTC6952
OUT7+
REFERENCE
100Ω
DISTRIBUTION
OUT7–
OUT8+
REF –
EZS_SRQ –
REF –
LTC6952
EZS_SRQ+
EZS_SRQ –
REF+
100Ω
REF –
LTC6952
EZS_SRQ+
OUT9+
OUT9–
EZS_SRQ –
REF+
100Ω
To determine the best configuration for a given application,
the flowchart in Figure 15 can be used. This flowchart
uses the parameters from Table 17 to guide the user to
the most suitable configuration.
REF –
LTC6952
EZS_SRQ+
OUT5+
OUT8–
EZS_SRQ–
REF+
100Ω
100Ω
EZS_SRQ –
LF(s)
VCO±
VCO
#1
OUTx±
CP
11 OUTPUTS
LF(s)
VCO±
VCO
#2
OUTx±
CP
11 OUTPUTS
LF(s)
VCO±
VCO
#3
OUTx±
CP
11 OUTPUTS
LF(s)
VCO±
VCO
#4
OUTx±
CP
11 OUTPUTS
LF(s)
VCO±
VCO
#5
OUTx±
11 OUTPUTS
6952 F14
OUT10+
OUT10–
CP
EZS_SRQ+
LTC6952
EZS_SRQ+
OUT4+
OUT4–
REF –
LTC6952
REF+
100Ω
OUT3+
Table 18. Reference Distribution Divider and DDEL Settings for
ParallelSync
Part-to-part skew in a ParallelSync application can be
minimized by setting the RAO bit in register h06 to “1”.
RAO stands for “reference aligned output”, and it aligns
internal delays such that the output rising edge will always
occur at an exact integer number of VCO clock cycles from
the incoming reference signal. The trade-off for using the
RAO mode is slightly degraded PLL in-band noise (
