LTC6953IUKG#PBF

LTC6953 Ultralow Jitter, 4.5GHz Clock Distributor with 11 Outputs and JESD204B/JESD204C Support FEATURES DESCRIPTION JESD204B/C, Subclass 1 SYSREF Signal Generation n Additive Output Jitter < 6fs RMS (Integration BW = 12kHz to 20MHz, f = 4.5GHz) n Additive Output Jitter 65fs RMS (ADC SNR Method) n EZSync™, ParallelSync™ Multichip Synchronization n Eleven Independent, Low Noise Outputs with Programmable Coarse Digital and Fine Analog Delays n Flexible Outputs Can Serve as Either a Device Clock or SYSREF Signal n LTC6952Wizard Software Design Tool Support n –40°C to 125°C Operating Junction Temperature Range The LTC®6953 is a high performance, ultralow jitter, JESD204B/C clock distribution IC. The LTC6953’s eleven outputs can be configured as up to five JESD204B/C subclass 1 device clock/SYSREF pairs plus one general purpose output, or simply eleven general purpose clock outputs for non-JESD204B/C applications. Each output has its own individually programmable frequency divider and output driver. All outputs can also be synchronized and set to precise phase alignment using individual coarse half cycle digital delays and fine analog time delays. n For applications requiring more than eleven total outputs, multiple LTC6953s can be connected together with LTC6952s and LTC6955s using the EZSync or ParallelSync synchronization protocols. APPLICATIONS High Performance Data Converter Clocking Wireless Infrastructure n Test and Measurement n All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. patents, including 8319551 and 8819472. n TYPICAL APPLICATION Cumulative Phase Noise, LTC6946 Driving LTC6953 Low Cost, Eleven Output JESD204B/C Solution 3.3V VVCO+ VCP+ VREF0+ VREF+ VD+ VRF+ 4.7nF 68nH CMA 100pF CMB OUT2± 15.625MHz ADC SYSREF OUT3± 500MHz ADC CLOCK IN– OUT4± 15.625MHz FPGA SYSREF OUT5± 125MHz FPGA CLOCK TUNE LTC6953 1µF + REF 49.9Ω 1µF SCLK REF – SPI BUS CS 100Ω 1µF CS LTC6946-2 SCLK SPI BUS CRYSTEK CCHD-575-25-100 100MHz REF OSC 1µF BB MUTE STAT REFO OUT7± 15.625MHz DAC SYSREF OUT8± 4.5GHz DAC CLOCK OUT9± 15.625MHz DAC SYSREF OUT10± 4.5GHz DAC CLOCK SDO STAT SDI SDO OUT6± SDI 3.3V REGISTER VALUES: LTC6952Wizard FILE: LTC6946 LTC6953 EZSync PLLWizard™ FILE: LTC6946 LTC6953 EZSync EZS_SRQ+ EZS_SRQ– 4.5GHz 500MHz –110 IN+ 160Ω RF – CMC VOUT + OUT0± 15.625MHz ADC SYSREF OUT1± 500MHz ADC CLOCK 68nH RF+ TB 2.2µF VD+ 100pF CP –100 3.3V VIN+ VREF+ OUTPUT TERMINATION DETAIL 0.1µF PHASE NOISE (dBc/Hz) 30.9Ω 3.3V 15Ω 5V 57nF –120 –130 –140 –150 TOTAL COMBINED RMS JITTER = 150fs LTC6946 RMS JITTER = 135fs LTC6963 RMS JITTER = 65fs EQUIVALENT ADC SNR METHOD –160 –170 1k 10k 100k 1M OFFSET FREQUENCY (Hz) 10M 40M 6953 TAO1b OUTx+ 100Ω 0.1µF OUTx– TO SYNC OUTPUTS: TOGGLE LTC6953 SSYNC REGISTER BIT 6953 TA01a Rev. A Document Feedback For more information www.analog.com 1 LTC6953 TABLE OF CONTENTS Features............................................................................................................................. 1 Applications........................................................................................................................ 1 Typical Application ................................................................................................................ 1 Description......................................................................................................................... 1 Absolute Maximum Ratings...................................................................................................... 4 Order Information.................................................................................................................. 4 Electrical Characteristics......................................................................................................... 4 Pin Configuration.................................................................................................................. 4 Typical Performance Characteristics........................................................................................... 8 Pin Functions......................................................................................................................11 Block Diagram.....................................................................................................................12 Timing Diagrams.................................................................................................................13 Operation..........................................................................................................................14 INPUT BUFFER...................................................................................................................................................... 14 Input Peak Detector........................................................................................................................................... 14 OUTPUT DIVIDERS (M0 TO M10)......................................................................................................................... 14 DIGITAL OUTPUT DELAYS (DDEL0 TO DDEL10)................................................................................................... 15 ANALOG OUTPUT DELAYS (ADEL0 TO ADEL10)................................................................................................... 15 CML OUTPUT BUFFERS (OUT0 TO OUT10)........................................................................................................... 15 OUTPUT SYNCHRONIZATION AND SYSREF GENERATION................................................................................... 16 EZS_SRQ Input Buffer....................................................................................................................................... 16 Synchronization Overview................................................................................................................................. 16 SYSREF Generation Overview ........................................................................................................................... 17 Multichip Synchronization and SYSREF Generation.......................................................................................... 17 EZSync Multichip............................................................................................................................................... 19 ParallelSync....................................................................................................................................................... 20 Power Savings in SYSREF Generation Mode..................................................................................................... 21 SERIAL PORT........................................................................................................................................................ 23 Communication Sequence................................................................................................................................. 23 Single Byte Transfers......................................................................................................................................... 23 Multiple Byte Transfers...................................................................................................................................... 24 Multidrop Configuration.................................................................................................................................... 25 Serial Port Registers.......................................................................................................................................... 25 STAT Output...................................................................................................................................................... 29 Block Power-Down Control................................................................................................................................ 29 Applications Information........................................................................................................30 INTRODUCTION..................................................................................................................................................... 30 OUTPUT FREQUENCY............................................................................................................................................ 30 DIGITAL AND ANALOG OUTPUT DELAYS.............................................................................................................. 30 INPUT BUFFER...................................................................................................................................................... 31 EZS_SRQ INPUT.................................................................................................................................................... 32 JESD204B/C DESIGN EXAMPLE USING EZSync STANDALONE............................................................................ 33 Input Assumptions............................................................................................................................................ 33 Design Procedure.............................................................................................................................................. 33 2 Rev. A For more information www.analog.com LTC6953 TABLE OF CONTENTS Determining Output Modes............................................................................................................................... 34 Determining Output Divider Values.................................................................................................................... 34 Determining Output Digital Delay Values........................................................................................................... 34 Status Register Programming........................................................................................................................... 35 Power and FILT Register Programming............................................................................................................. 35 Output Power-Down Programming................................................................................................................... 35 SYNC and SYSREF Global Modes Programming............................................................................................... 35 Output Divider, Delay and Function Programming............................................................................................. 36 Synchronization................................................................................................................................................. 36 Putting the IC Into a Lower Power Mode (Optional).......................................................................................... 36 Performing a SYSREF Request.......................................................................................................................... 36 JESD204B/C DESIGN EXAMPLE USING EZSync MULTICHIP................................................................................ 38 Input Assumptions............................................................................................................................................ 39 Design Procedure.............................................................................................................................................. 39 Determining Output Modes............................................................................................................................... 39 Determining Output Divider Values.................................................................................................................... 39 Determining Output Digital Delay Values........................................................................................................... 40 Status Register Programming........................................................................................................................... 41 Power and FILT Register Programming............................................................................................................. 41 Output Power-Down Programming................................................................................................................... 42 SYNC and SYSREF Global Modes Programming............................................................................................... 42 Output Divider, Delay and Function Programming............................................................................................. 42 Synchronization................................................................................................................................................. 43 Putting the ICs Into a Lower Power Mode......................................................................................................... 43 Performing a SYSREF Request.......................................................................................................................... 43 JESD204B/C DESIGN EXAMPLE USING ParallelSync............................................................................................ 45 SUPPLY BYPASSING AND PCB LAYOUT GUIDELINES.......................................................................................... 45 ADC CLOCKING AND JITTER REQUIREMENTS..................................................................................................... 47 MEASURING CLOCK JITTER INDIRECTLY USING ADC SNR.................................................................................. 49 ADC SAMPLE CLOCK INPUT DRIVE REQUIREMENTS.......................................................................................... 49 TRANSMISSION LINES AND TERMINATION......................................................................................................... 50 USING THE LTC6953 TO DRIVE DEVICE CLOCK INPUTS...................................................................................... 50 USING THE LTC6953 TO DRIVE DC-COUPLED SYSREF INPUTS ......................................................................... 50 DC-Coupled SYSREFs (MODEx = 0, 1 or 3)....................................................................................................... 50 USING THE LTC6953 TO DRIVE AC-COUPLED SYSREF INPUTS IN CONTINUOUS OR GATED MODE.................. 51 Continuous or Gated SYSREFs (MODEx = 0 or 1)............................................................................................. 51 USING THE LTC6953 TO DRIVE AC-COUPLED SYSREF INPUTS IN PULSED MODE............................................ 51 Pulsed SYSREFs (MODEx = 3).......................................................................................................................... 52 MEASURING DIFFERENTIAL SPURIOUS SIGNALS USING SINGLE-ENDED TEST EQUIPMENT............................ 52 Typical Applications..............................................................................................................53 Package Description.............................................................................................................56 Revision History..................................................................................................................57 Typical Application...............................................................................................................58 Related Parts......................................................................................................................58 Rev. A For more information www.analog.com 3 LTC6953 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) GND NC NC VREF+ NC NC EZS_SRQ+ EZS_SRQ– STAT SCLK SDO TOP VIEW SDI Supply Voltages V+ (VREF+, VIN+, VD+, VOUT+) to GND.....................3.6V Voltage on All Pins.....................GND – 0.3V to V+ + 0.3V Current Into OUTx+, OUTx–, (x = 0 to 10)..............±25mA Operating Junction Temperature Range, TJ (Note 2) LTC6953I............................................ –40°C to 125°C Junction Temperature, TJMAX................................. 130°C Storage Temperature Range................... –65°C to 150°C 52 51 50 49 48 47 46 45 44 43 42 41 CS 1 40 SD VD+ 2 39 VIN+ OUT10– 3 38 IN– OUT10+ 4 37 IN+ + 5 36 NC VOUT 35 VOUT+ OUT9– 6 OUT9+ 7 VOUT + 34 OUT0+ 8 OUT8– 9 32 VOUT+ OUT8+ 10 31 OUT1+ VOUT 11 30 OUT1– OUT7– 12 29 VOUT+ OUT7+ 13 28 OUT2+ VOUT 14 27 OUT2– 53 GND 33 OUT0– + + VOUT+ OUT3+ OUT3– VOUT+ OUT4+ OUT4– VOUT + OUT5+ OUT5– VOUT+ OUT6+ OUT6– 15 16 17 18 19 20 21 22 23 24 25 26 UKG PACKAGE 52-LEAD (7mm × 8mm) PLASTIC QFN TJMAX = 130°C, θJC = 2°C/W, θJA = 31°C/W EXPOSED PAD (PIN 53) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC6953IUKG#PBF LTC6953IUKG#TRPBF 6953 52-Lead (7mm × 8mm) Plastic QFN –40°C to 125°C Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C. VREF+ = VD+ = VIN+ = VOUT+ = 3.3V unless otherwise specified (Note 2). All voltages are with respect to GND. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 4500 MHz 1.6 VP-P 2.7 V Input (IN+, IN–) fIN Frequency Range Input Signal Level l RZ = 50Ω, Single-Ended l 0.25 800mVP-P Differential Input l 1.6 Self-Bias Voltage Input Common Mode Voltage 4 0.8 2.05 V Input Duty Cycle 50 % Minimum Input Slew Rate 100 V/µs Rev. A For more information www.analog.com LTC6953 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C. VREF+ = VD+ = VIN+ = VOUT+ = 3.3V unless otherwise specified (Note 2). All voltages are with respect to GND. SYMBOL PARAMETER CONDITIONS Minimum Input Signal Detected (VCOOK = 1) PDVCOPK = 0, fIN = 10MHz, Single-Ended Sine Wave l MIN TYP MAX Maximum Input Signal Not Detected (VCOOK = 0) PDVCOPK = 0, fIN = 10MHz, Single-Ended Sine Wave l Input Resistance Differential 250 Ω Input Capacitance Differential 1.0 pF 250 UNITS mVP-P 40 mVP-P CMOS SYNC/SYSREF Request Input (EZS_SRQ+ Only) High-Level Input Voltage EZS_SRQ– Tied to GND l Low-Level Input Voltage EZS_SRQ– Tied to GND l Input Voltage Hysteresis EZS_SRQ– Tied to GND Input Current EZS_SRQ– Tied to GND 1.3 V 0.6 200 l V mV ±1 µA Differential SYNC/SYSREF Request Inputs (EZS_SRQ+ and EZS_SRQ–) Input Signal Level l 0.5 0.8 2.7 VP-P Self-Bias Voltage l 1.6 2.1 2.5 V 3.0 V Input Common Mode Voltage 800mVP-P Differential Input 1.5 Input Resistance Differential 53 kΩ Input Capacitance Differential 1 pF Digital Pin Specifications VIH High-Level Input Voltage CS, SDI, SCLK, SD l VIL Low-Level Input Voltage CS, SDI, SCLK, SD l VIHYS Input Voltage Hysteresis CS, SDI, SCLK, SD Input Current CS, SDI, SCLK, SD 1.55 V 0.8 250 l + – 400mV IOH High-Level Output Current SDO and STAT, VOH = VD l IOL Low-Level Output Current SDO and STAT, VOL = 400mV l SDO Hi-Z Current –3.3 2.0 mV ±1 µA –1.9 mA 3.4 mA ±1 l V µA Digital Timing Specifications tCKH SCLK High Time l 25 ns tCKL SCLK Low Time l 25 ns tCSS CS Setup Time l 10 ns tCSH CS High Time l 10 ns tCS SDI to SCLK Setup Time l 6 ns tCH SDI to SCLK Hold Time l 6 ns tDO SCLK to SDO Time To VIH/VIL/Hi-Z with 30pF Load 16 l ns EZS_SRQ Timing Specifications tSRQH EZS_SRQ High Time l 1 ms tSRQL EZS_SRQ Low Time l 1 ms EZS_SRQ Skew, Part to Part SRQMD = 0, PARSYNC = 0 10 µs Output Dividers (M0, M1, M2, M3, M4, M5, M6, M7, M8, M9 and M10) Mx Output Divider Range (x = 0 to 10) Mx = P × 2N, Where P = 1 to 32 All Integers, N = 0 to 7 DDELx Output Digital Delay (x = 0 to 10) ½ Input Cycles (Note 3) l 1 4096 counts l 0 4095 ½ cycles Rev. A For more information www.analog.com 5 LTC6953 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C. VREF+ = VD+ = VIN+ = VOUT+ = 3.3V unless otherwise specified (Note 2). All voltages are with respect to GND. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS tADELx Output Analog Delay (x = 0 to 10) ADELx = 0 0 ps ADELx = 1, fOUTx ≤ 300MHz 90 ps ADELx = 63, fOUTx ≤ 300MHz 1100 ps Output Analog Delay (x = 0 to 10), Step Size ADELx = 1 to 31, fOUTx ≤ 300MHz 11 ps ADELx = 32 to 63, fOUTx ≤ 300MHz 26 ps Output Analog Delay (x = 0 to 10) 300MHz ≤ fOUTx ≤ 2.25GHz Note 4 Maximum Output Frequency for Analog Delay Temperature Coefficient of Analog Delay ps 2.25 GHz ADELx = 1 to 31 l 0.06 %/°C ADELx = 32 to 63 l 0.06 %/°C CML Clock Outputs (OUT0+, OUT0–, OUT1+, OUT1–, OUT2+, OUT2–, OUT10+, OUT10–) fOUT VOD Output Frequency Differential Termination = 100Ω, MODEx = 0 (Clock Mode) l 0 4500 MHz Differential Termination = 100Ω, MODEx = 1, 2 or 3 (SYSREF Modes) l 0 150 MHz Output Differential Voltage Differential Termination = 100Ω l 320 550 mVPK Output Resistance Differential 420 100 Ω + – 1.0 V Output Common Mode Voltage Differential Termination = 100Ω tRISE Output Rise Time, 20% to 80% Differential Termination = 100Ω 50 ps tFALL Output Fall Time, 80% to 20% Differential Termination = 100Ω 50 ps Output Duty Cycle Differential Termination = 100Ω tPD Propagation Delay from IN± to OUT10 fIN = 4500MHz, Mx = 16 335 ps Propagation Delay from IN± to OUT10, Temperature Variation fIN = 4500MHz, Mx = 16 0.35 ps/°C Skew, All Outputs (Note 12) One Part, All Mx the Same, Even or 1 tSKEW VOUT l 45 ±10 l One Part, Any Mx Accross Multiple Parts; All Mx the Same, Even or 1; All TJ within ±10°C Additional Output Delay, Mx = Odd vs Mx = 1 or Even 50 55 ±25 ±30 ps ps ±50 l % ps Mx = 5, 11, 15, 17, 19, 25 or 27 4 ps Mx = 3, 7, 9, 13, 21, 23, 29 or 31 15 ps Power Supply Voltages VREF+ Supply Range l 3.15 3.3 3.45 V + Supply Range l 3.15 3.3 3.45 V VD + Supply Range l 3.15 3.3 3.45 V VIN+ Supply Range l 3.15 3.3 3.45 V 750 850 mA VOUT Power Supply Currents IDDOUT Sum VOUT+ Supply Currents All Outputs Enabled (Note 5) l Typical JESD204B/C Application (Note 6) 570 PDALL = 1 ICC – 3.3V Sum VD+, VREF+, VIN+ Supply Currents Digital Inputs at Supply Levels Digital Inputs at Supply Levels, PDALL = 1 6 mA 500 l 99 500 µA 120 mA µA Rev. A For more information www.analog.com LTC6953 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C. VREF+ = VD+ = VIN+ = VOUT+ = 3.3V unless otherwise specified (Note 2). All voltages are with respect to GND. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Supply Current Deltas from Total Chip Current PDx[1:0] = 2 (x = 0 to 10) per Output –34 mA PDx[1:0] = 3 (x = 0 to 10) per Output –68 mA EZS_SRQ± State = 1, SSRQ = 1 or SRQMD = 1 +175 mA Mx = Odd (Not Mx = 1) per Output +8.6 mA ADELx = 1 to 31 per Output +3.0 mA ADELx = 32 to 63 per Output +4.7 mA Additive Phase Noise, Jitter and Spurious (Note 7) Additive Phase Noise and RMS Jitter (fIN = 4.5GHz, fOUTx = 4.5GHz, Mx = 1) Additive Phase Noise and RMS Jitter (fIN = 4.5GHz, fOUTx = 2.25GHz, Mx = 2) Additive Phase Noise and RMS Jitter (fIN = 4.5GHz, fOUTx = 1.125GHz, Mx = 4) Additive Phase Noise and RMS Jitter (fIN = 3.2GHz, fOUTx = 200MHz, Mx = 16) Phase Noise Floor –154.3 RMS Jitter, 12kHz to 20MHz Integration BW 6 fsRMS RMS Jitter, ADC SNR Method (Note 9) 65 fsRMS –157.1 dBc/Hz Phase Noise Floor RMS Jitter, 12kHz to 20MHz Integration BW 8 fsRMS RMS Jitter, ADC SNR Method (Note 9) 66 fsRMS –160.2 dBc/Hz RMS Jitter, 12kHz to 20MHz Integration BW Phase Noise Floor 9 fsRMS RMS Jitter, ADC SNR Method (Note 9) 65 fsRMS –167.8 dBc/Hz 21 fsRMS Phase Noise Floor RMS Jitter, 12kHz to 20MHz Integration BW RMS Jitter, ADC SNR Method (Note 9) Additive Phase Noise and RMS Jitter (fIN = 3.2GHz, fOUTx = 50MHz, Mx = 64) dBc/Hz 65 fsRMS –173.8 dBc/Hz RMS Jitter, 12kHz to 20MHz Integration BW 41 fsRMS RMS Jitter, ADC SNR Method (Note 9) 65 fsRMS Phase Noise Floor Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC6953 is guaranteed to meet specified performance limits over the full operating junction temperature range of –40°C to 125°C. Under maximum operation conditions, airflow or heat sinking may be required to maintain a junction temperature of 125°C or lower. It is required that the Exposed Pad (Pin 53) be soldered directly to the ground plane with an array of thermal vias as described in the Applications Information section. Note 3: Absolute maximum time of digital delay is limited to 100µs. Note 4: For fOUT ≥ 300MHz, analog delay time vs ADELx varies. See Typical Performance Characteristics plot and the Operation section Note 5: All outputs configured as enabled clocks: all PDx[1:0] = 0, EZS_ SRQ± pin state = 0, SSRQ = 0, SRQMD = 0, PDALL = 0, PDVCOPK = 0. Note 6: Configured with six enabled clock outputs and five SYSREF outputs with output drivers disabled: PD0, PD2, PD4, PD6, PD8, and PD10 = 0; PD1, PD3, PD5, PD7, and PD9 = 2; EZS_SRQ± pin state = 0; SSRQ = 0; SRQMD = 0; PDALL = 0; PDVCOPK = 0. Note 7: Additive phase noise and jitter from LTC6953 only. Incoming clock phase noise is not included. Note 8: Measured using DC2610. Note 9: Additive RMS jitter (ADC SNR method) is calculated by integrating the distribution section’s measured phase noise floor out to fCLK. Actual ADC SNR measurements show good agreement with this method. Note 10: Measured with 36" cables from output of DC2610 to measurement instrument. Cable loss is NOT accounted for in this plot. Note 11: Statistics calculated from 1200 total measured parts from two process lots. Note 12: Skew is defined as the difference between the zero-crossing time of a given output and the average zero-crossing time of all outputs. Note 13: Measured input power is de-embedded to the IN± pins of the LTC6953. Note 14: The LTC6953 is driven from a VCO (CVCO55CC-4000-4000) through a splitter. The other side of the splitter drives the input of a LTC6952 to lock the VCO in a PLL. The reference for the LTC6952 PLL is a Pascal OCXO-E, fREF = 100MHz, PREF = 6dBm. Rev. A For more information www.analog.com 7 LTC6953 TYPICAL PERFORMANCE CHARACTERISTICS –120 –130 –140 –150 –160 –180 100 1k 10k 100k 1M OFFSET FREQUENCY (Hz) 10M 40M –140 –150 –160 –180 2GHz 1GHz 500MHz 250MHz 1k 10k 100k 1M OFFSET FREQUENCY (Hz) 400 350 300 250 200 –160 10M 40M Mx = 1 –180 100 1k 10k 100k 1M OFFSET FREQUENCY (Hz) 10M 40M 6953 G03 250MHz 500MHz 1GHz 2GHz 4GHz 300 250 200 150 250MHz 500MHz 1GHz 2GHz 100 50 0 10 20 30 40 ADEL VALUE 50 100 50 0 60 0 6953 G04 100 90 800 JITTER (fsRMS) 80 75 70 500 400 300 60 200 55 100 28 32 Mx = 1 NOTES 7, 9 600 65 8 12 16 20 24 OUTPUT DIVIDER VALUE 1000 FILTV = 0 FILTV = 1 900 700 4 800 1000 85 0 400 600 DDEL VALUE Additive Jitter vs Input Slew Rate, ADC SNR Method ODD DIVIDER EVEN DIVIDER NOTES 7, 9 95 200 6953 G05 Additive Jitter vs Divider Setting, ADC SNR Method JITTER (fsRMS) –150 NOTES 7, 9 450 JITTER (fsRMS) JITTER (fsRMS) 500 NOTES 7, 9 150 0 0.1 6953 G06 8 –140 Additive Jitter vs DDEL Value, ADC SNR Method, fIN = 4GHz, Mx = 1, 2, 4, 8 and 16 350 50 –130 6953 G02 400 0 –120 –170 Additive Jitter vs ADEL Value, ADC SNR Method, fIN = 4GHz, Mx = 2, 4, 8 and 16 450 IN± Pins 10dBm, FILTV = 0 10dBm, FILTV = 1 0dBm, FILTV = 0 0dBm, FILTV = 1 –10dBm, FILTV = 0 –10dBm, FILTV = 1 –110 –130 6953 G01 500 –100 –120 –170 VCO OUTPUT LTC6953 OUTPUT Total Phase Noise, 100MHz Sine Wave Input Signal VCO: CVCO55CC-4000-4000 NOTE 14 –110 PHASE NOISE (dBc/Hz) PHASE NOISE (dBc/Hz) –110 –170 –100 VCO: CVCO55CC-4000-4000 NOTE 14 Total Phase Noise, Driven from VCO in a Locked PLL, fVCO = 4GHz, = 4GHz, Mx = 2, 4, 88,and and16 16 PHASE NOISE (dBc/Hz) –100 Total Phase Noise, Driven from VCO in a Locked PLL, fVCO = 4GHz, Mx = 1 1 INPUT SLEW RATE (V/ns) 10 6953 G07 Rev. A For more information www.analog.com LTC6953 TYPICAL PERFORMANCE CHARACTERISTICS 0.4 0.3 0.3 0.1 0.0 –0.1 –0.2 –0.3 0.2 0.1 0.0 –0.1 –0.2 –0.3 –0.4 –0.4 6953 G08 100ps/DIV –0.5 200ps/DIV 0.85 0.80 0.75 0.70 0.65 0.60 0.55 6953 G09 125°C 25°C –40°C 0.90 NOTES 8, 10 0 1 2 3 OUTPUT FREQUENCY (GHz) 4 6953 G10 Analog Delay Time vs ADEL Value, Temperature 1200 Analog Delay Time Temperature Variation from 25°C 40 1000 TADEL TEMPERATURE VARIATION (ps) label1 label3 label2 125°C 25°C –40°C 1100 ANALOG DELAY TIME (ps) 900 800 700 600 500 400 300 200 100 0 0 10 20 30 40 ADEL VALUE 50 label1 label3 label2 125°C –40°C 30 20 10 0 –10 –20 –30 –40 60 0 10 20 6953 G11 Analog Delay Time vs ADEL Value Over Multiple Output Frequencies 1200 1000 900 800 700 600 60 fvco = 4.5GHz, Mx=16 NOTES 11, 12 10 5 500 400 0 –5 +3σ 300 Average 200 –10 –3σ 100 0 50 Expected Skew Variation for a Single Part 15 100MHz 300MHz 500MHz 750MHz 1000MHz 1500MHz 1750MHz 2250MHz 1100 30 40 ADEL VALUE 6953 G12 SKEW (ps) –0.5 0.95 DIFFERENTIAL OUTPUT SWING (VP–P) 0.4 DIFFERENTIAL OUTPUT (V) 0.5 0.2 Differential Output Swing vs Frequency, Temperature CML Differential Output at 1GHz 0.5 ANALOG DELAY TIME (ps) DIFFERENTIAL OUTPUT (V) CML Differential Output at 4.5GHz 0 10 20 30 40 ADEL VALUE 50 60 –15 0 6953 G13 1 2 3 4 5 6 OUTPUT 7 8 9 10 6953 G14 Rev. A For more information www.analog.com 9 LTC6953 TYPICAL PERFORMANCE CHARACTERISTICS Skew Variation with Temperature for a Single Typical Part 20 Propagation Delay vs Frequency, Temperature 380 NOTE 12 FILTV = 0 370 360 10 tPD (ps) SKEW (ps) 350 0 –10 340 330 320 310 –20 –30 –40 –20 OUT0 OUT1 OUT2 OUT3 0 20 OUT4 OUT5 OUT6 OUT7 40 60 TJ (°C) OUT8 OUT9 OUT10 80 290 280 100 120 fVCO = 4.5GHz –6 NOTE 11 SENSITIVITY (dBm) NUMBER OF PARTS 4000 NOTE 13 –8 200 –10 –12 –14 0 320 325 330 335 340 tPD (ps) 345 –16 350 125°C 25°C –40°C 0 1 4 6953 G18 Supply Current vs Number of Disabled Outputs 1000 NOTE 5 900 800 850 CURRENT (mA) 700 840 600 500 400 300 830 200 FULLY DISABLED (PDx = 3) OUTPUT DISABLED (PDx = 2) 100 820 –40 –20 FILTV = 0 2 3 FREQUENCY (GHz) 6953 G17 Supply Current vs Junction Temperature, All Outputs Enabled 10 2000 3000 FREQUENCY (MHz) Input Signal Detected vs Frequency, Temperature 100 CURRENT (mA) 1000 6953 G16 300 860 0 6953 G15 Propagation Delay Variation, Input to OUT4Delay Variation Propagation 400 125°C 70°C 25°C –40°C 300 0 20 40 60 TJ (°C) 80 100 120 0 0 1 6953 G19 2 3 4 5 6 7 8 9 10 11 NUMBER OF DISABLED OUTPUTS 6953 G20 Rev. A For more information www.analog.com LTC6953 PIN FUNCTIONS CS (Pin 1): Serial Port Chip Select. This CMOS input initiates a serial port communication burst when driven low, ending the burst when driven back high. See the Operation section for more details. VIN+ (Pins 39): 3.15V to 3.45V Positive Supply Pin for Input Circuitry. This pin should be bypassed directly to the ground plane using a 0.01µF ceramic capacitor as close to the pin as possible. VD+ (Pin 2): 3.15V to 3.45V Positive Supply Pins for Synchronization/SYSREF Request Functions and Serial Port. This pin should be bypassed directly to the ground plane using a 0.01µF ceramic capacitor as close to the pin as possible. SD (Pin 40): Chip Shutdown Pin. When tied to GND, this CMOS input disables all blocks in the chip. This is the same function as PDALL in the serial interface. OUT0+, OUT0– (Pins 34, 33): Output Signals. The output divider is buffered and presented differentially on these pins. The outputs have 50Ω (typical) output resistance per side (100Ω differential). The far end of the transmission line is typically terminated with 100Ω connected across the outputs. See the Operation and Applications Information section for more details. VREF+ (Pin 44): 3.15V to 3.45V Positive Supply Pin for EZS_SRQ circuitry. This pin should be bypassed directly to the ground plane using a 0.1µF ceramic capacitor as close to the pin as possible. OUT1+, OUT1– (Pins 31, 30): Same as OUT0. OUT2+, OUT2– (Pins 28, 27): Same as OUT0. OUT3+, OUT3– (Pins 25, 24): Same as OUT0. OUT4+, OUT4– (Pins 22, 21): Same as OUT0. OUT5+, OUT5– (Pins 19, 18): Same as OUT0. OUT6+, OUT6– (Pins 16, 15): Same as OUT0. OUT7+, OUT7– (Pins 13, 12): Same as OUT0. OUT8+, OUT8– (Pins 10, 9): Same as OUT0. OUT9+, OUT9– (Pins 7, 6): Same as OUT0. OUT10+, OUT10– (Pins 4, 3): Same as OUT0. VOUT+ (Pins 5, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35): 3.15V to 3.45V Positive Supply Pins for Output Dividers. Each pin should be separately bypassed directly to the ground plane using a 0.01µF ceramic capacitor as close to the pin as possible. NC (Pins 36, 42, 43, 45, 46): Not Connected Internally. It is recommended that these pins be connected to the ground pad (pin 53). IN+, IN– (Pins 37, 38): Input Signals. The differential signal placed on these pins is buffered with a low noise amplifier and fed to the internal distribution path. These self-biased inputs present a differential 250Ω (typical) resistance to aid impedance matching. They may also be driven single-ended by using the matching circuit in the Operation section. GND (Pin 41): Negative Power Supply (Ground). This pin should be tied directly to the ground pad (Pin 53). EZS_SRQ+, EZS_SRQ– (Pins 47, 48): Synchronization or SYSREF Request Input. Bit SRQMD defines this differential or single-ended input as an EZSync request or SYSREF request. It can operate as a differential input, or EZS_SRQ– can be tied to GND and EZS_SRQ+ driven with a single-ended CMOS signal. See the Operation and Applications Information sections for more details. STAT (Pin 49): Status Output. This signal is a configurable logical OR combination of the VCOOK and VCOOK status bits, programmable via the STATUS register. It can also be configured to present a diode voltage for temperature measurement. See the Operation section for more details. SCLK (Pin 50): Serial Port Clock. This CMOS input clocks serial port input data on its rising edge. See the Operation section for more details. SDO (Pin 51): Serial Port Data Output. This CMOS threestate output presents data from the serial port during a read communication burst. Optionally attach a resistor of > 200kΩ to GND to prevent a floating output. See the Operation section for more details. SDI (Pin 52): Serial Port Data Input. The serial port uses this CMOS input for data. See the Operation section for more details. GND (Exposed Pad Pin 53): Negative Power Supply (Ground). The package exposed pad must be soldered directly to the PCB land. The PCB land pattern should have multiple thermal vias to the ground plane for both low ground inductance and also low thermal resistance. Rev. A For more information www.analog.com 11 LTC6953 BLOCK DIAGRAM 44 47 48 46 VREF+ NC 45 NC 43 NC 42 NC 41 GND NC SIGNAL DETECT EZS_SRQ+ EZS_SRQ– SYNC AND SYSREF CTRL IN+ IN– TEMPO 49 50 51 52 1 2 40 53 5 4 3 8 7 6 11 10 9 14 13 12 FILTV STAT DDEL0 0–4095 SCLK SDO CS M0 DIV 1–4096 ADEL0 0ns–1.1ns VOUT+ OUT0+ OUT0– VOUT+ SERIAL PORT AND DIGITAL SDI VIN+ OUT1+ DDEL1 0–4095 M1 DIV 1–4096 ADEL1 0ns–1.1ns OUT1– V D+ VOUT+ SD OUT2+ GND VOUT DDEL2 0–4095 EXPOSED PAD + M2 DIV 1–4096 ADEL2 0ns–1.1ns VOUT+ OUT10+ OUT10– VOUT OUT3+ ADEL10 0ns–1.1ns M10 DIV 1–4096 DDEL10 0–4095 DDEL3 0–4095 M3 DIV 1–4096 ADEL3 0ns–1.1ns + OUT3– + VOUT OUT9+ OUT9– OUT2– OUT4+ ADEL9 0ns–1.1ns M9 DIV 1–4096 DDEL9 0–4095 DDEL4 0–4095 M4 DIV 1–4096 ADEL4 0ns–1.1ns OUT4– VOUT+ VOUT+ OUT8+ OUT5+ OUT8- ADEL8 0ns–1.1ns M8 DIV 1–4096 DDEL8 0–4095 DDEL5 0–4095 M5 DIV 1–4096 ADEL5 0ns–1.1ns OUT5– VOUT+ VOUT+ OUT7+ OUT6+ OUT7– ADEL7 0ns–1.1ns M7 DIV 1–4096 DDEL7 0-4095 DDEL6 0–4095 M6 DIV 1–4096 ADEL6 0ns–1.1ns OUT6– 36 39 37 38 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 6953 BD 12 Rev. A For more information www.analog.com LTC6953 TIMING DIAGRAMS Propagation Delay and Output Skew IN– IN+ tPD-VCO tSKEW0 OUT0+ OUT0– tSKEW1 OUT1+ OUT1– tSKEW2 OUT2+ OUT2– tSKEW3 OUT3+ OUT3– tSKEW3 OUT10+ OUT10– 6953 TD01 AVERAGE ZERO CROSSING TIME OF ALL OUTPUTS Differential CML Rise/Fall Times 80% 20% tR tF 6953 TD02 Rev. A For more information www.analog.com 13 LTC6953 OPERATION The LTC6953 is a high performance multioutput clock distributor that operates up to 4.5GHz. Utilizing Analog Devices’ proprietary EZSync and ParallelSync standards, users of the LTC6953 and its companion part LTC6952 can synchronize clocks across multiple outputs and multiple chips. The device is able to achieve superior additive integrated jitter performance by way of its excellent output noise floor. For JESD204B/C subclass 1 applications, the LTC6953 also provides several convenient methods to generate SYSREF pulses. INPUT BUFFER The LTC6953’s input buffer provides a flexible interface to either differential or single-ended frequency sources. The inputs are self-biased, and AC-coupling is recommended for applications using external VCO/VCXO/VCSOs. However, the input can also be driven DC-coupled by LVPECL, CML or any other driver type within the input’s specified common mode range. See the Applications Information section for more information on common input interface configurations, noting that the LTC6953’s input buffer has an internal differential resistance of 250Ω as shown in Figure 1. BIAS VIN+ 2.1V phase noise performance will be achieved by enabling the internal broadband noise filtering circuit within the input buffer. This is accomplished by asserting the configuration bit FILTV in serial port register h02. Note that setting FILTV = 1 when the slew rate of the input is greater than 2V/ns will degrade the overall PLL phase noise performance. See Table 1 for recommended settings of FILTV. Table 1. FILTV Programming FILTV 1 < 2V/ns 0 ≥ 2V/ns Input Peak Detector An input peak detection circuit on the IN± inputs detects the presence of an input signal and provides the VCOOK and VCOOK status flags available through both the STAT output and serial port register h00. VCOOK is the logical inverse of VCOOK. The circuit has hysteresis to prevent the VCOOK flag from chattering at the detection threshold. The peak detector may be powered-down using the PDVCOPK bit found in register h02. The peak detector approximates an RMS detector, therefore sine and square wave inputs will give different detection thresholds by a factor of 4/π. See Table 2 for VCOOK detection values. Table 2. VCOOK, VCOOK Status Output vs Input Amplitude 935Ω VCOOK 125Ω SLEW RATE OF INPUT 125Ω IN+ FILTV – 6953 F01 VCOOK SINE WAVE fIN SQUARE WAVE fIN 1 0 ≥ 250mVP-P ≥ 200mVP-P 0 1 < 100mVP-P < 75mVP-P OUTPUT DIVIDERS (M0 TO M10) IN Figure 1. Simplified Input Interface Schematic The maximum input frequency for the input buffer is 4.5GHz, and the maximum amplitude is 1.6VP-P. It is also important that the IN± input signal be low noise and have a slew rate of at least 100V/µs, although better performance will be achieved with a higher slew rate. For applications with input slew rates less than 2V/ns, better 14 The eleven independent, identical output dividers are driven directly from the input buffer. They divide the input frequency fIN by the divide value Mx to produce a 50% duty cycle output signal at frequency fOUTx. The Mx value is set by the MPx[4:0] and the MDx[2:0] bits using Equation 1: (1) Mx = (MPx + 1) • 2MDx For proper operation, MDx must be 0 if Mx is less than or equal to 32. Rev. A For more information www.analog.com LTC6953 OPERATION Table 3. PDx[1:0] Programming PDx[1:0] DESCRIPTION 0 Normal Operation 1 Mute Output (OUTx = 0 If OINVx = 0, OUTx = 1 If OINVx = 1), Internal Divider Remains Running and Synchronized 2 Power-Down Output (Both + and – Outputs Go to VOUT+), Internal Divider Remains Running and Synchronized 3 Power-Down Divider and Output (Both + and – Outputs Go to VOUT+), Internal Divider Stops and Must Be Re-Synchronized Upon Return to Normal Operation DIGITAL OUTPUT DELAYS (DDEL0 TO DDEL10) Each output divider can have the start time of the output delayed by integer multiples of ½ of the input period after a synchronization event. The digital delay value is programmed into the DDELx[11:0] bits and can be any value from 0 to 4095. Digital delays are only enabled when the synchronization bits SRQENx are set to “1”, and any changes to the output digital delays will not be reflected until after synchronization. Digital delay can be used with no degradation to clock jitter performance. See the Operation section on Synchronization and the Applications Information section for details on the use of the digital delay settings. ANALOG OUTPUT DELAYS (ADEL0 TO ADEL10) Each output has a fine analog delay feature to further adjust its output delay time (tADELX) in small steps controlled by the ADELx[5:0] bits. For output frequencies less than 300MHz, absolute time delays range from 0 to 1.1ns. Above 300MHz, the time delay is frequency dependent, and the valid useful range of ADELx is reduced according to Table 4. Table 4. Maximum ADELx vs Output Frequency Range fOUT RANGE MAXIMUM ADELx fOUTx ≤ 750MHz 63 750MHz < fOUTx ≤ 1GHz 31 1GHz < fOUTx ≤ 1.5GHz 16 1.5GHz < fOUTx ≤ 1.75GHz 12 1.75GHz < fOUTx ≤ 2.25GHz 8 fOUTx > 2.25GHz 0 Figure  2 shows the approximate analog delay time (tADELx) vs ADELx and output frequency. Note that the y-axis is logarithmic scale, and that analog delay is zero for ADEL = 0. See the Applications Information section for a more comprehensive method of calculating expected analog delay. 1280 ANALOG DELAY, LOG SCALE (ps) Any divider can be muted or powered down to save current by adjusting its corresponding PDx[1:0] bits. The description of the PDx[1:0] bits is shown in Table 3. < 300MHz 500MHz 750MHz 1GHz 1.5GHz 1.75GHz 2.25GHz 640 320 160 80 0 10 20 30 40 ADEL CODE 50 60 6953 F02 Figure 2. Analog Delay Time vs ADEL Code and Output Frequency Use caution when using analog delay on device clocks as this will degrade jitter. Digital delay should be used whenever possible since it does not impact performance. The maximum value of analog delay will never need to be more than half of an input period. Analog delays are always enabled regardless of the value of the SRQENx bits, and they take effect immediately upon a write to the ADELx registers. However, changes in ADEL can cause the output to glitch temporarily, especially switching between ADEL = 0 and ADEL ≠ 0. See the Applications Information section for details on the use of the analog delay settings. The LTC6952Wizard may be used for ADEL calculation and visualization. CML OUTPUT BUFFERS (OUT0 TO OUT10) All of the outputs are very low noise, low skew 2.5V CML buffers. Each output can be either AC- or DC-coupled, and terminated with 100Ω differentially. If a single-ended output is desired, each side of the CML output can be individually AC-coupled and terminated with 50Ω. The OINVx bits can selectively invert the sense of each output to facilitate board routing without having to cross Rev. A For more information www.analog.com 15 LTC6953 OPERATION matched-length traces. OINVx also determines the state of the output in a muted condition (PDx = 1) as shown in Table 3. See Figure 3 for circuit details. BIAS 2.1V CMOS VOUT+ 7k VREF+ 28k 0.8V EZS_SRQ– 33Ω 50Ω CMOS 50Ω EZS_SRQ+ OUTx + OUTx – CMOS CMOS 6953 F03 Figure 3. Simplified CML Interface Schematic (All OUTx) CMOS 6953 F04 Figure 4. Simplified EZS_SRQ Interface Schematic OUTPUT SYNCHRONIZATION AND SYSREF GENERATION the request is for synchronization of the outputs. When SRQMD = 1, it is a request to output SYSREF pulses. The LTC6953 has circuitry to allow all outputs to be synchronized into known phase alignments in multiple ways to suit different applications using the EZSync Multichip Clock Edge Synchronization protocol. Synchronization can be between any combination of outputs on the same chip (EZSync Standalone) or across multiple cascaded FOLLOWER chips (EZSync Multichip). Once the outputs are at the correct frequency and synchronized, the LTC6953 also has the ability to produce free running, gated or finitely pulsed SYSREF signals as indicated by the JESD204B/C subclass 1 specification. Note that synchronization MUST be performed before a SYSREF request. The synchronization must be repeated only if the divider setting is changed or if the divider is powered down. EZS_SRQ Input Buffer Both synchronization and SYSREF requests are achieved by either a software signal (bit SSRQ in register h0B) or a voltage signal on the EZS_SRQ± pins. The voltage on these pins may be any differential signal within the specifications in the Electrical Characteristics or alternatively a CMOS signal on EZS_SRQ+ while EZS_SRQ– is tied to GND. A simplified schematic of the EZS_SRQ input is shown in Figure 4. When using the SSRQ bit, the state of the EZS_SRQ± pins must be a logic “0”, easily achieved by setting both EZS_SRQ± pins to GND. Likewise, when using the EZS_SRQ± pins, bit SSRQ must be set to “0”. Bit SRQMD determines the type of request issued by the EZS_SRQ± pins or SSRQ bit. When SRQMD = 0, 16 Synchronization Overview The goal of synchronization is to align all output dividers on single or multiple LTC6953s (or other compatible Analog Devices clocking parts) into a known phase relationship. At initial power-up, after a power-on reset (POR) or any time the output divide values are changed, the outputs will not be synchronized. Any changes to the output digital delays (DDELx) will not be reflected until after synchronization. Although the outputs will be at the correct frequency without synchronization, the phases will have an unknown relationship until a synchronization event occurs. To enable synchronization on the LTC6953, the SRQMD bit in register h0B must be set to “0”. Synchronization begins either with the EZS_SRQ input driven to a high state or by writing “1” to the SSRQ bit. For any output with its SRQENx bit set to “1”, the output divider will stop running and return to a logic “0” state after an internal timing delay of greater than 100µs. The EZS_SRQ input state or SSRQ bit must remain high for a minimum of 1ms. Rev. A For more information www.analog.com LTC6953 OPERATION When the EZS_SRQ input is driven back low or “0” is written to the SSRQ bit, the synchronized internal dividers will start after an initial latency. Outputs with DDELx ≠ 0 will be delayed by an extra DDELx/2 input cycles. The behavior of each output will be defined individually by the output’s corresponding SRQENx and MODEx bits as shown in Table 5. All dividers with the same DDELx delay setting will have their output rising edge occur within the skew times as defined in the Electrical Characteristics table. The range of each delay is 0 to 4095 input half cycles and is independent of the divide ratio setting of each divider. See the Applications Information section for synchronization programming examples. Additionally, the LTC6952Wizard may be used to visualize these timing relationships. Table 5. Synchronization (SRQMD = 0) Output Behavior vs Device Settings SRQENx 0 MODEx 0 1, 2 or 3 INTERNAL DIVIDER SYNC TO OTHER DIVIDERS INTERNAL DIVIDER START LATENCY FROM SYNC SIGNAL FALLING EDGE (DDELx = 0) No N/A 0 1 1 or 3 Yes ~45µs + 7/ fIN 2 The LTC6953 supports three different methods of SYSREF generation as described in the JESD204B/C specification: • Free running • Gated on/off by a SYSREF request signal • One, two, four or eight SYSREF pulses after the rising edge of a SYSREF request signal These modes are defined by each output’s individually programmable MODEx bits. In order to generate SYSREF pulses, bit SRQMD must be set to “1” and MPx must be greater than 0. SYSREF requests (SYSREQ) are applied on the EZS_SRQ± pins or by setting the SSRQ bit to “1”. Table 6 describes the output behavior in SYSREF generation mode. Bits SYSCT[1:0] can be found in register h0B. Note that synchronization MUST be completed prior to SYSREF generation as described in the Synchronization Overview. Table 6. Output Behavior in SYSREF Generation Mode (SRQMD = 1) OUTPUT BEHAVIOR Free Running SRQENx MODEx 0 Muted Mute on SYNC High, Run on Sync Low Muted Sync Signal Pass-Through SYSREF Generation Overview The JESD204B/C subclass 1 specification describes a method to align multiple data converter devices (ADCs or DACs) in time and provide repeatable and programmable latency across the serial link with a logic device (FPGA). The Local Multi-Frame Clocks (LMFC) and internal clock dividers on all devices in the system are synchronized by a pulse (or pulse train) named SYSREF. Care must be taken to make sure the SYSREF signal remains synchronized to the ADC, DAC, and FPGA clocks and meets setup and hold timing as specified by the devices. 1 OUTPUT BEHAVIOR 0 Free Run, Ignore SYSREQ 1, 2 or 3 Muted, Ignore SYSREQ 0 Free Run, Ignore SYSREQ 1 Gated Pulses: Run on SYSREQ High, Mute on Low 2 SYSREQ Pass-Through 3 Output 2SYSCT Pulses After SYSREQ Goes High Multichip Synchronization and SYSREF Generation Using one LTC6953 in EZSync Standalone configuration (Figure 5), up to eleven clock signals or SYSREFs can be generated and synchronized. For applications requiring more than eleven clock outputs, the LTC6953 and its companion chip, the LTC6952, support two methods of multichip synchronization and SYSREF generation: EZSync Multichip and ParallelSync. The synchronization configuration is determined by bits EZMD and PARSYNC (on the LTC6952 only), and their required settings are shown in Table 7. Table 8 introduces the important attributes of these methods and their variants, with further details provided in the following paragraphs. Note that this table only refers to two-stage applications. Many more outputs are possible by using more stages. Rev. A For more information www.analog.com 17 LTC6953 OPERATION Table 7. Settings of EZMD and PARSYNC for Different Synchronization Topologies CONTROLLER FOLLOWER ParallelSync MULTICHIP (SEE FIGURES Figure 8 AND Figure 9) 0 0 0 1 0 0 1 0 CONTROL BIT EZSync STANDALONE (SEE Figure 5) PARSYNC (LTC6952 Only) EZMD EZSync MULTICHIP (SEE FIGURES Figure 6 AND Figure 7) Table 8. Parameters and Limitations of EZSync and ParallelSync (Two Stages Only) EZSync MULTICHIP PIN CONTROLLED REQUESTS (SEE Figure 6) EZSync STANDALONE (SEE Figure 5) CONTROLLER FOLLOWER RMS Jittera ~75fs ~75fs ~105fs ParallelSync MULTICHIP CONTROLLER FOLLOWER GENERAL REFERENCE DISTRIBUTION (SEE Figure 8) ~75fs ~105fs ~75fs ~75fs REQUEST PASS-THROUGH (SEE Figure 7) LTC6953 REFERENCE DISTRIBUTION SEE Figure 9) Possible Number of Followers (Nfol) – 1 to 11 1 to 5 – – Possible Number of Parallel Parts (Npar) – – – Unlimitedb 1 to 5 Total Number of Outputs 11 11 Npar 11 Npar Unlimitedb 55 ~tSKEWd Easy Maximum Number of Outputs 11 11 Nfol 11 Nfol 11 – 2 Nfol 121 11 Nfol 56 Maximum Skew tSKEW ~ tSKEW + tPD ~ tSKEW + tPD ~tSKEWd SYNC Timing Easy Easy Easy Moderate SYSREF Request Timing Easy Moderate Easy Moderate Easy Number of External VCOs 1 1 1 Npar Npar Yes No Yes No Yes Software SYNC/SYSREF Request? c c a Assumes ADC SNR equivalent integrated PLL/VCO RMS jitter contribution of 27fs and additive jitter for distribution-only parts of 70fs. b The only limitation is the ability to distribute the reference accurately. c Assumes worst-case skew between CONTROLLER and FOLLOWER outputs. Dependent on propagation delay of FOLLOWER and skew of controller-to- follower routing. d Dependent on skew of reference distribution parts, reference routing and individual part-to-part skew. 18 Rev. A For more information www.analog.com LTC6953 OPERATION ALL CONTROLLER TO FOLLOWER CONNECTIONS MUST BE DC-COUPLED OUT0+ IN± CLOCK GENERATOR OUT0– 100Ω CONTROLLER OUT1+ OUT1– 100Ω IN± CLOCK GENERATOR OUT2+ OUT2– SYNC OR SYSREF REQUEST CMOS BUFFER OUT1– 100Ω EZS_SRQ– OUT4– 100Ω OUT2– SYNC OR SYSREF REQUEST OUT3– CMOS BUFFER EZS_SRQ+ 100Ω LTC6953 EZS_SRQ– 100Ω 160Ω OUT8+ OUT8– 100Ω IN+ OUTx± IN– LTC6953 EZS_SRQ+ IN+ OUTx± IN– LTC6953 EZS_SRQ+ IN+ OUTx± IN– LTC6953 EZS_SRQ+ IN+ 160Ω LTC6953 OUT7+ EZSync CONTROLLER 160Ω OUT7– 160Ω OUTx± LTC6953 IN– EZS_SRQ+ IN+ OUTx± IN– LTC6953 EZS_SRQ+ IN+ OUTx± IN– LTC6953 EZS_SRQ+ IN+ OUTx± IN– LTC6953 EZS_SRQ+ 11 OUTPUTS 11 OUTPUTS 11 OUTPUTS 11 OUTPUTS 11 OUTPUTS 11 OUTPUTS 11 OUTPUTS 11 OUTPUTS 11 OUTPUTS OUT9+ OUT10+ OUT10– 160Ω OUT5+ OUT6– 100Ω OUT9+ OUT9– 160Ω OUT6+ OUT8+ OUT8– OUT4– OUT5– 100Ω OUT7+ OUT7– 160Ω OUT4+ OUT6+ OUT6– 160Ω IN+ OUTx± LTC6953 IN– EZS_SRQ+ OUT3+ 100Ω OUT5+ OUT5– 160Ω OUTx± LTC6953 IN– EZS_SRQ+ OUT2+ OUT4+ EZS_SRQ+ OUT0– IN+ OUT1+ OUT3+ OUT3– FOLLOWERS OUT0+ OUT9– 100Ω 100Ω FOLLOWER-SYNCHRONOUS OUTPUT 100Ω FOLLOWER-SYNCHRONOUS OUTPUT OUT10+ 6953 F05 OUT10– Figure 5. EZSync Standalone EZSync Multichip 6953 F06 When using EZSync multichip, compatible devices are cascaded together, with the clock output of a CONTROLLER device driving the inputs of one to eleven FOLLOWER devices as shown in Figure 6. The EZSync protocol allows for simple synchronization of all devices due to loose timing constraints on the SYNC signal. When used in a JESD204B/C application, SYSREF requests may need to be retimed to a free running SYSREF output to assure all FOLLOWERS start and stop their SYSREF signals at the same time. It is recommended that LTC6953 be used Figure 6. EZSync Multichip Synchronization (Nine Followers Shown, Max Eleven Possible as any FOLLOWER devices. However, LTC6952 can be used as a FOLLOWER if necessary by disabling its PLL (PDPLL = 1). To simplify both SYNC and/or SYSREF requests down to a simple software write to the CONTROLLER’s SSRQ bit, the devices may be connected as shown in Figure 7, where an additional CONTROLLER output drives each FOLLOWER’s EZS_SRQ pins (only available for LTC6953 Rev. A For more information www.analog.com 19 LTC6953 OPERATION ALL CONTROLLER TO FOLLOWER CONNECTIONS MUST BE DC-COUPLED CONTROLLER FOLLOWERS OUT0+ IN± CLOCK GENERATOR OUT0– IN+ 160Ω OUT1+ OUT1– 100Ω OUT2+ OUT2– 160Ω OUT3– EZS_SRQ+ EZS_SRQ– 100Ω 160Ω 100Ω 160Ω OUT8+ ParallelSync EZS_SRQ– IN– OUTx ± 11 OUTPUTS LTC6953 EZS_SRQ– IN– OUTX ± 11 OUTPUTS LTC6953 EZS_SRQ+ IN– LTC6952 #1 OUTx ± 11 OUTPUTS REF± REFERENCE DISTRIBUTION LTC6953 EZS_SRQ+ 100Ω In a ParallelSync application, multiple ParallelSync compatible devices are connected in parallel with a shared distributed REF signal as shown in Figure 8. The advantage of parallel connection is improved jitter performance, as the clock signals do not propagate through two or more cascaded devices. However, synchronization requires tighter control of the SYNC and SYSREF request (SRQ) signals’ timing because of the need to have the SYNC/SRQ edges fall within the same REF cycle for all connected devices. The LTC6953 is not compatible as a ParallelSync device except as part of the reference and EZS_SRQ distribution EZS_SRQ– IN+ 160Ω OUT9+ OUT9– 11 OUTPUTS LTC6953 IN+ LTC6953 OUT7+ EZSync CONTROLLER 100Ω OUT7– OUT8– IN– OUTx ± EZS_SRQ+ OUT6+ OUT6– EZS_SRQ– IN+ OUT5+ OUT5– LTC6953 EZS_SRQ+ OUT4+ OUT4– 11 OUTPUTS EZS_SRQ+ IN+ OUT3+ SYNC OR SYSREF REQUEST: TOGGLE PIN OR WRITE SSRQ BIT IN– OUTx ± FOLLOWER before the FOLLOWER outputs or any follower-synchronous CONTROLLER outputs start clocking. Additionally, a CONTROLLER must have bit EZMD set to “0” and a FOLLOWER must have both EZMD and PDPLL set to “1”. See the Applications Information section for a programming example. Additionally, the LTC6952Wizard provides programming guidance. REFERENCE MAY BE SINGLEENDED OR DIFFERENTIAL EZS_SRQ– OUT10+ OUT10 – 100Ω OUTx ± LTC6952 #2 CP REF± EZS_SRQ± OUTx ± LTC6952 #3 CP EZS_SRQ± Figure 7. EZSync Multichip Synchronization with Request Pass-Through or LTC6952 FOLLOWERS). This request pass-through configuration reduces the system complexity at the cost of fewer possible FOLLOWERS (a maximum of 5). Note that MPx for the CONTROLLER’s pass-through output must be set greater than 0. For all cases of EZSync synchronization, the CONTROLLER must be programmed to output seven pre-pulses to each LTC6952 #N EZS_SRQ DISTRIBUTION REF± EZS_SRQ± EZS_SRQ MAY BE SINGLEENDED OR DIFFERENTIAL VCO 11 OUTPUTS LF(S) VCO± FOLLOWER-SYNCHRONOUS OUTPUT 6953 F07 LF(S) VCO± EZS_SRQ± REF± 20 CP VCO 11 OUTPUTS LF(S) VCO± OUTx ± CP VCO± OUTx ± 6953 F08 VCO 11 OUTPUTS LF(S) VCO 11 OUTPUTS Figure 8. ParallelSync Multichip Synchronization Rev. A For more information www.analog.com LTC6953 OPERATION as described below. See the LTC6952 data sheet for more information on ParallelSync. the settings given in Table 9, where DDELREF can be any valid DDEL value. The SYNC/SRQ timing for ParallelSync can be simplified to a single software bit write by using an LTC6953 (or LTC6952 with its PLL disabled) as the reference and EZS_SRQ distribution block, as shown in Figure 9. In this application, the EZS_SRQ outputs of the reference distribution part should be set to transition on the falling edge of its corresponding reference clock output. To achieve this, first synchronize the reference distribution part using Table 9. Reference Distribution Divider and DDEL Settings for ParallelSync EZS-SRQ CONNECTIONS MUST BE DC-COUPLED OUT0+ REF IN IN± OUT0– REF+ 100Ω OUT1+ OUT1– SYNC OR SYSREF REQUEST: TOGGLE PIN OR WRITE SSRQ BIT OUT3 100Ω EZS_SRQ– 100Ω 100Ω OUT8+ REF – EZS_SRQ– REF – EZS_SRQ– 100Ω REF – LF(S) CP VCO± VCO OUTx ± 11 OUTPUTS LF(S) CP VCO± VCO OUTx ± 11 OUTPUTS LF(S) CP VCO± VCO OUTx ± 100Ω EZS_SRQ– VCO± VCO 11 OUTPUTS 6953 F09 100Ω EZS_SRQ DIVIDE EZS_SRQ DDEL 1 DDELREF 2 DDELREF + 1 2 DDELREF 2 DDELREF + 2 3 DDELREF 3 DDELREF + 3 4 DDELREF 4 DDELREF + 4 REF Divide > 4 DDELREF = REF Divide DDELREF Just before sending a SYNC or SYSREF request to the parallel parts, set the reference distribution part’s SRQMD bit to “1”. This will automatically retime the passed-through requests to the reference clocks. After the request is done, set the SRQMD bit back to “0” to save supply current from the reference distribution part. See the Applications Information section for a programming example. To determine the best configuration for a given application, the flowchart in Figure 10 can be used. This flowchart uses the parameters from Table 8 to guide the user to the most suitable configuration. Depending on the user’s system requirements, many simplifications or additions can be made for multiple chip synchronization. For example, the above applications only assume a maximum of two stages, even though more stages can be added to increase the number of outputs. However, these applications are beyond the scope of this data sheet. Please contact the factory. Power Savings in SYSREF Generation Mode LF(S) CP OUTx ± REF CLK DDEL 11 OUTPUTS LTC6952 #5 EZS_SRQ+ OUT10+ OUT10– 11 OUTPUTS LTC6952 #4 EZS_SRQ+ REF+ OUT9+ OUT9– EZS_SRQ– REF+ 100Ω LTC6953 + REFERENCE OUT7 DISTRIBUTION 100Ω OUT7– OUT8– OUTx ± LTC6952 #3 EZS_SRQ+ OUT6+ OUT6– REF – REF+ 100Ω OUT5+ OUT5– EZS_SRQ– LTC6952 #2 EZS_SRQ+ OUT4+ OUT4– VCO LTC6952 #1 REF+ 100Ω + OUT3– EZS_SRQ+ VCO± EZS_SRQ+ OUT2+ OUT2– REF – LF(S) CP REF CLK DIVIDE 1 OUTPUT Figure 9. ParallelSync Multichip Synchronization with LTC6953 or LTC6952 Reference Distribution In most applications, SYSREF requests are a rare occurrence. The LTC6953 provides modes to shut down as much circuitry as possible while still maintaining the correct timing relationship between SYSREF outputs and clock outputs. Individual outputs may be put into a low power mode while leaving the internal dividers running by writing a “2” to the PDx bits, where x is the output of interest. Additionally, putting the LTC6953 into SYSREF generation mode (SRQMD = 1) causes the part to draw a significantly higher current than SRQMD = 0. Therefore, Rev. A For more information www.analog.com 21 LTC6953 OPERATION START NOTE: CEILING() FUNCTION MEANS ROUND UP TO NEXT HIGHEST INTEGER. YES JESD204B/C APPLICATION? NO INPUTS: TP = TOTAL NUMBER OF JESD DEVICE CLOCK/SYSREF PAIRS LNP = NUMBER OF JESD PAIRS REQUIRING LOW NOISE (< 100fs) DEVICE CLOCKS TS = TOTAL NUMBER OF STAND ALONE CLOCK SIGNALS LNS = NUMBER OF REQUIRED LOW NOISE (< 100fs) STAND ALONE CLOCKS T = 2TP + TS T ≤ 11? YES INPUTS: T = TOTAL NUMBER OF CLOCK SIGNALS LNS = NUMBER OF REQUIRED LOW NOISE (< 100fs) CLOCKS USE EZSync STANDALONE YES NO NO ⎡ ⎛ T – 11 TP – 5 ⎞ ⎤ ⎟⎥ P = CEILING ⎢⎢ MAX ⎜⎜ , ⎟ 4 ⎠ ⎥⎥⎦ ⎢⎣ ⎝ 9 T ≤ 56 AND TP ≤ 25 AND LNS ≤ 11 – P2 – 2LNP AND LNP ≤ 5 – P? ⎛ T – 11⎞ ⎟ P = CEILING ⎜⎜ ⎟ ⎝ 9 ⎠ USE EZSync MULTICHIP WITH REQUEST PASSTHROUGH (1 CONTROLLER AND P FOLLOWERS) YES YES NO ⎛ T – 11⎞ ⎟ P = CEILING ⎜⎜ ⎟ ⎝ 10 ⎠ USE ParallelSync WITH LTC6953 REFERENCE DISTRIBUTION (P PARALLEL PARTS) YES YES NO T ≤ 121 AND LNS ≤ 11 – P? NO ⎛ T⎞ P = CEILING ⎜⎜ ⎟⎟ ⎝ 11⎠ ⎡ ⎛ T – 11 TP – 5.5 ⎞ ⎤ ⎟⎥ P = CEILING ⎢⎢ MAX ⎜⎜ , ⎟ 4.5 ⎠ ⎥⎥⎦ ⎢⎣ ⎝ 10 T ≤ 121 AND TP ≤ 55 AND LNS ≤ 11 – P – 2LNP AND LNP ≤ (55 – TP)/9? T ≤ 56 AND LNS ≤ 11 – 2P? NO ⎡ ⎛ T TP ⎞ ⎤ P = CEILING ⎢⎢ MAX ⎜⎜ , ⎟⎟ ⎥⎥ ⎢⎣ ⎝ 11 5 ⎠ ⎥⎦ T ≤ 25 AND TP ≤ 25? T ≤ 11? YES USE STANDARD EZSync MULTICHIP (1 CONTROLLER AND P FOLLOWERS) NO ⎡ ⎛ T TP ⎞ ⎤ P = CEILING ⎢⎢ MAX ⎜⎜ , ⎟⎟ ⎥⎥ ⎢⎣ ⎝ 11 5 ⎠ ⎥⎦ YES T ≤ 55? NO USE STANDARD ParallelSync MULTICHIP (P PARALLEL PARTS) ⎛ T⎞ P = CEILING ⎜⎜ ⎟⎟ ⎝ 11⎠ 6953 F10 Figure 10. Flowchart to Determine the Best Synchronization Protocol for a Given Application 22 Rev. A For more information www.analog.com LTC6953 OPERATION leave the SRQMD bit set to “0” until a SYSREF request is required. When a SYSREF signal is needed, set SRQMD to “1”, return the PDx bits to “0”, then wait at least 50µs before issuing a SYSREF request. Put the SYSREF outputs back into low power mode (PDx = 2) and set SRQMD = 0 when finished. communication burst is terminated by the serial bus master returning CS high. See Figure 12 for details. Data is read from the part during a communication burst using SDO. Readback may be multidrop (more than one LTC6953 connected in parallel on the serial bus), as SDO is three-stated (Hi-Z) when CS is high or when data is not being read from the part. If the LTC6953 is not used in a multidrop configuration or if the serial port master is not capable of setting the SDO line level between read sequences, it is recommended to attach a high value resistor of greater than 200k between SDO and GND to ensure the line returns to a known level during Hi-Z states. See Figure 13 for details. SERIAL PORT The SPI-compatible serial port provides control and monitoring functionality. A configurable status output STAT gives additional instant monitoring. Communication Sequence The serial bus is composed of CS, SCLK, SDI, and SDO. Data transfers to the part are accomplished by the serial bus master device first taking CS low to enable the LTC6953’s port. Input data applied on SDI is clocked on the rising edge of SCLK, with all transfers MSB first. The Single Byte Transfers The serial port is arranged as a simple memory map, with status and control available in 56, byte-wide registers. All data bursts are comprised of at least two bytes. MASTER–CS tCSS tCKL tCKH tCSS tCSH MASTER–SCLK tCS MASTER–SDI tCH DATA DATA 6953 F11 Figure 11. Serial Port Write Timing Diagram MASTER–CS 8TH CLOCK MASTER–SCLK tDO LTC6953–SDO Hi-Z tDO tDO DATA tDO DATA Hi-Z 6953 F12 Figure 12. Serial Port Read Timing Diagram Rev. A For more information www.analog.com 23 LTC6953 OPERATION The 7 most significant bits of the first byte are the register address, with an LSB of “1” indicating a read from the part, and LSB of “0” indicating a write to the part. The subsequent byte or bytes, is data from/to the specified register address. See Figure 13 for an example of a detailed write sequence and Figure 14 for a read sequence. transfer. The first byte of the second burst contains the destination register address (ADDRY) and an LSB indicating a write. The next byte on SDI is the data intended for the register at address ADDRY. CS is then taken high to terminate the transfer. Multiple Byte Transfers Figure 15 shows an example of two write communication bursts. The first byte of the first burst sent from the serial bus master on SDI contains the destination register address (ADDRX) and an LSB of “0” indicating a write. The next byte is the data intended for the register at address ADDRX. CS is then taken high to terminate the More efficient data transfer of multiple bytes is accomplished by using the LTC6953’s register address autoincrement feature as shown in Figure 16. The serial port master sends the destination register address in the first byte and its data in the second byte as before, but MASTER–CS MASTER–SCLK 16 CLOCKS 7-BIT REGISTER ADDRESS MASTER–SDI LTC6953–SD0 8 BITS OF DATA A6 A5 A4 A3 A2 A1 A0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 = WRITE Hi-Z 6953 F13 Figure 13. Serial Port Write Sequence MASTER–CS 16 CLOCKS MASTER–SCLK 7-BIT REGISTER ADDRESS MASTER–SDI 1 = READ A6 A5 A4 A3 A2 A1 A0 1 8 BITS OF DATA LTC6953–SDO Hi-Z X D7 D6 D5 D4 D3 D2 D1 D0 DX Hi-Z 6953 F14 Figure 14. Serial Port Read Sequence MASTER–CS ADDRX + Wr MASTER–SDI LTC6953–SDO BYTE X ADDRY + Wr BYTE Y Hi-Z 6953 F15 Figure 15. Serial Port Single Byte Writes 24 Rev. A For more information www.analog.com LTC6953 OPERATION MASTER–CS ADDRX + Wr MASTER–SDI LTC6953–SDO BYTE X BYTE X + 1 BYTE X + 2 Hi-Z 6953 F16 Figure 16. Serial Port Auto-Increment Write continues sending bytes destined for subsequent registers. Byte 1’s address is ADDRX + 1, Byte 2’s address is ADDRX + 2, and so on. If the register address pointer attempts to increment past 56 (h38), it is automatically reset to 0. An example of an auto-increment read from the part is shown in Figure 17. The first byte of the burst sent from the serial bus master on SDI contains the destination register address (ADDRX) and an LSB of “1” indicating a read. Once the LTC6953 detects a read burst, it takes SDO out of the Hi-Z condition and sends data bytes sequentially, beginning with data from register ADDRX. The part ignores all other data on SDI until the end of the burst. Multidrop Configuration Several LTC6953s may share the serial bus. In this multidrop configuration, SCLK, SDI, and SDO are common between all parts. The serial bus master must use a separate CS for each part and ensure that only one device has CS asserted at any time. It is recommended to attach a high value resistor to SDO to ensure the line returns to a known level during Hi-Z states. Serial Port Registers The memory map of the LTC6953 is found in Table 10, with detailed bit descriptions found in Table 11. The register address shown in hexadecimal format under the “ADDR” column is used to specify each register. Each register is denoted as either read-only (R) or read-write (R/W). The register’s default value on device power-up or after a reset is shown at the right. The read-only register at address h00 is used to determine different status flags. These flags may be instantly output on the STAT pin by configuring register h01. See STAT Output section for more information. The register at address h38 is a read-only byte for device identification. MASTER–CS ADDRX + Rd MASTER–SDI LTC6953–SDO Hi-Z DON’T CARE BYTE X BYTE X + 1 Hi-Z BYTE X + 2 6953 F17 Figure 17. Serial Port Auto-Increment Read Rev. A For more information www.analog.com 25 LTC6953 OPERATION Table 10. Serial Port Register Contents ADDR MSB [6] [5] [4] [3] [2] [1] LSB R/W DEFAULT h00 0 0 1 0 VCOOK VCOOK 0 1 R h01 INVSTAT x[6] x[5] x[4] x[3] x[2] x[1] x[0] R/W h04 h02 PDALL * PDVCOPK * * * FILTV POR R/W h08 h03 PD3[1] PD3[0] PD2[1] PD2[0] PD1[1] PD1[0] PD0[1] PD0[0] R/W h00 h04 PD7[1] PD7[0] PD6[1] PD6[0] PD5[1] PD5[0] PD4[1] PD4[0] R/W h00 h05 TEMPO * PD10[1] PD10[0] PD9[1] PD9[0] PD8[1] PD8[0] R/W h00 h06 * * * * * * * * R/W h0C h07 * * * * * * * * R/W h01 h08 * * * * * * * * R/W h00 h09 * * * * * * * * R/W h2D h0A * * * * * * * * R/W h93 h0B * * * EZMD SRQMD SYSCT[1] SYSCT[0] SSRQ R/W h86 h0C MP0[4] MP0[3] MP0[2] MP0[1] MP0[0] MD0[2] MD0[1] MD0[0] R/W h00 h0D SRQEN0 MODE0[1] MODE0[0] OINV0 DDEL0[11] DDEL0[10] DDEL0[9] DDEL0[8] R/W h00 h0E DDEL0[7] DDEL0[6] DDEL0[5] DDEL0[4] DDEL0[3] DDEL0[2] DDEL0[1] DDEL0[0] R/W h00 h0F * * ADEL0[5] ADEL0[4] ADEL0[3] ADEL0[2] ADEL0[1] ADEL0[0] R/W h00 h10 MP1[4] MP1[3] MP1[2] MP1[1] MP1[0] MD1[2] MD1[1] MD1[0] R/W h00 h11 SRQEN1 MODE1[1] MODE1[0] OINV1 DDEL1[11] DDEL1[10] DDEL1[9] DDEL1[8] R/W h00 h12 DDEL1[7] DDEL1[6] DDEL1[5] DDEL1[4] DDEL1[3] DDEL1[2] DDEL1[1] DDEL1[0] R/W h00 h13 * * ADEL1[5] ADEL1[4] ADEL1[3] ADEL1[2] ADEL1[1] ADEL1[0] R/W h00 h14 MP2[4] MP2[3] MP2[2] MP2[1] MP2[0] MD2[2] MD2[1] MD2[0] R/W h00 h15 SRQEN2 MODE2[1] MODE2[0] OINV2 DDEL2[11] DDEL2[10] DDEL2[9] DDEL2[8] R/W h00 h16 DDEL2[7] DDEL2[6] DDEL2[5] DDEL2[4] DDEL2[3] DDEL2[2] DDEL2[1] DDEL2[0] R/W h00 h17 * * ADEL2[5] ADEL2[4] ADEL2[3] ADEL2[2] ADEL2[1] ADEL2[0] R/W h00 h18 MP3[4] MP3[3] MP3[2] MP3[1] MP3[0] MD3[2] MD3[1] MD3[0] R/W h00 h19 SRQEN3 MODE3[1] MODE3[0] OINV3 DDEL3[11] DDEL3[10] DDEL3[9] DDEL3[8] R/W h00 h1A DDEL3[7] DDEL3[6] DDEL3[5] DDEL3[4] DDEL3[3] DDEL3[2] DDEL3[1] DDEL3[0] R/W h00 h1B * * ADEL3[5] ADEL3[4] ADEL3[3] ADEL3[2] ADEL3[1] ADEL3[0] R/W h00 h1C MP4[4] MP4[3] MP4[2] MP4[1] MP4[0] MD4[2] MD4[1] MD4[0] R/W h00 h1D SRQEN4 MODE4[1] MODE4[0] OINV4 DDEL4[11] DDEL4[10] DDEL4[9] DDEL4[8] R/W h00 h1E DDEL4[7] DDEL4[6] DDEL4[5] DDEL4[4] DDEL4[3] DDEL4[2] DDEL4[1] DDEL4[0] R/W h00 h1F * * ADEL4[5] ADEL4[4] ADEL4[3] ADEL4[2] ADEL4[1] ADEL4[0] R/W h00 h20 MP5[4] MP5[3] MP5[2] MP5[1] MP5[0] MD5[2] MD5[1] MD5[0] R/W h00 h21 SRQEN5 MODE5[1] MODE5[0] OINV5 DDEL5[11] DDEL5[10] DDEL5[9] DDEL5[8] R/W h00 h22 DDEL5[7] DDEL5[6] DDEL5[5] DDEL5[4] DDEL5[3] DDEL5[2] DDEL5[1] DDEL5[0] R/W h00 h23 * * ADEL5[5] ADEL5[4] ADEL5[3] ADEL5[2] ADEL5[1] ADEL5[0] R/W h00 h24 MP6[4] MP6[3] MP6[2] MP6[1] MP6[0] MD6[2] MD6[1] MD6[0] R/W h00 26 Rev. A For more information www.analog.com LTC6953 OPERATION ADDR MSB [6] [5] [4] [3] [2] [1] LSB R/W DEFAULT h25 SRQEN6 MODE6[1] MODE6[0] OINV6 DDEL6[11] DDEL6[10] DDEL6[9] DDEL6[8] R/W h00 h26 DDEL6[7] DDEL6[6] DDEL6[5] DDEL6[4] DDEL6[3] DDEL6[2] DDEL6[1] DDEL6[0] R/W h00 h27 * * ADEL6[5] ADEL6[4] ADEL6[3] ADEL6[2] ADEL6[1] ADEL6[0] R/W h00 h28 MP7[4] MP7[3] MP7[2] MP7[1] MP7[0] MD7[2] MD7[1] MD7[0] R/W h00 h29 SRQEN7 MODE7[1] MODE7[0] OINV7 DDEL7[11] DDEL7[10] DDEL7[9] DDEL7[8] R/W h00 h2A DDEL7[7] DDEL7[6] DDEL7[5] DDEL7[4] DDEL7[3] DDEL7[2] DDEL7[1] DDEL7[0] R/W h00 h2B * * ADEL7[5] ADEL7[4] ADEL7[3] ADEL7[2] ADEL7[1] ADEL7[0] R/W h00 h2C MP8[4] MP8[3] MP8[2] MP8[1] MP8[0] MD8[2] MD8[1] MD8[0] R/W h00 h2D SRQEN8 MODE8[1] MODE8[0] OINV8 DDEL8[11] DDEL8[10] DDEL8[9] DDEL8[8] R/W h00 h2E DDEL8[7] DDEL8[6] DDEL8[5] DDEL8[4] DDEL8[3] DDEL8[2] DDEL8[1] DDEL8[0] R/W h00 h2F * * ADEL8[5] ADEL8[4] ADEL8[3] ADEL8[2] ADEL8[1] ADEL8[0] R/W h00 h30 MP9[4] MP9[3] MP9[2] MP9[1] MP9[0] MD9[2] MD9[1] MD9[0] R/W h00 h31 SRQEN9 MODE9[1] MODE9[0] OINV9 DDEL9[11] DDEL9[10] DDEL9[9] DDEL9[8] R/W h00 h32 DDEL9[7] DDEL9[6] DDEL9[5] DDEL9[4] DDEL9[3] DDEL9[2] DDEL9[1] DDEL9[0] R/W h00 h33 * * ADEL9[5] ADEL9[4] ADEL9[3] ADEL9[2] ADEL9[1] ADEL9[0] R/W h00 h34 MP10[4] MP10[3] MP10[2] MP10[1] MP10[0] MD10[2] MD10[1] MD10[0] R/W h00 h35 SRQEN10 MODE10[1] MODE10[0] DDEL10[11] DDEL10[10] DDEL10[9] DDEL10[8] R/W h00 OINV10 h36 DDEL10[7] DDEL10[6] DDEL10[5] DDEL10[4] DDEL10[3] DDEL10[2] DDEL10[1] DDEL10[0] R/W h00 h37 * * ADEL10[5] ADEL10[4] ADEL10[3] ADEL10[2] ADEL10[1] ADEL10[0] R/W h00 h38 REV[3] REV[2] REV[1] REV[0] PART[3] PART[2] PART[1] PART[0] R hx3† * Unused † Varies depending on revision Rev. A For more information www.analog.com 27 LTC6953 OPERATION Table 11. Serial Port Register Bit Field Summary BITS ADELx[5:0] DESCRIPTION OUT0 Analog Delay Setting DEFAULT ADDR BITS DESCRIPTION 0 Various REV[3:0] Revision Code DEFAULT ADDR h38 h000 Various SRQENx Enable SYNC or SYSREF on OUTx 0 Various EZMD EZSync Mode 0 h0B SRQMD 0 h0B FILTV Input Buffer Filter 0 h02 0 = Synchronization Mode 1 = SYSREF Request Mode INVSTAT Invert STAT Output 0 h01 SSRQ 0 h0B MDx[2:0] OUTx 2N Value 0 Various Software SYNC or SYSREF Request MODEx[1:0] SYSREF Mode (SRQENx = 1): 0 = Free Run 1 = Gated Pulses 2 = Request Pass-Through 3 = 2SYSCT Pulses 0 Various SYSREF Pulse Count for MODEx = 3: 0 = One Pulse 1 = Two Pulses 2 = Four Pulses 3 = Eight Pulses h3 h0B OUTx Prescaler Value h0 Various OUTx Inversion 0 Various DDELx[11:0] OUTx Delay in ½ Input Cycles MPx[4:0] OINVx PART[3:0] PDALL Part Code (h2 = 6952, h3 = 6953) h38 Full Chip Power-Down 0 h02 PDVCOPK Powers Down Input Signal Detector 0 h02 PDx[1:0] OUTx Power-Down Mode: 0 = Normal Operation 1 = Output Muted to Logic “0” 2 = Power-Down Output Driver 3 = Power-Down Full Divider h0 Various Force Power-On-Reset 0 h02 POR 28 SYSCT[1:0] TEMPO Enable temperature Measurement Diode on STAT h05 VCOOK Input Valid Flag h00 VCOOK Input Not Valid Flag h00 x[6:0] STAT Output OR Mask h04 h01 Rev. A For more information www.analog.com LTC6953 OPERATION STAT Output The STAT output pin is configured with the x[6:0] bits and INVSTAT of register h01. These bits are used to bit-wise mask or enable, the corresponding status flags of status register h00, according to Equation 2 and shown schematically in Figure 18. The result of this bit-wise boolean operation is then output on the STAT pin if TEMP0 is “0”. STAT = (OR (Reg00 [6 : 0] AND Reg01[6 : 0])) XOR INVSTAT (2) X[6] 0 X[5] 1 X[4] 0 1 X[3] VCOOK 0 X[2] VCOOK INVSTAT X[1] 0 X[0] 1 1 0 TEMPO STAT For example, if the application requires STAT to go high whenever the VCOOK flag is set, then x[2] should be set to “1” and INVSTAT should be set to “0”, giving a register value of h04. Since only VCOOK and VCOOK are used for the LTC6953, only bits x[3:2] should be used. Bits x[6:4] and x[1:0] should always be set to 0. The STAT pin may be transformed to a temperature measurement with internal 300µA bias current by setting bit TEMPO in register h05 to “1”. To get an approximate die temperature, a single calibration point is needed first. Measure the STAT pin voltage (VTEMPC) with the LTC6953 powered down (PDALL = 1) at a known temperature (TCAL). Then the operating temperature may be calculated in a desired application by measuring the STAT voltage (VTEMP) and using Equation 3: (3) T = 665 • ( VTEMPC – VTEMP ) + TCAL where T and TCAL are in ºC, and VTEMPC and VTEMP are in V. Note that no external bias current is required. Allow 50µs settling time after setting TEMPO to “1”. Block Power-Down Control 6953 F18 Figure 18. STAT Simplified Schematic The LTC6953’s power-down control bits are located in register h02, described in Table 11. Different portions of the device may be powered down independently. To power down individual outputs, see Table 3. Care must be taken with the LSB of this register, the POR (power-on-reset) bit. When written to “1”, this bit forces a full reset of the part’s digital circuitry to its power-up default state. Rev. A For more information www.analog.com 29 LTC6953 APPLICATIONS INFORMATION INTRODUCTION DIGITAL AND ANALOG OUTPUT DELAYS The purpose of a clock distributor is to take an incoming clock signal of frequency fIN and produce multiple new clock signals at the same frequency or some other frequency value divided down from the input frequency. Each output clock can have its phase individually adjusted relative to the other clocks through the synchronization process. Figure  19 shows a typical application of the LTC6953. Synchronization allows the start times of each output divider to be delayed by the value programmed into the digital delay bits (DDELx), expressed in ½ input cycles. Applications needing to calculate the delay in terms of time can use Equation 5 where DDELx is DDEL0 to DDEL10: LTC6953 10nF IN– (fIN) IN+ 75Ω 30Ω M0 DIV, DDEL, AND ADEL ÷M0 OUT0 (fOUT0) M1 DIV, DDEL, AND ADEL ÷M1 OUT1 (fOUT1) M10 DIV, DDEL, AND ADEL ÷M10 OUT10 (fOUT10) CLOCK GENERATOR 10nF 6953 F19 Figure 19. LTC6953 Typical Application OUTPUT FREQUENCY For a given input frequency fIN, the output frequency fOUTx produced at the output of the Mx dividers is given by Equation 4: fOUTx = fIN Mx (4) tDDELx = DDELx 2 ( • fIN ) (5) The analog delay blocks (ADELx) are useful in trimming signal timing differences caused by non-ideal PCB routing. This is effective for optimizing setup and hold times for SYSREFs versus device clocks in JESD204B/C applications. Unlike digital delay, adding analog delay will adversely affect the jitter performance. Add analog delay to the SYSREF path whenever possible to minimize the impact on the device clocks. For example, if the SYSREF signal in a SYSREF/Clock pair is arriving at the destination device too late, it is better to add one digital delay code to the device clock and then add analog delay to the SYSREF, if necessary, to bring it closer to the device clock. The approximated analog delay time can be calculated in picoseconds (ps) by Equations 6 (for ADELx < 32) and Equation 7 (for ADELx ≥ 32) while adhering to the frequency limitations described in Table 4. ADELx = 1 to 31: t ADEL = [(11.25 • ADELx + 93.8) (0.00285 • fOUT ) –2.5 + 2.5 –0.4 ] (6) ADELx = 32 to 63: t ADEL = [(26 • ADELx – 517) (0.00125 • fOUT ) 2.5 –0.4 ] –2.5 + (7) where fOUT is the output frequency in GHz. The LTC6952Wizard may be used for analog delay calculation and visualization. 30 Rev. A For more information www.analog.com LTC6953 APPLICATIONS INFORMATION INPUT BUFFER The LTC6953’s input buffer, shown in Figure 1, has a frequency range of DC to 4.5GHz. The buffer has a partial onchip differential input termination of 250Ω, allowing some flexibility for an external matching network if desired. Figure 20 shows recommended interfaces for different input signal types. 150Ω 0.1µF RF CLOCK GENERATOR 50Ω OUTPUT IN– Z0 75Ω + IN+ LVPECL 160Ω LTC6953 0.1µF 0.1µF Z0 – 0.1µF 150Ω IN+ IN– Z0 30Ω LTC6953 AC-COUPLED DIFFERENTIAL LVPECL AC-COUPLED SINGLE-ENDED INPUT 0.1µF 150Ω IN+ Z0 + 160Ω LVPECL – LTC6953 + 160Ω 0.1µF CML – 150Ω LTC6953 IN– Z0 IN– Z0 IN+ Z0 AC-COUPLED DIFFERENTIAL CML 0.1µF DC-COUPLED DIFFERENTIAL LVPECL* + + Z0 CML IN 160Ω – Z0 + LTC6953 0.1µF IN– Z0 1µF CMOS RSER IN– Z0 62.5Ω * OUTPUT COMMON MODE LEVELS OF DC-COUPLED DRIVERS MUST BE WITHIN THE MIN AND MAX IN± INPUT COMMON MODE LEVELS SPECIFIED IN THE ELECTRICAL CHARACTERISTICS. LTC6953 AC-COUPLED DIFFERENTIAL LVDS IN– DC-COUPLED DIFFERENTIAL CML* 160Ω LVDS – IN+ Z0 VCMOS RSER 3.3V 100Ω 1.8V 30Ω LTC6953 IN+ 1µF SINGLE-ENDED CMOS 6953 F20 Figure 20. Common Input Interface Configurations. All ZO Signal Traces Are 50Ω Transmission Lines Rev. A For more information www.analog.com 31 LTC6953 APPLICATIONS INFORMATION EZS_SRQ INPUT The LTC6953’s EZS_SRQ input buffer, shown in Figure 4, controls synchronization requests and SYSREF requests. All connections MUST be DC-coupled and can be either differential CML or LVPECL, differential LVDS with a levelshifting network or single-ended 1.8V to 3.3V CMOS into the EZS_SRQ+ input pin (EZS_SRQ– must be grounded for CMOS drive). Figure  21 shows the recommended interface types. 3.3V 100Ω 130Ω 50Ω + LVDS LTC6953 750Ω 50Ω – 150Ω EZS_SRQ+ Z0 100Ω 100Ω LVPECL EZS_SRQ– Z0 – DC-COUPLED DIFFERENTIAL LVDS EZS_SRQ+ Z0 CML 100Ω – Z0 LTC6953 EZS_SRQ– Z0 150Ω 130Ω + EZS_SRQ+ Z0 + DC-COUPLED DIFFERENTIAL LVPECL* 1.8V TO 3.3V CMOS EZS_SRQ+ LTC6953 LTC6953 EZS_SRQ– EZS_SRQ– DC-COUPLED DIFFERENTIAL CML* 1.8V TO 3.3V CMOS 6953 F21 * OUTPUT COMMON MODE LEVELS OF DIFFERENTIAL DRIVERS MUST BE WITHIN THE MIN AND MAX EZS_SRQ INPUT COMMON MODE LEVELS SPECIFIED IN THE ELECTRICAL CHARACTERISTICS. Figure 21. Common EZS_SRQ Input Interface Configurations. All ZO Signal Traces Are 50Ω Transmission Lines 32 Rev. A For more information www.analog.com LTC6953 APPLICATIONS INFORMATION JESD204B/C DESIGN EXAMPLE USING EZSync STANDALONE Input Assumptions For this example, assume the input is driven by an external clock generator with a frequency of 4000MHz. This design example consists of a system of two JESD204B/C analog-to-digital converters (ADCs), two JESD204B/C digital-to-analog converters (DACs) and a JESD204B/C compatible FPGA. All of the data converters (ADCs and DACs) and the FPGA require JESD204B/C subclass 1 device clocks and SYSREFs, and the FPGA requires an extra management clock. Additionally, the ADCs require a low noise clock of less than 100fs total RMS jitter. This leads to a total of 11 separate signals to generate, with frequencies listed below. For this example, the SYSREF frequencies for all devices are the same and should output four pulses upon a SYSREF request rising edge: fIN = 4000MHz Design Procedure Designing and enabling this clock distribution solution consists of the following steps: 1. Determine all output modes. 2. Determine all M divider values. 3. Determine all digital delay values. 4. Program the IC with the correct divider values, output delays, and other settings. fADC-CLK = 500MHz 5. Synchronize the outputs. fDAC-CLK = 4000MHz 6. Place the SYSREF outputs in a lower power mode until the next SYSREF request (optional, see Operations section). fFPGA-CLK = 125MHz fFPGA-MGMT = 100MHz 7. Place IC into SYSREF request mode and send a SYSREF request when needed. fSYSREF = 12.5MHz Since the total number of outputs is 11, a single LTC6953 can be used to generate all of the outputs needed as shown in Figure 22. Note that termination resistors and AC-coupling capacitors are not shown for clarity. 8. Return the IC into SYNC mode (SRQMD = 0) and place the SYSREF outputs into a lower power mode for power savings (optional). SYSREF ADC0 CLK CLOCK GENERATOR IN± LTC6953 M0 M1 M2 M4 SYNC AND SYSREF CTRL EZS_SRQ± M10 SSRQ BIT M9 M8 M3 M5 M7 M6 INPUT/OUTPUT TERMINATIONS AND AC-COUPLING CAPS NOT SHOWN. SYSREF ADC1 CLK SYSREF DEV CLK FPGA MGMT CLK SYSREF DAC0 CLK SYSREF DAC1 CLK 6953 F22 Figure 22. Block Diagram for JESD204B/C EZSync Standalone Design Example Rev. A For more information www.analog.com 33 LTC6953 APPLICATIONS INFORMATION Note that synchronization MUST be performed before a SYSREF request. The synchronization must be repeated only if the divider setting is changed or if the divider is powered down. Determining Output Modes All outputs can be programmed as clocks (MODEx = 0), SYSREFs (MODEx = 1 or 3) or SYNC/SRQ pass-through outputs (MODEx = 2) using each output’s individual MODEx bits as described in Table 5 and Table 6. Any output can also be programmed to ignore SYNC and SYSREF requests by setting that output’s corresponding SRQENx bit to “0”. Noting that this design example calls for pulsed SYSREFs (MODEx = 3) and that the FPGA management clock should always be free running (SRQENx  =  0), Table 12 summarizes each output’s mode settings. Table 12. Output Mode Settings for EZSync Standalone Design Example OUTPUT PURPOSE SRQENx MODEx PDx OUT0 ADC0 SYSREF 1 3 0 OUT1 ADC0 CLK 1 0 0 OUT2 ADC1 SYSREF 1 3 0 OUT3 ADC1 CLK 1 0 0 OUT4 FPGA SYSREF 1 3 0 OUT5 FPGA DEV CLK 1 0 0 OUT6 FPGA MGMT CLK 0 0 0 OUT7 DAC0 SYSREF 1 3 0 OUT8 DAC0 CLK 1 0 0 OUT9 DAC1 SYSREF 1 3 0 OUT10 DAC1 CLK 1 0 0 Table 13. Output Divide Settings for EZSync Standalone Design Example OUTPUT PURPOSE FREQUENCY (MHz) DIVIDE VALUE (Mx) OUT0 ADC0 SYSREF 12.5 320 OUT1 ADC0 CLK 500 8 OUT2 ADC1 SYSREF 12.5 320 OUT3 ADC1 CLK 500 8 OUT4 FPGA SYSREF 12.5 320 OUT5 FPGA DEV CLK 125 32 OUT6 FPGA MGMT CLK 100 40 OUT7 DAC0 SYSREF 12.5 320 OUT8 DAC0 CLK 4000 1 OUT9 DAC1 SYSREF 12.5 320 OUT10 DAC1 CLK 4000 1 Determining Output Digital Delay Values The output digital delay is used to control phase relationships between outputs. The minimum delay step is ½ of a period of the incoming input signal. For this design example, the digital delay is used to place each device’s SYSREF signal edges into a known phase relationship to its corresponding device clock, optimized for the setup (tS) and hold time (tH) requirements for that device. Assume that the optimum SYSREF edge location for each device occurs on the first falling clock edge before the desired SYSREF valid rising clock edge. In other words, SYSREF should change states ½ of a corresponding device clock period before the SYSREF valid device clock edge. Refer to Figure 23 for an example. Determining Output Divider Values tH Since the desired frequencies of each output are already determined, the output divider values can be calculated using Equation 4. The results are shown in Table 13. SYSREF TRANSITION TARGET RANGE tS DESIRED SYSREF VALID CLOCK EDGE DEVICE CLOCK SYSREF 6953F23 Figure 23. SYSREF Edge Timing Example 34 Rev. A For more information www.analog.com LTC6953 APPLICATIONS INFORMATION In order to calculate each output’s digital delay value for this design example, use the following procedure: 1. Delay all of the JESD204B/C device clocks by half of a period of the slowest JESD204B/C device clock. This delay setting is equal to the divide value of the slowest device clock because a one code digital delay equals half of an input cycle. Non-JESD204B/C clocks (such as the FPGA management clock) are not included in this calculation. This delay value defines the desired SYSREF valid clock edge. In this example, the slowest JESD204B/C clock is the FPGA device clock: DDELSYSvalid = MFPGACLK = 32 DDELADC–CLK = DDELSYSvalid = 32 DDELDAC–CLK = DDELSYSvalid = 32 DDELFPGA–CLK = DDELSYSvalid = 32 2. For each device clock/SYSREF pair, subtract half a device clock period from DDELSYSvalid to find the SYSREF delay. This is equivalent to subtracting the corresponding divide value of the device clock: DDELADC–SYS = DDELSYSvalid – MADC–CLK DDELADC–SYS = 32 – 8 = 24 DDELDAC–SYS = DDELSYSvalid – MDAC–CLK DDELDAC–SYS = 32 – 1 = 31 DDELFPGA–SYS = DDELSYSvalid – MFPGA–CLK DDELFPGA–SYS = 32 – 32 = 0 Table 14 summarizes the DDEL settings for all outputs. Table 14. Output DDELx Settings for EZSync Standalone Design Example OUTPUT PURPOSE DDELx OUT0 ADC0 SYSREF 24 OUT1 ADC0 CLK 32 OUT2 ADC1 SYSREF 24 OUT3 ADC1 CLK 32 OUT4 FPGA SYSREF 0 OUT5 FPGA DEV CLK 32 OUT6 FPGA MGMT CLK 0 OUT7 DAC0 SYSREF 31 OUT8 DAC0 CLK 32 OUT9 DAC1 SYSREF 31 OUT10 DAC1 CLK 32 Now that the output divider and delays have been determined, the LTC6953 can be programmed. Status Register Programming This example will use the STAT pin to alert the system whenever the LTC6953 generates a fault condition. Program x[3] = 1 to force the STAT pin high whenever the VCOOK flag asserts: Reg01 = h08 Power and FILT Register Programming For correct operation, all internal blocks should be enabled. Additionally, the input signal has a sufficient slew rate and power to not need the FILTV bit: Reg02 = h00 Output Power-Down Programming During initial setup and synchronization, all used outputs and the SRQ circuitry should be set to full power. These bits will be used later to place the IC in a lower power mode while waiting for SYSREF requests: Reg03 = h00 Reg04 = h00 Reg05 = h00 SYNC and SYSREF Global Modes Programming Bit EZMD controls whether the IC is an EZSync standalone/CONTROLLER (“0”) or FOLLOWER (“1”). Since this example is an EZSync standalone application, set bit EZMD to “0”. Bit SRQMD determines if the part is in synchronization mode (“0”) or SYSREF request mode (“1”). SYSCT programs the number of pulses for any output in pulsed SYSREF mode (# pulses = 2SYSCT, so SYSCT = 2 to achieve four pulses for this example). Using this information, register h0B can be programmed: Reg0B = h04 Note that the SSRQ bit will remain “0” for now, but will be used later during the synchronization and SYSREF request procedures. Also, the EZS_SRQ± pins should be grounded Rev. A For more information www.analog.com 35 LTC6953 APPLICATIONS INFORMATION because the synchronization and SYSREF requests will be accomplished through software control of the SSRQ bit. Output Divider, Delay and Function Programming Four registers for each output allow the outputs to be configured independently of each other. The first register controls the output divide ratio through two control words, MPx and MDx, as described in Equation 1. The second register contains the control modes and the most significant bits of the digital delay control word. The third register contains the remainder of the digital delay control word, and the fourth register is the analog delay control. Both the analog delay and the output invert (OINVx) bits can be used to correct PCB layout issues such as mismatched trace lengths and differential signal crossovers, respectively. Note that the use of analog delay on clock signals will degrade jitter performance. For this example, assume the PCB is laid out in an ideal manner and no output inversions or analog delays are needed. With this information, all of registers h0C through h37 can be programmed to the values in Table 15, calculated using the information in Tables Table 20, 21 (with Equation 1) and 22. Table 15. Output Register Settings for EZSync Standalone Design Example Synchronization The outputs in this example are now running at the desired frequency, but have random phase relationships with each other. Synchronization forces the outputs to run at known and repeatable phases and can be achieved in this example either externally, by driving the EZS_SRQ± pins or internally, with the SSRQ bit in Reg0B. Since the part was just programmed, set the SSRQ bit to “1” and hold the EZS_SRQ± pins low: Reg0B = h05 After waiting a minimum of 1ms, set SSRQ to “0”: Reg0B = h04 Once the internal synchronization process completes, the outputs will be aligned as shown in Figure 24. Note that the internal divider behavior for the muted SYSREF outputs is shown as well as the actual outputs to demonstrate the phase alignment following synchronization. Putting the IC Into a Lower Power Mode (Optional) If desired, the LTC6953 can be placed into a lower power mode while awaiting a SYSREF request. This is achieved by setting PDx = 2 for all SYSREF-defined outputs. This powers down the output driver circuitry but leaves the internal divider running and in the correct phase relationship to the clocks. ADDR VALUE ADDR VALUE ADDR VALUE h0C h9C h1C h9C h2C h00 h0D hE0 h1D hE0 h2D h80 Performing a SYSREF Request h0E h18 h1E h00 h2E h20 h0F h00 h1F h00 h2F h00 h10 h38 h20 hF8 h30 h9C h11 h80 h21 h80 h31 hE0 h12 h20 h22 h20 h32 h1F To produce SYSREF pulses, write a “1” to SRQMD and take the LTC6953 out of low power mode (if used) by writing all the SYSREF output PDx bits to “0”. Wait 50µs to allow circuitry to power up. Send the SYSREF request by writing a “1” to the SSRQ bit in Reg0B: h13 h00 h23 h00 h33 h00 h14 h9C h24 h99 h34 h00 h15 hE0 h25 h00 h35 h80 After waiting a minimum of 1ms, set SSRQ to “0”: h16 h18 h26 h00 h36 h20 h17 h00 h27 h00 h37 h00 Reg0B = h04 h18 h38 h28 h9C h19 h80 h29 hE0 h1A h20 h2A h1F h1B h00 h2B h00 36 Reg0B = h05 Place the IC back into low power mode if desired by writing a “0” to SRQMD and setting PDx = 2 for all SYSREF defined outputs. After the rising edge of the SYSREF request, the SYSREF outputs will pulse four times and then return to a “0” state as shown in Figure 25. Rev. A For more information www.analog.com LTC6953 APPLICATIONS INFORMATION EZS_SRQ OR SSRQ BIT ADC DEVICE CLOCKS (OUT1 AND 3) ADC SYSREFs (MUTED OUT0 AND 2) INTERNAL ADC SYSREF DIVIDERS (MUTED OUT0 AND 2) DAC DEVICE CLOCKS (OUT8 AND 10) DAC SYSREFs (MUTED OUT7 AND 9) INTERNAL DAC SYSREF DIVIDERS (MUTED OUT7 AND 9) FPGA DEVICE CLOCK (OUT5) FPGA SYSREF (MUTED OUT4) INTERNAL FPGA SYSREF DIVIDER (MUTED OUT4) SYSREF VALID CLOCK EDGE FPGA MANAGEMENT CLOCK (OUT6) NOT SYNCHRONIZED, PHASE UNDETERMINED 6953 F24 Figure 24. Outputs after Synchronization for the EZSync Standalone Design Example (SRQMD = 0) EZS_SRQ OR SSRQ BIT ADC DEVICE CLOCKS (OUT1 AND 3) 500MHZ ADC SYSREFs (OUT0 AND 2) DAC DEVICE CLOCKS (OUT8 AND 10) 4000MHZ DAC SYSREFs (OUT7 AND 9) FPGA DEVICE CLOCK (OUT5) 125MHZ FPGA SYSREF (OUT4) FPGA MANAGEMENT CLOCK (OUT6) 100MHZ 6953 F25 Figure 25. Outputs after SYSREF Request for the EZSync Standalone Design Example (SRQMD = 1) Rev. A For more information www.analog.com 37 LTC6953 APPLICATIONS INFORMATION JESD204B/C DESIGN EXAMPLE USING EZSync MULTICHIP fFPGA–MGMT = 100MHz fSYSREF = 12.5MHz To determine which multichip configuration to use, we utilize the flowchart in Figure 10. This example has nine total JESD204B/C device clock/SYSREF pairs, four of which need to be less than 100fs total jitter. We also need one additional non-low noise standalone clock for the FPGA. Therefore: This design example consists of a system of four JESD204B/C analog-to-digital converters (ADCs), four JESD204B/C digital-to-analog converters (DACs), and a JESD204B/C compatible FPGA. All of the data converters (ADCs and DACs) and the FPGA require JESD204B/C subclass 1 device clocks and SYSREFs, and the FPGA requires an extra management clock. Additionally, the ADCs require a low noise clock of less than 100fs total RMS jitter. This leads to a total of 19 separate signals to generate, with frequencies listed below. For this example, the SYSREF frequencies for all devices are the same and should output four pulses upon a SYSREF request rising edge: TP = 9 LNP = 4 TS = 1 LNS = 0 Based on these inputs, Figure  10 suggests using the EZSync multichip protocol with request pass-through topology shown in Figure 7, using one CONTROLLER and one FOLLOWER chip. Noting that the use of LTC6953 for any FOLLOWER chips is recommended, Figure 26 fADC–CLK = 500MHz fDAC–CLK = 4000MHz fFPGA–CLK = 125MHz SYSREF ADC0 CLK CLOCK GENERATOR IN± LTC6953 CONTROLLER M0 M1 M2 M4 SYNC AND SYSREF CTRL EZS_SRQ± M10 SSRQ BIT M9 M8 M3 M5 M7 M6 SYSREF ADC1 CLK SYSREF ADC2 CLK SYSREF ADC3 CLK MGMT CLK SYSREF FPGA DEV CLK IN± LTC6953 FOLLOWER M0 M1 M2 M3 M4 SYNC AND SYSREF CTRL M5 EZS_SRQ± M10 SSRQ BIT M9 M8 M7 SYSREF DAC0 CLK SYSREF DAC1 CLK M6 SYSREF DAC2 CLK INPUT/OUTPUT TERMINATIONS AND AC COUPLING CAPS NOT SHOWN. SYSREF DAC3 CLK 6953 F26 Figure 26. Block Diagram for JESD204B/C EZSync Multichip Design Example 38 Rev. A For more information www.analog.com LTC6953 APPLICATIONS INFORMATION shows a block diagram of the full system. OUT8 of the CONTROLLER LTC6953 is driving the IN± inputs of the FOLLOWER LTC6953. This output is referred to as the “follower-driver” output. OUT9 of the CONTROLLER is driving the EZS_SRQ± pins of the FOLLOWER, and is therefore the SYNC/SRQ pass-through output. Also notice that the CONTROLLER clock outputs are the lowest jitter clocks, and should therefore be used to drive the ADCs. Input Assumptions For this example, assume the input to the CONTROLLER LTC6953 is driven by an external clock generator with a frequency of 4000MHz. fIN = 4000MHz Determining Output Modes All outputs can be programmed as clocks (MODEx = 0), SYSREFs (MODEx = 1 or 3) or SYNC/SRQ pass-through outputs (MODEx = 2) using each output’s individual MODEx bits as described in Table 5 and Table 6. Any output can also be programmed to ignore SYNC and SYSREF requests by setting that output’s corresponding SRQENx bit to “0”. Noting that this design example calls for pulsed SYSREFs (MODEx = 3) and that the FPGA management clock should always be free running (CONTROLLER SRQEN10  = 0), Table  16 summarizes each output’s mode settings. Table 16. Output Mode Settings for EZSync Multichip Design Example IC PURPOSE SRQENx MODEx PDx OUT0 ADC0 SYSREF 1 3 0 Designing and enabling this clock distribution solution consists of the following steps: OUT1 ADC0 CLK 1 0 0 OUT2 ADC1 SYSREF 1 3 0 OUT3 ADC1 CLK 1 0 0 OUT4 ADC2 SYSREF 1 3 0 1. Determine all output modes for CONTROLLER and FOLLOWER. 2. Determine all M divider values. 3. Determine all digital delay values. CONTROLLER OUTPUT Design Procedure 4. Program the ICs with the correct divider values, output delays, and other settings. 5. Synchronize the outputs. 7. Place ICs into SYSREF request mode and send a SYSREF request when needed. 8. Return the IC into SYNC mode (SRQMD = 0) and place the SYSREF outputs into a lower power mode for power savings (optional). Note that synchronization MUST be performed before a SYSREF request. The synchronization must be repeated only if the divider setting is changed or if the divider is powered down. FOLLOWER 6. Place the SYSREF outputs in a lower power mode until the next SYSREF request (optional, see Operations section). OUT5 ADC2 CLK 1 0 0 OUT6 ADC3 SYSREF 1 3 0 OUT7 ADC3 CLK 1 0 0 OUT8 To FOLLOWER IN± 1 0 0 OUT9 FOLLOWER EZS_SRQ 1 2 0 OUT10 FPGA MGMT CLK 0 0 0 OUT0 Unused 0 0 3 OUT1 FPGA SYSREF 1 3 0 OUT2 FPGA DEV CLK 1 0 0 OUT3 DAC0 SYSREF 1 3 0 OUT4 DAC0 CLK 1 0 0 OUT5 DAC1 SYSREF 1 3 0 OUT6 DAC1 CLK 1 0 0 OUT7 DAC2 SYSREF 1 3 0 OUT8 DAC2 CLK 1 0 0 OUT9 DAC3 SYSREF 1 3 0 OUT10 DAC3 CLK 1 0 0 Determining Output Divider Values Once the desired frequencies of the outputs are determined, the output divider values can be calculated. The ADC, DAC and FPGA clock frequencies are already Rev. A For more information www.analog.com 39 LTC6953 APPLICATIONS INFORMATION known, which leaves the two CONTROLLER outputs that drive the FOLLOWER to be described. Since OUT8 of the CONTROLLER drives the FOLLOWER input, its frequency must be equal to or larger than, the highest FOLLOWER frequency. Therefore: fCONT-OUT8 = 4000MHz Additionally, when using the software-controlled EZSync configuration in a JESD204B/C application, the CONTROLLER output which drives the FOLLOWER’s EZS_SRQ inputs should be set to the same frequency as the SYSREF frequency (or the slowest SYSREF frequency if multiple SYSREF periods are used). fCONT–OUT9 = 12.5MHz Now that all frequencies are known, use Equation 4 to determine the output divider values. The results are shown in Table 17. Table 17. Output Divide Settings for EZSync Multichip Design Example CONTROLLER The output digital delay is used to control phase relationships between outputs. The minimum delay step is ½ of a period of the input signal. For this design example, the digital delay is used to place each device’s SYSREF signal edges into a known phase relationship to its corresponding device clock, optimized for the set-up (tS) and hold time (tH) requirements for that device. Assume that the optimum SYSREF edge location for each device occurs on the first falling clock edge before the desired SYSREF valid rising clock edge. Refer to Figure 23 for an example. For EZSync multichip synchronization, the CONTROLLER output which drives the FOLLOWER input (follower-driver) must output seven pulses before the FOLLOWER outputs begin. This means that any CONTROLLER outputs which should be aligned with the FOLLOWER outputs (followersynchronous) must be delayed by the same amount of time as the seven pulses, leading to a delay offset for each of these follower-synchronous outputs (DDELFS-OS): PURPOSE FREQUENCY (MHz) DIVIDE VALUE (Mx) OUT0 ADC0 SYSREF 12.5 320 OUT1 ADC0 CLK 500 8 OUT2 ADC1 SYSREF 12.5 320 OUT3 ADC1 CLK 500 8 OUT4 ADC2 SYSREF 12.5 320 OUT5 ADC2 CLK 500 8 OUT6 ADC3 SYSREF 12.5 320 OUT7 ADC3 CLK 500 8 OUT8 To FOLLOWER IN± 4000 1 OUT9 FOLLOWER EZS_SRQ 12.5 320 OUT10 FPGA MGMT CLK 100 40 OUT0 Unused N/A N/A OUT1 FPGA SYSREF 12.5 320 OUT2 FPGA DEV CLK 125 32 OUT3 DAC0 SYSREF 12.5 320 OUT4 DAC0 CLK 4000 1 OUT5 DAC1 SYSREF 12.5 320 OUT6 DAC1 CLK 4000 1 OUT7 DAC2 SYSREF 12.5 320 DDELADC–CLK´ = DDELSYSvalid = 32 OUT8 DAC2 CLK 4000 1 DDELDAC–CLK´ = DDELSYSvalid = 32 OUT9 DAC3 SYSREF 12.5 320 OUT10 DAC3 CLK 4000 1 DDELFPGA–CLK´ = DDELSYSvalid = 32 IC OUTPUT FOLLOWER Determining Output Digital Delay Values 40 DDELFS–OS = 14 • MFD + DDELFD (8) where MFD and DDELFD are the divider value and digital delay value, respectively, of the follower-driver. In most applications, DDELFD will be set to 0. In order to calculate each output’s delay value for this design example, use the following procedure: 1. Delay all of the JESD204B/C device clocks by half of a period of the slowest JESD204B/C device clock. This delay setting is equal to the divide value of the slowest device clock because a one code digital delay equals half of an input clock cycle. Non-JESD204B/C clocks (such as the FPGA management clock) are not included in this calculation. This delay value defines the desired SYSREF valid clock edge. In this example, the slowest JESD204B/C clock is the FPGA device clock: DDELSYSvalid = MFPGACLK = 32 Rev. A For more information www.analog.com LTC6953 APPLICATIONS INFORMATION DDELADC–SYS´ = DDELSYSvalid – MADC–CLK DDELADC–SYS´ = 32 – 8 = 24 DDELDAC–SYS´ = DDELSYSvalid – MDAC–CLK DDELDAC–SYS´ = 32 – 1 = 31 DDELFPGA–SYS´ = DDELSYSvalid – MFPGA–CLK DDELFPGA–SYS´ = 32 – 32 = 0 Table 18 summarizes the DDEL settings for all outputs. Table 18. O]utput DDELx Settings for EZSync Multichip Design Example IC CONTROLLER 2. For each device clock/SYSREF pair, subtract half a device clock period from DDELSYSvalid to find the SYSREF delay. This is equivalent to subtracting the corresponding divide value of the device clock: DDELADC–CLK = DDELADC–CLK´ + DDELFS–OS DDELADC–CLK = 32 + 14 = 46 DDELADC–SYS = DDELADC–SYS´ + DDELFS–OS DDELADC–SYS = 24 + 14 = 38 DDELDAC–CLK = DDELDAC–CLK´ + 0 = 32 DDELDAC–SYS = DDELDAC–SYS´ + 0 = 31 DDELFPGA–CLK = DDELFPGA–CLK´ + 0 = 32 DDELFPGA–SYS = DDELFPGA–SYS´ + 0 = 0 Even though CONTROLLER OUT9 is only passing through the SYNC/SRQ pulse, its digital delay should be set so that its edges occur at the same time as the latest occurring SYSREF in the overall system. This is to ensure that future SYSREF requests are aligned properly. Note that the delay offset from 8 will need to be added as well since it is located on the CONTROLLER part. The latest occurring SYSREF is the DAC SYSREF, therefore: DDELOUT9 = DDELDAC–SYS + DDELFS–OS DDELOUT9 = 31 + 14 = 45 The follower-driver digital delay is set to 0 in this example: DDELFD = DDELOUT8 = 0 FOLLOWER 3. Adjust for CONTROLLER vs FOLLOWER outputs. Any CONTROLLER output that is synchronous with the FOLLOWER must have the delay offset from Equation 8 added to its DDEL value. FOLLOWER outputs need no adjustment. For this example, the ADC CLKs and SYSREFs come from the CONTROLLER: OUTPUT PURPOSE DDELx OUT0 ADC0 SYSREF 38 OUT1 ADC0 CLK 46 OUT2 ADC1 SYSREF 38 OUT3 ADC1 CLK 46 OUT4 ADC2 SYSREF 38 OUT5 ADC2 CLK 46 OUT6 ADC3 SYSREF 38 OUT7 ADC3 CLK 46 OUT8 FOLLOWER Input 0 OUT9 FOLLOWER EZS_SRQ 45 OUT10 FPGA MGMT CLK 0 OUT0 Unused N/A OUT1 FPGA SYSREF 0 OUT2 FPGA DEV CLK 32 OUT3 DAC0 SYSREF 31 OUT4 DAC0 CLK 32 OUT5 DAC1 SYSREF 31 OUT6 DAC1 CLK 32 OUT7 DAC2 SYSREF 31 OUT8 DAC2 CLK 32 OUT9 DAC3 SYSREF 31 OUT10 DAC3 CLK 32 Now that the output divider and delays have been determined, the ICs can be programmed. Status Register Programming This example will use the STAT pin to alert the system whenever the LTC6953 generates a fault condition. For the CONTROLLER and FOLLOWER, program x[3] = 1 to force the STAT pin high whenever the VCOOK flag asserts: CONTROLLER Reg01 = h08 FOLLOWER Reg01 = h08 Power and FILT Register Programming For correct operation on both CONTROLLER and FOLLOWER, all internal blocks should be enabled. Rev. A For more information www.analog.com 41 LTC6953 APPLICATIONS INFORMATION Additionally, the input signal has a sufficient slew rate and power to not need the FILTV bit: CONTROLLER Reg02 = h00 FOLLOWER Reg02 = h00 Output Power-Down Programming During initial setup and synchronization, all used outputs should be set to full power. These bits will be used later to place the ICs in a lower power mode while waiting for SYSREF requests: CONTROLLER Reg03 = h00 CONTROLLER Reg04 = h00 CONTROLLER Reg05 = h00 FOLLOWER Reg03 = h03 FOLLOWER Reg04 = h00 words, MPx and MDx, as described in Equation 1. The second register contains the control modes and the most significant bits of the digital delay control word. The third register contains the remainder of the digital delay control word, and the fourth register is the analog delay control. Both the analog delay and the output invert (OINVx) bits can be used to correct PCB layout issues such as mismatched trace lengths and differential signal crossovers, respectively. Note that the use of analog delay on clock signals will degrade jitter performance. For this example, assume the PCB is laid out in an ideal manner and no output inversions or analog delays are needed. With this information, all of registers h0C through h37 for both CONTROLLER and FOLLOWER can be programmed to the values in Table 19 and Table 20, calculated using the information in Table 24, Table 25 (with Equation 1), and Table 26. Table 19. CONTROLLER Output Register Settings for EZSync Multichip Design Example FOLLOWER Reg05 = h00 ADDR VALUE ADDR VALUE ADDR VALUE SYNC and SYSREF Global Modes Programming h0C h9C h1C h9C h2C h00 Bit EZMD controls whether the IC is an EZSync standalone/ CONTROLLER (“0”) or FOLLOWER (“1”). Bit SRQMD determines if the part is in synchronization mode (“0”) or SYSREF request mode (“1”). SYSCT programs the number of pulses for any output in pulsed SYSREF mode (# pulses = 2SYSCT, so SYSCT = 2 to achieve four pulses for this example). Using this information, register h0B for CONTROLLER and FOLLOWER can be programmed: h0D hE0 h1D hE0 h2D h80 h0E h26 h1E h26 h2E h00 h0F h00 h1F h00 h2F h00 h10 h38 h20 h38 h30 h9C h11 h80 h21 h80 h31 hC0 h12 h2E h22 h2E h32 h2D h13 h00 h23 h00 h33 h00 h14 h9C h24 h9C h34 h99 h15 hE0 h25 hE0 h35 h00 h16 h26 h26 h26 h36 h00 FOLLOWER Reg0B = h14 h17 h00 h27 h00 h37 h00 Note that the SSRQ bits will remain “0” for now, but will be used later during the synchronization and SYSREF request procedures. h18 h38 h28 h38 h19 h80 h29 h80 h1A h2E h2A h2E h1B h00 h2B h00 CONTROLLER Reg0B = h04 Output Divider, Delay and Function Programming Four registers for each output allow the outputs to be configured independently of each other. The first register controls the output divide ratio through two control 42 Rev. A For more information www.analog.com LTC6953 APPLICATIONS INFORMATION Table 20. FOLLOWER Output Register Settings for EZSync Multichip Design Example ADDR VALUE ADDR VALUE ADDR VALUE h0C h00 h1C h00 h2C h00 h0D h00 h1D h80 h2D h80 h0E h00 h1E h20 h2E h20 h0F h00 h1F h00 h2F h00 h10 h9C h20 h9C h30 h9C h11 hE0 h21 hE0 h31 hE0 h12 h00 h22 h1F h32 h1F h13 h00 h23 h00 h33 h00 h14 hF8 h24 h00 h34 h00 h15 h80 h25 h80 h35 h80 h16 h20 h26 h20 h36 h20 h17 h00 h27 h00 h37 h00 h18 h9C h28 h9C h19 hE0 h29 hE0 h1A h1F h2A h1F h1B h00 h2B h00 shown as well as the actual outputs to demonstrate the phase alignment following synchronization. Also notice that all FOLLOWER outputs will have additional delay from the CONTROLLER outputs equal to the FOLLOWER’s tPD as described in the Electrical Characteristics. Putting the ICs Into a Lower Power Mode If desired, both ICs can be placed into lower power modes while awaiting a SYSREF request. This is achieved by setting PDx = 2 for all SYSREF-defined outputs. This powers down the output driver circuitry but leaves the internal divider running and in the correct phase relationship to the clocks. Performing a SYSREF Request To produce SYSREF pulses, write a “1” to SRQMD and take the parts out of low power mode (if used) by writing all the SYSREF output PDx bits to “0”. Wait 50µs to allow circuitry to power up. Send the SYSREF request by writing a “1” to the CONTROLLER SSRQ bit in Reg0B: Synchronization The outputs in this example are now running at the desired frequency, but have random phase relationships with each other. Synchronization forces the outputs to run at known and repeatable phases and can be achieved in this example either externally, by driving the CONTROLLER’s EZS_SRQ± pins or internally, with the CONTROLLER’s SSRQ bit in Reg0B. Since the part was just programmed, set the SSRQ bit to “1” and hold the EZS_SRQ± pins low: CONTROLLER Reg0B = h05 After waiting a minimum of 1ms, set SSRQ back to “0”: CONTROLLER Reg0B = h04 CONTROLLER Reg0B = h05 After waiting a minimum of 1ms, write Reg0B again: CONTROLLER Reg0B = h04 Place the ICs back into low power mode if desired by writing a “0” to SRQMD and setting PDx = 2 for all SYSREFdefined outputs. After the rising edge of the SYSREF request, the SYSREF outputs will pulse four times and then return to a “0” state as shown in Figure 28. Note that the FOLLOWER SYSREF pulses may not start and stop at exactly the same time as the CONTROLLER’s. This is not an issue, since the SYSREF edges will still be aligned correctly. Once the internal synchronization process completes, the outputs will be aligned as shown in Figure 27. Note that the internal divider behavior for the muted SYSREF outputs is Rev. A For more information www.analog.com 43 LTC6953 APPLICATIONS INFORMATION EZS_SRQ or SSRQ BIT CONTROLLER OUTPUTS FOLLOWER DRIVER (OUT8) SYNC PASS-THROUGH (OUT9) ADC DEVICE CLOCKS (OUT1, 3, 5 AND 7) ADC SYSREFs (MUTED OUT0, 2, 4 AND 6) INTERNAL ADC SYSREF DIVIDERS (MUTED OUT0, 2, 4 AND 6) FPGA MANAGEMENT CLOCK (OUT 2) NOT SYNCHRONIZED, PHASE UNDETERMINED tPD FOLLOWER OUTPUTS DAC DEVICE CLOCKS (OUT4, 6, 8 AND 10) DAC SYSREFs (MUTED OUT3, 5, 7 AND 9) INTERNAL DAC SYSREF DIVIDERS (MUTED OUT3, 5, 7 AND 9) FPGA DEVICE CLOCK (OUT2) FPGA SYSREF (MUTED OUT1) INTERNAL FPGA SYSREF DIVIDER (MUTED OUT1) 6953 F27 SYSREF VALID CLOCK EDGE Figure 27. Outputs After Synchronization for the EZSync Multichip Design Example (SRQMD = 0) EZS_SRQ OR SSRQ BIT CONTROLLER OUTPUTS FOLLOWER DRIVER (OUT8) 4000MHz SYSREQ PASS-THROUGH (OUT9) ADC DEVICE CLOCKS (OUT1, 3, 5 AND 7) 500MHz ADC SYSREFs (OUT0, 2, 4 AND 6) FPGA MANAGEMENT CLOCK (OUT10) 100MHz FOLLOWER OUTPUTS DAC DEVICE CLOCKS (OUT4, 6, 8 AND 10) 4000MHz DAC SYSREFs (OUT3, 5, 7 AND 9) FPGA DEVICE CLOCK (OUT2) 125MHz FPGA SYSREF (OUT1) 6953 F28 Figure 28. Outputs After SYSREF Request for the EZSync Multichip Design Example (SRQMD = 1) 44 Rev. A For more information www.analog.com LTC6953 APPLICATIONS INFORMATION JESD204B/C DESIGN EXAMPLE USING ParallelSync This design example consists of a system of eight JESD204B/C analog-to-digital converters (ADCs) and a JESD204B/C compatible FPGA. All of the ADCs and the FPGA require JESD204B/C subclass 1 device clocks and SYSREFs, and the FPGA requires an extra management clock. Additionally, the ADCs require low noise clocks of less than 100fs total RMS jitter. This leads to a total of 19 separate signals to generate, with frequencies listed below. For this example, the SYSREF frequencies for all devices are the same and should output four pulses upon a SYSREF request rising edge: fADC–CLK = 294.912MHz fFPGA–CLK = 147.456MHz and LTC6952 #2). Figure 29 shows a block diagram of the full system. Note that OUT0 of the reference LTC6953 is driving the REF± inputs of LTC6952 #1 and OUT1 is driving the EZS_SRQ± pins of LTC6952 #1. Likewise, OUT2 of the reference LTC6953 is driving the REF± inputs of LTC6952 #2 and OUT3 is driving the EZS_SRQ± pins of LTC6952 #2. All outputs in this configuration are low RMS jitter (~75fs ADC SNR Method). Although the ParallelSync design example has been shown here for reference, most of the design work for it involves the LTC6952. Please refer to the LTC6952 data sheet for detailed instructions on programming the ICs for this example. SUPPLY BYPASSING AND PCB LAYOUT GUIDELINES fFPGA–MGMT = 98.304MHz fSYSREF = 9.216MHz To determine which multichip configuration to use, we utilize the flowchart in Figure 10. This example has nine total JESD204B/C device clock/SYSREF pairs, eight of which need to be less than 100fs total jitter. We also need one additional non-low noise standalone clock for the FPGA. Therefore: TP = 9 LNP = 8 TS = 1 LNS = 0 Based on these inputs, Figure  10 suggests using the ParallelSync multichip protocol with LTC6953 reference distribution topology shown in Figure 9, using one LTC6953 as the reference distribution chip (REF LTC6953) and two LTC6952s in parallel to generate the clocks (LTC6952 #1 Care must be taken when creating a PCB layout to minimize power supply decoupling and ground inductances. All power supply V+ pins should be bypassed directly to the ground plane using either a 0.01µF or a 0.1µF ceramic capacitor as called out in the Pin Functions section as close to the pin as possible. Multiple vias to the ground plane should be used for all ground connections, including to the power supply decoupling capacitors. The package’s exposed pad is a ground connection, and must be soldered directly to the PCB land. The PCB land pattern should have multiple thermal vias to the ground plane for both low ground inductance and also low thermal resistance (see Figure 30 for an example). An example of grounding for electrical and thermal performance can be found on the DC2610 layout. Rev. A For more information www.analog.com 45 LTC6953 APPLICATIONS INFORMATION VCO SYSREF ADC0 CLK LF(S) EZS_SRQ± M0 REF± LTC6953 REFERENCE DISTRIBUTION SSRQ BIT VCO± CP REF OSC RDIV NDIV M1 M2 M4 SYNC AND SYSREF CTRL EZS_SRQ± M10 M9 M8 M3 M5 M7 M6 SYSREF ADC1 CLK SYSREF ADC2 CLK LTC6952 #1 SYSREF ADC3 IN± M10 M9 M8 CLK SYNC AND SYSREF CTRL M7 M6 M0 M4 SYSREF LF(S) M1 M0 M3 REF± RDIV NDIV M1 M2 M10 M9 M8 M3 M4 SYNC AND SYSREF CTRL EZS_SRQ± FPGA DEV CLK VCO± CP M2 M5 MGMT CLK VCO M5 M7 M6 SYSREF ADC4 CLK SYSREF ADC5 CLK LTC6952 #2 SYSREF ADC6 CLK INPUT/OUTPUT TERMINATIONS AND AC-COUPLING CAPS NOT SHOWN. SYSREF ADC7 CLK 6953 F29 Figure 29. Block Diagram for JESD204B/C ParallelSync with LTC6953 Reference Distribution Design Example 46 Rev. A For more information www.analog.com LTC6953 APPLICATIONS INFORMATION 6953 F30 Figure 30. PCB Top Metal Layer Pin and Exposed Ground Pad Design. Pin 41 is Signal Ground and Connected Directly to the Exposed Pad Metal ADC CLOCKING AND JITTER REQUIREMENTS Adding noise directly to a clean signal clearly reduces its signal to noise ratio (SNR). In data acquisition applications, digitizing a clean signal with a noisy clock signal also degrades the SNR. This issue is best explained in the time domain using jitter instead of phase noise. For this discussion, assume that the jitter is white (flat with frequency) and of Gaussian distribution. Figure 31 shows a sine wave signal entering a typical data acquisition circuit composed of an ADC, an input signal amplifier and a sampling clock. Also shown are three signal sampling scenarios for sampling the sine wave at its zero crossing. In the first scenario, a perfect sine wave input is buffered by a noiseless amplifier to drive the ADC. Sampling is performed by a perfect, zero jitter clock. Without any added noise or sampling clock jitter, the ADC’s digitized output value is very clearly determined and perfectly repeatable from cycle to cycle. In the second scenario, a perfect sine wave input is buffered by a noisy amplifier to drive the ADC. Sampling is performed by a perfect, zero jitter clock. The added noise results in an uncertainty in the digitized value, causing an error term which degrades the SNR. The degraded SNR in this scenario, from adding noise to the signal, is expected. In the third scenario, a perfect sine wave input is buffered by a noiseless amplifier to drive the ADC. Sampling is performed by a clock signal with added jitter. Note that as the signal is slewing, the jitter of the clock signal leads to an uncertainty in the digitized value and an error term just as in the previous scenario. Again, this error term degrades the SNR. A real-world system will have both additive amplifier noise and sample clock jitter. Once the signal is digitized, determining the root cause of any SNR degradation—amplifier noise or sampling clock jitter—is essentially impossible. Degradation of the SNR due to sample clock jitter only occurs if the analog input signal is slewing. If the analog input signal is stationary (DC) then it does not matter when in time the sampling occurs. Additionally, a faster slewing input signal yields a greater error (more noise) than a slower slewing input signal. Rev. A For more information www.analog.com 47 LTC6953 APPLICATIONS INFORMATION SINE WAVE INPUT SIGNAL AMP ADC BITS SAMPLING CLOCK SINE WAVE INPUT SIGNAL WITH NOISELESS AMP VSAMPLE SINE WAVE INPUT SIGNAL WITH NOISY AMP ∆V = VERROR SINE WAVE INPUT SIGNAL WITH NOISELESS AMP ∆V = VERROR tJ PERFECT SAMPLING CLOCK PERFECT SAMPLING CLOCK 6953 F31 SAMPLING CLOCK WITH ADDED JITTER Figure 31. A Typical Data Acquisition Circuit Showing the Sampling Error Effects of a Noisy Amplifier and a Jittery Sampling Clock Figure 32 demonstrates this effect. Note how much larger the error term is with the fast slewing signal than with the slow slewing signal. To maintain the data converter’s SNR performance, digitization of high input frequency signals requires a clock with much less jitter than applications with lower frequency input signals. FAST SINE WAVE SLOW SINE WAVE ∆V = VERROR(FAST) ∆V = VERROR(SLOW) tJ Quantitatively, the actual sample clock jitter requirement for a given application is calculated as: –SNR dB Figure 32. Fast and Slow Sine Wave Signals Sampled with a Jittery Clock It is important to note that the frequency of the analog input signal determines the sample clock’s jitter requirement. The actual sample clock frequency does not matter. Many ADC applications that undersample high frequency signals have especially challenging sample clock jitter requirements. (9) Where fSIG is the highest frequency signal to be digitized expressed in Hz, SNRdB is the SNR requirement in decibels and tJ(TOTAL) is the total RMS jitter in seconds. The total jitter is the RMS sum of the ADC’s aperture jitter and the sample clock jitter calculated as: 6953 F32 10 20 t J(TOTAL) = 2 • π • fSIG t J(TOTAL) = t J(CLK) 2 + t J(ADC)2 (10) Alternatively, for a given total jitter, the attainable SNR is calculated as follows: (11) SNR dB = –20log10 (2 • π • fSIG • t J(TOTAL) ) These calculations assume a full-scale sine wave input signal. If the input signal is a complex, modulated signal with a moderate crest factor, the peak slew rate of the signal may be lower and the sample clock jitter requirement may be relaxed. The previous discussion was useful for gaining an intuitive feel for the SNR degradation due to sampling clock jitter. 48 Rev. A For more information www.analog.com LTC6953 APPLICATIONS INFORMATION These calculations are also theoretical. They assume a noiseless ADC with infinite resolution. All realistic ADCs have both added noise and a resolution limit. The limitations of the ADC must be accounted for to prevent overspecifying the sampling clock. the ADC analog input. A non-jitter dominated SNR measurement (SNRbase) is created by applying a very low amplitude (or low frequency) sinewave to the ADC analog input.  The total clock jitter (tJ(TOTAL)) can be calculated using Equation 12. Figure 33 plots the previous equations and provides a simple, quick way to estimate the sampling clock jitter requirement for a given input signal or the expected SNR performance for a given sample clock jitter. 124 SNR (dB) 94 84 74 54 44 34 – SNRBASE SNRJITTER – 10 10 –10 10 2 fIN (12) Assuming the inherent aperture jitter of the ADC (tJ(ADC)) is known, the jitter of the clock generator (tJ(CLK)) is obtained using Equation 10. 104 64 TJ(TOTAL) = TOTAL CLOCK JITTER (RMS) 114 1 log10 10 2 ADC SAMPLE CLOCK INPUT DRIVE REQUIREMENTS 10fs 20fs 50fs 100fs 200fs 500fs 1ps 24 0.01 0.1 1 10 FREQUENCY OF FULL–SCALE INPUT SIGNAL (GHz) 6953 F33 Figure 33. SNR vs Input Signal Frequency vs Sample Clock Jitter MEASURING CLOCK JITTER INDIRECTLY USING ADC SNR For some applications, integrating a clock generator’s phase noise within a defined offset frequency range (i.e., 12kHz to 20MHz) is sufficient to calculate the clock’s impact on the overall system performance. In these situations, the RMS jitter can be calculated from a phase noise measurement. However, other applications require knowledge of the clock’s phase noise at frequency offsets that exceed the capabilities of today’s phase noise analyzers. This limitation makes it difficult to calculate jitter from a phase noise measurement. The RMS jitter of an ADC clock source can be indirectly measured by comparing a jitter dominated SNR measurement to a non-jitter dominated SNR measurement.  A jitter dominated SNR measurement (SNRjitter) is created by applying a low jitter, high frequency full-scale sinewave to Modern high speed, high resolution ADCs are incredibly sensitive components able to match or exceed laboratory instrument performance in many regards. Noise or interfering signals on the analog signal input, the voltage reference or the sampling clock input can easily appear in the digitized data. To deliver the full performance of any ADC, the sampling clock input must be driven with a clean, low jitter signal. Figure 34 shows a simplified version of a typical ADC sample clock input. In this case the input pins are labeled ENC± for Encode while some ADCs label the inputs CLK± for Clock. The input is composed of a differential limiting amplifier stage followed by a buffer that directly controls the ADC’s track and hold stage. The sample clock input amplifier also benefits from a fast slewing input signal as the amplifier has noise of its VDD 1.2V ENC+ 10k ENC– 6953 F34 Figure 34. Simplified Sample Clock Input Circuit Rev. A For more information www.analog.com 49 LTC6953 APPLICATIONS INFORMATION own. By slewing through the crossover region quickly, the amplifier noise creates less jitter than if the transition were slow. As shown in Figure 34, the ADC’s sample clock input is typically differential, with a differential sampling clock delivering the best performance. Figure 34 also shows the sample clock input having a different common mode input voltage than the LTC6953’s CML outputs. Most ADC applications will require AC-coupling to convert between the two common mode voltages. CLK+ Z0 OUTx – Z0 ADC, DAC, OR FPGA CLK– OUTx + Z0 CLK+ LTC6953 100Ω LTC6953 OUTx – 100Ω Z0 ADC, DAC, OR FPGA CLK– DEVICES THAT CAN ACCEPT A 2.3V COMMON MODE SIGNAL AC-COUPLED INTO LVDS OR DEVICES REQUIRING A SELFBIASED INPUT 6953 F36 Figure 36. OUTx CML Connections to Device Clock Inputs (Z0 = 50Ω) USING THE LTC6953 TO DRIVE DC-COUPLED SYSREF INPUTS TRANSMISSION LINES AND TERMINATION Interconnection of high speed signaling with fast rise and fall times requires the use of transmission lines with properly matched termination. The transmission lines may be stripline, microstrip or any other design topology. A detailed discussion of transmission line design is beyond the scope of this data sheet. Any mismatch between the transmission line’s characteristic impedance and the terminating impedance results in a portion of the signal reflecting back toward the other end of the transmission line. In the extreme case of an open or short circuit termination, all of the signal is reflected back. This signal reflection leads to overshoot and ringing on the waveform. Figure 35 shows the preferred method of farend termination of the transmission line. ZO 100Ω ZO 6953 F35 Figure 35. Far-End Transmission Line Termination (Z0 = 50Ω) USING THE LTC6953 TO DRIVE DEVICE CLOCK INPUTS The LTC6953’s CML outputs are designed to interface with standard CML or LVPECL devices while driving transmission lines with far-end termination. Figure 36 shows DC-coupled and AC-coupled output configurations for the CML outputs. Note that some receiver devices have the 100Ω termination resistor internal to the part, in which case the external 100Ω resistor is unnecessary. 50 OUTx + For JESD204B/C applications, the SYSREF signal would ideally be DC-coupled from the LTC6953 to the data converter or FPGA as shown in Figure 37. This is possible for receiver devices that can accept a 2.3V common mode input signal. Note that some receiver devices have the 100Ω termination resistor internal to the part, in which case the external 100Ω resistor is unnecessary. OUTx + LTC6953 OUTx – SYSREF + Z0 100Ω Z0 ADC, DAC, OR FPGA SYSREF – DEVICES THAT CAN ACCEPT A 2.3V COMMON MODE SIGNAL 6953 F37 Figure 37. OUTx CML DC-Coupled Connections to SYSREF Inputs Use the following procedure to achieve correct JESD204B/C SYSREF behavior for DC-coupled SYSREFs in any mode. These methods assume that the SYSREF outputs have already been synchronized and that the SYSREF output drivers have been disabled for power savings (PDx = 2). DC-Coupled SYSREFs (MODEx = 0, 1 or 3) 1. Enable the LTC6953 SYSREF output drivers by setting PDx = 0 and set SRQMD = 1. 2. Set the receiver device to accept SYSREFs. 3. Set SSRQ or the EZS_SRQ inputs to “1” for at least 1ms, then set back to “0”. Rev. A For more information www.analog.com LTC6953 APPLICATIONS INFORMATION 4. After the SYSREFs have been accepted by the receiver device, set the device to stop accepting SYSREFs. 5. Disable the LTC6953 SYSREF output drivers by setting PDx = 2 and set SRQMD = 0. USING THE LTC6953 TO DRIVE AC-COUPLED SYSREF INPUTS IN CONTINUOUS OR GATED MODE Some converters cannot accept a 2.3V common mode CML signal. In this situation, the SYSREF must be AC-coupled. AC-coupling complicates the usage of SYSREF since it is generally not continuously operational, leading to long settling time requirements before a SYSREF is requested. However, AC-coupling on SYSREF can be accomplished by using the connections shown in Figure 38 for continuous or gated SYSREF pulses (MODEx = 0 or 1). Note that some receiver devices have the 100Ω termination resistor internal to the part, in which case the external 100Ω resistor is unnecessary for continuous or gated SYSREFs. OUTx + CAC Z0 ADC, DAC, OR FPGA SYSREF + RDIFF /2 CAC OUTx – RCM 100Ω LTC6953 VCM RDIFF /2 Z0 Continuous or Gated SYSREFs (MODEx = 0 or 1) 1. Enable the LTC6953 SYSREF output drivers by setting PDx = 0 and set SRQMD = 1. 2. If gated SYSREFs (MODEx = 1) are being used, set SSRQ or the EZS_SRQ inputs to “1”. 3. Wait for a settling period of at least tsettleC. 4. Set the receiver device to accept SYSREFs. 5. After the SYSREFs have been accepted by the receiver device, set the device to stop accepting SYSREFs. 6. If gated SYSREFs (MODEx = 1) are being used, set SSRQ or the EZS_SRQ inputs to “0”. 7. Disable the LTC6953 SYSREF output drivers by setting PDx = 2 and set SRQMD = 0. USING THE LTC6953 TO DRIVE AC-COUPLED SYSREF INPUTS IN PULSED MODE If AC-coupling is required for pulsed SYSREF applications (MODEx = 3), the connections shown in Figure 39 can be used. Note that some receiver devices have the 100Ω termination resistor internal to the part. In this situation, the use of AC-coupled, pulsed SYSREFs is not recommended. SYSREF – 6953 F38 Figure 38. OUTx CML AC-Coupled Connections to SYSREF Inputs for Continuous or Gated Mode Operation Settling time for continuous or gated SYSREF connections is determined by the AC-coupling capacitors (CAC), and both the differential and common mode input resistances of the receiver device (RDIFF and RCM): ⎛ ⎞ R t settleC ≅ 10 • ⎜2RCM + DIFF ⎟ • C AC ⎝ 2 ⎠ CAC OUTx + R1 Z0 RDIFF /2 RCM 100Ω LTC6953 VCM RDIFF /2 CAC OUTx – ADC, DAC, OR FPGA + SYSREF SYSREF – Z0 VDD R2 6953 F39 Figure 39. OUTx CML AC-Coupled Connections to SYSREF Inputs for Pulsed Mode Operation Use the following procedure to achieve correct JESD204B/C SYSREF behavior for AC-coupled continuous or gated SYSREFs. These methods assume that the SYSREF outputs have already been synchronized and that the SYSREF output drivers have been disabled for power savings (PDx = 2). The purpose of R1 and R2 in Figure 39 is to force an offset at the SYSREF inputs equivalent to a CML logic “0” when the SYSREF output is not active. The resistors’ values are determined by the supply voltage (VDD) and the receiver device’s input common mode voltage (VCM) Rev. A For more information www.analog.com 51 LTC6953 APPLICATIONS INFORMATION and differential input resistance (RDIFF). Use Equation 14 to calculate R1 and Equation 15 to calculate R2. ⎡V ⎤ R1 = RDIFF • ⎢ CM – 0.5⎥ ⎣ 0.44 ⎦ (14) ⎡V – V ⎤ R 2 = RDIFF • ⎢ DD CM – 0.5⎥ ⎣ 0.44 ⎦ (15) For receiver devices with internal 100Ω terminations, the values of R1 and R2 can be very small and will affect the overall termination impedance, leading to undesirable impedance mismatch. For this reason, the use of pulsed SYSREFs (MODEx = 3) AC-coupled into receiver parts with internal 100Ω terminations is not recommended. Settling time for pulsed SYSREF connections (Figure 39) is approximately determined by the AC-coupling capacitors (CAC), both the differential and common mode input resistance of the receiver device (RDIFF and RCM), and resistors R1 and R2: ⎛R • ROS ⎞ t settleP ≅ 10 • ⎜ DEV ⎟ • C AC ⎝ RDEV + ROS ⎠ 2RCM +RDIFF 2 ROS = MINIMUM(R1,R 2 ) 4. Set SSRQ or the EZS_SRQ inputs to “1” for at least 1ms, then set back to “0”. 5. Set the receiver device to stop accepting SYSREFs. 6. Disable the LTC6953 SYSREF output drivers by setting PDx = 2 and set SRQMD = 0. MEASURING DIFFERENTIAL SPURIOUS SIGNALS USING SINGLE-ENDED TEST EQUIPMENT Using a spectrum analyzer to measure spurious signals on the single-ended output of a clock generation chip will give pessimistic results, particularly for outputs that approximate square waves. There are two reasons for this. (16) First, since the spurious energy is often an AC signal superimposed on the power supply, a differential output will reject the spurs to within the matching of the positive and negative outputs. Observing only one side of the differential output will provide no rejection. (17) Second, and most importantly, the spectrum analyzer will display all of the energy at its input, including amplitude modulation that occurs at the top and bottom pedestal voltage of the square wave. However, only amplitude modulation near a zero crossing will affect the clock. where: RDEV = 3. Set the receiver device to accept SYSREFs. For pulsed mode SYSREFs to work correctly with AC-coupling, tsettleP must be greater than 1000/fSYSREF, where fSYSREF is the frequency of the SYSREF pulses. Use the following procedure to achieve correct JESD204B/C SYSREF behavior for AC-coupled pulsed SYSREFs. These methods assume that the SYSREF outputs have already been synchronized and that the SYSREF output drivers have been disabled for power savings (PDx = 2). The best way to remove this measurement error is to drive the clock generator output differentially into a limiting buffer on a separate clean power supply. One of the differential outputs of the limiting buffer can then connect to a spectrum analyzer to correctly measure the spurious energy. An example of this technique using the LTC6953 OUTx + LTC6953 OUTx – Pulsed SYSREFs (MODEx = 3) IN+ 100Ω OUTx + LTC6955 IN – OUTx – 6953 F40 1. Enable the LTC6953 SYSREF output drivers by setting PDx = 0 and set SRQMD = 1. SPECTRUM ANALYZER 50Ω Figure 40. Example of Spurious Measurement Technique 2. Wait for a settling period of at least tsettleP. 52 Rev. A For more information www.analog.com LTC6953 TYPICAL APPLICATIONS ParallelSync Multichip Synchronization with Request Pass-Through STAGE 2 STAGE 1 1µF OUT2+ OUT2– OUT3+ – TO DAUGHTER CARD #2 OUT4+ OUT4– OUT5+ OUT5– TO DAUGHTER CARD #3 OUT6+ OUT6– OUT7+ OUT7– TO DAUGHTER CARD #4 OUT8+ OUT8– OUT9+ OUT9– TO DAUGHTER CARD #5 OUT3 1µF IN 1µF + 61.9Ω IN– EZS_SRQ+ EZS_SRQ– 100Ω 100Ω REF – EZS_SRQ+ 100Ω 48.7Ω 33nF 0.1µF CRYSTEK CVCO55CC4000-4000 0.1µF CP OUT0+ 12.5MHz SYSREF OUT0– OUT1+ 500MHz CLOCK OUT1– OUT2+ 12.5MHz SYSREF OUT2– OUT3+ 500MHz CLOCK OUT3– OUT4+ 12.5MHz SYSREF OUT4– OUT5+ 125MHz CLOCK OUT5– OUT6+ 100MHz CLOCK OUT6– OUT7+ 12.5MHz SYSREF OUT7– OUT8+ 4GHz CLOCK – OUT8 0.47µF 30Ω VCO+ 75Ω VCO– VTUNE CRYSTEK CCHD-575-25-100 100MHz REF OSC EZS_SRQ– 22nF 48.7Ω 1.2µF OUT10+ OUT10– 1µF REF + SSRQ PASS THRU OUT1 LTC6953 LTC6952 1µF 100MHz REF CLK OUT0+ OUT0 – OUT1+ – OUT9+ 12.5MHz SYSREF OUT9– OUT10+ 4GHz CLOCK – OUT10 DAUGHTER CARD #1 DAUGHTER CARD #2 DAUGHTER CARD #3 DAUGHTER CARD #4 DAUGHTER CARD #5 6953 TAO3a INITIAL SETUP: PROGRAM LTC6952 AND LTC6953 REGISTERS SETTINGS CREATED FROM THE LTC6952Wizard. STEP 1: SYNCHRONIZE STAGE 1 REFERENCE SIGNALS STEP 2: SYNCHRONIZE STAGE 2 OUTPUT SIGNALS STEP 3: SEND SYSREF REQUEST STEP 4: OPTIONAL REDUCE POWER A) EZSync: TOGGLE STAGE 1 LTC6953 SSRQ BIT A) SET STAGE 1 LTC6953 SRQMD = 1 A) POWER UP LTC6952 SYSREF OUTPUTS A) POWER DOWN LTC6952 SYSREF OUTPUTS B) OPT: FINE ALIGNMENT, ADJUST STAGE 1 ADEL BITS B) ParallelSync, TOGGLE STAGE 1 LTC6953 SSRQ BIT B) SET LTC6952 SRQMD = 1 B) SET STAGE 1 LTC6953 AND LTC6952 SRQMD = 0 C) SEND SYSREF, TOGGLE STAGE 1 LTC6953 SSRQ BIT Step 1: Reference Alignment at Daughter Card Inputs CARD #1 CARD #2 CARD #3 CARD #4 CARD #5 STAGE 1 ADEL ADJUSTMENTS REF EDGE ALIGNED < ±5.5ps (ADJUSTS FOR PART, CABLE AND PCB MISMATCH) 5ns/DIV Step 2: ParallelSync Multichip Clock Alignment OUT8: 4GHz CARD #1 OUT0: SYSREF 12.5MHz OUT1: 500MHz CARD #1 OUT1: CLOCK 500MHz OUT8: 4GHz CARDS #2–5 OUT7: SYSREF 12.5MHz 6953 TAO3b 6953 TAO3c 500ps/DIV Step 3: SYSREF Pulses –100 PHASE NOISE (dBc/Hz) 6953 TAO3e 500ps/DIV 6953 TA03d Stage 2 LTC6952 Phase Noise vs Stage 1 LTC6953 ADEL Setting fOUT = 4GHz, Mx = 1 RMS JITTER = 73fs EQUIVALENT ADC SNR METHOD –110 SYSREF 300mV/DIV SYSREF VALID CLOCK EDGE OUT8: CLOCK 4GHz OUT1: 500MHz CARDS #2–5 100ns/DIV Step 3: SYSREF SYSREFAlignment Alignment Step 3: –120 –130 –140 –150 –160 STAGE 1 ADEL = 0 STAGE 1 ADEL = 31 STAGE 1 ADEL = 63 –170 –180 1k 10k 100k 1M OFFSET FREQUENCY (Hz) 10M 40M 6953 TAO3f Rev. A For more information www.analog.com 53 LTC6953 TYPICAL APPLICATIONS Generation of Up to 125 ADC Clock/SYSREF Pairs Using a Three-Stage Synchronization Architecture: Schematics STAGE 3 STAGE 2 LTC6952 #1 OUT0± OUT1± LTC6952 #2 OUT2± OUT3± LTC6952 #3 OUT4± OUT5± LTC6952 #4 OUT6± OUT7± LTC6952 #5 OUT8± OUT9± STAGE 1 LTC6953 #1 STAGE 3 STAGE 2 LTC6953 #3 LTC6953 IN± OUT0± OUT4± IN± EZS_SRQ± OUT1± OUT5± EZS_SRQ± ± OUT10 OUT0± OUT1± LTC6952 #11 OUT2± OUT3± LTC6952 #12 OUT4± OUT5± LTC6952 #13 OUT6± OUT7± LTC6952 #14 OUT8± OUT9± LTC6952 #15 OUT10 LTC6952 #6 LTC6952 #7 OUT2± OUT3± LTC6952 #8 OUT4± OUT5± LTC6952 #9 OUT6± OUT7± LTC6952 #10 OUT8± OUT9± OUT8± OUT9± OUT10± OUT10± LTC6953 #4 IN± OUT2± OUT6± IN± EZS_SRQ± OUT3± OUT7± EZS_SRQ± LTC6953 #5 1µF IN+ 1µF 100Ω 61.9Ω IN– CRYSTEK CCHD-575-25-100 100MHZ REF OSC EZS_SRQ+ EZS_SRQ– OUT8± IN± OUT9± EZS_SRQ± OUT10± REF ± EZS_SRQ± FROM STAGE 2 30Ω 0.1µF LTC6952 #11 OUT0± OUT1± LTC6952 #16 OUT2± OUT3± LTC6952 #17 OUT4± OUT5± LTC6952 #18 OUT6± OUT7± LTC6952 #19 LTC6952 #20 75Ω 0.1µF LTC6952 #21 OUT2± OUT3± LTC6952 #22 OUT4± OUT5± LTC6952 #23 OUT6± OUT7± LTC6952 #24 OUT8± OUT9± LTC6952 #25 OUT7± 12.5MHz SYSREF OUT8± 4GHz CLOCK VCO – RF OUT9± 12.5MHz SYSREF OUT10± 4GHz CLOCK CP 48.7Ω 33nF 22nF 48.7Ω 1.2µF OUT0± OUT1± OUT4± 12.5MHz SYSREF OUT5± 125MHz CLOCK OUT6± 100MHz CLOCK CRYSTEK CVCO55CC4000-4000 VTUNE OUT0± 12.5MHz SYSREF OUT1± 500MHz CLOCK OUT2± 12.5MHz SYSREF OUT3± 500MHz CLOCK VCO+ ± OUT0± OUT1± LTC6953 #2 STAGE 3 DETAILS 0.47µF OUT10± 6953 TAO4 STAGE 1 LTC6953 OUTPUTS STAGE 2 LTC6953 INPUTS OUT(x)+ OUT(x)– DC-COUPLED 54 OUT(x)+ – OUT(x)– IN EZS_SRQ+ DC-COUPLED OUT(x + 1)– IN+ 160Ω OUT(x + 1)+ 100Ω STAGE 2 LTC6953 OUTPUTS EZS_SRQ– STAGE 3 LTC6952 INPUTS 1µF 100Ω 1µF OUT(x + 1)+ OUT(x + 1)– REF + REF – EZS_SRQ+ DC-COUPLED 100Ω EZS_SRQ– Rev. A For more information www.analog.com LTC6953 TYPICAL APPLICATIONS Generation of Up to 125 ADC Clock/SYSREF Pairs Using a Three-Stage Synchronization Architecture: Synchronization Procedure and Measurement Results Initial Setup: Program LTC6952 and LTC6953 Registers Settings Created from the LTC6952Wizard. Step 1: Synchronize Stage 1 and 2 Reference Signals A) EZSync: Toggle Stage 1 LTC6953 SSRQ Bit B) OPT: Fine Alignment, Adjust Stage 2 ADEL Bits Step 2: Synchronize Stage 3 Output Signals A) Set Stage 1 and 2 LTC6953 SRQMD = 1 B) ParallelSync: Toggle Stage 1 LTC6953 SSRQ Bit Step 3: Send SYSREF Request A) Power Up LTC6952 SYSREF Outputs B) Set LTC6952 SRQMD = 1 C) Send SYSREF: Toggle Stage 1 LTC6953 SSRQ Bit Step 4: Optional Reduce Power A) Power-Down LTC6952 SYSREF Outputs B) Set Stage 1 and 2 LTC6953 and LTC6952 SRQMD = 0 Step 2: ParallelSync Multichip Clock Alignment Step 1: Reference Reference AlignmentAlignment LTC6952 #13 OUT8: 4GHz LTC6952 #13 REF INPUT OUT0: SYSREF 12.5MHz OUT1: 500MHz LTC6952 #23 REF INPUT STAGE 2 ADEL ADJUSTMENTS REF EDGE ALIGNED < ±5.5ps (ADJUSTS FOR PART, CABLE AND PCB MISMATCH) 5ns/DIV SYSREF VALID CLOCK EDGE OUT1: CLOCK 500MHz LTC6952 #23 OUT8: 4GHz OUT7: SYSREF 12.5MHz OUT1: 500MHz OUT8: CLOCK 4GHz 6953 TAO5a 6953 TAO5b 500ps/DIV 500ps/DIV 6953 TAO5c Stage 2 LTC6952 Phase Noise vs Stage 1 LTC6953 ADEL Setting fOUT = 4GHz, Mx = 1 Step 3: SYSREF Pulses –100 RMS JITTER = 73fs EQUIVALENT ADC SNR METHOD PHASE NOISE (dBc/Hz) –110 SYSREF 300mV/DIV 100ns/DIV Step 3: SYSREF SYSREFAlignment Alignment Step 3: –120 –130 –140 –150 –160 6953 TAO5d STAGE 2 ADEL = 0 STAGE 2 ADEL = 31 STAGE 2 ADEL = 63 –170 –180 1k 10k 100k 1M OFFSET FREQUENCY (Hz) 10M 40M 6953 TA05e Rev. A For more information www.analog.com 55 LTC6953 PACKAGE DESCRIPTION UKG Package 52-Lead Plastic QFN (7mm × 8mm) (Reference LTC DWG # 05-08-1729 Rev Ø) 7.50 ±0.05 6.10 ±0.05 5.50 REF (2 SIDES) 0.70 ±0.05 6.45 ±0.05 6.50 REF 7.10 ±0.05 8.50 ±0.05 (2 SIDES) 5.41 ±0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 7.00 ±0.10 (2 SIDES) 0.75 ±0.05 0.00 – 0.05 R = 0.115 TYP 5.50 REF (2 SIDES) 51 52 0.40 ±0.10 PIN 1 TOP MARK (SEE NOTE 6) 1 2 PIN 1 NOTCH R = 0.30 TYP OR 0.35 × 45°C CHAMFER 8.00 ±0.10 (2 SIDES) 6.50 REF (2 SIDES) 6.45 ±0.10 5.41 ±0.10 R = 0.10 TYP TOP VIEW 0.200 REF 0.00 – 0.05 0.75 ±0.05 (UKG52) QFN REV Ø 0306 0.25 ±0.05 0.50 BSC BOTTOM VIEW—EXPOSED PAD SIDE VIEW NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 56 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE Rev. A For more information www.analog.com LTC6953 REVISION HISTORY REV DATE DESCRIPTION A 1/20 Corrected equations 14 and 15 PAGE NUMBER 52 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license For is granted implication or otherwise under any patent or patent rights of Analog Devices. more by information www.analog.com 57 LTC6953 TYPICAL APPLICATION EZSync Multichip Synchronization with Request Pass-Through 1µF STAGE 1 1µF 100Ω REF+ 49.9Ω CRYSTEK CCHD-575-25-100 100MHZ REF OSC 1µF REF – EZS_SRQ+ EZS_SRQ– 48.7Ω 33nF CP 22nF 48.7Ω 1.2µF 0.47µF 0.1µF VTUNE LTC6952 0.1µF 30Ω VCO+ 75Ω VCO– CRYSTEK CVCO55CC4000-4000 STAGE 2 4GHz CLK OUT0+ OUT0– OUT1+ OUT1– IN+ 160Ω OUT2+ OUT2– OUT3+ OUT3– SSRQ PASS-THRU TO DAUGHTER CARD #2 OUT4+ OUT4– OUT5+ OUT5– TO DAUGHTER CARD #3 OUT6+ OUT6– OUT7+ OUT7– TO DAUGHTER CARD #4 OUT8+ OUT8– OUT9+ – TO DAUGHTER CARD #5 OUT9 OUT10+ OUT10– IN – EZS_SRQ– OUT2+ 12.5MHz SYSREF OUT2– OUT3+ 500MHz CLOCK – OUT3 LTC6953 OUT4+ 12.5MHz SYSREF OUT4– OUT5+ 125MHz CLOCK – OUT5 EZS_SRQ+ 100Ω OUT0+ 12.5MHz SYSREF OUT0– OUT1+ 500MHz CLOCK – OUT1 OUT6+ 100MHz CLOCK OUT6– OUT7+ 12.5MHz SYSREF OUT7– OUT8+ 4GHz CLOCK – OUT8 OUT9+ 12.5MHz SYSREF OUT9– OUT10+ 4GHz CLOCK – OUT10 DAUGHTER CARD #1 DAUGHTER CARD #2 LTC6952 and LTC6953 EZSync Cascaded PhaseNoise Noise Cascaded Phase –100 DAUGHTER CARD #4 DAUGHTER CARD #5 RMS JITTER = 100fs EQUIVALENT ADC SNR METHOD –110 PHASE NOISE (dBc/Hz) DAUGHTER CARD #3 6953 TAO2a –120 –130 –140 –150 –160 –170 4GHz 500MHz 1k 10k 100k 1M OFFSET FREQUENCY (Hz) 10M 40M 6953 TA02b RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC6952 Ultralow Jitter, 4.5GHz PLL with 11 Outputs and JESD204B/C Support PLL with Eleven Independent CML Outputs with Dividers and Delays, 65fs Additive ADC SNR Jitter LTC6955/LTC6955-1 Ultralow Jitter, 7.5GHz, 11-Output Fanout Buffer Family Eleven CML Outputs, 45fs Additive ADC SNR Jitter HMC7043 High Performance, 3.2GHz, 14-Output Fanout Buffer with JESD204B/C HMC7044 High Performance, 3.2GHz, 14-Output Jitter Attenuator with JESD204B/C HMC987 3.3V Low Noise 1:9 Fanout Buffer, DC − 8GHz LTC6951 Ultralow Jitter Multioutput Clock Synthesizer with Integrated VCO 58 Four Independent CML Outputs and One LVDS Output, Integrated VCO, 110fs ADC SNR Jitter Rev. A 1/20 For more information www.analog.com © www.analog.com ANALOG DEVICES, INC. 2018-2020