LTC7062
100V Dual High-Side MOSFET Gate Driver
FEATURES
DESCRIPTION
Unique Symmetric Floating Gate Driver Architecture
n High Noise Immunity, Tolerates ±10V Ground
Difference
n 100V Maximum Input Voltage Independent of IC
Supply Voltage VCC
n 5V to 14V V
CC Operating Voltage
n 4V to 14V Gate Driver Voltage
n 0.8Ω Pull-Down, 1.5Ω Pull-Up for Fast Turn-On/Off
n TTL/CMOS Compatible Input
n V
CC UVLO/OVLO and Floating Supplies UVLO
n Drives Dual N-Channel MOSFETs
n Open-Drain Fault Indicator (V
CC UVLO/OVLO,
Gate Driver UVLO and Thermal Shutdown)
n Available in Thermally Enhanced 12-Lead MSOP
n AEC-Q100 Automotive Qualification in Progress
The LTC®7062 drives two high-side N-Channel MOSFETs
with supply voltages up to 100V. Both drivers can operate with a different ground reference, providing excellent
noise and transient immunity. The two drivers are symmetric and independent of each other, allowing complementary or non-complementary switching.
APPLICATIONS
Shoot-Through
Protection
n
Automotive and Industrial Power Systems
n Telecommunication Power Systems
n
All registered trademarks and trademarks are the property of their respective owners.
Its powerful 0.8Ω pull-down and 1.5Ω pull-up MOSFET
drivers allows the use of large gate capacitance
high voltage MOSFETs. Additional features include UVLO,
TTL/CMOS compatible inputs and fault indicator.
See chart below for a similar driver in this product family.
PARAMETER
LTC7060
LTC7061
LTC7062
LTC7063
Input Signal
3-State PWM
CMOS/
TTL Logic
CMOS/
TTL Logic
3-State PWM
Yes
Yes
No
Yes
Absolute Max
Voltage
115V
115V
115V
155V
VCC Falling
UVLO
5.3V
4.3V
4.3V
5.3V
TYPICAL APPLICATION
VCC
12V
VCC
51k
G1VCC
FLTB
VIN
48V–100V
G1
G1RTN
LTC7062
PWM
CONTROLLER
G2VCC
G1IN
VIN
48V–100V
VOUT1
5V
G2
G2IN
SGND
G2RTN
7062 TA01
VOUT2
3.3V
Rev. 0
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1
LTC7062
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(All voltages are referred to SGND unless otherwise noted.)
(Note 1)
TOP VIEW
VCC Supply Voltage .....................................−0.3V to 15V
G1 Gate Driver Voltage (G1VCC) ................−0.3V to 115V
G2 Gate Driver Voltage (G2VCC).................−0.3V to 115V
G1RTN, G2RTN........................................... −10V to 100V
(G1VCC – G1RTN).........................................−0.3V to 15V
(G2VCC – G2RTN)........................................−0.3V to 15V
FLT.............................................................. −0.3V to 15V
G1IN, G2IN.................................................... −0.3V to 6V
Output G1 (with Respect to G1RTN)............−0.3V to 15V
Output G2 (with Respect to G2RTN)............−0.3V to 15V
Operating Junction Temperature
Range (Notes 2, 3)............................ −40°C to 150°C
Storage Temperature Range................... −65°C to 150°C
G1IN
G2IN
FLT
NC
VCC
G2VCC
1
2
3
4
5
6
13
SGND
12
11
10
9
8
7
G1VCC
G1
G1RTN
NC
G2
G2RTN
MSE PACKAGE
12-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 40°C/W
EXPOSED PAD (PIN 13) IS SGND, MUST BE SOLDERED TO PCB
Note: All voltage are referred to SGND unless
otherwise noted.
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC7062EMSE#PBF
LTC7062EMSE#TRPBF
LTC7062
12-Lead Plastic MSOP
–40°C to 125°C
LTC7062IMSE#WPBF
LTC7062IMSE#WTRPBF
LTC7062
12-Lead Plastic MSOP
–40°C to 125°C
LTC7062JMSE#WPBF
LTC7062JMSE#WTRPBF
LTC7062
12-Lead Plastic MSOP
–40°C to 150°C
LTC7062HMSE#WPBF
LTC7062HMSE#WTRPBF
LTC7062
12-Lead Plastic MSOP
–40°C to 150°C
AUTOMOTIVE PRODUCTS**
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your
local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
these models.
Rev. 0
2
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LTC7062
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
temperature range, otherwise specifications are at TA = 25°C (Note 2). VCC = VG1VCC = VG2VCC =10V, VG1RTN = VG2RTN = 0V, unless
otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
100
V
Input Supply and VCC Supply
VIN
Input Supply Operating Range
VCC
IC Supply Operating Range
IVCC
VCC Supply Current
VG1IN = VG2IN = 0V
5
0.3
14
mA
V
VUVLO_VCC
VCC Undervoltage Lockout Threshold
VCC Falling
4.3
V
Hysteresis
0.2
V
VOVLO_VCC
VCC OVLO Threshold
VCC Rising
14.6
V
Hysteresis
0.8
V
G1 Gate Driver Supply (G1VCC – G1RTN)
VG1VCC–G1RTN
G1 Driver Supply Voltage Range
(With Respect to G1RTN)
IG1VCC
Total G1VCC Current (Note 4)
VUVLO_G1VCC
Undervoltage Lockout Threshold
4
14
V
G1 = L
8.9
µA
G1 = H
146
µA
G1VCC Falling, Respect to G1RTN
3.4
V
Hysteresis
0.3
V
G2 Gate Driver Supply (G2VCC – G2RTN)
VG2VCC–G2RTN
G2 Driver Supply Voltage Range
(With Respect to G2RTN)
IG2VCC
Total G2VCC Current (Note 4)
VVUVLO_G2VCC
Undervoltage Lockout Threshold
4
14
V
G2 = L
8.9
µA
G2 = H
146
µA
G2VCC Falling, Respect to G2RTN
3.4
V
Hysteresis
0.3
V
Input Signal (G1IN, G2IN)
VIH(G1IN)
G1 Turn-On Input Threshold
G1IN Rising
VIL(G1IN)
G1 Turn-Off Input Threshold
G1IN Falling
1.75
VIH(G2IN)
G2 Turn-On Input Threshold
G2IN Rising
VIL(G2IN)
G2 Turn-Off Input Threshold
G2IN Falling
RDOWN_G1IN
G1IN Internal Pull-Down Resistor
1000
kΩ
RDOWN_G2IN
G2IN Internal Pull-Down Resistor
1000
kΩ
60
Ω
Low to High
100
µs
0.5
V
V
1.75
0.5
V
V
FAULT (FLT)
RFLTb
FLT Pin Pull-Down Resistor
tFLTb
FLT Pin Delay
Gate Driver Output (G1)
VOH(G1)
G1 High Output Voltage
IG1 = −100mA, VOH(G1) = VG1VCC – VG1
150
mV
VOL(G1)
G1 Low Output Voltage
IG1 = 100mA, VOL(G1) = VG1 – VG1RTN
80
mV
RG1_UP
G1 Pull-Up Resistance
VG1VCC–G1RTN =10V
1.5
Ω
RG1_DOWN
G1 Pull-Down Resistance
VG1VCC–G1RTN =10V
0.8
Ω
Rev. 0
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3
LTC7062
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
temperature range, otherwise specifications are at TA = 25°C (Note 2). VCC = VG1VCC = VG2VCC =10V, VG1RTN = VG2RTN = 0V, unless
otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Gate Driver Output (G2)
VOH(G2)
G2 High Output Voltage
IG2 = −100mA, VOH(G2) = VG2Vcc – VG2
150
mV
VOL(G2)
G2 Low Output Voltage
IG2 = 100mA, VOL(G2) = VG2 – VG2RTN
80
mV
RG2_UP
G2 Pull-Up Resistance
VG2VCC–G2RTN =10V
1.5
Ω
RG2_DOWN
G2 Pull-Down Resistance
VG2VCC–G2RTN =10V
0.8
Ω
Switching Time
tPDLH(G1)
G1IN High to G1 High Propagation Delay
20
ns
tPDHL(G1)
G1IN Low to G1 Low Propagation Delay
20
ns
tPDLH(G2)
G2IN High to G2 High Propagation Delay
21
ns
tPDHL(G2)
G2IN Low to G2 Low Propagation Delay
21
ns
tr(G2)
G2 Output Rise Time
10% – 90%, CLOAD = 3nF
18
ns
tf(G2)
G2 Output Fall Time
10% – 90%, CLOAD = 3nF
14
ns
tr(G1)
G1 Output Rise Time
10% – 90%, CLOAD = 3nF
18
ns
tf(G1)
G1 Output Fall Time
10% – 90%, CLOAD = 3nF
14
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC7062E is guaranteed to meet performance specifications
from 0°C to 85°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC7062I is guaranteed over the –40°C to 125°C operation junction
temperature range. The LTC7062J and LTC7062H are guaranteed over
the –40°C to 150°C operation junction temperature range. High junction
temperature degrades operation lifetimes; operating lifetime is derated
for junction temperatures greater than 125°C. Note that the maximum
ambient temperature consistent with these specifications is determined by
specific operating conditions in conjunction with board layout, the rated
package thermal impedance and other environment factors.
Note 3: TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formula.
TJ = TA + (PD • 40 °C/W)
Note 4: The total current includes both the current from G1VCC/G2VCC to
G1RTN/G2RTN and the current to SGND. Dynamic supply current is higher
due to the gate charge being delivered at the switching frequency.
Note 5: Rise and fall times are measured using 10% and 90% levels.
Rev. 0
4
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LTC7062
TYPICAL PERFORMANCE CHARACTERISTICS
Quiescent Supply Current
vs Supply Voltage
1.7
300
1.5
250
1.3
SUPPLY CURRENT (μA)
G1IN/G2IN PIN THRESHOLDS (V)
G1IN/G2IN Pin Thresholds
vs Temperature
VIH(G1IN),VIH(G2IN)
1.1
0.9
TA = 25°C, unless otherwise noted.
VIL(G1IN),VIL(G2IN)
IVCC
200
150
IG1VCC, G1 = H
100
50
0.7
IG1VCC, G1 = L
0.5
–45 –20
5
0
30 55 80 105 130 155
TEMPERATURE (°C)
5
7062 G01
IG2VCC, G2 = L
6
7
8
9 10 11 12 13 14
VCC,VG1VCC–VG1RTN, VG2VCC–VG2RTN (V)
7062 G02
VCC Undervoltage Lockout
Thresholds vs Temperature
VCC Overvoltage Lockout
Thresholds vs Temperature
15.0
5.0
4.8
4.6
VCC OVLO THRESHOLDS (V)
VCC UVLO THRESHOLDS (V)
IG2VCC, G2 = H
VCC RISING
4.4
VCC FALLING
4.2
4.0
–45 –20
5
VCC RISING
14.5
14.0
VCC FALLING
13.5
13.0
–45 –20
30 55 80 105 130 155
TEMPERATURE (°C)
5
30 55 80 105 130 155
TEMPERATURE (°C)
7062 G04
7062 G03
Switching Supply Current
vs
vs Load
Load Capacitance
Capacitance
Supply Current
vs Input Frequency
800
35
700
30
600
25
500
IVCC
20
400
300
15
10
200
IG1VCC, IG2VCC
100
5
0
0
200
400
600
FREQUENCY (kHz)
100
800
0
1000
SWITCHING SUPPLY CURRRENT (mA)
VCC = G1VCC = G2VCC = 10V
CG1 = CG2 = 3.3nF
G1RTN = G1RTN = 0V
VCC SUPPLY CURRENT (µA)
G1VCC AND G2VCC CURRENT (mA)
40
VCC = G1VCC = G2VCC = 10V
G1RTN = G2RTN = 0V
IG1VCC, IG2VCC; fIN = 500kHz
10
IG1VCC, IG2VCC; fIN = 100kHz
1
IVCC; fIN = 500kHz
0.1
1
7062 G05
10
LOAD CAPACITANCE (nF)
30
7062 G06
Rev. 0
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5
LTC7062
TYPICAL PERFORMANCE CHARACTERISTICS
Rise and Fall Time
vs Floating Supply Voltage
30
CLOAD = 3.3nF
28
200
24
VCC = G1VCC = G2VCC = 10V
G1RTN = G2RTN = 0V
100
RISE/FALL TIME (ns)
RISE/FALL TIME (ns)
Rise and Fall Time
vs Load Capacitance
tr(G1)
tf(G1)
tr(G2)
tf(G2)
26
TA = 25°C, unless otherwise noted.
22
20
18
16
14
tr(G1)
tf(G1)
tr(G2)
tf(G2)
10
12
10
4
5
6
7
5
8
9 10 11 12 13 14
VG1VCC-G1RTN, VG2VCC-G2RTN, (V)
1
10
LOAD CAPACITANCE (nF)
7062 G08
7062 G07
Propagation Delay
vs Floating Supply Voltage
tr(G1)
tf(G1)
tr(G2)
tf(G2)
35
PROPAGATION DELAY (ns)
Propagation Delay vs
Temperature
Propagation Delay vs Temperture
30
25
20
40
30
25
20
15
15
10
tPDLH(G1)
tPDHL(G1)
tPDLH(G2)
tPDHL(G2)
35
PROPAGATION DELAY (ns)
40
4
5
6
7
10
–45 –20
8
9 10 11 12 13 14
VG1VCC-G1RTN, VG2VCC-G2RTN (V)
5
30 55 80 105 130 155
TEMPERATURE (°C)
7062 G09
7062 G10
G1/G2 Pull-Up and PullDown Resistance vs Floating
Supply Voltage
G1/G2 Pull-Up and Pull-Down
Resistance
Resistance vs
vs Temperature
Temperature
3
G1VCC = G2VCC =10V
G1RTN = G2RTN = 0V
2
IMPEDANCE (Ω)
IMPEDANCE (Ω)
3
30
1
0
–45 –20
RUP(G1)
RDOWN(G1)
RUP(G2)
RDOWN(G2)
5
30 55 80 105 130 155
TEMPERATURE (°C)
RUP(G1)
RDOWN(G1)
RUP(G2)
RDOWN(G2)
2
1
0
4
7062 G11
6
8
10
12
VG1VCC-G1RTN, VG2VCC-G2RTN (V)
14
7062 G12
Rev. 0
6
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LTC7062
PIN FUNCTIONS
VCC: VCC Supply. IC bias supply referred to the SGND pin.
An internal 4.5V supply is generated from the VCC supply
to bias all the internal circuitry. A bypass capacitor with a
minimum value of 0.1μF should be tied between this pin
and the SGND pin.
G1RTN: G1 MOSFET Driver Return. The G1 gate driver is
biased between G1VCC and G1RTN. Kelvin connect G1RTN
to the G1 MOSFET source pin for high noise immunity.
The voltage difference between the G1RTN pin and SGND
can be −10V to 100V.
G2VCC: G2 MOSFET Driver Supply. The G2 MOSFET gate
driver is biased between this pin and G2RTN pin. An external capacitor should be tied between this pin and G2RTN
and placed close to the IC.
G1: G1 MOSFET Gate Driver Output. This pin drives
the gate of the N-channel MOSFET between G1RTN
and G1VCC.
G2RTN: G2 MOSFET Driver Return. The G2 gate driver is
biased between G2VCC and G2RTN. Kelvin connect G2RTN
to the G2 MOSFET source pin for high noise immunity.
The voltage difference between the G2RTN pin and the
SGND can be −10V to 100V.
G2: G2 MOSFET Gate Driver Output. This pin drives the
gate of the N-channel MOSFET between G2RTN and
G2VCC.
G1VCC: G1 MOSFET Driver Supply. The G1 MOSFET gate
driver is biased between this pin and the G1RTN pin. An
external capacitor should be tied between this pin and the
G1RTN pin and placed close to the IC.
G1IN: Logic input for G1-side driver. If G1IN is unbiased
or floating, G1 is held low.
G2IN: Logic input for G2-side driver. If G2IN is unbiased
or floating, G2 is held low.
FLT: Open Drain Fault Output pin referred to the SGND pin.
Open-drain output that pulls to SGND during VCC UVLO/
OVLO and floating supplies UVLO condition. The typical
pull-down resistor is 60Ω.
SGND: Chip Ground. The exposed pad must be soldered
to the PCB ground for electrical contact and for rated
thermal performance.
Rev. 0
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7
LTC7062
BLOCK DIAGRAM
FLT
G1VCC
UVLO
VCC
DRIVER
UVLO
OVLO
G1IN
1000k
1.25V
G2IN
1000k
1.25V
G1
G1RTN
LEVEL
SHIFTER
+
–
DRIVER
LOGIC
LEVEL
SHIFTER
+
–
G2V CC
DRIVER
UVLO
G2
G2RTN
SGND
7062 BD
TIMING DIAGRAM
VIH(G1IN)
VIH(G2IN)
INPUT
(G1IN, G2IN)
VIL(G1IN)
VIL(G2IN)
VPDHL(G1)
VPDHL(G2)
VPDLH(G1)
VPDLH(G2)
90%
tr(G1IN)
tr(G2IN)
OUTPUT
(G1, G2)
10%
90%
tf(G1IN)
tf(G2IN)
10%
7062 TD
Rev. 0
8
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LTC7062
OPERATION
Overview
The LTC7062 has two ground-referenced, low voltage digital signal inputs to drive two N-channel high-side power
MOSFETs. The output G2 is driven high or low, swinging
between G2VCC and G2RTN, depending on the G2IN pin.
Similarly, the output G1 is swinging between G1VCC and
G1RTN. Each channel is controlled by its input pints (G1IN
and G2IN), allowing independent flexibility to control on
and off state of the output.
Both the G1 and G2 drivers are high-side gate drivers.
LTC7062 features robust drive with excellent noise
and transient immunity, including large negative ground
difference tolerance (−10V) on switch node (G1RTN,
G2RTN). The two drivers are symmetric and independent of each other, allowing G1 and G2 complementary
or non-complementary switching.
VCC Supply
VCC is the power supply for the LTC7062’s internal circuitry. An internal 4.5V supply is generated from the
VCC supply to bias all the internal circuits referred to
SGND. The VCC pin may be tied to the G2VCC pin if SGND
and G2RTN are at the same potential. VCC is independent
of VIN.
When G1IN/G2IN pin is floating, there is an internal 1000k
pull-down resistor from the G1IN/G2IN pin to SGND, keeping the G1/G2 default state low if the input is not driven.
Both G1IN and G2IN pin can be used by the controller IC
to perform the Discontinuous Conduction Mode (DCM)
in switching regulator applications.
Output Stage
A simplified version of the LTC7062’s output stage is
shown in Figure 1. Both G1 and G2 designs are symmetrical and have floating gate-driver outputs. The
pull-up device is a P-channel MOSFET with a typical
1.5Ω RDS(ON) and the pull-down device is a N-channel
MOSFET with a typical 0.8Ω RDS(ON). The wide driver
supply voltage ranging from 4V to 14V enables driving
different power MOSFETs, such as logic level or high
threshold MOSFETs. However, LTC7062 is optimized for
high threshold MOSFETs (e.g., G1VCC – G1RTN = 10V
and G2VCC – G2RTN = 10V). The driver output pull-up
and pull-down resistance may increase with lower driver
supply voltage.
LTC7062
CGD
1.5Ω
Input Stage (G1IN, G2IN)
VIN
G1VCC
G1
The LTC7062 employs two logic inputs with fixed transition thresholds. When the voltage on G1IN is greater
than the threshold VIH(G1IN), G1 is pulled up to G1VCC,
turning the external MOSFET on. This MOSFET will stay
on until G1IN falls below VIL(G1IN). Similarly, when G2IN
is greater than VIH(G2IN), G2 is pulled up to G2VCC, turning
the external MOSFET on. G2 will stay high until G2IN falls
below the threshold VIL(G2IN).
The hysteresis between the corresponding VIH and VIL
voltage levels eliminates false triggering due to the noise
during switch transitions. However, care should be taken to
keep noise from coupling into the input pins (G1IN, G2IN),
particularly in high frequency, high voltage applications.
CGS
0.8Ω
G1RTN
FLOATING
GROUND
G2VCC
VIN
CGD
1.5Ω
G2
CGS
0.8Ω
G2RTN
7062 F01
FLOATING
GROUND
Figure 1. Simplified Output Stage
Rev. 0
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9
LTC7062
OPERATION
Since the power MOSFETs generally account for the
majority of the power loss in a converter, it is important
to turn them on and off quickly, thereby minimizing the
transition time and power loss. The LTC7062’s typical
1.5Ω pull-up resistance and 0.8Ω pull-down resistance
are equivalent to 3A peak pull-up current and 6A peak
pull down current at a 10V driver supply. Both G2 and G1
can produce a rapid turn-on transition for the MOSFETs
with capability of driving a 3nF load with 18ns rise time.
Protection Circuitry
When using the LTC7062, care must be taken not to
exceed any of the Absolute Maximum Ratings. As an
added safeguard, the LTC7062 incorporates an overtemperature shutdown feature. If the junction temperature reaches approximately 180°C, the LTC7062 will
enter thermal shutdown mode and G2 will be pulled to
G2RTN; G1 will be pulled to G1RTN. Normal operation
will resume when the junction temperature cools to be
less than 165°C. The overtemperature level is not production tested. The LTC7062 is guaranteed to operate at
temperatures below 150°C.
The LTC7062 contains both undervoltage and overvoltage
lockout detectors that monitor the VCC supply. When VCC
falls below 4.3V or rises above 14.6V, the output pins G2
and G1 are pulled to G2RTN and G1RTN, respectively.
This turns off both the external MOSFETs. When VCC has
adequate supply voltage but less than the overvoltage
threshold, normal operation will resume.
Additional undervoltage lockout circuitry is included in
each floating driver supply. The G2 will be pulled down to
G2RTN when the floating voltage from G2VCC to G2RTN
falls below 3.3V. Similarly, the G1 will be pulled down to
G1RTN when the floating voltage from G1VCC to G1RTN
is less than 3.3V.
The normal operation and undervoltage/overvoltage logic
table is shown in Table 1.
Table 1. Normal Operation and Undervoltage/Overvoltage Logic
G1IN
X
(G1VCC– (G2VCC–
VCC
UVLO or G1RTN) G2RTN) Thermal
UVLO
UVLO Shutdown G1 G2 FLTB
G2IN OVLO
X
X
X
X
Yes
L
X
X
Yes
X
H
No
H
X
No
No
L
H
No
No
H
L
No
H
H
L
L
L
L
X
X
No
Yes
N
No
L
L
L
L
H
L
Yes
No
H
L
L
No
No
L
H
H
No
No
No
H
L
H
No
No
No
No
H
H
H
No
No
No
No
L
L
H
Note: “X” means “Don’t Care”, “H” means “High”, and “L” means “Low”.
FAULT FLAG
FLT pin is connected to the open-drain of an internal
N-channel MOSFET. It needs a pull-up resistor (e.g. 51k)
tied to a supply such as VCC or any other bias voltage up
to 15V. The FLT pin is pulled low to SGND immediately if
any of these conditions are met:
a. The VCC is below its UVLO threshold or above its OVLO
threshold.
b. (G2VCC – G2RTN) is below its UVLO threshold.
c. (G1VCC – G1RTN) is below its UVLO threshold.
d. The junction temperature reaches approximately
180°C.
When all the faults are cleared, FLT pin is pulled up by the
external resistor after a built-in 100µs delay.
Rev. 0
10
For more information www.analog.com
LTC7062
APPLICATIONS INFORMATION
Bootstrapped Supply (G2VCC – G2RTN, G1VCC – G1RTN)
where:
Either or both of the G2VCC – G2RTN and G1VCC – G1RTN
supplies can be bootstrapped supplies. An external boost
capacitor, CB, connected between G2VCC and G2RTN, or
between G1VCC and G1RTN, supplies the gate driver
voltage for its respective MOSFET driver. When the external MOSFET is turned on, the driver places the CB voltage
across the gate-source of the MOSFET. This enhances the
MOSFET and turns it on.
TJ = junction temperature
The charge to turn on the external MOSFET is referred to
gate charge, QG, and is typically specified in the external
MOSFET data sheet. The boost capacitor, CB, needs to
have at least 10 times the gate charge to turn on the
external MOSFET fully. Gate charge can range from 5nC
to hundreds of nC and is influenced by the gate drive level
and type of external MOSFET used. For most applications, a capacitor value of 0.1μF for CB will be sufficient.
However, if multiple MOSFETs are paralleled and drove
by the LTC7062, CB needs to be increased correspondingly and the following relationship for the CB should be
maintained:
CB >
10•External MOSFET QG
1V
An external supply, typically VCC connected through a
Schottky diode, is required to keep the CB charged. The
LTC7062 does not charge the CB and always discharges
the CB. When the G2/G1 is high, the total current from
G2VCC/G1VCC to G2RTN/G1RTN and SGND is typically
146µA; when the G2/G1 is low, the total current from
G2VCC/G1VCC is typically 9µA.
PD = power dissipation
θJA = junction-to-ambient thermal resistance
Power dissipation consists of standby, switching and
capacitive load power losses:
PD = PDC + PAC + PQG
where:
PDC = quiescent power loss
PAC = internal switching loss at input frequency fIN
PQG = loss due to turning on and off external MOSFET
with gate charge QG at frequency fIN
The LTC7062 consumes very little quiescent current. The
DC power loss at VCC = 10V is only (10V)(0.3mA) = 3mW.
At a particular switching frequency, the internal power
loss increases due to both AC currents required to charge
and discharge internal nodal capacitances and cross-conduction currents in the internal logic gates. The sum of the
quiescent current and internal switching current with no
load are shown in the Typical Performance Characteristics
plot of Switching Supply Current vs Load Capacitance.
The gate charge losses are primarily due to the large AC
currents required to charge and discharge the capacitance
of the external MOSFETs during switching. For identical
pure capacitive loads CLOAD on BG and TG at switching
frequency fIN, the load losses would be:
PCLOAD=(CLOAD)(fIN)[(VG1VCC-G1RTN)2+(VG2VCC-G2RTN)2]
POWER DISSIPATION
To ensure proper operation and long-term reliability, the
LTC7062 must not operate beyond its maximum temperature rating. Package junction temperature can be
calculated by:
TJ = TA + (PD)(θJA)
TA = ambient temperature
In a typical synchronous buck configuration, the VCC is
connected to the power for the bottom MOSFET driver,
G2VCC. VG1VCC–G1RTN is equal to VCC – VD, where VD is
the forward voltage drop of the external Schottky diode
between VCC and G1VCC. If this drop is small relative VCC,
the load losses can be approximated as:
PCLOAD ≈ 2(CLOAD)(fIN)(VCC)2
Rev. 0
For more information www.analog.com
11
LTC7062
APPLICATIONS INFORMATION
Unlike a pure capacitive load, a power MOSFET’s gate
capacitance seen by the driver output varies with its VGS
voltage level during switching. A MOSFET’s capacitive
load power dissipation can be calculated using its gate
charge, QG. The QG value corresponding to the MOSFET’s
VGS value (VCC in this case) can be readily obtained
from the manufacturer’s QG vs VGS curves. For identical
MOSFETs on G2 and G1:
PQG ≈ 2(QG)(fIN)(VCC)
BYPASSING AND GROUNDING
The LTC7062 requires proper bypassing on the VCC,
VG1VCC-G1RTN and VG2VCC-G2RTN supplies due to its high
speed Switching (nanoseconds) and large AC currents
(amperes). Careless component placement and PCB trace
routing may cause excessive ringing and under/overshoot.
To obtain the optimum performance form the LTC7062:
• Mount the bypass capacitors as close as possible
between the VCC and SGND pins, the G2VCC and
G2RTN pins, and the G1VCC and G1RTN pins. The leads
should be shortened as much as possible to reduce
lead inductance.
• Use a low inductance, low impedance ground place
to reduce any ground drop and stray capacitance.
Remember that the LTC7062 switches greater than
5A peak currents and any significant ground drop will
degrade signal integrity.
• Plan the power/ground routing carefully. Know where
the large load switching current is coming from and
going to. Maintain separate ground return paths for
the input pin and the output power stage.
• Kelvin connect the G1 pin to the G1 MOSFET gate and
G1RTN pin to the G1 MOSFET source. Kelvin connect
the G2 pin to the G2 MOSFET gate and G2RTN to the
G2 MOSFET source. Keep the copper trace between the
driver output pin and load short and wide.
• Be sure to solder the Exposed Pad on the back side of
the LTC7062 packages to the board. Failure to make
good thermal contact between the exposed back side
and the copper board will result in thermal resistances
far greater than specified for the packages.
Rev. 0
12
For more information www.analog.com
LTC7062
PACKAGE DESCRIPTION
MSE Package
12-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1666 Rev G)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 ±0.102
(.112 ±.004)
5.10
(.201)
MIN
2.845 ±0.102
(.112 ±.004)
0.889 ±0.127
(.035 ±.005)
6
1
1.651 ±0.102
(.065 ±.004)
1.651 ±0.102 3.20 – 3.45
(.065 ±.004) (.126 – .136)
12
0.65
0.42 ±0.038
(.0256)
(.0165 ±.0015)
BSC
TYP
RECOMMENDED SOLDER PAD LAYOUT
0.254
(.010)
0.35
REF
4.039 ±0.102
(.159 ±.004)
(NOTE 3)
0.12 REF
DETAIL “B”
CORNER TAIL IS PART OF
DETAIL “B” THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
7
NO MEASUREMENT PURPOSE
0.406 ±0.076
(.016 ±.003)
REF
12 11 10 9 8 7
DETAIL “A”
0° – 6° TYP
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
4.90 ±0.152
(.193 ±.006)
GAUGE PLANE
0.53 ±0.152
(.021 ±.006)
DETAIL “A”
1.10
(.043)
MAX
0.18
(.007)
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
TYP
1 2 3 4 5 6
0.650
(.0256)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL
NOT EXCEED 0.254mm (.010") PER SIDE.
0.86
(.034)
REF
0.1016 ±0.0508
(.004 ±.002)
MSOP (MSE12) 0213 REV G
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
moreby
information
www.analog.com
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
13
LTC7062
TYPICAL APPLICATION
Dual Outputs Boost Converters
VCC
10V
VCC
G1VCC
51k
(FROM μC)
G2VCC
FLT
G2IN
SGND
VOUT1
60V
VIN2
20V
VOUT2
80V
G1
G1RTN
LTC7062
G1IN
VIN1
10V
G2
G2RTN
7062 TA02
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Rev. 0
14
02/21
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