LTC7132IY#PBF

LTC7132 25A, Dual PolyPhase Regulator with Digital Power System Management FEATURES n DESCRIPTION PMBus/I2C Compliant Serial Interface The LTC®7132 is a dual output PolyPhase DC/DC synchronous step-down monolithic regulator with an I2C-based PMBus compliant serial interface. The regulator employs a constant-frequency current mode architecture, together with a unique scheme to provide excellent performance in sub-milliohm DCR applications. The LTC7132 is supported by the LTpowerPlay® software development tool with graphical user interface (GUI). – Telemetry Read-Back Includes VIN, IIN, VOUT, IOUT, Temperature and Faults – Programmable Voltage, Current Limit, Digital SoftStart/Stop, Sequencing, Margining, OV/UV/OC n Sub-Milliohm DCR Current Sensing n Digitally Adjustable Loop Compensation Parameters n ±0.5% Output Voltage Accuracy Over Temperature n Integrated Input Current Sense Amplifier n Internal EEPROM with ECC and Fault Logging n Integrated N-Channel MOSFET Gate Drivers Power Conversion n Wide V Range: 4.5V to 20V IN n V OUT Range: 0.5V to 3.5V (with Ultralow DCR Setting); 0.5V to 5.5V (Typical DCR Setting) n Accurate PolyPhase® Current Sharing for Up to 6 Phases n Available in a 140-Lead (9mm × 11.25mm × 2.22mm) BGA Package Programmable loop compensation allows the regulator to be compensated digitally. The switching frequency, channel phasing and device address can be programmed both by the digital interface as well as the external configuration resistors. Additionally, parameters can be set via the digital interface and stored in EEPROM. Both outputs have independent power good indicators and FAULT function. The LTC7132 can be configured to operate in discontinuous (pulse-skipping) mode or forced continuous conduction mode. Each channel can deliver up to 25A of load current; the total current capability will depend on the total power dissipations on both channels. APPLICATIONS Telecom, Datacom and Storage Systems Industrial and Point-of-Load Applications n All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. Patents including 5481178, 5705919, 5929620, 6144194, 6177787, 6580258, 5408150, 7420359, 8648623, 8786265, 8823352, 7000125. Licensed under U.S. Patent 7000125 and other related patents worldwide. n TYPICAL APPLICATION 2mΩ 4.7µF D2 INTVCC DCR = 0.29mΩ L2 0.3µH C5 0.1µF 100µF ×2 ISENSE0+ ISENSE1+ ISENSE1– VSENSE1+ TO/FROM OTHER LTC DEVICES 931Ω 4700pF 1µF 6 EXTVCC = 5.5V VIN = 12V fSW = 425kHz CCM 95 FAULT MANAGEMENT 5 90 4 85 3 80 2 75 1 0.22µF VOUT1 1V, 20A 330µF ×2 100µF ×2 VSENSE0– VSENSE1– TSNS0 TSNS1 ITH0 ITH1 ITH_R0 ITH_R1 VDD33 PGND SGND VDD25 150pF 100 DCR = 0.29mΩ L1 0.3µH BOOST1 ISENSE0– VSENSE0+ Efficiency and Power Loss vs Load Current POWER LOSS (W) 0.22µF VIN 4.5V TO 15V C10 270µF ×2 10µF ×2 D4 SW0 SW1 LTC7132* SDA FAULT0 SCL FAULT1 ALERT PGOOD0 RUN0 PGOOD1 RUN1 SHARE_CLK EXTVCC 931Ω 330µF ×2 IIN – PVIN1 BOOST0 PMBus INTERFACE VOUT0 1.8V, 20A SVIN IIN PVIN0 0.1µF + 1Ω EFFICIENCY (%) 10µF ×2 1µF 70 7132 TA01a 150pF 1500pF 10nF 1µF 0 4 8 12 LOAD CURRENT (A) 16 20 0 7132 TA01b EFFICIENCY VOUT = 1.8V VOUT = 1.0V POWER LOSS VOUT = 1.8V VOUT = 1.0V *SOME DETAILS OMITTED FOR CLARITY Rev 0 Document Feedback For more information www.analog.com 1 LTC7132 TABLE OF CONTENTS Features...................................................... 1 Applications................................................. 1 Typical Application ......................................... 1 Description.................................................. 1 Table of Contents........................................... 2 Absolute Maximum Ratings............................... 4 Order Information........................................... 4 Pin Configuration........................................... 4 Electrical Characteristics.................................. 5 Typical Performance Characteristics................... 11 Pin Functions............................................... 15 Block Diagram.............................................. 17 Operation................................................... 18 Overview.................................................................. 18 Main Control Loop................................................... 19 EEPROM.................................................................. 19 Power-Up and Initialization......................................20 Soft-Start.................................................................20 Time-Based Sequencing.......................................... 21 Voltage-Based Sequencing...................................... 21 Shutdown................................................................22 Light-Load Current Operation..................................22 Switching Frequency and Phase..............................22 PWM Loop Compensation.......................................23 Output Voltage Sensing...........................................23 INTVCC/EXTVCC Power............................................23 Output Current Sensing and Sub-Milliohm DCR Current Sensing....................................................... 24 Input Current Sensing..............................................25 PolyPhase Load Sharing..........................................25 External/Internal Temperature Sense.......................25 RCONFIG (Resistor Configuration) Pins...................26 Fault Detection and Handling................................... 27 Status Registers and ALERT Masking.................. 27 Mapping Faults to FAULT Pins.............................29 Power Good Pins.................................................29 CRC Protection....................................................29 Serial Interface........................................................29 Communication Protection..................................30 2 Device Addressing...................................................30 Responses to VOUT and IIN/IOUT Faults....................30 Output Overvoltage Fault Response.................... 31 Output Undervoltage Response........................... 31 Peak Output Overcurrent Fault Response............ 31 Responses to Timing Faults..................................... 31 Responses to VIN OV Faults..................................... 32 Responses to OT/UT Faults...................................... 32 Internal Overtemperature Fault Response........... 32 External Overtemperature and Undertemperature Fault Response.................................................... 32 Responses to Input Overcurrent and Output Undercurrent Faults................................................. 32 Responses to External Faults................................... 32 Fault Logging........................................................... 32 Bus Timeout Protection...........................................33 Similarity Between PMBus, SMBus and I2C 2-Wire Interface..................................................................33 PMBus Serial Digital Interface.................................33 PMBus Command Summary............................. 38 PMBus Commands..................................................38 *Data Format...........................................................43 Applications Information................................. 44 Current Limit Programming.....................................44 ISENSE0± and ISENSE1± Pins.......................................44 Inductor DCR Sensing.........................................45 Inductor Value Calculation.......................................46 Inductor Core Selection...........................................46 Low Value Resistor Current Sensing........................46 Slope Compensation and Inductor Peak Current..... 47 Variable Delay Time, Soft-Start and Output Voltage Ramping..................................................................48 Digital Servo Mode..................................................48 Soft Off (Sequenced Off)......................................... 49 INTVCC/EXTVCC Power............................................ 49 Topside MOSFET Driver Supply (CB, DB).................50 Undervoltage Lockout..............................................50 CIN and COUT Selection............................................ 51 Fault INDICATION..................................................... 51 Rev 0 For more information www.analog.com LTC7132 TABLE OF CONTENTS Open-Drain Pins...................................................... 52 Phase-Locked Loop and Frequency Synchronization .. 53 Minimum On-Time Considerations..........................53 External Temperature Sense....................................54 Input Current Sense Amplifier..................................54 External Resistor Configuration Pins (RCONFIG).....55 Voltage Selection.................................................55 Frequency Selection............................................56 Phase Selection...................................................56 Address Selection Using RCONFIG...................... 57 Efficiency Considerations........................................ 57 Thermal Considerations ..........................................58 Programmable Loop Compensation........................ 59 Checking Transient Response.................................. 59 PolyPhase Configuration.....................................60 PC Board Layout Checklist...................................... 61 PC Board Layout Debugging.................................... 61 Design Example.......................................................63 Additional Design Checks........................................64 Connecting the USB to I2C/SMBus/PMBus Controller to the LTC7132 in System........................................64 LTpowerPlay: An Interactive GUI for Digital Power..65 PMBus Communication and Command Processing.65 PMBus Command Details................................ 68 Addressing and Write Protect..................................68 General Configuration Commands........................... 70 On/Off/Margin......................................................... 71 PWM Configuration.................................................73 Voltage..................................................................... 76 Input Voltage and Limits...................................... 76 Output Voltage and Limits...................................77 Output Current and Limits.......................................80 Input Current and Limits ..................................... 82 Temperature.............................................................82 External Temperature Calibration........................82 Timing.....................................................................84 Timing—On Sequence/Ramp..............................84 Timing—Off Sequence/Ramp.............................85 Precondition for Restart......................................86 Fault Response........................................................86 Fault Responses All Faults...................................86 Fault Responses Input Voltage............................ 87 Fault Responses Output Voltage.......................... 87 Fault Responses Output Current..........................90 Fault Responses IC Temperature......................... 91 Fault Responses External Temperature................92 Fault Sharing............................................................93 Fault Sharing Propagation...................................93 Fault Sharing Response.......................................95 Scratchpad..............................................................95 Identification............................................................96 Fault Warning and Status......................................... 97 Telemetry............................................................... 104 NVM Memory Commands..................................... 108 Store/Restore.................................................... 108 Fault Logging..................................................... 109 Block Memory Write/Read................................ 112 Typical Applications..................................... 113 Package Description.................................... 117 Typical Application...................................... 118 Related Parts............................................. 118 Rev 0 For more information www.analog.com 3 LTC7132 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) SVIN, PVIN0, PVIN1, IIN+, IIN –....................... –0.3V to 20V (VIN –IIN+), (IIN+ –IIN –)................................. –0.3V to 0.3V BOOST0, BOOST1....................................... –0.3V to 26V Switch Transient Voltage (SW0, SW1)........... –5V to 26V ISENSE0+, ISENSE0 –, ISENSE1+, ISENSE1–, VSENSE0+, VSENSE1+....................................... –0.3V to 6V VSENSE0 –, VSENSE1–.................................... –0.3V to 0.3V (BOOST0-SW0), (BOOST1-SW1).................. –0.3V to 6V EXTVCC, INTVCC........................................... –0.3V to 6V PGOOD0, PGOOD1..................................... –0.3V to 3.6V RUN0, RUN1, SDA, SCL, ALERT................. –0.3V to 5.5V ASEL0, ASEL1, VOUT0_CFG0, VOUT1_CFG, FREQ_CFG, PHASE_CFG............................................. –0.3V to 2.75V FAULT0, FAULT1, SHARE_CLK, WP, SYNC. –0.3V to 3.6V TSNS0, TSNS1........................................... –0.3V to 2.2V ITH0, ITH1, ITHR0, ITHR1............................... –0.3V to 2.7V Operating Junction Temperature Range (Notes 2, 17, 18)........................................–40°C to 125°C Storage Temperature Range................... –40°C to 125°C FAULT0 FAULT1 ALERT VOUT0_CFG SDA SCL SYNC SGND TSNS0 TSNS1 ISENSE0– ISENSE0+ ITH0 ITHR0 ISENSE1+ ISENSE1– VSENSE0+ TOP VIEW A NC RUN0 RUN1 ASEL0 FREQ_CFG ASEL1 PHASE_CFG VOUT1_CFG B NC C PGOOD0 SVIN D WP ITH1 E SHARE_CLK F VDD25 PGND G VDD33 ITHR1 NC NC VSENSE1+ VSENSE0– IIN– IIN+ BOOST0 SW0 EXTVCC PGND VSENSE1– INTVCC PGOOD1 BOOST1 SW1 PVIN0 H PVIN1 J PGND K L M SW1 N SW0 P 1 2 3 4 5 6 7 8 9 10 BGA PACKAGE 140-LEAD (11.25mm × 9.00mm × 2.22mm) TJMAX = 125°C, θJA = 14.5°C/W, θJC = 1.1°C/W θJA DERIVED FROM LTC7132 DEMO BOARD WEIGHT = 0.52g NC (PINS B2, B4, E8, E9, F6) ARE NO CONNECT, PINS ARE NOT CONNECTED INTERNALLY. FLOAT OR GROUND THESE PINS *See Derating EEPROM Retention at Temperature in Applications Information section for junction temperatures in excess of 125°C. ORDER INFORMATION PART MARKING* PART NUMBER LTC7132EY#PBF LTC7132IY#PBF PAD OR BALL FINISH DEVICE FINISH CODE PACKAGE TYPE MSL RATING SAC305 (RoHS) LTC7132Y e1 BGA 4 • Contact the factory for parts specified with wider operating temperature ranges. *Pad or ball finish code is per IPC/JEDEC J-STD-609. TEMPERATURE RANGE (SEE NOTE 2) –40°C to 125°C • Recommended LGA and BGA PCB Assembly and Manufacturing Procedures • LGA and BGA Package and Tray Drawings 4 Rev 0 For more information www.analog.com LTC7132 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, EXTVCC = 0V, VRUN0,1 = 3.3V, fSYNC = 500kHz (externally driven) and all programmable parameters at factory default, unless otherwise specified. SYMBOL PARAMETER CONDITION MIN TYP MAX UNITS Input Voltage SVIN, PVIN0/1 Input Voltage Range (Note 11) IQ Input Voltage Supply Current VRUN0,1 = 3.3V (Note 16) VRUN0,1 = 0V (Note 16) VUVLO Undervoltage Lockout Threshold When VIN > 4.3V VINTVCC Falling VINTVCC Rising tINIT Initialization Time Time from VIN Applied Until the TON_DELAY Timer Starts tOFF(MIN) Short Cycle Retry Time l 4.5 20 25 23 V mA mA 3.55 3.90 V V 35 ms 120 ms Control Loop Range 1 Maximum VOUT Set Point Accuracy (0.6V ~ 2.5V) Resolution LSB Step Size 0.6V ≤ VOUT ≤ 2.5V MFR_PWM_MODE[1] = 1 (Notes 9, 10, 13) Range 0 Maximum VOUT Set Point Accuracy (0.6V ~ 5.0V) Resolution LSB Step Size 1.2V ≤ VOUT ≤ 5.5V MFR_PWM_MODE[1] = 0 (Notes 9, 10, 13) l l VLINEREG Line Regulation 6V < VIN < 20V l VLOADREG Load Regulation ∆VITH = 1.35V ~ 0.7V ∆VITH = 1.35V ~ 2V l l IISENSE0,1 Input Pin Bias Current 0V ≤ VPIN ≤ 5.5V l VSENSERIN0,1 VSENSE Input Resistance to GND 0V ≤ VPIN ≤ 5.5V VILIMIT VILIM_HIGH l VILIM_LOW VREV MFR_PWM_MODE[7],[2]=0, 1, ILIM[3:0]=1100, VOUT ≤ 3.5V (Note 15) MFR_PWM_MODE[7],[2]=0, 1, ILIM[3:0]=0001, VOUT ≤ 3.5V MFR_PWM_MODE[7],[2]=0, 1, VOUT ≥ VOV VILIM_HIGH VILIM_LOW VREV MFR_PWM_MODE[7][2]=1, 1, ILIM[3:0]=1100,VOUT ≤ 3.5V MFR_PWM_MODE[7][2]=1, 1, ILIM[3:0]=0001,VOUT ≤ 3.5V MFR_PWM_MODE[7][2]=1, 1, VOUT ≥ VOV l 27.0 29.5 17.0 –15 31.0 mV mV mV VILIM_HIGH VILIM_LOW VREV MFR_PWM_MODE[7][2]=0, 0, ILIM[3:0]=1100 MFR_PWM_MODE[7][2]=0, 0, ILIM[3:0]=0001 MFR_PWM_MODE[7][2]=0, 0, VOUT ≥ VOV l 35 41.38 25 –18.8 49 mV mV mV VILIM_HIGH VILIM_LOW VREV MFR_PWM_MODE[7][2]=1, 0, ILIM[3:0]=1100 MFR_PWM_MODE[7][2]=1, 0, ILIM[3:0]=0001 MFR_PWM_MODE[7][2]=1, 0, VOUT ≥ VOV l 67.5 74.5 43.5 –37.5 81.5 mV mV mV gm0,1 Resolution Error Amplifier gm(MAX) Error Amplifier gm(MIN) LSB Step Size ITH0,1 = 1.35V, MFR_PWM_CONFIG[7:5] = 0 to 7 3 4.6 0.8 0.54 RTH0, 1 Resolution Compensation Resistor RTH(MAX) Compensation Resistor RTH(MIN) MFR_PWM_CONFIG[4:0] = 0 to 31 (See Figure 1) 5 62 0 Bits kΩ kΩ tON(MIN) Minimum On-Time 90 ns RTOP Top Power NMOS On-Resistance 7.3 mΩ RBOTTOM Bottom Power NMOS On-Resistance 2.1 mΩ VOUTRL VOUTRH l –0.5 –0.5 2.75 12 0.688 5.5 12 1.375 0.5 0.5 V % Bits mV ±0.02 %/V 0.01 –0.01 0.1 –0.1 % % ±1 ±3 50 14.5 V % Bits mV 16.5 µA kΩ 18.5 9.5 –7.5 mV mV mV Bits mmho mmho mmho RDS(ON) Rev 0 For more information www.analog.com 5 LTC7132 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, EXTVCC = 0V, VRUN0,1 = 3.3V, fSYNC = 500kHz (externally driven) and all programmable parameters at factory default, unless otherwise specified. SYMBOL PARAMETER CONDITION MIN TYP MAX UNITS OV/UV Output Voltage Supervisor Channel 0/1 9 Bits VOUSTPSP_RL LSB Step Size MFR_PWM_MODE[1] = 1 (Note 13) 5.6 mV VOUSTPSP_RH LSB Step Size MFR_PWM_MODE[1] = 0 (Note 13) 11.2 mV N Resolution VRANGE_RL Range 0 Maximum Threshold MFR_PWM_MODE[1] = 1 2.86 V VRANGE_RH Range 1 Maximum Threshold MFR_PWM_MODE[1] = 0 5.74 V VTHAC0_RL Threshold Accuracy 1V < VOUT < 2.75V MFR_PWM_MODE[1] = 1 l ±1.5 l % VTHAC1_RH Threshold Accuracy 2V < VOUT < 5.5V MFR_PWM_MODE[1] = 0 ±1.5 % tPROPOV OV Comparator Response Time VOD = 10% of Threshold 100 µs tPROPUV UV Comparator Response Time VOD = 10% of Threshold 100 µs VIN Voltage Supervisor N Resolution 9 Bits VINSTP LSB Step Size 76 mV VIN Full-Scale Voltage 20 V VINTHACCM Threshold Accuracy 9V < VIN < 20V Threshold Accuracy 4.5V < VIN ≤ 9V tPROPVIN Comparator Response Time (VIN_ON and VIN_OFF) l l VOD = 10% of threshold ±3 ±6.0 % % 100 µs Output Voltage Readback N Resolution 16 Bits VOUTSTP LSB Step Size 244 µV VF/S Full-Scale Sense Voltage VRUNn = 0 (Note 8) 8 V VOUT_TUE Total Unadjusted Error VOUT > 0.6V (Note 8) VOS Zero-Code Offset Voltage tCONVERT Update Rate l –0.5 l 0.5 % ±500 µV (Note 6) 90 ms Bits VIN Voltage Readback N Resolution (Note 5) 10 20 VF/S Full-Scale Input Voltage (Note 11) VINTUE Total Unadjusted Error VVIN > 4.5V (Note 8) tCONVERT Update Rate (Note 6) V 0.5 2 l % % 90 ms Output Current Readback N Resolution (Note 5) 10 Bits VIOUTSTP LSB Step Size 0V ≤ |VISENSE+ – VISENSE–| < 16mV 16mV ≤ |VISENSE+ – VISENSE–| < 32mV 32mV ≤ |VISENSE+ – VISENSE–| < 64mV 64mV ≤ |VISENSE+ – VISENSE–| < 100mV 15.63 31.25 62.5 125 µV µV µV µV IF/S Full-Scale Input Current (Note 7) DCR or RISENSE = 1mΩ ±100 A IOUT_TUE Total Unadjusted Error 100mV > (VISENSE+ – VISENSE–) > 6mV (Note 8) VOS Zero-Code Offset Voltage tCONVERT Update Rate 6 ±1.25 l ±50 (Note 6) 90 % µV ms Rev 0 For more information www.analog.com LTC7132 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, EXTVCC = 0V, VRUN0,1 = 3.3V, fSYNC = 500kHz (externally driven) and all programmable parameters at factory default, unless otherwise specified. SYMBOL PARAMETER CONDITION MIN TYP MAX UNITS Input Current Readback N Resolution VIINSTP LSB Step Size Full-Scale Range = 16mV Gain = 8, 0V ≤ |VIIN+ – VIIN–| ≤ 5mV LSB Step Size Full-Scale Range = 32mV Gain = 4, 0V ≤ |VIIN+ – VIIN–| ≤ 20mV LSB Step Size Full-Scale Range = 64mV Gain = 2, 0V ≤ |VIIN+ – VIIN–| ≤ 50mV (Note 5) IIN_TUE Total Unadjusted Error VOS Zero-Code Offset Voltage tCONVERT Update Rate 10 Bits 15.26 30.52 61 µV µV µV Gain = 8, 2.5mV ≤ |VIIN+ – VIIN–| ≤ 5mV (Note 8) Gain = 4, 4mV ≤ |VIIN+ – VIIN–| ≤ 20mV (Note 8) Gain = 2, 6mV ≤ |VIIN+ – VIIN–| ≤ 50mV (Note 8) ±2 ±1.3 ±1.2 ±50 (Note 6) % % % µV 90 ms 10 Bits 244 µV Supply Current Readback N Resolution VICHIPSTP LSB Step Size Full-Scale Range = 256mV (Note 5) ICHIPTUE Total Unadjusted Error 20mV ≤ |VIIN+ – VIN| ≤ 150mV (Note 19) tCONVERT Update Rate (Note 6) ±3 l % 90 ms 0.25 °C Temperature Readback (T0, T1) TRES_T Resolution T0_TUE External Temperature Total Unadjusted Readback Error TSNS0, TSNS1 ≤ 1.85V (Note 8) MFR_PWM_MODE_[5] = 0 MFR_PWM_MODE_[5] = 1 (Note 14) T1_TUE Internal TSNS TUE VRUN0,1 = 0.0, fSYNC = 0kHz (Note 8) ±1 °C tCONVERT Update Rate (Note 6) 100 ms l l –3 –10 3 10 °C °C INTVCC Regulator/EXTVCC VINTVCC Internal VCC Voltage No Load 6V ≤ VIN ≤ 20V VLDO_INT INTVCC Load Regulation ICC = 0mA to 20mA, 6V ≤ VIN ≤ 20V VEXTVCC EXTVCC Switchover Voltage VIN ≥ 7V, EXTVCC Rising VLDO_HYS EXTVCC Hysteresis VLDO_EXT EXTVCC Voltage Drop ICC = 20mA, VEXTVCC = 5.5V VIN_THR VIN Threshold to Enable EXTVCC Switchover VIN Rising VIN_HYS VIN Hysteresis to Disable EXTVCC Switchover VIN Rising – VIN Falling l 5.25 l 4.5 5.5 5.75 V 0.5 ±2 % 4.7 4.9 V 290 50 mV 100 mV 7.4 V 600 mV VDD33 Regulator VDD33 Internal VDD33 Voltage 4.5V < VINTVCC or 4.8V < VEXTVCC 3.2 3.3 3.4 V ILIM VDD33 Current Limit VDD33 = GND, VIN = INTVCC = 4.5V 100 mA VDD33_OV VDD33 Overvoltage Threshold 3.5 V VDD33_UV VDD33 Undervoltage Threshold 3.1 V 2.5 V 80 mA VDD25 Regulator VDD25 Internal VDD25 Voltage ILIM VDD25 Current Limit VDD25 = GND, VIN = INTVCC = 4.5V Rev 0 For more information www.analog.com 7 LTC7132 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, EXTVCC = 0V, VRUN0,1 = 3.3V, fSYNC = 500kHz (externally driven) and all programmable parameters at factory default, unless otherwise specified. SYMBOL PARAMETER CONDITION MIN TYP MAX UNITS 1000 kHz ±7.5 % Oscillator and Phase-Locked Loop fRANGE PLL SYNC Range Syncronized with Falling Edge of SYNC l 200 fOSC Oscillator Frequency Accuracy Frequency Switch = 250kHz to 1000kHz l VTH(SYNC) SYNC Input Threshold VSYNC Falling VSYNC Rising 1 1.5 VOL(SYNC) SYNC Low Output Voltage ILOAD = 3mA 0.2 ILEAK(SYNC) SYNC Leakage Current in Slave Mode 0V ≤ VPIN ≤ 3.6V θSYNC-θ0 SYNC to Ch0 Phase Relationship Based on the Falling Edge of Sync and Rising Edge of TG0 MFR_PWM_CONFIG[2:0] = 0,2,3 MFR_PWM_CONFIG[2:0] = 5 MFR_PWM_CONFIG[2:0] = 1 MFR_PWM_CONFIG[2:0]= 4,6 0 60 90 120 Deg Deg Deg Deg θSYNC-θ1 SYNC to Ch1 Phase Relationship Based on the Falling Edge of Sync and Rising Edge of TG1 MFR_PWM_CONFIG[2:0] = 3 MFR_PWM_CONFIG[2:0] = 0 MFR_PWM_CONFIG[2:0] = 2,4,5 MFR_PWM_CONFIG[2:0] = 1 MFR_PWM_CONFIG[2:0] = 6 120 180 240 270 300 Deg Deg Deg Deg Deg V V 0.4 V ±5 µA EEPROM Characteristics Endurance (Note 12) 0°C < TJ < 85°C EEPROM Write Operations l 10,000 Cycles Retention (Note 12) TJ < 125°C l 10 Years Mass_Write Mass Write Operation Time STORE_USER_ALL, 0°C < TJ < 85°C During EEPROM Write Operation l OV ≤ VPIN ≤ 5.5V OV ≤ VPIN ≤ 3.6V 440 4100 ms l ±5 µA l ±2 µA Leakage Current SDA, SCL, ALERT, RUN IOL Input Leakage Current Leakage Current FAULTn, PGOODn IGL Input Leakage Current Digital Inputs SCL, SDA, RUNn, FAULTn VIH Input High Threshold Voltage l VIL Input Low Threshold Voltage l VHYST Input Hysteresis CPIN Input Capacitance 1.35 0.8 SCL, SDA V V 0.08 V 10 pF Digital Input WP IPUWP Input Pull-Up Current WP 10 µA Open-Drain Outputs SCL, SDA, FAULTn, ALERT, RUNn, SHARE_CLK, PGOODn VOL Output Low Voltage ISINK = 3mA 0.4 V 1.8 V Digital Inputs SHARE_CLK, WP VIH Input High Threshold Voltage l VIL Input Low Threshold Voltage l 1.5 0.6 1 V 3 µs Digital Filtering of FAULTn IFLTG 8 Input Digital Filtering FAULTn Rev 0 For more information www.analog.com LTC7132 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, EXTVCC = 0V, VRUN0,1 = 3.3V, fSYNC = 500kHz (externally driven) and all programmable parameters at factory default, unless otherwise specified. SYMBOL PARAMETER CONDITION MIN TYP MAX UNITS Digital Filtering of PGOODn IFLTG Output Digital Filtering PGOODn 60 µs 10 µs Digital Filtering of RUNn IFLTG Input Digital Filtering RUN PMBus Interface Timing Characteristics fSCL Serial Bus Operating Frequency l 10 tBUF Bus Free Time Between Stop and Start l 1.3 µs tHD(STA) Hold Time After Repeated Start Condition After This Period, the First Clock is Generated l 0.6 µs tSU(STA) Repeated Start Condition Setup Time l 0.6 tSU(ST0) Stop Condition Setup Time l 0.6 tHD(DAT) Data Hold Time Receiving Data Transmitting Data l l 0 0.3 tSU(DAT) Data Setup Time Receiving Data 400 10000 0.9 Serial Clock Low Period l 1.3 tHIGH Serial Clock High Period l 0.6 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC7132 is tested under pulsed load conditions such that TJ ≈ TA. The LTC7132E is guaranteed to meet performance specifications from 0°C to 85°C. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC7132I is guaranteed over the full –40°C to 125°C operating junction temperature range. TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: TJ = TA + (PD • θJA) The maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. Note 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified µs µs µs 32 255 tLOW µs µs 0.1 tTIMEOUT_SMB Stuck PMBus Timer Non-Block Reads Measured from the Last PMBus Start Event Stuck PMBus Timer Block Reads kHz ms 10000 µs µs Note 4: Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels. CLOAD = 3500pF is guaranteed by design. Note 5: The data format in PMBus is 5 bits exponent (signed) and 11 bits mantissa (signed). This limits the output resolution to 10 bits though the internal ADC is 16 bits and the calculations use 32-bit words. Note 6: The data conversion is done by default in round robin fashion. All inputs signals are continuously converted for a typical latency of 90ms. Setting MFR_ADC_CONTRL value to be 0 to 12, LTC7132 can do fast data conversion with only 8ms to 10ms. See section PMBus Command for details. Note 7: The IOUT_CAL_GAIN = 1.0mΩ and MFR_IOUT_TC = 0.0. Value as read from READ_IOUT in Amperes. Note 8: Part tested with PWM disabled. Evaluation in application demonstrates capability. TUE(%) = ADC Gain Error (%) +100 • (Zero code Offset + ADC Linearity Error)/Actual Value. Note 9: All VOUT commands assume the ADC is used to auto zero the output to achieve the stated accuracy. LTC7132 is tested in a feedback loop that servos VOUT to a specified value. Rev 0 For more information www.analog.com 9 LTC7132 ELECTRICAL CHARACTERISTICS Note 17: The LTC7132 includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 18: Write operations above TJ = 85°C or below 0°C are possible although the Electrical Characteristics are not guaranteed and the EEPROM will be degraded. Read operations performed at temperatures below 125°C will not degrade the EEPROM. Writing to the EEPROM above 85°C will result in a degradation of retention characteristics. Note 19: Properly adjust the input current sensing resistor RVIN to set the sensing voltage within the maximum voltage of 150mV. 62 56 50 43 RTH(kΩ) Note 10: The maximum programmable VOUT voltage is 5.5V when the output voltage range is High and 2.75V when the output voltage range is Low. Note 11: The maximum VIN voltage is 20V. Note 12: EEPROM endurance and retention are guaranteed by design, characterization and correlation with statistical process controls. Data retention is production tested via a high temperature at wafer level. The minimum retention specification applies for devices whose EEPROM has been cycled less than the minimum endurance specification. The RESTORE_USER_ALL command (NVM read) is valid over the entire operating junction temperature range. Note 13: MFR_PWM_MODE[1]=1 or 0 sets the output voltage range Low or High. Note 14: MFR_PWM_MODE_[5] = 0 or 1 sets the temperature measurement method through ∆VBE, or through 2VBE. Note 15: MFR_PWM_MODE[2] = 1 or 0 sets device in ultralow DCR mode or typical DCR mode respectively. MFR_PWM_MODE[7]=1 or 0 sets device in high output current range or low current range. See “Output Current Sensing and Sub-Milliohm DCR Current Sensing” in Operation Section for details. Only VLIMIT codes 1-9 are supported for DCR sensing. Note 16: The LTC7132 quiescent current (IQ) equals the IQ of VIN plus the IQ of EXTVCC. 37 31 25 19 12 6 0 0 5 10 15 20 CODE 25 30 35 7132 F01 Figure 1. Programmable RTH 10 Rev 0 For more information www.analog.com LTC7132 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VIN = 12V, L = 0.3µH, DCR = 0.29mΩ, EXTVCC = 0V unless otherwise noted. Efficiency vs Load Current 100 Efficiency vs Load Current 100 EXTVCC = 5.5V fSW = 425kHz 95 5 75 70 0 2 4 85 80 75 70 VOUT = 1.8V VOUT = 1.5V VOUT = 1.2V VOUT = 1.0V 65 POWERLOSS (W) EFFICIENCY (%) EFFICIENCY (%) 80 VOUT = 1.8V VOUT = 1.5V VOUT = 1.2V VOUT = 1.0V 65 60 6 8 10 12 14 16 18 20 LOAD CURRENT (A) 0 2 4 EFFICIENCY (%) 3 2 VOUT = 1.8V VOUT = 1.5V VOUT = 1.2V VOUT = 1.0V 2 4 0 2 4 6 8 10 12 14 16 18 20 LOAD CURRENT (A) 7132 G03 6 8 10 12 14 16 18 20 LOAD CURRENT (A) Load Step (Forced Continuous Mode) 6 VIN = 12V VOUT = 1V fSW = 425kHz CCM EFFICIENCY 95 90 0 0 85 4 80 3 75 70 2 65 60 55 50 0 VOUT 100mV/DIV AC-COUPLED 5 POWER LOSS (W) POWERLOSS (W) 100 4 0 2 Efficiency and Power Loss vs Load Current EXTVCC = 0V fSW = 425kHz 1 3 7132 G02 Power Loss vs Output Current 5 4 1 6 8 10 12 14 16 18 20 LOAD CURRENT (A) 7132 G01 6 VOUT = 1.8V VOUT = 1.5V VOUT = 1.2V VOUT = 1.0V EXTVCC = 5.5V fSW = 425kHz 90 85 60 EXTVCC = 0V fSW = 425kHz 95 90 Power Loss vs Load Current 6 IL 10A/DIV ILOAD 10A/DIV NO EXTVCC EXTVCC = 5.5V 1 NO EXTVCC POWER LOSS EXTVCC = 5.5V 0 5 10 15 20 25 LOAD CURRENT (A) 40µs/DIV 7132 G06 7132 G05 7132 G04 Load Step (Discontinuous Mode) Inductor Current at Light Load VOUT 100mV/DIV AC-COUPLED FORCED CONTINUOUS MODE 5A/DIV IL 10A/DIV DISCONTINUOUS MODE 5A/DIV ILOAD 10A/DIV 40µs/DIV 7132 G07 VOUT = 1V ILOAD = 1A 1µs/DIV 7132 G08 Rev 0 For more information www.analog.com 11 LTC7132 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VIN = 12V, L = 0.3µH, DCR = 0.29mΩ, EXTVCC = 0V unless otherwise noted. Soft-Start Ramp Start-Up Into a Pre-Biased Output Soft-Off Ramp RUN 2V/DIV 0V RUN 2V/DIV 0V RUN 2V/DIV 0V VOUT 1V/DIV 0V VOUT 1V/DIV 0V VOUT 1V/DIV 0V 5ms/DIV 7132 G09 5ms/DIV 7132 G10 5ms/DIV tON_RISE = 10ms tON_DELAY = 5ms VOUT = 1.8V tON_RISE = 10ms VOUT = 1.8V tOFF_FALL = 5ms tOFF_DELAY = 10ms Dynamic Current Sharing During a Load Transient in a 2-Phase System Dynamic Current Sharing During a Load Transient in a 2-Phase System Dynamic Current Sharing During a Load Transient in a 4-Phase System 10A/DIV 7132 G11 IL 5A/DIV 10A/DIV 0A 7132 G12 4µs/DIV VOUT = 1V fSW = 425kHz 0A TO 20A LOAD STEP Dynamic Current Sharing During a Load Transient in a 4-Phase System 7132 G13 Current Limit During an Output Short Condition VOUT 500mV/DIV 10µs/DIV VOUT = 1V fSW = 425kHz 0A TO 40A LOAD STEP 25 22 IL 10A/DIV 7132 G15 7132 G14 DC Output Current Matching in a 2-Phase System IOUT_OC_FAULT_LIMIT = 30A IL 5A/DIV 0A 10µs/DIV VOUT = 1V fSW = 425kHz 0A TO 40A LOAD STEP PHASE CURRENT (A) 4µs/DIV VOUT = 1V fSW = 425kHz 0A TO 20A LOAD STEP 10µs/DIV 19 16 13 9 CH0 CH1 6 7132 G16 3 0 0 8 16 24 32 TOTAL OUTPUT CURRENT (A) 40 7132 G17 12 Rev 0 For more information www.analog.com LTC7132 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VIN = 12V, L = 0.3µH, DCR = 0.29mΩ, EXTVCC = 0V unless otherwise noted. Current Sense Threshold vs Duty Cycle INTVCC Line Regulation 5.8 5.5 INTVCC (V) 5.2 4.9 4.6 4.3 4.0 0 5 10 VIN (V) 15 11.2 10.8 10.4 10.0 9.6 9.2 8.8 0 40 60 DUTY CYCLE (%) 80 98 95 93 100 22.5 20.0 17.5 16 20 1.0 4 12 VIN (V) 16 20 7132 G20 VREF vs Temperature RVIN = 2Ω 0.8 8 1.2220 1.2218 1.2215 0.6 1.2213 0.4 1.2210 0.2 VREF (V) 25.0 12 VIN (V) 100 7132 G19 SUPPLY CURRENT MEASUREMENT ERROR (%) QUIESCENT CURRENT (mA) 27.5 8 102 Supply Current Measurement Error vs Supply Current 30.0 4 20 7132 G18 Quiescent Current vs Input Voltage 15.0 105 8.4 8.0 20 107 MFM_PWM_MODE[7][2] = 0,1 IOUT_OC_FAULT_LIMIT= 29.6A 11.6 SHARE_CLK FREQUENCY (KHz) OVER CURRENT SENSE THRESHOLD (mV) 12.0 SHARE_CLK Frequency vs Input Voltage 0.0 –0.2 1.2208 1.2205 1.2203 1.2200 –0.4 1.2198 –0.6 1.2195 –0.8 1.2193 –1.0 20 40 60 80 100 SUPPLY CURRENT (mA) 7132 G21 1.2190 –55 120 –10 35 80 TEMPERATURE (°C) 125 7132 G23 7132 G22 VOUT Overvoltage Threshold vs Temperature (Target 1V) VOUT vs Temperature 1.005 VOUT Overvoltage Threshold vs Temperature (Target 2V) 1.015 2.030 1.010 2.020 1.003 OV THRESHOLD (V) VOUT (V) 1.002 1.001 1.000 0.999 0.998 0.997 OV THRESHOLD (V) 1.004 1.005 1.000 0.995 0.990 2.010 2.000 1.990 1.980 0.996 0.995 –55 –10 35 80 TEMPERATURE (°C) 125 7132 G24 0.985 –55 –10 35 80 TEMPERATURE (°C) 125 7132 G25 1.970 –55 –10 35 80 TEMPERATURE (°C) 125 7132 G26 Rev 0 For more information www.analog.com 13 LTC7132 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VIN = 12V, L = 0.3µH, DCR = 0.29mΩ, EXTVCC = 0V unless otherwise noted. VOUT Overvoltage Threshold vs Temperature (Target 4V) SHARE_CLK vs Temperature 4.02 SHARE_CLK (KHz) OV THRESHOLD (V) 4.04 4.00 3.98 Underlock Voltage vs Temperature 107 4.20 106 4.15 104 4.10 UNDERLOCK VOLTAGE (V) 4.06 103 101 100 99 97 96 3.96 –10 35 80 TEMPERATURE (°C) 93 –55 125 –10 35 80 TEMPERATURE (°C) –0.07 1.50 0.30 0.50 –0.15 –0.50 –0.22 5.5 –1.00 0.50 1.50 7132 G30 2.50 3.50 VOUT (V) 4.50 0.10 0.00 –0.10 –0.20 –0.30 0.5 5.50 1.5 2.5 3.5 VOUT (V) 4.5 5.5 7132 G32 Input Current Error vs Input Current 2 7.14 2 IINPUT MEASUREMENT ERROR (mA) IOUT MEASUREMENT ERROR (mA) IOUT Error vs IOUT 4.29 1.43 –1.43 –4.29 –7.14 16.0 24.0 IOUT (A) 125 0.20 7132 G31 10.00 8.0 –10 35 80 TEMPERATURE (°C) VOUT Error vs VOUT 0 4.5 FALLING 7132 G29 VOUT MEASUREMENT ERROR (mV) INL (LSB) DNL (LSB) 0.00 14 3.80 0.40 1.00 0.08 –10.00 0.1 3.85 2.00 0.15 2.5 3.5 VOUT (V) 3.90 VOUT Command INL 0.23 1.5 3.95 7132 G28 VOUT Command DNL –0.30 0.5 4.00 3.70 –55 125 7132 G27 0.30 4.05 3.75 94 3.94 –55 RISING 32.0 40.0 RIINSNS = 5mΩ 1 0 0 –1 –2 –2 –3 7132 G33 0 3 5 8 INPUT CURRENT(A) 10 7132 G34 Rev 0 For more information www.analog.com LTC7132 PIN FUNCTIONS VSENSE0+/VSENSE1+ (A9/F7): Positive Output Voltage Sense Inputs. VSENSE0–/VSENSE1– (A10/E7): Negative Output Voltage Sense Inputs. ITH0/ITH1 (A7/E5): Current Control Threshold and Error Amplifier Compensation Nodes. Each associated channel’s current comparator tripping threshold increases with its ITH voltage. ITHR0/ITHR1 (B7/E6): Loop Compensation Nodes. ISENSE0+/ISENSE1+ (B6/A8): Current sense comparator positive inputs, normally connected to DCR sensing networks or current sensing resistors. ISENSE0–/ISENSE1– (A6/B8): Current sense comparator negative inputs, normally connected to outputs. SYNC (A4): External Clock Synchronization Input and Open-Drain Output Pin. If an external clock is present at this pin, the switching frequency will be synchronized to the external clock. If clock master mode is enabled, this pin will pull low at the switching frequency with a 500ns pulse to ground. A resistor pull-up to 3.3V is required in the application if the LTC7132 is the master. SCL (B3): Serial Bus Clock Input. Open-drain output can hold the output low if clock stretching is enabled. A pullup resistor to 3.3V is required in the application. SDA (A3): Serial Bus Data Input and Output. A pull-up resistor to 3.3V is required in the application. ALERT (A2): Open-Drain Digital Output. Connect the SMBALERT signal to this pin. A pull-up resistor to 3.3V is required in the application. FAULT0/FAULT1 (A1/B1): Digital Programmable FAULT Inputs and Outputs. Open-drain output. A pull-up resistor to 3.3V is required in the application. RUN0/RUN1 (C1/C2): Enable Run Input and Output. Logic high on these pins enables the controller. An open-drain output holds the pin low until the LTC7132 is out of reset. A pull-up resistor to 3.3V is required in the application. ASEL0/ASEL1 (D1/E1): Serial Bus Address Select Inputs. Connect optional ±1% resistor dividers between VDD25 and SGND to these pins to select the serial bus interface address. Refer to the Applications Information section for more details. Minimize capacitance when the pin is open to assure accurate detection of the pin state. VOUT0_CFG/VOUT1_CFG (D2/F1): Output Voltage Select Pins. Connect optional ±1% resistor divider between VDD25 VOUT_CFG and SGND in order to select output voltage for each channel. If the pin is left open, the IC will use the value programmed in EEPROM. Refer to the Applications Information section for more details. Minimize capacitance when the pin is open to assure accurate detection of the pin state. FREQ_CFG (E2): Frequency Select Pin. Connect optional ±1% resistor divider between VDD25 and FREQ_CFG SGND in order to select PWM switching frequency. Refer to the Applications Information section for more details. Minimize capacitance when the pin is open to assure accurate detection of the pin state. PHASE_CFG (F2): Phase Select Pin. Connect ±1% resistor divider between VDD25 PHASE_CFG SGND to this pin to configure the phase of each PWM channel relative to SYNC. If the pin is left open, the IC will use the value programmed in the NVM. Refer to the Applications Information section for more details. Minimize capacitance when the pin is open to assure accurate detection of the pin state. VDD25 (F3): Internally Generated 2.5V Power Supply Output Pin. Bypass this pin to SGND with a low ESR 1μF capacitor. Do not load this pin with external current except for the ±1% resistor dividers required for the configuration pins. WP (E4): Write Protect Pin Active High. An internal 10μA current source pulls the pin to VDD33. If WP is high, the PMBus writes are restricted. SHARE_CLK (E3): Share Clock, Bidirectional Open-Drain Clock Sharing Pin. Nominally 100kHz. Used to synchronize the timing between multiple LTC7132s. Tie all SHARE_CLK pins together. All LTC7132s will synchronize to the fastest clock. A pull-up resistor to 3.3V is required. Rev 0 For more information www.analog.com 15 LTC7132 PIN FUNCTIONS VDD33 (F4): Internally Generated 3.3V Power Supply Output Pin. Bypass this pin to SGND with a low ESR 1μF capacitor. Do not load this pin with external current except for the pull-up resistors required for FAULTn, SHARE_CLK, SYNC and possibly RUNn, SDA and SCL, PGOODn. INTVCC (E10): Internal Regulator 5.5V Output. The control circuits are powered from this voltage. Decouple this pin to PGND with a minimum of 4.7μF low ESR tantalum or ceramic capacitor. This regulator is mainly designed for internal circuits, not to be used as supply for the other ICs. EXTVCC (D9): External Power Input to an Internal Switch Connected to INTVCC. This switch closes and supplies the IC power, bypassing the internal regulator whenever EXTVCC is higher than 4.7V and VIN is higher than 7V. EXTVCC also powers up VDD33 when EXTVCC is higher than 4.7V and INTVCC is lower than 3.8V. Do not exceed 6V on this pin. Decouple this pin to PGND with a minimum of 4.7μF low ESR tantalum or ceramic capacitor. If the EXTVCC pin is not used to power INTVCC, the EXTVCC pin must be tied to GND. The EXTVCC pin may be connected to a higher voltage than the VIN pin. SVIN (D8): Signal VIN. This pin is the input voltage to power the internal 5.5V INTVCC LDO. Tie this pin to VIN with a 2.2Ω resistor in series between VIN and SVIN. Decouple this pin to PGND with a ceramic capacitor (1µF to 10µF typical). BOOST0/BOOST1(C9/F10): Boosted Floating Driver Supplies. The (+) terminal of the booststrap capacitors connect to these pins. These pins swing from a diode voltage drop below INTVCC up to VIN + INTVCC. SW0/SW1 (C10, N6, N7, N8, N9, N10, P6, P7, P8, P9, P10/F9, N1, N2, N3, N4, N5, P1, P2, P3, P4, P5): Switch Node Connections to the Output Inductors. Voltage swings at the pins are from a diode (internal body diode) voltage drop below ground to VIN. 16 TSNS0/TSNS1 (A5/B5): External Diode Temperature Sense. Connect to the anode of a diode connected PNP transistor and star-connect the cathode to GND (Pin 49) in order to sense remote temperature. A bypass capacitor between the anode and cathode must be located in close proximity to the transistor. If external temperature sense elements are not installed, short pin to ground and set the UT_FAULT_LIMIT to –275°C and the UT_FAULT_ RESPONSE to ignore. IIN+ (B10): Positive Current Sense Comparator Input. If the input current sense amplifier is not used, this pin must be shorted to the IIN– and VIN pins. IIN– (B9): Negative Current Sense Comparator Input. If the input current sense amplifier is not used, this pin must be shorted to the IIN+ and VIN pins. PGOOD0/PGOOD1 (C8/F8): Power Good Indicator Outputs. Open-drain logic output that is pulled to ground when the output exceeds the UV and OV regulation window. The output is deglitched by an internal 60µs filter. A pull-up resistor to 3.3V is required in the application. SGND (C3, C4, C5, C6, C7, D3, D4, D5, D6, D7): Internal Signal Ground. All small-signal and compensation components should connect to this ground, which in turn connects to PGND at a single point. PVIN0/PVIN1 (G6, G7, G8, G9, G10, H6, H7, J6, J7, K6, K7, L6, L7, M6, M7/H1, H2, J1, J2, K1, K2, L1, L2, M1, M2): Main Input Supply. These pins connect directly to the drain of the internal high side power MOSFETs. Decouple these pins to PGND with the input capacitance CIN. PGND (Pins D10, G1, G2, G3, G4, G5, H3, H4, H5, H8, H9, H10, J3, J4, J5, J8, J9, J10, K3, K4, K5, K8, K9, K10, L3, L4, L5, L8, L9, L10, M3, M4, M5, M8, M9, M10): Power Ground. Rev 0 For more information www.analog.com LTC7132 BLOCK DIAGRAM (UK PACKAGE) VIN R VIN VIN ON/OFF + – 35R R R + – A=N CIN RIINSNS IIN– EXTVCC OV PGOOD0 PGOOD0 41R VSUPPLY IIN+ UV 5.5VREG 9-BIT VIN DAC EXTVCC INTVCC INTVCC VDD33 3.3V SUBREG S R Q PWM_CLOCK ICMP – + 5k + – VDD33 DB BOOST0 FCNT REV CB PREBIAS M1 ON SW0 SWITCH LOGIC AND ANTISHOOTTHROUGH REV UV UVLO SS VOUT0 COUT RUN ILIM RANGE SELECT HI: 1:1 LO: 1:1.8 M2 PGND OV 1 5k CVCC ISENSE0+ ISENSE0– SLOPE COMPENSATION GM INTVCC UVLO ITH0 CC2 ACTIVE CLAMP ILIM DAC (3 BITS) 16-BIT ADC RTH ITHR0 CC1 EA + – VSTBY 2µA OV UV + – + – 32µA + – – + + – – + + 10:1 – MUX + – + – + – + –+ – 11R 7R IVIN_SNS1 VSENSE0– – + ISENSE1+ ISENSE1– VSENSE1+ VSENSE1– PWM0 ICHIP AD 7R 11R + – VSENSE0+ TSNS0 TMUX 10R REF SGND SGND 4R 1.22V 12-BIT SET POINT DAC VCO PHASE SELECTOR VDD33 SCL SDA ALERT PMBus INTERFACE (400kHz COMPATIBLE) VDD33 COMPARE MAIN CONTROL WP SYNC PHASE DET 9-BIT OV DAC 9-BIT UV DAC PWM CLOCK CLOCK DIVIDER VDD25 2.5V SUBREG SLAVE MISO CLK MOSI MASTER SINC3 UVLO VDD25 ASEL0 OSC (32MHz) ASEL1 CONFIG DETECT FAULT0 RUN0 VDD33 CHANNEL TIMING MANAGEMENT PROGRAM ROM RAM EEPROM VOUT0_CFG FREQ_CFG PHASE_CFG SHARE_CLK 7132 F02 Figure 2. Block Diagram, One of Two Channels (Channel 0 Shown) Rev 0 For more information www.analog.com 17 LTC7132 OPERATION OVERVIEW Phase-Locked Loop for Synchronous PolyPhase Operation (2, 3, 4 or 6 Phases). n The LTC7132 is a dual channel/dual phase, constantfrequency, analog peak current mode controller for DC/ DC step-down applications with a digital interface. The LTC7132 digital interface is compatible with PMBus which supports bus speeds of up to 400kHz. A Typical Application circuit is shown on the first page of this data sheet. Integrated Gate Drivers n Nonvolatile Configuration Memory with ECC n Optional External Configuration Resistors for Key Operating Parameters n Optional Timebase Interconnect for Synchronization Between Multiple Controllers n Major features include: WP Pin to Protect Internal Configuration Sub-Milliohm DCR Sensing n Dedicated Power Good Indicators n Direct Input and Chip Current Sensing n Programmable Loop Compensation Parameters The PMBus interface provides access to important power management data during system operation including: n n Stand Along Operation After User Factory Configuration PMBus, Version 1.2, 400kHz Compliant Interface n n TINIT Start-Up Time: 35ms n PWM Synchronization Circuit, (See Frequency and Phasing Section for Details) Internal Controller Temperature n n n External System Temperature via Optional Diode Sense Elements MFR_ADC_CONTROL for Fast ADC Sampling of One Parameter (as Fast as 8ms) (See PMBus Command for Details) n Fully Differential Output Sensing for Both Channels; VOUT0/1 Both Programmable Up to 5.5V n n n Power-Up and Program EEPROM with EXTVCC n Input Voltage Up to 20V n Average Output Current Average Output Voltage n Average Input Voltage Average Input Current n Average Chip Input Current from VIN n Configurable, Latched and Unlatched Individual Fault and Warning Status n Dual Diode Temperature Sensing n SYNC Contention Circuit (Refer to Frequency and Phase Section for Details) Individual channels are accessed through the PMBus using the PAGE command, i.e., PAGE 0 or 1. Fault Logging Fault reporting and shutdown behavior are fully configurable. Two individual FAULT0, FAULT1 outputs are provided, both of which can be masked independently. Three dedicated pins for ALERT, PGOOD0/1 functions are provided. The shutdown operation also allows all faults to be individually masked and can be operated in either unlatched (hiccup) or latched modes. n n Programmable Output Voltage n Programmable Input Voltage On and Off Threshold Voltage n Programmable Current Limit n Programmable Switching Frequency n Programmable OV and UV Threshold voltage n Programmable ON and Off Delay Times n Programmable Output Rise/Fall Times n 18 Individual status commands enable fault reporting over the serial bus to identify the specific fault event. Fault or warning detection includes the following: n Output Undervoltage/Overvoltage Rev 0 For more information www.analog.com LTC7132 OPERATION n n n n Input Undervoltage/Overvoltage Input and Output Overcurrent Internal Overtemperature External Overtemperature is turned on. In continuous conduction mode, the bottom MOSFET stays on until the end of the switching cycle. EEPROM Communication, Memory or Logic (CML) Fault n MAIN CONTROL LOOP The LTC7132 is a constant-frequency, current mode stepdown controller containing two channels operating with user-defined relative phasing. During normal operation the top MOSFET is turned on when the clock for that channel sets the RS latch, and turned off when the main current comparator, ICMP, resets the RS latch. The peak inductor current at which ICMP resets the RS latch is controlled by the voltage on the ITH pin which is the output of each error amplifier, EA. The EA negative terminal is equal to the differential voltage between VSENSE+ and VSENSE– divided by 5.5 (or 2.75 if MFR_PWM_MODE[1] = 1). The positive terminal of the EA is connected to the output of a 12-bit DAC with values ranging from 0V to 1.024V. The output voltage, through feedback of the EA, will be regulated to 5.5 times the DAC output (or 2.75 times). The DAC value is calculated by the part to synthesize the user's desired output voltage. The output voltage is programmed by the user either with the resistor configuration pins detailed in Table 3 or by the PMBus VOUT command (either from EEPROM or by PMBus command). Refer to the PMBus command section of the data sheet or the PMBus specification for more details. The PMBus VOUT_COMMAND can be executed at any time while the device is running. This command will typically have a latency less than 10ms. The user is encouraged to refer to the PMBus Power System Management Protocol Specification to understand how to program the LTC7132. Continuing the basic operation description, the currentmode controller will turn off the top gate when the peak current is reached. If the load current increases, sense voltage will slightly droop with respect to the DAC reference. This causes the ITH voltage to increase until the average inductor current matches the new load current. After the top MOSFET has turned off, the bottom MOSFET The LTC7132 contains internal EEPROM (nonvolatile memory) with error correction coding (ECC) to store user configuration settings and fault log information. EEPROM endurance retention and mass write operation time are specified in the Electrical Characteristics and Absolute Maximum Ratings sections. Write operations above TJ = 85°C are possible although the Electrical Characteristics are not guaranteed and the EEPROM will be degraded. Read operations performed at temperatures between –40°C and 125°C will not degrade the EEPROM. Writing to the EEPROM above 85°C will result in a degradation of retention characteristics. The fault logging function, which is useful in debugging system problems that may occur at high temperatures, only writes to fault log EEPROM locations. If occasional writes to these registers occur above 85°C, the slight degradation in the data retention characteristics of the fault log will not take away from the usefulness of the function. It is recommended that the EEPROM not be written when the die temperature is greater than 85°C. If the die temperature exceeds 130°C, the LTC7132 will disable all EEPROM write operations. All EEPROM write operations will be re-enabled when the die temperature drops below 125°C. (The controller will also disable all the switching when the die temperature exceeds the internal overtemperature fault limit 160°C with a 10°C hysteresis) The degradation in EEPROM retention for temperatures >125°C can be approximated by calculating the dimensionless acceleration factor using the following equation: ⎡⎛ Ea ⎞ ⎛ ⎞⎤ 1 1 – ⎢⎜ ⎟•⎜ ⎟⎥ ⎣⎝ k ⎠ ⎝ TUSE +273 TSTRESS+273 ⎠⎦ AF = e where: AF = acceleration factor Ea = activation energy = 1.4eV K = 8.617 • 10–5 eV/°K TUSE = 125°C specified junction temperature TSTRESS = actual junction temperature in °C For more information www.analog.com Rev 0 19 LTC7132 OPERATION Example: Calculate the effect on retention when operating at a junction temperature of 135°C for 10 hours. TSTRESS = 130°C TUSE = 125°C, –5) • (1/398 – 1/403)] ) AF = e([(1.4/8.617 • 10 = 16.6 The equivalent operating time at 125°C = 16.6 hours. Thus the overall retention of the EEPROM was degraded by 16.6 hours as a result of operating at a junction temperature of 130°C for 10 hours. The effect of the overstress is negligible when compared to the overall EEPROM retention rating of 87,600 hours at a maximum junction temperature of 125°C. The integrity of the entire onboard EEPROM is checked with a CRC calculation each time its data is to be read, such as after a power-on reset or execution of a RESTORE_USER_ ALL command. If a CRC error occurs, the CML bit is set in the STATUS_BYTE and STATUS_WORD commands, the EEPROM CRC Error bit in the STATUS_MFR_SPECIFIC command is set, and the ALERT and RUN pins pulled low (PWM channels off). At that point the device will only respond at special address 0x7C, which is activated only after an invalid CRC has been detected. The chip will also respond at the global addresses 0x5A and 0x5B, but use of these addresses when attempting to recover from a CRC issue is not recommended. All power supply rails associated with either PWM channel of a device reporting an invalid CRC should remain disabled until the issue is resolved. See the Applications Information section or contact the factory for details on efficient in-system EEPROM programming, including bulk EEPROM Programming, which the LTC7132 also supports. POWER-UP AND INITIALIZATION The LTC7132 is designed to provide standalone supply sequencing and controlled turn-on and turn-off operation. It operates from a single input supply (4.5V to 20V) while three on-chip linear regulators generate internal 2.5V, 3.3V and 5.5V. If VIN does not exceed 6V, and the EXTVCC pin is not driven by an external supply, the INTVCC and SVIN pins must be tied together. The controller configuration is initialized by an internal threshold based UVLO where SVIN must be approximately 4V and the 5.5V, 3.3V 20 and 2.5V linear regulators must be within approximately 20% of the regulated values. In addition to power supply,a PMBus RESTORE_USER_ALL or MFR_RESET command can initialize the part too. The EXTVCC pin is driven by an external regulator to improve efficiency of the circuit and minimize power loss on the LTC7132 when VIN is high. The EXTVCC pin must exceed approximately 4.8V, and SVIN must exceed 7V before the INTVCC LDO operates from the EXTVCC pin. To minimize application power, the EXTVCC pin can be supplied by a switching regulator. During initialization, the external configuration resistors are identified and/or contents of the NVM are read into the controller’s commands. The RUNn and FAULTn and PGOODn are held low. The LTC7132 will use the contents of Tables 12 to 15 to determine the resistor defined parameters. See the Resistor Configuration section for more details. The resistor configuration pins only control some of the preset values of the controller. The remaining values are programmed in NVM either at the factory or by the user. If the configuration resistors are not inserted or if the ignore RCONFIG bit is asserted (bit 6 of the MFR_ CONFIG_ALL configuration command), the LTC7132 will use only the contents of NVM to determine the DC/ DC characteristics. The ASEL0/1 value read at power-up or reset is always respected unless the pin is open. The ASEL0/1 will set the MSB and the LSB from the detected threshold. See the Applications Information section for more details. After the part has initialized, an additional comparator monitors SVIN. The SVIN_ON threshold must be exceeded before the output power sequencing can begin. After SVIN is initially applied, the part will typically require 70ms to initialize and begin the TON_DELAY timer. The readback of voltages and currents may require an additional 0ms to 90ms. SOFT-START The method of start-up sequencing described below is time based. The part must enter the run state prior to soft-start. The run pins are released by the LTC7132 after Rev 0 For more information www.analog.com LTC7132 OPERATION the part is initialized and SVIN is greater than the SVIN_ON threshold. If multiple LTC7132s are used in an application, they all hold their respective run pins low until all devices are initialized and SVIN exceeds the SVIN_ON threshold for every device. The SHARE_CLK pin assures all the devices connected to the signal use the same time base. The SHARE_CLK pin is held low until the part has been initialized after VIN is applied. The LTC7132 can be set to turn-off (or remain off) if SHARE_CLK is low (set bit 2 of MFR_CHAN_CONFIG to 1). This allows the user to assure synchronization across numerous ADI ICs even if the RUN pins cannot be connected together due to board constraints. In general, if the user cares about synchronization between chips it is best not only to connect all the respective RUN pins together but also to connect all the respective SHARE_CLK pins together and pull up to VDD33 with a 10k resistor. This assures all chips begin sequencing at the same time and use the same time base. After the RUN pins release and prior to entering a constant output voltage regulation state, the LTC7132 performs a monotonic initial ramp or “soft-start”. Soft-start is performed by actively regulating the load voltage while digitally ramping the target voltage from 0V to the commanded voltage set-point. Once the LTC7132 is commanded to turn on (after power up and initialization), the controller waits for the user specified turn-on delay (TON_DELAY) prior to initiating this output voltage ramp. The rise time of the voltage ramp can be programmed using the TON_RISE command to minimize inrush currents associated with the start-up voltage ramp. The softstart feature is disabled by setting the value of TON_RISE to any value less than 0.25ms. The LTC7132 PWM always uses discontinuous mode during the TON_RISE operation. In discontinuous mode, the bottom gate is turned off as soon as reverse current is detected in the inductor. This will allow the regulator to start up into a pre-biased load. When the TON_MAX_FAULT_LIMIT is reached, the part transitions to continuous mode, if so programmed. If TON_MAX_FAULT_LIMIT is set to zero, there is no time limit and the part transitions to the desired conduction mode after TON_RISE completes and VOUT has exceeded the VOUT_UV_FAULT_LIMIT and IOUT_OC is not present. However setting TON_MAX_FAULT_LIMIT to a value of 0 is not recommended. TIME-BASED SEQUENCING The default mode for sequencing the outputs on and off is time based. Each output is enabled after waiting TON_ DELAY amount of time following either a RUN pin going high, a PMBus command to turn on or the VIN rising above a pre-programmed voltage. Off sequencing is handled in a similar way. To assure proper sequencing, make sure all ICs connect the SHARE_CLK pin together and RUN pins together. If the RUN pins cannot be connected together for some reasons, set bit 2 of MFR_CHAN_ CONFIG to 1. This bit requires the SHARE_CLK pin to be clocking before the power supply output can start. When the RUN pin is pulled low, the LTC7132 will hold the pin low for the MFR_ RESTART_DELAY. The minimum MFR_RESTART_ DELAY is TOFF_DELAY + TOFF_FALL + 136ms. This delay assures proper sequencing of all rails. The LTC7132 calculates this delay internally and will not process a shorter delay. However, a longer commanded MFR_RESTART_DELAY will be used by the part. The maximum allowed value is 65.52 seconds. VOLTAGE-BASED SEQUENCING The sequence can also be voltage based. As shown in Figure  3, The PGOODn pin is asserted when the UV threshold is exceeded for each output. It is possible to feed the PGOOD pin from one LTC7132 into the RUN pin of the next LTC7132 in the sequence, especially across multiple LTC7132s. The PGOODn has a 60μs filter. If the VOUT voltage bounces around the UV threshold for a long period of time it is possible for the PGOODn output to toggle more than once. To minimize this problem, set the TON_RISE time under 100ms. Voltage-Based Sequencing by Cascading PGs Into RUN Pins START RUN 0 PGOOD0 LTC7132 RUN 1 PGOOD1 RUN 0 PGOOD0 LTC7132 RUN 1 PGOOD1 7132 F03 TO NEXT CHANNEL IN THE SEQUENCE Figure 3. Event (Voltage) Based Sequencing Rev 0 For more information www.analog.com 21 LTC7132 OPERATION If a fault in the string of rails is detected, only the faulted rail and downstream rails will fault off. The rails in the string of devices in front of the faulted rail will remain on unless commanded off. SHUTDOWN The LTC7132 supports two shutdown modes. The first mode is closed-loop shutdown response, with user defined turn-off delay (TOFF_DELAY) and ramp down rate (TOFF_FALL). The controller will maintain the mode of operation for TOFF_FALL. The second mode is discontinuous conduction mode, the controller will not draw current from the load and the fall time will be set by the output capacitance and load current, instead of TOFF_FALL. The shutdown occurs in response to a fault condition or loss of SHARE_CLK (if bit 2 of MFR_CHAN_ CONFIG is set to a 1) or SVIN falling below the VIN_OFF threshold or FAULT pulled low externally (if the MFR_FAULT_ RESPONSE is set to inhibit). Under these conditions the power stage is disabled in order to stop the transfer of energy to the load as quickly as possible. The shutdown state can be entered from the soft-start or active regulation states or through user intervention. There are two ways to respond to faults; which are retry mode and latched off mode. In retry mode, the controller responds to a fault by shutting down and entering the inactive state for a programmable delay time (MFR_RETRY_DELAY). This delay minimizes the duty cycle associated with autonomous retries if the fault that causes the shutdown disappears once the output is disabled. The retry delay time is determined by the longer of the MFR_RETRY_ DELAY command or the time required for the regulated output to decay below 12.5% of the programmed value. If multiple outputs are controlled by the same FAULTn pin, the decay time of the faulted output determines the retry delay. If the natural decay time of the output is too long, it is possible to remove the voltage requirement of the MFR_RETRY_DELAY command by asserting bit 0 of MFR_CHAN_CONFIG. Alternatively, latched off mode means the controller remains latchedoff following a fault and clearing requires user intervention such as toggling RUNn or commanding the part OFF then ON. 22 LIGHT-LOAD CURRENT OPERATION The LTC7132 has two modes of operation: high efficiency discontinuous conduction mode or forced continuous conduction mode. Mode selection is done using the MFR_PWM _MODE command (discontinuous conduction is always the start-up mode, forced continuous is the default running mode). If a controller is enabled for discontinuous operation, the inductor current is not allowed to reverse. The reverse current comparator’s output, IREV, turns off the bottom gate of the external MOSFET just before the inductor current reaches zero, preventing it from reversing and going negative. In forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. The peak inductor current is determined solely by the voltage on the ITH pin. In this mode, the efficiency at light loads is lower than in discontinuous mode operation. However, continuous mode exhibits lower output ripple and less interference with audio circuitry, but may result in reverse inductor current, which can cause the input supply to boost. The VIN_OV_FAULT_LIMIT can detect this and turn off the offending channel. However, this fault is based on an ADC read and can take up to tCONVERT to detect. If there is a concern about the input supply boosting, keep the part in discontinuous conduction mode. If the part is set to discontinuous mode operation, as the inductor average current increases, the controller will automatically modify the operation from discontinuous mode to continuous mode. SWITCHING FREQUENCY AND PHASE The switching frequency of the PWM can be established with an internal oscillator or an external time base. The internal phase-locked loop (PLL) synchronizes PWM control to this timing reference with proper phase relation, whether the clock is provided internally or externally. The device can also be configured to provide the master clock to other ICs through PMBus command, NVM setting, or external configuration resistors as outlined in Table 4. As clock master, the LTC7132 will drive its open-drain SYNC pin at the selected rate with a pulse width of 500ns. Rev 0 For more information www.analog.com LTC7132 OPERATION An external pull-up resistor between SYNC and VDD33 is required in this case. Only one device connected to SYNC should be designated to drive the pin. But if multiple LTC7132s programmed as clock masters are wired to the same SYNC line with a pull-up resistor, just one of the devices is automatically elected to provide clocking, and the others disable their SYNC outputs. The transconductance of the LTC7132 PWM error amplifier can be adjusted using bit[7:5] of the MFR_PWM_COMP command. These two loop compensation parameters can be programmed when device is in operation. Refer to the Programmable Loop Compensation subsection in the Applications Information section for further details. The LTC7132 will automatically revert to an external SYNC input, disabling its own SYNC, as long as the external SYNC frequency is greater than 80% of the programmed SYNC frequency. The external SYNC input shall have a duty cycle between 20% and 80%. OUTPUT VOLTAGE SENSING Whether configured to drive SYNC or not, the LTC7132 can continue PWM operation using its own internal oscillator if an external clock signal is subsequently lost. The device can also be programmed to always require an external oscillator for PWM operation by setting bit 4 of MFR_CONFIG_ALL. The status of the SYNC driver circuit is indicated by bit 10 of MFR_PADS. The MFR_PWM_CONFIG command can be used to configure the phase of each channel. Desired phase can also be set from EEPROM or external configuration resistors as outlined in Table 5. Designated phase is the relationship between the falling edge of SYNC and the internal clock edge that sets the PWM latch to turn on the top power switch. Additional small propagation delays to the PWM control pins will also apply. Both channels must be off before the FREQUENCY_SWITCH and MFR_PWM_CONFIG commands can be written to the LTC7132. The phase relationships and frequency are independent of each other, providing numerous application options. Multiple LTC7132 ICs can be synchronized to realize a PolyPhase array. In this case the phases should be separated by 360/n degrees, where n is the number of phases driving the output voltage rail. PWM LOOP COMPENSATION The internal PWM loop compensation resistors RITHn of the LTC7132 can be adjusted using bit[4:0] of the MFR_ PWM_COMP command. Both channels in LTC7132 have differential amplifiers, which allow the remote sensing of the load voltage between VSENSEn+ and VSENSEn– pins. The telemetry ADC is also fully differential and makes measurements between VSENSEn+ and VSENSEn– pins respectively. The maximum allowed sense voltages for both channels is 5.5V. INTVCC/EXTVCC POWER Power for the top and bottom MOSFET drivers and most of the internal circuitry is derived from the INTVCC pin. When the EXTVCC pin is shorted to GND or tied to a voltage less than 4.7V, an internal 5.5V linear regulator supplies INTVCC power from SVIN. If EXTVCC is taken above 4.7V and SVIN is higher than 7.0V, the 5.5V regulator is turned off and an internal switch is turned on, connecting EXTVCC to INTVCC. Using the EXTVCC allows the INTVCC power to be derived from a high efficiency external source such as a switching regulator output. EXTVCC can provide power to the internal 3.3V linear regulator even when VIN is not present, which allows the LTC7132 to be initialized and programmed even without main power being applied. Each top MOSFET driver is biased from the floating bootstrap capacitor, CB, which normally recharges during each off cycle through an external diode when the bottom MOSFET turns on. If the input voltage VIN decreases to a voltage close to VOUT, the loop may enter dropout and attempt to turn on the top MOSFET continuously. The dropout detector detects this and forces the top MOSFET off for about one-twelfth of the clock period plus 100ns every three cycles to allow CB to recharge. However, it is recommended that a load be present or the IC operates at low frequency during the drop-out transition to ensure CB is recharged. Rev 0 For more information www.analog.com 23 LTC7132 OPERATION LTC7132 10k 4.99k 10k 10k ITH0 ITH1 ITHR0 ITHR1 10k R FAULT0 RUN0 RUN1 ALERT FAULT1 SYNC (ENABLED) SHARE_CLK VDD33 RUN ALERT FAULT SYNC SHARE_CLK 1µF SGND NOTE: SOME CONNECTORS AND COMPONENTS OMITTED FOR CLARITY BOTH CHIPS HAVE THE INTERNAL FREQUENCY COMMAND SET TO THE SAME DESIRED PWM FREQUENCY ITH0 ITHR0 1µF L/DCR ISENSE0+ ISENSE0– VSENSE0+ VSENSE0– C L/DCR R ISENSE1+ ISENSE1– VSENSE1+ VSENSE1– C PGND 1/2 LTC7132 RUN0 ISENSE0+ ALERT ISENSE0– FAULT0 SYNC (DISABLED) VSENSE0+ SHARE_CLK VSENSE0– VDD33 SGND GND L/DCR R C LOAD 7132 F04 Figure 4. Load Sharing Connections for 3-Phase Operation OUTPUT CURRENT SENSING AND SUB-MILLIOHM DCR CURRENT SENSING For DCR current sense applications, a resistor in series with a capacitor is placed across the inductor. In this configuration, the resistor is tied to the SW side of the inductor while the capacitor is tied to the load side of the inductor as shown in Figure 4. If the RC values are chosen such that the RC time constant matches the inductor time constant (L/DCR, where DCR is the inductor series resistance), the resultant voltage appearing across the capacitor equals the voltage across the inductor series resistance (VDCR) and thus represents the current flowing through the inductor. In addition to this regular current sensing, the LTC7132 employs a unique architecture to enhance the signal-to-noise ratio by 14dB, enabling it to operate with a small sense signal (as low as 2mV) via a sub-milliohm value of inductor DCR (such as 0.2mΩ) to improve the power efficiency for the heavy load applications while VOUT ≤ 3.5V. As shown in Figure 4, externally the new architecture only requires reducing R by 4/5, i.e., RLOWDCR = 1/5Rnomdcr. Better signal-to-noise ratio helps to reduce jitter at the output with as low as 2mV sensing signal. Low DCR improves power efficiency in heavy 24 system loads. So the new DCR sensing scheme provides a perfect solution for larger power, and noise sensitive systems. In the meantime, the current limit threshold is still a function of the inductor peak current and its DCR value, and can be accurately set with the MFR_PWM_MODE[2], MFR_PWM_MODE[7]. See Figure 26. The RC calculations are based on the room temperature DCR of the inductor. The RC time constant should remain constant as a function of temperature. This assures the transient response of the circuit is the same regardless of the temperature. The DCR of the inductor has a large temperature coefficient, approximately 3900ppm/°C. The temperature coefficient of the inductor must be written to the MFR_IOUT_CAL_GAIN_TC register. The external temperature is sensed near the inductor and used to modify the internal current limit circuit to maintain an essentially constant current limit with temperature. In this application, the ISENSEn+ pin is connected to the FET side of the DCR sensing filter capacitor while the ISENSEn– pin is placed on the load side of the capacitor. The current sensed from the input is then given by the expression VDCR/DCR. VDCR is digitized by the LTC7132’s telemetry ADC with an input range of ±128mV, a noise Rev 0 For more information www.analog.com LTC7132 OPERATION floor of 7μVRMS, and a peak-peak noise of approximately 46.5μV. The LTC7132 computes the inductor current using the DCR value stored in the IOUT_CAL_GAIN command and the temperature coefficient stored in command MFR_IOUT_CAL_GAIN_TC. The resulting current value is returned by the READ_IOUT command. Multiple chips need to tie all the VSENSE+ pins together, and all the VSENSE– pins together, and ITHR and ITH together as well. Do not assert bit[5] of MFR_PWM_CONFIG except in a PolyPhase application. EXTERNAL/INTERNAL TEMPERATURE SENSE INPUT CURRENT SENSING To sense the total input current consumed by the LTC7132 and the power stage, a resistor is placed between the input supply voltage and the PVIN pins. The IIN+ and IIN– pins are connected to the sense resistor. The filtered voltage is amplified by the internal high side current sense amplifier and digitized by the LTC7132’s telemetry ADC. The input current sense amplifier has three gain settings of 2x, 4x, and 8x set by the bit[6:5] of the MFR_PWM_CONFIG command. The maximum input sense voltage for the three gain settings is 50mV, 20mV, and 5mV respectively. The LTC7132 computes the input current using the R value stored in the IIN_CAL_GAIN command. The resulting measured power stage current is returned by the READ_ IIN command. The LTC7132 uses the RVIN resistor to measure the VIN pin supply current being consumed by the LTC7132. This value is returned by the MFR_READ_ICHIP command. The chip current is calculated by using the R value stored in the MFR_RVIN command. Refer to the subsection titled Input Current Sense Amplifier in the Applications Information section for further details. PolyPhase LOAD SHARING Multiple LTC7132s can be arrayed in order to provide a balanced load-share solution by bussing the necessary pins. Figure 4 illustrates the shared connections required for load sharing. If an external oscillator is not provided, the SYNC pin should only be enabled on one of the LTC7132s. The other(s) should be programmed to disable SYNC using bit 4 of MFR_CONFIG_ALL. If an external oscillator is present, the chip with the SYNC pin enabled will detect the presence of the external clock and disable its output. External temperature can best be measured using a remote, diode-connected PNP transistor such as the MMBT3906.The emitter should be connected to a TSNS pin while the base and collector terminals of the PNP transistor should be returned directly to the LTC7132 SGND pin. Two different currents are applied to the diode TSNS LTC7132 SGND SGND 10nF MMBT3906 7132 F05 Figure 5. Temperature Sense Circuit (nominally 2μA and 32μA) and the temperature is calculated from a ∆VBE measurement made with the internal 16-bit monitor ADC (see Figure 5). The LTC7132 also supports direct VBE based external temperature measurements. In this case the diode or diode network is trimmed to a specific voltage at a specific current and temperature. In general this method does not yield as accurate result as the single PNP transistor ∆VBE method, but may function better in a noisy application. Refer to MFR_PWM_MODE in the PMBus Command Details section for additional information on programming the LTC7132 for these two external temperature sense configurations. The calculated temperature is returned by the PMBus READ_TEMPERATURE_1 command. Refer to the Applications Information section for details on proper layout of external temperature sense elements and PMBus commands that can be used to improve the accuracy of calculated temperatures. The READ_TEMPERATURE_2 command returns the internal junction temperature of the LTC7132 using an on-chip diode with a ∆VBE measurement and calculation. Rev 0 For more information www.analog.com 25 LTC7132 OPERATION The slope of the external temperature sensor can be modified with the temperature slope coefficient stored in MFR_TEMP_1_GAIN. Typical PNPs require temperature slope adjustments slightly less than 1. The MMBT3906 has a recommended value in this command of approximately MFR_TEMP_1_GAIN = 0.991 based on the ideality factor of 1.01. Simply invert the ideality factor to calculate the MFR_TEMP_1_GAIN. Different manufacturers and different lots may have different ideality factors. Consult with the manufacturer to set this value. The offset of the external temperature sense can be adjusted by MFR_TEMP_1_OFFSET. A value of 0 in this register sets the temperature offset to –273.15°C. If the PNP cannot be placed in direct contact with the inductor, the slope or offset can be increased to account for temperature mismatches. If the user is adjusting the slope, the intercept point is at absolute zero, –273.15°C, so small adjustments in slope can change the apparent measured temperature significantly. Another way to artificially increase the slope of the temperature term is to increase the MFR_IOUT_CAL_GAIN_TC term. This will modify the temperature slope with respect to room temperature. RCONFIG (RESISTOR CONFIGURATION) PINS There are six input pins utilizing 1% resistor dividers between VDD25 and SGND to select key operating parameters. The pins are ASEL0, ASEL1, FREQ_CFG, VOUT0_CFG, VOUT1_CFG, PHASE_CFG. Refer to Tables 3, 4, 5 and 6 for more details of recommended values of these resistive dividers. If pins are floated, the value stored in the corresponding NVM command is used. If bit 6 of the MFR_CONFIG_ALL configuration command is asserted in NVM, the resistor inputs are ignored upon power-up except for ASEL0 and ASEL1 which are always respected. The resistor configuration pins are only measured during a power-up reset or after a MFR_RESET or after a RESTORE_USER_ALL command is executed. The VOUTn_CFG pin settings are described in Table 3. These pins select the output voltages for the LTC7132’s analog PWM controllers. If the pin is open, the VOUT_COMMAND command is loaded from NVM to determine the output voltage. The default setting is to have the switcher off unless the voltage configuration pins are installed. 26 The following parameters are set as a percentage of the output voltage if the RCONFIG pins are used to determine the output voltage: n n n n n n n VOUT_OV_FAULT_LIMIT................................... +10% VOUT_OV_WARN_LIMIT.................................. +7.5% VOUT_MAX....................................................... +7.5% VOUT_MARGIN_HIGH............................................5% VOUT_MARGIN_LOW.............................................5% VOUT_UV_WARN_LIMIT.....................................6.5% VOUT_UV_FAULT_LIMIT........................................7% The FREQ_CFG pin settings are described in Table 4. This pin selects the switching frequency. The phase relationships between the two channels and SYNC pin are determined by the PHASE_CFG pin described in Table 5. To synchronize to an external clock, the part should be put into external clock mode (SYNC output disabled but frequency set to the nominal value). If no external clock is supplied, the part will clock at the programmed frequency. If the application is multiphase and the SYNC signal between chips is lost, the parts will not operate at the designed phase even if they are programmed and trimmed to the same frequency. This may increase the ripple voltage on the output, possibly produce undesirable operation. If the external SYNC signal is being generated internally and external SYNC is not selected, bit 10 of MFR_PADS will be asserted. If no frequency is selected and the external SYNC frequency is not present, a PLL_FAULT will occur. If the user does not wish to see the ALERT from a PLL_FAULT even if there is not a valid synchronization signal at power-up, the ALERT mask for PLL_FAULT must be written. See the description on SMBALERT_MASK for more details. If the SYNC pin is connected between multiple ICs only one of the ICs should have the SYNC pin enabled, and all other ICs should be configured to have the SYNC pin disabled. The ASEL0,1 pin settings are described in Table 6. ASEL1 selects the top 3 bits of the slave address for the LTC7132. ASEL0 selects the bottom 4 bits of the slave address for the LTC7132. If ASEL1 is floating, the 3 most significant bits are retrieved from the NVM MFR_ADDRESS command. If ASEL0 is floating, the 4 LSB bits stored in NVM MFR_ ADDRESS command are used to determine the 4 LSB bits of the slave address. For more detail, refer to Table 6. Rev 0 For more information www.analog.com LTC7132 OPERATION Note: Per the PMBus specification, pin programmed parameters can be overridden by commands from the digital interface with the exception of ASEL which is always honored. Do not set any part address to 0x5A or 0x5B because these are global addresses and all parts will respond to them. FAULT DETECTION AND HANDLING A variety of fault and warning reporting and handling mechanisms are available. Fault and warning detection capabilities include: Input OV FAULT Protection and UV Warning n Average Input OC Warn n Output OV/UV Fault and Warn Protection n Output OC Fault and Warn Protection command operation is performed. The MFR_FAULT_ PROPAGATE command determines if the FAULT pins are pulled low when a fault is detected. Output and input fault event handling is controlled by the corresponding fault response byte as specified in Tables 7 to 12. Shutdown recovery from these types of faults can either be autonomous or latched. For autonomous recovery, the faults are not latched, so if the fault conditions not present after the retry interval has elapsed, a new soft-start is attempted. If the fault persists, the controller will continue to retry. The retry interval is specified by the MFR_RETRY_DELAY command and prevents damage to the regulator components by repetitive power cycling, assuming the fault condition itself is not immediately destructive. The MFR_RETRY_DELAY must be greater than 120ms. It can not exceed 83.88 seconds. n Internal and External Overtemperature Fault and Warn Protection n External Undertemperature Fault and Warn Protection n CML Fault (Communication, Memory or Logic) n External Fault Detection via the Bidirectional FAULTn Pins. n In addition, the LTC7132 can map any combination of fault indicators to their respective FAULTn pin using the propagate FAULTn response commands, MFR_FAULT_ PROPAGATE. Typical usage of a FAULTn pin is as a driver for an external crowbar device, overtemperature alert, overvoltage alert or as an interrupt to cause a microcontroller to poll the fault commands. Alternatively, the FAULTn pins can be used as inputs to detect external faults downstream of the controller that require an immediate response. Any fault or warning event will always cause the ALERT pin to assert low unless the fault or warning is masked by the SMBALERT_MASK. The pin will remain asserted low until the CLEAR_FAULTS command is issued, the fault bit is written to a 1 or bias power is cycled or a MFR_RESET command is issued, or the RUN pins are toggled OFF/ON or the part is commanded OFF/ON via PMBus or an ARA Status Registers and ALERT Masking Figure 6 summarizes the internal LTC7132 status registers accessible by PMBus command. These contain indication of various faults, warnings and other important operating conditions. As shown, the STATUS_BYTE and STATUS_WORD commands also summarize contents of other status registers. Refer to PMBus Command Details for specific information. NONE OF THE ABOVE in STATUS_BYTE indicates that one or more of the bits in the most-significant nibble of STATUS_WORD are also set. In general, any asserted bit in a STATUS_x register also pulls the ALERT pin low. Once set, ALERT will remain low until one of the following occurs. n A CLEAR_FAULTS or MFR_RESET Command Is Issued The Related Status Bit Is Written to a One n The Faulted Channel Is Properly Commanded Off and Back On n The LTC7132 Successfully Transmits Its Address During a PMBus ARA n Bias Power Is Cycled n Rev 0 For more information www.analog.com 27 LTC7132 OPERATION STATUS_WORD STATUS_VOUT* 7 6 5 4 3 2 1 0 VOUT_OV Fault VOUT_OV Warning VOUT_UV Warning VOUT_UV Fault VOUT_MAX Warning TON_MAX Fault TOFF_MAX Warning (reads 0) 15 14 13 12 11 10 9 8 VOUT IOUT INPUT MFR_SPECIFIC POWER_GOOD# (reads 0) (reads 0) (reads 0) 7 6 5 4 3 2 1 0 BUSY OFF VOUT_OV IOUT_OC (reads 0) TEMPERATURE CML NONE OF THE ABOVE STATUS_BYTE (PAGED) STATUS_IOUT 7 6 5 4 3 2 1 0 IOUT_OC Fault (reads 0) IOUT_OC Warning (reads 0) (reads 0) (reads 0) (reads 0) (reads 0) MFR_COMMON 7 6 5 4 3 2 1 0 STATUS_TEMPERATURE OT Fault OT Warning (reads 0) UT Fault (reads 0) (reads 0) (reads 0) (reads 0) (PAGED) STATUS_CML 7 6 5 4 3 2 1 0 Chip Not Driving ALERT Low Chip Not Busy Internal Calculations Not Pending Output Not In Transition EEPROM Initialized (reads 0) SHARE_CLK_LOW WP Pin High Invalid/Unsupported Command Invalid/Unsupported Data Packet Error Check Failed Memory Fault Detected Processor Fault Detected (reads 0) Other Communication Fault Other Memory or Logic Fault Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved EEPROM ECC Status Reserved Reserved Reserved Reserved DESCRIPTION General Fault or Warning Event General Non-Maskable Event Dynamic Status Derived from Other Bits 7 6 5 4 3 2 1 0 Internal Temperature Fault Internal Temperature Warning EEPROM CRC Error Internal PLL Unlocked Fault Log Present VDD33 UV or OV Fault VOUT Short Cycled FAULT Pulled Low By External Device (PAGED) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VDD33 OV Fault VDD33 UV Fault (reads 0) (reads 0) Invalid ADC Result(s) SYNC Clocked by External Source Channel 1 is POWER_GOOD Channel 0 is POWER_GOOD LTC7132 Forcing RUN1 Low LTC7132 Forcing RUN0 Low RUN1 Pin State RUN0 Pin State LTC7132 Forcing FAULT1 Low LTC7132 Forcing FAULT0 Low FAULT1 Pin State FAULT0 Pin State MFR_PADS MFR_INFO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VIN_OV Fault (reads 0) VIN_UV Warning (reads 0) Unit Off for Insuffcient VIN (reads 0) IIN_OC Warning (reads 0) STATUS_MFR_SPECIFIC (PAGED) (PAGED) 7 6 5 4 3 2 1 0 STATUS_INPUT 7 6 5 4 3 2 1 0 7132 F07 MASKABLE GENERATES ALERT BIT CLEARABLE Yes No No No Yes Yes No Not Directly Yes Yes No No Figure 6. LTC7132 Status Register Summary 28 Rev 0 For more information www.analog.com LTC7132 OPERATION With some exceptions, the SMBALERT_MASK command can be used to prevent the LTC7132 from asserting ALERT for bits in these registers on a bit-by-bit basis. These mask settings are promoted to STATUS_WORD and STATUS_BYTE in the same fashion as the status bits themselves. For example, if ALERT is masked for all bits in Channel 0 STATUS_VOUT, then ALERT is effectively masked for the VOUT bit in STATUS_WORD for PAGE 0. faults cleared when either RUN pin is toggled or, set bit 0 of MFR_CONFIG_ALL to a 1. The BUSY bit in STATUS_BYTE also asserts ALERT low and cannot be masked. This bit can be set as a result of various internal interactions with PMBus communication. This fault occurs when a command is received that cannot be safely executed with one or both channels enabled. As discussed in Application Information, BUSY faults can be avoided by polling MFR_COMMON before executing some commands. The PGOODn pins of the LTC7132 are connected to the open drains of internal MOSFETs. The MOSFETs turn on and pull the PGOODn pins low when the channel output voltage is not within the channel’s UV and OV voltage thresholds. During TON_DELAY and TON_RISE sequencing, the PGOODn pin is held low. The PGOODn pin is also pulled low when the respective RUNn pin is low. The PGOODn pin response is deglitched by an internal 60μs digital filter. The PGOODn pin and PGOOD status may be different at times due to communication latency of up to 10µs. If masked faults occur immediately after power up, ALERT may still be pulled low because there has not been time to retrieve all of the programmed masking information from EEPROM. Status information contained in MFR_COMMON and MFR_PADS can be used to further debug or clarify the contents of STATUS_BYTE or STATUS_WORD as shown, but the contents of these registers do not affect the state of the ALERT pin and may not directly influence bits in STATUS_BYTE or STATUS_WORD. Mapping Faults to FAULT Pins Channel-to-channel fault (including channels from multiple LTC7132s) dependencies can be created by connecting FAULTn pins together. In the event of an internal fault, one or more of the channels is configured to pull the bussed FAULTn pins low. The other channels are then configured to shut down when the FAULTn pins are pulled low. For autonomous group retry, the faulted channel is configured to let go of the FAULTn pin(s) after a retry interval, assuming the original fault has cleared. All the channels in the group then begin a soft-start sequence. If the fault response is LATCH_OFF, the FAULTn pin remains asserted low until either the RUN pin is toggled OFF/ON or the part is commanded OFF/ON. The toggling of the RUN either by the pin or OFF/ON command will clear faults associated with the channel. If it is desired to have all The status of all faults and warnings is summarized in the STATUS_WORD and STATUS_BYTE commands. Additional fault detection and handling capabilities are: Power Good Pins CRC Protection The integrity of the NVM memory is checked after a power on reset. A CRC error will prevent the controller from leaving the inactive state. If a CRC error occurs, the CML bit is set in the STATUS_BYTE and STATUS_WORD commands, the appropriate bit is set in the STATUS_MFR_SPECIFIC command, and the ALERT pin will be pulled low. NVM repair can be attempted by writing the desired configuration to the controller and executing a STORE_USER_ALL command followed by a CLEAR_FAULTS command. The LTC7132 manufacturing section of the NVM is mirrored. If both copies are corrupted, the “NVM CRC Fault” in the STATUS_MFR_SPECIFIC command is set. If this bit remains set after being cleared by issuing a CLEAR_ FAULTS or writing a 1 to this bit, an irrecoverable internal fault has occurred. The user is cautioned to disable both output power supply rails associated with this specific part. There are no provisions for field repair of NVM faults in the manufacturing section. SERIAL INTERFACE The LTC7132 serial interface is a PMBus compliant slave device and can operate at any frequency between Rev 0 For more information www.analog.com 29 LTC7132 OPERATION 10kHz and 400kHz. The address is configurable using either the NVM or an external resistor divider. In addition the LTC7132 always responds to the global broadcast address of 0x5A (7 bit) or 0x5B (7 bit). The serial interface supports the following protocols defined in the PMBus specifications: 1) send command, 2) write byte, 3) write word, 4) group, 5) read byte, 6) read word and 7) read block. 8) write block. All read operations will return a valid PEC if the PMBus master requests it. If the PEC_REQUIRED bit is set in the MFR_CONFIG_ALL command, the PMBus write operations will not be acted upon until a valid PEC has been received by the LTC7132. Communication Protection PEC write errors (if PEC_REQUIRED is active), attempts to access unsupported commands, or writing invalid data to supported commands will result in a CML fault. The CML bit is set in the STATUS_BYTE and STATUS_WORD commands, the appropriate bit is set in the STATUS_CML command, and the ALERT pin is pulled low. channel being acted upon. Device addressing can be disabled by writing a value of 0x80 to the MFR_ADDRESS. Rail addressing provides a means for the bus master to simultaneously communicate with all channels connected together to produce a single output voltage (PolyPhase). While similar to global addressing, the rail address can be dynamically assigned with the paged MFR_RAIL_ ADDRESS command, allowing for any logical grouping of channels that might be required for reliable system control. Reading from rail addresses is also strongly discouraged. All four means of PMBus addressing require the user to employ disciplined planning to avoid addressing conflicts. Communication to LTC7132 devices at global and rail addresses should be limited to command write operations. RESPONSES TO VOUT and IIN/IOUT FAULTS VOUT OV and UV conditions are monitored by comparators. The OV and UV limits are set in three ways. DEVICE ADDRESSING n The LTC7132 offers five different types of addressing over the PMBus interface, specifically: 1) global, 2) device, 3) rail addressing and 4) alert response address (ARA). n Global addressing provides a means of the PMBus master to address all LTC7132 devices on the bus. The LTC7132 global address is fixed 0x5A (7 bit) or 0xB4 (8 bit) and cannot be disabled. Commands sent to the global address act the same as if PAGE is set to a value of 0xFF. Commands sent are written to both channels simultaneously. Global command 0x5B (7 bit) or 0xB6 (8 bit) is paged and allows channel specific command of all LTC7132 devices on the bus. Other ADI device types may respond at one or both of these global addresses. Reading from global addresses is strongly discouraged. Device addressing provides the standard means of the PMBus master communicating with a single instance of an LTC7132. The value of the device address is set by a combination of the ASEL0 and ASEL1 configuration pins and the MFR_ ADDRESS command. When this addressing means is used, the PAGE command determines the 30 As a Percentage of the VOUT if Using the Resistor Configuration Pins In NVM if Either Programmed at the Factory or Through the GUI By PMBus Command n The IIN and IOUT overcurrent monitors are performed by ADC readings and calculations. Thus these values are based on average currents and can have a time latency of up to tCONVERT. The IOUT calculation accounts for the DCR or sense resistor and their temperature coefficient. The input current is equal to the voltage measured across the RIINSNS resistor divided by the resistors value as set with the MFR_IIN_CAL_GAIN command. If this calculated input current exceeds the IN_OC_WARN_LIMIT the ALERT pin is pulled low and the IIN_OC_WARN bit is asserted in the STATUS_INPUT command. The digital processor within the LTC7132 provides the ability to ignore the fault, shut down and latch off or shut down and retry indefinitely (hiccup). The retry interval is set in MFR_RETRY_ DELAY and can be from 120ms Rev 0 For more information www.analog.com LTC7132 OPERATION to 83.88 seconds in 1ms increments. The shutdown for OV/UV and OC can be done immediately or after a user selectable deglitch time. Output Overvoltage Fault Response A programmable overvoltage comparator (OV) guards against transient overshoots as well as long-term overvoltages at the output. In such cases, the top MOSFET is turned off and the bottom MOSFET is turned on. However, the reverse output current is monitored while device is in OV fault. When it reaches the limit, both top and bottom MOSFETs are turned off. The top and bottom MOSFETs will keep their state until the overvoltage condition is cleared regardless of the PMBus VOUT_OV_FAULT_RESPONSE command byte value. This hardware level fault response delay is typically 2μs from the overvoltage condition to BG asserted high. Using the VOUT_OV_FAULT_RESPONSE command, the user can select any of the following behaviors: OV Pull-Down Only (OV Cannot Be Ignored) n Shut Down (Stop Switching) Immediately—Latch Off n n Shut Down Immediately—Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY Either the Latch Off or Retry fault responses can be deglitched in increments of (0-7) • 10μs. See Table 7. Output Undervoltage Response The response to an undervoltage comparator output can be the following: circuit operates by limiting the ITH maximum voltage. If DCR sensing is used, the ITH maximum voltage has a temperature dependency directly proportional to the TC of the DCR of the inductor. The LTC7132 automatically monitors the external temperature sensors and modifies the maximum allowed ITH to compensate for this term. The overcurrent fault processing circuitry can execute the following behaviors: Current Limit Indefinitely n Shut Down Immediately—Latch Off n n The overcurrent responses can be deglitched in increments of (0-7) • 16ms. See Table 9. RESPONSES TO TIMING FAULTS TON_MAX_FAULT_LIMIT is the time allowed for VOUT to rise and settle at start-up. The TON_MAX_FAULT_LIMIT condition is predicated upon detection of the VOUT_UV_ FAULT_LIMIT as the output is undergoing a SOFT_START sequence. The TON_MAX_ FAULT_LIMIT time is started after TON_DELAY has been reached and a SOFT_START sequence is started. The resolution of the TON_MAX_ FAULT_LIMIT is 10μs. If the VOUT_UV_FAULT _LIMIT is not reached within the TON_MAX_FAULT_LIMIT time, the response of this fault is determined by the value of the TON_MAX_FAULT_RESPONSE command value. This response may be one of the following: Ignore Ignore n Shut Down Immediately—Latch Off n Shut Down Immediately—Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY. n n Shut Down (Stop Switching) Immediately—Latch Off n n Shut Down Immediately—Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY. The UV responses can be deglitched. See Table 8. Peak Output Overcurrent Fault Response Due to the current mode control algorithm, peak output current across the inductor is always limited on a cycleby-cycle basis. The value of the peak current limit is specified in sense voltage in the EC table. The current limit Shut Down Immediately—Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY. This fault response is not deglitched. A value of 0 in TON_MAX_FAULT_LIMIT means the fault is ignored. The TON_MAX_FAULT_LIMIT should be set longer than the TON_RISE time. It is recommended TON_MAX_FAULT_ LIMIT always be set to a non-zero value, otherwise the output may never come up and no flag will be set to the user. See Table 11. Rev 0 For more information www.analog.com 31 LTC7132 OPERATION RESPONSES TO VIN OV FAULTS VIN overvoltage is measured with the ADC. The response is naturally deglitched by the 90ms typical response time of the ADC. The fault responses are: Input overcurrent and output undercurrent are measured with the ADC. The fault responses are: Ignore n Ignore Shut Down Immediately—Latch Off n n Shut Down Immediately—Latch Off n Shut Down Immediately—Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY. See Table 11. n Shut Down Immediately—Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY RESPONSES TO EXTERNAL FAULTS Internal Overtemperature Fault Response An internal temperature sensor protects against NVM damage. Above 85°C, no writes to NVM are recommended. Above 130°C, the internal overtemperature warn threshold is exceeded and the part disables the NVM and does not re-enable until the temperature has dropped to 125°C. When the die temperature exceed 160°C the internal temperature fault response is enabled and the PWM is disabled until the die temperature drops below 150°C. Temperature is measured by the ADC. Internal temperature faults cannot be ignored. Internal temperature limits cannot be adjusted by the user. See Table 10. External Overtemperature and Undertemperature Fault Response Two external temperature sensors can be used to sense the temperature of critical circuit elements like inductors and power MOSFETs. The OT_FAULT_ RESPONSE and UT_FAULT_ RESPOSE commands are used to determine the appropriate response to an overtemperature and under temperature condition, respectively. If no external sense elements are used (not recommended) set the UT_FAULT_RESPONSE to ignore and set the UT_FAULT_ LIMIT to –275°C. The fault responses are: Ignore n Shut Down Immediately—Latch Off n Shut Down Immediately—Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY. See Table 9. 32 n See Table 11. RESPONSES TO OT/UT FAULTS n RESPONSES TO INPUT OVERCURRENT AND OUTPUT UNDERCURRENT FAULTS When either FAULTn pin is pulled low, the OTHER bit is set in the STATUS_WORD command, the appropriate bit is set in the STATUS_MFR_SPECIFIC command, and the ALERT pin is pulled low. Responses are not deglitched. Each channel can be configured to ignore or shut down then retry in response to its FAULTn pin going low by modifying the MFR_FAULT_RESPONSE command. To avoid the ALERT pin asserting low when FAULT is pulled low, assert bit 1 of MFR_CHAN_CONFIG, or mask the ALERT using the SMBALERT_MASK command. FAULT LOGGING The LTC7132 has fault logging capability. Data is logged into memory in the order shown in Table 13. The data is stored in a continuously updated buffer in RAM. When a fault event occurs, the fault log buffer is copied from the RAM buffer into NVM. Fault logging is allowed at temperatures above 85°C; however, retention of 10 years is not guaranteed. When the die temperature exceeds 130°C the fault logging is delayed until the die temperature drops below 125°C. The fault log data remains in NVM until a MFR_FAULT _LOG_CLEAR command is issued. Issuing this command re-enables the fault log feature. Before reenabling fault log, be sure no faults are present and a CLEAR_FAULTS command has been issued. When the LTC7132 powers-up or exits its reset state, it checks the NVM for a valid fault log. If a valid fault log exists in NVM, the “Valid Fault Log” bit in the Rev 0 For more information www.analog.com LTC7132 OPERATION STATUS_MFR_SPECIFIC command will be set and an ALERT event will be generated. Also, fault logging will be blocked until the LTC7132 has received a MFR_ FAULT_LOG_CLEAR command before fault logging will be re-enabled. The information is stored in EEPROM in the event of any fault that disables the controller on either channel. A FAULTn being externally pulled low will not trigger a fault logging event. BUS TIMEOUT PROTECTION The LTC7132 implements a timeout feature to avoid persistent faults on the serial interface. The data packet timer begins at the first START event before the device address write byte. Data packet information must be completed within 30ms or the LTC7132 will three-state the bus and ignore the given data packet. If more time is required, assert bit 3 of MFR_CONFIG_ALL to allow typical bus timeouts of 255ms. Data packet information includes the device address byte write, command byte, repeat start event (if a read operation), device address byte read (if a read operation), all data bytes and the PEC byte if applicable. The LTC7132 allows longer PMBus timeouts for block read data packets. This timeout is proportional to the length of the block read. The additional block read timeout applies primarily to the MFR_FAULT_LOG command. The timeout period defaults to 32ms. The user is encouraged to use as high a clock rate as possible to maintain efficient data packet transfer between all devices sharing the serial bus interface. The LTC7132 supports the full PMBus frequency range from 10kHz to 400kHz. SIMILARITY BETWEEN PMBus, SMBus AND I2C 2-WIRE INTERFACE The PMBus 2-wire interface is an incremental extension of the SMBus. SMBus is built upon I2C with some minor differences in timing, DC parameters and protocol. The PMBus/SMBus protocols are more robust than simple I2C byte commands because PMBus/SMBus provide timeouts to prevent persistent bus errors and optional packet error checking (PEC) to ensure data integrity. In general, a master device that can be configured for I2C communication can be used for PMBus communication with little or no change to hardware or firmware. Repeat start (restart) is not supported by all I2C controllers but is required for SMBus/PMBus reads. If a general purpose I2C controller is used, check that repeat start is supported. The LTC7132 supports the maximum SMBus clock speed of 100kHz and is compatible with the higher speed PMBus specification (between 100kHz and 400kHz) if MFR_ COMMON polling or clock stretching is enabled. For robust communication and operation refer to the Note section in the PMBus command summary. Clock stretching is enabled by asserting bit 1 of MFR_CONFIG_ALL. For a description of the minor extensions and exceptions PMBus makes to SMBus, refer to PMBus Specification Part 1 Revision 1.2: Paragraph 5: Transport. For a description of the differences between SMBus and I2C, refer to System Management Bus (SMBus) Specification Version 2.0: Appendix B—Differences Between SMBus and I2C. PMBus SERIAL DIGITAL INTERFACE The LTC7132 communicates with a host (master) using the standard PMBus serial bus interface. The Timing Diagram, Figure 7, shows the timing relationship of the signals on the bus. The two bus lines, SDA and SCL, must be high when the bus is not in use. External pull-up resistors or current sources are required on these lines. The LTC7132 is a slave device. The master can communicate with the LTC7132 using the following formats: Master Transmitter, Slave Receiver n Master Receiver, Slave Transmitter n Rev 0 For more information www.analog.com 33 LTC7132 OPERATION The following PMBus protocols are supported: Master reads slave immediately after the first byte. At the moment of the first acknowledgment (provided by the slave receiver) the master transmitter becomes a master receiver and the slave receiver becomes a slave transmitter. n Write Byte, Write Word, Send Byte n Read Byte, Read Word, Block Read, Block Write n Alert Response Address n Combined format. During a change of direction within a transfer, the master repeats both a start condition and the slave address but with the R/W bit reversed. In this case, the master receiver terminates the transfer by generating a NACK on the last byte of the transfer and a STOP condition. Figures 8-25 illustrate the aforementioned PMBus protocols. All transactions support PEC and GCP (group command protocol). The Block Read supports 255 bytes of returned data. For this reason, the PMBus timeout may be extended when reading the fault log. n Figure 8 is a key to the protocol diagrams in this section. PEC is optional. Refer to Figure 8 for a legend. Handshaking features are included to ensure robust system communication. Please refer to the PMBus Communication and Command Processing subsection of the Applications Information section for further details. A value shown below a field in the following figures is mandatory value for that field. The data formats implemented by PMBus are: Master transmitter transmits to slave receiver. The transfer direction in this case is not changed. n SDA tf tr tLOW tSU(DAT) tHD(SDA) tf tSP tr tBUF SCL tHD(STA) tHD(DAT) tSU(STA) tHIGH tSU(STO) 7132 F08 START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION Figure 7. Timing Diagram Table 1. Abbreviations of Supported Data Formats PMBus TERMINOLOGY SPECIFICATION ADI REFERENCE TERMINOLOGY DEFINITION L11 Linear Part II ¶7.1 Linear_5s_1s L16 Linear VOUT_MODE Part II ¶8.2 Linear_16u CF DIRECT Part II ¶7.2 Varies Reg register bits Part II ¶10.3 Reg ASC text characters Part II ¶22.2.1 ASCII 34 Floating point 16-bit data: value = Y • 2N, where N = b[15:11] and Y = b[10:0], both two’s compliment binary integers. EXAMPLE b[15:0] = 0x9807 = 10011_000_0000_0111 value = 7 • 2–13 = 854E-6 Floating point 16-bit data: value = Y • 2–12, b[15:0] = 0x4C00 = 0100_1100_0000_0000 where Y = b[15:0], an unsigned integer. value = 19456 • 2–12 = 4.75 16-bit data with a custom format defined in the detailed PMBus command description. Often an unsigned or two’s compliment integer. Per-bit meaning defined in detailed PMBus PMBus STATUS_BYTE command. command description. ISO/IEC 8859-1 [A05] LTC (0x4C5443) Rev 0 For more information www.analog.com LTC7132 OPERATION S START CONDITION Sr REPEATED START CONDITION Rd READ (BIT VALUE OF 1) Wr WRITE (BIT VALUE OF 0) A ACKNOWLEDGE (THIS BIT POSITION MAY BE 0 FOR AN ACK OR 1 FOR A NACK) P STOP CONDITION PEC PACKET ERROR CODE MASTER TO SLAVE SLAVE TO MASTER ... CONTINUATION OF PROTOCOL 7132 F07 Figure 8. PMBus Packet Protocol Diagram Element Key 1 7 S 1 1 SLAVE ADDRESS Rd/Wr A 1 P 7132 F08 Figure 9. Quick Command Protocol 1 7 S 1 1 SLAVE ADDRESS Wr A COMMAND CODE A 1 1 8 P 7132 F09 Figure 10. Send Byte Protocol 1 S 7 1 1 8 1 SLAVE ADDRESS Wr A COMMAND CODE A 8 1 PEC A 1 P 7132 F12 Figure 11. Send Byte Protocol with PEC 1 S 7 1 1 8 1 SLAVE ADDRESS Wr A COMMAND CODE A 8 1 1 DATA BYTE A P 7132 F13 Figure 12. Write Byte Protocol 1 S 7 1 1 8 1 SLAVE ADDRESS Wr A COMMAND CODE A 8 1 8 1 1 DATA BYTE A PEC A P 7132 F14 Figure 13. Write Byte Protocol with PEC 1 S 7 1 1 8 1 SLAVE ADDRESS Wr A COMMAND CODE A 8 1 DATA BYTE A 1 P 7132 F15 Figure 14. Write Word Protocol 1 S 7 1 1 8 1 SLAVE ADDRESS Wr A COMMAND CODE A 8 1 8 1 1 DATA BYTE A PEC A P 7132 F16 Figure 15. Write Word Protocol with PEC Rev 0 For more information www.analog.com 35 LTC7132 OPERATION 1 7 S 1 1 8 1 1 1 7 1 SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A 8 1 1 DATA BYTE A P 7132 F17 Figure 16. Read Byte Protocol 1 S 7 1 1 8 1 1 7 1 8 1 DATA BYTE A 1 SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A PEC 1 1 A P 7132 F18 Figure 17. Read Byte Protocol with PEC 1 S 7 1 1 8 1 1 SLAVE ADDRESS Wr A COMMAND CODE A 7 1 1 Sr SLAVE ADDRESS Rd A 8 1 DATA BYTE LOW A 1 1 DATA BYTE HIGH A 8 P 7132 F19 Figure 18. Read Word Protocol 1 S 7 1 1 8 1 1 7 1 1 SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A 8 1 DATA BYTE LOW A 8 1 DATA BYTE HIGH A 8 1 1 PEC A P 7132 F20 Figure 19. Read Word Protocol with PEC 1 S 7 1 1 8 1 1 7 1 1 SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A 8 1 BYTE COUNT = N A 8 1 8 1 … 8 1 DATA BYTE 1 A DATA BYTE 2 A … DATA BYTE N A … 1 P 7132 F21 Figure 20. Block Read Protocol 1 S 7 1 1 8 1 1 7 1 1 SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A 8 1 BYTE COUNT = N A 8 1 8 1 … 8 1 8 1 1 DATA BYTE 1 A DATA BYTE 2 A … DATA BYTE N A PEC A P … 7132 F22 Figure 21. Block Read Protocol with PEC 36 Rev 0 For more information www.analog.com LTC7132 OPERATION 1 S 7 1 1 8 1 8 1 SLAVE ADDRESS Wr A COMMAND CODE A BYTE COUNT = M A 8 1 DATA BYTE 2 1 7 1 8 A … 1 Sr SLAVE ADDRESS Rd A 8 1 DATA BYTE 1 A … 1 A … DATA BYTE M 8 1 BYTE COUNT = N A 8 1 1 DATA BYTE 1 A … 8 1 … 8 1 1 DATA BYTE 2 A … DATA BYTE N A P 7132 F23 Figure 22. Block Write – Block Read Process Call 1 S 7 1 1 8 1 8 1 SLAVE ADDRESS Wr A COMMAND CODE A BYTE COUNT = M A 8 1 DATA BYTE 2 1 7 1 8 A … 1 Sr SLAVE ADDRESS Rd A 8 1 DATA BYTE 1 A … 1 DATA BYTE M 8 A … 1 BYTE COUNT = N A 8 1 1 DATA BYTE 1 A … 8 1 … 8 1 8 1 1 DATA BYTE 2 A … DATA BYTE N A PEC A P 7132 F24 Figure 23. Block Write – Block Read Process Call with PEC 1 7 1 1 8 1 1 S ALERT RESPONSE Rd A DEVICE ADDRESS A ADDRESS P 7132 F25 Figure 24. Alert Response Address Protocol 1 7 1 1 8 1 S ALERT RESPONSE Rd A DEVICE ADDRESS A ADDRESS 8 1 1 PEC A P 7132 F26 Figure 25. Alert Response Address Protocol with PEC Rev 0 For more information www.analog.com 37 LTC7132 PMBus COMMAND SUMMARY PMBus COMMANDS The following tables list supported PMBus commands and manufacturer specific commands. A complete description of these commands can be found in the “PMBus Power System Mgt Protocol Specification – Part II – Revision 1.2”. Users are encouraged to reference this specification. Exceptions or manufacturer specific implementations are listed below in Table 2. Floating point values listed in the “DEFAULT VALUE” column are either Linear 16-bit Signed (PMBus Section 8.3.1) or Linear_5s_11s (PMBus Section 7.1) format, whichever is appropriate for the command. All commands from 0xD0 through 0xFF not listed in this table are implicitly reserved by the manufacturer. Users should avoid blind writes within this range of commands to avoid undesired operation of the part. All commands from 0x00 through 0xCF not listed in this table are implicitly not supported by the manufacturer. Attempting to access non-supported or reserved commands may result in a CML command fault event. All output voltage settings and measurements are based on the VOUT_MODE setting of 0x14. This translates to an exponent of 2–12. If PMBus commands are received faster than they are being processed, the part may become too busy to handle new commands. In these circumstances the part follows the protocols defined in the PMBus Specification v1.2, Part II, Section 10.8.7, to communicate that it is busy. The part includes handshaking features to eliminate busy errors and simplify error handling software while ensuring robust communication and system behavior. Please refer to the subsection titled PMBus Communication and Command Processing in the Applications Information section for further details. Table 2. Summary (Note: The Data Format abbreviations are detailed at the end of this table.) COMMAND NAME CMD CODE DESCRIPTION TYPE DATA PAGED FORMAT UNITS PAGE 0x00 Provides integration with multi-page PMBus devices. R/W Byte N Reg OPERATION 0x01 Operating mode control. On/off, margin high and margin low. R/W Byte Y Reg ON_OFF_CONFIG 0x02 RUN pin and PMBus bus on/off command configuration. R/W Byte Y Reg CLEAR_FAULTS 0x03 Clear any fault bits that have been set. Send Byte N PAGE_PLUS_WRITE 0x05 Write a command directly to a specified page. W Block N PAGE_PLUS_READ 0x06 Read a command directly from a specified page. Block R/W N WRITE_PROTECT 0x10 Level of protection provided by the device against accidental changes. R/W Byte N STORE_USER_ALL 0x15 Store user operating memory to EEPROM. Send Byte RESTORE_USER_ALL 0x16 Restore user operating memory from EEPROM. CAPABILITY 0x19 Summary of PMBus optional communication protocols supported by this device. SMBALERT_MASK 0x1B Mask ALERT activity VOUT_MODE 0x20 Output voltage format and exponent (2–12). VOUT_COMMAND DEFAULT VALUE PAGE 0x00 68 Y 0x80 72 Y 0x1E 72 NA 97 69 69 0x00 69 N NA 108 Send Byte N NA 108 R Byte N 0xB0 96 Reg Y Reg see CMD 97 2–12 0x14 77 Y 1.0 0x1000 79 V Y 2.75 0x2C00 77 L16 V Y 1.05 0x10CD 78 L16 V Y 0.95 0x0F33 79 Block R/W Y Reg R Byte Y Reg 0x21 Nominal output voltage set point. R/W Word Y L16 V VOUT_MAX 0x24 Upper limit on the commanded output voltage including VOUT_MARGIN_HI. R/W Word Y L16 VOUT_MARGIN_HIGH 0x25 Margin high output voltage set point. Must be greater than VOUT_COMMAND. R/W Word Y VOUT_MARGIN_LOW 0x26 Margin low output voltage set point. Must be less than VOUT_COMMAND. R/W Word Y 38 NVM Y Rev 0 For more information www.analog.com LTC7132 PMBus COMMAND SUMMARY COMMAND NAME CMD CODE DESCRIPTION VOUT_TRANSITION_ RATE 0X27 Rate the output changes when VOUT commanded to a new value. R/W Word Y L11 V/ms Y 0.25 0xAA00 85 FREQUENCY_SWITCH 0x33 Switching frequency of the controller. R/W Word N L11 kHz Y 425k 0xFB52 76 VIN_ON 0x35 Input voltage at which the unit should start power conversion. R/W Word N L11 V Y 6.5 0xCB40 76 VIN_OFF 0x36 Input voltage at which the unit should stop power conversion. R/W Word N L11 V Y 6.0 0xCB00 77 IOUT_CAL_GAIN 0x38 The ratio of the voltage at the current sense pins to the sensed current. For devices using a fixed current sense resistor, it is the resistance value in mΩ. R/W Word Y L11 mΩ Y 0.32 0xAA8F 80 VOUT_OV_FAULT_LIMIT 0x40 Output overvoltage fault limit. R/W Word Y L16 V Y 1.1 0x119A 78 VOUT_OV_FAULT_ RESPONSE 0x41 Action to be taken by the device when an output overvoltage fault is detected. R/W Byte Y Reg Y 0xB8 87 VOUT_OV_WARN_LIMIT 0x42 Output overvoltage warning limit. R/W Word Y L16 V Y 1.075 0x1133 78 VOUT_UV_WARN_LIMIT 0x43 Output undervoltage warning limit. R/W Word Y L16 V Y 0.925 0x0ECD 79 VOUT_UV_FAULT_LIMIT 0x44 Output undervoltage fault limit. R/W Word Y L16 V Y 0.9 0x0E66 79 VOUT_UV_FAULT_ RESPONSE 0x45 Action to be taken by the device when an output undervoltage fault is detected. R/W Byte Y Reg Y 0xB8 88 IOUT_OC_FAULT_LIMIT 0x46 Output overcurrent fault limit. R/W Word Y L11 Y 45.0 0xE2D0 80 IOUT_OC_FAULT_ RESPONSE 0x47 Action to be taken by the device when an output overcurrent fault is detected. R/W Byte Y Reg Y 0x00 90 IOUT_OC_WARN_LIMIT 0x4A Output overcurrent warning limit. R/W Word Y L11 A Y 35.0 0xE230 81 OT_FAULT_LIMIT 0x4F External overtemperature fault limit. R/W Word Y L11 C Y 100.0 0xEB20 83 OT_FAULT_RESPONSE 0x50 Action to be taken by the device when an external overtemperature fault is detected, R/W Byte Y Reg Y 0xB8 92 OT_WARN_LIMIT 0x51 External overtemperature warning limit. R/W Word Y L11 C Y 85.0 0xEAA8 83 UT_FAULT_LIMIT 0x53 External undertemperature fault limit. R/W Word Y L11 C Y –40.0 0xE580 84 UT_FAULT_RESPONSE 0x54 Action to be taken by the device when an external undertemperature fault is detected. R/W Byte Y Reg Y 0xB8 92 VIN_OV_FAULT_LIMIT 0x55 Input supply overvoltage fault limit. R/W Word N L11 Y 15.5 0xD3E0 76 VIN_OV_FAULT_ RESPONSE 0x56 Action to be taken by the device when an input overvoltage fault is detected. R/W Byte Y Reg Y 0x80 87 VIN_UV_WARN_LIMIT 0x58 Input supply undervoltage warning limit. R/W Word N L11 V Y 6.3 0xCB26 76 IIN_OC_WARN_LIMIT 0x5D Input supply overcurrent warning limit. R/W Word N L11 A Y 10.0 0xD280 82 TON_DELAY 0x60 Time from RUN and/or Operation on to output rail turn-on. R/W Word Y L11 ms Y 0.0 0x8000 84 TYPE DATA PAGED FORMAT UNITS A V NVM DEFAULT VALUE PAGE Rev 0 For more information www.analog.com 39 LTC7132 PMBus COMMAND SUMMARY COMMAND NAME CMD CODE DESCRIPTION TYPE DATA PAGED FORMAT UNITS NVM DEFAULT VALUE PAGE TON_RISE 0x61 Time from when the output starts to rise until the output voltage reaches the VOUT commanded value. R/W Word Y L11 ms Y 8.0 0xD200 84 TON_MAX_FAULT_LIMIT 0x62 Maximum time from the start of TON_RISE for VOUT to cross the VOUT_UV_FAULT_LIMIT. R/W Word Y L11 ms Y 10.00 0xD280 85 TON_MAX_FAULT_ RESPONSE 0x63 Action to be taken by the device when a TON_ MAX_FAULT event is detected. R/W Byte Y Reg Y 0xB8 90 TOFF_DELAY 0x64 Time from RUN and/or Operation off to the start R/W Word of TOFF_FALL ramp. Y L11 ms Y 0.0 0x8000 85 TOFF_FALL 0x65 Time from when the output starts to fall until the output reaches zero volts. R/W Word Y L11 ms Y 8.00 0xD200 85 TOFF_MAX_WARN_LIMIT 0x66 Maximum allowed time, after TOFF_FALL completed, for the unit to decay below 12.5%. R/W Word Y L11 ms Y 150.0 0xF258 86 STATUS_BYTE 0x78 One byte summary of the unit’s fault condition. R/W Byte Y Reg NA 98 STATUS_WORD 0x79 Two byte summary of the unit’s fault condition. R/W Word Y Reg NA 99 STATUS_VOUT 0x7A Output voltage fault and warning status. R/W Byte Y Reg NA 99 STATUS_IOUT 0x7B Output current fault and warning status. R/W Byte Y Reg NA 100 STATUS_INPUT 0x7C Input supply fault and warning status. R/W Byte N Reg NA 100 STATUS_TEMPERATURE 0x7D External temperature fault and warning status for READ_TEMPERATURE_1. R/W Byte Y Reg NA 101 STATUS_CML 0x7E Communication and memory fault and warning status. R/W Byte N Reg NA 101 STATUS_MFR_SPECIFIC 0x80 Manufacturer specific fault and state information. R/W Byte Y Reg NA 102 READ_VIN 0x88 Measured input supply voltage. R Word N L11 V NA 104 READ_IIN 0x89 Measured input supply current. R Word N L11 A NA 104 READ_VOUT 0x8B Measured output voltage. R Word Y L16 V NA 104 READ_IOUT 0x8C Measured output current. R Word Y L11 A NA 105 READ_TEMPERATURE_1 0x8D External temperature sensor temperature. This is the value used for all temperature related processing, including IOUT_CAL_GAIN. R Word Y L11 C NA 105 READ_TEMPERATURE_2 0x8E Internal die junction temperature. Does not affect any other commands. R Word N L11 C NA 105 READ_FREQUENCY 0x95 Measured PWM switching frequency. R Word Y L11 Hz NA 105 READ_POUT 0x96 Measured output power R Word Y L11 W N/A 105 READ_PIN 0x97 Calculated input power R Word Y L11 W N/A 105 PMBus_REVISION 0x98 PMBus revision supported by this device. Current revision is 1.2. R Byte N Reg 0x22 96 MFR_ID 0x99 The manufacturer ID of the LTC7132 in ASCII. R String N ASC LTC 96 MFR_MODEL 0x9A Manufacturer part number in ASCII. R String N ASC MFR_VOUT_MAX 0xA5 Maximum allowed output voltage including VOUT_OV_FAULT_LIMIT. R Word Y L16 MFR_PIN_ACCURACY 0xAC Returns the accuracy of the READ_PIN command R Byte N 40 LTC7132 96 V 5.7 0x5B33 79 % 5.0% 105 Rev 0 For more information www.analog.com LTC7132 PMBus COMMAND SUMMARY COMMAND NAME CMD CODE DESCRIPTION TYPE DATA PAGED FORMAT UNITS NVM DEFAULT VALUE PAGE N Reg Y NA 95 R/W Word Y Reg Y NA 95 R/W Word N Reg Y NA 95 0xB3 An NVM word available for the user. R/W Word Y Reg Y 0x0000 95 USER_DATA_04 0xB4 An NVM word available for the user. R/W Word N Reg Y 0x0000 95 MFR_INFO 0xB6 Manufacturer specific information R/W Word N Reg NA 103 MFR_EE_UNLOCK 0xBD Contact factory. 112 MFR_EE_ERASE 0xBE Contact factory. 112 USER_DATA_00 0xB0 OEM RESERVED. Typically used for part serialization. R/W Word USER_DATA_01 0xB1 Manufacturer reserved for LTpowerPlay. USER_DATA_02 0xB2 OEM RESERVED. Typically used for part serialization USER_DATA_03 112 MFR_EE_DATA 0xBF Contact factory. MFR_CHAN_CONFIG 0xD0 Configuration bits that are channel specific. R/W Byte Y Reg Y 0x1D 70 MFR_CONFIG_ALL 0xD1 General configuration bits. R/W Byte N Reg Y 0x21 71 MFR_FAULT_PROPAGATE 0xD2 Configuration that determines which faults are propagated to the FAULT pin. R/W Word Y Reg Y 0x6993 93 MFR_PWM_COMP 0xD3 PWM loop compensation configuration R/W Byte Y Reg Y 0xAE 74 MFR_PWM_MODE 0xD4 Configuration for the PWM engine. R/W Byte Y Reg Y 0xC7 73 MFR_FAULT_RESPONSE 0xD5 Action to be taken by the device when the FAULT pin is externally asserted low. R/W Byte Y Reg Y 0xC0 95 MFR_OT_FAULT_ RESPONSE 0xD6 Action to be taken by the device when an internal overtemperature fault is detected. R Byte N Reg 0xC0 91 MFR_IOUT_PEAK 0xD7 Report the maximum measured value of READ_ IOUT since last MFR_CLEAR_PEAKS. R Word Y L11 NA 105 MFR_ADC_CONTROL 0xD8 ADC telemetry parameter selected for repeated fast ADC read back R/W Byte N Reg 0x00 106 MFR_RETRY_DELAY 0xDB Retry interval during FAULT retry mode. R/W Word Y L11 ms Y 350.0 0xFABC 86 MFR_RESTART_DELAY 0xDC Minimum time the RUN pin is held low by the LTC7132. R/W Word Y L11 ms Y 500.0 0xFBE8 86 MFR_VOUT_PEAK 0xDD Maximum measured value of READ_VOUT since last MFR_CLEAR_PEAKS. R Word Y L16 V NA 106 MFR_VIN_PEAK 0xDE Maximum measured value of READ_VIN since last MFR_CLEAR_PEAKS. R Word N L11 V NA 106 MFR_TEMPERATURE_1_ PEAK 0xDF Maximum measured value of external Temperature (READ_TEMPERATURE_1) since last MFR_CLEAR_PEAKS. R Word Y L11 C NA 106 MFR_READ_IIN_PEAK 0xE1 Maximum measured value of READ_IIN command since last MFR_CLEAR_PEAKS R Word N L11 A NA 106 NA 98 A NA 106 NA 102 0x4F 70 0x4C0X 0x4CEX 96 MFR_CLEAR_PEAKS 0xE3 Clears all peak values. Send Byte N MFR_READ_ICHIP 0xE4 Measured supply current of the LTC7132 R Word N L11 MFR_PADS 0xE5 Digital status of the I/O pads. R Word N Reg Sets the 7-bit I2C address byte. MFR_ADDRESS 0xE6 MFR_SPECIAL_ID 0xE7 Manufacturer code representing the LTC7132 and revision R/W Byte N Reg R Word N Reg A Y Rev 0 For more information www.analog.com 41 LTC7132 PMBus COMMAND SUMMARY COMMAND NAME MFR_IIN_CAL_GAIN CMD CODE DESCRIPTION TYPE DATA PAGED FORMAT UNITS NVM DEFAULT VALUE PAGE 5.0 0xCA80 82 N NA 109 Send Byte N NA 112 NA 109 NA 103 NA 108 NA 106 Y 0x10 75 0xE8 The resistance value of the input current sense element in mΩ. R/W Word N MFR_FAULT_LOG_STORE 0xEA Command a transfer of the fault log from RAM to EEPROM. Send Byte MFR_FAULT_LOG_CLEAR 0xEC Initialize the EEPROM block reserved for fault logging. L11 mΩ Y MFR_FAULT_LOG 0xEE Fault log data bytes. R Block N Reg MFR_COMMON 0xEF Manufacturer status bits that are common across multiple ADI chips. R Byte N Reg MFR_COMPARE_USER_ ALL 0xF0 Compares current command contents with NVM. Send Byte N MFR_TEMPERATURE_2_ PEAK 0xF4 Peak internal die temperature since last MFR_CLEAR_PEAKS. R Word N L11 MFR_PWM_CONFIG 0xF5 Set numerous parameters for the DC/DC controller including phasing. R/W Byte N Reg MFR_IOUT_CAL_GAIN_ TC 0xF6 Temperature coefficient of the current sensing element. R/W Word Y CF ppm/ ˚C Y 3900 0x0F3C 80 MFR_RVIN 0xF7 The resistance value of the VIN pin filter element in mΩ. R/W Word N L11 mΩ Y 1000 0x03E8 77 MFR_TEMP_1_GAIN 0xF8 Sets the slope of the external temperature sensor. R/W Word Y CF Y 1.0 0x4000 83 MFR_TEMP_1_OFFSET 0xF9 Sets the offset of the external temperature sensor with respect to –273.1°C R/W Word Y L11 Y 0.0 0x8000 83 MFR_RAIL_ADDRESS 0xFA Common address for PolyPhase outputs to adjust common parameters. R/W Byte Y Reg Y 0x80 70 R Block N CF NA 107 Send Byte N NA 72 MFR_REAL_TIME 0xFB 48-bit share-clock counter value. MFR_RESET 0xFD Commanded reset without requiring a power down. Note 1: Commands indicated with Y in the NVM column indicate that these commands are stored and restored using the STORE_USER_ALL and RESTORE_USER_ALL commands, respectively. Note 2: Commands with a default value of NA indicate “not applicable”. Commands with a default value of FS indicate “factory set on a per part basis”. Note 3: The LTC7132 contains additional commands not listed in this table. Reading these commands is harmless to the operation of the IC; however, the contents and meaning of these commands can change without notice. 42 Y C C Note 4: Some of the unpublished commands are read-only and will generate a CML bit 6 fault if written. Note 5: Writing to commands not published in this table is not permitted. Note 6: The user should not assume compatibility of commands between different parts based upon command names. Always refer to the manufacturer’s data sheet for each part for a complete definition of a command’s function. ADI strives to keep command functionality compatible between all ADI devices. Differences may occur to address specific product requirements. Rev 0 For more information www.analog.com LTC7132 PMBus COMMAND SUMMARY *DATA FORMAT L11 Linear_5s_11s PMBus data field b[15:0] Value = Y • 2N where N = b[15:11] is a 5-bit two’s complement integer and Y = b[10:0] is an 11-bit two’s complement integer Example: For b[15:0] = 0x9807 = ‘b10011_000_0000_0111 Value = 7 • 2–13 = 854 • 10–6 From “PMBus Spec Part II: Paragraph 7.1” L16 Linear_16u PMBus data field b[15:0] Value = Y • 2N where Y = b[15:0] is an unsigned integer and N = Vout_mode_parameter is a 5-bit two’s complement exponent that is hardwired to –12 decimal Example: For b[15:0] = 0x9800 = ‘b1001_1000_0000_0000 Value = 19456 • 2–12 = 4.75 From “PMBus Spec Part II: Paragraph 8.2” Reg Register PMBus data field b[15:0] or b[7:0]. Bit field meaning is defined in detailed PMBus Command Description. I16 Integer Word PMBus data field b[15:0] Value = Y where Y = b[15:0] is a 16 bit unsigned integer Example: For b[15:0] = 0x9807 = ‘b1001_1000_0000_0111 Value = 38919 (decimal) CF ASC Custom Format Value is defined in detailed PMBus Command Description. This is often an unsigned or two’s complement integer scaled by an MFR specific constant. ASCII Format A variable length string of text characters conforming to ISO/IEC 8859-1 standard. Rev 0 For more information www.analog.com 43 LTC7132 APPLICATIONS INFORMATION CURRENT LIMIT PROGRAMMING The cycle-by-cycle current limit threshold voltage, VILIMIT, across the ISENSE+/ISENSE– pins is proportional to VITH. The VITH limit can be programmed from 1.45 to 2.2V using the PMBUS command IOUT_OC_FAULT_ LIMIT. See Figure 26. The LTC7132 has four ranges of current limit programming. Properly setting the value of MFR_PWM_MODE[2] and MFR_PWM_MODE[7], and IOUT_OC_FAULT_LIMIT, see the section of the PMBus commands, the device can regulate output voltage with the peak current under the value of IOUT_OC_FAULT_ LIMIT in normal operation. In case of output current 44 exceeding that current limit, an OC fault will be issued. Each range in Figure 26 affects the loop gain, and subsequently effects the loop stability, so setting range of current limiting is a part of loop design. 100 80 60 VILIMIT (mV) The Typical Application on the back page is a common LTC7132 application circuit. The LTC7132 is mainly designed for low DCR application via PMBus command MFR_PWM_MODE[2] = 1 applicable when 0 ≤ VOUT ≤ 3.5V, but it can be also configured to be regular DCR or regular resistor sensing by setting MFR_PWM_MODE[2] = 0 for 0≤ VOUT ≤ 5.5V. The choice among them is largely a design trade-off between cost, power consumption and accuracy. DCR sensing is becoming popular because it saves expensive current sensing resistors and is more power efficient, especially in high current applications. Low DCR provides the most power efficient solution, and best signal-to-noise ratio of the input sensing voltage. The accuracy of the current reading and current limit are typically limited by the accuracy of the DCR resistor (accounted for in the IOUT_CAL_GAIN parameter of the LTC7132). Thus current sensing resistors provide the most accurate current sensing and limiting for the application. Other external component selection is driven by the load requirement, and begins with the selection of RSENSE (if RSENSE is used) and inductor value. Then the input and output capacitors are selected. To have a stable loop performance and reliability, the loop compensation parameters such as GM of error amplifier programmed by MFR_PWM_ COMP[7:5] and RTH by MFR_PWM_ COMP[4:0] together with current limit range, set by bit[7] of MFR_PWM_MODE and voltage range set by bit[1] of MFR_ PWM_MODE have to be properly selected. All other programmable parameters do not affect the loop gain, allowing parameters to be modified without impacting the transient response to load changes. MFR_PWM_MODE[2]=0 MFR_PWM_MODE[7]=1 MFR_PWM_MODE[2]=0 MFR_PWM_MODE[7]=0 RC = L/DCR 40 20 0 MFR_PWM_MODE[2]=1 MFR_PWM_MODE[7]=1 MFR_PWM_MODE[2]=1 MFR_PWM_MODE[7]=0 RC = L/(5 • DCR) –20 –40 3994 F27 0 0.5 1 1.5 VITH (V) 2 2.5 3 Figure 26. VITH vs VILIMIT The LTC7132 will account for the DCR of the inductor if the device is configured for DCR sensing and automatically update the current limit as the inductor temperature changes. The temperature coefficient of the DCR is stored in the MFR_IOUT_CAL_GAIN_TC register. The setting MFR_PWM_MODE[2]  =  1, MFR_PWM_MODE[7] = 0, allows for the use of very low DCR inductors or sense resistors, the peak output current is up to 16.5mV/DCR, the application LTC7132 is mainly designed for. Keep in mind this operation is based on a cycle-by-cycle basis and is only a function of the peak inductor current. The average inductor current is monitored by the ADC converter and can provide a warning if too much average output current is detected. The overcurrent fault is detected when the ITH voltage hits the maximum value. The digital processor within the LTC7132 provides the ability to either ignore the fault, shut down and latch off or shut down and retry indefinitely (hiccup). Refer to the overcurrent portion of the Operation section for more detail. ISENSE0± AND ISENSE1± PINS The ISENSE+ and ISENSE– pins are the inputs to the current comparator and the A/D. The common mode input voltage range of the current comparators is 0V to 5.5V. Both the SENSE pins are high impedance inputs with small input currents typically less than 1µA. The high impedance Rev 0 For more information www.analog.com LTC7132 APPLICATIONS INFORMATION inputs to the current comparators enable accurate DCR sensing. Do not float these pins during normal operation. The RC sense filter time constant must be set by the following equations: Filter components connected to the ISENSE± traces should be placed close to the IC. The positive and negative traces should be routed differentially and Kelvin connected to the current sense element; see Figure 27. A non-Kelvin connection or improper placement can add parasitic inductance and capacitance to the current sense element, degrading the signal at the sense terminals and making the programmed current limit perform poorly. In a PolyPhase system, poor placement of the sensing element will result in sub-optimal current sharing between power stages. If DCR sensing is used (Figure 28a), sense resistor R1 should be placed close to the inductor to prevent noise from coupling into sensitive small-signal nodes. The capacitor C1 should be placed close to the IC pins. Any impedance difference between the ISENSE+ and ISENSE– signal paths can result in loss of accuracy in the current reading of the ADC. The current reading accuracy can be improved by matching the impedance of the two signal paths. To accomplish this add a series resistor R3 between VOUT and ISENSE– equal to R1. A capacitor of 1µF or greater should be placed in parallel with this resistor. RC = L/(5 • DCR) at MFR_PWM_MODE[2] = 1 for low DCR TO SENSE FILTER, NEXT TO THE CONTROLLER COUT INDUCTOR OR RSENSE 7132 F28 Figure 27. Sense Lines Placement with Inductor DCR Inductor DCR Sensing The DCR is the DC winding resistance of the inductor's copper, which is often less than 1mΩ for high current inductors. In high current and low output voltage applications, a conduction loss of a high DCR or a sense resistor will cause a significant reduction in power efficiency. For a specific output requirement, choose the inductor with the DCR that satisfies the maximum desirable sense voltage, and uses the relationship of the sense pin filters to output inductor characteristics as depicted in the following: DCR = VSENSE(MAX) ΔI IMAX + L 2 RC = L/DCR at MFR_PWM_MODE[2] = 0 for normal DCR where: VSENSE(MAX): Maximum sense voltage for a given ITH voltage IMAX: Maximum load current ∆IL: Inductor ripple current DCR: Inductor resistance RC: Filter time constant During normal DCR sensing, the voltage ripple across C1 is equal to the voltage ripple across the inductor DCR. During low DCR sensing, the voltage ripple across C1 is equal to the 5x the voltage ripple across the inductor DCR. To ensure the load current will be delivered over the full operating temperature range, the temperature coefficient of DCR resistance, approximately 3900ppm/˚C, should be taken into consideration. Typically, C is selected in the range of 0.047µF to 0.47µF. This forces R1 to around 2kΩ at MFR_PWM_MODE[2]=0, 400Ω at MFR_PWM_MODE[2]=1 reducing error that might have been caused by the ISENSE pins’ ±1µA current (R3 and C2 are for reducing sensing error caused by input current through R1). There will be some power loss in R1 that relates to the duty cycle, and will be the most in continuous mode at the maximum input voltage: PLOSS (R1) = ( VIN(MAX) – VOUT ) • VOUT R1 Ensure that R1 has a power rating higher than this value. However, DCR sensing eliminates the conduction loss of sense resistor; it will provide better efficiency at heavy loads. To maintain a good signal-to-noise ratio for low current sense signals, it is best to enable the LOW DCR sensing network (MFR_PWM_MODE[2] = 1, RC = L/(5 • DCR). Rev 0 For more information www.analog.com 45 LTC7132 APPLICATIONS INFORMATION For a DCR sensing application, the peak-to-peak ripple voltage will be determined by the equation: ΔVSENSE = VOUT VIN – VOUT • VIN RC • fOSC LOW VALUE RESISTOR CURRENT SENSING Low DCR sensing can be used at ∆VSENSE signal as low as 2mV. INDUCTOR VALUE CALCULATION Given the desired input and output voltages, the inductor value and operating frequency, fOSC, directly determine the inductor peak-to-peak ripple current: ∆IL = VOUT ( VIN – VOUT ) VIN • fOSC •L Lower ripple current reduces core losses in the inductor, ESR losses in the output capacitors, and output voltage ripple. Thus, at a given frequency, the highest efficiency operation is obtained with a small ripple current, which requires a large inductor. A reasonable starting point is to choose a ripple current that is about 40% of IOUT(MAX). Note that the largest ripple current occurs at the highest input voltage. To guarantee that the ripple current does not exceed a specified maximum, the inductor should be chosen according to: V (V – V ) L ≥ OUT IN OUT VIN • fOSC •IRIPPLE INDUCTOR CORE SELECTION Once the inductor value is determined, the type of inductor must be selected. Core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance. As the inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses increase. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core materials saturate hard, which means that the inductance collapses abruptly when the peak design current is 46 exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! A typical sensing circuit using a discrete resistor is shown in Figure 28b. RSENSE is chosen based on the required output current. The current comparator has a maximum threshold VSENSE(MAX) determined by the ILIMIT setting. The input common mode range of the current comparator is 0V to 5.5V. The current comparator threshold sets the peak of the inductor current, yielding a maximum average output current IMAX equal to the peak value less half the peakto-peak ripple current ∆IL. To calculate the sense resistor value, use the equation: RSENSE = VSENSE(MAX) ΔI IMAX + L 2 Due to possible PCB noise in the current sensing loop, the AC current sensing ripple of ∆VSENSE = ∆IL • RSENSE also needs to be checked in the design to get a good signal-tonoise ratio. In general, for a reasonably good PCB layout, a 15mV minimum ∆VSENSE voltage is recommended as a conservative number to start with for RSENSE applications. For previous generation current mode controllers, the maximum sense voltage was high enough (e.g., 75mV for the LTC1628/LTC3728 family) that the voltage drop across the parasitic inductance of the sense resistor represented a relatively small error. In the newer and higher current density solutions, the value of the sense resistor can be less than 1mΩ and the peak sense voltage can be less than 20mV. Also, inductor ripple currents greater than 50% with operation up to 750kHz are becoming more common. Under these conditions, the voltage drop across the sense resistor’s parasitic inductance is no longer negligible. A typical sensing circuit using a discrete resistor is shown in Figure 28b. In previous generations of controllers, a small RC filter placed near the IC was commonly used to reduce the effects of the capacitive and inductive noise coupled in the sense traces on the PCB. A typical filter consists of two series 100Ω resistors connected to a parallel 1000pF capacitor, resulting in a time constant of 200ns. Rev 0 For more information www.analog.com LTC7132 APPLICATIONS INFORMATION INTVCC BOOST TG LTC7132 INDUCTOR L SW BG ISENSE+ ISENSE– DCR VOUT C2 >1µF R1 C1* R3 7132 F29a OPTIONAL Figure 28a. Inductor DCR Current Sense Circuit If the RC time constant is chosen to be close to the parasitic inductance divided by the sense resistor (L/R), the resultant waveform looks resistive, as shown in Figure 29b. For applications using low maximum sense voltages, check the sense resistor manufacturer’s data sheet for information about parasitic inductance. In the absence of data, measure the voltage drop directly across the sense resistor to extract the magnitude of the ESL step and use Equation 1 to determine the ESL. However, do not overfilter the signal. Keep the RC time constant less than or equal to the inductor time constant to maintain a sufficient ripple voltage on VRSENSE for optimal operation of the current loop controller. INTVCC SENSE RESISTOR PLUS PARASITIC INDUCTANCE BOOST LTC7132 L SW GND ISENSE+ ISENSE– RF RS ESL VOUT VSENSE 20mV/DIV VESL(STEP) CF • 2RF ≤ ESL/RS POLE-ZERO CANCELLATION CF 500ns/DIV 7132 F29b RF 7132 F30a Figure 29a. Voltage Measured Directly Across RSENSE FILTER COMPONENTS PLACED NEAR SENSE PINS Figure 28b. Resistor Current Sense Circuit This same RC filter, with minor modifications, can be used to extract the resistive component of the current sense signal in the presence of parasitic inductance. For example, Figure 29a illustrates the voltage waveform across a 2mΩ resistor with a PCB footprint of 2010. The waveform is the superposition of a purely resistive component and a purely inductive component. It was measured using two scope probes and waveform math to obtain a differential measurement. Based on additional measurements of the inductor ripple current and the on-time, tON, and off-time, tOFF, of the top switch, the value of the parasitic inductance was determined to be 0.5nH using the equation: V (STEP ) tON • tOFF ESL = ESL • ΔI tON + tOFF L (1) VSENSE 20mV/DIV 500ns/DIV 7132 F30b Figure 29b. Voltage Measured After the RSENSE Filter SLOPE COMPENSATION AND INDUCTOR PEAK CURRENT Slope compensation provides stability in constant-frequency current-mode architectures by preventing subharmonic oscillations at high duty cycles. This is accomplished internally by adding a compensation ramp to the inductor current signal. The LTC7132 uses a patented Rev 0 For more information www.analog.com 47 LTC7132 APPLICATIONS INFORMATION current limit technique that counteracts the compensating ramp. This allows the maximum inductor peak current to remain unaffected throughout all duty cycles. VARIABLE DELAY TIME, SOFT-START AND OUTPUT VOLTAGE RAMPING The LTC7132 must enter the run state prior to soft-start. The RUNn pin is released after the part initializes and VIN is greater than the VIN_ON threshold. If multiple LTC7132s are used in an application, they should be configured to share the same RUNn pins. They all hold their respective RUNn pins low until all devices initialize and VIN exceeds the VIN_ON threshold for all devices. The SHARE_CLK pin assures all the devices connected to the signal use the same time base. After the RUNn pin releases, the controller waits for the user-specified turn-on delay (TON_DELAY) prior to initiating an output voltage ramp. Multiple LTC7132s and other ADI parts can be configured to start with variable delay times. To work correctly, all devices use the same timing clock (SHARE_CLK) and all devices must share the RUNn pin. This allows the relative delay of all parts to be synchronized. The actual variation in the delay will be dependent on the highest clock rate of the devices connected to the SHARE_CLK pin (all Analog Devices ICs are configured to allow the fastest SHARE_CLK signal to control the timing of all devices). The SHARE_CLK signal can be ±10% in frequency, thus the actual time delays will have proportional variance. Soft-start is performed by actively regulating the load voltage while digitally ramping the target voltage from 0.0V to the commanded voltage set point. The rise time of the voltage ramp can be programmed using the TON_ RISE command to minimize inrush currents associated with the start-up voltage ramp. The soft-start feature is disabled by setting TON_RISE to any value less than 0.250ms. The LTC7132 will perform the necessary math internally to assure the voltage ramp is controlled to the desired slope. However, the voltage slope cannot be any faster than the fundamental limits of the power stage. The shorter TON_RISE time is set, the larger the discrete steps in the TON_RISE ramp will appear. The number of steps in the ramp is equal to TON_RISE/0.1ms. 48 The LTC7132 PWM will always use discontinuous mode during the TON_RISE operation. In discontinuous mode, the bottom gate is turned off as soon as reverse current is detected in the inductor. This will allow the regulator to start up into a pre-biased load. There is no traditional tracking feature in the LTC7132. However, two outputs can be given the same TON_RISE and TON_DELAY times to effectively ramp up at the same time. If the RUN pin is released at the same time and both LTC7132s use the same time base, the outputs will track very closely. If the circuit is in a PolyPhase configuration, all timing parameters must be the same. The method of start-up sequencing described above is time based. For concatenated events it is possible to control the RUNn pins based on the PGOODn pin of a different controller. There is 60µs filtering to the PGOODn inside the device. If unwanted transitions still occur on PGOODn, place a capacitor to ground on the PGOODn pin to filter the waveform. The RC time-constant of the filter should be set sufficiently fast to assure no appreciable delay is incurred. A value of 300μs to 500μs will provide some additional filtering without significantly delaying the trigger event. DIGITAL SERVO MODE For maximum accuracy in the regulated output voltage, enable the digital servo loop by asserting bit 6 of the MFR_PWM_MODE command. In digital servo mode, the LTC7132 will adjust the regulated output voltage based on the ADC voltage reading. Every 90ms the digital servo loop will step the LSB of the DAC (nominally 1.375mV or 0.688mV depending on the voltage range bit) until the output is at the correct ADC reading. At power-up this mode engages after TON_MAX_FAULT_LIMIT unless the limit is set to 0 (infinite). If the TON_MAX_FAULT_LIMIT is set to 0 (infinite), the servo begins after TON_RISE is complete and VOUT has exceeded the VOUT_UV_FAULT_LIMIT. This same point in time is when the output changes from discontinuous to the programmed mode as indicated in MFR_PWM_MODE bit 0. Refer to Figure 30 for details on the VOUT waveform under time-based sequencing. If the TON_MAX_FAULT_LIMIT is set to a value greater than 0 Rev 0 For more information www.analog.com LTC7132 APPLICATIONS INFORMATION and the TON_MAX_FAULT_RESPONSE is set to ignore 0x00, the servo begins: 1. After the TON_RISE sequence is complete 2. After the TON_MAX_FAULT_LIMIT time is reached; and 3. After the VOUT_UV_FAULT_LIMIT has been exceed or the IOUT_OC_FAULT_LIMIT is no longer active. If the TON_MAX_FAULT_LIMIT is set to a value greater than 0 and the TON_MAX_FAULT_RESPONSE is not set to ignore 0X00, the servo begins: 1. After the TON_RISE sequence is complete; 2. After the TON_MAX_FAULT_LIMIT time has expired and both VOUT_UV_FAULT and IOUT_OC_FAULT are not present. The maximum rise time is limited to 1.3 seconds. In a PolyPhase configuration it is recommended only one of the control loops have the digital servo mode enabled. This will assure the various loops do not work against each other due to slight differences in the reference circuits. a controlled ramp. The output will decay as a function of the load. The output voltage will operate as shown in Figure  31 so long as the part is in forced continuous mode and the TOFF_FALL time is sufficiently slow that the power stage can achieve the desired slope. The TOFF_FALL time can only be met if the power stage and controller can sink sufficient current to assure the output is at zero volts by the end of the fall time interval. If the TOFF_FALL time is set shorter than the time required to discharge the load capacitance, the output will not reach the desired zero volt state. At the end of TOFF_FALL, the controller will cease to sink current and VOUT will decay at the natural rate determined by the load impedance. If the controller is in discontinuous mode, the controller will not pull negative current and the output will be pulled low by the load, not the power stage. The maximum fall time is limited to 1.3 seconds. The shorter TOFF_FALL time is set, the larger the discrete steps in the TOFF_FALL ramp will appear. The number of steps in the ramp is equal to TOFF_FALL/0.1ms. DIGITAL SERVO MODE ENABLED FINAL OUTPUT VOLTAGE REACHED TON_MAX_FAULT_LIMIT VOUT DAC VOLTAGE ERROR (NOT TO SCALE) VOUT TIME DELAY OF 200-400ms TOFF_DELAY TON_DELAY TON_RISE TIME 7132 F31 Figure 30. Timing Controlled VOUT Rise SOFT OFF (SEQUENCED OFF) In addition to a controlled start-up, the LTC7132 also supports controlled turn-off. The TOFF_DELAY and TOFF_ FALL functions are shown in Figure 31. TOFF_FALL is processed when the RUN pin goes low or if the part is commanded off. If the part faults off or FAULTn is pulled low externally and the part is programmed to respond to this, the output will three-state rather than exhibiting TOFF_FALL TIME 7132 F32 Figure 31. TOFF_DELAY and TOFF_FALL INTVCC/EXTVCC POWER The internal MOSFET drivers and most other internal circuitry are derived from the INTVCC pin. When the EXTVCC pin is shorted to GND or tied to a voltage less than 4.7V, or SVIN is lower than 7V, an internal 5.5V linear regulator supplies INTVCC power from VIN. If EXTVCC is taken above 4.7V and SVIN is higher than 7V, the internal 5.5V regulator is turned off and an internal switch is turned on connecting EXTVCC to INTVCC. EXTVCC reduces power dissipation from the internal low dropout 5.5V regulator, thus improves the overall efficiency and thermal performance. Rev 0 For more information www.analog.com 49 LTC7132 APPLICATIONS INFORMATION EXTVCC can be applied before VIN. The regulator can supply a peak current of 100mA. Both INTVCC and EXTVCC need to be bypassed to ground with a minimum of 1μF ceramic capacitor or low ESR electrolytic capacitor. No matter what type of bulk capacitor is used, an additional 0.1μF ceramic capacitor placed directly adjacent to the INTVCC and PGND pins is highly recommended. Good bypassing is needed to supply the high transient currents required by the MOSFET gate drivers. Do not tie INTVCC on the LTC7132 to an external supply because INTVCC will attempt to pull the external supply high and hit current limit, significantly increasing the die temperature. For applications where VIN is less than 6V, tie the SVIN and INTVCC pins together to the supply voltage through a 1Ω or 2.2Ω resistor as shown in Figure 32. To minimize the voltage drop caused by the gate charge current a low ESR capacitor must be connected to the SVIN/INTVCC pins. This configuration will override the INTVCC linear regulator and will prevent INTVCC from dropping too low. The UVLO on INTVCC is set to approximately 4V. PVIN0/1 SVIN + VIN 5V RVIN 1Ω CINTVCC 4.7µF Figure 32. Setup for a 5V Input LTC7132 SW INTVCC PGND + 1Ω TO 5Ω DB VIN CIN CB 0.1µF CINTVCC 4.7µF 7132 F34 Figure 33. Boost Circuit to Minimize PWM Jitter 50 PWM jitter has been observed in some designs operating at higher VIN/VOUT ratios. This jitter does not substantially affect the circuit accuracy. Referring to Figure 33, PWM jitter can be removed by inserting a series resistor with a value of 1Ω to 5Ω between the cathode of the diode and the BOOSTn pin. A resistor case size of 0603 or larger is recommended to reduce ESL and achieve the best results. UNDERVOLTAGE LOCKOUT 7132 F33 PVIN0/1 SVIN BOOST External bootstrap capacitors, CB, connected to the BOOSTn pin supplies the gate drive voltages for the internal topside MOSFETs. Capacitor CB in the Block Diagram is charged through external diode DB from INTVCC when the SWn pin is low. When one of the topside MOSFETs is to be turned on, the driver places the CB voltage across the gate source of the desired MOSFET. This enhances the MOSFET and turns on the topside switch. The switch node voltage, SWn, rises to VIN and the BOOSTn pin follows. With the internal topside MOSFET on, the boost voltage is above the input supply: VBOOST = VIN + VINTVCC. The value of the boost capacitor, CB, needs to be 100 times that of the total input capacitance of the topside MOSFET(s). The reverse breakdown of the external Schottky diode must be greater than VIN(MAX). CIN LTC7132 INTVCC PGND TOPSIDE MOSFET DRIVER SUPPLY (CB, DB) The LTC7132 is initialized by an internal threshold-based UVLO where VIN must be approximately 4V and INTVCC, VDD33, and VDD25 must be within approximately 20% of their regulated values. In addition, VDD33 must be within approximately 7% of the targeted value before the RUN pin is released. After the part has initialized, an additional comparator monitors VIN. The VIN_ON threshold must be exceeded before the power sequencing can begin. When VIN drops below the VIN_OFF threshold, the SHARE_CLK pin will be pulled low and VIN must increase above the VIN_ON threshold before the controller will restart. The normal start-up sequence will be allowed after the VIN_ ON threshold is crossed. If FAULTB is held low when VIN is applied, ALERT will be asserted low even if the part is programmed to not assert ALERT when FAULTB is held low. If I2C communication occurs before the LTC7132 is out of reset and only a portion of the command is seen by Rev 0 For more information www.analog.com LTC7132 APPLICATIONS INFORMATION the part, this can be interpreted as a CML fault. If a CML fault is detected, ALERT is asserted low. It is possible to program the contents of the NVM in the application if the VDD33 supply is externally driven directly to VDD33 or through EXTVCC. This will activate the digital portion of the LTC7132 without engaging the high voltage sections. PMBus communications are valid in this supply configuration. If VIN has not been applied to the LTC7132, bit 3 (NVM Not Initialized) in MFR_COMMON will be asserted low. If this condition is detected, the part will only respond to addresses 5A and 5B. To initialize the part issue the following set of commands: global address 0x5B command 0xBD data 0x2B followed by global address 5B command 0xBD and data 0xC4. The part will now respond to the correct address. Configure the part as desired then issue a STORE_USER_ALL. When VIN is applied a MFR_RESET command must be issued to allow the PWM to be enabled and valid ADC conversions to be read. CIN AND COUT SELECTION In continuous mode, the source current of the internal top MOSFET is a square wave of duty cycle (VOUT)/(VIN). To prevent large voltage transients, a low ESR capacitor sized for the maximum RMS current of one channel must be used. The maximum RMS capacitor current is given by: CIN Required IRMS ≈ 1/2 IMAX ⎡ ⎣( VOUT ) ( VIN – VOUT )⎤⎦ VIN This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturers’ ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may be paralleled to meet size or height requirements in the design. Due to the high operating frequency of the LTC7132, ceramic capacitors can also be used for CIN. Always consult the manufacturer if there is any question. The benefit of using a LTC7132 in 2-phase operation can be calculated by using the equation above for the higher power monolithic and then calculating the loss that would have resulted if both channels switched on at the same time. The total RMS power loss is lower when both channels are operating due to the reduced overlap of current pulses required through the input capacitor’s ESR. This is why the input capacitor’s requirement calculated above for the worst-case controller is adequate for the dual controller design. Also, the input protection fuse resistance, battery resistance, and PC board trace resistance losses are also reduced due to the reduced peak currents in a 2-phase system. The overall benefit of a multiphase design will only be fully realized when the source impedance of the power supply/battery is included in the efficiency testing. A small (0.1μF to 1μF) bypass capacitor between the chip SVIN pin and ground, placed close to the LTC7132, is also suggested. A 2.2Ω to 10Ω resistor placed between CIN (C1) and the VIN pin provides further isolation between the two LTC7132s. The selection of COUT is driven by the effective series resistance (ESR). Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering. The output ripple (∆VOUT) is approximated by: ⎛ ⎞ 1 ΔVOUT ≈IRIPPLE ⎜ESR+ ⎟ 8 • f •COUT ⎠ ⎝ where f is the operating frequency, COUT is the output capacitance and IRIPPLE is the ripple current in the inductor. The output ripple is highest at maximum input voltage since IRIPPLE increases with input voltage. FAULT INDICATION The LTC7132 FAULT pins are configurable to indicate a variety of faults including OV, UV, OC, OT, timing faults, and peak over current faults. In addition, the FAULT pins can be pulled low by external sources indicating a fault in Rev 0 For more information www.analog.com 51 LTC7132 APPLICATIONS INFORMATION some other portion of the system. The fault response is configurable and allows the following options: Ignore n Shut Down Immediately—Latch Off n Shut Down Immediately—Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY n Refer to the PMBus section of the data sheet and the PMBus specification for more details. The OV response is automatic. If an OV condition is detected, SWn goes low. Fault logging is available on the LTC7132. The fault logging is configurable to automatically store data when a fault occurs that causes the unit to fault off. The header portion of the fault logging table contains peak values. It is possible to read these values at any time. This data will be useful while troubleshooting the fault. If the LTC7132 internal temperature is in excess of 85°C, writes into the NVM (other than fault logging) are not recommended. The data will still be held in RAM, unless the 3.3V supply UVLO threshold is reached. If the die temperature exceeds 130°C all NVM communication is disabled until the die temperature drops below 120°C. OPEN-DRAIN PINS The LTC7132 has the following open-drain pins: All the above pins have on-chip pull-down transistors that can sink 3mA at 0.4V. The low threshold on the pins is 0.8V; thus, there is plenty of margin on the digital signals with 3mA of current. For 3.3V pins, 3mA of current is a 1.1k resistor. Unless there are transient speed issues associated with the RC time constant of the resistor pullup and parasitic capacitance to ground, a 10k resistor or larger is generally recommended. For high speed signals such as the SDA, SCL and SYNC, a lower value resistor may be required. The RC time constant should be set to 1/3 to 1/5 the required rise time to avoid timing issues. For a 100pF load and a 400kHz PMBus communication rate, the rise time must be less than 300ns. The resistor pull-up on the SDA and SCL pins with the time constant set to 1/3 the rise time is: RPULLUP = tRISE =1k 3 •100pF The closest 1% resistor value is 1k. Be careful to minimize parasitic capacitance on the SDA and SCL pins to avoid communication problems. To estimate the loading capacitance, monitor the signal in question and measure how long it takes for the desired signal to reach approximately 63% of the output value. This is a one time constant. The SYNC pin has an on-chip pull-down transistor with the output held low for nominally 500ns. If the internal oscillator is set for 500kHz and the load is 100pF and a 3x time constant is required, the resistor calculation is as follows: 3.3V Pins RPULLUP = 2µs – 500ns = 5k 3 •100pF 1. FAULT 2. SYNC The closest 1% resistor is 4.99k. 3. SHARE_CLK If timing errors are occurring or if the SYNC frequency is not as fast as desired, monitor the waveform and determine if the RC time constant is too long for the application. If possible reduce the parasitic capacitance. If not reduce the pull-up resistor sufficiently to assure proper timing. The SHARE_CLK pull-up resistor has a similar equation with a period of 10µs and a pull-down time of 1μs. The RC time constant should be approximately 3μs or faster. 4. PGOODn 5V Pins (5V pins operate correctly when pulled to 3.3V.) 1. RUNn 2. ALERT 3. SCL 4. SDA 52 Rev 0 For more information www.analog.com LTC7132 APPLICATIONS INFORMATION PHASE-LOCKED LOOP AND FREQUENCY SYNCHRONIZATION The LTC7132 has a phase-locked loop (PLL) comprised of an internal voltage-controlled oscillator (VCO) and a phase detector. The PLL is locked to the falling edge of the SYNC pin. The phase relationship between the PWM controller and the falling edge of SYNC is controlled by the lower 3 bits of the MFR_PWM_ CONFIG command. For PolyPhase applications, it is recommended that all the phases be spaced evenly. Thus for a 2-phase system the signals should be 180° out of phase and a 4-phase system should be spaced 90°. The phase detector is an edge-sensitive digital type that provides a known phase shift between the external and internal oscillators. This type of phase detector does not exhibit false lock to harmonics of the external clock. The output of the phase detector is a pair of complementary current sources that charge or discharge the internal filter network. The PLL lock range is guaranteed between 200kHz and 1MHz. Nominal parts will have a range beyond this; however, operation to a wider frequency range is not guaranteed. The PLL has a lock detection circuit. If the PLL should lose lock during operation, bit 4 of the STATUS_MFR_ SPECIFIC command is asserted and the ALERT pin is pulled low. The fault can be cleared by writing a 1 to the bit. If the user does not wish to see the ALERT pin assert if a PLL_FAULT occurs, the SMBALERT_MASK command can be used to prevent the alert. If the SYNC signal is not clocking in the application, the nominal programmed frequency will control the PWM circuitry. However, if multiple parts share the SYNC pins and the signal is not clocking, the parts will not be synchronized and excess voltage ripple on the output may be present. Bit 10 of MFR_PADS will be asserted low if this condition exists. If the PWM signal appears to be running at too high a frequency, monitor the SYNC pin. Extra transitions on the falling edge will result in the PLL trying to lock on to noise versus the intended signal. Review routing of digital control signals and minimize crosstalk to the SYNC signal to avoid this problem. Multiple LTC7132s are required to share one SYNC pin in PolyPhase configurations. For other configurations, connecting the SYNC pins to form a single SYNC signal is optional. If the SYNC pin is shared between LTC7132s, only one LTC7132 can be programmed with a frequency output. All the other LTC7132s should be programmed to disable the SYNC output. However their frequency should be programmed to the nominal desired value. MINIMUM ON-TIME CONSIDERATIONS Minimum on-time, tON(MIN), is the smallest time duration that the LTC7132 is capable of turning on the top MOSFET. It is determined by internal timing delays and the gate charge required to turn on the top MOSFET. Low duty cycle applications may approach this minimum limit and care should be taken to ensure that: tON(MIN) < VOUT VIN • fOSC If the duty cycle falls below what can be accommodated by the minimum on-time, the part will begin to skip cycles. The output voltage will continue to be regulated, but the ripple voltage and current will increase. The minimum on-time for the LTC7132 is approximately 90ns. Reasonably good PCB layout, minimum 30% inductor current ripple and at least 2mV for LOW DCR structure or 10mV to 15mV for regular DCR ripple on the current sense signal are required to avoid increasing the minimum on-time. The minimum on-time can be affected by PCB switching noise in the voltage and current loop. As the peak current sense voltage decreases, the minimum on-time gradually increases to 130ns. This is of particular concern in forced continuous applications with low ripple current at light loads. If the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. Rev 0 For more information www.analog.com 53 LTC7132 APPLICATIONS INFORMATION EXTERNAL TEMPERATURE SENSE The LTC7132 is capable of measuring the power stage temperature of each channel. Multiple methods using silicon junction type remote sensors are supported. The voltage produced by the remote sense circuit is digitized by the internal ADC, and the computed temperature value is returned by the paged READ_TEMPERATURE_1 telemetry command. The most accurate external temperature measurement can be made using a diode-connected PNP transistor such as the MMBT3906 as shown in Figure 34 with bit 5 of MFR_PWM_MODE should be set to 0 (∆VBE method) when using this sensor configuration. The transistor should be placed in contact with or immediately adjacent to the power stage inductor. Its emitter should be connected to the TSNSn pin while the base and collector terminals of the PNP transistor should be returned to the LTC7132 GND paddle using a Kevin connection. For best noise immunity, the connections should be routed differentially and a 10nF capacitor should be placed in parallel with the diode-connected PNP. Parasitic PCB trace inductance between the capacitor and transistor should be minimized. Avoid placing PCB vias between the transistor and capacitor. TSNS LTC7132 MMBT3906 GND 7132 F35 Figure 34. External ∆VBE Temperature Sense 495µA TSNS LTC7132 GND GND 1nF 1.35V AT 25°C 7132 F36 Figure 35. 2D+R Temperature Sense The LTC7132 also supports direct junction voltage measurements when bit 5 of MFR_PWM_MODE_LTC7132 is set to 1. The factory defaults support a resistor trimmed 54 For either method, the slope of the external temperature sensor can be modified with the coefficient stored in MFR_TEMP_1_GAIN. With the ∆VBE approach, typical PNPs require temperature slope adjustments slightly less than 1. The MMBT3906 has a recommended value in this command of approximately MFR_TEMP_1_GAIN = 0.991 based on the ideality factor of 1.01. Simply invert the ideality factor to calculate the MFR_TEMP_1_GAIN. Different manufacturers and different lots may have different ideality factors. Consult with the manufacturer to set this value. Bench characterization over temperature is recommended when adjusting MFR_TEMP_1_GAIN for the direct p-n junction measurement method. The offset of the external temperature sense can be adjusted by MFR_TEMP_1_OFFSET. If an external temperature sense element is not used, the TSNSn pin must be shorted to GND. The UT_FAULT_LIMIT must be set to –275°C, and the UT_FAULT_RESPONSE must be set to ignore. The user also needs to set the IOUT_CAL_GAIN_TC to a value of 0. To ensure proper use of these temperature adjustment parameters, refer to the specific formulas given for the two methods by the MFR_PWM_MODE command in the later section covering PMBus command details. 10nF GND dual diode network as shown in Figure 35. This second measurement method is not generally as accurate as the first, but it supports legacy power blocks or may prove necessary if high noise environments prevent use of the ∆VBE approach with its lower signal levels. INPUT CURRENT SENSE AMPLIFIER The LTC7132 input current sense amplifier can sense the supply current into the VIN pin using an external resistor as well as the power stage current using an external current sense resistor shown in Figure 36. Unless care is taken to mitigate the frequency noise caused by the discontinuous input current, significant input current measurement error may occur. The noise will be the greatest in high current applications and at large step-down ratios. Careful layout and filtering at the SVIN pin is recommended to minimize measurement error. The SVIN pin should be filtered with a resistor and a ceramic capacitor. The filter should be Rev 0 For more information www.analog.com LTC7132 APPLICATIONS INFORMATION located as close to the SVIN pin as possible. The supply side of the SVIN pin filter should be Kelvin connected to the supply side of the RIINSNS resistor. A 2Ω resistor should be sufficient for most applications. The resistor will cause an IR voltage drop from the supply to the SVIN pin due to the current flowing into the SVIN pin. To compensate for this voltage drop, the MFR_RVIN command value should be set to the nominal resistor value. The LTC7132 will multiply the MFR_READ_ICHIP measurement value by the user defined MFR_RVIN value and add this voltage to the measured voltage at the SVIN pin. Therefore RCONFIG pins are only interrogated at initial power up and during a reset, so modifying their values on the fly while the part is powered will have no effect. However, this does mean that RCONFIG pins on the same IC can be shared with a single resistor divider if they require identical programming. Resistors with a tolerance of 1% or better must be used to assure proper operation. In the following tables, RTOP is connected between VDD25 and the RCONFIG pin while RBOT is connected between the pin and GND. Noisy clock signals should not be routed near these pins. READ_VIN = VSVIN_PIN + (MFR_READ_ICHIP • MFR_RVIN) Voltage Selection Therefore the READ_VIN command will return the value of the voltage at the supply side of the SVIN pin filter. If no SVIN filter element is used, set MFR_RVIN = 0. The capacitor C1 should be a low ESR ceramic capacitor. It should be placed as close as possible to PVIN0/1 to supply high frequency transient input current. This will help prevent noise from the top gate MOSFET from feeding into the input current sense amplifier inputs and supply. If the input current sense amplifier is not used, short the SVIN, IIN+, and IIN– pins together. C1 10µF PVIN0/1 IIN– IIN+ 2Ω 1µF n n n n n n n VOUT_OV_FAULT_LIMIT.................................... +10% VOUT_OV_WARN_LIMIT................................... +7.5% VOUT_MAX....................................................... +7.5% VOUT_MARGIN_HIGH..........................................+5% VOUT_MARGIN_LOW...........................................–5% VOUT_UV_WARN_LIMIT.................................. –6.5% VOUT_UV_FAULT_LIMIT...................................... –7% Table 3. VOUT_CFGn Resistor Programming RINSNS VIN When an output voltage is set using the VOUT_CFGn pins (by Table 3) the following parameters are set as a percentage of the output voltage: LTC7132 SVIN 7132 F37 Figure 36. Low Noise Input Current Sense Circuit EXTERNAL RESISTOR CONFIGURATION PINS (RCONFIG) The LTC7132 is factory programmed to use the external resistor configuration. This allows output voltage, PWM frequency, PWM phasing, and the PMBus address to be set by the user without programming the part through the PMBus interface or purchasing custom programmed parts. To use resistor programming, the RCONFIG pins require a resistor divider between VDD25 and GND. The RTOP (kΩ) RBOTTOM (kΩ) VOUT (V) ON/OFF 0 or Open Open NVM NVM 10 23.2 5.000 ON 10 15.8 3.300 ON 16.2 20.5 2.500 ON 16.2 17.4 1.800 ON 20 17.8 1.500 ON 20 15 1.350 ON 20 12.7 1.250 ON 20 11 1.200 ON 24.9 11.3 1.150 ON 24.9 9.09 1.100 ON 24.9 7.32 1.050 ON 24.9 5.76 0.900 ON 24.9 4.32 0.750 ON 30.1 3.57 0.650 ON 30.1 1.96 0.600 ON Open 0 NVM OFF Rev 0 For more information www.analog.com 55 LTC7132 APPLICATIONS INFORMATION Frequency Selection Phase Selection The PWM switching frequency is set according to Table 4. The SYNC pins must be shared in PolyPhase configurations where multiple LTC7132s are used to produce the output. If the configuration is not PolyPhase, the SYNC pins do not have to be shared. If the SYNC pins are shared between LTC7132s only one SYNC pin should be enabled; all other SYNC pins should be disabled. A pull-up resistor to VDD33 is required on the SYNC pin. The phase of the channels with respect to the falling edge of SYNC is set using the values in Table 5. Table 4. FREQ_CFG Resistor Programming Table 5. PHASE_CFG Resistor Programming RTOP SYNC TO CH0 SYNC TO CH1 (DEGREES) (DEGREES) SYNC OUTPUT (kΩ) RBOTTOM (kΩ) 0 or Open Open NVM NVM NVM 10 23.2 NVM NVM NVM 10 15.8 NVM NVM NVM 16.2 20.5 120 300 RTOP (kΩ) RBOTTOM (kΩ) FREQUENCY (kHz) 16.2 17.4 60 240 0 or Open Open NVM 20 17.8 120 240 0 120 10 23.2 NVM 20 15 10 15.8 NVM 20 12.7 0 240 16.2 20.5 NVM 20 11 90 270 16.2 17.4 NVM 24.9 11.3 0 180 20 17.8 NVM 24.9 9.09 120 300 20 15 NVM 24.9 7.32 60 240 20 12.7 NVM 24.9 5.76 120 240 20 11 1000 24.9 4.32 0 120 24.9 11.3 750 30.1 3.57 0 240 24.9 9.09 650 30.1 1.96 90 270 24.9 7.32 575 Open 0 0 180 24.9 5.76 500 24.9 4.32 425 30.1 3.57 350 30.1 1.96 250 Open 0 External Clock DISABLED ENABLED For example in a 4-phase configuration clocked at 500kHz, all of the LTC7132s must be set to the desired frequency and phase and only one LTC7132 should be set to the desired frequency with the SYNC pin enabled. All phasing is with respect to the falling edge of SYNC. For LTC7132 Chip 1, set the frequency to 500kHz with 90° and 270° phase shift with the SYNC pin enabled: Frequency: RTOP = 24.9kΩ and RBOT = 5.76kΩ Phase: RTOP = 30.1kΩ and RBOT = 1.96kΩ For LTC7132 Chip 2, set the frequency to 500kHz with 0°and 180° phase shift and the SYNC pin disabled: Frequency: 24.9kΩ and RBOT = 5.76kΩ Phase: RTOP = 24.9kΩ and RBOT = 11.3kΩ 56 Rev 0 For more information www.analog.com LTC7132 APPLICATIONS INFORMATION Address Selection Using RCONFIG The LTC7132 address is selected based on the programming of the two configuration pins ASEL0 and ASEL1 according to Table 6. ASEL0 programs the bottom four bits of the device address for the LTC7132, and ASEL1 programs the three most significant bits. Either portion of the address can also be retrieved from the MFR_ADDRESS value in EEPROM. If both pins are left open, the full 7-bit MFR_ADDRESS value stored in EEPROM is used to determine the device address. The LTC7132 always responds to 7-bit global addresses 0x5A and 0x5B. MFR_ADDRESS should not be set to either of these values because these are global addresses and all parts will respond to them. Table 6. ASELn Resistor Programming RTOP (kΩ) 0 or Open 10 10 16.2 16.2 20 20 20 20 24.9 24.9 24.9 24.9 24.9 30.1 30.1 Open RBOTTOM (kΩ) Open 23.2 15.8 20.5 17.4 17.8 15 12.7 11 11.3 9.09 7.32 5.76 4.32 3.57 1.96 0 ASEL1 LTC7132 DEVICE ADDRESS BITS[6:4] BINARY HEX EEPROM 111 110 101 100 011 010 001 000 7 6 5 4 3 2 1 0 ASEL0 LTC7132 DEVICE ADDRESS BITS[3:0] BINARY HEX EEPROM 1111 F 1110 E 1101 D 1100 C 1011 B 1010 A 1001 9 1000 8 0111 7 0110 6 0101 5 0100 4 0011 3 0010 2 0001 1 0000 0 Table 6b1. LTC7132 MFR_ADDRESS Command Examples Expressing Both 7- or 8-Bit Addressing HEX DEVICE ADDRESS BIT BIT BIT BIT BIT BIT BIT BIT DESCRIPTION 7 BIT 8 BIT 7 6 5 4 3 2 1 0 R/W Rail4 0x5A 0xB4 Global4 0x5B 0xB6 0 1 0 1 1 0 1 1 0 Default 0x4F 0x9E 0 1 0 0 1 1 1 1 0 0 1 0 1 1 0 1 0 0 Example 1 0x60 0xC0 0 1 1 0 0 0 0 0 0 Example 2 0x61 0xC2 0 1 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 Disabled2,3,5 Note 1: This table can be applied to the MFR_RAIL_ADDRESS command as well as the MFR_ADDRESS command. Note 2: A disabled value in one command does not disable the device, nor does it disable the Global address. Note 3: A disabled value in one command does not inhibit the device from responding to device addresses specified in other commands. Note 4: It is not recommended to write the value 0x00, 0x0C (7 bit), or 0x5A or 0x5B(7 bit) to the MFR_ADDRESS, or the MFR_RAIL_ADDRESS commands. Note 5: To disable the address enter 0x80 in the MFR_ADDRESS command. The 0x80 is greater than the 7-bit address field, disabling the address. EFFICIENCY CONSIDERATIONS The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC7132 circuits: 1) IC VIN current, 2) INTVCC regulator current, 3) I2R losses, 4) Topside MOSFET transition losses. 1. The VIN current is the DC supply current given in the Electrical Characteristics table, which excludes internal MOSFET driver and control currents. VIN current typically results in a small (1μF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. If the ratio of CLOAD to COUT is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 • CLOAD. Thus a 10μF capacitor would require a 250μs rise time, limiting the charging current to about 200mA. PolyPhase Configuration When configuring a PolyPhase rail with multiple LTC7132s, the user must share the SYNC, ITH, SHARE_CLK, FAULT, and ALERT pins of these parts. Be sure to use pull-up resistors on FAULT, SHARE_CLK and ALERT. One of the part’s SYNC pins must be set to the desired switching frequency, and all other FREQUENCY_SWITCH commands must be set to External Clock. If an external oscillator is provided, set the FREQUENCY_SWITCH command to External Clock for all parts. The relative phasing of all the channels should be spaced equally. The MFR_RAIL_ ADDRESS of all the devices should be set to the same value. Rev 0 For more information www.analog.com LTC7132 APPLICATIONS INFORMATION When connecting a PolyPhase rail with LTC7132s, connect the VIN pins of the LTC7132s directly back to the supply voltage through the VIN pin filter networks. PC BOARD LAYOUT CHECKLIST When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the IC. These items are also illustrated graphically in the layout diagram of Figure 44. Figure 45 illustrates the current waveforms present in the various branches of a synchronous regulator operating in continuous mode. Check the following in your layout: 1. Are signal ground and power ground kept separate? The ground return of CINTVCC must return to the combined COUT (–) terminals. 2. The ITH trace should be as short as possible. 3. The loop formed by the top N-channel MOSFET, Schottky diode and the CIN capacitor should have short leads and PC trace lengths. 4. The output capacitor (–) terminals should be connected as close as possible to the (–) terminals of the input capacitor by placing the capacitors next to each other and away from the Schottky loop described in item 4. + – 5. Are the ISENSE and ISENSE leads routed together with minimum PC trace spacing? The filter capacitor between ISENSE+ and ISENSE– should be as close as possible to the IC. Ensure accurate current sensing with Kelvin connections at the sense resistor or inductor, whichever is used for current sensing. 6. Is the INTVCC decoupling capacitor connected close to the IC, between the INTVCC and the power ground pins? This capacitor carries the MOSFET driver current peaks. An additional 1µF ceramic capacitor placed immediately next to the INTVCC and GND pins can help improve noise performance substantially. 7. Keep the switching nodes (SWn) and boost nodes (BOOSTn) away from sensitive small-signal nodes, especially from the voltage and current sensing feedback pins. All of these nodes have very large and fast moving signals and therefore should be kept on the “output side” of the LTC7132 and occupy minimum PC trace area. If DCR sensing is used, place the top resistor (Figure 25a, R1) close to the switching node. PC BOARD LAYOUT DEBUGGING It is helpful to use a DC-50MHz current probe to monitor the current in the inductor while testing the circuit. Monitor the output switching node (SWn pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. Check for proper performance over the operating voltage and current range expected in the application. The frequency of operation should be maintained over the input voltage range down to dropout and until the output load drops below the low current operation threshold. The duty cycle percentage should be maintained from cycle to cycle in a well-designed, low noise PCB implementation. Variation in the duty cycle at a subharmonic rate can suggest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. Overcompensation of the loop can be used to tame a poor PC layout if regulator bandwidth optimization is not required. Reduce VIN from its nominal level to verify operation of the regulator in dropout. Check the operation of the undervoltage lockout circuit by further lowering VIN while monitoring the outputs to verify operation. Investigate whether any problems exist only at higher output currents or only at higher input voltages. If problems coincide with high input voltages and low output currents, look for capacitive coupling between the BOOSTn and SWn connections and the sensitive voltage and current pins. The capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the IC. This capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. If problems are encountered with high current output loading at lower input voltages, look for inductive coupling between CIN, Schottky components to the sensitive current and voltage sensing traces. In addition, investigate common ground path voltage pickup between these components and the GND pin of the IC. Rev 0 For more information www.analog.com 61 LTC7132 APPLICATIONS INFORMATION VIN RIINSNS IIN– IIN RVIN C1 PVIN TSNS + Q1 LTC7132 ISENSE+ ISENSE– L SW SVIN CVIN SYNC RSENSE VOUT CB BOOST RUN VSENSE+ VSENSE– ITHR INTVCC ITH + VDD33 VDD25 PGND/SGND CINTVCC 7132 F45 Figure 44. Recommended Printed Circuit Layout Diagram, Single Phase Shown SW1 L1 D1 RSENSE1 VOUT1 COUT1 RL1 VIN RIN CIN SW0 BOLD LINES INDICATE HIGH SWITCHING CURRENT. KEEP LINES TO A MINIMUM LENGTH. D0 L0 RSENSE0 VOUT0 COUT0 RL0 7132 F46 Figure 45. Branch Current Waveforms 62 Rev 0 For more information www.analog.com LTC7132 APPLICATIONS INFORMATION DESIGN EXAMPLE As a design example for a 2-channel medium current regulator, assume VIN = 12V nominal, VIN = 20V maximum, VOUT0 =1.5V, VOUT1 = 1.05V, IMAX0,1 = 20A and f = 425kHz. The regulated output is established by the VOUT_ COMMAND stored in NVM or placing the following resistor divider between VDD25, the RCONFIG pin and SGND: 1. VOUT0_CFG, RTOP = 20k, RBOTTOM = 17.8k 2. VOUT1_CFG, RTOP = 24.9k, RBOTTOM = 7.32k peak to peak inductor current ripple will be 7.72A (38.6%) for channel 0 and 7.2A (35.9%) for channel 1. VOUT ⎡ VOUT ⎤ ⎢ ⎥ ΔIL(NOM) = 1– f •L ⎢⎣ VIN(NOM) ⎥⎦ The peak inductor current will be the maximum DC value plus one-half the ripple current or 23.9A for channel 0 and 23.6A for channel 1. The minimum on time occurs on channel 1 at the maximum VIN, and should not be less than 90ns: The frequency and phase are set by NVM or by setting the resistor divider between VDD25, FREQ_CFG and SGND and VDD25, PHASE_CFG and SGND. Frequency, RTOP = 24.9kΩ and RBOTTOM = 4.32kΩ The next design focuses on Channel1 only. Phase, RTOP = open and RBOTTOM = 0Ω The Coiltronics/Eaton FP1007R3-R30-R 0.3μH (0.29mΩ DCR at 20°C) is used for channel 1. So IOUT_CAL_GAIN = 0.29mΩ. The address is set to XF where X is the MSB stored in the NVM. The following parameters are set as a percentage of the output voltage if the resistor configuration pins are used to determined output voltage: n n n n n n n VOUT_OV_FAULT_LIMIT................................... +10% VOUT_OV_WARN_LIMIT.................................. +7.5% VOUT_MAX....................................................... +7.5% VOUT_MARGIN_HIGH............................................5% VOUT_MARGIN_LOW.............................................5% VOUT_UV_WARN_LIMIT.....................................6.5% VOUT_UV_FAULT_LIMIT........................................7% All other user defined parameters must be programmed into the NVM. The GUI can be utilized to quickly set up the part with the desired operating parameters. tON(MIN) = VOUT 1.5V =118ns VIN(MAX) • f 20V • 425kHz = Based on the output current and inductor value, it is considered to be a perfect example of low DCR application. Set: MFR_PWM_MODE[2] = 1 (Ultralow DCR) then choose C = 220nF, R1= L DCR • C • 5 = 0.30µH 0.29m� • 220nF • 5 = 940.4� Choose R1 = 931Ω (standard value, 1% tolerance resistor). The maximum power loss in R1 is related to the duty cycle, and will occur in continuous conduction mode at the maximum input voltage: PLOSSR1 = ( VIN(MAX) – VOUT ) • VOUT R1 (20−1) •1.5 = 20.4mW = 931 The inductance values are based on a 40% maximum ripple current assumption (8A). The highest value of ripple current occurs at the maximum input voltage: VOUT ⎡ VOUT ⎤ ⎢ ⎥ L= 1– f • ΔIL(MAX) ⎢⎣ VIN(MAX) ⎥⎦ The current limit will be set 30% higher than the peak value to assure variation in components and noise in the system do not limit the average current. Channel 0 will require 0.41μH and channel 1 will require 0.28μH. Use a standard value of L = 0.4µH for channel 0 and L = 0.3µH for channel 1. At the nominal VIN = 12V, the VILIMIT = (1 + 30%) • IPEAK • RDCR(MAX) = (1 + 30%) • 23.6A • 0.29mΩ = 8.9mV Rev 0 For more information www.analog.com 63 LTC7132 APPLICATIONS INFORMATION Based on Figure 26, set MFR_PWM_MODE[1] = 1(low VOUT range), MFR_PWM_MODE[2] = 1, (ultralow DCR) and MFR_PWM_MODE[7] = 0 (low current range) and IOUT_CAL_GAIN = 0.29mΩ in GUI. Enter IOUT_OC_FAULT_LIMIT = 30.69A, the LTC7132 will automatically set the current limit to 29.62A, based on the IOUT_FAULT_LIMIT table, (see PMBus command for details). ADDITIONAL DESIGN CHECKS Tie FAULT0 and FAULT1 together and pull up to VDD33 with a 10k resistor. Tie RUN0 and RUN1 together and pull up to VDD33 with a 10k resistor. If there are other ADI PSM parts, connect the RUN pins between chips and connect the FAULT pins between chips. Be sure all PMBus pins have resistor pull-up to VDD33 and connect these inputs across all ADI PSM parts in the application. Tie SHARE_CLK high with a 4.99k resistor to VDD33 and share between all ADI PSM parts in the application. Be sure a unique address for each chip can be decoded with the ASEL0 and ASEL1 pins. Refer to Table 6. For maximum flexibility, allow board space for RTOP and RBOTTOM for any parameter that is set with resistors such as ASEL0 and ASEL1. CONNECTING THE USB TO I2C/SMBus/PMBus CONTROLLER TO THE LTC7132 IN SYSTEM The ADI USB-to-I2C/SMBus/PMBus adapter (DC1613A or equivalent) can be interfaced to the LTC7132 on the user’s board for programming, telemetry and system debug. The adapter, when used in conjunction with LTpowerPlay, provides a powerful way to debug an entire power system. Faults are quickly diagnosed using telemetry, fault status commands and the fault log. The final configuration can be quickly developed and stored to the LTC7132 EEPROM. Figure 46 illustrates the application schematic for powering, programming and communication with one or more LTC7132s via the ADI I2C/SMBus/PMBus adapter regardless of whether or not system power is present. If system power is not present the dongle will power the VIN LTC CONTROLLER HEADER ISOLATED 3.3V SDA 100k 100k VIN VDD33 TP0101K SCL 1µF 10k VDD25 1µF LTC7132 SDA 10k SCL WP PGND/SGND TO LTC DC1613 USB TO I2C/SMBus/PMBus CONTROLLER VIN TP0101K VDD33 1µF VDD25 1µF LTC7132 SDA VGS MAX ON THE TP0101K IS 8V IF VIN > 16V CHANGE THE RESISTOR DIVIDER ON THE PFET GATE SCL WP PGND/SGND 7132 F47 Figure 46. Controller Connection 64 Rev 0 For more information www.analog.com LTC7132 APPLICATIONS INFORMATION LTC7132 through the VDD33 supply pin. To initialize the part when VIN is not applied and the VDD33 pin is powered use global address 0x5B command 0xBD data 0x2B followed by address 0x5B command 0xBD data 0xC4.The LTC7132 can now communicate with, and the project file can be updated. To write the updated project file to the NVM issue a STORE_USER _ALL command. When VIN is applied, a MFR_RESET must be issued to allow the PWM to be enabled and valid ADCs to be read. Because of the adapter’s limited current sourcing capability, only the LTC7132s, their associated pull-up resistors and the I2C pull-up resistors should be powered from the ORed 3.3V supply. In addition any device sharing the I2C bus connections with the LTC7132 should not have body diodes between the SDA/SCL pins and their respective VDD node because this will interfere with bus communication in the absence of system power. If VIN is applied, the DC1613A will not supply the power to the LTC7132s on the board. It is recommended the RUNn pins be held low or no voltage configuration resistors inserted to avoid providing power to the load until the part is fully configured. The LTC7132 is fully isolated from the host PC’s ground by the DC1613A.The 3.3V from the adapter and the LTC7132 VDD33 pin must be driven to each LTC7132 with a separate PFET. If both VIN and EXTVCC are not applied, the VDD33 pins can be in parallel because the on-chip LDO is off. The controller 3.3V current limit is 100mA but typical VDD33 currents are under 15mA. The VDD33 does back drive the INTVCC/EXTVCC pin. Normally this is not an issue if VIN is open. LTpowerPlay: AN INTERACTIVE GUI FOR DIGITAL POWER LTpowerPlay (Figure 47) is a powerful Windows-based development environment that supports Analog Devices digital power system management ICs including the LTC7132. The software supports a variety of different tasks. LTpowerPlay can be used to evaluate Analog Devices ICs by connecting to a demo board or the user application. LTpowerPlay can also be used in an offline mode (with no hardware present) in order to build multiple IC configuration files that can be saved and reloaded at a later time. LTpowerPlay provides unprecedented diagnostic and debug features. It becomes a valuable diagnostic tool during board bring-up to program or tweak the power system or to diagnose power issues when bring up rails. LTpowerPlay utilizes Analog Devices' USB-to-I2C/SMBus/ PMBus adapter to communication with one of the many potential targets including the DC2165A demo board, the DC2666A socketed programming board, or a customer target system. The software also provides an automatic update feature to keep the revisions current with the latest set of device drivers and documentation. A great deal of context sensitive help is available with LTpower Play along with several tutorial demos. Complete information is available at: www.analog.com/en/design-center/ltpower-play PMBus COMMUNICATION AND COMMAND PROCESSING The LTC7132 has a one deep buffer to hold the last data written for each supported command prior to processing as shown in Figure 48, Write Command Data Processing. When the part receives a new command from the bus, it copies the data into the Write Command Data Buffer, indicates to the internal processor that this command data needs to be fetched, and converts the command to its internal format so that it can be executed. Two distinct parallel blocks manage command buffering and command processing (fetch, convert, and execute) to ensure the last data written to any command is never lost. Command data buffering handles incoming PMBus writes by storing the command data to the Write Command Data Buffer and marking these commands for future processing. The internal processor runs in parallel and handles the sometimes slower task of fetching, converting and executing commands marked for processing. Some computationally intensive commands (e.g., timing parameters, temperatures, voltages and currents) have internal processor execution times that may be long relative to PMBus timing. If the part is busy processing a command, and new command(s) arrive, execution may be delayed or processed in a different order than received. The part Rev 0 For more information www.analog.com 65 LTC7132 APPLICATIONS INFORMATION Figure 47. LTpowerPlay Screen Shot CMD PMBus WRITE WRITE COMMAND DATA BUFFER DECODER CMDS DATA MUX CALCULATIONS PENDING S R PAGE • • • VOUT_COMMAND 0x00 0x21 • • • MFR_RESET INTERNAL PROCESSOR FETCH, CONVERT DATA AND EXECUTE 0xFD x1 7132 F49 Figure 48. Write Command Data Processing 66 Rev 0 For more information www.analog.com LTC7132 APPLICATIONS INFORMATION // wait until chip is not busy do { mfrCommonValue = PMBUS_READ_BYTE(0xEF); partReady = (mfrCommonValue & 0x68) == 0x68; }while(!partReady) // now the part is ready to receive the next command PMBUS_WRITE_WORD(0x21, 0x2000); //write VOUT_COMMAND to 2V Figure 50. Example of a Command Write of VOUT_COMMAND indicates when internal calculations are in process via bit  5 of MFR_COMMON (‘calculations not pending’). When the part is busy calculating, bit 5 is cleared. When this bit is set, the part is ready for another command. An example polling loop is provided in Figure 50 which ensures that commands are processed in order while simplifying error handling routines. When the part receives a new command while it is busy, it will communicate this condition using standard PMBus protocol. Depending on part configuration it may either NACK the command or return all ones (0xFF) for reads. It may also generate a BUSY fault and ALERT notification, or stretch the SCL clock low. For more information refer to PMBus Specification v1.1, Part II, Section 10.8.7 and SMBus v2.0 section 4.3.3. Clock stretching can be enabled by asserting bit 1 of MFR_CONFIG_ ALL. Clock stretching will only occur if enabled and the bus communication speed exceeds 100kHz. PMBus busy protocols are well accepted standards, but can make writing system level software somewhat complex. The part provides three ‘hand shaking’ status bits which reduce complexity while enabling robust system level communication. The three hand shaking status bits are in the MFR_ COMMON register. When the part is busy executing an internal operation, it will clear bit 6 of MFR_COMMON (‘chip not busy’). When the part is busy specifically because it is in a transitional VOUT state (margining hi/lo, power off/on, moving to a new output voltage set point, etc.) it will clear bit 4 of MFR_COMMON (‘output not in transition’). When internal calculations are in process, the part will clear bit 5 of MFR_COMMON (‘calculations not pending’). These three status bits can be polled with a PMBus read byte of the MFR_COMMON register until all three bits are set. A command immediately following the status bits being set will be accepted without NACKing or generating a BUSY fault/ALERT notification. The part can NACK commands for other reasons, however, as required by the PMBus spec (for instance, an invalid command or data). An example of a robust command write algorithm for the VOUT_COMMAND register is provided in Figure 50. It is recommended that all command writes (write byte, write word, etc.) be preceded with a polling loop to avoid the extra complexity of dealing with busy behavior and unwanted ALERT notification. A simple way to achieve this is to create a SAFE_WRITE_BYTE() and SAFE_WRITE_ WORD() subroutine. The above polling mechanism allows your software to remain clean and simple while robustly communicating with the part. For a detailed discussion of these topics and other special cases please refer to the application note section located at: www.analog.com/en/education.html When communicating using bus speeds at or below 100kHz, the polling mechanism shown here provides a simple solution that ensures robust communication without clock stretching. At bus speeds in excess of 100kHz, it is strongly recommended that the part be configured to enable clock stretching. This requires a PMBus master that supports clock stretching. System software that detects and properly recovers from the standard PMBus NACK/ BUSY faults as described in the PMBus Specification v1.1, Part II, Section 10.8.7 is required to communicate: the LTC7132 is not recommended in applications with bus speeds in excess of 400kHz. Rev 0 For more information www.analog.com 67 LTC7132 PMBus COMMAND DETAILS ADDRESSING AND WRITE PROTECT CMD CODE 0x00 0x05 0x06 COMMAND NAME PAGE PAGE_PLUS_WRITE PAGE_PLUS_READ DATA DEFAULT TYPE PAGED FORMAT UNITS NVM VALUE R/W Byte N Reg 0x00 W Block N Block N R/W R/W Byte N Reg Y 0x00 DESCRIPTION Provides integration with multi-page PMBus devices. Write a supported command directly to a PWM channel. Read a supported command directly from a PWM channel. 0x10 Level of protection provided by the device against accidental changes. 0xE6 Sets the 7-bit I2C address byte. 0xFA Common address for PolyPhase outputs to adjust common parameters. WRITE_PROTECT MFR_ADDRESS MFR_RAIL_ADDRESS R/W Byte R/W Byte N Y Reg Reg Y Y 0x4F 0x80 PAGE The PAGE command provides the ability to configure, control and monitor both PWM channels through only one physical address, either the MFR_ADDRESS or GLOBAL device address. Each PAGE contains the operating commands for one PWM channel. Pages 0x00 and 0x01 correspond to Channel 0 and Channel 1, respectively, in this device. Setting PAGE to 0xFF applies any following paged commands to both outputs. With PAGE set to 0xFF the LTC7132 will respond to read commands as if PAGE were set to 0x00 (Channel 0 results). This command has one data byte. PAGE_PLUS_WRITE The PAGE_PLUS_WRITE command provides a way to set the page within a device, send a command, and then send the data for the command, all in one communication packet. Commands allowed by the present write protection level may be sent with PAGE_PLUS_WRITE. The value stored in the PAGE command is not affected by PAGE_PLUS_WRITE. If PAGE_PLUS_WRITE is used to send a non-paged command, the Page Number byte is ignored. This command uses Write Block protocol. An example of the PAGE_PLUS_WRITE command with PEC sending a command that has two data bytes is shown in Figure 50. 1 7 S SLAVE ADDRESS 1 1 W PAGE_PLUS A A COMMAND CODE 8 8 LOWER DATA BYTE 1 8 BLOCK COUNT (= 4) 1 8 A PAGE NUMBER 1 8 1 8 1 A UPPER DATA BYTE A PEC BYTE A 1 8 1 A COMMAND CODE A … 1 P 7132 F51 Figure 50. Example of PAGE_PLUS_WRITE 68 Rev 0 For more information www.analog.com LTC7132 PMBus COMMAND DETAILS PAGE_PLUS_READ The PAGE_PLUS_READ command provides the ability to set the page within a device, send a command, and then read the data returned by the command, all in one communication packet . The value stored in the PAGE command is not affected by PAGE_PLUS_READ. If PAGE_PLUS_READ is used to access data from a non-paged command, the Page Number byte is ignored. This command uses the Process Call protocol. An example of the PAGE_PLUS_READ command with PEC is shown in Figure 51. 1 7 S SLAVE ADDRESS 1 7 Sr SLAVE ADDRESS 1 R 1 1 W PAGE_PLUS A A COMMAND CODE 8 1 8 A BLOCK COUNT (= 2) 1 8 BLOCK COUNT (= 2) 1 8 A LOWER DATA BYTE 1 8 A PAGE NUMBER 1 8 1 A COMMAND CODE A 1 8 1 8 A UPPER DATA BYTE A PEC BYTE 1 … 1 NA P 7132 F52 Figure 51. Example of PAGE_PLUS_READ Note: PAGE_PLUS commands cannot be nested. A PAGE_PLUS command cannot be used to read or write another PAGE_PLUS command. If this is attempted, the LTC7132 will NACK the entire PAGE_PLUS packet and issue a CML fault for Invalid/Unsupported Data. WRITE_PROTECT The WRITE_PROTECT command is used to control writing to the LTC7132 device. This command does not indicate the status of the WP pin which is defined in the MFR_COMMON command. The WP pin takes precedence over the value of this command. BYTE MEANING 0x80 Disable all writes except to the WRITE_PROTECT, PAGE, MFR_ EE_UNLOCK, and STORE_USER_ALL commands. 0x40 Disable all writes except to the WRITE_PROTECT, PAGE, MFR_EE_UNLOCK, MFR_CLEAR_PEAKS, STORE_USER_ALL, OPERATION and CLEAR_FAULTS command. Individual fault bits can be cleared by writing a 1 to the respective bits in the STATUS commands. 0x20 Disable all writes except to the WRITE_PROTECT, OPERATION, MFR_EE_UNLOCK, MFR_CLEAR_PEAKS, CLEAR_FAULTS, PAGE, ON_OFF_CONFIG, VOUT_COMMAND and STORE_USER_ ALL. Individual fault bits can be cleared by writing a 1 to the respective bits in the STATUS commands. 0x10 Reserved, must be 0 0x08 Reserved, must be 0 0x04 Reserved, must be 0 0x02 Reserved, must be 0 0x01 Reserved, must be 0 Enable writes to all commands when WRITE_PROTECT is set to 0x00. If WP pin is high, PAGE, OPERATION, MFR_CLEAR_PEAKS, MFR_EE_UNLOCK, WRITE_PROTECT and CLEAR_FAULTS commands are supported. Individual fault bits can be cleared by writing a 1 to the respective bits in the STATUS commands. Rev 0 For more information www.analog.com 69 LTC7132 PMBus COMMAND DETAILS MFR_ADDRESS The MFR_ADDRESS command byte sets the 7 bits of the PMBus slave address for this device. Setting this command to a value of 0x80 disables device addressing. The GLOBAL device address, 0x5A and 0x5B, cannot be deactivated. If RCONFIG is set to ignore, the ASEL0 and ASEL1 pins are still used to determine the LSB and MSB, respectively, of the channel address. If the ASEL0 and ASEL1 pins are both open, the LTC7132 will use the address value stored in NVM. If the ASEL0 pin is open, the LTC7132 will use the lower 4 bits of the MFR_ADDRESS value stored in NVM to construct the effective address of the part. If the ASEL1 pin is open, the LTC7132 will use the upper 4 bits of the MFR_ADDRESS value stored in NVM to construct the effective address of the part. This command has one data byte. MFR_RAIL_ADDRESS The MFR_RAIL_ADDRESS command enables direct device address access to the PAGE activated channel. The value of this command should be common to all devices attached to a single power supply rail. The user should only perform command writes to this address. If a read is performed from this address and the rail devices do not respond with EXACTLY the same value, the LTC7132 will detect bus contention and may set a CML communications fault. Setting this command to a value of 0x80 disables rail device addressing for the channel. This command has one data byte. GENERAL CONFIGURATION COMMANDS COMMAND NAME CMD CODE DESCRIPTION TYPE DATA PAGED FORMAT UNITS NVM DEFAULT VALUE MFR_CHAN_CONFIG 0xD0 Configuration bits that are channel specific. R/W Byte Y Reg Y 0x10 MFR_CONFIG_ALL 0xD1 General configuration bits. R/W Byte N Reg Y 0x21 MFR_CHAN_CONFIG General purpose configuration command common to multiple ADI products. BIT MEANING 7 Reserved 6 Reserved 5 Reserved 4 Disable RUN Low. When asserted the RUN pin is not pulsed low if commanded OFF. 3 Enable Short Cycle recognition if this bit is set to a 1. 2 SHARE_CLOCK control. If SHARE_CLOCK is held low, the output is disabled. 1 No FAULT ALERT, ALERT is not pulled low if FAULT is pulled low externally. Assert this bit if either POWER_GOOD or VOUT_UVUF are propagated on FAULT. 0 Disables the VOUT decay value requirement for MFR_RETRY_TIME and tOFF(MIN) processing. When this bit is set to a 0, the output must decay to less than 12.5% of the programmed value for any action that turns off the rail including a fault, an OFF/ON command, or a toggle of RUN from high to low to high. This command has one data byte. 70 Rev 0 For more information www.analog.com LTC7132 PMBus COMMAND DETAILS A ShortCycle event occurs whenever the PWM channel is commanded back ON, or reactivated, after the part has been commanded OFF and is processing either the TOFF_DELAY or the TOFF_FALL states. The PWM channel can be turned ON and OFF through either the RUN pin and or the PMBus OPERATION command. If the PWM channel is reactivated during the TOFF_DELAY, the part will perform the following: 1. Immediately tri-state the PWM channel output; 2. Start the retry delay timer as specified by the tOFF(MIN). 3. After the tOFF(MIN) value has expired, the PWM channel will proceed to the TON_DELAY state and the STATUS_ MFR_SPECIFIC bit #1 will assert. If the PWM channel is reactivated during the TOFF_FALL, the part will perform the following: 1. Stop ramping down the PWM channel output; 2. Immediately tri-state the PWM channel output; 3. Start the retry delay timer as specified by the tOFF(MIN). 4. After the tOFF(MIN) value has expired, the PWM channel will proceed to the TON_DELAY state and the STATUS_ MFR_SPEFIFIC bit #1 will assert. If the ShortCycle event occurs and the ShortCycle MFR_CHAN_CONFIG bit is not set, the PWM channel state machine will complete its TOFF_DELAY and TOFF_FALL operations as previously commanded by the user. MFR_CONFIG_ALL General purpose configuration command common to multiple ADI products. BIT MEANING 7 Enable Fault Logging 6 Ignore Resistor Configuration Pins 5 Mask PMBus, Part II, Section 10.9.1 Violations 4 Disable SYNC output 3 Enable 255ms PMBus timeout 2 PMBus command writes require a valid Packet Error Checking, PEC to be accepted.* 1 Enable the use of PMBus clock stretching 0 Execute CLEAR_FAULTS on rising edge of either RUN pin. *PMBus command writes that have a valid PEC byte are always processed. PMBus command writes that have an invalid PEC byte are not processed and set a CML status fault. This command has one data byte. ON/OFF/MARGIN COMMAND NAME CMD CODE DESCRIPTION ON_OFF_CONFIG 0x02 OPERATION MFR_RESET TYPE PAGED RUN pin and PMBus bus on/off command configuration. R/W Byte Y 0x01 Operating mode control. On/off, margin high and margin low. R/W Byte Y 0xFD Commanded reset without requiring a power-down. Send Byte N DATA FORMAT UNITS NVM DEFAULT VALUE Reg Y 0x1E Reg Y 0x80 NA Rev 0 For more information www.analog.com 71 LTC7132 PMBus COMMAND DETAILS ON_OFF_CONFIG The ON_OFF_CONFIG command specifies the combination of RUNn pin input state and PMBus commands needed to turn the PWM channel on and off. Supported Values: VALUE MEANING 0x1F OPERATION value and RUNn pin must both command the device to start/run. Device executes immediate off when commanded off. 0x1E OPERATION value and RUNn pin must both command the device to start/run. Device uses TOFF_ command values when commanded off. 0x17 RUNn pin control with immediate off when commanded off. OPERATION on/off control ignored. 0x16 RUNn pin control using TOFF_ command values when commanded off. OPERATION on/off control ignored. Programming an unsupported ON_OFF_CONFIG value will generate a CML fault and the command will be ignored. This command has one data byte. OPERATION The OPERATION command is used to turn the unit on and off in conjunction with the input from the RUNn pins. It is also used to cause the unit to set the output voltage to the upper or lower MARGIN VOLTAGEs. The unit stays in the commanded operating mode until a subsequent OPERATION command or change in the state of the RUNn pin instructs the device to change to another mode. If the part is stored in the MARGIN_LOW/HIGH state, the next RESET or POWER_ON cycle will ramp to that state. If the OPERATION command is modified, for example ON is changed to MARGIN_LOW, the output will move at a fixed slope set by the VOUT_TRANSITION_RATE. The default operation command is sequence off. If VIN is applied to a part with factory default programming and the VOUT_CONFIG resistor configuration pins are not installed, the outputs will be commanded off. The part defaults to the Sequence Off state. This command has one data byte. Supported Values: VALUE MEANING 0xA8 Margin high. 0x98 Margin low. 0x80 On (VOUT back to nominal even if bit 3 of ON_OFF_CONFIG is not set). 0x40* Soft off (with sequencing). 0x00* Immediate off (no sequencing). *Device does not respond to these commands if bit 3 of ON_OFF_CONFIG is not set. Programming an unsupported OPERATION value will generate a CML fault and the command will be ignored. This command has one data byte. MFR_RESET This command provides a means to reset the LTC7132 from the serial bus. This forces the LTC7132 to turn off both PWM channels, load the operating memory from internal EEPROM, clear all faults and then perform a soft-start of both PWM channels, if enabled. This write-only command has no data bytes. 72 Rev 0 For more information www.analog.com LTC7132 PMBus COMMAND DETAILS PWM CONFIGURATION COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA DEFAULT FORMAT UNITS NVM VALUE MFR_PWM_COMP 0xD3 PWM loop compensation configuration R/W Byte Y Reg Y 0xAE MFR_PWM_MODE 0xD4 Configuration for the PWM engine. R/W Byte Y Reg Y 0xC7 MFR_PWM_CONFIG 0xF5 Set numerous parameters for the DC/DC controller including phasing. R/W Byte N Reg Y 0x10 FREQUENCY_SWITCH 0x33 Switching frequency of the controller. R/W Word N L11 Y 425 0xFB52 kHz MFR_PWM_MODE The MFR_PWM_MODE command sets important PWM controls for each channel. The MFR_PWM_MODE command allows the user to program the PWM controller to use discontinuous (pulse-skipping mode), or forced continuous conduction mode. BIT 7 0b 1b 6 5 MEANING Use High Range of ILIMIT Low Current Range High Current Range Enable Servo Mode External temperature sense: 0: ΔVBE measurement. [4:3] 2 1 1b 0b Bit[0] 0b 1b 1: Direct voltage measurement. Reserved Enable ultra-low DCR current sense VOUT Range The maximum output voltage is 2.75V The maximum output voltage is 5.5V Mode Discontinuous Forced Continuous Bit [7] of this command determines if the part is in high range or low range of the IOUT_OC_FAULT_LIMIT command. Changing this bit value changes the PWM loop gain and compensation. This bit value should not be changed when the channel output is active. Writing this bit when the channel is active will generate a CML fault. Bit [6] The LTC7132 will not servo while the part is OFF, ramping on or ramping off. When set to a one, the output servo is enabled. The output set point DAC will be slowly adjusted to minimize the difference between the READ_VOUT_ADC and the VOUT_COMMAND (or the appropriate margined value). When Bit[5] is cleared, the LTC7132 computes temperature in °C from ∆VBE measured by the ADC at the TSNSn pin as T = (G • ΔVBE • q/(K • ln(16))) – 273.15 + O When Bit[5] is set, the LTC7132 computes temperature in °C from TSNSn voltage measured by the ADC as T = (G • (1.35 – VTSNSn + O)/4.3e-3) + 25 Rev 0 For more information www.analog.com 73 LTC7132 PMBus COMMAND DETAILS For both equations, G = MFR_TEMP_1_GAIN • 2–14, and O = MFR_TEMP_1_OFFSET K = 1.381 • 10–23J/K q = 1.602 • 10–19C Bit[2] determines if the part uses ultralow DCR for sensing the output current. This is a very critical selection in terms of overcurrent limit. It is highly recommend that Bit[2] should not be changed when device is in operation. Bit[1] of this command determines if the part is in high range or low voltage range. Changing this bit value changes the PWM loop gain and compensation. This bit value should not be changed when the channel output is active. Writing this bit when the channel is active will generate a CML fault. Bit[0] determines if the PWM mode of operation is discontinuous (pulse-skipping mode), or forced continuous conduction mode. Whenever the channel is ramping on, the PWM mode will be discontinuous, regardless of the value of this bit. This command has one data byte. MFR_PWM_COMP The MFR_PWM_COMP command sets the gm of the PWM channel error amplifiers and the value of the internal RITHn compensation resistors. This command affects the loop gain of the PWM output which may require modifications to the external compensation network. BIT BIT [7:5] 000b 001b 010b 011b 100b 101b 110b 111b BIT [4:0] 00000b 00001b 00010b 00011b 00100b 00101b 00110b 00111b 01000b 01001b 01010b 01011b 01100b 01101b 74 MEANING Error Amplifier GM Adjust (mS) 0.8 1.3 1.9 2.4 2.9 3.5 4.0 4.6 RITH (kΩ) 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.5 3 3.5 4 4.5 Rev 0 For more information www.analog.com LTC7132 PMBus COMMAND DETAILS 01110b 01111b 10000b 10001b 10010b 10011b 10100b 10101b 10110b 10111b 11000b 11001b 11010b 11011b 11100b 11101b 11110b 11111b 5 5.5 6 7 8 9 11 13 15 17 20 24 28 32 38 46 54 62 This command has one data byte. MFR_PWM_CONFIG The MFR_PWM_CONFIG command sets the switching frequency phase offset with respect to the falling edge of the SYNC signal. The part must be in the OFF state to process this command. Either the RUN pins must be low or the channels must be commanded off. If either channel is in the RUN state and this command is written, the command will be NACK’d and a BUSY fault will be asserted. BIT MEANING 7 Reserved [6:5] 00b 01b 10b 11b Input current sense gain. 2x gain. 0mV to 50mV range. 4x gain. 0mV to 20mV range. 8x gain. 0mV to 5mV range. Reserved 4 Share Clock Enable : If this bit is 1, the SHARE_CLK pin will not be released until VIN > VIN_ON. The SHARE_CLK pin will be pulled low when VIN < VIN_OFF. If this bit is 0, the SHARE_CLK pin will not be pulled low when VIN < VIN_OFF except for the initial application of VIN. BIT [2:0] CHANNEL 0 (DEGREES) CHANNEL 1 (DEGREES) 000b 0 180 001b 90 270 010b 0 240 011b 0 120 100b 120 240 101b 60 240 110b 120 300 Rev 0 For more information www.analog.com 75 LTC7132 PMBus COMMAND DETAILS FREQUENCY_SWITCH The FREQUENCY_SWITCH command sets all switching frequencies between 250kHz to 1MHz. The part must be in the OFF state to process this command. The RUN pin must be low or both channels must be commanded off. If the part is in the RUN state and this command is written, the command will be NACK'd and a BUSY fault will be asserted. When the part is commanded off and the frequency is changed, a PLL_UNLOCK status may be detected as the PLL locks onto the new frequency. This command has two data bytes and is formatted in Linear_5s_11s format. VOLTAGE Input Voltage and Limits COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAULT VALUE VIN_OV_FAULT_LIMIT 0x55 Input supply overvoltage fault limit. R/W Word N L11 V Y 15.5 0xD3E0 VIN_UV_WARN_LIMIT 0x58 Input supply undervoltage warning limit. R/W Word N L11 V Y 6.3 0xCB26 VIN_ON 0x35 Input voltage at which the unit should start power conversion. R/W Word N L11 V Y 6.5 0xCB40 VIN_OFF 0x36 Input voltage at which the unit should stop power conversion. R/W Word N L11 V Y 6.0 0xCB00 MFR_RVIN 0xF7 The resistance value of the VIN pin filter element in milliohms R/W Word N L11 mΩ Y 1000 0x03E8 VIN_OV_FAULT_LIMIT The VIN_OV_FAULT_LIMIT command sets the value of the input voltage measured by the ADC, in volts, that causes an input overvoltage fault. This command has two data bytes in Linear_5s_11s format. VIN_UV_WARN_LIMIT The VIN_UV_WARN_LIMIT command sets the value of input voltage measured by the ADC that causes an input undervoltage warning. This warning is disabled until the input exceeds the input startup threshold value set by the VIN_ON command and the unit has been enabled. If the VIN Voltage drops below the VIN_OV_WARN_LIMIT the device: • Sets the INPUT Bit Is the STATUS_WORD • Sets the VIN Undervoltage Warning Bit in the STATUS_INPUT Command • Notifies the Host by Asserting ALERT, unless Masked VIN_ON The VIN_ON command sets the input voltage, in Volts, at which the unit starts power conversion. This command has two data bytes and is formatted in Linear_5s_11s format. 76 Rev 0 For more information www.analog.com LTC7132 PMBus COMMAND DETAILS VIN_OFF The VIN_OFF command sets the input voltage, in Volts, at which the unit stops power conversion. This command has two data bytes and is formatted in Linear_5s_11s format. MFR_RVIN The MFR_RVIN command is used to set the resistance value of the VIN pin filter element in milliohms. (See also READ_VIN). Set MFR_RVIN equal to 0 if no filter element is used. This command has two data bytes and is formatted in Linear_5s_11s format. Output Voltage and Limits COMMAND NAME VOUT_MODE CMD CODE 0x20 DESCRIPTION Output voltage format and exponent (2–12). TYPE R Byte PAGED Y DATA FORMAT Reg UNITS NVM VOUT_MAX 0x24 L16 V Y Y L16 V Y VOUT_OV_WARN_ LIMIT 0x42 Output overvoltage warning limit. Y L16 V Y VOUT_MARGIN_HIGH 0x25 Y L16 V Y VOUT_COMMAND 0x21 Margin high output voltage set point. Must be greater than VOUT_COMMAND. Nominal output voltage set point. Y L16 V Y VOUT_MARGIN_LOW 0x26 Y L16 V Y VOUT_UV_WARN_ LIMIT 0x43 Margin low output voltage set point. Must be less than VOUT_COMMAND. Output undervoltage warning limit. Y L16 V Y VOUT_UV_FAULT_ LIMIT 0x44 Output undervoltage fault limit. Y L16 V Y MFR_VOUT_MAX 0xA5 Maximum allowed output voltage. R/W Word R/W Word R/W Word R/W Word R/W Word R/W Word R/W Word R/W Word R Word Y 0x40 Upper limit on the output voltage the unit can command regardless of any other commands. Output overvoltage fault limit. VOUT_OV_FAULT_ LIMIT Y L16 V DEFAULT VALUE 2–12 0x14 2.75 0x2C00 1.1 0x119A 1.075 0x1133 1.05 0x10CD 1.0 0x1000 0.95 0x0F33 0.925 0x0ECD 0.9 0x0E66 5.7 0x5B33 VOUT_MODE The data byte for VOUT_MODE command, used for commanding and reading output voltage, consists of a 3-bit mode (only linear format is supported) and a 5-bit parameter representing the exponent used in output voltage Read/Write commands. This read-only command has one data byte. VOUT_MAX The VOUT_MAX command sets an upper limit on any voltage, including VOUT_MARGIN_HIGH, the unit can command regardless of any other commands or combinations. The maximum allowed value of this command is 5.8V. The maximum output voltage the LTC7132 can produce is 5.5V including VOUT_MARGIN_HIGH. However, the VOUT_ OV_FAULT_LIMIT can be commanded as high as 5.7V. This command has two data bytes and is formatted in Linear_16u format. Rev 0 For more information www.analog.com 77 LTC7132 PMBus COMMAND DETAILS VOUT_OV_FAULT_LIMIT The VOUT_OV_FAULT_LIMIT command sets the value of the output voltage measured by the OV supervisor comparator at the sense pins, in volts, which causes an output overvoltage fault. If the VOUT_OV_FAULT_LIMIT is modified and the part is in the RUN state, allow 10ms after the command is modified to assure the new value is being honored. The part indicates if it is busy making a calculation. Monitor bits 5 and 6 of MFR_COMMON. Either bit is low if the part is busy. If this wait time is not honored and the VOUT_COMMAND is modified above the old overvoltage limit, an OV condition might temporarily be detected resulting in undesirable behavior and possible damage to the switcher. If VOUT_OV_FAULT_RESPONSE is set to OV_PULLDOWN or 0x00, the FAULT pin will not assert if VOUT_OV_FAULT is propagated. The LTC7132 will pull the TG low and assert the BG bit as soon as the overvoltage condition is detected. This command has two data bytes and is formatted in Linear_16u format. VOUT_OV_WARN_LIMIT The VOUT_OV_WARN_LIMIT command sets the value of the output voltage measured by the ADC at the sense pins, in volts, which causes an output voltage high warning. The MFR_VOUT_PEAK value can be used to determine if this limit has been exceeded. In response to the VOUT_OV_WARN_LIMIT being exceeded, the device: • Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE • Sets the VOUT bit in the STATUS_WORD • Sets the VOUT Overvoltage Warning bit in the STATUS_VOUT command • Notifies the host by asserting ALERT pin, unless masked This condition is detected by the ADC so the response time may be up to tCONVERT. This command has two data bytes and is formatted in Linear_16u format. VOUT_MARGIN_HIGH The VOUT_MARGIN_HIGH command loads the unit with the voltage to which the output is to be changed, in Volts, when the OPERATION command is set to “Margin High”. The value should be greater than VOUT_COMMAND. The maximum guaranteed value on VOUT_MARGIN_HIGH is 5.5V. This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_ RATE will be used if this command is modified while the output is active and in a steady-state condition. This command has two data bytes and is formatted in Linear_16u format. 78 Rev 0 For more information www.analog.com LTC7132 PMBus COMMAND DETAILS VOUT_COMMAND The VOUT_COMMAND consists of two bytes and is used to set the output voltage, in volts. The maximum guaranteed value on VOUT is 5.5V. This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_ RATE will be used if this command is modified while the output is active and in a steady-state condition. This command has two data bytes and is formatted in Linear_16u format. VOUT_MARGIN_LOW The VOUT_MARGIN_LOW command loads the unit with the voltage to which the output is to be changed, in volts, when the OPERATION command is set to “Margin Low”. The value must be less than VOUT_COMMAND. This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_ RATE will be used if this command is modified while the output is active and in a steady-state condition. This command has two data bytes and is formatted in Linear_16u format. VOUT_UV_WARN_LIMIT The VOUT_UV_ WARN_LIMIT command reads the value of the output voltage measured by the ADC at the sense pins, in volts, which causes an output voltage low warning. In response to the VOUT_UV_WARN_LIMIT being exceeded, the device: • Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE • Sets the VOUT bit in the STATUS_WORD • Sets the VOUT Undervoltage Warning bit in the STATUS_VOUT command • Notifies the host by asserting ALERT pin, unless masked This command has two data bytes and is formatted in Linear_16u format. VOUT_UV_FAULT_LIMIT The VOUT_UV_FAULT_LIMIT command reads the value of the output voltage measured by the UV supervisor comparator at the sense pins, in volts, which causes an output undervoltage fault. This command has two data bytes and is formatted in Linear_16u format. MFR_VOUT_MAX The MFR_VOUT_MAX command is the maximum output voltage in volts for each channel, including VOUT_OV_FAULT_ LIMIT. If the output voltages are set to high range (Bit 1 of MFR_PWM_MODE set to a 0) MFR_VOUT_MAX is 5.5V. If the output voltage is set to low range (Bit 1 of MFR_PWM_MODE set to a 1) the MFR_VOUT_MAX is 2.75V. Entering a VOUT_COMMAND value greater than this will result in a CML fault and the output voltage setting will be clamped to the maximum level. This will also result in Bit 3 VOUT_MAX_Warning in the STATUS_VOUT command being set. This read only command has 2 data bytes and is formatted in Linear_16u format. Rev 0 For more information www.analog.com 79 LTC7132 PMBus COMMAND DETAILS OUTPUT CURRENT AND LIMITS COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAULT VALUE mΩ Y 0.32 0xAA8F Y 3900 0x0F3C IOUT_CAL_GAIN 0x38 The ratio of the voltage at the current R/W Word sense pins to the sensed current. For devices using a fixed current sense resistor, it is the resistance value in mΩ. Y L11 MFR_IOUT_CAL_GAIN_TC 0xF6 Temperature coefficient of the current R/W Word sensing element. Y CF IOUT_OC_FAULT_LIMIT 0x46 Output overcurrent fault limit. R/W Word Y L11 A Y 45.0 0xE2D0 IOUT_OC_WARN_LIMIT 0x4A Output overcurrent warning limit. R/W Word Y L11 A Y 34.0 0xE230 IOUT_CAL_GAIN The IOUT_CAL_GAIN command is used to set the resistance value of the current sense resistor in milliohms. (see also MFR_IOUT_CAL_GAIN_TC). This command has two data bytes and is formatted in Linear_5s_11s format. MFR_IOUT_CAL_GAIN_TC The MFR_IOUT_CAL_GAIN_TC command allows the user to program the temperature coefficient of the IOUT_CAL_ GAIN sense resistor or inductor DCR in ppm/°C. This command has two data bytes and is formatted in 16-bit 2’s complement integer ppm. N = –32768 to 32767 • 10–6. Nominal temperature is 27°C. The IOUT_CAL_GAIN is multiplied by: [1.0 + MFR_IOUT_CAL_GAIN_TC • (READ_TEMPERATURE_1‑27)]. DCR sensing will have a typical value of 3900. The IOUT_CAL_GAIN and MFR_IOUT_CAL_GAIN_TC impact all current parameters including: READ_IOUT, MFR_IOUT_PEAK, IOUT_OC_FAULT_LIMIT and IOUT_OC_WARN_LIMIT. IOUT_OC_FAULT_LIMIT The IOUT_OC_FAULT_LIMIT command sets the value of the peak output current limit, in Amperes. When the controller is in current limit, the overcurrent detector will indicate an overcurrent fault condition. The following table lists the progammable peak output current limit value in mV between ISENSE+ and ISENSE–. The actual value of current limit is (ISENSE+ – ISENSE–)/IOUT_CAL_GAIN in Amperes. 80 Rev 0 For more information www.analog.com LTC7132 PMBus COMMAND DETAILS CODE 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 MFR_PWM_MODE[2] = 1 (Sub-milli Ω DCR) RC = L/(5 • DCR) MFR_PWM_MODE[7]=0 MFR_PWM_MODE[7]=1 High Current Range VILIMIT (mV) Low Current Range VILIMIT (mV) 15.45 8.59 16.59 9.22 17.73 9.85 18.86 10.48 20.42 11.34 21.14 11.74 22.27 23.41 24.55 25.68 26.82 27.95 29.5 30.23 31.36 32.50 MFR_PWM_MODE[2] = 0 (Normal Value of DCR) RC = L/(DCR) MFR_PWM_MODE[7]=1 MFR_PWM_MODE[7]=0 High Current Range VILIMIT (mV) Low Current Range VILIMIT (mV) 38.64 21.46 41.48 23.04 44.32 24.62 47.16 26.20 51.04 28.36 52.84 29.36 12.37 13.01 13.64 14.27 14.90 15.53 16.5 16.79 17.42 18.06 55.68 58.52 61.36 64.20 67.05 69.89 74.5 75.57 78.41 81.25 30.93 32.51 34.09 35.67 37.25 38.83 41.38 41.98 43.56 45.14 Note: VILIMIT values used to calculate IOUT_OC_FAULT_LIMIT. Note: This is the peak of the current waveform. The READ_IOUT command returns the average current. The peak output current limits are adjusted with temperature based on the MFR_IOUT_CAL_GAIN_TC using the equation: Peak Current Limit = IOUT_CAL_GAIN • (1 + MFR_IOUT_CAL_GAIN_TC • (READ_TEMPERTURE_1-27.0)). The LTC7132 automatically converts currents to the appropriate internal bit value. The IOUT range is set with bit 7 of the MFR_PWM_MODE command. The IOUT_OC_FAULT_LIMIT is ignored during TON_RISE and TOFF_FALL. If the IOUT_OC_FAULT_LIMIT is exceeded, the device: • Sets the IOUT bit in the STATUS word • Sets the IOUT Overcurrent fault bit in the STATUS_IOUT • Notifies the host by asserting ALERT, unless masked This command has two data bytes and is formatted in Linear_5s_11s format. IOUT_OC_WARN_LIMIT This command sets the value of the output current measured by the ADC that causes an output overcurrent warning in Amperes. The READ_IOUT value will be used to determine if this limit has been exceeded. In response to the IOUT_OC_WARN_LIMIT being exceeded, the device: • Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE • Sets the IOUT bit in the STATUS_WORD • Sets the IOUT Overcurrent Warning bit in the STATUS_IOUT command, and Rev 0 For more information www.analog.com 81 LTC7132 PMBus COMMAND DETAILS • Notifies the host by asserting ALERT pin, unless masked The IOUT_OC_FAULT_LIMIT is ignored during TON_RISE and TOFF_FALL. This command has two data bytes and is formatted in Linear_5s_11s format Input Current and Limits COMMAND NAME MFR_IIN_CAL_GAIN CMD CODE DESCRIPTION 0xE8 The resistance value of the input current sense element in mΩ. TYPE R/W Word DATA FORMAT L11 UNITS mΩ DEFAULT VALUE 5.000 0xCA80 NVM Y MFR_IIN_CAL_GAIN The MFR_IIN_CAL_GAIN command is used to set the resistance value of the input current sense resistor in milliohms. (see also READ_IIN). This command has two data bytes and is formatted in Linear_5s_11s format. COMMAND NAME IIN_OC_WARN_LIMIT TYPE PAGED DATA FORMAT UNITS NVM R/W Word N L11 A Y CMD CODE DESCRIPTION 0x5D Input overcurrent warning limit. DEFAULT VALUE 10.0 0xD280 IIN_OC_WARN_LIMIT The IIN_OC_WARN_LIMIT command sets the value of the input current measured by the ADC, in amperes, that causes a warning indicating the input current is high. The READ_IIN value will be used to determine if this limit has been exceeded. In response to the IIN_OC_WARN_LIMIT being exceeded, the device: • Sets the OTHER bit in the STATUS_BYTE • Sets the INPUT bit in the upper byte of the STATUS_WORD • Sets the IIN Overcurrent Warning bit[1] in the STATUS_INPUT command, and • Notifies the host by asserting ALERT pin This command has two data bytes and is formatted in Linear_5s_11s format. TEMPERATURE External Temperature Calibration COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA DEFAULT FORMAT UNITS NVM VALUE MFR_TEMP_1_GAIN 0xF8 Sets the slope of the external temperature sensor. R/W Word Y CF MFR_TEMP_1_OFFSET 0xF9 Sets the offset of the external temperature sensor. R/W Word Y L11 82 C Y 1.0 0x4000 Y 0.0 0x8000 Rev 0 For more information www.analog.com LTC7132 PMBus COMMAND DETAILS MFR_TEMP_1_GAIN The MFR_TEMP_1_GAIN command will modify the slope of the external temperature sensor to account for non-idealities in the element and errors associated with the remote sensing of the temperature in the inductor. This command has two data bytes and is formatted in 16-bit 2’s complement integer. The effective gain adjustment is N • 2–14. The nominal value is 1. MFR_TEMP_1_OFFSET The MFR_TEMP_1_OFFSET command will modify the offset of the external temperature sensor to account for nonidealities in the element and errors associated with the remote sensing of the temperature in the inductor. This command has two data bytes and is formatted in Linear_5s_11s format. External Temperature Limits COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAULT VALUE OT_FAULT_LIMIT 0x4F External overtemperature fault limit. R/W Word Y L11 C Y 100.0 0xEB20 OT_WARN_LIMIT 0x51 External overtemperature warning limit. R/W Word Y L11 C Y 85.0 0xEAA8 UT_FAULT_LIMIT 0x53 External undertemperature fault limit. R/W Word Y L11 C Y –40.0 0xE580 OT_FAULT_LIMIT The OT_FAULT_LIMIT command sets the value of the external sense temperature measured by the ADC, in degrees Celsius, which causes an overtemperature fault. The READ_TEMPERATURE_1 value will be used to determine if this limit has been exceeded. This command has two data bytes and is formatted in Linear_5s_11s format. OT_WARN_LIMIT The OT_WARN_LIMIT command sets the value of the external sense temperature measured by the ADC, in degrees Celsius, which causes an overtemperature warning. The READ_TEMPERATURE_1 value will be used to determine if this limit has been exceeded. In response to the OT_WARN_LIMIT being exceeded, the device: • Sets the TEMPERATURE bit in the STATUS_BYTE • Sets the Overtemperature Warning bit in the STATUS_TEMPERATURE command, and • Notifies the host by asserting ALERT pin, unless masked This command has two data bytes and is formatted in Linear_5s_11s format. Rev 0 For more information www.analog.com 83 LTC7132 PMBus COMMAND DETAILS UT_FAULT_LIMIT The UT_FAULT_LIMIT command sets the value of the external sense temperature measured by the ADC, in degrees Celsius, which causes an undertemperature fault. The READ_TEMPERATURE_1 value will be used to determine if this limit has been exceeded. Note: If the temp sensors are not installed, the UT_FAULT_LIMIT can be set to –275°C and UT_FAULT_LIMIT response set to ignore to avoid ALERT being asserted. This command has two data bytes and is formatted in Linear_5s_11s format. TIMING Timing—On Sequence/Ramp COMMAND NAME TON_DELAY CMD CODE DESCRIPTION 0x60 Time from RUN and/or Operation on to output rail turn-on. TON_RISE 0x61 Time from when the output starts to rise until the output voltage reaches the VOUT commanded value. TON_MAX_FAULT_LIMIT 0x62 Maximum time from the start of TON_RISE for VOUT to cross the VOUT_UV_FAULT_LIMIT. VOUT_TRANSITION_RATE 0x27 Rate the output changes when VOUT commanded to a new value. TYPE PAGED R/W Word Y DATA FORMAT L11 UNITS ms NVM Y DEFAULT VALUE 0.0 0x8000 8.0 0xD200 R/W Word Y L11 ms Y R/W Word Y L11 ms Y 10.0 0xD280 R/W Word Y L11 V/ms Y 0.25 0xAA00 TON_DELAY The TON_DELAY command sets the time, in milliseconds, from when a start condition is received until the output voltage starts to rise. Values from 0ms to 83 seconds are valid. The resulting turn-on delay will have a typical delay of 270µs for TON_DELAY = 0 and an uncertainty of ±50µs for all values of TON_DELAY. This command has two data bytes and is formatted in Linear_5s_11s format. TON_RISE The TON_RISE command sets the time, in milliseconds, from the time the output starts to rise to the time the output enters the regulation band. Values from 0 to 1.3 seconds are valid. The part will be in discontinuous mode during TON_RISE events. If TON_RISE is less than 0.25ms, the LTC7132 digital slope will be bypassed and the output voltage transition will only be controlled by the analog performance of the PWM switcher. The number of steps in TON_RISE is equal to TON_RISE (in ms)/0.1ms with an uncertainty of ±0.1ms. This command has two data bytes and is formatted in Linear_5s_11s format. 84 Rev 0 For more information www.analog.com LTC7132 PMBus COMMAND DETAILS TON_MAX_FAULT_LIMIT The TON_MAX_FAULT_LIMIT command sets the value, in milliseconds, on how long the unit can attempt to power up the output without reaching the output undervoltage fault limit. A data value of 0ms means that there is no limit and that the unit can attempt to bring up the output voltage indefinitely. The maximum limit is 83 seconds. This command has two data bytes and is formatted in Linear_5s_11s format. VOUT_TRANSITION_RATE When a PMBus device receives either a VOUT_COMMAND or OPERATION (Margin High, Margin Low) that causes the output voltage to change, this command set the rate in V/ms at which the output voltage changes. The commanded rate of change does not apply when the unit is commanded on or off. The maximum allowed slope is 4V/ms. This command has two data bytes and is formatted in Linear_5s_11s format. Timing—Off Sequence/Ramp COMMAND NAME TOFF_DELAY TOFF_FALL TOFF_MAX_WARN_LIMIT CMD CODE DESCRIPTION TYPE 0x64 Time from RUN and/or Operation off to R/W Word the start of TOFF_FALL ramp. 0x65 Time from when the output starts to fall R/W Word until the output reaches zero volts. 0x66 Maximum allowed time, after TOFF_FALL R/W Word completed, for the unit to decay below 12.5%. PAGED Y DATA FORMAT L11 UNITS ms NVM Y Y L11 ms Y Y L11 ms Y DEFAULT VALUE 0.0 0x8000 8.0 0xD200 150 0xF258 TOFF_DELAY The TOFF_DELAY command sets the time, in milliseconds, from when a stop condition is received until the output voltage starts to fall. Values from 0 to 83 seconds are valid. The resulting turn off delay will have a typical delay of 270µs for TOFF_DELAY = 0 and an uncertainty of ±50µs for all values of TOFF_DELAY. TOFF_DELAY is not applied when a fault event occurs This command has two data bytes and is formatted in Linear_5s_11s format. TOFF_FALL The TOFF_FALL command sets the time, in milliseconds, from the end of the turn-off delay time until the output voltage is commanded to zero. It is the ramp time of the VOUT DAC. When the VOUT DAC is zero, the PWM output will be set to high impedance state. The part will maintain the mode of operation programmed. For defined TOFF_FALL times, the user should set the part to continuous conduction mode. Loading the max value indicates the part will ramp down at the slowest possible rate. The minimum supported fall time is 0.25ms. A value less than 0.25ms will result in a 0.25ms ramp. The maximum fall time is 1.3 seconds. The number of steps in TOFF_FALL is equal to TOFF_FALL (in ms)/0.1ms with an uncertainty of ±0.1ms. In discontinuous conduction mode, the controller will not draw current from the load and the fall time will be set by the output capacitance and load current. This command has two data bytes and is formatted in Linear_5s_11s format. Rev 0 For more information www.analog.com 85 LTC7132 PMBus COMMAND DETAILS TOFF_MAX_WARN_LIMIT The TOFF_MAX_WARN_LIMIT command sets the value, in milliseconds, on how long the output voltage exceeds 12.5% of the programmed voltage before a warning is asserted. The output is considered off when the VOUT voltage is less than 12.5% of the programmed VOUT_COMMAND value. The calculation begins after TOFF_FALL is complete. A data value of 0ms means that there is no limit and that the output voltage exceeds 12.5% of the programmed voltage indefinitely. Other than 0, values from 120ms to 524 seconds are valid. This command has two data bytes and is formatted in Linear_5s_11s format. Precondition for Restart COMMAND NAME CMD CODE DESCRIPTION MFR_RESTART_ DELAY 0xDC Minimum time the RUN pin is held low by the LTC7132. TYPE PAGED DATA FORMAT UNITS NVM R/W Word Y L11 ms Y DEFAULT VALUE 500 0xFBE8 MFR_RESTART_DELAY This command specifies the minimum RUN off time in milliseconds. This device will pull the RUN pin low for this length of time once a falling edge of RUN has been detected. The minimum recommended value is 136ms. Note: The restart delay is different than the retry delay. The restart delay pulls RUN low for the specified time, after which a standard start-up sequence is initiated. The minimum restart delay should be equal to TOFF_DELAY + TOFF_ FALL + 136ms. Valid values are from 136ms to 65.52 seconds in 16ms increments. To assure a minimum off time, set the MFR_RESTART_DELAY 16ms longer than the desired time. The output rail can be off longer than the MFR_ RESTART_DELAY after the RUN pin is pulled high if the output decay bit 0 is enabled in MFR_CHAN_CONFIG and the output takes a long time to decay below 12.5% of the programmed value. This command has two data bytes and is formatted in Linear_5s_11s format. FAULT RESPONSE Fault Responses All Faults COMMAND NAME MFR_RETRY_ DELAY CMD CODE DESCRIPTION 0xDB Retry interval during FAULT retry mode. TYPE PAGED DATA FORMAT UNITS NVM R/W Word Y L11 ms Y DEFAULT VALUE 350 0xFABC MFR_RETRY_DELAY This command sets the time in milliseconds between retries if the fault response is to retry the controller at specified intervals. This command value is used for all fault responses that require retry. The retry time starts once the fault has been detected by the offending channel. Valid values are from 120ms to 83.88 seconds in 10µs increments. Note: The retry delay time is determined by the longer of the MFR_RETRY_DELAY command or the time required for the regulated output to decay below 12.5% of the programmed value. If the natural decay time of the output is too long, it is possible to remove the voltage requirement of the MFR_RETRY_DELAY command by asserting bit 0 of MFR_CHAN_CONFIG. This command has two data bytes and is formatted in Linear_5s_11s format. 86 Rev 0 For more information www.analog.com LTC7132 PMBus COMMAND DETAILS Fault Responses Input Voltage COMMAND NAME VIN_OV_FAULT_RESPONSE CMD CODE DESCRIPTION 0x56 Action to be taken by the device when an input supply overvoltage fault is detected. TYPE R/W Byte DATA PAGED FORMAT Y UNITS Reg NVM DEFAULT VALUE Y 0x80 VIN_OV_FAULT_RESPONSE The VIN_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an input overvoltage fault. The data byte is in the format given in Table 11. The device also: • Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE • Set the INPUT bit in the upper byte of the STATUS_WORD • Sets the VIN Overvoltage Fault bit in the STATUS_INPUT command, and • Notifies the host by asserting ALERT pin, unless masked This command has one data byte. Fault Responses Output Voltage COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAULT VALUE VOUT_OV_FAULT_RESPONSE 0x41 Action to be taken by the device when an output overvoltage fault is detected. R/W Byte Y Reg Y 0xB8 VOUT_UV_FAULT_RESPONSE 0x45 Action to be taken by the device when an output undervoltage fault is detected. R/W Byte Y Reg Y 0xB8 TON_MAX_FAULT_ RESPONSE 0x63 Action to be taken by the device when a TON_MAX_FAULT event is detected. R/W Byte Y Reg Y 0xB8 VOUT_OV_FAULT_RESPONSE The VOUT_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an output overvoltage fault. The data byte is in the format given in Table 7. The device also: • Sets the VOUT_OV bit in the STATUS_BYTE • Sets the VOUT bit in the STATUS_WORD • Sets the VOUT Overvoltage Fault bit in the STATUS_VOUT command • Notifies the host by asserting ALERT pin, unless masked The only values recognized for this command are: 0x00–Part performs OV pull down only, or OV_PULLDOWN. 0x80–The device shuts down (disables the output) and the unit does not attempt to retry. (PMBus, Part II, Section 10.7). Rev 0 For more information www.analog.com 87 LTC7132 PMBus COMMAND DETAILS 0xB8–The device shuts down (disables the output) and device attempts to retry continuously, without limitation, until it is commanded OFF (by the RUN pin or OPERATION command or both), bias power is removed, or another fault condition causes the unit to shut down. 0x4n The device shuts down and the unit does not attempt to retry. The output remains disabled until the part is commanded OFF then ON or the RUN pin is asserted low then high or RESET through the command or removal of VIN. The OV fault must remain active for a period of n • 10µs, where n is a value from 0 to 7. 0x78+n The device shuts down and the unit attempts to retry continuously until either the fault condition is cleared or the part is commanded OFF then ON or the RUN pin is asserted low then high or RESET through the command or removal of VIN. The OV fault must remain active for a period of n • 10µs, where n is a value from 0 to 7. Any other value will result in a CML fault and the write will be ignored. This command has one data byte. Table 7. VOUT_OV_FAULT_RESPONSE Data Byte Contents BITS DESCRIPTION 7:6 Response VALUE MEANING 00 Part performs OV pull down only or OV_PULLDOWN (i.e., turns off the top MOSFET and turns on lower MOSFET while For all values of bits [7:6], the LTC7132: VOUT is > VOUT_OV_FAULT). • Sets the corresponding fault bit in the status commands and 01 The PMBus device continues operation for the delay time specified • Notifies the host by asserting ALERT pin, unless masked. by bits [2:0] and the delay time unit specified for that particular fault. If the fault condition is still present at the end of the delay The fault bit, once set, is cleared only when one or more of the time, the unit responds as programmed in the Retry Setting following events occurs: (bits [5:3]). • The device receives a CLEAR_FAULTS command. 10 The device shuts down immediately (disables the output) and • The output is commanded through the RUN pin, the OPERATION responds according to the retry setting in bits [5:3]. command, or the combined action of the RUN pin and 11 Not supported. Writing this value will generate a CML fault. OPERATION command, to turn off and then to turn back on, or 5:3 • Bias power is removed and reapplied to the LTC7132. Retry Setting 2:0 Delay Time 000 The unit does not attempt to restart. The output remains disabled until the fault is cleared until the device is commanded OFF bias power is removed. 111 The PMBus device attempts to restart continuously, without limitation, until it is commanded OFF (by the RUN pin or OPERATION command or both), bias power is removed, or another fault condition causes the unit to shut down without retry. Note: The retry interval is set by the MFR_RETRY_DELAY command. 000-111 The delay time in 10µs increments. This delay time determines how long the controller continues operating after a fault is detected. Only valid for deglitched off state. VOUT_UV_FAULT_RESPONSE The VOUT_UV_FAULT_RESPONSE command instructs the device on what action to take in response to an output undervoltage fault. The data byte is in the format given in Table 8. The device also: • Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE • Sets the VOUT bit in the STATUS_WORD • Sets the VOUT undervoltage fault bit in the STATUS_VOUT command • Notifies the host by asserting ALERT pin, unless masked 88 Rev 0 For more information www.analog.com LTC7132 PMBus COMMAND DETAILS The UV fault and warn are masked until the following criteria are achieved: 1) The TON_MAX_FAULT_LIMIT has been reached 2) The TON_DELAY sequence has completed 3) The TON_RISE sequence has completed 4) The VOUT_UV_FAULT_LIMIT threshold has been reached 5) The IOUT_OC_FAULT_LIMIT is not present The UV fault and warn are masked whenever the channel is not active. The UV fault and warn are masked during TON_RISE and TOFF_FALL sequencing. This command has one data byte. Table 8. VOUT_UV_FAULT_RESPONSE Data Byte Contents BITS 7:6 DESCRIPTION VALUE MEANING Response 00 The PMBus device continues operation without interruption. (Ignores the fault functionally) 01 The PMBus device continues operation for the delay time specified by bits [2:0] and the delay time unit specified for that particular fault. If the fault condition is still present at the end of the delay time, the unit responds as programmed in the Retry Setting (bits [5:3]). • The device receives a CLEAR_FAULTS command. 10 • The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin and OPERATION command, to turn off and then to turn back on, or The device shuts down (disables the output) and responds according to the retry setting in bits [5:3]. 11 Not supported. Writing this value will generate a CML fault. 000 The unit does not attempt to restart. The output remains disabled until the fault is cleared until the device is commanded OFF bias power is removed. 111 The PMBus device attempts to restart continuously, without limitation, until it is commanded OFF (by the RUN pin or OPERATION command or both), bias power is removed, or another fault condition causes the unit to shut down without retry. Note: The retry interval is set by the MFR_RETRY_DELAY command. 000111 The delay time in 10µs increments. This delay time determines how long the controller continues operating after a fault is detected. Only valid for deglitched off state. For all values of bits [7:6], the LTC7132: • Sets the corresponding fault bit in the status commands and • Notifies the host by asserting ALERT pin, unless masked. The fault bit, once set, is cleared only when one or more of the following events occurs: • The device receives a RESTORE_USER_ALL command. • The device receives a MFR_RESET command. • The device supply power is cycled. 5:3 2:0 Retry Setting Delay Time Rev 0 For more information www.analog.com 89 LTC7132 PMBus COMMAND DETAILS TON_MAX_FAULT_RESPONSE The TON_MAX_FAULT_RESPONSE command instructs the device on what action to take in response to a TON_MAX fault. The data byte is in the format given in Table 11. The device also: • Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE • Sets the VOUT bit in the STATUS_WORD • Sets the TON_MAX_FAULT bit in the STATUS_VOUT command, and • Notifies the host by asserting ALERT pin, unless masked A value of 0 disables the TON_MAX_FAULT_RESPONSE. It is not recommended to use 0. Note: The PWM channel remains in discontinues mode until the TON_MAX_FAULT_LIMIT has been exceeded. This command has one data byte. Fault Responses Output Current COMMAND NAME IOUT_OC_FAULT_RESPONSE CMD CODE DESCRIPTION 0x47 Action to be taken by the device when an output overcurrent fault is detected. TYPE PAGED DATA FORMAT R/W Byte Y Reg UNITS NVM DEFAULT VALUE Y 0x00 IOUT_OC_FAULT_RESPONSE The IOUT_OC_FAULT_RESPONSE command instructs the device on what action to take in response to an output overcurrent fault. The data byte is in the format given in Table 9. The device also: • Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE • Sets the IOUT_OC bit in the STATUS_BYTE • Sets the IOUT bit in the STATUS_WORD • Sets the IOUT Overcurrent Fault bit in the STATUS_IOUT command, and • Notifies the host by asserting ALERT pin, unless masked This command has one data byte. 90 Rev 0 For more information www.analog.com LTC7132 PMBus COMMAND DETAILS Table 9. IOUT_OC_FAULT_RESPONSE Data Byte Contents BITS 7:6 DESCRIPTION VALUE Response 00 The LTC7132 continues to operate indefinitely while maintaining the output current at the value set by IOUT_OC_FAULT_LIMIT without regard to the output voltage (known as constantcurrent or brick-wall limiting). 01 Not supported. 10 The LTC7132 continues to operate, maintaining the output current at the value set by IOUT_OC_FAULT_LIMIT without regard to the output voltage, for the delay time set by bits [2:0]. If the device is still operating in current limit at the end of the delay time, the device responds as programmed by the Retry Setting in bits [5:3]. 11 The LTC7132 shuts down immediately and responds as programmed by the Retry Setting in bits [5:3]. 000 The unit does not attempt to restart. The output remains disabled until the fault is cleared by cycling the RUN pin or removing bias power. 111 The device attempts to restart continuously, without limitation, until it is commanded OFF (by the RUN pin or OPERATION command or both), bias power is removed, or another fault condition causes the unit to shut down. Note: The retry interval is set by the MFR_RETRY_DELAY command. For all values of bits [7:6], the LTC7132: • Sets the corresponding fault bit in the status commands and • Notifies the host by asserting ALERT pin, unless masked. The fault bit, once set, is cleared only when one or more of the following events occurs: • The device receives a CLEAR_FAULTS command. • The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin and OPERATION command, to turn off and then to turn back on, or • The device receives a RESTORE_USER_ALL command. MEANING • The device receives a MFR_RESET command. • The device supply power is cycled. 5:3 2:0 Retry Setting Delay Time 000-111 The number of delay time units in 16ms increments. This delay time is used to determine the amount of time a unit is to continue operating after a fault is detected before shutting down. Only valid for deglitched off response. Fault Responses IC Temperature COMMAND NAME MFR_OT_FAULT_RESPONSE CMD CODE DESCRIPTION 0xD6 Action to be taken by the device when an internal overtemperature fault is detected. TYPE PAGED DATA FORMAT R Byte N Reg UNITS NVM DEFAULT VALUE 0xC0 MFR_OT_FAULT_RESPONSE The MFR_OT_FAULT_RESPONSE command byte instructs the device on what action to take in response to an internal overtemperature fault. The data byte is in the format given in Table 10. The LTC7132 also: • Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE • Sets the MFR bit in the STATUS_WORD, and • Sets the Overtemperature Fault bit in the STATUS_MFR_SPECIFIC command • Notifies the host by asserting ALERT pin, unless masked This command has one data byte. Rev 0 For more information www.analog.com 91 LTC7132 PMBus COMMAND DETAILS Table 10. Data Byte Contents MFR_OT_FAULT_RESPONSE BITS 7:6 DESCRIPTION VALUE MEANING Response 00 Not supported. Writing this value will generate a CML fault. For all values of bits [7:6], the LTC7132: 01 Not supported. Writing this value will generate a CML fault • Sets the corresponding fault bit in the status commands and 10 The device shuts down immediately (disables the output) and responds according to the retry setting in bits [5:3]. 11 The device’s output is disabled while the fault is present. Operation resumes and the output is enabled when the fault condition no longer exists. 000 The unit does not attempt to restart. The output remains disabled until the fault is cleared. • Notifies the host by asserting ALERT pin, unless masked. The fault bit, once set, is cleared only when one or more of the following events occurs: • The device receives a CLEAR_FAULTS command. • The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin and OPERATION command, to turn off and then to turn back on, or • Bias power is removed and reapplied to the LTC7132. 5:3 Retry Setting 001-111 Not supported. Writing this value will generate CML fault. 2:0 Delay Time XXX Not supported. Value ignored Fault Responses External Temperature COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAULT VALUE OT_FAULT_ RESPONSE 0x50 Action to be taken by the device when an external overtemperature fault is detected, R/W Byte Y Reg Y 0xB8 UT_FAULT_ RESPONSE 0x54 Action to be taken by the device when an external undertemperature fault is detected. R/W Byte Y Reg Y 0xB8 OT_FAULT_RESPONSE The OT_FAULT_RESPONSE command instructs the device on what action to take in response to an external overtemperature fault on the external temp sensors. The data byte is in the format given in Table 11. The device also: • Sets the TEMPERATURE bit in the STATUS_BYTE • Sets the Overtemperature Fault bit in the STATUS_TEMPERATURE command, and • Notifies the host by asserting ALERT pin, unless masked This command has one data byte. UT_FAULT_RESPONSE The UT_FAULT_RESPONSE command instructs the device on what action to take in response to an external undertemperature fault on the external temp sensors. The data byte is in the format given in Table 11. The device also: • Sets the TEMPERATURE bit in the STATUS_BYTE • Sets the Undertemperature Fault bit in the STATUS_TEMPERATURE command, and • Notifies the host by asserting ALERT pin, unless masked 92 Rev 0 For more information www.analog.com LTC7132 PMBus COMMAND DETAILS This condition is detected by the ADC so the response time may be up to tCONVERT. This command has one data byte. Table 11. Data Byte Contents: TON_MAX_FAULT_RESPONSE, VIN_OV_FAULT_RESPONSE, OT_FAULT_RESPONSE, UT_FAULT_RESPONSE BITS 7:6 DESCRIPTION VALUE MEANING Response 00 The PMBus device continues operation without interruption. For all values of bits [7:6], the LTC7132: 01 Not supported. Writing this value will generate a CML fault. • Sets the corresponding fault bit in the status commands, and 10 The device shuts down immediately (disables the output) and responds according to the retry setting in bits [5:3]. 11 Not supported. Writing this value will generate a CML fault. 000 The unit does not attempt to restart. The output remains disabled until the fault is cleared until the device is commanded OFF bias power is removed. 111 The PMBus device attempts to restart continuously, without limitation, until it is commanded OFF (by the RUN pin or OPERATION command or both), bias power is removed, or another fault condition causes the unit to shut down without retry. Note: The retry interval is set by the MFR_RETRY_DELAY command. XXX Not supported. Values ignored • Notifies the host by asserting ALERT pin, unless masked. The fault bit, once set, is cleared only when one or more of the following events occurs: • The device receives a CLEAR_FAULTS command. • The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin and OPERATION command, to turn off and then to turn back on, or • The device receives a RESTORE_USER_ALL command. • The device receives a MFR_RESET command. • The device supply power is cycled. 5:3 2:0 Retry Setting Delay Time FAULT SHARING Fault Sharing Propagation COMMAND NAME MFR_FAULT_ PROPAGATE CMD CODE 0xD2 DESCRIPTION Configuration that determines which faults are propagated to the FAULT pins. TYPE PAGED DATA FORMAT R/W Word Y Reg UNITS NVM DEFAULT VALUE Y 0x6993 MFR_FAULT_PROPAGATE The MFR_FAULT_PROPAGATE command enables the faults that can cause the FAULTn pin to assert low. The command is formatted as shown in Table 12. Faults can only be propagated to the FAULTn pin if they are programmed to respond to faults. This command has two data bytes. Rev 0 For more information www.analog.com 93 LTC7132 PMBus COMMAND DETAILS Table 12. FAULTn Propagate Fault Configuration The FAULT0 and FAULT1 pins are designed to provide electrical notification of selected events to the user. Some of these events are common to both output channels. Others are specific to an output channel. They can also be used to share faults between channels. BIT(S) B[15] SYMBOL VOUT disabled while not decayed. B[14] Mfr_fault_propagate_short_CMD_cycle OPERATION This is used in a PolyPhase configuration when bit 0 of the MFR_CHAN_CONFIG_LTC7132 is a zero. If the channel is turned off, by toggling the RUN pin or commanding the part OFF, and then the RUN is reasserted or the part is commanded back on before the output has decayed, VOUT will not restart until the 12.5% decay is honored. The FAULT pin is asserted during this condition if bit 15 is asserted. 0: No action Mfr_fault_propagate_ton_max_fault 1: Asserts low if commanded off then on before the output has sequenced off. Re-asserts high tOFF(MIN) after sequence off. 0: No action if a TON_MAX_FAULT fault is asserted b[13] 1: Associated output will be asserted low if a TON_MAX_FAULT fault is asserted FAULT0 is associated with page 0 TON_MAX_FAULT faults FAULT1 is associated with page 1 TON_MAX_FAULT faults b[12] b[11] Reserved Mfr_fault0_propagate_int_ot, b[10] b[9] b[8] Mfr_fault1_propagate_int_ot Reserved Reserved Mfr_fault0_propagate_ut, 0: No action if the UT_FAULT_LIMIT fault is asserted Mfr_fault1_propagate_ut 1: Associated output will be asserted low if the UT_FAULT_LIMIT fault is asserted 0: No action if the MFR_OT_FAULT_LIMIT fault is asserted 1: Associated output will be asserted low if the MFR_OT_FAULT_LIMIT fault is asserted FAULT0 is associated with page 0 UT faults b[7] Mfr_fault0_propagate_ot, FAULT1 is associated with page 1 UT faults 0: No action if the OT_FAULT_LIMIT fault is asserted Mfr_fault1_propagate_ot 1: Associated output will be asserted low if the OT_FAULT_LIMIT fault is asserted FAULT0 is associated with page 0 OT faults FAULT1 is associated with page 1 OT faults b[6] b[5] b[4] Reserved Reserved Mfr_fault0_propagate_input_ov, b[3] b[2] Mfr_fault1_propagate_input_ov Reserved Mfr_fault0_propagate_iout_oc, 0: No action if the IOUT_OC_FAULT_LIMIT fault is asserted Mfr_fault1_propagate_iout_oc 1: Associated output will be asserted low if the IOUT_OC_FAULT_LIMIT fault is asserted 0: No action if the VIN_OV_FAULT_LIMIT fault is asserted 1: Associated output will be asserted low if the VIN_OV_FAULT_LIMIT fault is asserted FAULT0 is associated with page 0 OC faults b[1] Mfr_fault0_propagate_vout_uv, FAULT1 is associated with page 1 OC faults 0: No action if the VOUT_UV_FAULT_LIMIT fault is asserted Mfr_fault1_propagate_vout_uv 1: Associated output will be asserted low if the VOUT_UV_FAULT_LIMIT fault is asserted FAULT0 is associated with page 0 UV faults b[0] Mfr_fault0_propagate_vout_ov, FAULT1 is associated with page 1 UV faults 0: No action if the VOUT_OV_FAULT_LIMIT fault is asserted Mfr_fault1_propagate_vout_ov 1: Associated output will be asserted low if the VOUT_OV_FAULT_LIMIT fault is asserted FAULT0 is associated with page 0 OV faults FAULT1 is associated with page 1 OV faults 94 Rev 0 For more information www.analog.com LTC7132 PMBus COMMAND DETAILS Fault Sharing Response COMMAND NAME CMD CODE DESCRIPTION MFR_FAULT_RESPONSE 0xD5 Action to be taken by the device when the FAULT pin is asserted low. TYPE R/W Byte PAGED Y DATA FORMAT Reg UNITS NVM Y DEFAULT VALUE 0xC0 MFR_FAULT_RESPONSE The MFR_FAULT_RESPONSE command instructs the device on what action to take in response to the FAULTn pin being pulled low by an external source. Supported Values: VALUE MEANING 0xC0 FAULT_INHIBIT The LTC7132 will three-state the output in response to the FAULT pin pulled low. 0x00 FAULT_IGNORE The LTC7132 continues operation without interruption. The device also: • Sets the MFR Bit in the STATUS_WORD. • Sets Bit 0 in the STATUS_MFR_SPECIFIC Command to Indicate FAULTn Is Being Pulled Low • Notifies the Host by Asserting ALERT, Unless Masked This command has one data byte. SCRATCHPAD COMMAND NAME USER_DATA_00 USER_DATA_01 USER_DATA_02 USER_DATA_03 USER_DATA_04 CMD CODE DESCRIPTION 0xB0 OEM reserved. Typically used for part serialization. 0xB1 Manufacturer reserved for LTpowerPlay. 0xB2 OEM reserved. Typically used for part serialization. 0xB3 A NVM word available for the user. 0xB4 A NVM word available for the user. TYPE R/W Word PAGED N DATA FORMAT Reg NVM Y DEFAULT VALUE NA R/W Word R/W Word Y N Reg Reg Y Y NA NA R/W Word R/W Word Y N Reg Reg Y Y 0x0000 0x0000 UNITS USER_DATA_00   through USER_DATA_04 These commands are non-volatile memory locations for customer storage. The customer has the option to write any value to the USER_DATA_nn at any time. However, the LTpowerPlay software and contract manufacturers use some of these commands for inventory control. Modifying the reserved USER_DATA_nn commands may lead to undesirable inventory control and incompatibility with these products. These commands have 2 data bytes and are in register format. Rev 0 For more information www.analog.com 95 LTC7132 PMBus COMMAND DETAILS IDENTIFICATION COMMAND NAME PMBus_REVISION CAPABILITY MFR_ID MFR_MODEL MFR_SPECIAL_ID CMD CODE DESCRIPTION 0x98 PMBus revision supported by this device. Current revision is 1.2. 0x19 Summary of PMBus optional communication protocols supported by this device. 0x99 The manufacturer ID of the LTC7132 in ASCII. 0x9A Manufacturer part number in ASCII. 0xE7 Manufacturer code representing the LTC7132. TYPE R Byte PAGED N DATA FORMAT Reg R Byte N Reg 0xB0 R String R String R Word N N N ASC ASC Reg LTC LTC7132 0x4C0X UNITS NVM FS DEFAULT VALUE 0x22 PMBus_REVISION The PMBUS_REVISION command indicates the revision of the PMBus to which the device is compliant. The LTC7132 is PMBus Version 1.2 compliant in both Part I and Part II. This read-only command has one data byte. CAPABILITY This command provides a way for a host system to determine some key capabilities of a PMBus device. The LTC7132 supports packet error checking, 400kHz bus speeds, and ALERT pin. This read-only command has one data byte. MFR_ID The MFR_ID command indicates the manufacturer ID of the LTC7132 using ASCII characters. This read-only command is in block format. MFR_MODEL The MFR_MODEL command indicates the manufacturer’s part number of the LTC7132 using ASCII characters. This read-only command is in block format. MFR_SPECIAL_ID The 16-bit word representing the part name and revision. 0x4C denotes the part is an LTC7132, XX is adjustable by the manufacturer. This read-only command has two data bytes. 96 Rev 0 For more information www.analog.com LTC7132 PMBus COMMAND DETAILS FAULT WARNING AND STATUS COMMAND NAME CLEAR_FAULTS SMBALERT_MASK CMD CODE DESCRIPTION 0x03 Clear any fault bits that have been set. 0x1B Mask activity. MFR_CLEAR_PEAKS STATUS_BYTE 0xE3 0x78 STATUS_WORD 0x79 STATUS_VOUT 0x7A STATUS_IOUT 0x7B STATUS_INPUT STATUS_ TEMPERATURE 0x7C 0x7D STATUS_CML 0x7E STATUS_MFR_ SPECIFIC 0x80 MFR_PADS MFR_COMMON 0xE5 0xEF TYPE Send Byte Block R/W Clears all peak values. Send Byte One byte summary of the unit’s fault R/W Byte condition. Two byte summary of the unit’s fault R/W Word condition. Output voltage fault and warning R/W Byte status. Output current fault and warning R/W Byte status. Input supply fault and warning status. R/W Byte External temperature fault and warning R/W Byte status for READ_TEMPERATURE_1. Communication and memory fault and R/W Byte warning status. Manufacturer specific fault and state R/W Byte information. Digital status of the I/O pads. R Word Manufacturer status bits that are R Byte common across multiple ADI chips. Y Y Reg DEFAULT VALUE NA See CMD Details NA NA Y Reg NA Y Reg NA Y Reg NA N Y Reg Reg NA NA N Reg NA Y Reg NA N N Reg Reg NA NA PAGED N Y FORMAT Reg UNITS NVM Y CLEAR_FAULTS The CLEAR_FAULTS command is used to clear any fault bits that have been set. This command clears all bits in all status commands simultaneously. At the same time, the device negates (clears, releases) its ALERT pin signal output if the device is asserting the ALERT pin signal. If the fault is still present when the bit is cleared, the fault bit will remain set and the host notified by asserting the ALERT pin low. CLEAR_FAULTS can take up to 10µs to process. If a fault occurs within that time frame it may be cleared before the status register is set. This write-only command has no data bytes. The CLEAR_FAULTS does not cause a unit that has latched off for a fault condition to restart. Units that have shut down for a fault condition are restarted when: • The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin and OPERATION command, to turn off and then to turn back on, or • MFR_RESET command is issued. • Bias power is removed and reapplied to the integrated circuit SMBALERT_MASK The SMBALERT_MASK command can be used to prevent a particular status bit or bits from asserting ALERT as they are asserted. Figure 52 shows an example of the Write Word format used to set an ALERT mask, in this case without PEC. The bits in the mask byte align with bits in the specified status register. For example, if the STATUS_TEMPERATURE command code is sent in the first data byte, and the mask byte contains 0x40, then a subsequent External Overtemperature Warning Rev 0 For more information www.analog.com 97 LTC7132 PMBus COMMAND DETAILS would still set bit 6 of STATUS_TEMPERATURE but not assert ALERT. All other supported STATUS_TEMPERATURE bits would continue to assert ALERT if set. Figure 53 shows an example of the Block Write – Block Read Process Call protocol used to read back the present state of any supported status register, again without PEC. SMBALERT_MASK cannot be applied to STATUS_BYTE, STATUS_WORD, MFR_COMMON or MFR_PADS_LTC7132. Factory default masking for applicable status registers is shown below. Providing an unsupported command code to SMBALERT_MASK will generate a CML for Invalid/Unsupported Data. SMBALERT_MASK Default Setting: (Refer Also to Figure 2) STATUS RESISTER ALERT Mask Value MASKED BITS STATUS_VOUT STATUS_IOUT STATUS_TEMPERATURE STATUS_CML STATUS_INPUT STATUS_MFR_SPECIFIC 0x00 0x00 0x00 0x00 0x00 0x11 None None None None None Bit 4 (internal PLL unlocked), bit 0 (FAULT pulled low by external device) 1 7 S SLAVE ADDRESS 1 1 W A SMBALERT_MASK A COMMAND CODE 8 1 8 8 1 1 MASK BYTE A P 1 STATUS_x A COMMAND CODE 7132 F53 Figure 52. Example of Writing SMBALERT_MASK 1 7 S SLAVE ADDRESS 1 1 W A SMBALERT_MASK A COMMAND CODE 1 7 Sr SLAVE ADDRESS 8 1 R 1 8 1 BLOCK COUNT (= 1) A 8 1 STATUS_x A COMMAND CODE 1 8 1 8 A BLOCK COUNT (= 1) A MASK BYTE 1 … 1 NA P 7132 F54 Figure 53. Example of Reading SMBALERT_MASK MFR_CLEAR_PEAKS The MFR_CLEAR_PEAKS command clears the MFR_*_PEAK data values. A MFR_RESET command will also clear the MFR_*_PEAK data values. This write-only command has no data bytes. STATUS_BYTE The STATUS_BYTE command returns one byte of information with a summary of the most critical faults. This is the lower byte of the status word. 98 Rev 0 For more information www.analog.com LTC7132 PMBus COMMAND DETAILS STATUS_BYTE Message Contents: BIT 7* 6 STATUS BIT NAME BUSY OFF 5 4 3 2 1 0* VOUT_OV IOUT_OC VIN_UV TEMPERATURE CML NONE OF THE ABOVE MEANING A fault was declared because the LTC7132 was unable to respond. This bit is set if the channel is not providing power to its output, regardless of the reason, including simply not being enabled. An output overvoltage fault has occurred. An output overcurrent fault has occurred. Not supported (LTC7132 returns 0). A temperature fault or warning has occurred. A communications, memory or logic fault has occurred. A fault Not listed in bits[7:1] has occurred. *ALERT can be asserted if either of these bits is set. They may be cleared by writing a 1 to their bit position in the STATUS_BYTE, in lieu of a CLEAR_ FAULTS command. This command has one data byte. STATUS_WORD The STATUS_WORD command returns a two-byte summary of the channel's fault condition. The low byte of the STATUS_WORD is the same as the STATUS_BYTE command. STATUS_WORD High Byte Message Contents: BIT STATUS BIT NAME MEANING 15 VOUT An output voltage fault or warning has occurred. 14 IOUT An output current fault or warning has occurred. 13 INPUT An input voltage fault or warning has occurred. 12 MFR_SPECIFIC A fault or warning specific to the LTC7132 has occurred. 11 POWER_GOOD# The POWER_GOOD state is false if this bit is set. 10 FANS Not supported (LTC7132 returns 0). 9 OTHER Not supported (LTC7132 returns 0). 8 UNKNOWN Not supported (LTC7132 returns 0). If any of the bits in the upper byte are set, NONE_OF_THE_ABOVE is asserted. This command has two data bytes. STATUS_VOUT The STATUS_VOUT command returns one byte of VOUT status information. STATUS_VOUT Message Contents: BIT 7 6 5 4 3 2 1 0 MEANING VOUT overvoltage fault. VOUT overvoltage warning. VOUT undervoltage warning. VOUT undervoltage fault. VOUT max warning. TON max fault. TOFF max fault. Not supported (LTC7132 returns 0). Rev 0 For more information www.analog.com 99 LTC7132 PMBus COMMAND DETAILS The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear status by means other than using the CLEAR_FAULTS command. Any supported fault bit in this command will initiate an ALERT event. This command has one data byte. STATUS_IOUT The STATUS_IOUT command returns one byte of IOUT status information. STATUS_IOUT Message Contents: BIT MEANING 7 IOUT overcurrent fault. 6 Not supported (LTC7132 returns 0). 5 IOUT overcurrent warning. 4:0 Not supported (LTC7132 returns 0). The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear status by means other than using the CLEAR_FAULTS command. Any supported fault bit in this command will initiate an ALERT event. This command has one data byte. STATUS_INPUT The STATUS_INPUT command returns one byte of VIN (VINSNS) status information. STATUS_INPUT Message Contents: BIT 7 6 5 4 3 2 1 0 MEANING VIN overvoltage fault. Not supported (LTC7132 returns 0). VIN undervoltage warning. Not supported (LTC7132 returns 0). Unit off for insufficient VIN. Not supported (LTC7132 returns 0). IIN overcurrent warning. Not supported (LTC7132 returns 0). The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear status by means other than using the CLEAR_FAULTS command. Any supported fault bit in this command will initiate an ALERT event. Bit 3 of this command is not latched and will not generate an ALERT even if it is set. This command has one data byte. 100 Rev 0 For more information www.analog.com LTC7132 PMBus COMMAND DETAILS STATUS_TEMPERATURE The STATUS_TEMPERATURE commands returns one byte with status information on temperature. This is a paged command and is related to the respective READ_TEMPERATURE_1 value. STATUS_TEMPERATURE Message Contents: BIT MEANING 7 External overtemperature fault. 6 External overtemperature warning. 5 Not supported (LTC7132 returns 0). 4 External undertemperature fault. 3:0 Not supported (LTC7132 returns 0). . The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear status by means other than using the CLEAR_FAULTS command. This command has one data byte. STATUS_CML The STATUS_CML command returns one byte of status information on received commands, internal memory and logic. STATUS_CML Message Contents: BIT MEANING 7 Invalid or unsupported command received. 6 Invalid or unsupported data received. 5 Packet error check failed. 4 Memory fault detected. 3 Processor fault detected. 2 Reserved (LTC7132 returns 0). 1 Other communication fault. 0 Other memory or logic fault. If either bit 3 or bit 4 of this command is set, a serious and significant internal error has been detected. Continued operation of the part is not recommended if these bits are continuously set. The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear status by means other than using the CLEAR_FAULTS command. Any supported fault bit in this command will initiate an ALERT event. This command has one data byte. Rev 0 For more information www.analog.com 101 LTC7132 PMBus COMMAND DETAILS STATUS_MFR_SPECIFIC The STATUS_MFR_SPECIFIC commands returns one byte with the manufacturer specific status information. The format for this byte is: BIT MEANING 7 Internal Temperature Fault Limit Exceeded. 6 Internal Temperature Warn Limit Exceeded. 5 Factory Trim Area NVM CRC Fault. 4 PLL is Unlocked 3 Fault Log Present 2 VDD33 UV or OV Fault 1 ShortCycle Event Detected 0 FAULT Pin Asserted Low by External Device If any of these bits are set, the MFR bit in the STATUS_WORD will be set, and ALERT may be asserted. The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear status by means other than using the CLEAR_FAULTS command. However, the fault log present bit can only be cleared by issuing the MFR_FAULT_LOG_CLEAR command. Any supported fault bit in this command will initiate an ALERT event. This command has one data byte. MFR_PADS This command provides the user a means of directly reading the digital status of the I/O pins of the device. The bit assignments of this command are as follows: BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ASSIGNED DIGITAL PIN VDD33 OV Fault VDD33 UV Fault Reserved Reserved ADC Values Invalid, Occurs During Start-Up. May Occur Briefly on Current Measurement Channels During Normal Operation SYNC clocked by external device (when LTC7132 configured to drive SYNC pin) Channel 1 Power Good Channel 0 Power Good LTC7132 Driving RUN1 Low LTC7132 Driving RUN0 Low RUN1 Pin State RUN0 Pin State LTC7132 Driving FAULT1 Low LTC7132 Driving FAULT0 Low FAULT1 Pin State FAULT0 Pin State A 1 indicates the condition is true. This read-only command has two data bytes. 102 Rev 0 For more information www.analog.com LTC7132 PMBus COMMAND DETAILS MFR_COMMON The MFR_COMMON command contains bits that are common to all ADI digital power and telemetry products. BIT MEANING 7 Chip Not Driving ALERT Low 6 LTC7132 Not Busy 5 Calculations Not Pending 4 LTC7132 Outputs Not in Transition 3 NVM Initialized 2 Reserved 1 SHARE_CLK Timeout 0 WP Pin Status This read-only command has one data byte. MFR_INFO The MFR_INFO command contains additional status bits that are LTC7132-specific and may be common to multiple ADI PSM products. MFR_INFO Data Contents: BIT MEANING 15:5 Reserved. 4 EEPROM ECC status. 0: Corrections made in the EEPROM user space. 1: No corrections made in the EEPROM user space. 3:0 Reserved EEPROM ECC status is updated after each RESTORE_USER_ALL or RESET command, a power-on reset or an EEPROM bulk read operation. This read-only command has two data bytes. Rev 0 For more information www.analog.com 103 LTC7132 PMBus COMMAND DETAILS TELEMETRY COMMAND NAME READ_VIN READ_IIN READ_VOUT READ_IOUT READ_TEMPERATURE_1 CMD CODE 0x88 0x89 0x8B 0x8C 0x8D READ_TEMPERATURE_2 0x8E READ_FREQUENCY READ_POUT READ_PIN MFR_PIN_ACCURACY MFR_IOUT_PEAK 0x95 0x96 0x97 0xAC 0xD7 MFR_VOUT_PEAK 0xDD MFR_VIN_PEAK 0xDE MFR_TEMPERATURE_1_PEAK 0xDF MFR_READ_IIN_PEAK 0xE1 MFR_READ_ICHIP MFR_TEMPERATURE_2_PEAK 0xE4 0xF4 MFR_ADC_CONTROL 0xD8 MFR_REAL_TIME 0xFB DESCRIPTION TYPE PAGED FORMAT UNITS Measured input supply voltage. R Word N L11 V Measured input supply current. R Word N L11 A Measured output voltage. R Word Y L16 V Measured output current. R Word Y L11 A External diode junction temperature. This R Word Y L11 C is the value used for all temperature related processing, including IOUT_CAL_GAIN. Internal junction temperature. Does not affect R Word N L11 C any other commands. Measured PWM switching frequency. R Word Y L11 Hz Calculated output power. R Word Y L11 W Calculated input power. R Word N L11 W Returns the accuracy of the READ_PIN command R Byte N % Report the maximum measured value of R Word Y L11 A READ_IOUT since last MFR_CLEAR_PEAKS. Maximum measured value of READ_VOUT R Word Y L16 V since last MFR_CLEAR_PEAKS. Maximum measured value of READ_VIN since R Word N L11 V last MFR_CLEAR_PEAKS. Maximum measured value of external R Word Y L11 C Temperature (READ_TEMPERATURE_1) since last MFR_CLEAR_PEAKS. Maximum measured value of READ_IIN R Word N L11 A command since last MFR_CLEAR_PEAKS. Measured current used by the LTC7132. R Word N L11 A R Word N L11 C Peak internal die temperature since last MFR_CLEAR_PEAKS. ADC telemetry parameter selected for repeated R/W Byte N N Reg fast ADC read back. 48-bit share-clock counter value R Block N CF NVM DEFAULT VALUE NA NA NA NA NA NA NA NA NA 5.0% NA NA NA NA NA NA NA NA NA READ_VIN The READ_VIN command returns the measured VIN pin voltage, in volts added to READ_ICHIP • MFR_RVIN. This compensates for the IR voltage drop across the VIN filter element due to the supply current of the LTC7132. This read-only command has two data bytes and is formatted in Linear_5s_11s format. READ_VOUT The READ_VOUT command returns the measured output voltage by the VOUT_MODE command. This read-only command has two data bytes and is formatted in Linear_16u format. READ_IIN The READ_IIN command returns the input current, in Amperes, as measured across the input current sense resistor (see also MFR_IIN_CAL_GAIN). This read-only command has two data bytes and is formatted in Linear_5s_11s format. 104 Rev 0 For more information www.analog.com LTC7132 PMBus COMMAND DETAILS READ_IOUT The READ_IOUT command returns the average output current in amperes. The IOUT value is a function of: a) the differential voltage measured across the ISENSE pins b) the IOUT_CAL_GAIN value c) the MFR_IOUT_CAL_GAIN_TC value, and d) READ_TEMPERATURE_1 value e) The MFR_TEMP_1_GAIN and the MFR_TEMP_1_OFFSET This read-only command has two data bytes and is formatted in Linear_5s_11s format. READ_TEMPERATURE_1 The READ_TEMPERATURE_1 command returns the temperature, in degrees Celsius, of the external sense element. This read-only command has two data bytes and is formatted in Linear_5s_11s format. READ_TEMPERATURE_2 The READ_TEMPERATURE_2 command returns the LTC7132’s die temperature, in degrees Celsius, of the internal sense element. This read-only command has two data bytes and is formatted in Linear_5s_11s format. READ_FREQUENCY The READ_FREQUENCY command is a reading of the PWM switching frequency in kHz. This read-only command has 2 data bytes and is formatted in Linear_5s_11s format. READ_POUT The READ_POUT command is a reading of the DC/DC converter output power in Watts. POUT is calculated based on the most recent correlated output voltage and current reading. This read-only command has 2 data bytes and is formatted in Linear_5s_11s format. READ_PIN The READ_PIN command is a reading of the DC/DC converter input power in Watts. PIN is calculated based on the most recent input voltage and current reading. This read-only command has 2 data bytes and is formatted in Linear_5s_11s format. MFR_PIN_ACCURACY The MFR_PIN_ACCURACY command returns the accuracy, in percent, of the value returned by the READ_PIN command. There is one data byte. The value is 0.1% per bit which gives a range of ±0.0% to ±25.5%. This read-only command has one data byte and is formatted as an unsigned integer. Rev 0 For more information www.analog.com 105 LTC7132 PMBus COMMAND DETAILS MFR_IOUT_PEAK The MFR_IOUT_PEAK command reports the highest current, in amperes, reported by the READ_IOUT measurement. This command is cleared using the MFR_CLEAR_PEAKS command. This read-only command has two data bytes and is formatted in Linear_5s_11s format. MFR_VOUT_PEAK The MFR_VOUT_PEAK command reports the highest voltage, in volts, reported by the READ_VOUT measurement. This command is cleared using the MFR_CLEAR_PEAKS command. This read-only command has two data bytes and is formatted in Linear_16u format. MFR_VIN_PEAK The MFR_VIN_PEAK command reports the highest voltage, in volts, reported by the READ_VIN measurement. This command is cleared using the MFR_CLEAR_PEAKS command. This read-only command has two data bytes and is formatted in Linear_5s_11s format. MFR_TEMPERATURE_1_PEAK The MFR_TEMPERATURE_1_PEAK command reports the highest temperature, in degrees Celsius, reported by the READ_TEMPERATURE_1 measurement. This command is cleared using the MFR_CLEAR_PEAKS command. This read-only command has two data bytes and is formatted in Linear_5s_11s format. MFR_READ_IIN_PEAK The MFR_READ_IIN_PEAK command reports the highest current, in Amperes, reported by the READ_IIN measurement. This command is cleared using the MFR_CLEAR_PEAKS command. This command has two data bytes and is formatted in Linear_5s_11s format. MFR_READ_ICHIP The MFR_READ_ICHIP command returns the measured input current, in Amperes, used by the LTC7132. This command has two data bytes and is formatted in Linear_5s_11s format. MFR_TEMPERATURE_2_PEAK The MFR_TEMPERATURE_2_PEAK command reports the highest temperature, in degrees Celsius, reported by the READ_TEMPERATURE_2 measurement. This command is cleared using the MFR_CLEAR_PEAKS command. This read-only command has two data bytes and is formatted in Linear_5s_11s format. MFR_ADC_CONTROL The MFR_ADC_CONTROL command determines the ADC read back selection. A default value of 0 in the command runs the standard telemetry loop with all parameters updated in a round robin fashion with a typical latency of tCONVERT. The user can command a non-zero value to monitored a single parameter with an approximate update rate of 8ms. 106 Rev 0 For more information www.analog.com LTC7132 PMBus COMMAND DETAILS This command has a latency of up to 2 ADC conversions or approximately 16ms (external temperature conversions may have a latency of up to 3 ADC conversion or approximately 24ms). It is recommended the part remain in standard telemetry mode except for special cases where fast ADC updates of a single parameter is required. The part should be commanded to monitor the desired parameter for a limited period of time (less then 1 second) then set the command back to standard round robin mode. If this command is set to any value except standard round robin telemetry (0) all warnings and faults associated with telemetry other than the selected parameter are effectively disabled and voltage servoing is disabled. When round robin is reasserted, all warnings and faults and servo mode are re-enabled. COMMANDED VALUE 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00 TELEMETRY COMMAND NAME READ_TEMPERATURE_1 READ_IOUT READ_VOUT READ_TEMPERATURE_1 READ_IOUT READ_VOUT READ_TEMPERATURE_2 READ_IIN MFR_READ_ICHIP READ_VIN DESCRIPTION Reserved Reserved Reserved Channel 1 external temperature Reserved Channel 1 measured output current Channel 1 measured output voltage Channel 0 external temperature Reserved Channel 0 measured output current Channel 0 measured output voltage Internal junction temperature Measured input supply current Measured supply current of the LTC7132 Measured input supply voltage Standard ADC Round Robin Telemetry If a reserved command value is entered, the telemetry will default to Internal IC Temperature and issue a CML fault. CML faults will continue to be issued by the LTC7132 until a valid command value is entered. The accuracy of the measured input supply voltage is only guaranteed if the MFR_ADC_CONTROL command is set to standard round robin telemetry. This write-only command has 1 data byte and is formatted in register format. MFR_REAL_TIME The MFR_REAL_TIME command is the real-time clock value of the device with a resolution of 200µs. The value is synchronous to the share-clock. The format of the PMBus block read is as follows: Format of the MFR_REAL_TIME BYTE 0 1 2 3 4 5 6 BIT [7:0] [15:8] [23:16] [31:24] [39:32] [47:40] DESCRIPTION Length of the block read (fixed at 6) LSB of the 48-bit real-time clock value MSB of the 48-bit real-time clock value This read-only command is in block format. The length will be 6. The value of this command is typically updated every 25ms. Rev 0 For more information www.analog.com 107 LTC7132 PMBus COMMAND DETAILS NVM MEMORY COMMANDS Store/Restore COMMAND NAME STORE_USER_ALL CMD CODE 0x15 RESTORE_USER_ALL 0x16 MFR_COMPARE_USER_ALL 0xF0 DESCRIPTION TYPE Store user operating memory to Send Byte EEPROM. Restore user operating memory from Send Byte EEPROM. Compares current command contents Send Byte with NVM. PAGED N FORMAT UNITS NVM DEFAULT VALUE NA N NA N NA STORE_USER_ALL The STORE_USER_ALL command instructs the PMBus device to copy the non-volatile user contents of the Operating Memory to the matching locations in the non-volatile User NVM memory. Executing this command if the die temperature exceeds 85°C or is below 0°C is not recommended and the data retention of 10 years cannot be guaranteed. If the die temperature exceeds 130°C, the STORE_USER_ALL command is disabled. The command is re-enabled when the IC temperature drops below 125°C. Communication with the LTC7132 and programming of the NVM can be initiated when EXTVCC or VDD33 is available and VIN is not applied. To enable the part in this state, using global address 0x5B write MFR_EE_UNLOCK to 0x2B followed by 0xC4. The LTC7132 will now communicate normally, and the project file can be updated. To write the updated project file to the NVM issue a STORE_USER_ALL command. When VIN is applied, a MFR_RESET must be issued to allow the PWM to be enabled and valid ADCs to be read. This write-only command has no data bytes. RESTORE_USER_ALL The RESTORE_USER_ALL command instructs the LTC7132 to copy the contents of the non-volatile User memory to the matching locations in the Operating Memory. The values in the Operating Memory are overwritten by the value retrieved from the User commands. The LTC7132 ensures both channels are off, loads the operating memory from the internal EEPROM, clears all faults, reads the resistor configuration pins, and then performs a soft-start of both PWM channels if applicable. STORE_USER_ALL, MFR_COMPARE_USER_ALL and RESTORE_USER_ALL commands are disabled if the die exceeds 130°C and are not re-enabled until the die temperature drops below 125°C. This write-only command has no data bytes. MFR_COMPARE_USER_ALL The MFR_COMPARE_USER_ALL command instructs the PMBus device to compare current command contents with what is stored in non-volatile memory. If the compare operation detects differences, a CML bit 0 fault will be generated. This write-only command has no data bytes. 108 Rev 0 For more information www.analog.com LTC7132 PMBus COMMAND DETAILS Fault Logging COMMAND NAME MFR_FAULT_LOG MFR_FAULT_LOG_ STORE MFR_FAULT_LOG_CLEAR CMD CODE DESCRIPTION 0xEE Fault log data bytes. 0xEA Command a transfer of the fault log from RAM to EEPROM. 0xEC Initialize the EEPROM block reserved for fault logging. DATA TYPE PAGED FORMAT UNITS R Block N CF Send Byte N Send Byte NVM Y DEFAULT VALUE NA NA N NA MFR_FAULT_LOG The MFR_FAULT_LOG command allows the user to read the contents of the FAULT_LOG after the first fault occurrence since the last MFR_FAULT_LOG_CLEAR command was written. The contents of this command are stored in non-volatile memory, and are cleared by the MFR_FAULT_LOG_CLEAR command. The length and content of this command are listed in Table 13. If the user accesses the MFR_FAULT_LOG command and no fault log is present, the command will return a data length of 0. If a fault log is present, the MFR_FAULT_LOG will return a block of data 147 bytes long. If a fault occurs within the first second of applying power, some of the earlier pages in the fault log may not contain valid data. NOTE: The approximate transfer time for this command is 3.4ms using a 400kHz clock. This read-only command is in block format. MFR_FAULT_LOG_STORE The MFR_FAULT_LOG_STORE command forces the fault log operation to be written to NVM just as if a fault event occurred. This command will set bit 3 of the STATUS_MFR_SPECIFIC fault if bit 7 “Enable Fault Logging” is set in the MFR_CONFIG_ALL command. If the die temperature exceeds 130°C, the MFR_FAULT_LOG_STORE command is disabled until the IC temperature drops below 125°C. This write-only command has no data bytes. Table 13. Fault Logging This table outlines the format of the block data from a read block data of the MFR_FAULT_LOG command. Data Format Definitions DATA Block Length LIN 11 = PMBus = Rev 1.2, Part 2, section 7.1 LIN 16 = PMBus Rev 1.2, Part 2, section 8. Mantissa portion only BYTE = 8 bits interpreted per definition of this command BITS DATA FORMAT BYTE BYTE NUM BLOCK READ COMMAND 147 The MFR_FAULT_LOG command is a fixed length of 147 bytes The block length will be zero if a data log event has not been captured HEADER INFORMATION Fault Log Preface Fault Source [7:0] [7:0] [15:8] [7:0] [7:0] ASC Reg Reg 0 1 2 3 4 Returns LTxx beginning at byte 0 if a partial or complete fault log exists. Word xx is a factory identifier that may vary part to part. Refer to Table 13a. Rev 0 For more information www.analog.com 109 LTC7132 PMBus COMMAND DETAILS MFR_REAL_TIME MFR_VOUT_PEAK (PAGE 0) [7:0] [15:8] [23:16] [31:24] [39:32] [47:40] [15:8] L16 5 6 7 8 9 10 11 MFR_VOUT_PEAK (PAGE 1) [7:0] [15:8] L16 12 13 MFR_IOUT_PEAK (PAGE 0) [7:0] [15:8] L11 14 15 MFR_IOUT_PEAK (PAGE 1) [7:0] [15:8] L11 16 17 MFR_VIN_PEAK READ_TEMPERATURE1 (PAGE 0) READ_TEMPERATURE1 (PAGE 1) READ_TEMPERATURE2 [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] Reg L11 L11 L11 L11 18 19 20 21 22 23 24 25 26 CYCLICAL DATA EVENT n READ_VOUT (PAGE 1) READ_IOUT (PAGE 0) READ_IOUT (PAGE 1) READ_VIN READ_IIN STATUS_VOUT (PAGE 0) STATUS_VOUT (PAGE 1) STATUS_WORD (PAGE 0) STATUS_WORD (PAGE 1) STATUS_MFR_SPECIFIC (PAGE 0) STATUS_MFR_SPECIFIC (PAGE 1) 110 [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] Peak READ_VOUT on Channel 0 since last power-on or CLEAR_PEAKS command. Peak READ_VOUT on Channel 1 since last power-on or CLEAR_PEAKS command. Peak READ_IOUT on Channel 0 since last power-on or CLEAR_PEAKS command. Peak READ_IOUT on Channel 1 since last power-on or CLEAR_PEAKS command. Peak READ_VIN since last power-on or CLEAR_PEAKS command. External temperature sensor 0 during last event. External temperature sensor 1 during last event. LTC7132 die temperature sensor during last event. Event “n” represents one complete cycle of ADC reads through the MUX at time of fault. Example: If the fault occurs when the ADC is processing step 15, it will continue to take readings through step 25 and then store the header and all 6 event pages to EEPROM (Data at Which Fault Occurred; Most Recent Data) READ_VOUT (PAGE 0) 48 bit share-clock counter value when fault occurred (200µs resolution). LIN 16 LIN 16 LIN 16 LIN 16 LIN 11 LIN 11 LIN 11 LIN 11 LIN 11 LIN 11 LIN 11 LIN 11 BYTE BYTE WORD WORD WORD WORD BYTE BYTE 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Rev 0 For more information www.analog.com LTC7132 PMBus COMMAND DETAILS EVENT n-1 (data measured before fault was detected) READ_VOUT (PAGE 0) [15:8] [7:0] READ_VOUT (PAGE 1) [15:8] [7:0] READ_IOUT (PAGE 0) [15:8] [7:0] READ_IOUT (PAGE 1) [15:8] [7:0] READ_VIN [15:8] [7:0] READ_IIN [15:8] [7:0] STATUS_VOUT (PAGE 0) STATUS_VOUT (PAGE 1) STATUS_WORD (PAGE 0) [15:8] [7:0] STATUS_WORD (PAGE 1) [15:8] [7:0] STATUS_MFR_SPECIFIC (PAGE 0) STATUS_MFR_SPECIFIC (PAGE 1) * * * EVENT n-5 (Oldest Recorded Data) READ_VOUT (PAGE 0) READ_VOUT (PAGE 1) READ_IOUT (PAGE 0) READ_IOUT (PAGE 1) READ_VIN READ_IIN STATUS_VOUT (PAGE 0) STATUS_VOUT (PAGE 1) STATUS_WORD (PAGE 0) STATUS_WORD (PAGE 1) STATUS_MFR_SPECIFIC (PAGE 0) STATUS_MFR_SPECIFIC (PAGE 1) [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] LIN 16 LIN 16 LIN 16 LIN 16 LIN 11 LIN 11 LIN 11 LIN 11 LIN 11 LIN 11 LIN 11 LIN 11 BYTE BYTE WORD WORD WORD WORD BYTE BYTE 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 LIN 16 LIN 16 LIN 16 LIN 16 LIN 11 LIN 11 LIN 11 LIN 11 LIN 11 LIN 11 LIN 11 LIN 11 BYTE BYTE WORD WORD WORD WORD BYTE BYTE 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 Rev 0 For more information www.analog.com 111 LTC7132 PMBus COMMAND DETAILS Table 13a. Explanation of Position_Fault Values POSITION_FAULT VALUE SOURCE OF FAULT LOG 0xFF MFR_FAULT_LOG_STORE 0x00 TON_MAX_FAULT 0x01 VOUT_OV_FAULT 0x02 VOUT_UV_FAULT 0x03 IOUT_OC_FAULT 0x05 TEMP_OT_FAULT 0x06 TEMP_UT_FAULT 0x07 VIN_OV_FAULT 0x0A MFR_TEMP_2_OT_FAULT MFR_FAULT_LOG_CLEAR The MFR_FAULT_LOG_CLEAR command will erase the fault log file stored values. It will also clear bit 3 in the STATUS_MFR_SPECIFIC command. After a clear is issued, the status can take up to 8ms to clear. This write-only command is send bytes. Block Memory Write/Read COMMAND NAME CMD CODE DESCRIPTION TYPE DATA PAGED FORMAT UNITS NVM DEFAULT VALUE MFR_EE_UNLOCK 0xBD Unlock user EEPROM for access by MFR_EE_ERASE and MFR_EE_DATA commands. R/W Byte N Reg NA MFR_EE_ERASE 0xBE Initialize user EEPROM for bulk programming by MFR_EE_DATA. R/W Byte N Reg NA MFR_EE_DATA 0xBF Data transferred to and from EEPROM using sequential PMBus word reads or writes. Supports bulk programming. R/W Word N Reg NA All the NVM commands are disabled if the die temperature exceeds 130°C. NVM commands are re-enabled when the die temperature drops below 125°C. MFR_EE_xxxx The MFR_EE_xxxx commands facilitate bulk programming of the LTC7132 internal EEPROM. Contact the factory for details. 112 Rev 0 For more information www.analog.com LTC7132 TYPICAL APPLICATIONS 1µF 1Ω 1% 2mΩ 10µF ×2 4.7µF D2 L0 0.51µH INTVCC SVIN PVIN0 0.1µF 4.99k DCR = 0.29mΩ 10k 10k 931Ω 1% 10k 10k 10k VDD33 10k 10k 10k 10k 10k 220nF VOUT0 0.9V/25A 100µF ×2 6.3V 330µF ×2 6.3V 10nF 150pF MMBT3906-AL3-R IIN+ BOOST0 IIN– PVIN1 BOOST1 SW0 SW1 SYNC LTC7132 PGOOD0 VIN 6V TO 14V 180µF 25V ×2 10µF ×2 D1 L1 0.51µH 0.1µF VDD25 DCR = 0.29mΩ 24.9k 24.9k VOUT0_CFG PGOOD1 5.76k SDA 20k ALERT VOUT1_CFG FAULT0 VDD25 11k FAULT1 SHARE_CLK RUN0 RUN1 WP FREQ_CFG ASEL1 ASEL0 PHASE_CFG EXTVCC ISENSE0+ ISENSE1+ ISENSE0– VSENSE0+ ISENSE1– VSENSE1+ VSENSE1– VSENSE0– TSNS1 TSNS0 ITH1 ITH0 ITHR1 ITHR0 2200pF VDD33 PGND GND VDD25 VDD33 750Ω 1% VDD25 SCL 2.2µF 24.9k 4.32k 4.32k 470nF 330µF ×2 6.3V VOUT1 100µF 1.2V/10A ×2 6.3V 10nF 150pF 2200pF VDD25 1µF MMBT3906-AL3-R 7132TA02 D1, D2: CMDSH3-TR L0: VITEC 59PR9874N L1: VITEC 59PR9876N High Efficiency, Ultralow DCR Sense Dual-Output 0.9V/25A and 1.2V/10A, 425 kHz Buck Converter Rev 0 For more information www.analog.com 113 114 For more information www.analog.com 330µF x2 6.3V MMBT3906-AL3-R 100µF x2 6.3V 931Ω 1% 220pF VDD33 10nF FP1007R3-R30-R DCR = 0.29mΩ L1 0.3µH 10µF x2 SDA SCL ALERT 10k 10k 10k INTVCC SCL SDA SYNC PGOOD0 PGOOD1 SW0 BOOST0 PVIN0 D2 10nF 220nF + VSENSE0+ VDD33 VDD33 VSENSE0– TSNS0 ITH0 ITHR0 ISENSE1– 2.2µF 1µF 10pF 5.76k 24.9k 0.1µF D1 10nF 220nF 5.76k 24.9k VDD25 L2 0.3µH 330µF x2 6.3V MMBT3906-AL3-R 931Ω 1% 100µF x2 6.3V L3 0.3µH 10µF x2 330µF x2 6.3V 10nF FP1007R3-R30-R DCR = 0.29mΩ MMBT3906-AL3-R VOUT 1.0V/80A 100µF x2 6.3V 180µF 25V x2 1Ω 1% FP1007R3-R30-R DCR = 0.29mΩ C3 1µF SYNC 10pF INTVCC VDD33 VSENSE0– TSNS0 ITH0 ITHR0 VSENSE0+ ISENSE0– ISENSE0+ WP SW1 BOOST1 PVIN1 IIN– VDD25_1 1µF 1.96k 30.1k 0.1µF D3 10pF 220nF 5.76k 24.9k 5.76k 24.9k 10µF x2 2mΩ D1, D2, D3, D4: CMDSH3-TR PGND SGND VDD25 VSENSE1– TSNS1 ITH1 ITHR1 VSENSE1 + ISENSE1– ISENSE1+ PHASE_CFG FREQ_CFG ASEL1 ASEL0 VOUT0_CFG VOUT1_CFG IIN+ U1 LTC7132 SVIN 2.2µF SHARE_CLK RUN0 RUN1 ALERT FAULT0 FAULT1 SCL SDA SYNC PGOOD0 PGOOD1 SW0 BOOST0 PVIN0 D4 VDD33_1 220nF RUN SHARE_CLK FAULT ALERT SCL SDA PGOOD 931Ω 1% 0.1µF 4.7µF High Efficiency, 500kHz, 4-Phase Single-Output, 1.0V/80A Buck Converter VDD25 PGND SGND VDD25 VSENSE1– TSNS1 ITH1 ITHR1 VSENSE1 ISENSE1+ PHASE_CFG FREQ_CFG ASEL0 ASEL1 VOUT0_CFG VOUT1_CFG SW1 BOOST1 PVIN1 IIN– ISENSE0+ U0 LTC7132 SVIN IIN+ ISENSE0– WP ALERT FAULT0 10k FAULT FAULT1 10k SHARE_CLK SHARE_CLK RUN0 10k RUN RUN1 PGOOD 10k 4.99k SYNC 0.1µF 4.7µF 10µF x2 2mΩ 10nF 11k 20k 931Ω 1% 7132 TA03 100µF x2 6.3V VIN 6V TO 14V 330µF x2 6.3V MMBT3906-AL3-R VDD25_1 L4 0.3µH 180µF 25V x2 1Ω 1% FP1007R3-R30-R DCR = 0.29mΩ C3 1µF LTC7132 TYPICAL APPLICATIONS Rev 0 LTC7132 TYPICAL APPLICATIONS 1Ω 1% 1µF 2mΩ 10µF ×2 4.7µF L1 1µH 10µF ×2 D2 INTVCC SVIN PVIN0 0.1µF 4.99k XAL1010-102ME DCR = 1mΩ 10k 909Ω 1% 10k 10k 10k VDD33 10k 10k 10k 10k 10k 10k 220nF VOUT0 2.5V/15A 330µF ×2 6.3V 100µF ×2 6.3V 10nF 150pF MMBT3906-AL3-R IIN+ BOOST0 D1 IIN– PVIN1 BOOST1 SW0 SYNC 16.2k PGOOD1 SDA 16.2k 30.1k VOUT0_CFG VOUT1_CFG ASEL1 SCL ALERT 909Ω 1% 20.5k FAULT0 17.4k 1.96k ASEL0 FAULT1 SHARE_CLK FREQ_CFG RUN0 PHASE_CFG RUN1 WP EXTVCC ISENSE0+ ISENSE1+ ISENSE0– VSENSE0+ ISENSE1– VSENSE1+ 350kHz VSENSE1– VSENSE0– TSNS1 TSNS0 ITH1 ITH0 ITHR1 ITHR0 1500pF VDD33 PGND SGND VDD25 VDD33 XAL1010-102ME DCR = 1mΩ VDD25 LTC7132 VIN 7V TO 14V L2 1µH 0.1µF SW1 PGOOD0 180µF ×2 25V 2mΩ 2.2µF 220nF 100µF ×2 6.3V VOUT1 330µF 1.8V/15A ×2 6.3V 10nF 150pF 1500pF VDD25 1µF MMBT3906-AL3-R 7132TA04 D1, D2, D3, D4: CMDSH3-TR High Efficiency, 350kHz, Dual-Output, 2.5V/15A and 1.8V/15A Buck Converter Rev 0 For more information www.analog.com 115 LTC7132 TYPICAL APPLICATIONS C3 1µF 2mΩ 10µF ×2 10µF ×2 4.7µF D2 L1 1.5µH INTVCC SVIN PVIN0 0.1µF 4.99k XAL1010-152ME DCR = 1.6mΩ 10k 4.32k 1% 10k 10k VDD33 10k 10k 10k 10k IIN+ BOOST0 IIN– PVIN1 SW0 SW1 SYNC PGOOD0 PGOOD1 VOUT0_CFG SDA VOUT1_CFG SCL FREQ_CFG 10k VIN 10V TO 14V L2 1.5µH 0.1µF XAL1010-152ME DCR = 1.6mΩ VDD25 LTC7132 ALERT 180µF ×2 25V 2mΩ D1 BOOST1 1Ω 1% 30.1k 24.9k 4.32k 1% ASEL1 23.2k FAULT0 FAULT1 1.96k 4.32k ASEL0 SHARE_CLK RUN0 PHASE_CFG EXTVCC 5.5V RUN1 WP 220nF 330µF ×2 6.3V 100µF ×2 6.3V 10nF 330pF MMBT3906-AL3-R 3.3nF ISENSE0+ ISENSE1+ ISENSE0– VSENSE0+ ISENSE1– VSENSE1+ VSENSE1– VSENSE0– TSNS1 TSNS0 ITH1 ITH0 ITHR1 ITHR0 VDD33 PGND SGND VDD25 VDD33 2.2µF VOUT1 5.0V/30A 220nF 100µF ×2 6.3V 330µF ×2 6.3V 10nF MMBT3906-AL3-R VDD25 1µF 7132TA05 High Efficiency, Typical DCR Current Sense, 250kHz, Dual Phase Single-Output, 5V/30A Buck Converter 116 Rev 0 For more information www.analog.com 2.000 2.000 SUGGESTED PCB LAYOUT TOP VIEW 1.200 X D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No licenseFor is granted implication or otherwise under any patent or patent rights of Analog Devices. more by information www.analog.com 5.200 4.400 3.600 2.800 2.000 1.200 0.400 0.400 1.200 2.000 2.800 3.600 4.400 5.200 Y 0.000 aaa Z NOM 2.22 0.40 1.82 0.50 0.40 11.25 9.0 0.80 10.40 7.2 0.32 1.50 MAX 2.42 0.50 1.92 0.55 0.43 DIMENSIONS BALL DIMENSION PAD DIMENSION BALL HT NOTES DETAIL B PACKAGE SIDE VIEW A2 A SUBSTRATE THK 0.37 MOLD CAP HT 1.55 0.15 0.10 0.20 0.15 0.08 TOTAL NUMBER OF BALLS: 140 0.27 1.45 MIN 2.02 0.30 1.72 0.45 0.37 H1 SUBSTRATE ddd M Z X Y eee M Z DETAIL A Øb (140 PLACES) SYMBOL A A1 A2 b b1 D E e F G H1 H2 aaa bbb ccc ddd eee b1 DETAIL B H2 MOLD CAP ccc Z A1 Z (Reference LTC DWG # 05-08-1569 Rev Ø) Z aaa Z 0.4 Ø 140x 0.000 PACKAGE TOP VIEW 0.400 4 0.400 PIN “A1” CORNER 2.800 E 1.200 // bbb Z BGA Package 140-Lead (11.25mm × 9.00mm × 2.22mm) e 10 9 7 6 5 4 3 PACKAGE BOTTOM VIEW 8 b G 2 1 DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE BALL DESIGNATION PER JEP95 P N M L K J H G F E D C B A TRAY PIN 1 BEVEL COMPONENT PIN “A1” 7 ! PACKAGE IN TRAY LOADING ORIENTATION LTMXXXX µModule PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY 7 DETAIL A PIN 1 SEE NOTES BGA 140 0117 REV Ø 6. SOLDER BALL COMPOSITION CAN BE 96.5% Sn/3.0% Ag/0.5% Cu OR Sn Pb EUTECTIC 5. PRIMARY DATUM -Z- IS SEATING PLANE 4 3 2. ALL DIMENSIONS ARE IN MILLIMETERS NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 3 SEE NOTES F b e LTC7132 PACKAGE DESCRIPTION Rev 0 117 3.600 2.800 3.600 LTC7132 TYPICAL APPLICATION Low DCR Sensing, 425kHz, Dual Phase Single-Output, 1V/40A Buck Converter C3 1µF 2mΩ 10µF ×2 4.7µF D2 L1 0.3µH INTVCC SVIN PVIN0 0.1µF 4.99k PA3288.301HL DCR = 0.29mΩ BOOST1 SW0 SW1 PGOOD0 10k 10k 10k 10k VOUT0_CFG SDA VOUT1_CFG SCL FREQ_CFG ALERT 10k D1 180µF ×2 25V PHASE_CFG FAULT0 EXTVCC FAULT1 ASEL0 SHARE_CLK ASEL1 VIN 6V TO 14V L2 0.3µH 0.1µF PA3288.301HL DCR = 0.29mΩ VDD25 LTC7132 PGOOD1 10k VDD33 BOOST0 IIN– PVIN1 SYNC 10k 931Ω 1% IIN+ 10µF ×2 1Ω 1% 24.9k 24.9k 30.1k 7.32k 4.32k 1.96k 931Ω 1% RUN0 RUN1 WP 220nF 330µF ×2 6.3V 100µF ×2 6.3V 10nF 220pF MMBT3906-AL3-R 4.7nF ISENSE0+ ISENSE1+ ISENSE0– VSENSE0+ ISENSE1– VSENSE1+ VSENSE1– VSENSE0– TSNS1 TSNS0 ITH1 ITH0 ITHR1 ITHR0 VDD33 PGND SGND VDD25 VDD33 2.2µF 220nF VOUT 1V/40A 100µF ×2 6.3V 330µF ×2 6.3V 10nF 10pF MMBT3906-AL3-R VDD25 1µF 7132 TA07 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTM4676A Dual 13A or Single 26A Step-Down DC/DC µModule Regulator with Digital Power System Management 4.5V ≤ VIN ≤17V; 0.5V ≤ VOUT (±0.5%) ≤ 5.5V, I2C/PMBus Interface, 16mm × 16mm × 5mm, BGA Package LTM4675 Dual 9A or Single 18A μModule Regulator with Digital Power System Management 4.5V ≤ VIN ≤17V; 0.5V ≤ VOUT (±0.5%) ≤ 5.5V, I2C/PMBus Interface, 11.9mm × 16mm × 5mm, BGA Package LTM4677 Dual 18A or Single 36A µModule Regulator with Digital Power System Management 4.5V ≤ VIN ≤ 16V; 0.5V ≤ VOUT (±0.5%) ≤ 1.8V, I2C/PMBus Interface, 16mm × 16mm × 5.01mm, BGA Package LTC3874 Multiphase Step-Down Synchronous Slave Controller with Sub MilliOhm DCR Sensing 4.5V ≤ VIN ≤ 38V, VOUT up to 5.5V, Very High Output Current, Accurate Current Sharing, Current Mode Applications LTC3887/ LTC3887-1 Dual Output Multiphase Step-Down DC/DC Controller with Digital Power System Management, 70mS Start-Up 4.5V ≤ VIN ≤ 24V, 0.5V ≤ VOUT0,1 (±0.5%) ≤ 5.5V, 70mS Start-Up, I2C/ PMBus Interface, –1 Version uses DrMOS or Power Blocks LTC3882/ LTC3882-1 Dual Output Multiphase Step-Down DC/DC Voltage Mode Controller with Digital Power System Management 3V ≤ VIN ≤ 38V, 0.5V ≤ VOUT1,2 ≤ 5.25V, (±0.5%) VOUT Accuracy I2C/ PMBus Interface, uses DrMOS or Power Blocks LTC3886 60V Dual Output Step-Down Controller with Digital Power System Management 4.5V ≤ VIN ≤ 60V, 0.5V ≤ VOUT0,1 (±0.5%) ≤ 13.8V, 70mS Start-Up, I2C/ PMBus Interface, Input Current Sense LTC3815 6A Monolithic Synchronous DC/DC Step-Down Converter with Digital Power System Management 2.25V ≤ VIN ≤ 5.5V, 0.4V ≤ VOUT ≤ 0.72VIN, Programmable VOUT Range ±25% with 0.1% Resolution, Up to 3MHz Operation with 13-Bit ADC Licensed under U.S. Patent 7000125 and other related patents worldwide. 118 Rev 0 9/20 www.analog.com For more information www.analog.com  ANALOG DEVICES, INC. 2019