LTC7840
2-Phase Dual Output
Nonsynchronous Boost Controller
with Hiccup Mode
DESCRIPTION
FEATURES
Wide VIN Range: 5.5V to 60V
nn Configurable for Dual Phase Single/Dual Output
Operation
nn Peak Current Mode Control with Smooth Quadratic
Slope Compensation and Dynamic Slope Recovery
nn Adjustable Max Duty Cycle
nn Adjustable Min On-Time
nn Hiccup Mode for Overcurrent Protection
nn Adjustable Current Sense Limit
nn Output Overvoltage Protection
nn Programmable and Phase-Lockable Operating
Frequency (from 50kHz to 425kHz)
nn Adjustable Soft-Start Current Ramping
nn ±1% Internal Voltage Reference
nn Internal 10V LDO Regulator for Gate Driver
nn Two RUN Pins and Dual Power Good Monitors
nn Flexible Topology for Boost, SEPIC and Flyback
nn
APPLICATIONS
nn
Automotive System, Telecom System and Industrial
Power Supplies
The LTC®7840 is a dual phase dual output, constant frequency current mode, nonsynchronous boost controller
that drives N-channel power MOSFETs. The nonsynchronous topology makes the output voltage dependent on
the choice of external components.
A wide 5.5V to 60V input supply range can accommodate
high input voltage surges. The LTC7840 can be configured as a dual phase single output or dual output controller. It can be also configured for the SEPIC and flyback
topologies. The switching frequency is programmed by
the voltage on the FREQ pin or synchronized to an external
clock. The LTC7840 features a precise 1.2V internal reference. It has two RUN pins and two power good output
indicators.
The LTC7840 has an internal 10V LDO with undervoltage
lockout protection for its on-chip gate driver. The maximum duty cycle and blanking time can be programmed
by the voltage on DMAX and BLANK pins, respectively. The
hiccup mode protects the system in the event of faults.
The LTC7840 is available in a 28-lead thermally enhanced
TSSOP package (FE28) or a 28-lead QFN package (UFD28).
All registered trademarks and trademarks are the property of their respective owners.
TYPICAL APPLICATION
475k
12.1k
10µH
33µF
63V 12.1k
73.2k
0.1µF
100pF
33nF
15k
2.2µF
RUN1
VIN
BLANK
DMAX
ITH1
SS2
GATE1
66µF
80V
SENSE1+
VFB1
FREQ
SS1
ILIM1
2mΩ
SENSE1–
INTVCC
SGND
LTC7840
DRVCC
PGND
1nF
ITH2
46.4k
VFB2
11.8k
ILIM2
VEfficiency
OUT = 240V
92
PINS NOT SHOWN:
CLKOUT,
SYNC,
PGOOD2
100µH
VOUT
240V
0.7A
10µF
200µF
400V
SENSE2+
Efficiency vs Output Current
vs Output Current
94
GATE2
100pF
47nF
VOUT1
48V
84.5k
90
88
EFFICIENCY (%)
VIN
12V
86
84
82
80
78
76
72
70
8mΩ
RUN2 PGOOD1 SENSE2–
VIN = 24V
VIN = 12V
VIN = 9V
74
0
0.2
0.4
0.6
0.8
IOUT (A)
1.0
1.2
7840 TA01b
2.37M
7840 TA01a
Rev 0
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1
LTC7840
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Input Supply Voltage (VIN).......................... –0.3V to 65V
RUN1, RUN2 Voltage..................................... –0.3V to 6V
SENSE1+, SENSE2+ Voltage.................... –0.3V to INTVCC
DMAX, BLANK Voltage............................ –0.3V to INTVCC
PGOOD1, PGOOD2 Voltage........................... –0.3V to 6V
VFB1, VFB2 Voltage............................... –0.3V to INTVCC
SS1, SS2 Voltage................................... –0.3V to INTVCC
ITH1, ITH2 Voltage................................. –0.3V to INTVCC
ILIM1, ILIM2 Voltage.............................. –0.3V to INTVCC
FREQ, SYNC Voltage.............................. –0.3V to INTVCC
DRVCC Peak Output Current .................................100mA
Operating Junction Temperature Range (Note 3)
LTC7840E........................................... –40°C to 125°C
LTC7840I............................................ –40°C to 125°C
LTC7840H........................................... –40°C to 150°C
Storage Temperature Range................... –65°C to 150°C
Reflow Peak Body Temperature............................. 260°C
PIN CONFIGURATION
TOP VIEW
SYNC
3
26 ILIM1
DMAX
4
25 INTVCC
DMAX 1
22 INTVCC
FREQ
5
24 SGND
FREQ 2
21 SGND
SS1
6
23 VIN
VFB1
7
22 DRVCC
VFB1 4
ITH1
8
21 GATE1
ITH1 5
20 PGND
RUN1 6
19 GATE2
RUN2 7
ITH2 13
16 ILIM2
SENSE2+ 14
16 GATE2
SS2 8
15 PGOOD1
9 10 11 12 13 14
15 SENSE2–
FE PACKAGE
28-LEAD PLASTIC TSSOP
TJMAX = 150°C, θJA = 30°C/W
EXPOSED PAD (PIN 29) IS SGND, MUST BE SOLDERED TO PCB
PGOOD2
17 PGOOD2
18 GATE1
ILIM2
18 PGOOD1
19 DRVCC
17 PGND
SENSE2–
SS2 11
VFB2 12
20 VIN
29
SGND
SENSE2+
RUN2 10
SS1 3
ITH2
9
29
SGND
28 27 26 25 24 23
VFB2
RUN1
2
ILIM1
27 SENSE1–
SENSE1–
2
SENSE1+
CLKOUT
BLANK
28 SENSE1+
CLKOUT
1
SYNC
TOP VIEW
BLANK
UFD PACKAGE
28-LEAD (4mm × 5mm) PLASTIC QFN
TJMAX = 150°C, θJA = 47°C/W
EXPOSED PAD (PIN 29) IS SGND, MUST BE SOLDERED TO PCB
Rev 0
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LTC7840
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC7840EFE#PBF
LTC7840EFE#TRPBF
LTC7840 FE
28-Lead Plastic TSSOP
–40°C to 125°C
LTC7840IFE#PBF
LTC7840IFE#TRPBF
LTC7840 FE
28-Lead Plastic TSSOP
–40°C to 125°C
LTC7840HFE#PBF
LTC7840HFE#TRPBF
LTC7840 FE
28-Lead Plastic TSSOP
–40°C to 150°C
LTC7840EUFD#PBF
LTC7840EUFD#TRPBF
7840
28-Lead Plastic (4mm × 5mm) QFN
–40°C to 125°C
LTC7840IUFD#PBF
LTC7840IUFD#TRPBF
7840
28-Lead Plastic (4mm × 5mm) QFN
–40°C to 125°C
LTC7840HUFD#PBF
LTC7840HUFD#TRPBF
7840
28-Lead Plastic (4mm × 5mm) QFN
–40°C to 150°C
Consult ADI Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
Rev 0
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3
LTC7840
ELECTRICAL CHARACTERISTICS
(Notes 2, 3) The l denotes the specifications which apply over the specified
operating junction temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VRUN = 2V and SS1,2 = open, unless
otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Main Control Loops
VIN
Input Voltage Range
5.5
IQ
Input DC Supply Current
Normal Operation
Shutdown
(Note 5)
VIN = 12V, VRUN = 2V, No Switching
VRUN = 0V
3
40
UVLO_DRVCC
DRVCC Undervoltage Lockout Threshold
DRVCC Rising
DRVCC Falling
4.4
3.9
V
V
UVLO_INTVCC
INTVCC Undervoltage Lockout Threshold
INTVCC Rising
INTVCC Falling
3.3
3
V
V
VFB1, VFB2
Regulated Feedback Voltage
ITH1,2 Voltage = 1V (Note 6)
l
1.188
5
80
mA
µA
1.212
V
±50
nA
Feedback Current
(Note 6)
±5
DMAX
Maximum Duty Cycle
VDMAX = 0V (Note 8)
VDMAX = Float
VDMAX = INTVCC
96
84
75
VOVL
Feedback Overvoltage Lockout
Measured at VFB1, VFB2
VREFLNREG
Reference Voltage Line Regulation
VIN = 5.5V to 60V (Note 6)
VLOADREG
Output Voltage Load Regulation
(Note 6)
In Servo Loop; ∆ITH Voltage = 1V to 0.7V
In Servo Loop; ∆ITH Voltage = 1V to 1.3V
l
l
V
1.2
IFB1, IFB2
8.5
60
%
%
%
10.5
12.5
%
0.002
0.01
%/V
0.01
–0.01
0.1
–0.1
%
%
gm1, gm2
EA Transconductance
ITH1,2 Voltage = 1V; Sink/Source 5µA (Note 6)
ILIM1, ILIM2
Current Limit Setting Current
IILIM1,2 Voltage = 0.3V
VITH1,
VITH2(PSKIP)
Pulse Skip Mode ITH Voltage
ITH Voltage Rising (Note 6)
Hysteresis
ISS1,2
Soft Start Charge Current
VTK/SS1,2 = 0V
VRUN1, VRUN2
RUN Pin On Threshold
VRUN1,2 Rising
VRUN1,2 HYS
RUN Pin ON Hysteresis
80
mV
IRUN1,2 HYS
RUN Pin Current Hysteresis
4.5
µA
Current Sense Pin Bias Current
–10
µA
0.8
9.5
l
1.1
10
mmho
10.5
µA
0.5
40
V
mV
10
µA
1.22
1.35
V
Current Sensing
ISENSE+
ISENSE–
Current Sense Pin Bias Current
VITH = 1.4V
VSENSE(MAX)
Maximum Current Sense Threshold
ILIM1,2 = Float
–20
IMISMATCH
Channel-to-Channel Current Mismatch
ILIM = Float
RUP1,2
Driver Pull-Up RDS(ON)
GATE High
RDOWN1,2
Driver Pull-Down RDS(ON)
GATE Low
1.0
Ω
tON(MIN)1
Minimum On-Time
VBLANK = 0V (Note 7)
120
ns
tON(MIN)2
Minimum On-Time
VBLANK = Float (Note 7)
160
ns
tON(MIN)3
Minimum On-Time
VBLANK = INTVCC (Note 7)
200
ns
l
70
75
µA
80
mV
5
%
Gate Drivers
2
Ω
DRVCC Linear Regulator
DRVCC
Internal LDO Output Voltage for Gate
Driver
12V < VIN < 60V
∆DRVCC(Load)
DRVCC Load Regulation
ICC = 0 to 20mA
4
9.6
10
10.4
V
0.5
2
%
Rev 0
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LTC7840
ELECTRICAL CHARACTERISTICS
(Notes 2, 3) The l denotes the specifications which apply over the specified
operating junction temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VRUN = 2V and SS1,2 = open, unless
otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
3.65
3.8
3.95
V
185
160
200
200
215
240
kHz
kHz
INTVCC Linear Regulator
INTVCC
Internal LDO Output Voltage for Control
Circuit
Oscillator and Phase-Locked Loop
fNOM
Nominal Frequency
VFREQ = 1.03V
(Note 3)
l
fRANGE
Frequency Range
50
425
kHz
fSYNC
SYNC Frequency Range
50
450
kHz
VSYNC
SYNC Input Threshold
0.3
V
V
Φ2 – Φ1
Channel 2 to Channel 1 Phase Delay
VSYNC Rising
VSYNC Falling
1.6
180
Deg
Power Good Output
VPGL
PGOOD Voltage Low
IPGOOD = 2mA
0.1
0.3
V
1
µA
IPGOOD
PGOOD Leakage Current
VPGOOD = 3V
VPG
PGOOD Trip Level
VFB1,FB2P with Respect to Set Output Voltage
VFB1,FB2P Ramping Up
VFB1,FB2P Ramping Down
10
–10
%
%
TDELAY
VPGOOD High to Low Delay Time
(Note 9)
135
µs
Note 1: Stresses beyond those listed in under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
Note 3: The LTC7840E is guaranteed to meet specifications from
0°C to 85°C junction temperature. Specifications over the –40°C to
125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC7840I is guaranteed over the full –40°C to 125°C operating junction
temperature range and the LTC7840H is guaranteed over the full –40°C to
150°C operating temperature range. High junction temperature degrades
operating lifetimes. Operating lifetime is degraded at junction temperature
greater than 125°C. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
impedance and other environmental factors.
Note 4: The LTC7840 includes over-temperature protection that is intended
to protect the devices during momentary overload conditions. Continuous
operation above the specified maximum operating junction temperature
may impair device reliability.
Note 5: Supply current in normal operation is dominated by the current
needed to charge the external MOSFET gates. This current will vary with
the supply voltage and the external MOSFETs used. See Applications
Information.
Note 6: The LTC7840 is tested in a feedback loop that servos VITH1,2 to a
specified voltage and measures the resultant VFB1,FB2.
Note 7: The minimum on-time condition is specified for an inductor
peak-to-peak ripple current ≥30% of IMAX (see Minimum On-Time
Considerations in the Applications Information section).
Note 8: The maximum duty cycle limit is derived from an internal
clock that runs at 12x the programmed switching frequency. See the
Applications Information section for additional information.
Note 9: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Rev 0
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5
LTC7840
TYPICAL PERFORMANCE CHARACTERISTICS
Dual Phase Single Output Load
Transient (0.2A to 0.8A)
(Circuit on Last Page)
Output Efficiency
94
VOUT = 240V
92
90
LOAD CURRENT
500mA/DIV
EFFICIENCY (%)
88
86
84
82
80
INDUCTOR CURRENT
500mA/DIV
78
76
VIN = 24V
VIN = 12V
VIN = 9V
74
72
70
0
0.2
0.4
0.6
0.8
IOUT (A)
1.0
20µs/DIV
VIN = 12V
VOUT = 36V
1.2
7840 G01
Output Voltage Tracking Up and
Down with External Ramp
Switch Node Voltage and Inductor
Current at Light Load (300mA)
12
SS1, SS2
1V/DIV
VSW
20V/DIV
8
DRVCC (V)
VOUT2 (24V)
10V/DIV
VIN = 12V
RLOAD = 240Ω
VIN = 12V
VOUT=48V
2µs/DIV
DRVCC Line Regulation
10
VOUT1 (36V)
10V/DIV
IL
2A/DIV
7840 G02
7840 G03
4
2
7840 G04
50ms/DIV
6
0
5
16
27
38
INPUT VOLTAGE (V)
49
60
7840 G05
QUIESCENT CURRENT (mA)
DRVCC (V)
10.15
10.10
10.05
10.00
9.95
0
10 20 30 40 50 60 70 80 90 100
DRVCC LOAD CURRENT
7840 G06
6
Quiescent Current vs Temperature
5
3
4
QUIESCENT CURRENT (mA)
10.20
Quiescent Current vs Input
Voltage
DRVCC Load Regulation
3
2
1
0
5
16
27
38
INPUT VOLTAGE (V)
49
60
7840 G07
2
1
0
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
7840 G08
Rev 0
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LTC7840
TYPICAL PERFORMANCE CHARACTERISTICS
60
60
50
50
40
30
20
10
0
4.75
40
4.25
30
4.00
20
3.75
10
5
16
27
38
INPUT VOLTAGE (V)
49
0
–50 –25
60
0
0
25 50 75 100 125 150
TEMPERATURE (°C)
7840 G11
Current Sense Threshold vs ITH
Voltage (ILIM Pin Float)
Feedback Voltage vs Temperature
1.210
RISING
FALLING
3.3
3.50
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
7840 G10
INTVCC UVLO Threshold vs
Temperature
3.4
RISING
FALLING
4.50
7840 G09
75
1.205
3.1
VSENSE (mV)
3.2
VFB (V)
INTVCC VOLTAGE (V)
DRVCC UVLO Threshold vs
Temperature
Shutdown Current vs Temperature
SHUTDOWN CURRENT (µA)
SHUTDOWN CURRENT (µA)
Shutdown Current vs Input
Voltage
1.200
3.0
50
25
1.195
2.9
2.8
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
1.190
–50 –25
0
7840 G12
25
0
–50 –25
1.30
8
RISING
FALLING
25 50 75 100 125 150
TEMPERATURE (°C)
IRUN (µA)
1.20
7840 G15
1.10
–50 –25
1.4
RUN = 0.5V
RUN = 2V
6
1.15
0
1.3
RUN Source Current vs
Temperature
1.25
VRUN (V)
VSENSE (mV)
50
1.0
1.1
1.2
ITH VOLTAGE (V)
7840 G14
RUN Threshold vs Temperature
ILIM = GND
ILIM = 0.3V
ILIM = INTVCC
75
0.8
7840 G13
Current Sense Threshold vs
Temperature
100
0
0.7
25 50 75 100 125 150
TEMPERATURE (°C)
4
2
0
25 50 75 100 125 150
TEMPERATURE (°C)
7840 G16
0
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
7840 G17
Rev 0
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7
LTC7840
TYPICAL PERFORMANCE CHARACTERISTICS
SS Pin Pull-Up Current vs
Temperature
SS Pin Pull-Down Current vs
Temperature
2.5
10.1
10.0
9.9
9.8
9.7
9.6
9.5
–50 –25
0
600
2.4
2.3
SWITCHING FREQUENCY (kHz)
SOFT–START PULL–DOWN CURRENT (µA)
SOFT–START PULL–UP CURRENT (µA)
10.2
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.4
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
0
200
100
27
38
INPUT VOLTAGE (V)
49
0
25 50 75 100 125 150
TEMPERATURE (°C)
FREQ Pin Pull-Up Current vs
Temperature
400
300
200
100
0
60
11
0
0.5
1
1.5
2
2.5
VFREQ (V)
7840 G21
ILIM Pin Pull-Up Current vs
Temperature
3
10.5
10
9.5
9
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
7840 G22
7840 G23
Hiccup Mode Overcurrent
Protection and Recovery
(1µF SS Capacitor)
Minimum On-Time vs
Temperature
250
11
ITH
2V/DIV
MINIMUM ON–TIME (ns)
ILIM PULL–UP CURRENT (µA)
100
7840 G20
FREQ PULL–UP CURRENT (µA)
300
16
200
0
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
500
SWITCHING FREQUENCY (kHz)
SWITCHING FREQUENCY (kHz)
500
5
300
Switching Frequency vs FREQ Pin
Voltage
VFREQ = GND
VFREQ = 1.03V
VFREQ = INTVCC
FREQ = GND
FREQ = 1.03V
FREQ = INTVCC
400
7840 G19
Switching Frequency vs Input
Voltage
400
500
1.5
7840 G18
0
Switching Frequency vs
Temperature
10.5
10
9.5
9
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
200
SS
5V/DIV
150
GATE
10V/DIV
100
50
–50 –25
BLANK = GND
BLANK = FLOAT
BLANK = INTVCC
0
2s/DIV
7840 G26
25 50 75 100 125 150
TEMPERATURE (°C)
7840 G25
7840 G24
8
VOUT
50V/DIV
Rev 0
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LTC7840
PIN FUNCTIONS
(TSSOP/QFN)
RUN1 (Pin 9/Pin 6): Channel 1 Run Control Input. A
voltage above 1.22V on this pin turns on the Channel 1.
However, forcing this pin below 1.14V causes the Channel
1 to shut down. There is a 1.0µA pull-up current for this
pin. Once the Run pin rises above 1.22V, an additional
4.5µA pull-up current is added to the pin.
VFB1 (Pin 7/Pin 4): Channel 1 Error Amplifier Feedback
Input. This pin connects to the center tap of an external
resistor divider across the Channel 1 output.
RUN2 (Pin 10/Pin 7): Channel 2 Run Control Input. A
voltage above 1.22V on this pin turns on the Channel 2.
However, forcing this pin below 1.14V causes the Channel
2 to shut down. There is a 1.0µA pull-up current for this
pin. Once the Run pin rises above 1.22V, an additional
4.5µA pull-up current is added to the pin.
FREQ (Pin 5/Pin 2): Oscillator Frequency Control Input.
There is a precise 10µA current flowing out of this pin. A
resistor to ground sets a voltage which in turn programs
the frequency. Alternatively, this pin can be driven with a
DC voltage to vary the frequency of the internal oscillator.
INTVCC (Pin 25/Pin 22): Internal 3.8V LDO Output. The
low voltage analog and digital circuits are powered from
this voltage. Bypass this pin to SGND with 1nF low ESR
ceramic capacitor.
ILIM1 (Pin 26/Pin 23): Channel 1 Current Comparator’s
Sense Voltage Range Input Pin. There is a precise 10µA
current flowing out of this pin. A resistor to SGND can
set the voltage on this pin to program the maximum current sense threshold to any voltage lower than 75mV.
Alternatively, a DC voltage which is lower than 0.5V can
be added to this pin to adjust the maximum current sense
threshold. Floating this pin makes the current comparator’s maximum sense voltage be 75mV.
ILIM2 (Pin 16/Pin 13): Channel 2 Current Comparator’s
Sense Voltage Range Input Pin. There is a precise 10µA
current flowing out of this pin. A resistor to SGND can
set the voltage on this pin to program the maximum current sense threshold to any voltage lower than 75mV.
Alternatively, a DC voltage which is lower than 0.5V can
be added to this pin to adjust the maximum current sense
threshold. Floating this pin makes the current comparator’s maximum sense voltage be 75mV.
DMAX (Pin 4/Pin 1): Maximum Duty Cycle. This pin programs the maximum duty cycle. Floating this pin provides
84% duty cycle. Connecting this pin to INTVCC provides
75% duty cycle, while connecting this pin to SGND provides 96% duty cycle.
VFB2 (Pin 12/Pin 9): Channel 2 Error Amplifier Feedback
Input. This pin connects to the center tap of an external
resistor divider across the Channel 2 output.
GATE1 (Pin 21/Pin 18): Channel 1 Gate Drive Output. The
LTC7840 provides a 10V gate drive referred to PGND to
drive a high voltage MOSFET.
GATE2 (Pin 19/Pin 16): Channel 2 Gate Drive Output. The
LTC7840 provides a 10V gate drive referred to PGND to
drive a high voltage MOSFET.
DRVCC (Pin 22/Pin 19): Internal 10V LDO Output. The
gate drivers are powered from this voltage. Bypass this
pin to PGND with a minimum of 4.7µF low ESR ceramic
capacitor.
ITH1 (Pin 8/Pin 5): Channel 1 Current Control Threshold
and Error Amplifier Compensation Point. Channel 1’s current comparator’s tripping threshold increases with this
control voltage.
ITH2 (Pin 13/Pin 10): Channel 2 Current Control Threshold
and Error Amplifier Compensation Point. Channel 2’s current comparator’s tripping threshold increases with this
control voltage.
SGND (Pin 24/Pin 21 and Exposed Pad): Signal Ground
Pin. All small-signal components and compensation components should connect to this ground.
PGND (Pin 20/Pin 17): Power Ground Pin. Connect
this pin closely to the sources of the bottom N-channel
MOSFETs and the negative terminals of the VIN and DRVCC
bypassing capacitors.
Rev 0
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9
LTC7840
PIN FUNCTIONS
(TSSOP/QFN)
BLANK (Pin 1/Pin 26): Blanking Time Pin. Floating this
pin provides a nominal minimum on-time of 160ns.
Connecting this pin to INTVCC provides a minimum ontime of 200ns, while connecting this pin to SGND provides
a minimum on-time of 120ns.
SENSE1+ (Pin 28/Pin 25): Positive Terminal of Channel
1 Current Comparator. This pin is normally connected to
a sense resistor in series with the source of the power
MOSFET.
SENSE2+ (Pin 14/Pin 11): Positive Terminal of Channel
2 Current Comparator. This pin is normally connected to
a sense resistor in series with the source of the power
MOSFET.
SENSE1- (Pin 27/Pin 24): Negative Terminal of Channel
1 Current Comparator. This pin is normally connected to
the bottom of the sense resistor.
SENSE2- (Pin 15/Pin 12): Negative Terminal of Channel
2 Current Comparator. This pin is normally connected to
the bottom of the sense resistor.
SS1 (Pin 6/Pin 3): Soft Start Inputs. A capacitor to SGND
at this pin sets the ramp rate for Channel 1’s output voltage. An internal soft start current of 10µA charges this pin.
The Hiccup Mode timing is also set by this pin. At least
0.1µF capacitor is needed between this pin and SGND.
SS2 (Pin 11/Pin 8): Soft Start Inputs. A capacitor to SGND
at this pin sets the ramp rate for Channel 2’s output voltage. An internal soft start current of 10µA charges this pin.
10
The Hiccup Mode timing is also set by this pin. At least
0.1µF capacitor is needed between this pin and SGND.
SYNC (Pin 3/Pin 28): PLL Synchronization Input. Applying
an external clock between 50 kHz and 450 kHz will force
the operating frequency to synchronize to the clock. The
PLL compensation network is integrated into the IC. This
pin has an internal 100kΩ pull down resistor. An external
clock signal with amplitude greater than 1.6V is considered active high, while with amplitude less than 0.3V is
considered active low.
PGOOD1 (Pin 18/Pin 15): Power Good Indicator Output
for Channel 1. Open drain logic that is pulled to ground
when Channel 1’s output exceeds its ±10% regulation
window after the internal 135µs power bad mask timer
expires.
PGOOD2 (Pin 17/Pin 14): Power Good Indicator Output
for Channel 2. Open drain logic that is pulled to ground
when Channel 2’s output exceeds its ±10% regulation
window after the internal 135µs power bad mask timer
expires.
VIN (Pin 23/Pin 20): Main Input Supply. Bypass this pin
to PGND with a capacitor (0.1µF to 1 µF).
CLKOUT (Pin 2/Pin 27): Clock Output Pin. Clock output
used for daisy-chaining multiple LTC7840 ICs in multiphase systems. The phase shift from Channel 1 to Clock
Output is 90°.
Rev 0
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LTC7840
BLOCK DIAGRAM
SYNC
VIN
(UP TO 60V)
FREQ
10V
LDO
RFREQ
SYNC
DETECT
PLL-SYNC
OT
CLK1
DMAX
OSC
UVLO1
UVLO1
3.8V
LDO
OVER
TEMP
UVLO2
BIAS
CLK2
DMAX
S
BLANK
OC
OT
UVLO1,2
R1 Q
BLOGIC
OV
PSKIP
CINTVCC
D
SGND
GATE
OT
UVLO1,2
SD
SLOPE
COMPENSATION
ITRIP
+
ICMP
–
VOUT
COUT
M
INTVCC (3.8V)
10µA
SS
ILIM
ILIM
ADJUSTMENT
7.5k
SENSE+
7.5k
SENSE–
RILIM
RSENSE
V TO I
1.25µA
PGND
ITH
ACTIVE
CLAMP
RC
CC
INTVCC
(3.8V)
LOGIC
BLOGIC
RUN
PWM LATCH
HICCUP
L
+
10µA
CSS
CDRVCC
*
R2
INTVCC (3.8V)
START-UP
DRVCC
(10V)
UVLO2
CLKOUT
BLANK
LOGIC
VIN
CIN
PSKIP
PSKIP
+ –
0.5V
PGOOD
UV
EA
++–
SS
1.2V
UV
+ –
1.08V
OV
SD
OV
– +
R2
1.32V
RUN
– +
VFB
INTERNAL
(4.5V)
R1
1µA/5.5µA
RUN
1.22V
7840 BD
* DUPLICATE FOR SECOND CHANNEL
Rev 0
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11
LTC7840
OPERATION
The Control Loop
supply (DRVCC) and one for the low voltage analog and
digital control circuitry (INTVCC). A block diagram of this
power supply architecture is shown in Figure 1.
The LTC7840 is a constant frequency, current mode,
boost controller with two channels operating 180º out-ofphase. During normal operation, each external MOSFET
is turned on when the clock for that channel sets the RS
latch, and turned off when the main current comparator,
ICMP, resets the RS latch. The peak inductor current at
which ICMP resets the RS latch is controlled by the voltage on the ITH pin, which is the output of each error amplifier EA. The error amplifier compares the output feedback
signal at the VFB pin to the internal 1.2V reference and
generates an error signal at the ITH pin. When the load current increases, it causes a slight decrease in the feedback
relative to the 1.2V reference, which in turn causes the
ITH voltage to increase until the average inductor current
matches the new load current. After the MOSFET is turned
off, the inductor current flows through the boost diode
into the output capacitor and load, until the beginning of
the next clock cycle.
The output of either LDO cannot be biased from external
power supply. Otherwise, two possible failure modes will
be caused. As shown in Figure 1, there are body diodes
in parallel with the PMOS output transistors in the two
LDO regulators. If the DRVCC or INTVCC supply comes
up before the VIN supply, high current will flow from the
external DRVCC or INTVCC supply through the body diode
to the input capacitor and VIN pin. This high current flow
could cause catastrophic failure of the IC.
If the VIN supply comes up before the DRVCC or INTVCC
supply, or if the DRVCC or INTVCC pins are biased to any
voltage lower than the regulated voltage by low-impedance voltage sources, the LDO will attempt to pull up its
output voltage and this current will result in excessive
power dissipation and possible thermal overload of the
LTC7840.
Cascaded LDOs Supply Power to the Gate Driver and
Control Circuitry
Also, in multi-chip parallel applications, the output pins
of LDOs should not be connected together. When two
or more LDO outputs are tied together, the highest voltage regulator supplies all of the gate driver and control
The LTC7840 contains two cascaded PMOS output stage
low dropout regulators (LDOs), one for the gate driver
LTC7840
VIN
1.218V
CIN
–
P-CH
+
R2
R1
SGND
INTVCC
1.218V
DRVCC
–
CDRVCC
P-CH
+
R4
R3
GATE
PGND
SGND
INTVCC
ANALOG
CIRCUITS
INTVCC
LOGIC
CINTCC
SGND
7840 F01
NOTE: PLACE CDRVCC AND CINTVCC CAPACITORS AS CLOSE AS POSSIBLE TO DEVICE PINS
Figure 1. Cascaded LDOs Provide Gate Driver and Control Circuitry Power
12
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LTC7840
OPERATION
circuit current, but the other regulators are off. This would
place a thermal burden on the highest output voltage LDO
and could cause the maximum die temperature to be
exceeded. In multi-chip parallel applications, each LDO
output should be independently bypassed to its respective
GND pin as close as possible to each IC.
The Gate Driver Supply LDO (DRVCC)
The 10V output (DRVCC) of the first LDO is powered from
VIN and supplies power to the power MOSFET gate drivers. The DRVCC pin should be bypassed to PGND with
a minimum of 4.7µF ceramic capacitor (X5R or better)
placed as close as possible to the IC pin. If two power
MOSFETs are connected in parallel for each channel in
order to increase the output power level, or if a single
MOSFET with a Qg greater than 50nC is used, then it is
recommended that the bypass capacitor be increased to
a minimum of 10µF.
An under voltage lockout (UVLO) circuit senses the DRVCC
regulator output in order to protect the power MOSFETs
from operating with the inadequate gate drive. For the
LTC7840, the rising UVLO threshold is 4.4V and the hysteresis is typically 500mV. In low VIN applications, the
low threshold MOSFET (10%) as well as other more serious conditions that may overvoltage the output. In such cases, the
external power MOSFET is turned off until the overvoltage
condition is cleared.
Overcurrent Protection
(ILIM1, ILIM2 Pins and Hiccup Mode)
The LTC7840 has ILIM1 and ILIM2 pins to set the maximum inductor current limit of each channel respectively,
as described in the ILIM1 and ILIM2 pins function. The
voltage on each ILIM pin is used to generate the internal
ITH clamp voltage. Along with the increase of load current, ITH voltage will rise to allow higher inductor current
flowing to the load. If the load current keeps increasing,
the ITH voltage will finally reach the clamp voltage and
the inductor current cannot go up any more. This situation is thought as an overcurrent event by the controller.
If this event lasts for 16 continuous switching periods,
the controller will enter hiccup mode. The ITH voltage is
pulled down to GND and the external power MOSFET is
turned off. The inductor current will gradually reduce to
zero. At this moment, the soft-start capacitor connected
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LTC7840
OPERATION
between the SS pin and SGND is discharged by a 1.25µA
current. When the voltage on SS pin reaches 0V, the ITH
pin is released and the controller retries to soft-start, as
described in the Shutdown and Start-Up section. The
hiccup mode is disabled during the soft-start period. To
realize the function of the hiccup mode, a minimum 0.1µF
soft-start capacitor has to be connected between the SS
pin and SGND. The sleep time can be estimated by:
tSLEEP = CSS •
1.5V
1.25µA
= 1.2 • CSS
reset to zero and the output will soft recover by using the
internal soft-start, thus reducing output overshoot. In the
absence of this feature, the output capacitors would have
been charged at current limit, and in applications with
minimal output capacitance, this may have resulted in
output overshoot.
ITH
2V/DIV
SS
5V/DIV
Compared with the start-up time estimated in the
Shutdown and Start-Up section, the sleep time is roughly
10 times the start-up time.
If the overcurrent situation is removed continuously for
two or more switching periods before the 16 switching
period timer expires, the 16 switching period timer will
GATE
10V/DIV
VOUT
50V/DIV
2s/DIV
7840 F12
Figure 12. Hiccup Mode Overcurrent Protection and Recovery
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21
LTC7840
APPLICATIONS INFORMATION
The LTC7840 is a dual-phase constant frequency current
mode nonsynchronous step-up controller. This topology
makes the output voltage not limited by the IC voltage.
The LTC7840 can be configured in many ways as:
• a dual-phase dual-output boost converter with each
phase operating independently;
• a dual-phase dual-output boost converter with one
phase’s output connected to the other phase’s input.
As a result of this two-step-up configuration, a much
higher output voltage can be obtained;
• a dual-phase single-output boost converter;
• SEPIC topology;
• Other applications.
A wide 5.5V to 60V input voltage range can accommodate high input voltage surges. With the selectable leading edge blanking time, the noise on the SENSE pins at
the leading edge of the power MOSFET turn-on is filtered
out maximally. The programmable maximum duty cycle
provides the flexibility to the user for configuring different
topologies with LTC7840. The maximum current limit can
be adjusted by the user based on the sense resistor value.
For light load application, once ITH drops below 0.5V,
the controller is forced to skip cycles to maintain output
regulation. Each channel of the LTC7840 has a power
good indicator output to reflect if this channel’s output
voltage is within the regulation window. The LTC7840 can
be configured for single-phase, dual-phase and 4-phase
operation. The SYNC pin allows the IC to be synchronized to an external clock. Without the external clock, the
switching frequency of the controller can be set by the
voltage on the FREQ pin. The LTC7840 provides overcurrent protection by the hiccup mode. The controller also
has output overvoltage protection.
In general, the external component selection is driven by
the characteristics of the load and the input supply. Next,
power MOSFETs are selected. Finally, input and output
capacitors are selected.
22
Duty Cycle Considerations
For a boost converter operating in a continuous conduction mode (CCM), the duty cycle of the main switch is:
⎛V +V –V ⎞
D = ⎜ O F IN ⎟ = tON • f
⎝ VO + VF ⎠
where VF is the forward voltage of the boost diode. The
minimum on-time for a given application operating in
CCM is:
1⎛ VO + VF – VIN(MAX) ⎞
tON(MIN) = ⎜
⎟⎠
f⎝
VO + VF
For a given input voltage range and output voltage, it is
important to know how close the minimum on-time of the
application comes to the minimum on-time of the control
IC. The LTC7840 minimum on-time can be programmed
from 120ns to 200ns using the BLANK pin.
Minimum On-Time Limitations
In a boost converter, two steady-state conditions can
result in operation at the minimum on-time of the controller. The first condition is when the input voltage is
close to the output voltage. When VIN approaches VOUT
the voltage across the inductor approaches zero during
the switch off-time. Under this operating condition the
converter can become unstable and the output can experience high ripple voltage oscillation at audible frequencies.
For applications where the input voltage can approach
or exceed the output voltage, consider using a SEPIC or
buck-boost topology instead of a boost converter.
The second condition that can result in operation at the
minimum on-time of the controller is at light load, in deep
discontinuous mode. As the load current is decreased, the
on-time of the switch decreases, until the minimum ontime limit of the controller is reached. Any further decrease
in the output current will result in pulse-skipping, a typically benign condition where cycles are skipped in order
to maintain output regulation.
Rev 0
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LTC7840
APPLICATIONS INFORMATION
Maximum Duty Cycle Limitations
Another operating extreme occurs at high duty cycle,
when the input voltage is low and the output voltage is
high. In this case:
⎛ VO + VF – VIN(MIN) ⎞
DMAX = ⎜
⎟⎠
VO + VF
⎝
VIN
1– DMAX
IIN(MAX) =
IO(MAX)
1– DMAX
The peak current in each inductor is:
A single-ended boost converter needs a minimum offtime every cycle in order to allow energy transfer from
the input inductor to the output capacitor. This minimum
off-time translates to a maximum duty cycle for the converter. The equation above can be rearranged to obtain
the maximum output voltage for a given minimum input
or maximum duty cycle.
VO(MAX) =
output power is equal to the input power, the maximum
average input current is:
1 ⎛ χ ⎞ IO(MAX)
• ⎜ 1+ ⎟ •
n ⎝ 2 ⎠ 1– DMAX
IIN(PK) =
where n represents the number of phases and χ represents the percentage peak-to-peak ripple current in the
inductor. For example, if the design goal is to have 30%
ripple current in the inductor, then χ = 0.30, and the peak
current is 15% greater than the average.
Inductor Selection
– VF
The equation for DMAX above can be used as an initial
guideline for determining the maximum duty cycle of the
application circuit. However, losses in the inductor, input
and output capacitors, the power MOSFETs, the sense
resistors and the controller (gate drive losses) all contribute to an increasing of the duty cycle. The effect of these
losses will be to decrease the maximum output voltage
for a given minimum input voltage.
After the initial calculations have been completed for an
application circuit, it is important to build a prototype of
the circuit and measure it over the entire input voltage
range, from light load to full load, and over temperature,
in order to verify proper operation of the circuit.
Peak and Average Input Currents
The control circuit in the LTC7840 measures the input
current (by means of resistors in the sources of the power
MOSFETs), so the output current needs to be reflected
back to the input in order to dimension the power
MOSFETs properly. Based on the fact that, ideally, the
Given an input voltage range, operating frequency and
ripple current, the inductor value can be determined using
the following equation:
L=
VIN(MIN)
∆IL • f
• DMAX
where:
∆IL =
χ
•
IO(MAX)
n 1– DMAX
Choosing a larger value of ∆IL allows the use of a lower
value inductor but results in higher output voltage ripple,
greater core losses, and higher ripple current ratings for
the input and output capacitors. A reasonable starting
point is 30% ripple current in the inductor (χ = 0.3), or:
∆IL =
0.3
n
•
IO(MAX)
1– DMAX
The inductor saturation current rating needs to be higher
than the worst-case peak inductor current during an
overload condition. If IO(MAX) is the maximum rated load
Rev 0
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23
LTC7840
APPLICATIONS INFORMATION
current, then the maximum current limit value (IO(CL))
would normally be chosen to be some factor (e.g., 30%)
greater than IO(MAX).
IO(CL) = 1.3 • IO(MAX)
Reflecting this back to the input, where the current is being
measured, and accounting for the ripple current, gives a
minimum saturation current rating for the inductor of:
1 ⎛ χ ⎞ 1.3 •IO(MAX)
IL(SAT) ≥ • ⎜ 1+ ⎟ •
n ⎝ 2 ⎠ 1– DMAX
The saturation current rating for the inductor should be
determined at the minimum input voltage (which results
in the highest duty cycle and maximum input current),
maximum output current and the maximum expected core
temperature. The saturation current ratings for most commercially available inductors drop at high temperature.
To verify safe operation, it is a good idea to characterize
the inductor’s core/winding temperature under the following conditions: 1) worst-case operating conditions,
2) maximum allowable ambient temperature and 3) with
the power supply mounted in the final enclosure. Thermal
characterization can be done by placing a thermocouple
in intimate contact with the winding/core structure, or by
burying the thermocouple within the windings themselves.
Remember that a single-ended boost converter is not
short-circuit protected, and that under a shorted output
condition, the output current is limited only by the input
supply capability. For applications requiring a step-up
converter that is short-circuit protected, consider using
a SEPIC or forward converter topology.
The gate driver for the LTC7840 consists of PMOS pullup and NMOS pull-down devices, allowing the full DRVCC
voltage to be applied to the gates during power MOSFET
switching. Nonetheless, care must be taken to ensure
that the minimum gate drive voltage is still sufficient to
full enhance the power MOSFET. Check the MOSFET data
sheet carefully to verify that the RDS(ON) of the MOSFET
is specified for a voltage less than or equal to the nominal
DRVCC voltage of 10V.
Also pay close attention to the BVDSS specifications for
the MOSFETs relative to the maximum actual switch voltage in the application. Check the switching waveforms of
the MOSFET directly on the drain terminal using a single
probe and a high bandwidth oscilloscope. Ensure that the
drain voltage ringing does not approach the BVDSS of the
MOSFET. Excessive ringing at high frequency is normally
an indicator of too much series inductance in the high di/
dt current path that includes the MOSFET, the boost diode,
the output capacitor, the sense resistor and the PCB traces
connecting these components.
The GATE of MOSFET Q1 could experience transient voltage spikes during turn-on and turn-off of the MOSFET,
due to parasitic lead inductance and improper PCB layout.
These voltage spikes could exceed the absolute maximum voltage ratings of LTC7840’s GATE pin. The GATE
pins are rated for an absolute maximum voltage of –0.3V
minimum and 11V maximum. Hence it is recommended
to add an external buffer close to the GATE of the MOSFET
as shown in Figure 13.
VIN
L
Power MOSFET Selection
DRVCC
The peak-to-peak gate drive level is set by the DRVCC
voltage is 10V for the LTC7840 under normal operating
conditions. Selection criteria for the power MOSFETs
include the RDS(ON), gate charge QG, drain-to-source
breakdown voltage BVDSS, maximum continuous drain
current ID(MAX), and thermal resistances RTH(JA) and
RTH(JC)—both junction-to-ambient and junction-to-case.
PBS4140DPN
LTC7840
GATE1, 2
VOUT
Q2A
10Ω
Q1
Q2B
COUT
RSENSE
PGND
SGND
7840 F13
Figure 13. External Buffer Circuit
24
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LTC7840
APPLICATIONS INFORMATION
Calculating Power MOSFET Switching and Conduction
Losses and Junction Temperatures
In order to calculate the junction temperature of the
power MOSFET, the power dissipated by the device must
be known. This power dissipation is a function of the
duty cycle, the load current and the junction temperature
itself (due to the positive temperature coefficient of its
RDS(ON)). As a result, some iterative calculation is normally required to determine a reasonably accurate value.
The power dissipated by the MOSFET in a multi-phase
boost converter with n phases is:
2
⎛ IO(MAX) ⎞
PFET = ⎜
⎟ • RDS(ON) • DMAX • ρT
⎝ n • (1– DMAX ) ⎠
+ k • VOUT2 •
IO(MAX)
n • (1– DMAX )
• CRSS • f
The first term in the equation above represents the I2R
losses in the device, and the second term, the switching losses. The constant, k = 1.7, is an empirical factor
inversely related to the gate drive current and has the
dimension of 1/current.
The ρT term accounts for the temperature coefficient of
the RDS(ON) of the MOSFET, which is typically 0.4%/ºC.
Figure 14 illustrates the variation of normalized RDS(ON)
over temperature for a typical power MOSFET.
2.0
ρT NORMALIZED ON RESISTANCE
Finally, check the MOSFET manufacturer’s data sheet for
an avalanche energy rating (EAS). Some MOSFETs are not
rated for body diode avalanche and will fail catastrophically if the VDS exceeds the device BVDSS, even if only by
a fraction of a volt. Avalanche-rated MOSFETs are better
able to sustain high frequency drain-to-source ringing
near the device BVDSS during the turn-off transition.
1.5
1.0
0.5
0
–50
50
100
0
JUNCTION TEMPERATURE (°C)
150
7840 F14
Figure 14. Normalized Power MOSFET RDS(ON) vs Temperature
From a known power dissipated in the power MOSFET, its
junction temperature can be obtained using the following
formula:
TJ = TA + PFET • RTH(JA)
The RTH(JA) to be used in this equation normally includes
the RTH(JC) for the device plus the thermal resistance from
the case to the ambient temperature (RTH(CA)). This value
of TJ can then be compared to the original, assumed value
used in the iterative calculation process.
It is tempting to choose a power MOSFET with a very low
RDS(ON) in order to reduce conduction losses. In doing
so, however, the gate charge QG is usually significantly
higher, which increases switching and gate drive losses.
Since the switching losses increase with the square of
the output voltage, applications with a low output voltage
generally have higher MOSFET conduction losses, and
high output voltage applications generally have higher
MOSFET switching losses. At high output voltages, the
highest efficiency is usually obtained by using a MOSFET
with a higher RDS(ON) and lower QG. The equation above
can easily be split into two components (conduction and
switching) and entered into a spreadsheet, in order to
compare the performance of different MOSFETs.
Rev 0
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25
LTC7840
APPLICATIONS INFORMATION
Programming the Current Limit
The LTC7840 has ILIM1 and ILIM2 pins to adjust the current comparator’s maximum sense voltage for Channel 1
and Channel 2 respectively. There is a precise 10µA current flowing out of ILIM pin. A resistor to SGND can set
the voltage on ILIM pin to program the peak current sense
threshold to any voltage lower than 75mV. Alternatively,
a DC voltage which is lower than 0.5V can be added to
ILIM pin to adjust the maximum current sense threshold.
Floating ILIM pin or adding any voltage higher than 0.5V
make the current comparator’s maximum sense voltage
be 75mV.
For a boost converter where the current limit value is
chosen to be 30% higher than the maximum load current,
the peak current in the MOSFET and sense resistor is:
ISW(MAX) = IR(SENSE) =
1 ⎛
χ ⎞ 1.3 • IO(MAX)
• ⎜ 1+ ⎟ •
1– DMAX
n ⎝
2⎠
The sense resistor value is then:
R SENSE =
χ⎞
⎛
1.3 • 1+
• IO(MAX)
⎝
2⎠
Again, the factor n is the number of phases used, and χ
represents the percentage ripple current in the inductor.
The number 1.3 represents the factor by which the current limit exceeds the maximum load current, IO(MAX). For
example, if the current limit needs to exceed the maximum load current by 50%, then the 1.3 factor should be
replaced with 1.5.
The average power dissipated in the sense resistor can
easily be calculated as:
⎛ 1.3 •IO(MAX) ⎞
PR(SENSE) = ⎜
• RSENSE • DMAX
n • (1– DMAX ) ⎟⎠
⎝
26
The resistor temperature can be calculated using the
equation:
TD = TA + PR(SENSE) • RTH(JA)
Selecting the Output Diodes
To maximize efficiency, a fast switching diode with low
forward drop and low reverse leakage is required. The
output diode in a boost converter conducts current during the switch off-time. The peak reverse voltage that the
diode must withstand is equal to the regulator output voltage. The average forward current in normal operation is
equal to the output current, and the peak current is equal
to the peak inductor current:
VSENSE(MAX) • n • ( 1– DMAX )
2
This equation assumes no temperature coefficient for the
sense resistor. If the resistor chosen has a significant temperature coefficient, then substitute the worst-case high
resistance value into the equation.
I
•V
IIN = OUT OUT
VIN
Although the average diode current is equal to the output
current, in very high duty cycle applications (low VIN to
high VOUT) the peak diode current can be several times
higher than the average, as shown in Figure 15. In this
case check the diode manufacturer’s data sheet to ensure
that its peak current rating exceeds the peak current in
the equation above. In addition, when calculating the
power dissipation in the diode, use the value of the forward voltage (VF) measured at the peak current, not the
average output current. Excess power will be dissipated
in the series resistance of the diode, which would not be
accounted for if the average output current and forward
voltage were used in the equations. Finally, this additional
power dissipation is important when deciding on a diode
current rating, package type, and method of heat sinking.
Rev 0
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LTC7840
APPLICATIONS INFORMATION
SW1
100V/DIV
SW NODE
50V/DIV
SW2
100V/DIV
IL1
2A/DIV
IL2
2A/DIV
VOUT
100mV/DIV
AC COUPLED
INDUCTOR
CURRENT
1A/DIV
DIODE
CURRENT
1A/DIV
VIN = 12V
VOUT = 72V
1µs/DIV
7840 F15
VIN = 24V
VOUT = 72V
350mA LOAD
Figure 15. Diode Current Waveform for a High
Duty Cycle Application
To a close approximation, the power dissipated by the
diode is:
PD = ID(PEAK) • VF(PEAK) • (1 – DMAX)
The diode junction temperature is:
TJ = TA + PD • RTH(JA)
The RTH(JA) to be used in this equation normally includes
the RTH(JC) for the device plus the thermal resistance from
the board to the ambient temperature in the enclosure.
Once the proper diode has been selected and the circuit
performance has been verified, measure the temperature
of the power components using a thermal probe or infrared camera over all operating conditions to ensure a good
thermal design.
Finally, remember to keep the diode lead lengths short and
to observe proper switch-node layout (see Board Layout
Checklist) to avoid excessive ringing and increased
dissipation.
1µs/DIV
7840 F16
Figure 16. Switching Waveforms for a Boost Converter
The choice of component(s) begins with the maximum
acceptable ripple voltage (expressed as a percentage of
the output voltage), and how this ripple should be divided
between the ESR step and the charging/discharging ∆V.
For the purpose of simplicity we will choose 2% for the
maximum output ripple, to be divided equally between the
ESR step and the charging/discharging ∆V. This percentage ripple will change, depending on the requirements
of the application, and the equations provided below can
easily be modified.
One of the key benefits of multi-phase operation is a reduction in the peak current supplied to the output capacitor
by the boost diodes. As a result, the ESR requirement
of the capacitor is relaxed. For a 1% contribution to the
total ripple voltage, the ESR of the output capacitor can
be determined using the following equation:
ESR COUT ≤
0.01• VOUT
ID(PEAK)
where:
Output Capacitor Selection
Contributions of ESR (equivalent series resistance), ESL
(equivalent series inductance) and the bulk capacitance
must be considered when choosing the correct combination of output capacitors for a boost converter application. The effects of these three parameters on the output
voltage ripple waveform are illustrated in Figure 16 for a
typical boost converter.
ID(PEAK) =
1 ⎛ χ ⎞ IO(MAX)
• ⎜ 1+ ⎟ •
n ⎝ 2 ⎠ 1– DMAX
The factor n represents the number of phases and the
factor χ represents the percentage inductor ripple current.
Rev 0
For more information www.analog.com
27
LTC7840
APPLICATIONS INFORMATION
For the bulk capacitance, which we assume contributes
1% to the total output ripple, the minimum required
capacitance is approximately:
COUT ≥
IO(MAX)
0.01• n • VOUT • f
For many designs it will be necessary to use one type of
capacitor to obtain the required ESR, and another type to
satisfy the bulk capacitance. For example, using a low ESR
ceramic capacitor can minimize the ESR step, while an
electrolytic capacitor can be used to supply the required
bulk C.
The voltage rating of the output capacitor must be greater
than the maximum output voltage, with sufficient derating
to account for the maximum capacitor temperature.
IORIPPLE/IOUT
Because the ripple current in the output capacitor is a
square wave, the ripple current requirements for this
capacitor depend on the duty cycle, the number of phases
and the maximum output current. Figure 17 illustrates the
normalized output capacitor ripple current as a function of
duty cycle. In order to choose a ripple current rating for
the output capacitor, first establish the duty cycle range,
based on the output voltage and range of input voltage.
3.25
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
0.1
1-PHASE
2-PHASE
0.2
0.3 0.4 0.5 0.6 0.7 0.8
DUTY CYCLE OR (1-VIN/VOUT)
0.9
7840 F17
Figure 17. Normalized Output Capacitor
Ripple Current (RMS) for a Boost Converter
28
Referring to Figure 17, choose the worst-case high normalized ripple current, as a percentage of the maximum
load current.
The output ripple current is divided between the various
capacitors connected in parallel at the output voltage.
Although ceramic capacitors are generally known for low
ESR (especially X5R and X7R), these capacitors suffer
from a relatively high voltage coefficient. Therefore, it is
not safe to assume that the entire ripple current flows in
the ceramic capacitor. Aluminum electrolytic capacitors
are generally chosen because of their high bulk capacitance, but they have a relatively high ESR. As a result,
some amount of ripple current will flow in this capacitor. If the ripple current flowing into a capacitor exceeds
its RMS rating, the capacitor will heat up, reducing its
effective capacitance and adversely affecting its reliability. After the output capacitor configuration has been
determined using the equations provided, measure the
individual capacitor case temperatures in order to verify
good thermal performance.
Input Capacitor Selection
The input capacitor voltage rating in a boost converter
should comfortably exceed the maximum input voltage.
Although ceramic capacitors can be relatively tolerant of
overvoltage conditions, aluminum electrolytic capacitors
are not. Be sure to characterize the input voltage for any
possible overvoltage transients that could apply excess
stress to the input capacitors.
The value of the input capacitor is a function of the
source impedance, and in general, the higher the source
impedance, the higher the required input capacitance.
The required amount of input capacitance is also greatly
affected by the duty cycle. High output current applications that also experience high duty cycles can place great
demands on the input supply, both in terms of DC current
and ripple current.
The input ripple current in a multi-phase boost converter
is relatively low (compared with the output ripple current),
because this current is continuous and is being divided
Rev 0
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LTC7840
APPLICATIONS INFORMATION
between two or more inductors. Nonetheless, significant
stress can be placed on the input capacitor, especially
in high duty cycle applications. Figure 18 illustrates the
normalized input ripple current, where:
INORM =
VIN
Checking the Load Transient Response
L•f
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, VOUT shifts by an
amount equal to ΔILOAD • (ESR), where ESR is the effective
series resistance of COUT. ΔILOAD also begins to charge or
discharge COUT, generating the feedback error signal that
forces the regulator to adapt to the current change and
return VOUT to its steady-state value. During this recovery
time VOUT can be monitored for excessive overshoot or
ringing, which would indicate a stability problem.
1.00
0.90
0.80
ΔIIN/INORM
0.70
0.60
1-PHASE
0.50
0.40
2-PHASE
0.30
0.20
0.10
0
0
on SS pin reaches 1.32V, the hiccup mode is enabled to
make the converter enter the sleep mode even though
the output voltage hasn’t reached the target value. In this
case, the system cannot start up normally.
0.2
0.6
0.4
DUTY CYCLE
0.8
1.0
7840 F18
Figure 18. Normalized Input Peak-to-Peak Ripple Current
Soft Start (SS Pin) Capacitor Selection
The LTC7840 has hiccup mode to protect the system in
the event of overcurrent. Because the hiccup mode timing
is set by discharging the soft start capacitor, at least 0.1µF
capacitor must be tied between SS pin and SGND. At start
up, an 10µA current flowing out of SS pin to charge the
soft start capacitor. The hiccup mode is disabled until the
voltage on SS pin ramps up to 1.32V (10% higher than
the 1.2V internal reference). For a properly configured
system, the output’s feedback voltage tracks the voltage
on SS pin until it reaches 1.2V. At this moment, the converter’s output voltage reaches the regulated value and the
system enters the steady state. If the target output voltage
is high or if heavy loaded, the soft start capacitor needs to
be larger to slow down the ramp up speed, otherwise, the
converter’s output voltage cannot follow the voltage on SS
pin in time. At the same time, the system keeps operating
at the maximum current limit. This situation is thought
as overcurrent event by the controller. Once the voltage
The availability of the ITH pin not only allows optimization
of control loop behavior but also provides a DC coupled
and AC filtered closed loop response test point. The DC
step, rise time and settling at this test point truly reflects
the closed loop response. Assuming a predominantly second order system, phase margin and/or damping factor
can be estimated using the percentage of overshoot seen
at this pin. The bandwidth can also be estimated by examining the rise time at the pin.
The ITH series RC • CC filter sets the dominant pole-zero
loop compensation. The transfer function for boost and
flyback converters contains a right half plane zero that normally requires the loop crossover frequency to be reduced
significantly in order to maintain good phase margin.
The RC • CC filter values can typically be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and the
particular output capacitor type(s) and value(s) have been
determined. The output capacitor configuration needs to
be selected in advance because the effective ESR and bulk
capacitance have a significant effect on the loop gain and
phase. An output current pulse of 20% to 80% of full-load
current having a rise time of 1μs to 10μs will produce output voltage and ITH pin waveforms that will give a sense
Rev 0
For more information www.analog.com
29
LTC7840
APPLICATIONS INFORMATION
of the overall loop stability without breaking the feedback
loop. Placing a power MOSFET and load resistor directly
across the output capacitor and driving the gate with an
appropriate signal generator is a practical way to produce
a fast load step condition. The initial output voltage step
resulting from the step change in the output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This is
why it is better to look at the ITH pin signal which is in the
feedback loop and is the filtered and compensated control loop response. The gain of the loop will be increased
by increasing RC and the bandwidth of the loop will be
increased by decreasing CC. If RC is increased by the same
factor that CC is decreased, the zero frequency will be kept
the same, thereby keeping the phase shift the same in the
most critical frequency range of the feedback loop. The
output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
overall supply performance. Figure 19 illustrates the load
step response of a properly compensated boost converter.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the converter:
1. For lower power applications a 2-layer PC board is sufficient. However, for higher power levels, a multilayer
PC board is recommended. Using a solid ground plane
and proper component placement under the circuit is
the easiest way to ensure that switching noise does
not affect the operation.
2. In order to help dissipate the power from the MOSFETs
and diodes, keep the ground plane on the layers closest to the power components. Use power planes for
the MOSFETs and diodes in order to maximize the heat
spreading from these components into the PCB.
3. Place all power components in a tight area. This will
minimize the size of high current loops. The high di/
dt loops formed by the sense resistor, power MOSFET,
the boost diode and the output capacitor should be
kept as small as possible to avoid EMI.
4. Orient the input and output capacitors and current
sense resistors in a way that minimizes the distance
between the pads connected to the ground plane. Keep
the capacitors for INTVCC, DRVCC and VIN as close as
possible to LTC7840.
LOAD CURRENT
500mA/DIV
VIN = 12V
VOUT=36V
INDUCTOR CURRENT
500mA/DIV
20µs/DIV
7840 F19
Figure 19. Load Step Response of a Properly
Compensated Boost Converter
5. Place the DRVCC decoupling capacitor as close as possible to the DRVCC and PGND pins, on the same layer
as the IC. A low ESR (X5R or better) 4.7μF to 10μF
ceramic capacitor should be used.
6. Use a local via to ground plane for all pads that
connect to the ground. Use multiple vias for power
components.
30
Rev 0
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LTC7840
APPLICATIONS INFORMATION
7. Place the small-signal components away from high
frequency switching nodes on the board. The pinout
of the LTC7840 was carefully designed in order to
make component placement easy. All of the power
components can be placed on one side of the IC, away
from all of the small-signal components.
13. If an external RC filter is used between the sense resistor and the SENSE+ and SENSE– pins, these filter components should be placed as close as possible to the
SENSE+ and SENSE– pins of the IC. Ensure that the
SENSE– line is connected to the ground only at the
point where the current sense resistor is grounded.
8. The exposed area on the bottom of the package is
internally connected to SGND.
14. Keep the MOSFET drain nodes (SW1, SW2) away
from sensitive small-signal nodes, especially from the
opposite channel’s current-sensing signals. The SW
nodes can have slew rates in excess of 1V/ns relative
to ground and should therefore be kept on the “output
side” of the LTC7840.
9. The MOSFETs should also be placed on the same
layer of the board as the sense resistors. The MOSFET
source should connect to the sense resistor using a
short, wide PCB trace.
10. The output resistor divider should be located as close
as possible to the IC, with the bottom resistor connected between VFB pin and SGND. The PCB trace
connecting the top resistor to the upper terminal of
the output capacitor should avoid any high frequency
switching nodes.
11. Since the inductor acts like a current source in a peak
current mode control topology, its placement on the
board is less critical than the high di/dt components.
12. The SENSE+ and SENSE– PCB traces should be routed
parallel to one another with minimum spacing in
between all the way to the sense resistor. These traces
should avoid any high frequency switching nodes in
the layout. These PCB traces should also be Kelvinconnected to the interior of the sense resistor pads,
in order to avoid sensing errors due to parasitic PCB
resistance IR drops.
15. Check the stress on the power MOSFETs by independently measuring the drain-to-source voltages directly
across the devices terminals. Beware of inductive ringing that could exceed the maximum voltage rating of
the MOSFET. If this ringing cannot be avoided and
exceeds the maximum rating of the device, choose
a higher voltage rated MOSFET or consider using a
snubber.
16. When synchronizing the LTC7840 to an external clock,
use a low impedance source such as a logic gate to
drive the SYNC pin and keep the lead as short as
possible.
Rev 0
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31
LTC7840
APPLICATIONS INFORMATION
VIN
12V
10µH
SER2918H-103KL
+
4.7µFx4
100V
1210
33µF
63V
84.5k
RUN1
GATE1
VIN
12.1k
73.2k
0.1µF
100pF
33nF
15k
2.2µF
100pF
47nF
46.4k
11.8k
10Ω
SENSE1+
12.1k
475k
0805
ILIM1
VFB1
FREQ
SS1
ITH1
SS2
V8P10
SW1
BSC047N08
2mΩ
2010
10nF
SENSE1–
INTVCC
LTC7840
SGND
DRVCC
PGND
BLANK
CLKOUT
GATE2
SYNC
+
SENSE2
DMAX
ITH2
ILIM2
VFB2
–
2.37M RUN2 PGOOD1 PGOOD2 SENSE2
1206
VOUT1
48V
4.7µFx7
100V
1210
+
1mΩ
2010
33µFx2
80V
1nF
+
33µF
80V
100µH
PCV-2-104-05L
IDD04SG60C
10µF
0805
SW2
STB45N40DM2AG
2.2µFx4
450V
2220
10Ω
+
8mΩ
2010
10nF
VOUT
240V
0.7A
100µF
x2
400V
7840 F20
Figure 20. 12V Input, 240V/0.7A Output Two-Stage Boost Converter
Design Example
A two-stage step up converter is shown in Figure 20. The
two channels of LTC7840 are connected in cascade, i.e.,
the output of Channel 1 is tied to the input of Channel 2.
The output voltage of Channel 1 is 48V and the output
voltage of Channel 2 is 240V. The input voltage range
of Channel 1 is 9V to 36V. The maximum output current
of Channel 2 is 0.7A when the input voltage of Channel
1 is 12V.
2. The operating frequency is chosen to be 150kHz so
the period is 6.67μs. From Figure 6, the resistor from
the FREQ pin to SGND is 73.2k.
3. Channel 2 maximum DC input current is:
IIN2(MAX) =
IIN1(MAX) =
O1
F
⎛ 48V + 0.5V – 12V ⎞
=⎜
= 75.3%
⎝ 48V + 0.5V ⎟⎠
⎛ 48V + 0.5V – 36V ⎞
DMIN1 = ⎜
= 25.8%
⎝ 48V + 0.5V ⎟⎠
⎛V +V –V ⎞
DMAX2 = ⎜ O2 F O1⎟
⎝ VO2 + VF ⎠
32
⎛ 240V + 0.5V – 48V ⎞
=⎜
= 80%
⎝ 240V + 0.5V ⎟⎠
1– DMAX2
=
0.7A
1– 0.8
= 3.5A
Channel 1 maximum DC input current is:
1. The duty cycle range is:
⎛V +V –V ⎞
DMAX1 = ⎜ O1 F IN1⎟
⎝ V +V
⎠
IO2(MAX)
IO1(MAX)
1– DMAX1
=
IIN2(MAX)
1– DMAX1
=
3.5A
1– 0.753
= 14.17A
4. A ripple current of 40% is chosen so the peak current
in each inductor is:
⎛ 0.4 ⎞
⎛ χ⎞
IL1(PK) = ⎜ 1+ ⎟ •IIN1(MAX) = ⎜ 1+
⎟ • 14.17A
⎝
⎝ 2⎠
2 ⎠
= 17A
⎛ 0.4 ⎞
⎛ χ⎞
IL2(PK) = ⎜ 1+ ⎟ •IIN2(MAX) = ⎜ 1+
⎟ • 3.5A
⎝
⎝ 2⎠
2 ⎠
= 4.2A
Rev 0
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LTC7840
APPLICATIONS INFORMATION
5. The inductor peak-to-peak ripple current is:
∆IL1 = 40% • IIN1(MAX ) = 0.4 • 14.17A = 5.67A
∆IL2 = 40% • IIN2(MAX ) = 0.4 • 3.5A = 1.4A
6. The inductor value is therefore:
L1 =
VIN1
∆IL1 • f
• DMAX1 =
12V
5.67A • 150kHz
• 0.753
= 10.62µH
L2 =
VIN2
∆IL2 • f
• DMAX2 =
48V
1.4A • 150kHz
• 0.8
= 183µH
7. For a current limit value 30% higher than the maximum load current, the saturation current rating of the
inductors must therefore exceed:
I L1(SAT) ≥ 1.3 • I L1(PK ) = 1.3 • 17A = 22.1A
I
L2(SAT)
9. The total IC quiescent current, IC power dissipation and
maximum junction temperature are approximately:
IQ(TOT) = IQ + QG1(TOT) • f + QG2(TOT) • f
= 3mA + 52nC • 150kHz + 56nC • 150kHz
= 19.2mA
PDISS = 12V • 19.2mA = 230.4mW
TJ = 70°C + 230.4mW • 30°C/W = 76.9°C
10. For a current limit set at 30% above the maximum
load current, the peak switch and sense resistor currents are:
ISW1(PK) = IR1(PK) = 1.3 • IL1(PK) = 1.3 • 17A = 22.1A
ISW2(PK) = IR2(PK) = 1.3 • IL2(PK) = 1.3 • 4.2A = 5.46A
11. The maximum current sense threshold for the
LTC7840 is 75mV when ILIM1 and ILIM2 pins are
floating. This threshold keeps constant over duty
cycle. The sense resistor is calculated to be:
≥ 1.3 • I L2(PK ) = 1.3 • 4.2A = 5.46A
In order to obtain higher efficiency with acceptable
ripple, the Channel 1 inductor value chosen is 10µH
and the part number is SER2918H-103KL. This
inductor has a saturation current rating of 28A. The
Channel 2 inductor chosen is 100µH and the part
number is PCV-2-104-05L.
8. The power MOSFET of Channel 1 chosen for this
application is an Infineon BSC047N08. This MOSFET
has a typical RDS(ON) of 3.9mΩ at VGS = 10V. The
BVDSS is rated at a minimum of 80V and the maximum continuous drain current is 100A. The typical
gate charge is 52nC for VGS = 0V to 10V. The power
MOSFET of Channel 2 chosen for this application is an
STMicroelectronics STB45N40DM2AG. This MOSFET
has a typical RDS(ON) of 63mΩ at VGS = 10V. The
BVDSS is rated at a minimum of 400V and the maximum continuous drain current is 38A. The typical
gate charge is 56nC for VGS = 10V.
R SENSE1 =
R SENSE2 =
VSENSE(MAX)
ISW1(PK )
VSENSE(MAX)
ISW2(PK )
=
=
75mV
= 3.4mΩ
22.1A
75mV
5.46A
= 13.7mΩ
For this application, a 2mΩ surface mount resistor
is used for Channel 1 and an 8mΩ surface mount
resistor is used for Channel 2.
12. The power dissipation in the sense resistors at current
limit is:
(
PR1(SENSE) = 1.3 • IIN1(MAX)
)
2
• R SENSE1 • DMAX1
2
= ( 1.3 • 14.17A ) • 2mΩ • 0.753
= 0.51W
(
PR2(SENSE) = 1.3 • IIN2(MAX)
)
2
• R SENSE2 • DMAX2
2
= ( 1.3 • 3.5A ) • 8mΩ • 0.8
= 0.13W
Rev 0
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33
LTC7840
APPLICATIONS INFORMATION
13. The average current in the boost diodes is half the
output current:
I D1 =
I D2 =
IO1(MAX)
2
IO2(MAX)
2
=
=
3.5A
2
= 1.75A
0.7A
2
= 0.35A
15. Two types of output capacitors are connected in parallel for this application; a low ESR ceramic capacitor
and an aluminum electrolytic for bulk storage. For a
1% contribution to the total ripple voltage, the maximum ESR of the composite output capacitance is
approximately:
14. The peak current in each boost diode is:
ID1(PK) = IL1(PK) = 17A
The diode chosen for Channel 1 is the V8P10, manufactured by Vishay General Semiconductor. This surface mount diode has a maximum average forward
current of 8A at 25°C and a maximum reverse voltage
of 100V. The maximum forward voltage at 25°C is
0.522V at 25°C and 0.466V at 125°C when forward
current is 4A. The diode chosen for Channel 2 is the
IDD04SG60C, manufactured by Infineon. This diode
has a maximum average forward current of 4A when
temperature is lower than 130°C and a maximum
reverse voltage of 600V at 25°C. The maximum forward voltage at 25°C is 2.1V at 25°C and 2.8V at
125°C when forward current is 4A.
The power dissipated by the diode is approximately:
PD1 = ID1(PK) • VF1(PK) • (1 – DMAX1)
= 17A • 0.466V • (1 – 0.753) = 1.96W
PD2 = ID2(PK) • VF2(PK) • (1 – DMAX2)
= 4.2A • 2.8V • (1 – 0.8) = 2.35W
34
ID1(PK)
ESR COUT2 ≤
ID2(PK) = IL2(PK) = 4.2A
0.01• VOUT1
ESR COUT1 ≤
=
0.01• VOUT2
ID2(PK)
=
0.01• 48V
17A
= 0.028Ω
0.01• 240V
4.2A
= 0.57Ω
For the bulk capacitance, which we assume contributes 1% to the total output ripple, the minimum
required capacitance is approximately:
COUT1 ≥
IO1(MAX)
0.01• VOUT1 • f
=
3.5A
0.01• 48V • 150kHz
= 48.6µF
COUT2 ≥
IO2(MAX )
0.01• VOUT2 • f
=
0.7A
0.01• 240V • 150kHz
= 1.94µF
For this application, in order to obtain both low ESR
and an adequate ripple current rating, Channel 1 has
two 33µF, 80V aluminum electrolytic capacitors connected in parallel with seven 4.7µF, 100V ceramic
capacitors. Channel 2 has two 100µF, 400V aluminum
electrolytic capacitors connected in parallel with four
2.2µF, 450V ceramic capacitors.
Rev 0
For more information www.analog.com
LTC7840
TYPICAL APPLICATIONS
+
33µF
63V
4.7µFx4
100V
1210
•
158k
0.22µF
330pF
6.8nF
VFB1
FREQ
SS1
0.1µF
VIN
GATE1
SENSE1+
BLANK
CLKOUT
SYNC
DMAX
ITH1
RUN1
RUN2
15.4k
100pF
SS2
ILIM1
SENSE1–
INTVCC
LTC7840
SGND
DRVCC
PGND
MBR560MFS
BSC014N06NS
+
10Ω
10nF
5mΩ
2010
6.8µFx2
50V
X7R 1812
15k
VFB2
12.1k
475k
330µF
16V
10µH
SER2918H-103KL
V8P10
4.7µF
10Ω
10nF
–
PGOOD1 PGOOD2 SENSE2
VOUT2
48V/1A
4.7µFx7
100V
1210
BSC047N08
SENSE2+
ILIM2
VOUT1
12V/2A
1nF
GATE2
ITH2
33nF
6.8µH
WURTH 744870006
6.8µFx4
50V
X7R 1812
118k
13k
•
VIN
9V
2mΩ
2010
33µFx2
80V
+
7840 TA02
Figure 21. Dual Output 12V/2A, 48V/1A Converter with Channel 1 Configured as SEPIC and Channel 2 Configured as Boost Converter
Rev 0
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35
LTC7840
PACKAGE DESCRIPTION
FE Package
28-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev L)
Exposed Pad Variation EA
9.60 – 9.80*
(.378 – .386)
7.56
(.298)
7.56
(.298)
28 2726 25 24 23 22 21 20 19 18 1716 15
6.60 ±0.10
4.50 ±0.10
3.05
(.120)
SEE NOTE 4
0.45 ±0.05
EXPOSED
PAD HEAT SINK
ON BOTTOM OF
PACKAGE
6.40
3.05 (.252)
(.120) BSC
1.05 ±0.10
0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50*
(.169 – .177)
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN MILLIMETERS
(INCHES)
3. DRAWING NOT TO SCALE
36
1 2 3 4 5 6 7 8 9 10 11 12 13 14
0.25
REF
1.20
(.047)
MAX
0° – 8°
0.65
(.0256)
BSC
0.195 – 0.30
(.0077 – .0118)
TYP
0.05 – 0.15
(.002 – .006)
FE28 (EA) TSSOP REV L 0117
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
Rev 0
For more information www.analog.com
LTC7840
PACKAGE DESCRIPTION
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev C)
0.70 ±0.05
4.50 ±0.05
3.10 ±0.05
2.50 REF
2.65 ±0.05
3.65 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
3.50 REF
4.10 ±0.05
5.50 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 ±0.10
(2 SIDES)
0.75 ±0.05
R = 0.05
TYP
PIN 1 NOTCH
R = 0.20 OR 0.35
× 45° CHAMFER
2.50 REF
R = 0.115
TYP
27
28
0.40 ±0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
5.00 ±0.10
(2 SIDES)
3.50 REF
3.65 ±0.10
2.65 ±0.10
(UFD28) QFN 0816 REV C
0.25 ±0.05
0.200 REF
0.50 BSC
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGHD-3).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
Rev 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No licenseFor
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
more by
information
www.analog.com
37
LTC7840
TYPICAL APPLICATION
12V Input, 24V/2A Output 2-Phase Boost Converter
VIN
12V
+
RUN1
RUN2
VFB1
VFB2
BLANK
CLKOUT
SYNC
DMAX
FREQ
226k
12.1k
100k
SS1
SS2
0.47µF
100pF
68µF
63V
14.2k
6.8nF
ITH1
ITH2
PGOOD1
PGOOD2
4.7µFx4
100V
1210
VIN
GATE1
82µH
WURTH
7447709820
BSC047N08NS
SENSE1+
ILIM1
SENSE1–
INTVCC
LTC7840
B560C-13-F
SGND
DRVCC
PGND
4.7µFx4
50V
10Ω
10nF
68µF
35V
82µH
WURTH 7447709820
VOUT
24V/2A
1nF
B560C-13-F
4.7µF
BSC047N08NS
GATE2
4.7µFx4
50V
10Ω
SENSE2+
ILIM2
+
20mΩ
10nF
SENSE2–
20mΩ
+
68µF
35V
7840 TA04
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC3788/LTC3788-1
Dual Output, Low IQ Multiphase Synchronous
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4.5V (Down to 2.5V after Start-Up) ≤ VIN ≤ 38V, VOUT up to 60V, 50kHZ to
900kHz Fixed Operating Frequency, 5mm x 5mm QFN-32, SSOP-28
LTC3787
Single Output, Low IQ Multiphase Synchronous 4.5V (Down to 2.5V after Start-Up) ≤ VIN ≤ 38V, VOUT up to 60V, 50kHZ to
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900kHz Fixed Operating Frequency, 4mm x 5mm QFN-28, SSOP-28
LTC3769
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4.5V (Down to 2.3V after Start-up) ≤ VIN ≤ 60V, VOUT up to 60V, 50kHZ to 900kHz
Fixed Operating Frequency, 4mm x 4mm QFN-24, TSSOP-20
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Synchronous Boost Controller
4.5V (Down to 2.3V after Start-Up) ≤ VIN ≤ 60V, VOUT up to 60V, 50kHZ to
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Single Output, Multiphase Non-synchronous
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2.9V ≤ VIN ≤ 40V/100V, 100kHz to 1MHz Fixed Operating Frequency, 3mm x 3mm
DFN-10 and MSOP-10E
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Flyback and SEPIC Controller
LTC1871-7
2.5V ≤ VIN ≤ 36V, 50kHz to 1MHz Fixed Operating Frequency, MSOP-10
LTC7815
Low IQ, Up to 2.25MHz, Triple Output Buck/
Buck/Boost Synchronous DC/DC Controller
All Outputs Remain in Regulation Through Cold Crank, 4.5V (Down to 2.5V after
Start-up) ≤ VIN ≤ 38V, VOUT(BUCKS) Up to 24V, VOUT(BOOST) Up to 60V, IQ = 28µA
LTC3789
High Efficiency Synchronous 4-Switch BuckBoost DC/DC Controller
4V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 38V, SSOP-28, 4mm x 5mm QFN-28, SSOP-28
LT8710
Synchronous SEPIC/ Inverting/Boost Controller 4V ≤ VIN ≤ 80V, SSOP-28, TSSOP-20
with Output Current Control
38
Rev 0
D16991-0-7/18(0)
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For more information www.analog.com
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