LTC7883
Quad Output PolyPhase
Step-Down DC/DC Voltage Mode Controller
with Digital Power System Management
FEATURES
DESCRIPTION
PMBus/I2C Compliant Serial Interface
n Monitor Voltage, Current, Temperature and Faults
n Program Voltage, Soft-Start/Stop, Sequencing,
Margining, AVP and UV/OV/OC Limits
n 3V ≤ VINSNS ≤ 38V, 0.1V (Limited by DrMOS
tON_MIN) ≤ VOUT ≤ 5.25V
n ±0.5% Output Voltage Error
n Programmable PWM Frequency or External Clock
Synchronization from 250kHz to 2.5MHz
n Accurate PolyPhase® Current Sharing
n Internal EEPROM with Fault Logging and ECC
n IC Supply Range: 3V to 13.2V
n Resistor or Inductor DCR Current Sensing
n Power Good Output Voltage Monitor
n Supports Start-Up Into a Prebiased Load
n Optional Resistor Programming for Key Parameters
n 99-Lead BGA Package (9mm × 7.5mm)
The LTC®7883 is a quad, PolyPhase DC/DC synchronous
step-down switching regulator controller with PMBus
compliant serial interface. It uses a constant frequency,
leading-edge modulation, voltage mode architecture for
excellent transient response and output regulation. Each
PWM channel can produce output voltages from 0.1V
to 5.25V using a wide range of 3.3V compatible power
stages, including power blocks, DrMOS or discrete FET
drivers. LTC7883 devices can operate in parallel, supporting ideal phasor positioning for PolyPhase rails up
to 8-phases.
n
System configuration and monitoring is supported by the
LTpowerPlay® software tool. The LTC7883 serial interfaces
can read back input voltage, output voltage and current,
temperature and fault status. Most operating parameters
can be set via the digital interfaces or stored in internal
EEPROM for use at power-up. Switching frequency and
phase, output voltage and device address can also be set
using external configuration resistors.
APPLICATIONS
High Current Distributed Power Systems
Servers, Network and Storage Equipment
n Intelligent Energy Efficient Power Regulation
n
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. patents, including 5396245, 5859606, 6144194, 6937178, 7420359 and 7000125.
n
TYPICAL APPLICATION
VIN
7V TO 13.2V
VCCA VINSA
VSNSA0P
FBA0
1/2 LTC7883
SDA_A
TO/FROM
MCU
SCL_A
ALERTA
RUNA0
RUNA1
PGA0
FLTA0
TO/FROM
EXTERNAL DEVICES
PGA1
FLT1A1
SYNCA
CLKA
IAVGA0
IAVGA1
IAVGNDA
FDMF5820DC
PWM
VIN
SW
L0
COMPA0
VOUT
1V
100A
COMPA1
IOUT
10A/DIV
GND
PWMA0
Load Step Transient Current Sharing
(Using FDMF5820DC DrMOS)
TSNSA0
CSA0P
CSA0M
VSNSA1P
CSA1M
CSA1P
PWMA1
FDMF5820DC
PWM
TSNSA1
VSNSA0M
V
GND SNSA1M
7883 TA01a
IL0, IL1
10A/DIV
VIN
SW
L1
50µs/DIV
7883 TA01b
GND
INDUCTORS: COOPER FP1007R1-R22
SOME DETAILS OMITTED FOR CLARITY
Rev. 0
Document Feedback
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1
LTC7883
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
VCC[A/B] Supply........................................... –0.3V to 15V
VINS[A/B]................................................... –0.3V to 40V
VSNS[A/B][1:0]M............................................... –0.3V to 1V
VSNS[A/B][1:0]P, CS[A/B][1:0]P/M.................... –0.3V to 6V
FB[A/B][1:0], COMP[A/B][1:0],
TSNS[A/B][1:0], IAVGND[A/B],
IAVG[A/B][1:0]....................................... –0.3V to 3.6V
SYNC[A/B], FLT[A/B][1:0], WP[A/B],
PG[A/B][1:0], SHCLK[A/B]..................... –0.3V to 3.6V
SCL[A/B], SDA[A/B], RUN[A/B][1:0],
ALERT[A/B]............................................. –0.3V to 5.5V
ASEL0[A/B], ASEL1[A/B],
VO[A/B][1:0]CFG, FCFG[A/B],
PCFG[A/B]........................................... –0.3V to 2.75V
PWM[A/B][1:0], VDD25[A/B]............................... (Note 13)
VDD33[A/B]......................................................... (Note 14)
Operating Junction Temperature
(Notes 2, 3)....................................... –40°C to 125°C*
Storage Temperature Range............. –65°C to 150°C*
Absolute Maximum Junction Temperature........ 125°C
PIN 1
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
H
J
BGA PACKAGE
99-LEAD (9mm × 7.5mm × 1.29mm)
TJMAX = 125°C, θJA = 32°C/W,
θJCtop = 17°C/W, θJCbottom = 12.1°C/W, θJB = 14.5°C/W,
WEIGHT = TBDg,
θ VALUES DETERMINED PER JEDEC 51-9, 51-12
*See Derating EEPROM Retention at Temperature in the
Applications Information section for junction temperatures in excess of 125°C.
ORDER INFORMATION
PART MARKING*
PART NUMBER
LTC7883AY#PBF
PAD OR BALL FINISH
SAC305 (RoHS)
DEVICE
FINISH CODE
PACKAGE
TYPE
LTC7883Y
e1
BGA
• Contact the factory for parts specified with wider operating temperature
ranges. *The temperature grade is identified by a label on the shipping
container.
• Pad or ball finish code is per IPC/JEDEC J-STD-609.
2
MSL
RATING
3
OPERATING JUNCTION
TEMPERATURE RANGE
–40°C to 125°C
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures
• LGA and BGA Package and Tray Drawings
Rev. 0
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LTC7883
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). Specifications apply to both units with VCC = 5V,
VSNSP = 1.8V, VSNSM = IAVGND = GND = 0V, fSYNC = 500kHz (externally driven) unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCC
VCC Voltage Range
VDD33 = Internal LDO
VDD33_EXT
VDD33 Voltage Range
VCC = VDD33 (Note 6)
l
4.5
13.8
V
VUVLO
Undervoltage Lockout Threshold
VDD33 Rising
Hysteresis
l
3
3.6
IQ
IC Operating Current
per Unit
32
mA
tINIT
Controller Initialization Time
Delay from RESTORE_USER_ALL, MFR_RESET or VDD33
> VUVLO Until TON_DELAY Can Begin
35
ms
IC Supply
42
3
V
V
mV
VDD33 Linear Regulators
VDD33
VDD33 Regulator Output Voltage
VCC ≥ 4.5V
IDD33
VDD33 Current Limit
VDD33 = 2.8V
VDD33 = 0V
3.2
3.3
3.4
85
40
V
mA
mA
VDD25 Linear Regulators
VDD25
VDD25 Regulator Output Voltage
IDD25
VDD25 Current Limit
2.25
2.5
2.75
95
V
mA
PWM Control Loops
VINS
VIN Sense Voltage Range
RVINS
VINS Input Resistance
278
VOUT_R0
Range 0 Maximum VOUT
Range 0 Set Point Error (Note 7)
Range 0 Set Point Resolution
0.6V ≤ VOUT ≤ 5V
5.25
Range 1 Maximum VOUT
Range 1 Set Point Error (Note 7)
Range 1 Set Point Resolution
0.6V ≤ VOUT ≤ 2.5V
VOUT_R1
IVSNS
VSNS Input Current
3
l
–0.5
–0.5
l
VSNSP = 5.5V
VSNSM = 0V
38
1.375
2.65
0.6875
kΩ
0.5
V
%
mV
0.5
V
%
mV
235
–335
VLINEREG
VCC Line Regulation, No Output Servo
4.5V ≤ VCC ≤ 13.2V (See Test Circuit)
–0.02
AVP
AVP ∆VOUT
AVP = 10%, VOUT_COMMAND = 1.8V,
CS Differential Step 3mV to 12mV
with IOUT_OC_WARN_LIMIT = 15mV
–118
–108
V
µA
µA
0.02
%/V
–96
mV
AV(OL)
Error Amplifier Open-Loop Voltage Gain
87
dB
SR
Error Amplifier Slew Rate
9.5
V/µs
f0dB
Error Amplifier Bandwidth
(Note 12)
30
MHz
ICOMP
Error Amplifier Output Current
Sourcing
Sinking
–2.6
34
mA
mA
RVSFB
Resistance Between VSNSP and FB
Range 0
Range 1
VISENSE
CS Differential Input Range
IISENSE
CSP/M Input Current
0V ≤ VPIN ≤ 5.5V
IAVG_VOS
IAVG Current Sense Offset
Referred to CS Inputs
VSIOS
Slave Current Sharing Offset
Referred to CS Inputs
fSYNC
SYNC Frequency Error
250kHz ≤ fSYNC ≤ 1.25MHz
l
l
52
37
67
49
83
61
±70
–1
–600
–800
l
–10
±0.1
±175
±300
kΩ
kΩ
mV
1
µA
650
µV
µV
700
µV
µV
10
%
Rev. 0
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3
LTC7883
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). Specifications apply to both units with VCC = 5V,
VSNSP = 1.8V, VSNSM = IAVGND = GND = 0V, fSYNC = 500kHz (externally driven) unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input Voltage Supervisor
VON_TOL
Input ON/OFF Threshold Error
NVON
Input ON/OFF Threshold Resolution
15V ≤ VIN_ON ≤ 35V
l
–2
2
143
%
mV
Output Voltage Supervisors
VUVOV_R0
Range 0 Maximum Threshold
Range 0 Error
Range 0 Threshold Resolution
Range 0 Threshold Hysteresis
VUVOV_R1
Range 1 Maximum Threshold
Range 1 Error
Range 1 Threshold Resolution
Range 1 Threshold Hysteresis
Output Current Supervisors
Output Current Limit Tolerance
VILIM_TOL
CSP – CSM
CSP – CSM Threshold Resolution
NlLIM
ADC Readback Telemetry (Note 8)
VINS Readback Resolution
NVIN
VINS Total Unadjusted Readback Error
VIN_TUE
2V ≤ VOUT ≤ 5V (Falling for UV and Rising for OV)
l
1V ≤ VOUT ≤ 2.5V (Falling for UV and Rising for OV)
l
15mV < CSP – CSM ≤ 30mV
30mV < CSP – CSM ≤ 50mV
50mV < CSP – CSM ≤ 70mV
1LSB
l
l
l
–1
–1
5.5
11
50
2.75
5.5
25
–1.7
–2.5
–5.2
0.4
(Note 9)
4.5V ≤ VINS ≤ 38V
PWM Duty Cycle Resolution
PWM Duty Cycle Total Unadjusted
Readback Error
VOUT Readback Resolution
VOUT Total Unadjusted Readback Error
(Note 9)
PWM Duty Cycle = 12.5%
NISENSE
IOUT Readback Resolution
LSB Step Size (at ISENSE±)
ISENSE_TUE
ISENSE_OS
NTEMP
TEXT_TUE
IOUT Total Unadjusted Readback Error
IOUT Zero-Code Offset Voltage
Temperature Resolution
External Temperature Total Unadjusted
Readback Error
(Note 9)
0mV ≤ |CSP – CSM| < 16mV
16mV ≤ |CSP – CSM| < 32mV
32mV ≤ |CSP – CSM| < 63.9mV
63.9mV ≤ |CSP – CSM| ≤ 70mV
|CSP – CSM| ≥ 6mV, 0V ≤ VOUT ≤ 5.5V
NVOUT
VOUT_TUE
10
0.5
2
10
–2
0.6V ≤ VOUT ≤ 5.5V, Constant Load
l
Internal Temperature Total Unadjusted
Readback Error
Update Rate
tCONVERT
Internal EEPROM (Notes 4, 6)
Endurance
Number of Write Operations
Retention
Stored Data Retention
Mass Write Time STORE_USER_ALL Execution Duration
TINT_TUE
4
TSNS ≤ 1.85V (Note 10)
MFR_PWM_MODE_LTC3882-1[6] = 0
MFR_PWM_MODE_LTC3882-1[6] = 1
Internal Diode (Note 10)
–0.5
l
l
l
2
244
±0.2
0.5
10
15.625
31.25
62.5
125
±1
±32
0.25
–3
–7
(Note 11)
0°C ≤ TJ ≤ 85°C During All Write Operations
TJ ≤ 125°C
0°C ≤ TJ ≤ 85°C During All Write Operations
1
1.7
2.5
5.2
l
NDC
DCTUE
1
3
7
V
%
mV
mV
V
%
mV
mV
mV
mV
mV
mV
Bits
%
%
Bits
%
µV
%
%
Bits
µV
µV
µV
µV
%
µV
°C
±1
°C
°C
°C
90
ms
0.2
Cycles
Years
s
10,000
10
2
Rev. 0
For more information www.analog.com
LTC7883
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). Specifications apply to both units with VCC = 5V,
VSNSP = 1.8V, VSNSM = IAVGND = 0V, fSYNC = 500kHz (externally driven) unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
Digital Inputs (SCL, SDA, RUN, FLT, SYNC, SHCLK, WP)
Input High Voltage
SCL, SDA, RUN, FLT
VIH
SYNC, SHCLK, WP
Input Low Voltage
SCL, SDA, RUN, FLT
VIL
SYNC, SHCLK, WP
MIN
l
l
TYP
MAX
1.35
1.8
0.8
0.6
l
l
UNITS
V
V
V
V
VHYST
Input Hysteresis
SCL, SDA
80
mV
ILKG
Input Pull-Up Current
WP = 0V
10
µA
CIN
Input Capacitance
SCL, SDA, RUN, FLT, SYNC, SHCLK (Note 12)
tFILT
Input Digital Filter Delay
FLT
RUN
10
3
10
pF
µs
µs
Digital Outputs (SCL, SDA, RUN, FLT, SYNC, SHCLK, ALERT, PWM, PG)
VOL
Output Low Voltage
ISINK = 3mA; SCL, SDA, RUN, FLT, SYNC, SHCLK, ALERT l
l
ISINK = 2mA; PWM, PG
VOH
PWM Output High Voltage
ISOURCE = 2mA
ILKG
Output Leakage Current
0V ≤ PWM, PG ≤ VDD33
0V ≤ FLT, SYNC, SHCLK ≤ 3.6V
0V ≤ RUN ≤ 5.5V
0V ≤ SCL, SDA, ALERT ≤ 5.5V
tRO
PWM Output Rise Time
CLOAD = 30pF, 10% to 90%
5
ns
tFO
PWM Output Fall Time
CLOAD = 30pF, 90% to 10%
4
ns
l
0.2
V
V
1
5
µA
µA
5
µA
2.7
V
–1
–5
l
0.4
0.3
–5
Serial Bus Timing
fSMB
Serial Bus Operating Frequency
l
10
tBUF
Bus Free Time Between Stop and Start
l
1.3
µs
tHD,STA
Hold Time After (Repeated) Start
Condition. After This Period, the First
Clock Is Generated
l
0.6
µs
tSU,STA
Repeated Start Condition Setup Time
l
0.6
µs
tSU,STO
Stop Condition Setup Time
l
0.6
µs
tHD,DAT
Data Hold Time:
Receiving Data
Transmitting Data
l
l
0
0.3
tSU,DAT
Input Data Setup Time
l
100
tTIMEOUT
Clock Low Timeout
l
25
35
ms
tLOW
Serial Clock Low Period
l
1.3
10000
µs
tHIGH
Serial Clock High Period
l
0.6
400
0.9
kHz
ns
µs
ns
µs
Rev. 0
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5
LTC7883
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC7883 is specified over the –40°C to 125°C operating
junction temperature range. High Junction temperatures degrade operating
lifetimes; operating lifetime is derated for junction temperatures greater
than 125°C. Note the maximum ambient temperature consistent with
these specifications is determined by specific operating conditions in
conjunction with board layout, the rated package thermal impedance and
other environmental factors.
Note 3: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
the device.
Note 4: EEPROM endurance, retention and mass write times are
guaranteed by design, characterization and correlation with statistical
process controls. Minimum retention applies only for devices cycled less
than the minimum endurance specification. EEPROM read commands
(e.g. RESTORE_USER_ALL) are valid over the entire specified operating
junction temperature range.
Note 5: All currents into device pins are positive; all currents out of
device pins are negative. All voltages are referenced to GND unless
otherwise specified.
6
Note 6: Minimum EEPROM endurance, retention and mass write time
specifications apply when writing data with 3.15V ≤ VDD33 ≤ 3.45V.
EEPROM read commands are valid over the entire specified VDD33
operating range.
Note 7: Specified VOUT error with AVP = 0% requires servo mode to be
set with MFR_PWM_MODE_LTC3882-1 command bit 6. Performance is
guaranteed by testing the LTC7883 in a feedback loop that servos VOUT to
a specified value.
Note 8: ADC tested with PWMs disabled. Comparable capability
demonstrated by in-circuit evaluations. Total Unadjusted Error includes all
gain and linearity errors, as well as offsets.
Note 9: Internal 32-bit calculations using 16-bit ADC results are limited to
10-bit resolution by PMBus Linear 11-bit data format.
Note 10: Limits guaranteed by TSNS voltage and current measurements
during test, including ADC readback.
Note 11: Data conversion is done in round robin fashion. All inputs signals
are continuously scanned in sequence resulting in a typical conversion
latency of 90ms.
Note 12: Guaranteed by design.
Note 13: Do not apply a voltage or current source directly to these pins.
They should only be connected to passive RC loads, otherwise permanent
damage may occur.
Note 14: Do not apply a voltage source to this pin unless shorted to VCC.
See Electrical Characteristics for applicable limits beyond which permanent
damage may occur.
Rev. 0
For more information www.analog.com
LTC7883
TYPICAL PERFORMANCE CHARACTERISTICS
LTC7883 1.0V Regulated Output
vs Temperature
1000
NUMBER OF CHANNELS
VIN = 12V
VOUT_COMMAND = 1.0V
DIGITAL SERVO ENGAGED
1.0005 I
OUT = 6.5A
1.0
0.9995
0.999
1200
1094 UNITS
900 VOUT_COMMAND = 1.0V
DIGITAL SERVO
800 ENGAGED
700
1000
NUMBER OF CHANNELS
1.001
VOUT (V)
Typical LTC78883 Output Voltage
Distribution at 105°C
Typical LTC7883 Output Voltage
Distribution at 0°C
600
500
400
300
200
1078 UNITS
VOUT_COMMAND = 1.0V
DIGITAL SERVO
ENGAGED
800
600
400
200
100
0.9985
–5
15
35
55
TA (°C)
75
7883 G01
7883 G02
Efficiency vs Load Current
(1-Phase Using D12S1R880A
Power Block)
Efficiency and Loss vs Load
(2-Phase Using FDMF5820DC
DrMOS)
92
13
95
5
83
85
85
3.3V
2.5V
1.8V
1.5V
1.2V
1.0V
80
VIN = 12V
VOUT = 1V
SYNC = 500kHz
82
81
0
10
20
30 40 50 60
LOAD CURRENT (A)
70
3
80
1
75
0
10
7883 G04
75
65
1500
1500
–400 –300–200–100 0 100 200 300 400
CH1 ISENSE OFFSET TO IDEAL (µV)
7883 G07
0
11783 UNITS
FROM 3 LOTS
TJ = 121°C
CHO MASTER
3000
2500
2000
1500
1000
500
500
2
20 40 60 80 100 120 140 160 180 200
LOAD CURRENT (A)
3500
1000
1000
0
4000
NUMBER OF ICs
NUMBER OF ICs
2000
9
VIN = 12V
VOUT = 1V
4500
2000
16
Typical Distribution of Slave
IOUT Offset (Not Including DCR
Mismatch)
8593 UNITS
FROM 3 LOTS
3000 T = 38°C
J
CHO MASTER
2500
2500
23
7883 G06
3500
9595 UNITS
3500 FROM 3 LOTS
TA = –40°C
3000 TJ = –22°C
CHO MASTER
30
POWER LOSS
70
Typical Distribution of Slave
IOUT Offset (Not Including DCR
Mismatch)
4000
NUMBER OF ICs
80
60
37
EFFICIENCY 500kHz
EFFICIENCY 1MHz
POWER LOSS 500kHz
POWER LOSS 1MHz
7883 G05
Typical Distribution of Slave
IOUT Offset (Not Including DCR
Mismatch)
0
40
20
30
LOAD CURRENT (A)
EFFICIENCY (%)
84
EFFICIENCY (%)
EFFICIENCY (%)
85
44
POWER LOSS (W)
7
86
POWERLOSS (W)
87
51
EFFICIENCY
90
9
2.5
7883 G03
90
89
88
2
95
11
90
1.5
Efficiency and Loss vs Load
(4-Phase Using LTC7051)
VIN = 12V
91
80
0
–2.5 –2 –1.5 –1 –0.5 0 0.5 1
VOUT ERROR (mV)
0
–1.25 –1 –0.75–0.5–0.25 0 0.25 0.5 0.75 1 1.25
VOUT ERROR (mV)
95
500
–400 –300–200–100 0 100 200 300 400
CH1 ISENSE OFFSET TO IDEAL (µV)
7883 G08
0
–300 –200–100 0 100 200 300 400 500
CH1 ISENSE OFFSET TO IDEAL (µV)
7883 G09
Rev. 0
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7
LTC7883
TYPICAL PERFORMANCE CHARACTERISTICS
3-Phase DC Output Current
Sharing (Using D12S1R845A
Power Block
20
Load Step Transient Current
Sharing (Using FDMF6707B
DrMOS)
CHANNEL 1
CHANNEL 2
CHANNEL 3
18
16
IOUT
20A/DIV
IOUT
20A/DIV
14
PHASE CURRENT (A)
Load Dump Transient Current
Sharing (Using FDMF6707B
DrMOS)
VOUT
20mV/DIV
VOUT
20mV/DIV
12
IL1, IL2
10A/DIV
10
8
IL1, IL2
10A/DIV
6
4
VOUT = 1V
VIN = 12V
SYNC = 500kHz
L = 320nH
2
0
0
10
20 30 40 50 60
TOTAL RAIL CURRENT (A)
70
80
7883 G11
5µs/DIV
VOUT = 1V
VIN = 12V
SYNC = 500kHz
L = 320nH
5µs/DIV
7883 G12
7883 G10
Efficiency and Power Loss vs
Input Voltage
(1-Phase Using LTC4449)
100
3.0
VO = 1.8V
98
EFFICIENCY (%)
2.0
92
IOUT
(10A/DIV)
POWERLOSS (W)
94
VSW
(10V/DIV)
90
1.5
88
VOUT
(10mV/DIV)
1.0
86
84
80
VOUT
(20mV/DIV)
2.5
96
5
10
15
20
VIN (V)
25mVP-P
0.5
POWER FET: BSC050N04LS G
SYNC FET: BSC010N04LS
82
25
30
100µs/DIV
0
7883 G13
3+1 Channel Crosstalk
(Using D12S1R845A Power
Blocks)
VOUT0
(1-PHASE)
20mV/DIV
25%
LOAD STEP
100µs/DIV
7883 G16
2µs/DIV
VOUT = 0.9V/90A
VIN = 12V
SYNC = 500kHz
L = 210nH
VOUT = 1V/25A
VIN = 12V
SYNC = 1MHz
L = 210nH
Load Step Transient Response
Using AVP
Line Step Transient Response
(1-Phase Using LTC4449)
IO
10A/DIV
IOUT1
10A/DIV
IOUT
(10A/DIV)
7883 G14
VIN
2V/DIV
VOUT1
(3-PHASE)
20mV/DIV
8
1-Phase Single Cycle Response
(Using D12S1R860A Power Block
with COUT = 6 × 100µF X5R 1210)
3-Phase Transient Response
(Using D12S1R860A Power Block)
7883 G15
7V
1.8V
VOUT
50mV/DIV
VOUT
10mV/DIV
200µs/DIV
7883 G17
200µs/DIV
7883 G18
Rev. 0
For more information www.analog.com
LTC7883
TYPICAL PERFORMANCE CHARACTERISTICS
Soft-Start Ramp
Start-Up Into a Prebiased Load
VOUT
0.5V/DIV
VOUT
0.5V/DIV
0V
IL1, IL2
10A/DIV
IL1, IL2
10A/DIV
VIN = 12V
7883 G19
1ms/DIV
1.7995
RUN
2V/DIV
VOUT
1V/DIV
VIN = 12V
Regulated Output vs Temperature
1.8000
Soft-Off Ramp
7883 G20
1ms/DIV
VOUT_COMMAND INL
VOUT_COMMAND DNL
1.5
VOUT_COMMAND = 1.8V
DIGITAL SERVO OFF
1.0
0.8
1.0
0.6
0.4
1.7985
0.5
DNL (LSB)
INL (LSB)
VOUT (V)
1.7990
0
1.7980
0.2
0
–0.2
–0.4
–0.5
1.7975
–0.6
1.7970
–40 –20
0
20 40 60 80
TEMPERATURE (°C)
–1.0
0.3
100 120
1.1
1.9
7883 G22
Output Overvoltage Threshold
Error vs Temperature
0
–0.05
–0.10
VOUT_OV_FAULT_LIMIT = 2V
VOUT RANGE = 1
0
20 40 60 80
TEMPERATURE (°C)
4.3
–0.8
0.3
5.1
100 120
1.9
2.7
3.5
VOUT (V)
4.3
5.1
7883 G24
PWM Frequency vs Temperature
1.2
500.2
1.0
500.1
0.8
0.6
0.4
0.2
0
500.0
499.9
499.8
499.7
499.6
–0.2
–0.4
–40 –20
1.1
7883 G23
PWM FREQUENCY (kHz)
OUTPUT OC THRESHOLD ERROR (%)
0.05
–0.15
–40 –20
2.7
3.5
VOUT (V)
Output Overcurrent Threshold
Error vs Temperature
0.10
VOUT OV THRESHOLD ERROR (%)
7883 G21
5ms/DIV
TOFF_DELAY = 10ms
TOFF_FALL = 5ms
0
20 40 60 80
TEMPERATURE (°C)
100 120
7883 G25
7883 G26
499.5
–40 –20
FREQUENCY_SWITCH = 500kHz
0
20 40 60 80
TEMPERATURE (°C)
100 120
7883 G27
Rev. 0
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9
LTC7883
TYPICAL PERFORMANCE CHARACTERISTICS
–1
0.30
–2
–3
–4
–5
–6
–7
IOUT ADC TUE
8
6
0.20
0.10
0
–0.10
–0.20
–0.30
–8
–9
VOUT ADC TUE
MEASUREMENT ERROR (mA)
0.40
MEASUREMENT ERROR (mV)
MEASUREMENT ERROR (mV)
VINS ADC TUE
0
0
5
10
15 20 25
VINSNS (V)
30
35
40
Temperature ADC TUE
1
1.5
2
2.5 3 3.5
VOUT (V)
4
4.5
5
–2
–4
–8
5.5
10
5
15
OUTPUT CURRENT (A)
0
7883 G29
20
7883 G30
IC Operating Current vs
Temperature
31.0
110
0.8
VCC = 14V
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
ICC OPERATING CURRENT (mA)
30.8
SHCLK FREQUENCY (kHz)
MEASUREMENT ERROR (°C)
0
SHCLK Frequency vs Temperature
1.0
105
100
95
30.6
30.4
30.2
30.0
29.8
29.6
–0.8
–1.0
–45 –25 –5 15 35 55 75 95 115
ACTUAL TEMPERATURE (°C)
90
–50 –30 –10 10 30 50 70
TEMPERATURE (°C)
90
110
7883 G32
7883 G31
10
2
–6
–0.40
0.5
7883 G28
4
29.4
–40 –20
0
20 40 60 80
TEMPERATURE (°C)
100 120
7883 G33
Rev. 0
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LTC7883
LTC7883 PIN (BALL) ASSIGNMENTS
PIN NAME
BALL
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
B1
B2
B3
B4
B5
B6
UNIT A
VSNSA1P
VSNSA1M
VSNSA0M
VSNSA0P
ALERTA
VCCA
B7
B8
B9
B10
B11
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
E1
E2
E3
E4
E5
E6
E7
GND
RUNA0
RUNA1
PIN NAME
UNIT B
ALERTB
VSNSB1P
VSNSB1M
VSNSB0M
VSNSB0P
ASELA1
ASELA0
GND
ASELB1
ASELB0
GND
VCCB
GND
RUNB0
RUNB1
SDA_A
GND
PCFGA
FCFGA
GND
GND
SCL_A
SDA_B
GND
GND
PCFGB
VOB1CFG
GND
SCL_B
FLTA1
FLTA0
FLTB1
FLTB0
VOA0CFG
GND
GND
SYNCA
GND
FCFGB
VOB0CFG
GND
SYNCB
IAVGNDA
VDD25A
VOA1CFG
GND
GND
GND
GND
GND
GND
GND
GND
BALL
E6
E7
E8
E9
E10
E11
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
UNIT A
GND
GND
GND
GND
UNIT B
GND
GND
GND
GND
VDD25B
IAVGNDB
COMPA1
FBA1
VDD33A
SHCLKA
GND
WPA
SHCLKB
GND
WPB
VDD33B
FBB0
COMPB0
COMPA0
FBA0
PGA0
PGA1
GND
GND
GND
GND
PGB0
PGB1
FBB1
COMPB1
COMPB1
CSA1M
IAVGA0
IAVGA1
TSNSA1
TSNSA0
VINSA
IAVGB0
IAVGB1
TSNSB1
TSNSB0
PWMB0
CSA1P
PWMA1
CSA0M
CSA0P
PWMA0
VINSB
CSB1M
CSB1P
PWMB1
CSB0M
CSB0P
Rev. 0
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11
LTC7883
PIN FUNCTIONS
COMP[A/B][1:0]: Error Amplifier Outputs. PWM duty
cycle increases with this control voltage. These are true
low impedance outputs and cannot be directly connected
together when active. For PolyPhase operation, wiring
FB to VDD33 will three-state the error amplifier output of
that channel, making it a slave. PolyPhase control is then
implemented in part by connecting all slave COMP pins
together to one master error amplifier output.
TSNS[A/B][1:0]: External Temperature Sense Inputs. The
LTC7883 supports two methods of calculation of external temperature based on forward-biased P/N junctions
between these pins and GND.
VINS[A/B]: VIN Supply Sense. Connect to the VIN power
supply to provide line feedforward compensation. A
change in VIN immediately modulates the input to the
PWM comparator and inversely changes the pulse width
to provide excellent transient line regulation and fixed
modulator voltage gain. An external lowpass filter can be
added to this pin to prevent noisy signals from affecting
the loop gain.
IAVGND[A/B]: IAVG Ground Reference. The same IAVGND
should be shared between all channels of a PolyPhase
rail and connected to system ground at a single point.
IAVGND may be wired directly to GND on units that do
not share phases with other units.
PG[A/B][1:0]: Power Good Indicator Open-Drain Outputs.
These outputs are driven low through a 30µs filter when
the respective channel output is below its programmed
UV fault limit or above its programmed OV fault limit.
If used, a pull-up resistor is required in the application.
Operating voltage range is GND to VDD33.
PWM[A/B][1:0]: PWM Three-State Control Outputs.
These pins provide single-wire PWM switching control
for each channel to an external gate driver, DrMOS or
power block. Operating voltage range is GND to VDD33.
SYNC[A/B]: External Clock Synchronization Input and
Open-Drain Output. If desired, an external clock can
be applied to this pin to synchronize the internal PWM
channels. If an LTC7883 unit is configured as a clock
master, this pin will also pull to ground at the selected
12
PWM switching frequency with a 125ns pulse width. A
pull-up resistor to 3.3V is required in the application if
SYNC is driven by any LTC7883. Minimize the capacitance
on this line to ensure its time constant is fast enough for
the application.
SCL[A/B]: Serial Bus Clock Input. A pull-up resistor to
3.3V is required in the application.
SDA[A/B]: Serial Bus Data Input and Output. A pull-up
resistor to 3.3V is required in the application.
ALERT[A/B]: Open-Drain Status Output. This pin may
be connected to the system SMBALERT wire-AND interrupt signal and should be left open if not used. If used, a
pull-up resistor is required in the application. Operating
voltage range is GND to VDD33.
FLT[A/B][1:0]: Programmable Digital Inputs and OpenDrain Outputs for Fault Sharing. Used for channel-to-channel fault communication and propagation. These pins
should be left open if not used. If used, a pull-up resistor
to 3.3V is required in the application.
RUN[A/B][1:0]: Run Control Inputs and Open-Drain
Outputs. A voltage above 2V is required on these pins
to enable the respective PWM channel. The LTC7883 will
drive these pins low under certain reset/restart conditions
regardless of any PMBus command settings. A pull-up
resistor to 3.3V is required in the application.
ASELA[1:0]: Unit A Serial Bus Address Select Pins. Connect
optional 1% resistor dividers between VDD25A and GND
to these pins to select the serial bus interface address.
ASELB[1:0]: Unit B Serial Bus Address Select Pins. Connect
optional 1% resistor dividers between VDD25B and GND
to these pins to select the serial bus interface address.
VO[A/B][1:0]CFG: Output Voltage Configuration Pins.
Connect optional 1% resistor dividers between VDD25
and GND to these pins to select the output voltage for
each channel.
FCFG[A/B]: Frequency Configuration Pins. Connect an
optional 1% resistor divider between VDD25 and GND to
these pins to configure PWM switching frequency.
Rev. 0
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LTC7883
PIN FUNCTIONS
PCFG[A/B]: Phase Configuration Pins. Connect an
optional 1% resistor divider between VDD25 and GND to
these pins to configure the phase of each PWM channel
relative to SYNC.
VDD25[A/B]: Internal 2.5V Regulator Outputs. Bypass these
pins to GND with a low ESR 1µF capacitor. Do not short
these pins together or load them with external current
beyond that required for local LTC7883 configuration.
WP[A/B]: Write Protect Inputs. If WP is above 2V, PMBus
writes are restricted and any software WRITE_PROTECT
settings for that unit are overridden. These pins have an
internal 10µA pull-up to VDD33.
SHCLK[A/B]: Share Clock Open-Drain Outputs (bussed).
Share Clock, nominally 100kHz, is used to sequence multiple rails in a power system utilizing more than one ADI
PSM controller. A pull-up resistor is required in the application. Minimize the capacitance on this line to ensure the
time constant is fast enough for the application. Operating
voltage range is GND to VDD33.
VDD33[A/B]: Internal 3.3V Regulator Outputs. Bypass these
pins to GND with a low ESR 2.2µF capacitor. The LTC7883
may also be powered from an external 3.3V rail attached
to these pins, if also shorted to VCC[A/B]. Otherwise do not
short these pins together or overload them with external
system current. Local pull-up resistors for the LTC7883
itself may be powered from VDD33.
VCC[A/B] (Pin 25): 3.3V Regulator Input(s). Bypass these
pins, which may be shorted together, to GND with a capacitor (0.1µF to 1µF ceramic) in close proximity to the IC.
VSNS[A/B][1:0]M: Negative Output Voltage Sense Inputs.
These pins must still be properly connected on slave
channels for accurate output current telemetry.
VSNS[A/B][1:0]P: Positive Output Voltage Sense Inputs.
These pins must still be properly connected on slave
channels for accurate output current telemetry.
CS[A/B][1:0]M: Current Sense Amplifier Inputs. These (–)
inputs to the amplifiers are normally connected to the low
side of a DCR sensing network or output current sense
resistor for each phase.
CS[A/B][1:0]P: Current Sense Amplifier Inputs. These
(+) inputs are normally connected to the high side of an
output current sense resistor or the R-C midpoint of a
parallel DCR sense circuit for each phase.
IAVG[A/B][1:0]: Average Current Control Pins. A capacitor connected between these pins and IAVGND stores a
voltage proportional to the average output current of the
master channel. PolyPhase control is then implemented
in part by connecting all slave IAVG pins together to the
master IAVG output. This pin should be left open on channels that control single-phase outputs. Operating voltage
range is GND to 2.1V.
FB[A/B][1:0]: Error Amplifier Inverting Inputs. These pins
provide an internally scaled version of the output voltage
for use in loop compensation.
GND: Ground. All GND balls must be soldered to a suitable
PCB copper ground plane for proper electrical operation
and to obtain the specified package thermal resistance.
Rev. 0
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13
LTC7883
BLOCK DIAGRAM
(“A” Side, 1 of 2 Units)
ROM
RAM
EEPROM
VINSA
R_CONFIG
IAVGA0
MCU AND
CUSTOM
LOGIC
SHCLKA
PMBus
CSA0P/M
2.5V
REGULATOR
12-BIT
DAC
PWM0
VSNSA0P/M
PGA0
SYNCA
PWMA0
PLL
VOLTAGE
REFERENCE
VREF
IAVGNDA
3.3V
REGULATOR
VCCA
PWMA1
VDD33A
PGA1
BIAS AND
HOUSEKEEPING
IAVGA1
INTERNAL DATA BUS
VSNSA0P/M
16-BIT
ADC
CSA0P/M
VSNSA1P/M
PWM1
CSA1P/M
VINSA
PWMA0
TSNSA0
PWMA1
12-BIT
DAC
VSNSA1P/M
VINSA
ANALOG
MUX
INTERNAL
TEMPERATURE
CSA1P/M
TSNSA1
14
7883 BD
Rev. 0
For more information www.analog.com
LTC7883
TEST CIRCUIT
(Channel A0 Example)
LTC7883
1.024V
VR
12-BIT
D/A
DIGITAL
+
EA
–
VSNSA0P
VSNSA0M
A3
FBA0
A4
COMPA0
G2
G1
+
LTC1055
TARGET = VOUT_COMMAND
–
1V
7883 TC
TIMING DIAGRAM
SDA
tf
tLOW
tr
tSU(DAT)
tHD(SDA)
tf
tSP
tr
tBUF
SCL
tHD(STA)
START
CONDITION
tHD(DAT)
tHIGH
tSU(STA)
tSU(STO)
7883 TD
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
Rev. 0
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15
LTC7883
OPERATION
Overview
The LTC7883 is a quad channel constant frequency
analog voltage mode controller for DC/DC step-down
applications. It features PMBus compliant digital interfaces for monitoring and control of important power system parameters. The IC operates from power supplies
between 3V and 13.2V and is intended for conversion
from VIN between 3V and 38V to output voltages between
0.1V and 5.25V. It is designed to be used in a switching
architecture with external FET drivers, including higher
level integrations such as non-isolated power blocks.
Major features include:
• Digitally Programmable Output Voltage, Current Limit
and Related Supervisors
• Digitally Programmable Input Voltage Supervisor
• Digitally Programmable Switching Frequency with PLL
for Synchronous PolyPhase Operation Up to 8 Phases
• Digitally Programmable On and Off Delay Times
• Digitally Programmable Soft-Start/Stop
• Operating Condition Telemetry
• Warning and Fault Status with Fault Event Data Logging
• PMBus Revision 1.2 Compliant Interface Up to 400kHz
Internal Structure
The LTC7883 is comprised of two dual-channel units,
each equivalent to an LTC3882-1 with the added feature
of a hardware PMBus write protect for each unit.
Refer to the LTC3882-1 data sheet for a detailed description of operation, PMBus command set, and applications
information for each unit.
Refer to the LTC3888 data sheet for additional details on
operation of the WP pins and their interaction with the
PMBus WRITE_PROTECT command on each unit.
Unique Special ID
Each internal unit of the LTC7883 reports a unique MFR_
SPECIAL_ID to differentiate it from an LTC3882-1. Table 1
lists MFR_SPECIAL_ID values for these products. X is
adjustable by the manufacturer.
Table 1. MFR_SPECIAL_ID Values
• Fully Differential Load Sense
• Nonvolatile Configuration Memory with ECC Capable
of Standalone Operation
• Optional External Resistor Configuration of Key
Operating Parameters
16
• Optional Time-Base Interconnect for Synchronization
Between Multiple Controllers
DEVICE
MFR_SPECIAL_ID
MFR_MODEL
LTC3882-1
0x424X
LTC3882-1
LTC7883 Unit A
0x450X
LTC7883A
LTC7883 Unit B
0x451X
LTC7883B
Rev. 0
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LTC7883
OPERATION
Additional Identification Commands
The LTC7883 features a few new PMBus product identification commands as detailed in Table 2.
Switching Frequency and Phase
There is a high degree of flexibility for setting the PWM
operating frequency of the LTC7883. The switching frequency of the PWM can be established with an internal
oscillator or an external time base. The internal phaselocked loop (PLL) synchronizes PWM control to this
timing reference with proper phase relation, whether
the clock is provided internally or externally. The device
can also be configured to provide the master clock to
other ICs through PMBus command, EEPROM setting,
or external configuration resistors as outlined in application Table 6. For PMBus or EEPROM configuration, an
LTC7883 unit is designated as a clock master by clearing
bit 4 of MFR_CONFIG_ALL_LTC3882-1. As clock master,
an LTC7883 unit will drive its open-drain SYNC pin at the
selected rate with a pulse width of 125ns. An external
pull-up resistor between SYNC and VDD33 is required in
this case. Only one unit connected to SYNC should be
designated to drive the pin. If more than one LTC7883 unit
sharing SYNC is programmed as clock master, just one
of the units is automatically elected to provide the clock.
The others disable their SYNC outputs and indicate this
with bit 10 of MFR_PADS_LTC3882-1.
Unlike the LTC3882-1, which only allows a fixed set of
predetermined frequencies, the LTC7883 FREQUENCY_
SWITCH command supports a continuous range of values
from 250kHz to 2.5MHz. The special case of 0x0000 for
External SYNC Only is not permitted by the LTC7883.
Sending this FREQUENCY_SWITCH command value will
result in a CML fault for invalid data.
The LTC7883 will automatically accept an external SYNC
input, disabling is own SYNC drive if necessary, as long as
the external clock frequency is greater than 1/2 of the programmed internal oscillator. Whether configured to drive
SYNC or not, an LTC7883 unit can continue PWM operation at the selected frequency (FREQUENCY_SWITCH)
using its own internal oscillator if an expected external
clock signal is not present.
The MFR_PWM_CONFIG_LTC3882-1 command can be
used to configure the phase of each channel. Desired
phase can also be set from EEPROM or external configuration resistors as outlined in Table 6. Phase designates
the relationship between the falling edge of SYNC and the
internal clock edge that resets the PWM latch. That reset
turns off the top power switch, producing a PWM falling
edge. Additional small propagation delays to the PWM
control pins will apply.
Table 2. New Identification Commands
DEFAULT VALUE
COMMAND NAME
CMD CODE
DESCRIPTION
TYPE
PAGED
DATA FORMAT
UNIT A
UNIT B
ID_DEVICE_ID
0xAD
LTC7883 Model Number
R String
N
ASC
LTC7883A
LTC7883B
ID_DEVICE_REV
0xAE
LTC7883 Device Revision
Code
R String
N
ASC
C0001
C0001
Rev. 0
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17
LTC7883
OPERATION
The phase relationships and frequency are independent
of each other, providing numerous application options.
Multiple LTC7883 units/ICs can be synchronized to realize a PolyPhase array. In this case the phases should be
separated by 360/n degrees, where n is the number of
phases driving the output voltage rail.
Serial Bus Addressing
The LTC7883 supports four types of serial bus addressing
schemes to access the individual PWM channels separately or jointly.
• Global Bus Addressing
• Power Rail Addressing
• Individual Unit (Device) Addressing
• Page+ Channel Addressing
Each internal unit of the LTC7883 must be given a unique
serial bus address for configuration and control. These
units addresses can be derived from a combination of
external configuration resistors attached to the ASEL
pins and PMBus command values stored in on-board
EEPROM. This method of using ASEL pins to specify
some or all of each unit’s physical address is necessary
when using default factory EEPROM programing, where
both units are assigned to 0x4F. Applying external resistor
configuration for unit addresses is recommended, as it
allows for easier device recovery under a wide range of
programming errors. Refer to the values in Table 7 for full
details on setting each unit address.
Advanced Power Stages
Some LTC7883 factory EEPROM defaults have been
modified from LTC3882-1 values to better accommodate
newer, advanced power stages that provide an output
proportional to load current. Table 3 details these values. Refer to Figure 1 for an example of interfacing the
LTC7883 to power stages or blocks of this type. If traditional DCR or discrete resistor sense of output current is
used as shown on the front page, refer to factory EEPROM
defaults given for Table 3 commands in the LTC3882-1
data sheet.
Table 3. Unique LTC7883 Default Factory EEPROM Values
COMMAND NAME
CMD CODE
DESCRIPTION
TYPE
PAGED DATA FORMAT
UNITS
DEFAULT VALUE
IOUT_CAL_GAIN
0x38
Ratio of ISENSE ± Voltage
to Sensed Current
R/W Word
Y
L11
mΩ
0.25mΩ
0xAA00
IOUT_OC_FAULT_LIMIT
0x46
Output Overcurrent Fault Limit
R/W Word
Y
L11
A
70.0A
0xEA30
IOUT_OC_WARN_LIMIT
0x4A
Output Overcurrent Warning Limit
R/W Word
Y
L11
A
50.0A
0xE320
MFR_IOUT_CAL_GAIN_TC
0xF6
Output Current Sense Element
Temperature Coefficient
R/W Word
Y
CF
ppm/°C
0ppm/°C
0x0000
18
Rev. 0
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LTC7883
APPLICATIONS INFORMATION
Using FREQUENCY_SWITCH
Each unit in the LTC7883 that is a clock slave should have
FREQUENCY_SWITCH programmed to the same value
as its clock master, whether another LTC7883 or not. In
the case where external synchronization will be used to
control the shared SYNC line, each LTC7883 should be
programmed with a value of FREQUENCY_SWITCH that
is as close to the external clock frequency as possible.
Resistor Configuration Pins
Like the LTC3882-1, each LTC7883 unit is programmed
to use external resistor configuration by factory default.
This allows output voltage, PWM frequency and phasing,
and the PMBus address to be set without programming
the part through its serial interface or purchasing devices
with custom EEPROM contents. The RCONFIG pins all
require a resistor divider between VDD25 and GND. The
RCONFIG pins are only interrogated at initial power-up
and during a reset, so modifying their values on-the-fly
is not recommended. RCONFIG pins on the same unit
can share a single resistor divider if they require identical
programming, but these dividers should not be shared
across different LTC7883 units. Resistors with a tolerance
of 1% or better must be used to assure proper operation.
In Table 4 through Table 6, RTOP is connected between
VDD25 and the RCONFIG pin, while RBOT is connected
between the pin and GND. Noisy clock signals should not
be routed near these pins.
RCONFIG address selection for each LTC7883 unit follows
the values given in Table 7 of this data sheet.
Output voltage can be set as shown in Table 4. For example, setting RTOP to 16.2kΩ and RBOT to 17.4kΩ is equivalent to programming a VOUT_COMMAND value of 1.8V.
Refer to the Operation section of the LTC3882-1 data
sheet for related parameters that are also automatically
set as a percentage of the programmed VOUT if resistor
configuration pins are used to determined output voltage.
Operating PWM frequency can be set as shown in
Table 5. Note that if SYNC pins are shared between
LTC7883 units, all those units should be programmed
to the same frequency, but only one SYNC output should
be enabled. All other SYNC outputs should be disabled.
Refer to the following PCFG discussion for additional
details on controlling SYNC output enable with external
programming resistors.
Table 4. VOnCFGA/B Resistor Programming
RTOP (kΩ)
RBOT (kΩ)
VOUT (V)
0 or Open
10
10
16.2
16.2
20
20
20
20
24.9
24.9
24.9
24.9
24.9
30.1
30.1
Open
23.2
15.8
20.5
17.4
17.8
15
12.7
11
11.3
9.09
7.32
5.76
4.32
3.57
1.96
From EEPROM
5.0
3.3
2.5
1.8
1.5
1.35
1.25
1.2
1.15
1.1
1.0
0.9
0.75
0.65
0.6
Open
0
Output OFF*
(VOUT from EEPROM)
*OPERATION value and RUNn pin must both command the channel to
start from this configuration.
Table 5. FCFGA/B Resistor Programming
RTOP (kΩ)
RBOT (kΩ)
SWITCHING
FREQUENCY (kHz)
0 or Open
10
10
16.2
16.2
20
20
20
20
24.9
24.9
24.9
24.9
24.9
30.1
30.1
Open
23.2
15.8
20.5
17.4
17.8
15
12.7
11
11.3
9.09
7.32
5.76
4.32
3.57
1.96
From EEPROM
2500
2250
2000
1750
1500
1250
1000
900
750
600
500
450
400
350
300
Open
0
250
Rev. 0
For more information www.analog.com
19
LTC7883
APPLICATIONS INFORMATION
Table 6 shows various PWM phase configurations that
can be selected with external resistor programming. This
RCONFIG pin, as with the LTC3882-1, can also be used
to control SYNC output drive for each LTC7883 unit.
However, there are more choices here, affording greater
flexibility in PolyPhase configurations.
For example, to build a four-phase rail, one approach
might be to select RTOP of 24.9kΩ and RBOT of 5.76kΩ for
PHAS_CFG of Unit A (PCFGA). This programs the phase
angles of PWMA0 to 0° and PWMA1 to 180°, relative to
the falling edge of SYNC. Unit A is enabled to drive the
shared SYNC clock line through the SYNCA pin (opendrain output).
For Unit B, RTOP of 10kΩ and RBOT of 15.8kΩ selects
phase angles for PWMB0 of 90° and PWMB1 of 270°,
configuring SYNCB as an input to accept the master clock
from Unit A. The result, when wired as a 4-phase rail
as described in PolyPhase Operation and Load Sharing
under Applications Information in the LTC3882-1 data
sheet, will be four non-overlapping phases operating in
quadrature as desired. In this case, either Unit A or Unit
B may be defined and wired as the voltage loop master,
since this function is independent of clock mastering.
Only mix phase selections on PolyPhase rails that have
the same maximum duty cycle specified in Table 6.
Table 6. CFGA/B Resistor Programming
RTOP (kΩ)
RBOT (kΩ)
θSYNC TO θ0
θSYNC TO θ1
MAXIMUM DUTY CYCLE
SYNC OUTPUT DISABLED
0 or Open
Open
From EEPROM
From EEPROM
See MFR_PWM_CONFIG
From EEPROM
10
23.2
135°
315°
10
15.8
90°
270°
16.2
20.5
45°
225°
87.5%
Yes
16.2
17.4
0°
180°
20
17.8
120°
300°
20
15
60°
240°
20
12.7
0°
180°
83.3%
Yes
87.5%
No
83.3%
No
20
11
0°
120°
24.9
11.3
135°
315°
24.9
9.09
90°
270°
24.9
7.32
45°
225°
24.9
5.76
0°
180°
24.9
4.32
120°
300°
30.1
3.57
60°
240°
30.1
1.96
0°
180°
Open
0
0°
120°
20
Rev. 0
For more information www.analog.com
LTC7883
APPLICATIONS INFORMATION
Table 7. ASELn Resistor Programming
RTOP (kΩ) RBOT (kΩ)
ASEL1
ASEL0
LTC3882-1 DEVICE
ADDRESS BITS[6:4]
LTC3882-1 DEVICE
ADDRESS BITS[3:0]
BINARY
HEX
from EEPROM
BINARY
HEX
from EEPROM
solution volume. Placing the power stage directly beneath
the LTC7883 on the other side of the PCB allows direct
through-hole via connections to the power block for PWM
controls, as well as output voltage and current sense.
Table 8 shows the recommended channel mapping for
the most efficient interconnect in this case. CCM operation, fast boost refresh, low VOUT range and digital output
voltage servo are selected by programming MFR_PWM_
MODE_LTC3882-1 to 0xC0 on all channels.
0 or Open
Open
10
23.2
1111
F
10
15.8
1110
E
16.2
20.5
1101
D
16.2
17.4
1100
C
20
17.8
1011
B
20
15
1010
A
20
12.7
1001
9
20
11
1000
8
24.9
11.3
111
7
0111
7
A1
24.9
9.09
110
6
0110
6
B0
B1
24.9
7.32
101
5
0101
5
24.9
5.76
100
4
0100
4
24.9
4.32
011
3
0011
3
30.1
3.57
010
2
0010
2
30.1
1.96
001
1
0001
1
Open
0
000
0
0000
0
Design Example
As a design example, consider a 180W 4-phase application such as the one shown in Figure 1, where VIN = 12V,
VOUT = 1.5V, and IOUT = 120A. An auxiliary 7V source
supplies the LTC7883 VCC pins and the power stage FET
gate drive voltage with a 2.2µF ceramic bypass, in addition to a smaller 0.1µF ceramic placed near the LTC7883
filtering HF components. Bypassing is also provided for
each VDD33 (2.2µF) and VDD25 (1µF) LDO output. These
LDO outputs should not be shared with each other or
separate ICs that might have outputs of the same name,
because they have independent, internal control loops.
The Delta D12S1R8140D power block is chosen for its
high level of integration, power efficiency and direct
interface to the LTC7883 using 3.3V three-state control.
The use of a power block with the LTC7883 creates an
efficient solution in terms of power, parts count and total
Table 8. Suggested Power Block Channel Mapping
LTC7883 PWM
LTC7883 UNIT
PMBus PAGE
(CH)
PB PWM
A0
A
0
2
1
1
0
4
1
3
B
The regulated output is established by programming the
VOUT_COMMAND stored in EEPROM for PWMA0 (the
master channel) to 1.5V. The other PWMs are designated
as slaves to PWMA0 by wiring their FB pins to VDD33 and
shorting their COMP control pins to COMPA0 as shown.
The frequency and phase are also set by EEPROM values. Both units are programmed to operate at 500kHz
(default FREQUENCY_SWITCH), with Unit A providing
the clock master (see Figure 3, SYNCB output disabled
by bit 4 of MFR_CONFIG_ALL_LTC3882-1 on Unit B).
MFR_PWM_CONFIG_LTC3882-1 is programmed to 0x14
on Unit A to put PWMA0 phase at 0° and PWMA1 phase
at 180°. This register is programmed to 0x16 on Unit B
to put PWMB0 phase at 90° and PWMB1 phase at 270°,
producing optimum 4-phase separation for minimum
input and output ripple.
With these configurations, the inductors on the
power block (160nH nominal) create an IOUT ripple of
16.4AP-P. Each channel supplies 40ADC to the output at
full load, resulting in a peak phase current of 48A. Setting
IOUT_FAULT_LIMIT to 50A per phase adequately protects
against the typical inductor saturation current of 55A.
Rev. 0
For more information www.analog.com
21
LTC7883
APPLICATIONS INFORMATION
Two 100μF SUNCON capacitors and four 22μF ceramic
capacitors are selected to provide acceptable input AC
impedance against the designed converter ripple current.
Ten 220μF ceramic capacitors are chosen for the output to
maintain supply regulation during severe transient conditions and to minimize output voltage ripple.
The power block provides its own output current monitor
signals for use by the LTC7883. The interface network,
shown in detail for differential input CSA1, is also replicated for the other three channels. These remove high
frequency noise from the power block outputs and scale
those signals to be compatible with the LTC7883 inputs. A
fixed common mode reference voltage is required for the
power block –CS[4:1] outputs. A filtered resistor divider
from VDD33 (10k/12.1k/4.3μF) fulfills this requirement,
driving the negative side of the differential current sense
(CSx) signals.
External temperature sense will employ an accurate ΔVBE
method. Q1 serves to sense the temperature of the PCB
as close to the power block as physically possible, and
the 10nF filter capacitor should be placed with the BJT.
Unused TSNS inputs are loaded with 2.74k to produce
a benign reading of about 25ºC with factory EEPROM
settings, if the direct VBE interface mode is selected by
MFR_PWM_MODE_LTC3888-1 on these channels.
Each internal LTC7883 unit must be configured for a
unique address. Resistor configuration is used on the
22
ASEL pins to program the three most significant PMBus
address bits from EEPROM (MFR_ADDRESS, 0x4X).
Then each unit is given its own unique lower address
nibble, setting the two addresses to 0x4C (Unit A) and
0x4D (Unit B). Ensure the selected addresses do not collide with global addresses or any other specific devices
in the system. Identical MFR_RAIL_ADDRESS should be
set in EEPROM for all four channels to allow single-command control of common rail parameters such as IOUT_
OC_FAULT_LIMIT. The LTC7883 units also respond to
7-bit global addresses 0x5A and 0x5B. MFR_ADDRESS
and MFR_RAIL_ADDRESS should not be set to either of
these values.
PMBus connections, as well as shared RUN control
and fault propagation (FLT) are provided. SYNC can be
used to synchronize other PWMs to this rail if required.
Recommended PMBus connections and shared PSM connections are shown in more detail in Figure 3.
Pull-ups are provided on all shared open-drain signals
(Figure 1 and Figure 3). The values shown assume a
maximum 100pF line load and PMBus rate of 100kHz.
These pins should not be left floating. Termination to
3.3V ensures the absolute maximum ratings for the pins
are not exceeded. All other operating parameters such
as soft start/stop and desired faults responses are programmed via PMBus command values stored in internal
LTC7883 EEPROM.
Rev. 0
For more information www.analog.com
LTC7883
TYPICAL APPLICATIONS
VIN 12V
22µF
4×
VDR 7V
VDD33
10k
2.2µF
0.1µF
VINSA
VINSB
VCCA
VIN
VOUT
1.5V
120A
+CS1
N
4.99k
PGB1
220µF
10×
PGB0
VOUT
VSNSA1P
PWMA0
CSA0P
CSA0M
PWMB1
CSB1P
CSB1M
PWMB0
CSB0P
CSB0M
FBA1
FBB1
FBB0
VSNSA1M
VSNSB1M
VSNSB0M
COMPA1
COMP
VDD33
10k
COMPB1
DS12S18R140D
–CS1
CSA1M
VSNSB0P
VDD33
100pF
2k
VSNSB1P
100µF
2×
VCCB
PWMA1
CSA1P
PGA0
PGA1
+7V
+
N
+CS2
–CS2
N
+CS3
–CS3
N
+CS4
–CS4
121k
LTC7883
COMPB0
100k
THREE ADDITIONAL
IDENTICAL POWER
STAGES AND
EXTERNAL
CS FILTER
NETWORKS (N)
VDD33
0.01µF
×4*
Q1
10nF
RUNA1
TSNSA0
VSNSA0P
VSNSA0M
RUNA0
RUNB1
VDD25
RUN
16.2k
16.2k
2
RUNB0
4.12k
FBA0
ASEL1A/B
ASEL0A
20.5k
17.4k
2
2
4
60.4k
18pF
ASEL0B
180pF
FCFGA/B
COMPA0
PCFGA/B
VO[A/B][1:0]CFG
TSNSA1
VDD33
100pF
2
VDD25B
GND
VDD25A
7883 F01
2.2µF
SEE FIGURE 2 FOR PMBus
AND SHARED PSM PIN DETAILS
IAVGA0
IAVGNDA/B
VDD33B
VDD33A
IAVGA1
*1 PER PHASE
IAVGB0
TSNSB0
2.74k
COMP
IAVGB1
TSNSB1
2.74k
470pF
2.2µF
1µF
VDD25
1µF
Figure 1. High Density 1.5V/120A 500kHz 4-Phase Converter Using Quad Power Block
Rev. 0
For more information www.analog.com
23
LTC7883
TYPICAL APPLICATIONS
See Figure 2 for the LTC7883 controller plus the LTC7050/
LTC7051 SilentMOS™ smart power stage. The LTC7050/
LTC7051 have an on-chip diode that can be used by
the LTC7883 to sense the temperature. Use the direct
VBE measurement option in MFR_PWM_MODE of the
LTC7883. Consult the factory or review the LTC3882 DS
for more information on this temperature sensing method.
PWM
R2
140k
R1
49.9Ω
C1
4.7nF
IMON
IREF
VCC
CFIL
0.1µF
L1
LTC7050/
LTC7051
VCC
VOUT
SW
COUT
TDIO
GND
RT
750Ω
RB
237Ω
ISNS–
ISNS+
PWM
TSNS
VOUT
LTC7883
7883 F02
Figure 2. LTC7883 with LTC7050/LTC7051 SilentMOS Smart Power Stage
24
Rev. 0
For more information www.analog.com
0.40 REF Ø 99x
0.00
1.600
SUGGESTED PCB LAYOUT
TOP VIEW
0.800
PACKAGE TOP VIEW
E
0.800
4
1.600
PIN 1
CORNER
4.000
3.200
2.400
2.400
3.200
4.000
aaa Z
X
3.200
2.400
1.600
0.800
0.800
1.600
2.400
3.200
Y
D
0.000
aaa Z
// bbb Z
DETAIL B
SYMBOL
A
A1
A2
b
b1
D
E
e
F
G
H1
H2
aaa
bbb
ccc
ddd
eee
NOM
1.52
0.40
1.12
0.50
0.40
7.50
9.00
0.80
6.40
8.00
0.32 REF
0.80 REF
MAX
1.72
0.50
1.22
0.55
0.43
DIMENSIONS
A2
A
Z
SUBSTRATE THK
MOLD CAP HT
BALL DIMENSION
PAD DIMENSION
BALL HT
NOTES
DETAIL B
PACKAGE SIDE VIEW
0.15
0.10
0.20
0.15
0.08
TOTAL NUMBER OF BALLS: 99
MIN
1.32
0.30
1.02
0.45
0.37
H1
SUBSTRATE
ddd M Z X Y
eee M Z
DETAIL A
Øb (99 PLACES)
H2
MOLD
CAP
b1
ccc Z
A1
Z
(Reference LTC DWG # 05-08-7029 Rev Ø)
BGA Package
99-Lead (9mm × 7.5mm × 1.52mm)
e
10
b
9
7
G
6
5
e
PACKAGE BOTTOM VIEW
8
4
3
2
1
DETAIL A
J
H
G
F
E
D
C
B
A
3
SEE NOTES
PIN 1
DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PIN 1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
4
6
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
more by
information
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TRAY PIN 1
BEVEL
!
BGA 99 0120 REV Ø
PACKAGE IN TRAY LOADING ORIENTATION
LTXXXXXX
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
5. PRIMARY DATUM -Z- IS SEATING PLANE
BALL DESIGNATION PER JEP95
3
6
SEE NOTES
2. ALL DIMENSIONS ARE IN MILLIMETERS. DRAWING NOT TO SCALE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
COMPONENT
PIN 1
F
b
11
LTC7883
PACKAGE DESCRIPTION
Rev. 0
25
LTC7883
TYPICAL APPLICATION
(Also See Figure 1)
WPA
VDD33
WPB
PMBus
WRITE
ENABLE
VN2222
PMBus
1k
SCL
SHCLKA
SHCLKB
1k
SDA
SHARE_CLK
10k
10k
SMBALERT
4.99k
LTC7883
VDD33
ALERTA
FLTA1
ALERTB
FLTA0
SDA_A
FLTB1
SDA_B
FLTB0
SCL_A
SYNCA
SCL_B
GND
FAULT
2k
SYNC
PSM
SHARED
PINS
SYNCB
7883 F03
Figure 3. LTC7883 PMBus Interface and Configuration
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LTM4700
Dual 50A or Single 100A Step-Down DC/DC µModule
Regulator with Digital Power Management
VIN Up to 16V; 0.5V ≤ VOUT (±0.5%) ≤ 1.8V, ±3% IOUT ADC Accuracy,
Fault Logging, I2C/PMBus Interface, 330-Lead BGA Package
LTC3882/
LTC3882-1
Dual Output Multiphase Step-Down DC/DC Voltage Mode
Controller with Digital Power System Management
VIN Up to 38V, 0.5V ≤ VOUT (±0.5%) ≤ 5.25V, Fault Logging, I2C/PMBus
Interface, with EEPROM and 16-Bit ADC.
LTC3884/
LTC3884-1
Dual Output Multiphase Step-Down DC/DC Current Mode
Controller with Sub-mΩ DCR Sensing and Digital Power
Management
VIN Up to 38V, 0.5V ≤ VOUT (±0.5%) ≤ 5.5V, Fault Logging, I2C/PMBus
Interface, EEPROM, 16-Bit ADC, Input Current Sense, Programmable
Analog Loop Compensation
LTC3886
60V Dual Output Multiphase Step-Down DC/DC Current Mode VIN Up to 60V, 0.5V ≤ VOUT (±0.5%) ≤ 13.8V, Fault Logging, I2C/PMBus
Controller with Digital Power System Management
Interface, EEPROM, 16-Bit ADC, Input Current Sense, Programmable
Analog Loop Compensation
LTC3887/
LTC3887-1
Dual Output Multiphase Step-Down DC/DC Current Mode
Controller with Digital Power System Management
LTC3889
60V Dual Output Multiphase Step-Down DC/DC Current Mode VIN Up to 60V, 1V ≤ VOUT (±0.5%) ≤ 40V, Fault Logging, I2C/PMBus
Controller with Digital Power System Management
Interface, EEPROM, 16-Bit ADC, Input Current Sense, Programmable
Analog Loop Compensation
LTC7880
Dual Output Multiphase DC/DC Current Mode Boost
Controller with Digital Power System Management
VIN Up to 40V, VOUT Up to 60V with ±0.5% Accuracy, Fault Logging,
I2C/PMBus Interface, EEPROM, 16-Bit ADC, Input Current Sense,
Programmable Analog Loop Compensation
LTC2980
16-Channel PMBus Power System Manager Featuring
Accurate Output Voltage Measurement and Trim
Fault Logging, I2C/PMBus Interface, EEPROM, 16-Bit ADC Monitors
16 Output Voltages, 2 Input Voltages and Die Temperature
LTC2980-24
24-Channel PMBus Power System Manager Featuring
Accurate Output Voltage Measurement and Trim
Fault Logging, I2C/PMBus Interface, EEPROM, 16-Bit ADC Monitors
24 Output Voltages, 3 Input Voltages and Die Temperature
LTC7851/
LTC7851-1
Quad Output Multiphase Step-Down DC/DC Voltage Mode
Controller with Soft-Start and Accurate Current Share
VIN up to 27V, 0.6V ≤ VOUT ≤ 5V, Operates up to 2.25MHz with Power FET
Drivers, DrMOS Devices and Power Blocks
LTC3888/
LTC3888-1
Dual Loop, 8-Phase Step-Down DC/DC Controller with Digital VIN Up to 26.5V; 0.1V ≤ VOUT (±0.5%) ≤ 3.45V, Fault Logging, I2C/PMBus
Power System Management
Interface with NVM and 16-Bit ADC and Load Step Emulation
26
VIN Up to 24V, 0.5V ≤ VOUT (±0.5%) ≤ 5.5V, Fault Logging, I2C/PMBus
Interface, EEPROM, 16-Bit ADC
Rev. 0
12/21
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