LTM2173-14
14-Bit, 80Msps Low Power
Quad ADC
FEATURES
DESCRIPTION
4-Channel Simultaneous Sampling ADC
nn 73dB SNR
nn 88dB SFDR
nn Low Power: 96mW per Channel
nn Single 1.8V Supply
nn Serial LVDS Outputs: 1 or 2 Bits per Channel
nn Selectable Input Ranges: 1V
P-P to 2VP-P
nn 800MHz Full Power Bandwidth S/H
nn Shutdown and Nap Modes
nn Serial SPI Port for Configuration
nn Internal Bypass Capacitance, No External
Components
nn 140-Pin (11.25mm × 9mm) BGA Package
The LTM®2173-14 is a 4-channel, simultaneous sampling 14-bit A/D converter designed for digitizing high
frequency, wide dynamic range signals. AC performance
includes 73dB SNR and 88dB spurious free dynamic range
(SFDR). Low power consumption per channel reduces
heat in high channel count applications. Integrated bypass
capacitance and flow-through pinout reduces overall
board space requirements.
nn
DC specs include ±1LSB INL (typ), ±0.3LSB DNL (typ) and
no missing codes over temperature. The transition noise
is a low 1.2LSBRMS.
The digital outputs are serial LVDS to minimize the number of data lines. Each channel outputs two bits at a time
(2-lane mode). At lower sampling rates there is a one bit
per channel option (1-lane mode).
APPLICATIONS
Automotive
Communications
nn Cellular Base Stations
nn Software Defined Radios
nn Portable Medical Imaging
nn Multichannel Data Acquisition
nn Nondestructive Testing
nn
The ENC+ and ENC– inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL, or
CMOS inputs. An internal clock duty cycle stabilizer allows high performance at full speed for a wide range of
clock duty cycles.
nn
All registered trademarks and trademarks are the property of their respective owners.
TYPICAL APPLICATION
1.8V
VDD
14-BIT
ADC CORE
OUT1A
0
OUT1B
–10
S/H
14-BIT
ADC CORE
OUT2A
–20
ENCODE
INPUT
S/H
•••
OUT4A
14-BIT
ADC CORE
OUT4B
SERIALIZED
LVDS
OUTPUTS
AMPLITUDE (dBFS)
CHANNEL 4
ANALOG
INPUT
DATA
SERIALIZER
–30
OUT2B
•••
•••
CHANNEL 2
ANALOG
INPUT
S/H
•••
CHANNEL 1
ANALOG
INPUT
LTM2173-14, 80Msps,
2-Tone FFT, fIN = 70MHz and 75MHz
1.8V
OVDD
DATA
CLOCK
OUT
PLL
FRAME
GND
GND
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
10
20
30
FREQUENCY (MHz)
40
217314 TA01b
217314 TA01
217314f
For more information www.linear.com/LTM2173-14
1
LTM2173-14
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
Supply Voltages
VDD, OVDD................................................. –0.3V to 2V
Analog Input Voltage (AIN+, AIN –,
PAR/SER, SENSE) (Note 3)........... –0.3V to (VDD + 0.2V)
Digital Input Voltage (ENC+, ENC–, CS,
SDI, SCK) (Note 4)..................................... –0.3V to 3.9V
SDO (Note 4).............................................. –0.3V to 3.9V
Digital Output Voltage................. –0.3V to (OVDD + 0.3V)
Operating Temperature Range
LTM2173............................................. –40°C to 105°C
Storage Temperature Range................... –55°C to 125°C
TOP VIEW
A
B
C
D
E
F
G
H
J
K
L
M
N
P
2
1
3
4
5
6
7
8
9
10
BGA PACKAGE
140-LEAD (11.25mm × 9.00mm × 2.72mm)
TJMAX = 150°C, θJA = 30°C/W, θJC = 25°C/W, θJB = 15°C/W, θJCbottom = 12°C/W
ORDER INFORMATION
http://www.linear.com/product/LTM2173-14#orderinfo
LEAD FREE FINISH
TRAY
PART MARKING*
LTM2173HY-14#PBF
LTM2173HY-14#PBF
LTM2173Y14
PACKAGE DESCRIPTION
TEMPERATURE RANGE
140-Lead (11.25mm × 9mm × 2.72mm) BGA –40°C to 105°C
• Device temperature grade is indicated by a label on the shipping
container.
• Recommended BGA PCB Assembly and Manufacturing Procedures:
www.linear.com/umodule/pcbsssembly
• Pad or ball finish code is per IPC/JEDEC J-STD-609.
• BGA Package and Tray Drawings: www.linear.com/packaging
• Terminal Finish Part Marking: www.linear.com/leadfree
• This product is moisture sensitive. For more information, go to:
www.linear.com/BGA-assy
• This product is not recommended for second side reflow. For more
information, go to www.linear.com/BGA-assy
2
217314f
For more information www.linear.com/LTM2173-14
LTM2173-14
CONVERTER
CHARACTERISTICS l denotes the specifications which apply over the full operating
The
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
LTM2173-14
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
14
Integral Linearity Error
Differential Analog Input (Note 6)
l
–2.75
±1
2.75
LSB
Differential Linearity Error
Differential Analog Input
l
–0.8
±0.3
0.8
LSB
Offset Error
(Note 7)
l
–12
±3
12
mV
Gain Error
Internal Reference
External Reference
–2.6
–1.3
–1.3
0
%FS
%FS
Resolution (No Missing Codes)
l
Offset Drift
Bits
±20
µV/°C
Full-Scale Drift
Internal Reference
External Reference
±35
±25
ppm/°C
ppm/°C
Gain Matching
External Reference
±0.2
%FS
±3
mV
External Reference
1.2
LSBRMS
Offset Matching
Transition Noise
ANALOG
INPUT
The
l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
1.7V < VDD < 1.9V
l
VIN(CM)
Analog Input Range (AIN+ – AIN –)
Analog Input Common Mode (AIN+ + AIN –)/2
Differential Analog Input (Note 8)
l
VCM – 100mV
VCM
VCM + 100mV
V
VSENSE
External Voltage Reference Applied to SENSE
External Reference Mode
l
0.625
1.250
1.300
V
–1
1
µA
VIN
1 to 2
VP-P
IINCM
Analog Input Common Mode Current
Per Pin, 80Msps
IIN1
Analog Input Leakage Current
0 < AIN+, AIN – < VDD, No Encode
l
100
µA
IIN2
PAR/SER Input Leakage Current
0 < PAR/SER < VDD
l
–3
3
µA
IIN3
SENSE Input Leakage Current
0.625 < SENSE < 1.3V
l
–6
6
µA
t AP
Sample-and-Hold Acquisition Delay Time
0
ns
t JITTER
Sample-and-Hold Acquisition Delay Jitter
0.15
psRMS
CMRR
Analog Input Common Mode Rejection Ratio
80
dB
BW-3B
Full-Power Bandwidth
800
MHz
Figure 6 Test Circuit
217314f
For more information www.linear.com/LTM2173-14
3
LTM2173-14
DYNAMIC ACCURACY
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
LTM2173-14
SYMBOL PARAMETER
CONDITIONS
SNR
5MHz Input
70MHz Input
140MHz Input
Spurious Free Dynamic Range
2nd or 3rd Harmonic
Spurious Free Dynamic Range
4th Harmonic or Higher
SFDR
S/(N+D)
MIN
TYP
l
69.7
73
72.9
72.5
dBFS
dBFS
dBFS
5MHz Input
70MHz Input
140MHz Input
l
74
88
85
82
dBFS
dBFS
dBFS
5MHz Input
70MHz Input
140MHz Input
l
82
90
90
90
dBFS
dBFS
dBFS
Signal-to-Noise Plus Distortion Ratio 5MHz Input
70MHz Input
140MHz Input
l
69.6
72.9
72.6
72
dBFS
dBFS
dBFS
Signal-to-Noise Ratio
MAX
UNITS
Crosstalk, Near Channel
10MHz Input (Note 12)
–90
dBc
Crosstalk, Far Channel
10MHz Input (Note 12)
–105
dBc
INTERNAL
REFERENCE CHARACTERISTICS l denotes the specifications which apply over the
The
full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
PARAMETER
CONDITIONS
VCM Output Voltage
IOUT = 0
MIN
TYP
MAX
0.5 • VDD – 25mV
0.5 • VDD
0.5 • VDD + 25mV
VCM Output Temperature Drift
±25
VCM Output Resistance
–600µA < IOUT < 1mA
VREF Output Voltage
IOUT = 0
VREF Output Temperature Drift
±25
VREF Output Resistance
–400µA < IOUT < 1mA
VREF Line Regulation
1.7V < VDD < 1.9V
4
1.250
7
0.6
V
ppm/°C
4
1.225
UNITS
Ω
1.275
V
ppm/°C
Ω
mV/V
217314f
For more information www.linear.com/LTM2173-14
LTM2173-14
DIGITAL
INPUTS AND OUTPUTS l denotes the specifications which apply over the full operating
The
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ENCODE INPUTS (ENC +, ENC – )
VID
Differential Input Voltage
(Note 8)
VICM
Common Mode Input Voltage
Internally Set
Externally Set (Note 8)
l
1.1
VIN
Input Voltage Range
ENC+, ENC – to GND
l
0.2
RIN
Input Resistance
(See Figure 10)
CIN
Input Capacitance
l
0.2
V
1.2
1.6
3.6
V
V
V
10
kΩ
3.5
pF
DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)
VIH
High Level Input Voltage
VDD = 1.8V
l
VIL
Low Level Input Voltage
VDD = 1.8V
l
IIN
Input Current
VIN = 0V to 3.6V
l
CIN
Input Capacitance
1.3
V
–10
0.6
V
10
µA
3
pF
200
Ω
SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2kΩ Pull-Up Resistor if SDO Is Used)
ROL
Logic Low Output Resistance to GND
VDD = 1.8V, SDO = 0V
IOH
Logic High Output Leakage Current
SDO = 0V to 3.6V
COUT
Output Capacitance
l
–10
10
3
µA
pF
DIGITAL DATA OUTPUTS
VOD
Differential Output Voltage
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l
l
247
125
350
175
454
250
VOS
Common Mode Output Voltage
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l
l
1.125
1.125
1.250
1.250
1.375
1.375
RTERM
On-Chip Termination Resistance
Termination Enabled, OVDD = 1.8V
100
mV
mV
V
V
Ω
217314f
For more information www.linear.com/LTM2173-14
5
LTM2173-14
POWER
REQUIREMENTS l denotes the specifications which apply over the full operating temperature
The
range, otherwise specifications are at TA = 25°C. (Note 9)
LTM2173-14
MIN
TYP
MAX
VDD
SYMBOL PARAMETER
Analog Supply Voltage
(Note 10)
CONDITIONS
l
1.7
1.8
1.9
OVDD
Output Supply Voltage
(Note 10)
l
1.7
1.8
1.9
V
IVDD
Analog Supply Current
Sine Wave Input
l
189
205
mA
IOVDD
Digital Supply Current
2-Lane Mode, 1.75mA Mode
2-Lane Mode, 3.5mA Mode
l
l
25
47
29
52
mA
mA
PDISS
Power Dissipation
2-Lane Mode, 1.75mA Mode
2-Lane Mode, 3.5mA Mode
l
l
385
425
421
462
mW
mW
PSLEEP
Sleep Mode Power
1
mW
PNAP
Nap Mode Power
85
mW
20
mW
PDIFFCLK Power Decrease With Single-Ended Encode Mode Enabled
(No Decrease for Sleep Mode)
UNITS
V
TIMING
CHARACTERISTICS l denotes the specifications which apply over the full operating temperature
The
range, otherwise specifications are at TA = 25°C. (Note 5)
LTM2173-14
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fS
Sampling Frequency
(Notes 10,11)
l
5
80
MHz
tENCL
ENC Low Time (Note 8)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
5.93
2
6.25
6.25
100
100
ns
ns
tENCH
ENC High Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
5.93
2
6.25
6.25
100
100
ns
ns
t AP
Sample-and-Hold
Acquisition Delay Time
SYMBOL
PARAMETER
0
CONDITIONS
MIN
TYP
ns
MAX
UNITS
Digital Data Outputs (RTERM = 100Ω Differential, CL = 2pF to GND on Each Output)
1/(8 • fS)
1/(7 • fS)
1/(6 • fS)
1/(16 • fS)
1/(14 • fS)
1/(12 • fS)
tSER
Serial Data Bit Period
2-Lanes, 16-Bit Serialization
2-Lanes, 14-Bit Serialization
2-Lanes, 12-Bit Serialization
1-Lane, 16-Bit Serialization
1-Lane, 14-Bit Serialization
1-Lane, 12-Bit Serialization
tFRAME
FR to DCO Delay
(Note 8)
l
tDATA
DATA to DCO Delay
(Note 8)
l
tPD
Propagation Delay
(Note 8)
l
tR
Output Rise Time
tF
0.35 • tSER
0.5 • tSER
0.65 • tSER
s
0.35 • tSER
0.5 • tSER
0.65 • tSER
s
0.7n + 2 • tSER 1.1n + 2 • tSER 1.5n + 2 • tSER
s
Data, DCO, FR, 20% to 80%
0.17
ns
Output Fall Time
Data, DCO, FR, 20% to 80%
0.17
ns
DCO Cycle-Cycle Jitter
tSER = 1ns
60
psP-P
6
Cycles
Pipeline Latency
6
s
s
s
s
s
s
217314f
For more information www.linear.com/LTM2173-14
LTM2173-14
TIMING
CHARACTERISTICS l denotes the specifications which apply over the full operating temperature
The
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SPI Port Timing (Note 8)
tSCK
SCK Period
tS
Write Mode
Read Back Mode, CSDO = 20pF,
RPULLUP = 2k
l
l
40
250
ns
ns
CS to SCK Setup Time
l
5
ns
tH
SCK to CS Setup Time
l
5
ns
tDS
SDI Setup Time
l
5
ns
tDH
SDI Hold Time
l
5
ns
tDO
SCK Falling to SDO Valid
Read Back Mode, CSDO = 20pF,
RPULLUP = 2k
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND (unless otherwise
noted).
Note 3: When these pin voltages are taken below GND or above VDD,
they will be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND or above VDD without
latchup.
Note 4: When these pin voltages are taken below GND they will be
clamped by internal diodes. When these pin voltages are taken above
VDD they will not be clamped by internal diodes. This product can handle
input currents of greater than 100mA below GND without latchup.
Note 5: VDD = OVDD = 1.8V, f SAMPLE = 80MHz, 2-lane output mode,
differential ENC+/ENC – = 2VP-P sine wave, input range = 2VP-P with
differential drive, unless otherwise noted.
Note 6: Integral nonlinearity is defined as the deviation of a code from
a best fit straight line to the transfer curve. The deviation is measured
from the center of the quantization band.
l
125
ns
Note 7: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 00 0000 0000 0000 and 11 1111 1111
1111 in 2’s complement output mode.
Note 8: Guaranteed by design, not subject to test.
Note 9: VDD = OVDD = 1.8V, fSAMPLE = 80MHz, 2-lane output mode,
differential ENC+/ENC – = 2VP-P sine wave, input range = 2VP-P with
differential drive, unless otherwise noted. The supply current and
power dissipation specifications are totals for the entire device, not per
channel.
Note 10: Recommended operating conditions.
Note 11: The maximum sampling frequency depends on the speed grade
of the part and also which serialization mode is used. The maximum
serial data rate is 1000Mbps so tSER must be greater than or equal to 1ns.
Note 12: Near-channel crosstalk refers to Ch. 1 to Ch.2, and Ch.3 to
Ch.4. Far-channel crosstalk refers to Ch.1 to Ch.3, Ch.1 to Ch.4, Ch.2 to
Ch.3, and Ch.2 to Ch.4.
217314f
For more information www.linear.com/LTM2173-14
7
LTM2173-14
TIMING DIAGRAMS
2-Lane Output Mode, 16-Bit Serialization*
tAP
ANALOG
INPUT
N+1
N
tENCH
ENC–
tENCL
ENC+
tSER
DCO–
DCO+
tFRAME
FR–
FR+
tDATA
tSER
tPD
OUT#A–
OUT#A+
OUT#B–
OUT#B+
tSER
D5
D3
D1
0
D13 D11 D9
D7
D5
D3
D1
0
D13 D11 D9
D4
D2
D0
0
D12 D10 D8
D6
D4
D2
D0
0
D12 D10 D8
SAMPLE N-6
SAMPLE N-5
SAMPLE N-4
217314 TD01
*SEE THE DIGITAL OUTPUTS SECTION
2-Lane Output Mode, 14-Bit Serialization
tAP
ANALOG
INPUT
N+2
N
tENCH
ENC–
N+1
tENCL
ENC+
tSER
DCO–
DCO+
tFRAME
FR–
FR+
OUT#A–
OUT#A+
OUT#B–
OUT#B+
tDATA
tSER
tPD
tSER
D7
D5
D3
D1 D13 D11 D9
D7
D5
D3
D1 D13 D11 D9
D7
D5
D3
D1 D13 D11 D9
D6
D4
D2
D0 D12 D10 D8
D6
D4
D2
D0 D12 D10 D8
D6
D4
D2
D0 D12 D10 D8
SAMPLE N-6
SAMPLE N-5
SAMPLE N-4
SAMPLE N-3
217314 TD02
NOTE THAT IN THIS MODE FR+/FR– HAS TWO TIMES THE PERIOD OF ENC+/ENC–
8
217314f
For more information www.linear.com/LTM2173-14
LTM2173-14
TIMING DIAGRAMS
2-Lane Output Mode, 12-Bit Serialization
tAP
ANALOG
INPUT
N
N+1
tENCH
ENC–
tENCL
ENC+
tSER
DCO–
DCO+
FR+
tFRAME
tDATA
tPD
tSER
FR–
OUT#A–
OUT#A+
OUT#B–
OUT#B+
tSER
D9
D7
D5
D3 D13 D11 D9
D7
D5
D3 D13 D11 D9
D8
D6
D4
D2 D12 D10 D8
D6
D4
D2 D12 D10 D8
SAMPLE N-6
SAMPLE N-5
SAMPLE N-4
217314 TD03
1-Lane Output Mode, 16-Bit Serialization
tAP
ANALOG
INPUT
N+1
N
tENCH
ENC–
tENCL
ENC+
tSER
DCO–
DCO+
tFRAME
FR–
FR+
OUT#A–
OUT#A+
tDATA
tSER
tPD
D1
D0
SAMPLE N-6
0
tSER
0
D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
SAMPLE N-5
D0
0
0
D13 D12 D11 D10
SAMPLE N-4
217314 TD04
OUT#B+, OUT#B– ARE DISABLED
217314f
For more information www.linear.com/LTM2173-14
9
LTM2173-14
TIMING DIAGRAMS
1-Lane Output Mode, 14-Bit Serialization
tAP
ANALOG
INPUT
N+1
N
tENCH
ENC–
tENCL
ENC+
tSER
DCO–
DCO+
tFRAME
FR–
FR+
OUT#A–
OUT#A+
tDATA
tSER
tPD
D3
D2
D1
tSER
D0 D13 D12 D11 D10 D9
SAMPLE N-6
D8
D7
D6
D5
D4
D3
D2
SAMPLE N-5
D1
D0 D13 D12 D11 D10
SAMPLE N-4
217314 TD06
OUT#B+, OUT#B– ARE DISABLED
1-Lane Output Mode, 12-Bit Serialization
tAP
ANALOG
INPUT
N+1
N
tENCH
ENC–
tENCL
ENC+
tSER
DCO–
DCO+
tFRAME
FR–
FR+
OUT#A–
OUT#A+
tDATA
tSER
tPD
D5
D4
SAMPLE N-6
D3
tSER
D2 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
SAMPLE N-5
D3
D2 D13 D12 D11
SAMPLE N-4
217314 TD07
OUT#B+, OUT#B– ARE DISABLED
10
217314f
For more information www.linear.com/LTM2173-14
LTM2173-14
TIMING DIAGRAMS
SPI Port Timing (Readback Mode)
tDS
tS
tDH
tSCK
tH
CS
SCK
tDO
SDI
SDO
R/W
A6
A5
A4
A3
A2
A1
A0
XX
D7
HIGH IMPEDANCE
XX
D6
XX
D5
XX
D4
XX
D3
XX
D2
XX
XX
D1
D0
SPI Port Timing (Write Mode)
CS
SCK
SDI
SDO
R/W
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
217314 TD08
HIGH IMPEDANCE
217314f
For more information www.linear.com/LTM2173-14
11
LTM2173-14
TYPICAL PERFORMANCE CHARACTERISTICS
LTM2173-14: Integral Nonlinearity
(INL)
LTM2173-14: Differential
Nonlinearity (DNL)
2.0
1.0
0
1.5
0.8
–10
0
–0.5
–1.0
0.2
0
–0.2
–0.4
–0.8
0
4096
8192
12288
OUTPUT CODE
–1.0
16384
0
4096
9009101114 G29
LTM2173-14: 8k Point FFT,
fIN = 30MHz, –1dBFS, 80Msps
–40
–50
–60
–70
–80
–90
–100
–0.6
–1.5
8192
12288
OUTPUT CODE
16384
–110
–120
0
0
–10
–10
–20
–20
–20
–30
–30
–30
–60
–70
–80
AMPLITUDE (dBFS)
0
–50
–40
–50
–60
–70
–80
–60
–70
–80
–90
–100
–110
–120
–110
–120
–110
–120
20
30
FREQUENCY (MHz)
40
0
10
217314 G04
20
30
FREQUENCY (MHz)
40
0
0
10
217314 G05
LTM2173-14: 8k Point 2-Tone FFT,
fIN = 70MHz, 75MHz, –7dBFS per
Tone, 80Msps
40
217314 G03
–40
–90
–100
10
20
30
FREQUENCY (MHz)
–50
–90
–100
0
10
LTM2173-14: 8k Point FFT,
fIN = 140MHz, –1dBFS, 80Msps
–10
–40
0
217314 G02
LTM2173-14: 8k Point FFT,
fIN = 70MHz, –1dBFS, 80Msps
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
–30
0.4
AMPLITUDE (dBFS)
DNL ERROR (LSB)
INL ERROR (LSB)
0.5
–2.0
–20
0.6
1.0
LTM2173-14: 8k Point FFT,
fIN = 5MHz, –1dBFS, 80Msps
20
30
FREQUENCY (MHz)
40
217314 G06
LTM2173-14: Shorted Input
Histogram
6000
–10
–20
5000
–40
–60
3000
–70
–80
2000
–90
–100
1000
–110
–120
12
4000
–50
COUNT
AMPLITUDE (dBFS)
–30
0
10
20
30
FREQUENCY (MHz)
40
0
8184
8186
217314 G07
8188
8190
OUTPUT CODE
8192
217314 G08
217314f
For more information www.linear.com/LTM2173-14
LTM2173-14
TYPICAL PERFORMANCE CHARACTERISTICS
LTM2173-14: SNR vs Input
Frequency, –1dBFS, 2V Range,
80Msps
LTM2173-14: SFDR vs Input
Frequency, –1dBFS, 2V Range,
80Msps
74
LTM2173-14: SFDR vs Input Level,
fIN = 70MHz, 2V Range, 80Msps
95
73
110
100
90
70
69
SFDR (dBc AND dBFS)
SFDR (dBFS)
SNR (dBFS)
71
85
80
75
68
66
0
50
100 150 200 250 300
INPUT FREQUENCY (MHz)
350
0
50
217314 G09
190
74
100 150 200 250 300
INPUT FREQUENCY (MHz)
dBc
60
50
40
30
0
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
350
217314 G10
LTM2173-14: SNR vs SENSE,
fIN = 5MHz, –1dBFS
DCO Cycle-Cycle Jitter vs Serial
Data Rate
350
PEAK-TO-PEAK JITTER (ps)
300
SNR (dBFS)
72
170
160
71
70
69
68
150
20
40
60
SAMPLE RATE (Msps)
80
217314 G12
66
250
200
150
100
50
67
0
0
217314 G11
73
180
IVDD (mA)
70
10
65
LTM2173-14: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dBFS
140
80
20
70
67
dBFS
90
72
0.6
0.7
0.8
0.9
1
1.1
SENSE PIN (V)
1.2
1.3
217314 G13
0
0
200
400
600
800
SERIAL DATA RATE (Mbps)
1000
217314 G14
217314f
For more information www.linear.com/LTM2173-14
13
LTM2173-14
PIN FUNCTIONS
AIN1+ (B2): Channel 1 Positive Differential Analog Input.
AIN1– (B1): Channel 1 Negative Differential Analog Input.
VCM12 (B3): Common Mode Bias Output, Nominally Equal
to VDD/2. VCM should be used to bias the common mode
of the analog inputs of channels 1 and 2. VCM is internally
bypassed to ground with a 0.1µF ceramic capacitor. No
external capacitance is required.
AIN2+ (G2): Channel 2 Positive Differential Analog Input.
AIN2– (G1): Channel 2 Negative Differential Analog Input.
AIN3+ (H1): Channel 3 Positive Differential Analog Input.
AIN3 – (H2): Channel 3 Negative Differential Analog Input.
VCM34 (N3): Common Mode Bias Output, Nominally Equal
to VDD/2. VCM should be used to bias the common mode
of the analog inputs of channels 3 and 4. VCM is internally
bypassed to ground with a 0.1µF ceramic capacitor. No
external capacitance is required.
AIN4 + (N1): Channel 4 Positive Differential Analog Input.
AIN4 – (N2): Channel 4 Negative Differential Analog Input.
VDD (D3, D4, E3, E4, K3, K4, L3, L4): 1.8V Analog Power
Supply. VDD is internally bypassed to ground with 0.1μF
ceramic capacitors.
ENC+ (P5): Encode Input. Conversion starts on the rising
edge.
ENC – (P6): Encode Complement Input. Conversion starts
on the falling edge.
CS (L5): In serial programming mode, (PAR/SER = 0V),
CS is the serial interface chip select input. When CS is
low, SCK is enabled for shifting data on SDI into the
mode control registers. In parallel programming mode
(PAR/SER = VDD), CS selects 2-lane or 1-lane output
mode. CS can be driven with 1.8V to 3.3V logic.
SCK (L6): In serial programming mode, (PAR/SER = 0V),
SCK is the serial interface clock input. In parallel programming mode (PAR/SER = VDD), SCK selects 3.5mA
or 1.75mA LVDS output currents. SCK can be driven with
1.8V to 3.3V logic.
14
SDI (M6): In serial programming mode, (PAR/SER =
0V), SDI is the serial interface data Input. Data on SDI
is clocked into the mode control registers on the rising
edge of SCK. In parallel programming mode (PAR/SER =
VDD), SDI can be used to power down the part. SDI can
be driven with 1.8V to 3.3V logic.
GND (See Pin Configuration Table): ADC Power Ground.
Use multiple vias close to pins.
OVDD (G9, G10): Output Driver Supply. OVDD is internally
bypassed to ground with a 0.1µF ceramic capacitor.
SDO (E6): In serial programming mode, (PAR/SER = 0V),
SDO is the optional serial interface data output. Data on
SDO is read back from the mode control registers and can
be latched on the falling edge of SCK. SDO is an opendrain N-channel MOSFET output that requires an external
2k pull-up resistor from 1.8V to 3.3V. If read back from the
mode control registers is not needed, the pull-up resistor
is not necessary and SDO can be left unconnected. In
parallel programming mode (PAR/SER = VDD), SDO is an
input that enables internal 100Ω termination resistors on
the digital outputs. When used as an input, SDO can be
driven with 1.8V to 3.3V logic through a 1k series resistor.
PAR/SER (A7): Programming Mode Selection Pin.
Connect to ground to enable the serial programming
mode. CS, SCK, SDI and SDO become a serial interface
that control the A/D operating modes. Connect to VDD
to enable parallel programming mode where CS, SCK,
SDI and SDO become parallel logic inputs that control a
reduced set of the A/D operating modes. PAR/SER should
be connected directly to ground or the VDD of the part and
not be driven by a logic signal.
VREF (B6): Reference Voltage Output. VREF is internally
bypassed to ground with a 2.2μF ceramic capacitor, nominally 1.25V.
SENSE (C5): Reference Programming Pin. Connecting
SENSE to VDD selects the internal reference and a ±1V
input range. Connecting SENSE to ground selects the
internal reference and a ±0.5V input range. An external
reference between 0.625V and 1.3V applied to SENSE
selects an input range of ±0.8 • VSENSE. SENSE is internally bypassed to ground with a 0.1µF ceramic capacitor.
217314f
For more information www.linear.com/LTM2173-14
LTM2173-14
PIN FUNCTIONS
LVDS Outputs
All pins in this section are differential LVDS outputs.
The output current level is programmable. There is an
optional internal 100Ω termination resistor between
the pins of each LVDS output pair.
OUT1A – /OUT1A +, OUT1B – /OUT1B + (E7/E8, C8/D8):
Serial Data Outputs for Channel 1. In 1-lane output mode
only OUT1A–/OUT1A+ are used.
OUT2A –/OUT2A+,
OUT2B –/OUT2B+
(C9/C10, F7/F8):
Serial Data Outputs for Channel 2. In 1-lane output mode
only OUT2A–/OUT2A+ are used.
OUT3A – /OUT3A +, OUT3B – /OUT3B + (J8/J7, K8/K7):
Serial Data Outputs for Channel 3. In 1-lane output mode
only OUT3A–/OUT3A+ are used.
OUT4A–/OUT4A+, OUT4B –/OUT4B+ (L8/M8, M10/M9):
Serial Data Outputs for Channel 4. In 1-lane output mode
only OUT4A–/OUT4A+ are used.
FR–/FR+ (H7/H8): Frame Start Outputs.
DCO –/DCO+ (G8/G7): Data Clock Outputs.
PIN CONFIGURATION TABLE
1
2
3
4
5
6
7
8
9
10
A
GND
GND
GND
GND
GND
GND
PAR/SER
GND
GND
GND
B
A IN1–
A IN1+
VCM12
GND
GND
VREF
GND
GND
GND
GND
OUT2A –
OUT2A+
C
GND
GND
GND
GND
SENSE
GND
GND
OUT1B –
D
GND
GND
VDD
VDD
GND
GND
GND
OUT1B+
GND
GND
SDO
OUT1A –
OUT1A+
GND
GND
OUT2B+
E
GND
VDD
VDD
GND
F
GND
GND
GND
GND
GND
GND
OUT2B –
GND
GND
G
A IN2 –
A IN2+
GND
GND
GND
GND
DCO+
DCO –
OVDD
OVDD
H
A IN3+
A IN3 –
GND
GND
GND
GND
FR–
FR+
GND
GND
GND
OUT3A+
OUT3A –
GND
GND
GND
OUT3B+
OUT3B –
GND
GND
J
K
GND
GND
GND
GND
GND
VDD
GND
VDD
GND
GND
L
GND
GND
VDD
VDD
CS
SCK
GND
OUT4A –
GND
GND
M
GND
GND
GND
GND
GND
SDI
GND
OUT4A+
OUT4B+
OUT4B –
N
A IN4+
A IN4 –
VCM34
GND
GND
GND
GND
GND
GND
GND
GND
ENC+
ENC –
GND
GND
GND
GND
P
GND
GND
GND
GND
Top View of BGA Package (Looking Through Component).
217314f
For more information www.linear.com/LTM2173-14
15
LTM2173-14
FUNCTIONAL BLOCK DIAGRAM
VDD = 1.8V
OVDD = 1.8V
S/H
14-BIT
ADC CORE
OUT1A+
OUT1A–
OUT1B+
OUT1B–
CH 2
ANALOG
INPUT
S/H
14-BIT
ADC CORE
OUT2A+
OUT2A–
OUT2B+
OUT2B–
CH 3
ANALOG
INPUT
S/H
14-BIT
ADC CORE
OUT3A+
OUT3A–
OUT3B+
OUT3B–
S/H
14-BIT
ADC CORE
OUT4A+
OUT4A–
OUT4B+
OUT4B–
CH 1
ANALOG
INPUT
CH 4
ANALOG
INPUT
DATA
SERIALIZER
ENC+
DCO±
FR±
PLL
ENC–
1.25V
REFERENCE
VREF
REFH
RANGE
SELECT
REFL
REF
BUFFER
MODE
CONTROL
REGISTERS
SDO
SDI
SCK
CS
PAR/SER
VDD/2
DIFF
REF
AMP
GND
217314 F01
SENSE
VCM12
VCM34
Figure 1. Functional Block Diagram
16
217314f
For more information www.linear.com/LTM2173-14
LTM2173-14
APPLICATIONS INFORMATION
CONVERTER OPERATION
INPUT DRIVE CIRCUITS
The LTM2173-14 is a low power, 4-channel, 14-bit, 80Msps
A/D converter that is powered by a single 1.8V supply. The
analog inputs should be driven differentially. The encode
input can be driven differentially for optimal jitter performance, or single-ended for lower power consumption.
The digital outputs are serial LVDS to minimize the number of data lines. Each channel outputs two bits at a time
(2-lane mode). At lower sampling rates there is a one bit
per channel option (1-lane mode). Many additional features can be chosen by programming the mode control
registers through a serial SPI port.
Input Filtering
ANALOG INPUT
The analog inputs are differential CMOS sample-and-hold
circuits (Figure 2). The inputs should be driven differentially around a common mode voltage set by the appropriate VCM output pins, which are nominally VDD/2. For the
2V input range, the inputs should swing from VCM – 0.5V
to VCM + 0.5V. There should be 180° phase difference
between the inputs.
The eight channels are simultaneously sampled by a
shared encode circuit (Figure 2).
If possible, there should be an RC low pass filter right at
the analog inputs. This lowpass filter isolates the drive circuitry from the A/D sample-and-hold switching, and also
limits wideband noise from the drive circuitry. Figure 3
shows an example of an input RC filter. The RC component values should be chosen based on the application’s
input frequency.
Transformer Coupled Circuits
Figure 3 shows the analog input being driven by an RF
transformer with a center-tapped secondary. The center
tap is biased with VCM, setting the A/D input at its optimal
DC level. At higher input frequencies a transmission line
balun transformer (Figures 4 to 6) has better balance,
resulting in lower A/D distortion.
50Ω
VCM
0.1µF
0.1µF
ANALOG
INPUT
T1
1:1
25Ω
25Ω
AIN+
LTM2173-14
0.1µF
12pF
25Ω
LTM2173-14
AIN+
VDD
RON
25Ω
10Ω
CPARASITIC
1.8pF
VDD
AIN–
CSAMPLE
3.5pF
RON
25Ω
10Ω
VDD
CSAMPLE
3.5pF
25Ω
T1: MA/COM MABAES0060
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
AIN–
217314 F03
Figure 3. Analog Input Circuit Using a Transformer.
Recommended for Input Frequencies from 5MHz to 70MHz
CPARASITIC
1.8pF
1.2V
10k
ENC+
ENC–
10k
1.2V
217314 F02
Figure 2. Equivalent Input Circuit. Only One
of the Eight Analog Channels Is Shown
217314f
For more information www.linear.com/LTM2173-14
17
LTM2173-14
APPLICATIONS INFORMATION
Amplifier Circuits
Figure 7 shows the analog input being driven by a high
speed differential amplifier. The output of the amplifier is
AC-coupled to the A/D so the amplifier’s output common
mode voltage can be optimally set to minimize distortion.
50Ω
At very high frequencies an RF gain block will often have
lower distortion than a differential amplifier. If the gain
block is single-ended, then a transformer circuit (Figures
4 to 6) should convert the signal to differential before
driving the A/D.
50Ω
VCM
VCM
0.1µF
0.1µF
ANALOG
INPUT
0.1µF
0.1µF
AIN+
T2
T1
25Ω
LTM2173-14
0.1µF
ANALOG
INPUT
AIN+
T2
T1
25Ω
LTM2173-14
0.1µF
4.7pF
0.1µF
25Ω
1.8pF
0.1µF
–
AIN
25Ω
AIN–
217314 F04
T1: MA/COM MABA-007159-000000
T2: COILCRAFT WBC1-1LB
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
T1: MA/COM MABA-007159-000000
T2: MA/COM MABAES0060
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
Figure 4. Recommended Front End Circuit for Input
Frequencies from 70MHz to 170MHz
50Ω
217314 F05
Figure 5. Recommended Front End Circuit for Input
Frequencies from 170MHz to 300MHz
VCM
VCM
HIGH SPEED
DIFFERENTIAL
0.1µF
AMPLIFIER
0.1µF
0.1µF
2.7nH
ANALOG
INPUT
25Ω
+
AIN
LTM2173-14
0.1µF
T1
0.1µF
25Ω
2.7nH
AIN–
ANALOG
INPUT
+
+
–
–
200Ω
200Ω
25Ω
0.1µF
AIN+
LTM2173-14
12pF
0.1µF
25Ω
AIN–
217314 F07
217314 F06
T1: MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
Figure 6. Recommended Front End Circuit for Input
Frequencies Above 300MHz
18
Figure 7. Front End Circuit Using a High Speed
Differential Amplifier
217314f
For more information www.linear.com/LTM2173-14
LTM2173-14
APPLICATIONS INFORMATION
Reference
The input range can be adjusted by applying a voltage to
SENSE that is between 0.625V and 1.30V. The input range
will then be 1.6 • VSENSE. The reference is shared by all
four ADC channels, so it is not possible to independently
adjust the input range of individual channels.
The LTM2173-14 has an internal 1.25V voltage reference.
For a 2V input range using the internal reference, connect
SENSE to VDD. For a 1V input range using the internal
reference, connect SENSE to ground. For a 2V input range
with an external reference, apply a 1.25V reference voltage to SENSE (Figure 9).
VREF
1.25V
LTM2173-14
The VREF and SENSE pins are internally bypassed, as
shown in Figure 8.
5Ω
1.25V BANDGAP
REFERENCE
2.2µF
0.625V
TIE TO VDD FOR 2V RANGE;
TIE TO GND FOR 1V RANGE;
RANGE = 1.6 • VSENSE FOR
0.65V < VSENSE < 1.300V
RANGE
DETECT
AND
CONTROL
SENSE
0.1µF
0.1µF
INTERNAL ADC
BUFFER
HIGH REFERENCE
REFH
2.2µF
0.1µF
0.8x
DIFF AMP
REFL
INTERNAL ADC
LOW REFERENCE
217314 F08
Figure 8. Reference Circuit
1.25V
EXTERNAL
REFERENCE
LTM2173-14
SENSE
1µF
217314 F09
Figure 9. Using an External 1.25V Reference
217314f
For more information www.linear.com/LTM2173-14
19
LTM2173-14
APPLICATIONS INFORMATION
Encode Input
The signal quality of the encode inputs strongly affects
the A/D noise performance. The encode inputs should
be treated as analog signals—do not route them next to
digital traces on the circuit board. There are two modes
of operation for the encode inputs: the differential encode
mode (Figure 10), and the single-ended encode mode
(Figure 11).
The differential encode mode is recommended for sinusoidal, PECL, or LVDS encode inputs (Figures 12 and 13).
LTM2173-14
The encode inputs are internally biased to 1.2V through
10k equivalent resistance. The encode inputs can be taken
above VDD (up to 3.6V), and the common mode range is
from 1.1V to 1.6V. In the differential encode mode, ENC–
should stay at least 200mV above ground to avoid falsely
triggering the single-ended encode mode. For good jitter
performance ENC+ should have fast rise and fall times.
The single-ended encode mode should be used with
CMOS encode inputs. To select this mode, ENC – is connected to ground and ENC+ is driven with a square wave
VDD
DIFFERENTIAL
COMPARATOR
VDD
15k
ENC+
LTM2173-14
1.8V TO
3.3V
ENC–
0V
30k
ENC+
ENC–
30k
217314 F11
217314 F10
Figure 10. Equivalent Encode Input Circuit
for Differential Encode Mode
0.1µF
ENC+
T1
0.1µF
Figure 11. Equivalent Encode Input Circuit
for Single-Ended Encode Mode
LTM2173-14
0.1µF
50Ω
100Ω
PECL OR
LVDS
CLOCK
50Ω
0.1µF
CMOS LOGIC
BUFFER
ENC–
217314 F12
ENC+
LTM2173-14
0.1µF
ENC–
217314 F13
T1 = MA/COM ETC1-1-13
RESISTORS AND CAPACITORS
ARE 0402 PACKAGE SIZE
Figure 12. Sinusoidal Encode Drive
20
Figure 13. PECL or LVDS Encode Drive
217314f
For more information www.linear.com/LTM2173-14
LTM2173-14
APPLICATIONS INFORMATION
encode input. ENC+ can be taken above VDD (up to 3.6V)
so 1.8V to 3.3V CMOS logic levels can be used. The ENC+
threshold is 0.9V. For good jitter performance ENC+
should have fast rise and fall times.
Clock PLL and Duty Cycle Stabilizer
The encode clock is multiplied by an internal phase-locked
loop (PLL) to generate the serial digital output data. If the
encode signal changes frequency or is turned off, the PLL
requires 25µs to lock onto the input clock.
A clock duty cycle stabilizer circuit allows the duty cycle
of the applied encode signal to vary from 30% to 70%.
In the serial programming mode it is possible to disable
the duty cycle stabilizer, but this is not recommended. In
the parallel programming mode the duty cycle stabilizer
is always enabled.
DIGITAL OUTPUTS
The digital outputs of the LTM2173-14 are serialized LVDS
signals. Each channel outputs two bits at a time (2-lane
mode). At lower sampling rates there is a one bit per channel option (1-lane mode). The data can be serialized with
16, 14, or 12-bit serialization (see the Timing Diagrams
section for details). Note that with 12-bit serialization the
two LSBs are not available.
The output data should be latched on the rising and falling
edges of the data clock out (DCO). A data frame output
(FR) can be used to determine when the data from a new
conversion result begins. In the 2-lane, 14-bit serialization
mode, the frequency of the FR output is halved.
The maximum serial data rate for the data outputs is
1Gbps, so the maximum sample rate of the ADC will
depend on the serialization mode as well as the speed
grade of the ADC (see Table 1). The minimum sample rate
for all serialization modes is 5Msps.
By default the outputs are standard LVDS levels: 3.5mA
output current and a 1.25V output common mode voltage. An external 100Ω differential termination resistor
is required for each LVDS output pair. The termination
resistors should be located as close as possible to the
LVDS receiver.
The outputs are powered by OVDD which is independent
from the A/D core power.
Table 1. Maximum Sampling Frequency for All Serialization Modes.
SERIALIZATION MODE
MAXIMUM SAMPLING
FREQUENCY, f S (MHz)
DCO FREQUENCY
FR FREQUENCY
SERIAL DATA RATE
2-Lane
16-Bit Serialization
80
4 • fS
fS
8 • fS
2-Lane
14-Bit Serialization
80
3.5 • fS
0.5 • fS
7 • fS
2-Lane
12-Bit Serialization
80
3 • fS
fS
6 • fS
1-Lane
16-Bit Serialization
62.5
8 • fS
fS
16 • fS
1-Lane
14-Bit Serialization
71.4
7 • fS
fS
14 • fS
1-Lane
12-Bit Serialization
80
6 • fS
fS
12 • fS
217314f
For more information www.linear.com/LTM2173-14
21
LTM2173-14
APPLICATIONS INFORMATION
Programmable LVDS Output Current
Table 2. Output Codes vs Input Voltage
The default output driver current is 3.5mA. This current
can be adjusted by control register A2 in the serial programming mode. Available current levels are 1.75mA,
2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA. In the parallel programming mode, the SCK pin can select either
3.5mA or 1.75mA.
Optional LVDS Driver Internal Termination
In most cases, using just an external 100Ω termination resistor will give excellent LVDS signal integrity. In
addition, an optional internal 100Ω termination resistor
can be enabled by serially programming mode control register A2. The internal termination helps absorb
any reflections caused by imperfect termination at the
receiver. When the internal termination is enabled, the
output driver current is doubled to maintain the same
output voltage swing. In the parallel programming
mode the SDO pin enables internal termination. Internal
termination should only be used with 1.75mA, 2.1mA or
2.5mA LVDS output current modes.
DATA FORMAT
Table 2 shows the relationship between the analog input
voltage and the digital data output bits. By default the
output data format is offset binary. The 2’s complement
format can be selected by serially programming mode
control register A1.
22
A IN+ – A IN –
(2V RANGE)
D13-D0
(OFFSET BINARY)
D13-D0
(2’s COMPLEMENT)
>1.000000V
11 1111 1111 1111
01 1111 1111 1111
+0.999878V
11 1111 1111 1111
01 1111 1111 1111
+0.999756V
11 1111 1111 1110
01 1111 1111 1110
+0.000122V
10 0000 0000 0001
00 0000 0000 0001
+0.000000V
10 0000 0000 0000
00 0000 0000 0000
–0.000122V
01 1111 1111 1111
11 1111 1111 1111
–0.000244V
01 1111 1111 1110
11 1111 1111 1110
–0.999878V
00 0000 0000 0001
10 0000 0000 0001
–1.000000V
00 0000 0000 0000
10 0000 0000 0000
工商网监
湘ICP备2023018690号