LTM4601A/LTM4601A-1
12A µModule Regulators
with PLL, Output Tracking
and Margining
DESCRIPTION
FEATURES
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Complete Switch Mode Power Supply
Wide Input Voltage Range: 4.5V to 20V
12A DC Typical, 14A Peak Output Current
0.6V to 5V Output Voltage
Output Voltage Tracking and Margining
Redundant Mounting Pads for Enhanced SolderJoint Strength
Parallel Multiple µModules for Current Sharing
Differential Remote Sensing for Precision
Regulation (LTM4601A Only)
PLL Frequency Synchronization
±1.5% Total DC Error
Current Foldback Protection (Disabled at Start-Up)
SnPb or RoHS Compliant Finish
UltraFast™ Transient Response
Current Mode Control
Up to 95% Efficiency at 5VIN, 3.3VOUT
Programmable Soft-Start
Output Overvoltage Protection
Enhanced (15mm × 15mm × 2.82mm) Surface Mount
LGA and (15mm × 15mm × 3.42mm) BGA Packages
APPLICATIONS
Telecom and Networking Equipment
Servers
The LTM®4601A is a complete 12A step-down switch mode
DC/DC power supply with onboard switching controller,
MOSFETs, inductor and all support components. The
µModule® regulator is housed in a small surface mount
15mm × 15mm × 2.82mm LGA or 15mm × 15mm ×
3.42mm BGA package. The LTM4601A LGA and BGA
packages are designed with redundant mounting pads to
enhance solder-joint strength for extended temperature
cycling endurance. Operating over an input voltage range
of 4.5V to 20V, the LTM4601A supports an output voltage
range of 0.6V to 5V as well as output voltage tracking
and margining. The high efficiency design delivers 12A
continuous current (14A peak). Only bulk input and output
capacitors are needed to complete the design.
The low profile and light weight package easily mounts
on the back side of PC boards. The µModule regulator
can be synchronized with an external clock for reducing
undesirable frequency harmonics and allows PolyPhase®
operation for high load currents.
An onboard differential remote sense amplifier can be used
to accurately regulate an output voltage independent of
load current. The onboard remote sense amplifier is not
available in the LTM4601A-1.
L, LT, LTC, LTM, µModule and PolyPhase are registered trademarks of Linear Technology
Corporation. UltraFast and LTpowerCAD are trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Protected by U.S. Patents
including 5481178, 5847554, 6304066, 6476589, 6580258, 6677210, 6774611.
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TYPICAL APPLICATION
Efficiency and Power Loss
vs Load Current
1.5V/12A Power Supply with 4.5V to 20V Input
95
CLOCK SYNC
TRACK/SS CONTROL
ON/OFF
CIN
R1
392k
5% MARGIN
RUN
COMP
INTVCC
DRVCC
MPGM
SGND
PLLIN TRACK/SS
VOUT
LTM4601A
PGND
VFB
MARG0
MARG1
VOUT
1.5V
12A
100pF
MARGIN
CONTROL
COUT
VOUT_LCL
DIFFVOUT
VOSNS+
VOSNS–
fSET
3.5
85
12VIN
80
12VIN
70
1.5
POWER LOSS
55
50
2.0
5VIN
65
4601A TA01a
3.0
2.5
75
60
RSET
40.2k
4.0
5VIN
0
2
4
6
8
10
LOAD CURRENT (A)
1.0
12
14
4601A TA01b
For more information www.linear.com/LTM4601A
POWER LOSS (W)
VIN
PGOOD
EFFICIENCY
90
EFFICIENCY (%)
VIN
4.5V TO 20V
0.5
4601afe
1
LTM4601A/LTM4601A-1
ABSOLUTE MAXIMUM RATINGS
(Note 1)
INTVCC, DRVCC, VOUT_LCL, VOUT (VOUT ≤ 3.3V with
DIFFVOUT )..................................................... –0.3V to 6V
PLLIN, TRACK/SS, MPGM, MARG0, MARG1,
PGOOD, fSET...............................–0.3V to INTVCC + 0.3V
RUN.............................................................. –0.3V to 5V
VFB, COMP................................................. –0.3V to 2.7V
VIN
MTP1
MTP2
INTVCC
MTP3
fSET
VIN
MARG0
MARG1
MTP2
DRVCC
INTVCC
MTP3
MPGM
fSET
MARG0
MARG1
DRVCC
VFB
PGND
PGOOD
PGOOD
SGND
VOSNS
SGND
DIFFVOUT/NC3*
VOSNS+/NC2*
+/NC2*
VOUT
COMP
MTP1
VFB
PGND
RUN
PLLIN
INTVCC
MPGM
COMP
TOP VIEW
TRACK/SS
(See Table 5. Pin Assignment)
RUN
PLLIN
INTVCC
TOP VIEW
TRACK/SS
PIN CONFIGURATION
VIN.............................................................. –0.3V to 20V
VOSNS+, VOSNS –...........................–0.3V to INTVCC + 0.3V
Operating Temperature Range (Note 2).... –40°C to 85°C
Junction Temperature............................................ 125°C
Storage Temperature Range................... –55°C to 125°C
Peak Solder Reflow Body Temperature.................. 245°C
VOUT_LCL
DIFFVOUT/NC3*
VOUT
VOSNS–/NC1*
VOUT_LCL
VOSNS–/NC1*
BGA PACKAGE
133-LEAD (15mm × 15mm × 3.42mm)
LGA PACKAGE
133-LEAD (15mm × 15mm × 2.82mm)
TJMAX = 125°C, θJA = 15.5°C/W, θJCbottom = 6.5°C/W
θJA DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS
WEIGHT = 1.9g, *LTM4601A-1 ONLY
TJMAX = 125°C, θJA = 15°C/W, θJC = 6°C/W
θJA DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS
WEIGHT = 1.7g, *LTM4601A-1 ONLY
ORDER INFORMATION
PART NUMBER
PAD OR BALL FINISH
PART MARKING*
DEVICE
FINISH CODE
PACKAGE
TYPE
MSL
RATING
TEMPERATURE RANGE
(Note 2)
LTM4601AEV#PBF
Au (RoHS)
LTM4601AV
e4
LGA
3
–40°C to 85°C
LTM4601AIV#PBF
Au (RoHS)
LTM4601AV
e4
LGA
3
–40°C to 85°C
LTM4601AEV-1#PBF
Au (RoHS)
LTM4601AV-1
e4
LGA
3
–40°C to 85°C
LTM4601AIV-1#PBF
Au (RoHS)
LTM4601AV-1
e4
LGA
3
–40°C to 85°C
LTM4601AEY#PBF
SAC305 (RoHS)
LTM4601AY
e1
BGA
3
–40°C to 85°C
LTM4601AEY-1#PBF
SAC305 (RoHS)
LTM4601AY-1
e1
BGA
3
–40°C to 85°C
LTM4601AIY-1#PBF
SAC305 (RoHS)
LTM4601AY-1
e1
BGA
3
–40°C to 85°C
LTM4601AIY#PBF
SAC305 (RoHS)
LTM4601AY
e1
BGA
3
–40°C to 85°C
LTM4601AIY
SnPb (63/37)
LTM4601AY
e0
BGA
3
–40°C to 85°C
LTM4601AIY-1
SnPb (63/37)
LTM4601AY-1
e0
BGA
3
–40°C to 85°C
Consult Marketing for parts specified with wider operating temperature
ranges. *Device temperature grade is indicated by a label on the shipping
container. Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures:
www.linear.com/umodule/pcbassembly
• Terminal Finish Part Marking:
www.linear.com/leadfree
• LGA and BGA Package and Tray Drawings:
www.linear.com/packaging
2
For more information www.linear.com/LTM4601A
4601afe
LTM4601A/LTM4601A-1
ELECTRICAL
CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
temperature range (Note 2), otherwise specifications are at TA = 25°C, VIN = 12V, per typical application (front page) configuration.
SYMBOL
PARAMETER
VIN(DC)
Input DC Voltage
CONDITIONS
VOUT(DC)
Output Voltage, Total Variation with
Line and Load
CIN = 10µF ×3, COUT = 200µF, RSET = 40.2k
VIN = 5V to 20V, IOUT = 0A to 12A (Note 5)
MIN
l
4.5
l
1.478
TYP
MAX
UNITS
20
V
1.5
1.522
V
4
V
Input Specifications
VIN(UVLO)
Undervoltage Lockout Threshold
IOUT = 0A
3.2
IINRUSH(VIN)
Input Inrush Current at Startup
IOUT = 0A. VOUT = 1.5V
VIN = 5V
VIN = 12V
0.6
0.7
A
A
IQ(VIN,NOLOAD)
Input Supply Bias Current
VIN = 12V, No Switching
VIN = 12V, VOUT = 1.5V, Switching Continuous
VIN = 5V, No Switching
VIN = 5V, VOUT = 1.5V, Switching Continuous
Shutdown, RUN = 0, VIN = 12V
3.8
38
2.5
42
22
mA
mA
mA
mA
µA
IS(VIN)
Input Supply Current
VIN = 12V, VOUT = 1.5V, IOUT = 12A
VIN = 12V, VOUT = 3.3V, IOUT = 12A
VIN = 5V, VOUT = 1.5V, IOUT = 12A
1.81
3.63
4.29
A
A
A
INTVCC
VIN = 12V, RUN > 2V
No Load
4.7
5
5.3
V
12
A
Output Specifications
IOUTDC
Output Continuous Current Range
VIN = 12V, VOUT = 1.5V (Note 5)
0
∆VOUT(LINE)
Line Regulation Accuracy
VOUT = 1.5V, IOUT = 0A, VIN from 4.5V to 20V
l
0.3
%
Load Regulation Accuracy
VOUT = 1.5V, 0A to 12A (Note 5)
VIN = 12V, with Remote Sense Amplifier
VIN = 12V (LTM4601A-1)
l
l
0.25
1
%
%
VOUT
∆VOUT(LOAD)
VOUT
VOUT(AC)
Output Ripple Voltage
IOUT = 0A, COUT = 2× 100µF X5R Ceramic
VIN = 12V, VOUT = 1.5V
VIN = 5V, VOUT = 1.5V
20
18
mVP-P
mVP-P
fS
Output Ripple Voltage Frequency
IOUT = 5A, VIN = 12V, VOUT = 1.5V
850
kHz
∆VOUT(START)
Turn-On Overshoot
COUT = 200µF, VOUT = 1.5V, IOUT = 0A,
TRACK/SS = 10nF
VIN = 12V
VIN = 5V
20
20
mV
mV
COUT = 200µF, VOUT = 1.5V, TRACK/SS = Open,
IOUT = 1A Resistive Load
VIN = 12V
VIN = 5V
0.5
0.5
ms
ms
Load: 0% to 50% to 0% of Full Load,
COUT = 2 × 22µF Ceramic, 470µF 4V Sanyo
POSCAP
VIN = 12V
VIN = 5V
35
35
mV
mV
25
µs
17
17
A
A
tSTART
ΔVOUTLS
Turn-On Time
Peak Deviation for Dynamic Load
tSETTLE
Settling Time for Dynamic Load Step Load: 0% to 50%, or 50% to 0% of Full Load
VIN = 12V
IOUTPK
Output Current Limit
COUT = 200µF Ceramic
VIN = 12V, VOUT = 1.5V
VIN = 5V, VOUT = 1.5V
4601afe
For more information www.linear.com/LTM4601A
3
LTM4601A/LTM4601A-1
ELECTRICAL
CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
temperature range (Note 2), otherwise specifications are at TA = 25°C, VIN = 12V, per typical application (front page) configuration.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Remote Sense Amp (Note 3) (LTM4601A Only, Not Supported in the LTM4601A-1)
VOSNS+, VOSNS–
CM Range
Common Mode Input Voltage Range VIN = 12V, RUN > 2V
0
INTVCC – 1
V
DIFFVOUT Range
Output Voltage Range
0
INTVCC – 1
V
VOS
Input Offset Voltage Magnitude
AV
Differential Gain
1
V/V
GBP
Gain-Bandwidth Product
3
MHz
SR
Slew Rate
RIN
Input Resistance
CMRR
Common Mode Rejection Mode
VIN = 12V, DIFFVOUT Load = 100k
1.25
VOSNS+ to GND
mV
2
V/µs
20
kΩ
100
dB
Control Stage
VFB
Error Amplifier Input Voltage
Accuracy
IOUT = 0A, VOUT = 1.5V
VRUN
RUN Pin On/Off Threshold
ITRACK/SS
Soft-Start Charging Current
VTRACK/SS = 0V
l
0.594
0.6
0.606
V
1
1.5
1.9
V
–1
–1.5
–2
µA
tON(MIN)
Minimum On-Time
(Note 4)
50
100
ns
tOFF(MIN)
Minimum Off-Time
(Note 4)
250
400
ns
RPLLIN
PLLIN Input Resistance
IDRVCC
Current into DRVCC Pin
50
VOUT = 1.5V, IOUT = 1A, DRVCC = 5V
60.098
kΩ
18
25
mA
60.4
60.702
kΩ
RFBHI
Resistor Between VOUT_LCL and VFB
VMPGM
Margin Reference Voltage
1.18
V
VMARG0 , VMARG1
MARG0, MARG1 Voltage Thresholds
1.4
V
PGOOD Output
∆VFBH
PGOOD Upper Threshold
VFB Rising
7
10
13
%
∆VFBL
PGOOD Lower Threshold
VFB Falling
–7
–10
–13
%
∆VFB(HYS)
PGOOD Hysteresis
VFB Returning
1.5
VPGL
PGOOD Low Voltage
IPGOOD = 5mA
0.15
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTM4601A is tested under pulsed load conditions such that
TJ ≈ TA . The LTM4601AE/LTM4601AE-1 are guaranteed to meet
performance specifications from 0°C to 85°C. Specifications over the
%
0.4
V
–40°C to 85°C operating temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTM4601AI/LTM4601AI-1 are guaranteed over the –40°C to 85°C
operating temperature range.
Note 3: Remote sense amplifier recommended for ≤3.3V output.
Note 4: 100% tested at wafer level only.
Note 5: See output current derating curves for different VIN , VOUT and TA .
4601afe
4
For more information www.linear.com/LTM4601A
LTM4601A/LTM4601A-1
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Load Current
with 20VIN
Efficiency vs Load Current
with 12VIN
100
100
95
95
95
90
90
90
85
85
85
80
75
70
0.6VOUT
1.2VOUT
1.5VOUT
2.5VOUT
3.3VOUT
65
60
55
50
0
5
10
80
75
70
0.6VOUT
1.2VOUT
1.5VOUT
2.5VOUT
3.3VOUT
5VOUT
65
60
55
50
15
100
EFFICIENCY (%)
EFFICIENCY (%)
EFFICIENCY (%)
Efficiency vs Load Current
with 5VIN
(See Figure 18 for all curves)
0
LOAD CURRENT (A)
80
75
70
65
55
10
5
LOAD CURRENT (A)
4601A G01
15
50
0
10
5
LOAD CURRENT (A)
4601A G02
1.2V Transient Response
1.5V Transient Response
1.8V Transient Response
VOUT
50mV/DIV
VOUT
50mV/DIV
IOUT
5A/DIV
IOUT
5A/DIV
IOUT
5A/DIV
4601A G04
20µs/DIV
1.5V AT 6A/µs LOAD STEP
COUT = 3 • 22µF 6.3V CERAMICS,
470µF 4V SANYO POSCAP
C3 = 100pF
4601A G05
20µs/DIV
1.8V AT 6A/µs LOAD STEP
COUT = 3 • 22µF 6.3V CERAMICS,
470µF 4V SANYO POSCAP
C3 = 100pF
4601A G06
3.3V Transient Response
2.5V Transient Response
VOUT
50mV/DIV
VOUT
50mV/DIV
IOUT
5A/DIV
IOUT
5A/DIV
20µs/DIV
2.5V AT 6A/µs LOAD STEP
COUT = 3 • 22µF 6.3V CERAMICS,
470µF 4V SANYO POSCAP
C3 = 100pF
15
4601A G03
VOUT
50mV/DIV
20µs/DIV
1.2V AT 6A/µs LOAD STEP
COUT = 3 • 22µF 6.3V CERAMICS,
470µF 4V SANYO POSCAP
C3 = 100pF
1.2VOUT
1.5VOUT
2.5VOUT
3.3VOUT
5.0VOUT
60
4601A G07
20µs/DIV
3.3V AT 6A/µs LOAD STEP
COUT = 3 • 22µF 6.3V CERAMICS,
470µF 4V SANYO POSCAP
C3 = 100pF
4601A G08
4601afe
For more information www.linear.com/LTM4601A
5
LTM4601A/LTM4601A-1
TYPICAL PERFORMANCE CHARACTERISTICS (See Figure 18 for all curves)
Start-Up, IOUT = 12A
(Resistive Load)
Start-Up, IOUT = 0A
VOUT
0.5V/DIV
VOUT
0.5V/DIV
IIN
1A/DIV
IIN
0.5A/DIV
5ms/DIV
VIN = 12V
VOUT = 1.5V
COUT = 470µF, 3 × 22µF
SOFT-START = 10nF
2ms/DIV
VIN = 12V
VOUT = 1.5V
COUT = 470µF, 3 × 22µF
SOFT-START = 10nF
4601A G09
VIN to VOUT Step-Down Ratio
Track, IOUT = 12A
5.5
3.3V OUTPUT WITH
130k ADDED FROM
VOUT TO fSET
5.0
OUTPUT VOLTAGE (V)
4.5
TRACK/SS
0.5V/DIV
VFB
0.5V/DIV
5V OUTPUT WITH
100k RESISTOR
ADDED FROM fSET
TO GND
4.0
3.5
3.0
2.0
5V OUTPUT WITH
NO RESISTOR ADDED
FROM fSET TO GND
1.5
2.5V OUTPUT
1.0
1.8V OUTPUT
0.5
1.5V OUTPUT
2.5
0
VOUT
1V/DIV
2ms/DIV
VIN = 12V
VOUT = 1.5V
COUT = 470µF, 3 × 22µF
SOFT-START = 10nF
1.2V OUTPUT
0
2
4
4601A G10
4601A G12
6 8 10 12 14 16 18 20
INPUT VOLTAGE (V)
4601A G11
Short-Circuit Protection, IOUT = 0A
Short-Circuit Protection, IOUT = 12A
VOUT
0.5V/DIV
VOUT
0.5V/DIV
IIN
1A/DIV
IIN
1A/DIV
50µs/DIV
VIN = 12V
VOUT = 1.5V
COUT = 470µF, 3 × 22µF
SOFT-START = 10nF
4601A G13
50µs/DIV
VIN = 12V
VOUT = 1.5V
COUT = 470µF, 3 × 22µF
SOFT-START = 10nF
4601A G14
4601afe
6
For more information www.linear.com/LTM4601A
LTM4601A/LTM4601A-1
PIN FUNCTIONS
(See Package Description for Pin Assignment)
VIN (Bank 1): Power Input Pins. Apply input voltage between these pins and PGND pins. Recommend placing
input decoupling capacitance directly between VIN pins
and PGND pins.
VOUT (Bank 3): Power Output Pins. Apply output load
between these pins and PGND pins. Recommend placing
output decoupling capacitance directly between these pins
and PGND pins. See Figure 15.
PGND (Bank 2): Power ground pins for both input and
output returns.
VOSNS– (Pin M12): (–) Input to the Remote Sense Amplifier. This pin connects to the ground remote sense point.
The remote sense amplifier is used for VOUT ≤ 3.3V. Tie
to INTVCC if not used.
NC1 (Pin M12): No Internal Connection on the LTM4601A-1.
VOSNS+ (Pin J12): (+) Input to the Remote Sense Amplifier. This pin connects to the output remote sense point.
The remote sense amplifier is used for VOUT ≤ 3.3V. Tie
to GND if not used.
NC2 (Pin J12): No Internal Connection on the LTM4601A-1.
DIFFVOUT (Pin K12): Output of the Remote Sense Amplifier.
This pin connects to the VOUT_LCL pin. Leave floating if
not used.
NC3 (Pin K12): No Internal Connection on the LTM4601A-1.
DRVCC (Pin E12): This pin normally connects to INTVCC
for powering the internal MOSFET drivers. This pin can
be biased up to 6V from an external supply with about
50mA capability, or an external circuit shown in Figure 16.
This improves efficiency at the higher input voltages by
reducing power dissipation in the module.
INTVCC (Pin A7, D9): This pin is for additional decoupling
of the 5V internal regulator. These pins are internally
connected. Pin A7 is a test pin.
PLLIN (Pin A8): External Clock Synchronization Input to
the Phase Detector. This pin is internally terminated to
SGND with a 50k resistor. Apply a clock with high level
above 2V and below INTVCC. See the Applications Information section.
TRACK/SS (Pin A9): Output Voltage Tracking and SoftStart Pin. When the module is configured as a master
output, then a soft-start capacitor is placed on this pin
to ground to control the master ramp rate. A soft-start
capacitor can be used for soft-start turn on as a stand
alone regulator. Slave operation is performed by putting
a resistor divider from the master output to ground, and
connecting the center point of the divider to this pin. See
the Applications Information section.
MPGM (Pins A12, B11): Programmable Margining Input.
A resistor from this pin to ground sets a current that is
equal to 1.18V/R. This current multiplied by 10kΩ will
equal a value in millivolts that is a percentage of the 0.6V
reference voltage. See the Applications Information section. To parallel LTM4601As, each requires an individual
MPGM resistor. Do not tie MPGM pins together. Both pins
are internally connected. Pin A12 is a test pin.
fSET (Pins B12, C11): Frequency Set Internally to 850kHz.
An external resistor can be placed from this pin to ground
to increase frequency. See the Applications Information
section for frequency adjustment. Both pins are internally
connected. Pin B12 is a test pin.
VFB (Pin F12): The Negative Input of the Error Amplifier.
Internally, this pin is connected to VOUT_LCL pin with a
60.4k precision resistor. Different output voltages can
be programmed with an additional resistor between VFB
and SGND pins. See the Applications Information section.
MARG0 (Pin C12): This pin is the LSB logic input for the
margining function. Together with the MARG1 pin it will
determine if margin high, margin low or no margin state
is applied. The pin has an internal pull-down resistor of
50k. See the Applications Information section.
4601afe
For more information www.linear.com/LTM4601A
7
LTM4601A/LTM4601A-1
PIN FUNCTIONS
(See Package Description for Pin Assignment)
MARG1 (Pin D12): This pin is the MSB logic input for the
margining function. Together with the MARG0 pin it will
determine if margin high, margin low or no margin state
is applied. The pin has an internal pull-down resistor of
50k. See the Applications Information section.
SGND (Pins H12, H11, G11): Signal Ground. These pins
connect to PGND at output capacitor point. See Figure 15.
COMP (Pin A11): Current Control Threshold and Error
Amplifier Compensation Point. The current comparator
threshold increases with this control voltage. The voltage
ranges from 0V to 2.4V with 0.7V corresponding to zero
sense voltage (zero current).
PGOOD (Pins G12, F11): Output Voltage Power Good
Indicator. Open-drain logic output that is pulled to ground
when the output voltage is not within ±10% of the regulation point, after a 25µs power bad mask timer expires.
RUN (Pin A10): Run Control Pin. A voltage above 1.9V
will turn on the module, and when below 1V, will turn
off the module. A programmable UVLO function can be
accomplished by connecting to a resistor divider from
VIN to ground. See Figure 1. This pin has a 5.1V Zener to
ground. Maximum pin voltage is 5V. Limit current into
the RUN pin to less than 1mA.
VOUT_LCL (Pin L12): VOUT connects directly to this pin to
bypass the remote sense amplifier, or DIFFVOUT connects
to this pin when the remote sense amplifier is used.
VOUT_LCL can be connected to VOUT on the LTM4601A-1,
VOUT is internally connected to VOUT_LCL with 50Ω in the
LTM4601A-1.
MTP1, MTP2, MPT3 (Pins C10, D10, D11 ): Extra Mounting Pads. These pads must be left floating (electrical open
circuit) and are used for enhanced solder joint strength.
4601afe
8
For more information www.linear.com/LTM4601A
LTM4601A/LTM4601A-1
SIMPLIFIED BLOCK DIAGRAM
VIN
VOUT_LCL
R1
UVLO
FUNCTION
>1.9V = ON
4.8V use 4.8V
LTM4601A minimum on-time = 100ns
tON = ((VOUT • 10pF)/IfSET)
LTM4601A minimum off-time = 400ns
tOFF = t – tON, where t = 1/Frequency
LTM4601A minimum off-time = 400ns
tOFF = t – tON, where t = 1/Frequency
Duty Cycle = tON/t or VOUT/VIN
Duty Cycle (DC) = tON/t or VOUT/VIN
Equations for setting frequency:
Equations for setting frequency:
IfSET = (VIN/(3 • RfSET)), for 20V operation, IfSET = 170µA,
tON = ((4.8 • 10pF)/IfSET), tON = 282ns, where the internal
RfSET is 39.2k. Frequency = (VOUT/(VIN • tON)) = (5V/(20
• 282ns)) ≈ 886kHz. The inductor ripple current begins
to get high at the higher input voltages due to a larger
voltage across the inductor. This is noted in the Inductor Ripple Current vs Duty Cycle graph (Figure 3) where
IL ≈ 10A at 25% duty cycle. The inductor ripple current
can be lowered at the higher input voltages by adding an
external resistor from fSET to ground to increase the switching frequency. An 8A ripple current is chosen, and the total
peak current is equal to 1/2 of the 8A ripple current plus
the output current. The 5V output current is limited to 8A,
so the total peak current is less than 12A. This is below the
14A peak specified value. A 100k resistor is placed from
fSET to ground, and the parallel combination of 100k and
39.2k equates to 28k. The IfSET calculation with 28k and
20V input voltage equals 238µA. This equates to a tON of
200ns. This will increase the switching frequency from
~886kHz to ~1.25MHz for the 20V to 5V conversion. The
minimum on-time is above 100ns at 20V input. Since
the switching frequency is approximately constant over
input and output conditions, then the lower input voltage
range is limited to 10V for the 1.25MHz operation due to
the 400ns minimum off-time. Equation: tON = (VOUT/VIN)
• (1/Frequency) equates to a 400ns on-time, and a 400ns
off-time. The VIN to VOUT Step-Down Ratio curve reflects
an operating range of 10V to 20V for 1.25MHz operation
with a 100k resistor to ground, and an 8V to 16V operation
for fSET floating. These modifications are made to provide
wider input voltage ranges for the 5V output designs while
limiting the inductor ripple current, and maintaining the
400ns minimum off-time.
IfSET = (VIN/(3 • RfSET)), for 20V operation, IfSET = 170µA,
tON = ((3.3 • 10pF)/IfSET), tON = 195ns, where the internal
RfSET is 39.2k. Frequency = (VOUT/(VIN • tON)) = (3.3V/(20
• 195ns)) ≈ 846kHz. The minimum on-time and minimum
off-time are within specification at 195ns and 980ns. The
4.5V minimum input for converting 3.3V output will not
meet the minimum off-time specification of 400ns. tON =
868ns, Frequency = 850kHz, tOFF = 315ns.
Solution
Lower the switching frequency at lower input voltages to
allow for higher duty cycles, and meet the 400ns minimum
off-time at 4.5V input voltage. The off-time should be about
500ns, which includes a 100ns guard band. The duty cycle
for (3.3V/4.5V) ≈ 73%. Frequency = (1 – DC)/tOFF, or
(1 – 0.73)/500ns = 540kHz. The switching frequency needs
to be lowered to 540kHz at 4.5V input. tON = DC/frequency,
or 1.35µs. The fSET pin voltage is 1/3 of VIN, and the IfSET
current equates to 38µA with the internal 39.2k. The IfSET
current needs to be 24µA for 540kHz operation. A resistor
can be placed from VOUT to fSET to lower the effective IfSET
current out of the fSET pin to 24µA. The fSET pin is 4.5V/3
=1.5V and VOUT = 3.3V, therefore 130k will source 14µA
into the fSET node and lower the IfSET current to 24µA.
This enables the 540kHz operation and the 4.5V to 20V
input operation for down converting to 3.3V output. The
frequency will scale from 540kHz to 1.1MHz over this
input range. This provides for an effective output current
of 8A over the input range.
4601afe
For more information www.linear.com/LTM4601A
21
LTM4601A/LTM4601A-1
APPLICATIONS INFORMATION
VOUT
VIN
10V TO 20V
R2
100k
R4
100k
TRACK/SS CONTROL
VIN
PGOOD
MPGM
RUN
COMP
INTVCC
DRVCC
5% MARGIN
R1
392k
1%
C1
10µF
25V
C2
10µF
25V
PLLIN TRACK/SS
VOUT
VFB
MARG0
MARG1
LTM4601A-1
SGND
PGND
REVIEW TEMPERATURE
DERATING CURVE
+
C6 100pF
VOUT
5V
C3
8A
100µF
REFER TO
6.3V
SANYO POSCAP TABLE 2
VOUT_LCL
NC3
NC1
NC2
fSET
RfSET
100k
RSET
8.25k
MARGIN CONTROL
IMPROVE
EFFICIENCY
FOR ≥12V INPUT
SOT-323
CMSSH-3C
4601A F16
Figure 16. 5V at 8A Design Without Differential Amplifier
VIN
4.5V TO 16V
VOUT
R2
100k
TRACK/SS CONTROL
R4
100k
VIN
PGOOD
PGOOD
C2
10µF
25V
×3
MPGM
RUN
COMP
INTVCC
DRVCC
PLLIN TRACK/SS
VOUT
LTM4601A
R1
392k
SGND
5% MARGIN
PGND
REVIEW TEMPERATURE
DERATING CURVE
VFB
MARG0
MARG1
VOUT_LCL
DIFFVOUT
VOSNS+
VOSNS–
fSET
C6 100pF
+
RfSET
130k
MARGIN CONTROL
VOUT
3.3V
10A
C3
100µF
6.3V
SANYO POSCAP
RSET
13.3k
4601A F17
Figure 17. 3.3V at 10A Design
4601afe
22
For more information www.linear.com/LTM4601A
LTM4601A/LTM4601A-1
APPLICATIONS INFORMATION
CLOCK SYNC
C5
0.01µF
VOUT
VIN
4.5V TO 20V
R2
100k
R4
100k
PGOOD
CIN
BULK
OPT
+
CIN
10µF
25V
×3 CER
PLLIN TRACK/SS
VOUT
VIN
PGOOD
MPGM
RUN
ON/OFF
COMP
INTVCC
DRVCC
R1
392k
LTM4601A
SGND
PGND
REVIEW TEMPERATURE
DERATING CURVE
VFB
MARG0
MARG1
C3 100pF
COUT1
100µF
6.3V
MARGIN
CONTROL
VOUT_LCL
DIFFVOUT
VOSNS+
VOSNS–
fSET
RSET
40.2k
4601A F18
5% MARGIN
+
COUT2
470µF
6.3V
VOUT
1.5V
12A
REFER TO
TABLE 2 FOR
DIFFERENT
OUTPUT
VOLTAGE
Figure 18. Typical 4.5V to 20V, 1.5V at 12A Design
VOUT
VIN
4.5V TO 20V
118k
1%
R2
100k
+
C1
0.1µF
LTC6908-1
1
2
3
V+
OUT1
GND
OUT2
SET
MOD
6
5
4
CLOCK SYNC
0° PHASE
C5*
100µF
25V
C2
10µF
25V
×2
R4
100k
VIN
PGOOD
MPGM
RUN
COMP
INTVCC
DRVCC
R1
392k
SGND
PLLIN TRACK/SS
VOUT
LTM4601A
PGND
5%
MARGIN
2-PHASE
OSCILLATOR
VFB
MARG0
MARG1
60.4k + R
SET
N
RSET
N = NUMBER OF PHASES
VOUT = 0.6V
TRACK/SS CONTROL
C6 220pF
VOUT_LCL
DIFFVOUT
VOSNS+
VOSNS–
C3
22µF
6.3V
C4
470µF
6.3V
VOUT
1.5V
24A
+
REFER TO
TABLE 2
fSET
RSET
20k
100pF
MARGIN CONTROL
CLOCK SYNC
180° PHASE
TRACK/SS CONTROL
4.5V TO 20V
C7
0.033µF
VIN
PGOOD
PGOOD
MPGM
RUN
COMP
INTVCC
DRVCC
C8
10µF
25V
×2
PLLIN TRACK/SS
VOUT
LTM4601A-1
392k
SGND
PGND
C3
22µF
6.3V
VFB
MARG0
MARG1
C4
470µF
6.3V
REFER TO
TABLE 2
VOUT_LCL
NC3
NC2
NC1
fSET
+
4601A F19
*C5 OPTIONAL TO REDUCE ANY LC RINGING.
NOT NEEDED FOR LOW INDUCTANCE PLANE CONNECTION
Figure 19. 2-Phase Parallel, 1.5V at 24A Design
4601afe
For more information www.linear.com/LTM4601A
23
24
+
C11
100µF
35V
OPT
3.3V
For more information www.linear.com/LTM4601A
C2
10µF
25V
×3
VIN
PGOOD
SGND
MPGM
RUN
COMP
INTVCC
DRVCC
VIN
PGOOD
SGND
MPGM
RUN
ON/OFF
COMP
INTVCC
DRVCC
R1
392k
R3
100k
8V TO 16V
5% MARGIN
PGOOD
R2
100k
R27
392k
ON/OFF
5% MARGIN
C8
10µF
25V
×3
PGOOD
R7
100k
8V TO 16V
INTERMEDIATE
BUS
3.3V
R6
100k
–48V
INPUT
fSET
VOUT_LCL
DIFFVOUT
VOSNS+
VOSNS–
PGND
LTM4601A
fSET
VOUT_LCL
DIFFVOUT
VOSNS+
VOSNS–
VFB
MARG0
MARG1
PLLIN TRACK/SS
VOUT
CLOCK SYNC 3
PGND
LTM4601A
VFB
MARG0
MARG1
PLLIN TRACK/SS
VOUT
MARGIN
CONTROL
C8 100pF
R19
30.1k
MARGIN
CONTROL
R8
13.3k
R12
30.1k
R21
60.4k
C7
0.15µF
C12 100pF
TRACK/SS
CONTROL
CLOCK SYNC 1
3.3V
+
REFER TO
TABLE 2
C3
22µF
6.3V
+
1.8V AT 12A
REFER TO
TABLE 2
C9
22µF
6.3V
R17
59k
LTC6902
C4
470µF
6.3V
C10
470µF
6.3V
V+
SET
DIV
MOD
PH
GND
OUT1 OUT4
OUT2 OUT3
3.3V AT 10A
4-PHASE
OSCILLATOR
8V TO 16V
C26
0.1µF
C14
10µF
25V
×3
PGND
LTM4601A
VIN
PGOOD
SGND
PGND
LTM4601A
fSET
VOUT_LCL
DIFFVOUT
VOSNS+
VOSNS–
VFB
MARG0
MARG1
PLLIN TRACK/SS
VOUT
fSET
VOUT_LCL
DIFFVOUT
VOSNS+
VOSNS–
VFB
MARG0
MARG1
PLLIN TRACK/SS
VOUT
CLOCK SYNC 4
SGND
MPGM
RUN
COMP
INTVCC
DRVCC
VIN
PGOOD
CLOCK SYNC 2
MPGM
RUN
ON/OFF
COMP
INTVCC
DRVCC
R14
392k
R16
100k
8V TO 16V
5% MARGIN
PGOOD
R15
100k
R9
392k
ON/OFF
5% MARGIN
3.3V
C14
10µF
25V
×3
8V TO 16V
R11
100k
PGOOD
R10
100k
3.3V
4-Phase, Four Outputs (3.3V, 2.5V, 1.8V and 1.5V) with Coincident Tracking
R18
19.1k
R13
40.2k
R25
60.4k
4601A TA04
MARGIN
CONTROL
C24 100pF
R26
40.2k
MARGIN
CONTROL
C18 100pF
R24
19.1k
R23
60.4k
3.3V
3.3V
+
REFER TO
TABLE 2
C16
22µF
6.3V
+
1.5V AT 12A
REFER TO
TABLE 2
C16
22µF
6.3V
2.5V AT 12A
C15
470µF
6.3V
C15
470µF
6.3V
LTM4601A/LTM4601A-1
TYPICAL APPLICATIONS
4601afe
aaa Z
0.630 ±0.025 Ø 133x
3.1750
3.1750
SUGGESTED PCB LAYOUT
TOP VIEW
1.9050
PACKAGE TOP VIEW
E
0.6350
0.0000
0.6350
4
1.9050
PIN “A1”
CORNER
6.9850
5.7150
4.4450
4.4450
5.7150
6.9850
Y
For more information www.linear.com/LTM4601A
6.9850
5.7150
4.4450
3.1750
1.9050
0.6350
0.0000
0.6350
1.9050
3.1750
4.4450
5.7150
6.9850
X
D
2.45 – 2.55
aaa Z
SYMBOL
A
A1
A2
b
b1
D
E
e
F
G
aaa
bbb
ccc
ddd
eee
NOM
3.42
0.60
2.82
0.75
0.63
15.0
15.0
1.27
13.97
13.97
DIMENSIONS
0.15
0.10
0.20
0.30
0.15
MAX
3.62
0.70
2.92
0.90
0.66
NOTES
DETAIL B
PACKAGE SIDE VIEW
A2
TOTAL NUMBER OF BALLS: 133
MIN
3.22
0.50
2.72
0.60
0.60
DETAIL A
b1
0.27 – 0.37
SUBSTRATE
A1
ddd M Z X Y
eee M Z
DETAIL B
MOLD
CAP
ccc Z
Øb (133 PLACES)
// bbb Z
A
Z
F
e
b
b
L
K
J
G
G
F
e
E
PACKAGE BOTTOM VIEW
H
D
C
B
A
DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
4
TRAY PIN 1
BEVEL
BGA 133 0511 REV B
PACKAGE IN TRAY LOADING ORIENTATION
LTMXXXXXX
µModule
5. PRIMARY DATUM -Z- IS SEATING PLANE
BALL DESIGNATION PER JESD MS-028 AND JEP95
3
2. ALL DIMENSIONS ARE IN MILLIMETERS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
M
DETAIL A
COMPONENT
PIN “A1”
3
SEE NOTES
(Reference(Reference
LTM DWGLTC
# 05-08-1877
Rev B)Rev B)
DWG # 05-08-1877
BGA Package
BGA Package
133-Lead133-Lead
(15mm (15mm
× 15mm
× 3.42mm)
× 15mm × 3.42mm)
1
2
3
4
5
6
7
8
9
10
11
12
PIN 1
LTM4601A/LTM4601A-1
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
PACKAGE DESCRIPTION
4601afe
25
For more information www.linear.com/LTM4601A
6.9850
5.7150
4.4450
3.1750
1.9050
0.6350
0.0000
0.6350
1.9050
3.1750
4.4450
5.7150
6.9850
4
PAD 1
CORNER
15
BSC
PACKAGE TOP VIEW
3.1750
3.1750
SUGGESTED PCB LAYOUT
TOP VIEW
1.9050
X
15
BSC
Y
DETAIL B
2.72 – 2.92
DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
LAND DESIGNATION PER JESD MO-222, SPP-010
SYMBOL TOLERANCE
aaa
0.10
bbb
0.10
eee
0.05
6. THE TOTAL NUMBER OF PADS: 133
5. PRIMARY DATUM -Z- IS SEATING PLANE
4
3
2. ALL DIMENSIONS ARE IN MILLIMETERS
3
M
L
TRAY PIN 1
BEVEL
COMPONENT
PIN “A1”
PADS
SEE NOTES
1.27
BSC
13.97
BSC
0.12 – 0.28
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
DETAIL A
0.27 – 0.37
SUBSTRATE
eee S X Y
DETAIL B
MOLD
CAP
0.630 ±0.025 SQ. 133x
aaa Z
2.45 – 2.55
bbb Z
aaa Z
0.6350
0.0000
0.6350
(Reference LTM DWG # 05-08-1755, Rev Ø)
Z
26
1.9050
LGA Package
133-Lead (15mm × 15mm × 2.82mm)
K
G
F
E
LTMXXXXXX
μModule
PACKAGE BOTTOM VIEW
H
D
C
B
LGA 133 0807 REV Ø
A
DETAIL A
PACKAGE IN TRAY LOADING ORIENTATION
J
13.97
BSC
1
2
3
4
5
6
7
8
9
10
11
12
C(0.30)
PAD 1
LTM4601A/LTM4601A-1
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
4601afe
6.9850
5.7150
4.4450
4.4450
5.7150
6.9850
LTM4601A/LTM4601A-1
PACKAGE DESCRIPTION
Table 5. Pin Assignment (Arranged by Pin Number)
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
A1
VIN
B1
VIN
C1
VIN
D1
PGND
E1
PGND
F1
PGND
A2
VIN
B2
VIN
C2
VIN
D2
PGND
E2
PGND
F2
PGND
A3
VIN
B3
VIN
C3
VIN
D3
PGND
E3
PGND
F3
PGND
A4
VIN
B4
VIN
C4
VIN
D4
PGND
E4
PGND
F4
PGND
A5
VIN
B5
VIN
C5
VIN
D5
PGND
E5
PGND
F5
PGND
A6
VIN
B6
VIN
C6
VIN
D6
PGND
E6
PGND
F6
PGND
A7
INTVCC
B7
PGND
C7
PGND
D7
–
E7
PGND
F7
PGND
A8
PLLIN
B8
–
C8
–
D8
PGND
E8
–
F8
PGND
A9
TRACK/SS
B9
PGND
C9
PGND
D9
INTVCC
E9
PGND
F9
PGND
A10
RUN
B10
–
C10
MTP1
D10
MTP2
E10
–
F10
–
A11
COMP
B11
MPGM
C11
fSET
D11
MTP3
E11
–
F11
PGOOD
A12
MPGM
B12
fSET
C12
MARG0
D12
MARG1
E12
DRVCC
F12
VFB
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
G1
PGND
H1
PGND
J1
VOUT
K1
VOUT
L1
VOUT
M1
VOUT
G2
PGND
H2
PGND
J2
VOUT
K2
VOUT
L2
VOUT
M2
VOUT
G3
PGND
H3
PGND
J3
VOUT
K3
VOUT
L3
VOUT
M3
VOUT
G4
PGND
H4
PGND
J4
VOUT
K4
VOUT
L4
VOUT
M4
VOUT
G5
PGND
H5
PGND
J5
VOUT
K5
VOUT
L5
VOUT
M5
VOUT
G6
PGND
H6
PGND
J6
VOUT
K6
VOUT
L6
VOUT
M6
VOUT
G7
PGND
H7
PGND
J7
VOUT
K7
VOUT
L7
VOUT
M7
VOUT
G8
PGND
H8
PGND
J8
VOUT
K8
VOUT
L8
VOUT
M8
VOUT
G9
PGND
H9
PGND
J9
VOUT
K9
VOUT
L9
VOUT
M9
VOUT
G10
–
H10
–
J10
VOUT
K10
VOUT
L10
VOUT
M10
VOUT
G11
SGND
H11
SGND
J11
–
K11
VOUT
L11
VOUT
M11
VOUT
G12
PGOOD
H12
SGND
J12
VOSNS+/NC2*
K12
DIFFVOUT/NC2*
L12
VOUT_LCL
M12
VOSNS–/NC1*
*LTM4601A-1 Only
4601afe
For more information www.linear.com/LTM4601A
27
LTM4601A/LTM4601A-1
PACKAGE DESCRIPTION
Pin Assignment Table 6
(Arranged by Pin Function)
PIN NAME
A1
A2
A3
A4
A5
A6
VIN
VIN
VIN
VIN
VIN
VIN
B1
B2
B3
B4
B5
B6
VIN
VIN
VIN
VIN
VIN
VIN
C1
C2
C3
C4
C5
C6
VIN
VIN
VIN
VIN
VIN
VIN
PIN NAME
D1
D2
D3
D4
D5
D6
D8
PGND
PGND
PGND
PGND
PGND
PGND
PGND
E1
E2
E3
E4
E5
E6
E7
PGND
PGND
PGND
PGND
PGND
PGND
PGND
F1
F2
F3
F4
F5
F6
F7
F8
F9
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
G1
G2
G3
G4
G5
G6
G7
G8
G9
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
H1
H2
H3
H4
H5
H6
H7
H8
H9
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PIN NAME
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
PIN NAME
A7
A8
A9
A10
A11
A12
INTVCC
PLLIN
TRACK/SS
RUN
COMP
MPGM
B12
fSET
C12
MARG0
D12
MARG1
E12
DRVCC
F12
VFB
G12
PGOOD
H12
SGND
J12
VOSNS+/NC2*
K12
DIFFVOUT/NC3*
L12
VOUT_LCL
M12
VOSNS–/NC1*
*LTM4601A-1 Only
PIN NAME
B7
B8
B9
B10
B11
PGND
PGND
MPGM
C7
C8
C9
C10
C11
PGND
PGND
MTP1
fSET
D7
D8
D9
D10
D11
PGND
INTVCC
MTP2
MTP3
E8
E9
E10
E11
PGND
-
F10
F11
PGOOD
G10
G11
SGND
H10
H11
SGND
J11
-
4601afe
28
For more information www.linear.com/LTM4601A
LTM4601A/LTM4601A-1
REVISION HISTORY
(Revision history begins at Rev C)
REV
DATE
DESCRIPTION
PAGE NUMBER
C
8/11
Added BGA package. Changes reflected throughout the data sheet.
D
2/14
Added SnPb BGA option
E
10/14
Added LTM4601A-1 BGA to data sheet
1 to 30
1, 2
1, 2, 25, 27,
28, 30
4601afe
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of itsinformation
circuits as described
herein will not infringe on existing patent rights.
For more
www.linear.com/LTM4601A
29
LTM4601A/LTM4601A-1
PACKAGE PHOTOS
3.42mm
15mm
15mm
15mm
2.82mm
15mm
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LTM4604A
4A Low Voltage DC/DC µModule Regulator
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8A Low Voltage DC/DC µModule Regulator
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This product contains technology licensed from Silicon Semiconductor Corporation.
30
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTM4601A
●
●
(408) 432-1900 FAX: (408) 434-0507
www.linear.com/LTM4601A
®
4601afe
LT 1014 REV E • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2007
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湘ICP备2023018690号
