LTM4611
Ultralow VIN, 15A DC/DC
µModule Regulator
Features
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Description
Complete Switch Mode Power Supply
Input Voltage Range: 1.5V to 5.5V
15A DC Output
Output Voltage Range: 0.8V to 5V
±1.5% Total DC Output Error
Differential Remote Sensing for Precision Regulation
Current Mode Control/ Fast Transient Response
Overcurrent Foldback Protection
Parallel Multiple LTM®4611s for Current Sharing
Frequency Synchronization
Selectable Pulse-Skipping or Burst Mode® Operation
Soft-Start/Voltage Tracking
Up to 94% Efficiency
Output Overvoltage Protection
Small 15mm × 15mm × 4.32mm LGA Package
The LTM®4611 is a high density 15A output, switch mode
DC/DC buck converter power supply capable of operating
from very low voltage input supplies. Included in the package are the buck switching controller, power FETs, inductor and loop-compensation components. The LTM4611
delivers up to 15A continuous current at high efficiency
from an input voltage of 1.5VIN up to 5.5VIN. The output
voltage is set between 0.8V and 5V by a resistor. Only a
few input and output capacitors are needed.
High switching frequency and a current mode architecture
enable a very fast transient response to line and load
changes without sacrificing stability. The device supports
frequency synchronization, multiphase/current sharing
operation, Burst Mode operation and output voltage tracking for supply rail sequencing.
Applications
The LTM4611 is available in a thermally enhanced 15mm
× 15mm × 4.32mm LGA package. The LTM4611 is PB-free
and RoHS compliant.
Telecom Servers and Networking Equipment
Storage and ATCA Cards
n General Purpose Point of Load Regulation
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L, LT, LTC, LTM, Linear Technology, the Linear logo, Burst Mode, PolyPhase and µModule are
registered trademarks of Linear Technology Corporation. All other trademarks are the property
of their respective owners. Protected by U.S. Patents, including 5481178, 5847554, 6580258,
6304066, 6476589, 6774611, 6677210.
Click to view associated TechClip Videos.
Typical Application
1.5VIN to 5.5VIN, 15A Step-Down DC/DC µModule® Regulator
96
22µF
×3
94
CSS
0.1µF
VIN
PGOOD
VOUT
TRACK/SS
LTM4611
CFF*
VFB
RUN
VOUT_LCL
MODE_PLLIN
DIFFVOUT
VOUT**
STEP-DOWN
15A
100µF*
×4
VOSNS+
SGND GND
92
EFFICIENCY (%)
VIN
1.5V TO 5.5V
Efficiency vs Load Current
90
5VIN, 3.3VOUT
3.3VIN, 2.5VOUT
2.5VIN, 1.5VOUT
2.5VIN, 1.2VOUT
3.3VIN, 1VOUT
1.5VIN, 0.9VOUT
5VIN, 1VOUT
88
86
84
82
VOSNS–
80
CP*
4611 TA01
RFB**
*SEE TABLE 5
**SEE TABLE 1
78
0
5
10
LOAD CURRENT (A)
15
4611 TA01b
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1
LTM4611
Absolute Maximum Ratings
(Note 1)
Terminal Voltages
VIN............................................................ –0.2V to 6V
VOUT with
DIFF AMP.....–0.1V to the Lesser of (VIN + 0.1V) or 4V
VOUT without
DIFF AMP...–0.1V to the Lesser of (VIN + 0.1V) or 5.5V
RUN, INTVCC, VOUT_LCL...........................................6V
MODE_PLLIN, PLLFLTR/fSET,
TRACK/SS, VOSNS–, VOSNS+,
PGOOD.................................................. –0.3V to 5.5V
COMP, VFB.............................................. –0.3V to 2.7V
Terminal Currents
DIFFVOUT.............................................. –10mA to 1mA
Temperatures
Operating Junction Temperature Range
(Note 2) ............................................. –40°C to 125°C
Storage Temperature Range............... –55°C to 125°C
Peak Solder Reflow Body Temperature
(Note 3)............................................................. 250°C
Pin Configuration
1
2
3
VIN
4
5
TOP VIEW
INTVCC
TRACK/SS
MODE_PLLIN
RUN COMP
6
7
8
9
10
11
12
A
VIN
PLLFLTR/fSET
B
C
MTP1-9
D
E
GND
VOUT
INTVCC
F
VFB
G
PGOOD
H
SGND
J
VOSNS+
K
DIFFVOUT
L
VOUT_LCL
M
VOSNS–
LGA PACKAGE
133-LEAD (15mm × 15mm × 4.32mm)
TJ(MAX) = 125°C
θJCtop = 26°C/W, θJCbottom = 2.3°C/W, θJB = 10°C/W, θJA = 14°C/W
θ VALUES DETERMINED PER JESD51-12
WEIGHT = 2.6 GRAMS
Order Information
LEAD FREE FINISH
TRAY
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTM4611EV#PBF
LTM4611EV#PBF
LTM4611V
133-Lead (15mm × 15mm × 4.32mm) LGA
–40°C to 125°C
LTM4611IV#PBF
LTM4611IV#PBF
LTM4611V
133-Lead (15mm × 15mm × 4.32mm) LGA
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
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LTM4611
Electrical
Characteristics l denotes the specifications which apply over the full internal operating
The
junction temperature range, otherwise specifications are at TA = 25°C, VIN = 3.3V, per the typical application in Figure 21.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input Specifications
VIN
Input DC Voltage
VRUN
RUN Pin On Threshold
VRUNHYS
RUN Pin On Hysteresis
VRUN(FLOAT)
RUN Pin Voltage when Floating
IRUN(UP,1V)
RUN Pin Pull-Up Current
(RUN = 1V)
1.1
µA
IRUN(UP,1.5V)
RUN Pin Pull-Up Current
(RUN = 1.5V)
10
µA
IRUN(DOWN,5V)
RUN Pin Pull-Down Current
(RUN = 5V)
1
nA
IQ
Input Supply Bias Current
VOUT = 1.5V, Burst Mode Operation, IOUT = 0.1A
VOUT = 1.5V, Pulse-Skipping Mode, IOUT = 0.1A
VOUT = 1.5V, Switching Continuous, IOUT = 0.1A
Shutdown, RUN = 0V
70
140
145
1.1
mA
mA
mA
mA
IS(VIN)
Input Supply Current
VIN = 2.5V, VOUT = 1.5V, IOUT = 15A
VIN = 3.3V, VOUT = 1.5V, IOUT = 15A
VIN = 5V, VOUT = 1.5V, IOUT = 15A
VIN = 1.5V, VOUT = 0.8V, IOUT = 15A
10.4
7.9
5.3
10.2
A
A
A
A
VRUN Rising
l
1.5
l
1.1
5.5
1.22
1.35
80
3.4
3.65
V
V
mV
4
V
Output Specifications
VOUT(DC)
Output Voltage, Total Variation
with Line and Load
Utilizing DIFF_AMP, RFB = Not Used, VIN = 1.5V to
l
5.5V, IOUT = 0A to 15A (Note 4), RFB Electrically
Floating, MODE_PLLIN = GND
VOUT(RANGE)
Utilizing DIFF_AMP
0.785
0.781
0.797
0.797
0.809
0.813
V
V
(Example See Figure 21)
3.7
V
Not Utilizing DIFF_AMP
(Example See Figure 20)
5.4
V
IOUT(DC)
Output Continuous Current Range
VOUT = VFB (Note 4)
∆VOUT (Line)
VOUT
Line Regulation Accuracy
VOUT = VFB, VIN from 1.5V to 5.5V, IOUT = 0A
l
0
∆VOUT (Load)
VOUT
Load Regulation Accuracy
VOUT = 1.5V, IOUT = 0A to 15A, VIN = 3.3V
(Note 4)
l
VOUT(AC)
Output Ripple Voltage
IOUT = 0A, COUT = 100µF ×4 X5R Ceramic,
VIN = 3.3V, VOUT = 1.5V
8
mVP-P
∆VOUT(START)
Turn-On Overshoot
COUT = 100µF ×4 X5R Ceramic, VOUT = 1.5V,
IOUT = 0A, VIN = 3.3V, CSS = 1nF
5
mV
tSTART
Turn-On Time
COUT = 100µF ×4 X5R Ceramic, No Load,
CSS = 1nF, VIN = 3.3V, VOUT = 1.5V
500
µs
∆VOUTLS
Peak Deviation for Dynamic Load
Load: 0% to 50% to 0% of Full Load
VIN = 3.3V, VOUT = 1.5V, COUT = 100µF ×4
X5R Ceramic, CFF = 100pF
60
mV
tSETTLE
Settling Time for Dynamic Load
Step
Load: 0% to 50% to 0% of Full Load
VIN = 3.3V, VOUT = 1.5V, COUT = 100µF ×4
X5R Ceramic, CFF = 100pF
40
µs
IOUT(PK)
Output Current Limit
VIN = 5V, VOUT = 1.5V
VIN = 3.3V, VOUT = 1.5V
30
30
A
A
0.2
15
A
0.3
%
0.5
%
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3
LTM4611
Electrical
Characteristics l denotes the specifications which apply over the full internal operating
The
junction temperature range, otherwise specifications are at TA = 25°C, VIN = 3.3V, per the typical application in Figure 21.
SYMBOL
PARAMETER
CONDITIONS
Voltage at VFB Pin
IOUT = 0A, VOUT = VFB
MIN
TYP
MAX
UNITS
l
0.783
0.797
0.811
V
l
0.84
0.87
0.89
V
0.9
1.4
1.9
µA
Control Section
VFB
–10
IFB
nA
VOVL
Feedback Overvoltage Lockout
ITRACK/SS
Track Pin Soft-Start Pull-Up
Current
TRACK/SS = 0V
tON(MIN)
Minimum On-Time
(Note 5)
RFBHI
Resistor Between VOUT_LCL
and VFB Pins
VOSNS+,
VOSNS – CM RANGE
Common Mode Input Range
VIN = 3.3V, Run > 1.5V
0
INTVCC – 1
V
DIFFVOUT Range
DIFF_AMP Output Voltage Range
VIN = 3.3V, DIFFVOUT Load = 100k
0
INTVCC
V
VOS
DIFF_AMP Input Offset Voltage
Magnitude
90
60.05
60.40
ns
60.75
1.25
2
l
1
kΩ
mV
mV
AV
DIFF_AMP Differential Gain
VPGOOD
PGOOD Trip Level
SR
DIFF_AMP Slew Rate
2
V/µs
GBP
DIFF_AMP Gain-Bandwidth
Product
3
MHz
CMRR
DIFF_AMP Common Mode
Rejection
100
RIN
DIFF_AMP Input Resistance
VFB with Respect to Set Output
VFB Ramping Positive, PGOOD Transitioning
VFB Ramping Positive, PGOOD Transitioning
VFB Ramping Negative, PGOOD Transitioning
VFB Ramping Negative, PGOOD Transitioning
–10
5
5
–10
–7.5
7.5
7.5
–7.5
V/V
–5
10
10
–5
%
%
%
%
dB
VOSNS+ to GND
19.9
20.0
20.1
kΩ
4.8
5
5.2
V
INTVCC Linear Regulator
VINTVCC
Internal VCC Voltage
1.5V < VIN < 5.5V
VINTVCC Load Reg
INTVCC Load Regulation
ICC = 0 to 50mA
0.5
%
Oscillator and Phase-Locked Loop
fS
Output Ripple Voltage Frequency
fSYNC
SYNC Capture Range
PLLFLTR/fSET(FLOAT) PLLFLTR/fSET Open-Circuit
Voltage
VIN = 3.3V, VOUT = 1.5V,
0.85V ≤ PLLFLTR/fSET ≤ 2.0V
280
835
kHz
360
710
kHz
PLLFLTR/fSET Pin Voltage When Floating
1.23
V
Frequency Nominal Nominal Frequency
PLLFLTR/fSET Floating
500
kHz
Frequency Low
Lowest Frequency
PLLFLTR/fSET = 0.85V
330
kHz
Frequency High
Highest Frequency
PLLFLTR/fSET = 2.0V
780
kHz
IPLLFLTR
PLLFLTR
Sourcing Capability
Sinking Capability
Mode_PLLIN Frequency > fOSC
Mode_PLLIN Frequency < fOSC
–13
13
µA
µA
RMODE(PLLIN)
Mode_PLLIN Input Resistance
250
kΩ
VIH
Clock Input Level High
VIL
Clock Input Level Low
Mode_PLLIN
Clock
Clock Input Duty Cycle Range
2.0
40
V
50
0.6
V
60
%
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LTM4611
Electrical Characteristics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTM4611 is tested under pulsed load conditions such that
TJ ≈ TA. The LTM4611E is guaranteed to meet performance specifications
over the 0°C to 125°C operating junction temperature (TJ) range.
Specifications over the full –40°C to 125°C operating junction temperature
range are assured by design, characterization and correlation with
statistical process controls. The LTM4611I is guaranteed to meet
specifications over the full –40°C to 125°C operating junction temperature
range. Note that the maximum ambient temperature consistent with
these specifications is determined by specific operating conditions in
conjunction with board layout, the rated package thermal resistance and
other environmental factors.
Note 3: Consistent with Pb-free 260°C peak IR reflow soldering profiles.
See Application Note 100.
Note 4: See output current derating curves for different VIN, VOUT and TA.
Note 5: The minimum on-time condition is specified for a peak-to-peak
inductor ripple current of ~40% of IMAX Load. (See the Typical Applications
section)
Typical Performance Characteristics
85
80
75
3
9
12
6
OUTPUT CURRENT (A)
85
75
15
1.5VOUT
1.2VOUT
1.0VOUT
0.9VOUT
0.8VOUT
0
3
9
12
6
OUTPUT CURRENT (A)
0
3
EFFICIENCY (%)
EFFICIENCY (%)
EFFICIENCY (%)
90
2.5VOUT
1.8VOUT
1.5VOUT
1.2VOUT
85
80
1.0VOUT
0.9VOUT
0.8VOUT
9
12
6
OUTPUT CURRENT (A)
15
4611 G04
3
9
12
6
OUTPUT CURRENT (A)
75
3.3VOUT
2.5VOUT
1.8VOUT
1.5VOUT
0
3
1.2VOUT
1.0VOUT
0.9VOUT
0.8VOUT
9
12
6
OUTPUT CURRENT (A)
15
Burst Mode Efficiency
95
80
0
1.0VOUT
0.9VOUT
0.8VOUT
4611 G03
Efficiency vs Load Current at
5VIN, Forced Continuous Mode
90
75
75
15
1.8VOUT
1.5VOUT
1.2VOUT
4611 G02
Efficiency vs Load Current at
3.3VIN, Forced Continuous Mode
85
85
80
4611 G01
95
Efficiency vs Load Current at
2.5VIN, Forced Continuous Mode
90
80
0
95
90
EFFICIENCY (%)
90
EFFICIENCY (%)
95
1.2VOUT
1.0VOUT
0.9VOUT
0.8VOUT
Efficiency vs Load Current at
1.8VIN, Forced Continuous Mode
EFFICIENCY (%)
95
Efficiency vs Load Current at
1.5VIN, Forced Continuous Mode
15
4611 G05
95
90
85
80
75
70
65
60
55
50
45
40
35
30
0.1
3.3VIN TO 1.5VOUT
5VIN TO 1VOUT
1
OUTPUT CURRENT (A)
10
4611 G06
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5
LTM4611
Typical Performance Characteristics
1V Transient Response, 3.3VIN
Pulse-Skipping Mode Efficiency
EFFICIENCY (%)
95
90
85
80
75
70
65
60
55
50
45
40
35
30
0.1
3.3VIN TO 1.5VOUT
1V Transient Response, 5VIN
VOUT
50mV/DIV
AC-COUPLED
VOUT
50mV/DIV
AC-COUPLED
ILOAD
5A/DIV
ILOAD
5A/DIV
5VIN TO 1VOUT
1
OUTPUT CURRENT (A)
4611 G08
20µs/DIV
VIN = 3.3V, VOUT = 1V, USING DIFF AMP
4 × 100µF CERAMIC OUTPUT CAPACITORS
CFF = 47pF, CP = NONE
7.5A LOAD STEP AT 7.5A/µs
4611 G09
20µs/DIV
VIN = 5V, VOUT = 1V, USING DIFF AMP
4 × 100µF CERAMIC OUTPUT CAPACITORS
CFF = 47pF, CP = NONE
7.5A LOAD STEP AT 7.5A/µs
Start-Up, No Load
Start-Up, 15A Load
10
4611 G07
3.3V Transient Response, 5VIN
VOUT
50mV/DIV
AC-COUPLED
VIN
1V/DIV
VIN
1V/DIV
VOUT
500mV/DIV
ILOAD
5A/DIV
IIN
5A/DIV
VOUT
500mV/DIV
ILOAD
5A/DIV
IIN
1A/DIV
4611 G10
20µs/DIV
VIN = 5V, VOUT = 3.3V, USING DIFF AMP
2 × 100µF CERAMIC OUTPUT CAPACITORS
CFF = 10pF, CP = NONE
7.5A LOAD STEP AT 7.5A/µs
4611 G11
1ms/DIV
VIN = 3.3V, VOUT = 1.5V, NO LOAD
3 × 22µF CERAMIC INPUT CAPACITORS
CSS = 10nF
4 × 100µF CERAMIC OUTPUT CAPACITORS
CFF = 33pF, CP = 10pF
4611 G12
1ms/DIV
VIN = 3.3V, VOUT = 1.5V, 100mΩ LOAD
3 × 22µF CERAMIC INPUT CAPACITORS
CSS = 10nF
4 × 100µF CERAMIC OUTPUT CAPACITORS
CFF = 33pF, CP = 10pF
Start-Up, Pre-Bias
Short-Circuit, 15A
Short-Circuit, No Load
VOUT
500mV/DIV
ILOAD
2mA/DIV
IIN
1A/DIV
RUN
5V/DIV
4611 G13
2ms/DIV
VIN = 3.3V, VOUT = 1.5V, 0.75V PRE-BIAS LOAD
3 × 22µF CERAMIC INPUT CAPACITORS
CSS = 10nF
4 × 100µF CERAMIC OUTPUT CAPACITORS
CFF = 33pF, CP = 10pF
VOUT
500mV/DIV
VOUT
500mV/DIV
IIN
2A/DIV
IIN
1A/DIV
20µs/DIV
VIN = 3.3V, VOUT = 1.5V
15A LOAD PRIOR TO SHORT
4611 G14
20µs/DIV
VIN = 3.3V, VOUT = 1.5V
NO LOAD PRIOR TO SHORT
4611 G15
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LTM4611
Pin Functions
VIN (A1-A6, B1-B6, C1-C6): Power Input Pins. Apply input
voltage between these pins and GND pins. Recommend
placing input decoupling capacitance directly between VIN
pins and GND pins.
VOUT (J1-J10, K1-K11, L1-L11, M1-M11): Power Output
Pins. Apply output load between these pins and GND
pins. Recommend placing output decoupling capacitance
directly between these pins and GND pins. Review Table 5.
GND (B7, B9, C7, C9, D1-D6, D8, E1-E7, E9, F1-F9, G1-G9,
H1-H9): Power Ground Pins for Both Input and Output
Returns.
PGOOD (F11, G12): Output Voltage Power Good Indicator.
Open-drain logic output that is pulled to ground when the
output voltage exceeds a ±5% regulation window. Both
pins are tied together internally.
SGND (G11, H11, H12): Signal Ground Pin. Return ground
path for all analog and low power circuitry. Tie a single
connection to the output capacitor GND in the application.
See the layout guidelines in Figure 17.
MODE_PLLIN (A8): Forced Continuous Mode, Burst Mode
Operation, or Pulse-Skipping Mode Selection Pin and
External Synchronization Input to Phase Detector Pin.
Connect this pin to GND to force continuous mode
operation. Connect to INTVCC to enable pulse-skipping mode operation. Leaving the pin floating will
enable Burst Mode operation. A clock on this pin will
enable synchronization with forced continuous operation.
See the Applications Information section.
PLLFLTR/f SET (B12): Phase-Locked Loop Lowpass
Filter for the Internal Phase Detector. LTM4611’s default
switching frequency is 500kHz. Its switching frequency
can be increased by connecting a resistor from this pin to
INTVCC, or decreased by connecting a resistor from this
pin to SGND. See the Applications Information section.
VFB (F12): The Negative Input of the Error Amplifier.
Internally, this pin is connected to VOUT_LCL with a 60.4k
precision resistor. Different output voltages can be programmed with an additional resistor between the VFB and
GND pins. In PolyPhase® operation, tying the VFB pins
together allows for parallel operation. See the Applications
Information section for details.
TRACK/SS (A9): Output Voltage Tracking Pin and SoftStart Inputs. The pin has a 1.4µA pull-up current source.
A capacitor from this pin to ground will set a soft-start
ramp rate. In tracking, the regulator output can be tracked
to a different voltage. The different voltage is applied to
a voltage divider then the slave output’s track pin. This
voltage divider is equal to the slave output’s feedback
divider for coincidental tracking. Tie all TRACK/SS pins
together for parallel operation. See the Applications Information section.
COMP (A11): Current Control Threshold and Error Amplifier
Compensation Point. The current comparator threshold
increases with this control voltage. Tie all COMP pins
together for parallel operation. The device is internally
compensated.
RUN (A10): Run Control Pin. A voltage above 1.35V will
turn on in the module. The VIN undervoltage lockout (UVLO)
of the LTM4611 must be set with resistor networks from
VIN to RUN and optionally from RUN to GND. Tie all RUN
pins together for parallel operation.
INTVCC (A7, D9): Internal 5V LDO for Driving the Control
Circuitry and the Power MOSFET Drivers. Both pins are
internally connected.
VOUT_LCL (L12): This pin connects to VOUT through a 1M
resistor and to VFB with a 60.4k resistor. The remote sense
amplifier output DIFFVOUT is connected to VOUT_LCL, and
drives the 60.4k top feedback resistor in remote sensing
applications. When the remote sense amplifier is used,
the DIFF_VOUT effectively eliminates the 1MΩ from VOUT
to VOUT_LCL. When the remote sense amplifier is not used,
then connect VOUT_LCL to VOUT directly.
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LTM4611
Pin Functions
VOSNS+ (J12) (+): Input to the Remote Sense Amplifier.
This pin connects to the output remote sense point. The
remote sense amplifier is used for VOUT ≤ 3.7V. For VOUT
> 3.7V, tie VOSNS+ to GND to rail the output of the remote
sense amplifier.
VOSNS – (M12) (–): Input to the Remote Sense Amplifier.
This pin connects to the ground remote sense point. The
remote sense amplifier is used for VOUT ≤ 3.7 V. For VOUT >
3.7V, tie VOSNS – to INTVCC to rail the output of the remote
sense amplifier.
DIFFVOUT (K12): Output of the Remote Sense Amplifier.
This pin connects to the VOUT_LCL pin for remote sense
applications. Otherwise float when not used.
MTP1:A12, MTP2:B11, MTP3:C10, MTP4:C11, MTP5:
C12, MTP6:D10, MTP7:D11, MTP8:D12, MTP9:E12:
Extra mounting pads used for increased solder integrity
strength. Leave electrically open circuit.
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LTM4611
Block Diagram
INTVCC
1M
VOUT_LCL
VIN
R1
>1.35V = ON
7.5%. The top MOSFET is turned off and the
bottom MOSFET is turned on until the output is cleared.
Pulling the RUN pin below 1.1V forces the regulator into a
shutdown state. The TRACK/SS pin is used for programming the output voltage ramp and voltage tracking during
start-up. See the Application Information section.
The LTM4611 is internally compensated to be stable over
all operating conditions. Table 5 provides a guideline for
input and output capacitances for several operating conditions. The Linear Technology µModule Power Design
Tool will be provided for transient and stability analysis.
The VFB pin is used to program the output voltage with a
single external resistor to ground.
A remote sense amplifier is provided for accurately sensing
output voltages ≤3.7V at the load point.
Multiphase operation can be easily employed with the
synchronization inputs using an external clock source.
See the Typical Applications.
High efficiency at light loads can be accomplished with
selectable Burst Mode operation using the MODE_PLLIN
pin. These light-load features will accommodate battery
operation. Efficiency graphs are provided for light-load
operation in the Typical Performance Characteristics
section.
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LTM4611
Applications Information
The typical LTM4611 application circuit is shown in
Figure 21. External component selection is primarily
determined by the maximum load current and output
voltage. Refer to Table 5 for specific external capacitor
requirements for particular applications.
VIN to VOUT Step-Down Ratios
There are restrictions in the VIN to VOUT step-down
ratio that can be achieved for a given input voltage. The
VIN to VOUT minimum dropout is still a function of its load
current at very low input voltages. A dropout voltage of
300mV from input to output of LTM4611 is achievable
at 15A load, but reflected input voltage ripple and noise
should be taken into consideration in such applications.
Additionally, the transient-handling capability of the source
supply feeding LTM4611 can become an important factor
in truly achieving ultralow dropout at high output current.
For example, VIN can sag or overshoot dramatically when
LTM4611 responds to heavy transient step loads on its
output, if insufficient input bypass capacitance is used in
combination with a sluggish source supply.
When VOUT is expected to be within 600mV of VIN, or
when the caliber of the source supply is in question, it
is recommended to evaluate the amount and quality of
input bypass capacitance needed to maintain one’s target
dropout voltage with the source supply that will be used
in the end application. Demo Board DC1588A can be used
for such evaluation.
At very low duty cycles the minimum specified on-time
must be maintained. See the Frequency Adjustment section and temperature derating curves.
To prevent overstress to the µpower bias generator, do
not ramp up VIN at a rate exceeding 5V/µs (in practice, it
is difficult to violate this guideline.) There is no restriction
on how rapidly VIN may be discharged.
Output Voltage Programming
The PWM controller has an internal 0.8V ±1.75% reference
voltage over temperature. As shown in the Block Diagram,
a 60.4k internal feedback resistor connects the VOUT_LCL
and VFB pins together. When the remote sense amplifier
is used, then DIFFVOUT is connected to the VOUT_LCL pin.
If the remote sense amplifier is not used, then VOUT_LCL
connects to VOUT. The output voltage will default to 0.8V
with no feedback resistor. Adding a resistor RFB from VFB
to GND programs the output voltage:
VOUT = 0.8V •
60.4k + R FB
R FB
Table 1. VFB Resistor Table vs Various Output Voltages
VOUT
0.8V
1.0V
1.2V
1.5V
1.8V
2.5V
3.3V
5.0V
RFB (kΩ) Open
243
121
68.1
47.5
28.0
19.1
11.5
For parallel operation of N LTM4611s, the following equation can be used to solve for RFB:
RFB =
60.4k / N
VOUT
–1
0.8V
Tie the VFB pins together for each parallel output. The
COMP, TRACK/SS, VOUT_LCL, and RUN pins must also be
tied together as shown in Figures 18 and 19.
For parallel applications, best noise immunity can be
achieved by placing capacitors of value CP from VFB to GND,
and value CFF from VOUT to VFB, local to each µModule.
If space limitations impede realizing this, then placement
of capacitors of value N • CP from VFB to GND, and value
N • CFF from VOUT to the bussed VFB signal, can suffice.
Input Capacitors
The LTM4611 module should be connected to a low
AC impedance DC source. Additional input capacitors
are needed for the RMS input ripple current rating. The
ICIN(RMS) equation which follows can be used to calculate
the input capacitor requirement. Typically 22µF X7R ceramics are a good choice with RMS ripple current ratings
of ~2A each. A 100µF to 150µF surface mount aluminum
electrolytic bulk capacitor can be used for more input
bulk capacitance. This bulk input capacitor is only needed
if the input source impedance is compromised by long
inductive leads, traces or not enough source capacitance.
If low impedance power planes are used, then this bulk
capacitor is not needed.
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LTM4611
Applications Information
For a buck converter, the switching duty cycle can be
estimated as:
V
D = OUT
VIN
Without considering the inductor current ripple, for each
output, the RMS current of the input capacitor can be
estimated as:
ICIN(RMS) =
IOUT(MAX)
η%
• D • (1– D)
In the above equation, η% is the estimated efficiency of the
power module. The bulk capacitor can be a switcher-rated
electrolytic aluminum capacitor or a Polymer capacitor.
Output Capacitors
The LTM4611 is designed for low output voltage ripple
noise. The bulk output capacitors defined as COUT are
chosen with low enough effective series resistance (ESR)
to meet the output voltage ripple and transient requirements. COUT can be the low ESR tantalum capacitor, the
low ESR Polymer capacitor or ceramic capacitors. The
typical output capacitance range is from 200µF to 800µF.
Additional output filtering may be required by the system
designer, if further reduction of output ripple or dynamic
transient spikes is required. Table 5 shows a matrix of different output voltages and output capacitors to minimize
the voltage droop and overshoot during a 7A/µs transient.
The table optimizes total equivalent ESR and total bulk
capacitance to optimize the transient performance. Stability criteria are considered in the Table 5 matrix, and the
Linear Technology µModule Power Design Tool will be
provided for stability analysis. Multiphase operation will
reduce effective output ripple as a function of the number of phases. Application Note 77 discusses this noise
reduction versus output ripple current cancellation, but
the output capacitance should be considered carefully as
a function of stability and transient response. The Linear
Technology µModule Power Design Tool can calculate the
output ripple reduction as the number of implemented
phase’s increases by N times.
Burst Mode Operation
The LTM4611 is capable of Burst Mode operation in which
the power MOSFETs operate intermittently based on load
demand, thus saving quiescent current. For applications
where maximizing the efficiency at very light loads is a high
priority, Burst Mode operation should be applied. To enable
Burst Mode operation, simply leave the MODE_PLLIN pin
floating. During Burst Mode operation, the peak current of
the inductor is set to approximately 33% of the maximum
peak current value in normal operation even though the
voltage at the ITH pin indicates a lower value. The voltage
at the ITH pin drops when the inductor’s average current is
greater than the load requirement. As the ITH voltage drops
below 0.5V, the burst comparator trips, causing the internal
sleep line to go high and turn off both power MOSFETs.
In this sleep mode, the internal circuitry is partially turned
off, reducing the LTM4611’s quiescent current while the
load current is supplied by the output capacitors. When
the output voltage drops–causing ITH to rise–the internal
sleep line goes low and the LTM4611 resumes normal
operation. The next oscillator cycle turns on the top power
MOSFET and the switching cycle repeats.
Pulse-Skipping Mode Operation
In applications where low output ripple and high efficiency at intermediate currents are desired, pulse-skipping
mode should be used. Pulse-skipping operation allows
the LTM4611 to skip cycles at low output loads, thus
increasing efficiency by reducing switching loss. Tying
the MODE_PLLIN pin to INTVCC enables pulse-skipping
operation. With pulse-skipping mode at light load, the
internal current comparator may remain tripped for several
cycles, thus skipping operation cycles. This mode has lower
ripple than Burst Mode operation and maintains a higher
frequency operation than Burst Mode operation.
Forced Continuous Operation
In applications where fixed frequency operation is more
critical than low current efficiency, and where the lowest
output ripple is desired, forced continuous operation
should be used. Forced continuous operation can be
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LTM4611
Applications Information
enabled by tying the MODE_PLLIN pin to GND. In this
mode, inductor current is allowed to reverse during low
output loads, the ITH voltage is in control of the current
comparator threshold throughout, and the top MOSFET
always turns on with each oscillator pulse. During start-up,
forced continuous mode is disabled and inductor current
is prevented from reversing until the LTM4611’s output
voltage is in regulation.
Multiphase Operation
For outputs that demand more than 15A of load current,
multiple LTM4611 devices can be paralleled to provide
more output current without increasing input and output
voltage ripples. The MODE_PLLIN pin allows the LTM4611
to be synchronized to an external clock (between 360kHz
to 710kHz) and the internal phase-locked loop allows the
LTM4611 to lock onto input clock phase as well. The PLLFLTR/fSET pin has the onboard loop filter for the PLL. See
Figures 18 and 19 for a synchronizing example circuit.
A multiphase power supply significantly reduces the
amount of ripple current in both the input and output capacitors. The RMS input ripple current is reduced by, and
0.60
0.55
0.50
the effective ripple frequency is multiplied by, the number
of phases used (assuming that the input voltage is greater
than the number of phases used times the output voltage).
The output ripple amplitude is also reduced by the number
of phases used. See Application Note 77.
The LTM4611 device is an inherently current mode controlled device, so parallel modules will have good current
sharing. This will balance the thermals on the design.
Tie the COMP, VOUT_LCL and VFB pins of each LTM4611
together to share the current evenly. In addition, tie the
respective TRACK/SS and RUN pins of paralleled LTM4611
devices together, to ensure proper start-up and shutdown
behavior. Figures 18 and 19 show schematics of LTM4611
devices operating in parallel.
Input RMS Ripple Current Cancellation
Application Note 77 provides a detailed explanation of
multiphase operation. The input RMS ripple current cancellation mathematical derivations are presented, and a
graph is displayed representing the RMS ripple current
reduction as a function of the number of interleaved phases
(see Figure 2).
1 PHASE
2 PHASE
3 PHASE
4 PHASE
6 PHASE
RMS INPUT RIPPLE CURRENT
DC LOAD CURRENT
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
DUTY FACTOR (VOUT/VIN)
4611 F02
Figure 2. Normalized Input RMS Ripple Current vs Duty Factor for One to Six µModules (Phases)
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LTM4611
Applications Information
PLL, Frequency Adjustment and Synchronization
The default switching frequency of the LTM4611–with
PLLFLTR/fSET left floating–is 500kHz, nominally. The
PLLFLTR/fSET pin is driven to 1.23V through a high impedance (>350kΩ) network. If desired, a resistor (RfSET)
can be connected from the PLLFLTR/fSET pin to INTVCC
to increase the switching frequency to as high as 780kHz,
nominally. Alternatively, RfSET can instead be connected
from PLLFLTR/fSET to signal ground (SGND) to decrease
the switching frequency to as low as the minimum specified
value of 330kHz, nominally. In practical terms, however, be
advised that switching frequencies below 400kHz may be
of limited benefit due to the high inductor ripple currents
associated with that operating condition. See Figure 3.
There exists a fundamental trade-off between switch
mode DC/DC power conversion efficiency and switching
frequency: higher operating module switching frequency
enables the smallest overall solution size (minimized
output capacitance) for a given application; whereas,
lower switching frequency enables the highest efficiency
for a given application (to the extent that peak and RMS
inductor currents can be supported), but requires more
output capacitance to maintain comparable output voltage
ripple and noise characteristics.
2.05
800
1.91
750
1.78
1.64
1.50
1.37
RfSET CONNECTED
TO INTVCC
700
650
RfSET
NOT USED
600
550
1.23
500
1.09
450
0.96
0.82
400
RfSET CONNECTED
TO GND
350
0.68
300
SWITCHING FREQUENCY
250
PLLFLTR/fSET VOLTAGE
0.41
200
1
10
100
0.1
VALUE OF RESISTOR ON PLLFLTR/fSET PIN (MΩ)
SWITCHING FREQUENCY (kHz)
PLLFLTR/fSET PIN VOLTAGE (V)
The LTM4611 can be synchronized from 360kHz to 710kHz
with an input clock that has a high level above 2V and a
low level below 0.6V. Again in practical terms, be advised
that switching frequencies below 400kHz may be of limited
0.55
4611 F03
Figure 3. Relationship Between Oscillator Frequency,
PLLFLTR/fSET Voltage, and External RISET Value and
Connection
14
benefit due to the high inductor ripple currents associated
with that operating condition. See the Typical Applications
section for synchronization examples. The LTM4611 minimum on-time is limited to 90ns. Guardband the on-time
to 130ns. The on-time can be calculated as:
t ON(MIN)=
1 ⎛ V OUT ⎞
•⎜
⎟
FREQ ⎝ VIN ⎠
Output Voltage Tracking and Soft-Start Functions
Output voltage tracking can be programmed externally
using the TRACK/SS pin. The output can be tracked up
and down with another regulator. The master regulator’s
output is divided down with an external resistor divider
that is the same as the slave regulator’s feedback divider
to implement coincident tracking. The LTM4611 uses an
accurate 60.4k resistor internally for the top feedback resistor. Figure 4 shows an example of coincident tracking.
⎛ 60.4k ⎞
VOUT _ SLAVE = ⎜1+
⎟ • V TRACK
RFB2 ⎠
⎝
V TRACK is the track ramp applied to the slave’s track pin.
V TRACK has a control range of 0V to 0.8V, or the internal
reference voltage. When the master’s output is divided
down with the same resistor values used to set the slave’s
output, then the slave will coincident track with the master
until it reaches its final value. The master will continue
to its final value from the slave’s regulation point. Voltage tracking is disabled when V TRACK is more than 0.8V.
RTA in Figure 4 will be equal to the RFB2 for coincident
tracking.
The TRACK/SS pin of the master can be controlled by an
external ramp or the soft-start function of that regulator
can be used to develop that master ramp. The LTM4611 can
be used as a master by setting the ramp rate on its track
pin using a soft-start capacitor. A 1.4µA current source
is used to charge the soft-start capacitor. The following
equation can be used:
⎛ C
⎞
t SOFTSTART = 0.8V • ⎜ SS ⎟
⎝ 1.4µA ⎠
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LTM4611
Applications Information
VIN
1.8V TO 5.5V
CIN1
22µF
10V
CIN2
22µF
10V
CIN3
22µF
10V
R2
10k
SOFT-START
CAPACITOR
CSS
VOUT
TRACK/SS
RUN
CONTINUOUS MODE
INTVCC PGOOD
VIN
COMP
LTM4611
VIN
1.8V TO 5.5V
CIN4
22µF
10V
CIN5
22µF
10V
CIN6
22µF
10V
VOSNS+
MODE_PLLIN
VOSNS–
R1
10k
MASTER RAMP
OR OUTPUT
RTA
121k
RTB
60.4k
VFB
GND
LTM4611
RFB1
69.8k
CP1*
47pF
+
VOUT_LCL
DIFFVOUT
PLLFLTR/fSET
VOSNS+
MODE_PLLIN
VOSNS–
SGND
COUT2*
100µF
6.3V
CFF1*
VOUT
COMP
RUN
COUT1*
470µF
6.3V
INTVCC PGOOD
VIN
TRACK/SS
CONTINUOUS MODE
DIFFVOUT
PLLFLTR/fSET
SGND
+
VOUT_LCL
GND
VFB
VOUT
1.5V
15A
COUT3*
470µF
6.3V
COUT4*
100µF
6.3V
VOUT
1.2V
15A
CFF2*
RFB2
121k
CP2*
47pF
4611 F04
*SEE TABLE 5
Figure 4. Dual Outputs (1.5V and 1.2V) With Tracking
MASTER OUTPUT
OUTPUT
VOLTAGE
SLAVE OUTPUT
TIME
4611 F05
Figure 5. Output Voltage Coincident Tracking
Even for applications that do not require tracking or
sequencing, a minimum recommended value for CSS is
10nF (X7R MLCC, 10% tolerance, nominal; X5R material
may be substituted if the capacitor temperature will not
exceed 85°C), yielding extreme turn-on rise times of 3.8ms
minimum to 9.8ms maximum. Tracking a rail in a manner such that TRACK/SS ramps up at a rate faster than
210V/s may also warrant special attention, as explained
in the following.
Faster turn-on and tracking rates are achievable, if needed:
one need only decrease the default PLLFLTR/fSET RC time
constant. Recall that the PLLFLTR/fSET pin is biased to
1.23V via a high impedance source (>350kΩ); also be aware
that the internal PLL filter contains an initially discharged
10nF capacitor prior to INTVCC being established.
Requiring the output voltage to power up rapidly without
attention to the PLLFLTR/fSET time-constant results in
an initial switching frequency of operation that is initially
lower than expected (~250kHz)—only during the early
stages of start-up—until the PLLFLTR/fSET voltage reaches
steady-state value (1.23V by default).
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LTM4611
Applications Information
Decreasing the PLLFLTR/fSET RC time constant can be
accomplished, for example, by driving the PLLFLTR/fSET
pin with an external, lower impedance resistor divider
network from INTVCC and GND to PLLFLTR/fSET—in the
simplest of implementations, by shorting PLLFLTR/fSET
to INTVCC (thereby programming the switching frequency
to 780kHz, nominal), or by driving the PLLFLTR/fSET pin
from a low impedance voltage source.
When, in addition to needing faster turn-on time, one is also
synchronizing to an external clock signal, one need bear in
mind: the PLL’s sink and source current is recommended
for not more than ±8µA loading, and the PLL will need
to successfully drive any external PLLFLTR/fSET network
impedance to achieve phase lock; and lastly, some phase
shift in clock synchronization will occur as external loading
on PLLFLTR/fSET becomes heavier.
To be clear, using a CSS value of 10nF (or higher) eliminates
the need for any of the above special considerations or
provisions.
Ratiometric tracking can be achieved by a few simple
calculations and the slew rate value applied to the master’s
TRACK/SS pin. As mentioned above, the TRACK/SS pin has
a control range from 0V to 0.8V. The master’s TRACK/SS
pin slew rate is directly equal to the master’s output slew
rate in volts/time. The equation:
MR
• 60.4k = R TB
SR
For example, MR = 1.5V/ms, and SR = 1.2V/ms. Then RTB
= 75k. Solve for RTA to equal to 87k.
Beware that without any kind of soft-start ramp up, it is
important to provide thorough input filter capacitance to
handle input surge currents at start-up, so as to avoid
excessive input line sag and power supply motor boating.
Leaving provision for at least a soft-start capacitor in one’s
application is strongly recommended.
Overcurrent and Overvoltage Protection
The LTM4611 has overcurrent protection (OCP) in a
short circuit. The internal current comparator threshold
folds back during a short to reduce the output current.
An overvoltage condition (OVP) above 7.5% of the regulated output voltage will force the top MOSFET off and
the bottom MOSFET on until the condition is cleared. An
input electronic circuit breaker or fuse can be sized to be
tripped or cleared when the bottom MOSFET is turned on
to protect against the overvoltage. Foldback current limiting
is disabled during soft-start or tracking start-up.
Run Enable
where MR is the master’s output slew rate and SR is the
slave’s output slew rate in volts/time. When coincident
tracking is desired, then MR and SR are equal, thus RTB
is equal to 60.4k. RTA is derived from equation:
R TA =
In ratiometric tracking, a different slew rate maybe desired
for the slave regulator. RTB can be solved for when SR is
slower than MR. Make sure that the slave supply slew rate
is chosen to be fast enough so that the slave output voltage
will reach its final value before the master output.
0.8V
V FB V TRACK
V FB
+
–
60.4k RFB2
R TB
The RUN pin is used to enable the power module or
sequence the power module. The threshold is 1.22V. The
RUN pin must be used as an undervoltage lockout (UVLO)
function by connecting a resistor divider from the input
supply to the RUN pin:
R2 =
where VFB is the feedback voltage reference of the regulator, and V TRACK is 0.8V. Since RTB is equal to the 60.4k
top feedback resistor of the slave regulator in equal slew
rate or coincident tracking, then RTA is equal to RFB2 with
VFB = V TRACK. Therefore RTB = 60.4k, and RTA = 121k in
Figure 4.
R1
VUVLO
–1
1.22V
To achieve the lowest possible UVLO, 1.22V, leave R2
unpopulated. R1 can be 10k, or if R2 is unpopulated, R1
may be replaced with a hardwired connection from VIN
to RUN.
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LTM4611
Applications Information
See the Block Diagram for the example of use. When
RUN is below its threshold, TRACK/SS is pulled low by
internal circuity.
INTVCC Regulator
The LTM4611 has an internally regulated bias supply called
INTVCC. This regulator output has a 4.7µF ceramic capacitor internal. This regulator powers the internal controller
and MOSFET drivers. The gate driver current is ~13mA for
500kHz operation and ~20mA for 780kHz operation; the
regulator loss is ~40mW and ~60mW, respectively.
Stability Compensation
The module has already been internally compensated
for all output voltages. Table 5 is provided for most application requirements. The Linear Technology µModule
Power Design Tool will be provided for other control loop
optimization.
Thermal Considerations and Output Current Derating
The LTM4611 output current may need to be derated if it
is required to operate in a high ambient temperature or
deliver a large amount of continuous power. Some factors
that influence derating are input voltage, output power,
ambient temperature, airflow, and elevation (air density).
The power loss curves in Figures 7 to 9 and current derating curves in Figures 10 to 16 can be used as a guide.
These curves were generated by an LTM4611 mounted to
a 95mm × 76mm 4-layer FR4 printed circuit board (PCB)
1.6mm thick with two ounce copper for the outer layers
and one ounce copper for the two inner layers. Boards of
other sizes and layer count can exhibit different thermal
behavior, so it is ultimately incumbent upon the user to
verify proper operation over the intended system’s line,
load and environmental operating conditions.
The thermal resistance numbers listed in the Pin Configuration section of the data sheet are based on modeling the
µModule package mounted on a test board specified per
JESD51-9 (“Test Boards for Area Array Surface Mount
Package Thermal Measurements”). The thermal coefficients provided are based on JESD 51-12 (“Guidelines
for Reporting and Using Electronic Package Thermal
Information”).
For increased accuracy and fidelity to the actual application, many designers use finite element analysis (FEA)
to predict thermal performance. To that end, the Pin
Configuration section of the data sheet typically gives
four thermal coefficients:
1. θJA: thermal resistance from junction to ambient.
2. θJCbottom: thermal resistance from junction to the bottom of the product case.
3. θJCtop: thermal resistance from junction to top of the
product case.
4. θJB: thermal resistance from junction to the printed
circuit board.
While the meaning of each of these coefficients may seem
to be intuitive, JEDEC has defined each to avoid confusion
and inconsistency. These definitions are given in JESD
51-12, and are quoted or paraphrased in the following:
1. θJA is the natural convection junction-to-ambient air
thermal resistance measured in a one cubic foot sealed
enclosure. This environment is sometimes referred to
as “still air” although natural convection causes the
air to move. This value is determined with the part
mounted to a JESD 51-9 defined test board, which does
not necessarily reflect an actual application or viable
operating condition.
2. θJCbottom is the junction-to-board thermal resistance
with all of the component power dissipation flowing through the bottom of the package. In the typical
µModule, the bulk of the heat flows out the bottom of
the package, but there is always heat flow out into the
ambient environment. As a result, this thermal resistance
value may be useful for comparing packages but the test
conditions don’t generally match the user’s application.
3. θJCtop is determined with nearly all of the component
power dissipation flowing through the top of the package. As the electrical connections of the typical µModule
are on the bottom of the package, it is rare for an application to operate such that most of the heat flows
from the junction to the top of the part. As in the case
of θJCbottom, this value may be useful for comparing
packages but the test conditions don’t generally match
the user’s application.
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LTM4611
Applications Information
4. θJB is the junction-to-board thermal resistance where
almost all of the heat flows through the bottom of the
µModule and into the board, and is really the sum of
the θJCbottom and the thermal resistance of the bottom
of the part through the solder joints and through a portion of the board. The board temperature is measured a
specified distance from the package, using a two sided,
two layer board. This board is described in JESD 51-9.
Given these definitions, it should now be apparent that
none of these thermal coefficients reflects an actual
physical operating condition of a µModule. Thus, none
of them can be individually used to accurately predict the
thermal performance of the product. Likewise, it would
be inappropriate to attempt to use any one coefficient to
correlate to the junction temperature versus load graphs
given in the product’s data sheet. The only appropriate
way to use the coefficients is to run a detailed thermal
analysis, such as FEA, which considers all of the thermal
resistances simultaneously.
A graphical representation of these thermal resistances
is given in Figure 6.
The blue resistances are contained within the µModule,
and the green are outside.
The die temperature of the LTM4611 must be lower than
the maximum rating of 125°C, so care should be taken in
the layout of the circuit to ensure good heat sinking of the
LTM4611. The bulk of the heat flow out of the LTM4611 is
through the bottom of the module and the LGA pads into
the printed circuit board. Consequently, a poor printed
circuit board design can cause excessive heating, resulting in impaired performance or reliability. Please refer to
the PCB Layout section for printed circuit board design
suggestions
The 1.2V, 2.5V and 3.3V power loss curves in Figures 7
and 8 can be used in coordination with the load current
derating curves in Figures 9 to 16 for calculating an
approximate θJA thermal resistance for the LTM4611
with various heat sinking and air flow conditions, as
evaluated on the aforementioned 4-layer FR4 PCB. The
power loss curves are taken at room temperature, and
are increased with multiplicative factors with ambient
temperature. These approximate factors are: 1 up to 50°C;
1.1 for 60°C; 1.15 for 70°C; 1.2 for 80°C; 1.25 for
90°C; 1.3 for 100°C; 1.35 for 110°C and 1.4 for 120°C.
The derating curves are plotted with the output current
starting at 15A and the ambient temperature at 55°C. The
output voltages are 1.2V, 2.5V and 3.3V. These are chosen
to include the lower and higher output voltage ranges for
correlating the thermal resistance. Thermal models are
derived from several temperature measurements in a
controlled temperature chamber along with thermal modeling analysis. The junction temperatures are monitored
while ambient temperature is increased with and without
air flow, and with and without a heat sink attached with
thermally conductive adhesive tape. The BGA heat sinks
evaluated in Table 5 yield very comparable performance
in laminar airflow despite being visibly different in construction and form factor. The power loss increase with
ambient temperature change is factored into the derating
JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)
JUNCTION-TO-CASE (TOP)
RESISTANCE
JUNCTION
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION-TO-CASE
CASE (BOTTOM)-TO-BOARD
(BOTTOM) RESISTANCE
RESISTANCE
At
BOARD-TO-AMBIENT
RESISTANCE
µMODULE
4611 F06
Figure 6
4611fb
18
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LTM4611
Applications Information
curves. The junctions are maintained at 115°C maximum
while lowering output current or power while increasing
ambient temperature. The decreased output current will
decrease the internal module loss as ambient temperature
is increased. The monitored junction temperature of 115°C
minus the ambient operating temperature specifies how
much module temperature rise can be allowed. As an
example in Figure 11, the load current is derated to ~12A
at ~75°C with no air or heat sink and the power loss for
the 3.3V to 1.2V at 12A output is a 2.82W loss. The 2.82W
loss is calculated with the ~2.4W room temperature loss
from the 3.3V to 1.2V power loss curve at 12A (Figure 7),
and the 1.175 multiplying factor at 75°C ambient. If the
75°C ambient temperature is subtracted from the 115°C
4.0
2.5
3.0
2.0
1.5
2.5
2.0
1.5
1.0
1.0
0.5
0.5
0
3
0
5VIN TO 2.5VOUT
5VIN TO 3.3VOUT
3.3VIN TO 2.5VOUT
3.5
POWER LOSS (W)
3.0
POWER LOSS (W)
4.0
5VIN
3.3VIN
2.5VIN
1.8VIN
1.5VIN
3.5
junction temperature, then the difference of 40°C divided
by 2.82W yields a thermal resistance, θJA, of 14.2°C/W—in
good agreement with Table 2. Tables 2, 3 and 4 provide
equivalent thermal resistances for 1.2V, 2.5V and 3.3V
outputs with and without air flow and heat sinking. The
derived thermal resistances in Tables 2, 3 and 4 for the
various conditions can be multiplied by the calculated
power loss as a function of ambient temperature to derive
temperature rise above ambient, thus maximum junction
temperature. Room temperature power loss can be derived
from the efficiency curves in the Typical Performance
Characteristics section and adjusted with the above ambient temperature multiplicative factors.
6
12
9
OUTPUT CURRENT (A)
0
15
3
0
6
12
9
OUTPUT CURRENT (A)
15
4611 F07
4611 F08
Figure 8. 2.5VOUT and 3.3VOUT Power Loss
16
16
14
14
MAXIMUM LOAD CURRENT (A)
MAXIMUM LOAD CURRENT (A)
Figure 7. 1.2VOUT Power Loss
12
10
8
6
4
400LFM
200LFM
0LFM
2
0
55
65
10
8
6
4
400LFM
200LFM
0LFM
2
95 105 115
85
AMBIENT TEMPERATURE (°C)
75
12
125
0
55
4611 F09
Figure 9. 5VIN to 1.2VOUT No Heat Sink
65
75
95 105 115
85
AMBIENT TEMPERATURE (°C)
125
4611 F10
Figure 10. 5VIN to 1.2VOUT with Heat Sink
4611fb
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19
LTM4611
16
16
14
14
MAXIMUM LOAD CURRENT (A)
MAXIMUM LOAD CURRENT (A)
Applications Information
12
10
8
6
4
400LFM
200LFM
0LFM
2
0
55
65
12
10
8
6
4
400LFM
200LFM
0LFM
2
95 105 115
85
AMBIENT TEMPERATURE (°C)
75
0
125
55
65
75
95 105 115
85
AMBIENT TEMPERATURE (°C)
4611 F11
4611 F12
Figure 12. 3.3VIN to 1.2VOUT with Heat Sink
16
16
14
14
MAXIMUM LOAD CURRENT (A)
MAXIMUM LOAD CURRENT (A)
Figure 11. 3.3VIN to 1.2VOUT No Heat Sink
12
10
8
6
4
400LFM
200LFM
0LFM
2
0
55
65
12
10
8
6
4
400LFM
200LFM
0LFM
2
95 105 115
85
AMBIENT TEMPERATURE (°C)
75
0
125
55
65
75
95 105 115
85
AMBIENT TEMPERATURE (°C)
4611 F13
Figure 14. 3.3VIN to 2.5VOUT with Heat Sink
16
16
14
14
12
10
8
6
4
400LFM
200LFM
0LFM
2
0
55
65
12
10
8
6
4
400LFM
200LFM
0LFM
2
95 105 115
85
AMBIENT TEMPERATURE (°C)
75
125
0
55
4611 F15
Figure 15. 5VIN to 3.3VOUT No Heat Sink
125
4611 F14
MAXIMUM LOAD CURRENT (A)
MAXIMUM LOAD CURRENT (A)
Figure 13. 3.3VIN to 2.5VOUT No Heat Sink
125
65
75
95 105 115
85
AMBIENT TEMPERATURE (°C)
125
4611 F16
Figure 16. 5VIN to 3.3VOUT with Heat Sink
4611fb
20
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LTM4611
Applications Information
Table 2. 1.2V Output
DERATING
CURVE
VIN
POWER LOSS
CURVE
AIR FLOW
(LFM)
HEAT SINK
θJA (°C/W)
Figures 9, 11
5V, 3.3V
Figure 7
0
None
14
Figures 9, 11
5V, 3.3V
Figure 7
200
None
11.5
Figures 9, 11
5V, 3.3V
Figure 7
400
None
10.6
Figures 10, 12
5V, 3.3V
Figure 7
0
BGA Heat Sink
11.5
Figures 10, 12
5V, 3.3V
Figure 7
200
BGA Heat Sink
8.4
Figures 10, 12
5V, 3.3V
Figure 7
400
BGA Heat Sink
7.5
AIR FLOW
(LFM)
HEAT SINK
θJA (°C/W)
Table 3. 2.5V Output
DERATING
CURVE
VIN
POWER LOSS
CURVE
Figures 13
3.3V
Figure 8
0
None
15.5
Figures 13
3.3V
Figure 8
200
None
12.7
Figures 13
3.3V
Figure 8
400
None
12.1
Figures 14
3.3V
Figure 8
0
BGA Heat Sink
12.6
Figures 14
3.3V
Figure 8
200
BGA Heat Sink
10.6
Figures 14
3.3V
Figure 8
400
BGA Heat Sink
8.9
DERATING
CURVE
VIN
POWER LOSS
CURVE
AIR FLOW
(LFM)
HEAT SINK
θJA (°C/W)
Figures 15
5V
Figure 8
0
None
14
Figures 15
5V
Figure 8
200
None
11.5
Figures 15
5V
Figure 8
400
None
10.2
Figures 16
5V
Figure 8
0
BGA Heat Sink
12
Figures 16
5V
Figure 8
200
BGA Heat Sink
10.1
Figures 16
5V
Figure 8
400
BGA Heat Sink
9.3
Table 4. 3.3V Output
4611fb
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21
LTM4611
Applications Information
Table 5. Output Voltage Response Versus Component Matrix, 0A to 7.5A Load Step
TYPICAL MEASURED VALUES
COUT1 VENDORS
PART NUMBER
COUT2 VENDORS
PART NUMBER
AVX
12106D107MAT2A (100µF, 6.3V, 1210 Case Size)
Sanyo POSCAP
6TPF330M9L (330µF, 6.3V, 9mΩ ESR, D3L Case Size)
Taiyo Yuden
JMK325BJ107MM-T (100µF, 6.3V, 1210 Case Size)
Sanyo POSCAP
2R5TPE470M9 (470µF, 2.5V, 9mΩ ESR, D2E Case Size)
TDK
C3225X5R0J107MT (100µF, 6.3V, 1210 Case Size)
AVX
1206D226MAT (22µF, 6.3V, 1206 Case Size)
Taiyo Yuden
JMK316BJ226ML-T (22µF, 6.3V, 1206 Case Size)
TDK
C3216X5R0J226MT (22µF, 6.3V, 1206 Case Size)
TRANSIENT
LOAD
DROOP,
TRANSIENT
STEP
USING
0A TO 7.5A PEAK-TO-PEAK,
SLEW
DIFF
LOAD STEP 0A TO 7.5A TO 0A RECOVERY RATE RSET
VOUT VIN
CIN*
CIN*
COUT2
COUT1
AMP FIGURE
(mV)
(mVP-P)
(V) (V) (CERAMIC) (BULK) (CERAMIC) (BULK) CFF
TIME (µs) (A/µs) (kΩ)
CP
0.9 1.5 2 × 47µF 470µF 5 × 100µF None 220pF None
Y
21
65
118
15
7.5
481
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
1
1
1
1
1
1
1
1
1.5
1.8
1.8
1.8
2.5
2.5
3.3
3.3
5
5
1.5
1.5
1.8
1.8
1.8
2.5
2.5
3.3
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
1
1
1
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
3.3
5
5
1.5
1.5
1.8
1.8
1.8
2.5
2.5
3.3
3.3
5
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
470µF
220µF
220µF
220µF
150µF
150µF
150µF
150µF
150µF
150µF
680µF
680µF
330µF
330µF
330µF
150µF
150µF
3 × 22µF
4 × 100µF
3 × 22µF
4 × 22µF
5 × 100µF
7 × 22µF
4 × 100µF
7 × 22µF
4 × 100µF
6 × 22µF
5 × 100µF
3 × 22µF
4 × 100µF
3 × 22µF
4 × 22µF
4 × 100µF
7 × 22µF
470µF
None
470µF
330µF
None
330µF
None
330µF
None
330µF
None
470µF
None
470µF
330µF
None
330µF
22pF
220pF
47pF
22pF
33pF
None
47pF
10pF
47pF
10pF
220pF
33pF
220pF
33pF
22pF
47pF
10pF
None
None
None
None
10pF
22pF
None
10pF
None
10pF
None
None
None
None
None
None
10pF
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
63
65
60
64
54
65
50
55
47
61
70
62
68
60
66
61
63
122
119
113
119
108
123
104
109
102
116
128
121
123
115
123
115
115
25
20
25
30
20
20
25
20
20
20
20
25
20
30
30
25
25
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
481
481
481
481
481
481
481
481
481
481
243
243
243
243
243
243
243
150µF
150µF
150µF
150µF
1000µF
1000µF
470µF
470µF
470µF
220µF
220µF
150µF
150µF
150µF
4 × 100µF
7 × 22µF
4 × 100µF
6 × 22µF
6 × 100µF
2 × 22µF
4 × 100µF
3 × 22µF
4 × 22µF
4 × 100µF
5 × 22µF
4 x 100µF
None
330µF
None
330µF
None
470µF
None
470µF
330µF
None
330µF
None
330µF
None
47pF
10pF
47pF
10pF
220pF
47pF
220pF
22pF
22pF
100pF
10pF
33pF
10pF
47pF
None
10pF
None
10pF
None
None
None
None
None
None
10pF
10pF
10pF
None
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
21
21
21
21
21
21
21
21
21
21
21
21
21
21
52
57
53
62
82
70
75
64
72
58
65
60
63
47
106
111
108
119
145
133
136
126
137
114
122
116
117
105
30
20
25
25
20
30
25
30
30
30
25
30
20
30
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
243
243
243
243
121
121
121
121
121
121
121
121
121
121
7 × 22µF
4 × 100µF
4611fb
22
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LTM4611
Applications Information
VOUT
(V)
1.2
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.8
1.8
1.8
1.8
1.8
1.8
2.5
2.5
2.5
2.5
2.5
2.5
3.3
3.3
3.3
3.3
5
5
VIN
CIN*
CIN*
(V) (CERAMIC) (BULK)
5 2 × 47µF 150µF
1.8 2 × 47µF 1000µF
1.8 2 × 47µF 1000µF
2.5 2 × 47µF 220µF
2.5 2 × 47µF 220µF
3.3 2 × 47µF 150µF
3.3 2 × 47µF 150µF
5 2 × 47µF 150µF
5 2 × 47µF 150µF
2.5 2 × 47µF 330µF
2.5 2 × 47µF 330µF
3.3 2 × 47µF 150µF
3.3 2 × 47µF 150µF
5 2 × 47µF 150µF
5 2 × 47µF 150µF
3.3 2 × 47µF 330µF
3.3 2 × 47µF 330µF
3.3 2 × 47µF 330µF
5 2 × 47µF 150µF
5 2 × 47µF 150µF
5 2 × 47µF 150µF
5 2 × 47µF 150µF
5 2 × 47µF 150µF
5 2 × 47µF 150µF
5 2 × 47µF 150µF
5.5 2 × 47µF 680µF
5.5 2 × 47µF 680µF
COUT2
(CERAMIC)
6 × 22µF
6 × 100µF
2 × 22µF
4 × 100µF
5 × 22µF
4 × 100µF
4 × 22µF
4 × 100µF
6 × 22µF
4 × 100µF
5 × 22µF
4 × 100µF
4 × 22µF
4 × 100µF
6 × 22µF
3 × 100µF
4 × 100µF
3 × 22µF
COUT1
(BULK)
330µF
None
470µF
None
330µF
None
330µF
None
330µF
None
330µF
None
330µF
None
330µF
None
None
330µF
CFF
10pF
220pF
47pF
220pF
22pF
33pF
22pF
33pF
None
220pF
22pF
47pF
22pF
33pF
None
100pF
100pF
47pF
TRANSIENT
LOAD
DROOP,
TRANSIENT
STEP
USING
0A TO 7.5A PEAK-TO-PEAK,
SLEW
DIFF
LOAD STEP 0A TO 7.5A TO 0A RECOVERY RATE RSET
AMP FIGURE
(mV)
(mVP-P)
CP
TIME (µs) (A/µs) (kΩ)
10pF
Y
21
64
123
25
7.5
121
None
Y
21
83
147
25
7.5
69
None
Y
21
71
135
40
7.5
69
None
Y
21
64
122
40
7.5
69
10pF
Y
21
68
133
30
7.5
69
10pF
Y
21
66
123
30
7.5
69
None
Y
21
67
124
30
7.5
69
10pF
Y
21
59
122
30
7.5
69
10pF
Y
21
67
131
30
7.5
69
None
Y
21
73
137
45
7.5 48.1
None
Y
21
76
145
35
7.5 48.1
10pF
Y
21
57
118
40
7.5 48.1
None
Y
21
69
137
30
7.5 48.1
10pF
Y
21
64
127
40
7.5 48.1
10pF
Y
21
69
133
30
7.5 48.1
None
Y
21
71
143
45
7.5 28.4
None
Y
21
66
123
40
7.5 28.4
None
Y
21
67
128
50
7.5 28.4
3 × 100µF
4 × 100µF
5 × 22µF
2 × 100µF
3 × 100µF
4 × 100µF
5 × 22µF
1 × 100µF
7 × 22µF
None
None
330µF
None
None
None
330µF
None
None
100pF
100pF
22pF
22pF
47pF
100pF
22pF
10pF
None
None
None
None
None
None
None
None
None
None
Y
Y
Y
Y
Y
Y
Y
N
N
21
21
21
21
21
21
21
20
20
60
54
81
137
67
56
95
264
218
134
115
160
274
143
119
193
511
431
HEAT SINK MANUFACTURER
PART NUMBER
WEBSITE
Wakefield Engineering
LTN20069
www.wakefield.com
AAVID Thermalloy
375424B00034G
www.aavidthermalloy.com
THERMALLY CONDUCTIVE ADHESIVE
TAPE MANUFACTURER
PART NUMBER
WEBSITE
Chromerics
T411
www.chromerics.com
*The quantity and quality of bulk input bypass capacitance
needed, particularly for low dropout scenarios (VIN – VOUT
< 600mV) is mainly dependent on the output impedance
and dynamic response of the power source feeding the
LTM4611(s). Consider, in the extreme: for a heavy load
step, the full transient on LTM4611’s output is directly
45
50
40
40
50
60
45
30
40
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
28.4
28.4
28.4
19.3
19.3
19.3
19.3
11.5
11.5
referred to its input, and the LTM4611 can only deliver
to its output whatever the source supply and local input
caps can provide. Sluggish source supplies will call for
more bulk capacitance placed locally to the LTM4611’s
input, to assist the source supply in riding through severe
transient load steps.
4611fb
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23
LTM4611
Applications Information
Safety Considerations
The LTM4611 modules do not provide galvanic isolation
from VIN to VOUT. There is no internal fuse. If required,
a slow blow fuse with a rating twice the maximum input
current needs to be provided to protect each unit from
catastrophic failure. The device does support overvoltage
protection and overcurrent protection.
Layout Checklist/Example
The high integration of LTM4611 makes the PCB board
layout very simple and easy. However, to optimize its
electrical and thermal performance, some layout considerations are still necessary.
• Use large PCB copper areas for high current paths,
including VIN, GND and VOUT. It helps to minimize the
PCB conduction loss and thermal stress.
• Place high frequency ceramic input and output capacitors next to the VIN, GND and VOUT pins to minimize
high frequency noise.
• Place a dedicated power ground layer underneath the
unit.
• To minimize the via conduction loss and reduce module
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
• Do not put vias directly on the pad, unless they are
capped or plated over.
• Use a separated SGND ground copper area for components connected to signal pins. Connect the SGND
to GND underneath the unit.
• For parallel modules, tie the respective COMP, VFB,
VOUT_LCL, TRACK/SS and RUN pins together. Use an
internal layer to closely connect these pins together.
Figure 17 gives a good example of the recommended
layout. Figures 18 and 19 show schematics of the
LTM4611 devices operating in parallel.
• To facilitate stuffing verification, test and debug activities, consider routing control signals of the LTM4611
with short traces to localized test points, test pads or
test vias–as PCB layout space permits. Both in-house
and contract manufacturers enjoy gaining electrical
access to all non low impedance (>10Ω) pins of an
IC or µModule device to improve in-circuit test (ICT)
coverage.
VIN
CIN
CIN
CONTROL
CONTROL
GND
SIGNAL
GROUND
CONTROL
COUT
COUT
VOUT
VOUT
4611 F17
Figure 17. Recommended PCB Layouts
4611fb
24
For more information www.linear.com/LTM4611
LTM4611
Typical Applications
VIN
1.5V TO 5.5V
R1
10k
CIN1
22µF
10V
CIN2
22µF
10V C
SS
0.1µF
INTVCC
VIN
INTVCC PGOOD
VOUT
COMP
TRACK/SS
VOUT_LCL
RUN
DIFFVOUT
LTM4611
PLLFLTR/fSET
SGND
INTVCC
C1
1µF
V+
OUT1
OUT2
VOSNS+
COUT2*
100µF
6.3V
CFF1*
VFB
GND
COUT1*
470µF
6.3V
RFB
30.1k
CP1*
R2
100k
SET
LTC6902
MOD
DIV
PH
+
VOSNS–
MODE_PLLIN
4-PHASE CLOCK
VOUT
1.2V
60A
GND
CIN3
22µF
10V
CIN4
22µF
10V
OUT4
VIN
INTVCC PGOOD
VOUT
COMP
OUT3
TRACK/SS
VOUT_LCL
RUN
DIFFVOUT
LTM4611
PLLFLTR/fSET
SGND
CIN5
22µF
10V
CIN6
22µF
10V
VIN
VFB
GND
VOUT_LCL
RUN
DIFFVOUT
CFF3*
VFB
GND
COUT6*
100µF
6.3V
COUT7*
470µF
6.3V
COUT8*
100µF
6.3V
INTVCC
CP3*
INTVCC PGOOD
VOUT
COMP
TRACK/SS
VOUT_LCL
RUN
DIFFVOUT
LTM4611
PLLFLTR/fSET
CFF4*
+
VOSNS+
VOSNS–
MODE_PLLIN
SGND
+
VOSNS+
VOSNS–
MODE_PLLIN
VIN
COUT5*
470µF
6.3V
INTVCC
VOUT
TRACK/SS
CIN8
22µF
10V
COUT4*
100µF
6.3V
INTVCC PGOOD
LTM4611
PLLFLTR/fSET
CIN7
22µF
10V
COUT3*
470µF
6.3V
CP2*
COMP
SGND
+
VOSNS+
VOSNS–
MODE_PLLIN
CFF2*
VFB
GND
INTVCC
CP4*
4611 F18
*FOR BEST NOISE IMMUNITY, DISTRIBUTE CAPACITORS WITH
VFB CONNECTIONS AMONGST ALL PARALLELED LTM4611s
Figure 18. 1.2V, 60A, Current Sharing with 4-Phase Operation
4611fb
For more information www.linear.com/LTM4611
25
LTM4611
Typical Applications
VIN
1.5V TO 5.5V
CIN2
22µF
10V
CIN1
22µF
10V
INTVCC
CIN3
22µF
10V
VOUT
COMP
R1
10k
TRACK/SS
RUN
INTVCC
C1
1µF
R2
200k
CLOCK SYNC 0 PHASE
OUT1
V+
LTC6908-1
OUT2
GND
INTVCC PGOOD
VIN
CSS
0.1µF
LTM4611
VOSNS+
MODE_PLLIN
VOSNS–
GND
CIN5
22µF
10V
CIN4
22µF
10V
CIN6
22µF
10V
VFB
RFB
121k
VOUT
RUN
CLOCK SYNC 180 PHASE
CP1*
INTVCC PGOOD
VIN
COMP
TRACK/SS
LTM4611
VOUT_LCL
VOSNS+
MODE_PLLIN
VOSNS–
GND
CFF2*
+
COUT3*
470µF
6.3V
DIFFVOUT
PLLFLTR/fSET
SGND
COUT2*
100µF
6.3V
CFF1*
MOD
SET
COUT1*
470µF
6.3V
DIFFVOUT
PLLFLTR/fSET
SGND
+
VOUT_LCL
VOUT
1V
30A
COUT4*
100µF
6.3V
INTVCC
VFB
CP2*
4611 F19
*FOR BEST NOISE IMMUNITY, DISTRIBUTE CAPACITORS WITH
VFB CONNECTIONS AMONGST ALL PARALLELED LTM4611s
Figure 19. 1V at 30A LTM4611 Two Parallel Outputs with 2-Phase Operation
5V
CIN1
22µF
10V
CIN2
22µF
10V
CIN3
22µF
10V
CSS
0.1µF
R1
10k
INTVCC PGOOD
VIN
VOUT
COMP
VOUT_LCL
TRACK/SS
RUN
CONTINUOUS
MODE
LTM4611
DIFFVOUT
PLLFLTR/fSET
VOSNS+
MODE_PLLIN
VOSNS–
SGND
GND
CFF*
+
VFB
COUT1*
220µF
6.3V
COUT2*
47µF
6.3V
3.3V
15A
INTVCC
RFB
19.1k
CP*
4611 F20
*SEE TABLE 5
Figure 20. 3.3V at 15A Design, Example of Not Using Differential Remote Sense
4611fb
26
For more information www.linear.com/LTM4611
LTM4611
Package Photograph
Package Description
Pin Assignment Table
(Arranged by Pin Number)
PIN NAME
A1 VIN
A2 VIN
A3 VIN
A4 VIN
A5 VIN
A6 VIN
A7 INTVCC
A8 MODE_PLLIN
A9 TRACK/SS
A10 RUN
A11 COMP
A12 MTP1
PIN NAME
B1 VIN
B2 VIN
B3 VIN
B4 VIN
B5 VIN
B6 VIN
B7 GND
B8 B9 GND
B10 B11 MTP2
B12 PLLFLTR/fSET
PIN NAME
C1 VIN
C2 VIN
C3 VIN
C4 VIN
C5 VIN
C6 VIN
C7 GND
C8 C9 GND
C10 MTP3
C11 MTP4
C12 MTP5
PIN NAME
D1 GND
D2 GND
D3 GND
D4 GND
D5 GND
D6 GND
D7 D8 GND
D9 INTVCC
D10 MTP6
D11 MTP7
D12 MTP8
PIN NAME
E1 GND
E2 GND
E3 GND
E4 GND
E5 GND
E6 GND
E7 GND
E8 E9 GND
E10 E11 E12 MTP9
PIN NAME
F1 GND
F2 GND
F3 GND
F4 GND
F5 GND
F6 GND
F7 GND
F8 GND
F9 GND
F10 F11 PGOOD
F12 V FB
PIN NAME
G1 GND
G2 GND
G3 GND
G4 GND
G5 GND
G6 GND
G7 GND
G8 GND
G9 GND
G10 G11 SGND
G12 PGOOD
PIN NAME
H1 GND
H2 GND
H3 GND
H4 GND
H5 GND
H6 GND
H7 GND
H8 GND
H9 GND
H10 H11 SGND
H12 SGND
PIN NAME
J1 VOUT
J2 VOUT
J3 VOUT
J4 VOUT
J5 VOUT
J6 VOUT
J7 VOUT
J8 VOUT
J9 VOUT
J10 VOUT
J11 J12 VOSNS+
PIN NAME
K1 VOUT
K2 VOUT
K3 VOUT
K4 VOUT
K5 VOUT
K6 VOUT
K7 VOUT
K8 VOUT
K9 VOUT
K10 VOUT
K11 VOUT
K12 DIFFVOUT
PIN NAME
L1 VOUT
L2 VOUT
L3 VOUT
L4 VOUT
L5 VOUT
L6 VOUT
L7 VOUT
L8 VOUT
L9 VOUT
L10 VOUT
L11 VOUT
L12 VOUT_LCL
PIN NAME
M1 VOUT
M2 VOUT
M3 VOUT
M4 VOUT
M5 VOUT
M6 VOUT
M7 VOUT
M8 VOUT
M9 VOUT
M10 VOUT
M11 VOUT
M12 VOSNS –
4611fb
For more information www.linear.com/LTM4611
27
For more information www.linear.com/LTM4611
6.9850
5.7150
4.4450
3.1750
1.9050
0.6350
0.0000
0.6350
1.9050
3.1750
4.4450
5.7150
6.9850
4
PACKAGE TOP VIEW
3.1750
0.630
SUGGESTED PCB LAYOUT
TOP VIEW
1.9050
PAD 1
CORNER
15
BSC
0.6350
0.0000
0.6350
15
BSC
Y
0.630
X
DETAIL B
eee S X Y
0.27 – 0.37
SUBSTRATE
DETAIL B
DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
LAND DESIGNATION PER JESD MO-222, SPP-010
7
3
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
SYMBOL TOLERANCE
aaa
0.15
bbb
0.10
eee
0.05
!
6. THE TOTAL NUMBER OF PADS: 133
5. PRIMARY DATUM -Z- IS SEATING PLANE
4
3
2. ALL DIMENSIONS ARE IN MILLIMETERS
1.27
BSC
13.97
BSC
M
L
TRAY PIN 1
BEVEL
COMPONENT
PIN “A1”
PADS
SEE NOTES
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
DETAIL A
0.630 ±0.025 SQ. 133x
aaa Z
3.95 – 4.05
MOLD
CAP
4.22 – 4.42
0.12 – 0.28
(Reference LTC DWG # 05-08-1777 Rev A)
bbb Z
aaa Z
1.9050
Z
28
3.1750
LGA Package
133-Lead (15mm × 15mm × 4.32mm)
K
G
F
E
LTMXXXXXX
µModule
PACKAGE BOTTOM VIEW
H
D
C
B
A
LGA 133 1212 REV A
PACKAGE IN TRAY LOADING ORIENTATION
J
13.97
BSC
DETAIL A
1
2
3
4
5
6
7
8
9
10
11
12
C(0.30)
PAD 1
7
SEE NOTES
LTM4611
Package Description
4611fb
6.9850
5.7150
4.4450
4.4450
5.7150
6.9850
LTM4611
Revision History
REV
DATE
DESCRIPTION
A
6/11
Added Video TechClip Link
PAGE NUMBER
1
B
5/13
Added new video icon.
1
4611fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representaFor more
www.linear.com/LTM4611
tion that the interconnection
of itsinformation
circuits as described
herein will not infringe on existing patent rights.
29
LTM4611
Typical Application
VIN
1.5V TO 5.5V*
CIN1
22µF
10V
CIN2
22µF
10V
INTVCC
CIN3
22µF
10V
CSS
0.1µF
R1
10k
VOUT
COMP
TRACK/SS
RUN
CONTINUOUS MODE
INTVCC PGOOD
VIN
LTM4611
VOUT_LCL
DIFFVOUT
PLLFLTR/fSET
VOSNS+
MODE_PLLIN
VOSNS–
SGND
GND
CFF*
VFB
RFB
240k
+
COUT1*
220µF
6.3V
VOUT
1V
COUT2* 15A
22µF
6.3V
×2
CP*
4611 F21
*SEE TABLE 5
Figure 21. 1.5V to 5.5VIN, 1V at 15A Design
Related Parts
PART NUMBER
DESCRIPTION
COMMENTS
LTM4600
10A DC/DC µModule
Basic 10A DC/DC µModule
LTM4601A
12A DC/DC µModule with PLL, Output Tracking/
Margining and Remote Sensing
Synchronizable, PolyPhase Operation to 48A, Pin Compatible with the
LTM4611 and LTM4617
LTM4602
6A DC/DC µModule
Pin Compatible with the LTM4600
LTM4603
6A DC/DC µModule with PLL and Output Tracking/
Margining and Remote Sensing
Synchronizable, PolyPhase Operation, LTM4603-1 Version has no
Remote Sensing, Pin Compatible with the LTM4601
LTM4604A
4A Low Voltage DC/DC µModule
2.375V ≤ VIN ≤ 5.5V; 0.8V ≤ VOUT ≤ 5V,
9mm × 15mm × 2.3mm (Ultrathin) LGA Package
LTM4605
Buck-Boost DC/DC µModule Family
All Pin Compatible; Up to 5A; Up to 36VIN, 34VOUT 15mm × 15mm × 2.8mm
LTM4606
Ultralow Noise 6A DC/DC µModule
4.5V ≤ VIN ≤ 28V, 0.6V ≤ VOUT ≤ 5V, 15mm × 15mm × 2.8mm Package
LTM4607
Buck-Boost DC/DC µModule Family
All Pin Compatible; Up to 5A; Up to 36VIN, 34VOUT 15mm × 15mm × 2.8mm
LTM4608A
8A Low Voltage DC/DC µModule
2.7V ≤ VIN ≤ 5.5V; 0.6V ≤ VOUT ≤ 5V; 9mm × 15mm × 2.8mm LGA Package
LTM4609
Buck-Boost DC/DC µModule Family
All Pin Compatible; Up to 5A; Up to 36VIN, 34VOUT 15mm × 15mm × 2.8mm
LTM4612
Ultralow Noise High VOUT DC/DC µModule
5A, 5V ≤ VIN ≤ 36V, 3.3V ≤ VOUT ≤ 15V, 15mm × 15mm × 2.8mm Package
LTM8023
36V, 2A DC/DC µModule
3.6V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 10V, 9mm × 11.25mm × 2.8mm Package
LTM8032
Ultralow Noise 36V, 2A DC/DC µModule
EN55022 Class B Compliant; 0.8V ≤ VOUT ≤ 10V; 3.6V ≤ VIN ≤ 36V;
9mm × 15mm × 2.8mm
4611fb
30 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTM4611
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTM4611
LT 0513 REV B • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2010
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