LTM4615
Triple Output, Low Voltage
DC/DC µModule Regulator
Features
Description
Dual 4A Output Power Supply with 1.5A VLDO™
n Short-Circuit and Overtemperature Protection
n Power Good Indicators
Switching Regulators Section—Current Mode Control
n Input Voltage Range: 2.375V to 5.5V
n 4A DC Typical, 5A Peak Output Current Each
n 0.8V Up to 5V Output Each, Parallelable
n ±2% Total DC Output Error
n Output Voltage Tracking
n Up to 95% Efficiency
n Programmable Soft-Start
VLDO Section
n VLDO, 1.14V to 3.5V Input Range
n VLDO, 0.4V to 2.6V, 1.5A Output
n VLDO, 40dB Supply Rejection at f
SW
n ±1% Total DC Output Error
n Small and Very Low Profile Package:
15mm × 15mm × 2.82mm
The LTM®4615 is a complete 4A dual output switching
mode DC/DC power supply plus an additional 1.5A VLDO
(very low dropout) linear regulator. Included in the package are the switching controllers, power FETs, inductors,
a 1.5A regulator and all support components. The dual 4A
DC/DC converters operate over an input voltage range of
2.375V to 5.5V, and the VLDO operates from a 1.14V to
3.5V input. The LTM4615 supports output voltages ranging from 0.8V to 5V for the DC/DC converters, and 0.4V
to 2.6V for the VLDO. The three regulator output voltages
are set by a single resistor for each output. Only bulk input
and output capacitors are needed to complete the design.
n
The low profile package (2.82mm) enables utilization of
unused space on the bottom of PC boards for high density
point of load regulation. High switching frequency and a
current mode architecture enables a very fast transient
response to line and load changes without sacrificing
stability. The device supports output voltage tracking for
supply rail sequencing.
Applications
n
n
n
n
Additional features include overvoltage protection, overcurrent protection, thermal shutdown and programmable
soft-start. The power module is offered in a space saving
and thermally enhanced 15mm × 15mm × 2.82mm LGA
package. The LTM4615 is RoHS compliant with Pb-free
finish.
Telecom and Networking Equipment
Industrial Power Systems
Low Noise Applications
FPGA, SERDES Power
L, LT, LTC, LTM, Linear Technology, the Linear logo, µModule and PolyPhase are registered
trademarks and VLDO and LTpowerCAD are trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Protected by U.S. Patents
including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131, 6724174.
Typical Application
Efficiency vs Output Current
1.2V at 4A, 1.5V at 4A and 1V at 1A DC/DC µModule® Regulator
91
22µF
6.3V
10k
100µF
6.3V
1.2V
10µF
VIN
VIN1
PGOOD1
VOUT1
FB1
TRACK1
RUN/SS1
LDO_IN
EN3
VIN2
PGOOD2
VOUT2
LTM4615
FB2
TRACK2
RUN/SS2
LDO_OUT
FB3
PGOOD3
GND1
GND3
GND2
PGOOD2
10µF
6.3V
10k
VIN
87
VOUT2
1.5V
4A
PGOOD3
22µF
6.3V
5.76k
VOUT3
1V AT 1A
10µF
6.3V
100µF
6.3V
VOUT2
1.5V
85
83
VOUT3
1V
(VIN = 1.2V)
81
VOUT1
1.2V
79
77
3.32k
75
10k
VOUT3
EFFICIENCY (%)
VOUT1
1.2V
4A
PGOOD1
10µF
6.3V
10k
VIN = 3.3V
89
VIN 3V TO 5.5V
4615 TA01a
0
2
1
3
OUTPUT CURRENT (A)
4
4615 TA01b
4615fb
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1
LTM4615
Absolute Maximum Ratings
(Note 1)
Switching Regulators
VIN1, VIN2, PGOOD1, PGOOD2....................... –0.3V to 6V
COMP1, COMP2, RUN/SS1, RUN/SS2
VFB1, VFB2,TRACK1, TRACK2....................... –0.3V to VIN
SW, VOUT....................................... –0.3V to (VIN + 0.3V)
Very Low Dropout Regulator
LDO_IN, PGOOD3, EN3................................. –0.3V to 6V
LDO_OUT.........................................................–0.3 to 4V
FB3......................................... –0.3V to (LDO_IN + 0.3V)
LDO_OUT Short-Circuit.................................... Indefinite
Internal Operating Temperature Range
(Notes 2, 5)............................................. –40°C to 125°C
Junction Temperature............................................ 125°C
Storage Temperature Range................... –55°C to 125°C
Pin Configuration
TOP VIEW
TRACK1
RUN/SS1
COMP1
PGOOD1
FB1
M
VOUT1
L
K
SW1
GND1
LDO_IN
PGOOD3
VIN1
J
GND1
H
LDO_OUT
G
FB3
GND3
FB2
BOOST3
EN3
GND3
F
GND2
E
RUN/SS2
D
VIN2
VOUT2
C
B
GND2
A
1
2
3
4
5
6
7
8
9
10
11
12
TRACK2
COMP2 SW2
PGOOD2
LGA PACKAGE
144-LEAD (15mm × 15mm × 2.82mm)
TJMAX = 125°C, θJCbottom = 2-3°C/W, θJA = 15°C/W, θJCtop = 25°C/W,
θ VALUES DETERMINED FROM 4 LAYER 76mm × 95mm PCB
WEIGHT = 1.6g
Order Information
LEAD FREE FINISH
TRAY
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE †
LTM4615EV#PBF
LTM4615EV#PBF
LTM4615V
144-Lead (15mm × 15mm × 2.82mm) LGA
–40°C to 125°C
LTM4615IV#PBF
LTM4615IV#PBF
LTM4615V
144-Lead (15mm × 15mm × 2.82mm) LGA
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
† See Note 2.
2
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LTM4615
Electrical
Characteristics
The
l denotes the specifications which apply over the full internal
operating temperature range (Note 2), otherwise specifications are at TA = 25°C, VIN = 5V, LDO_IN = 1.2V unless otherwise noted.
Per Typical Application Figure 12.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Switching Regulator Section: per Channel
VIN(DC)
Input DC Voltage Range
l
2.375
5.5
V
VOUT(DC)
Output DC Voltage Range
l
0.8
5.0
V
VOUT(DC)
Output Voltage
l
1.460
1.45
1.49
1.49
1.512
1.512
V
V
1.6
2
2.3
V
12
mA
mA
µA
CIN = 22µF, COUT = 100µF, RFB = 5.76k,
VIN = 2.375V to 5.5V, IOUT = 0A to 4A (Note 6)
0°C ≤ TJ ≤ 125°C
VIN(UVLO)
Undervoltage Lockout Threshold
IOUT = 0A
IINRUSH(VIN)
Input Inrush Current at Start-Up
IOUT = 0A, CIN = 22µF, COUT = 100µF, VOUT = 1.5V,
VIN = 5.5V
0.35
IQ(VIN)
Input Supply Bias Current
VIN = 2.375V, VOUT = 1.5V, Switching Continuous
VIN = 5.5V, VOUT = 1.5V, Switching Continuous
Shutdown, RUN = 0, VIN = 5V
28
45
7
IS(VIN)
Input Supply Current
VIN = 2.375V, VOUT = 1.5V, IOUT = 4A
VIN = 5.5V, VOUT = 1.5V, IOUT = 4A
IOUT(DC)
Output Continuous Current Range
VIN = 5.5V, VOUT = 1.5V (Note 6)
∆VOUT(LOAD + LINE)
Load and Line Regulation Accuracy VOUT = 1.5V, 0A to 4A (Note 6)
VIN = 2.375V to 5.5V
VOUT
Output Ripple Voltage
IOUT = 0A, COUT = 100µF
VIN = 5V, VOUT = 1.5V
fs
Output Ripple Voltage Frequency
IOUT = 4A, VIN = 5V, VOUT = 1.5V
∆VOUT(START)
Turn-On Overshoot
tSTART
3.2
1.48
0
±1.0
±1.3
l
VOUT(AC)
Turn-On Time
A
A
A
4
A
±1.30
±1.6
%
%
12
mVP-P
1.25
MHz
COUT = 100µF, VOUT = 1.5V, RUN/SS = 10nF,
IOUT = 0A
VIN = 3.3V
VIN = 5V
20
20
mV
mV
COUT = 100µF, VOUT = 1.5V, IOUT = 1A Resistive
Load, TRACK = VIN and RUN/SS = Float
VIN = 5V
0.5
ms
∆VOUT(LS)
Peak Deviation for Dynamic Load
Load: 0% to 50% to 0% of Full Load,
COUT = 100µF, VIN = 5V, VOUT = 1.5V
25
mV
tSETTLE
Settling Time for Dynamic Load
Step
Load: 0% to 50% to 0% of Full Load,
VIN = 5V, VOUT = 1.5V
10
µs
IOUT(PK)
Output Current Limit
COUT = 100µF, VIN = 5V, VOUT = 1.5V
8
A
VFB
Voltage at FB Pin
IOUT = 0A, VOUT = 1.5V
l
0.790
0.786
0.8
0.8
0.6
0.75
0.807
0.809
0.2
IFB
VRUN
RUN Pin On/Off Threshold
ITRACK
TRACK Pin Current
µA
0.9
0.2
VTRACK(OFFSET)
Offset Voltage
VTRACK(RANGE)
Tracking Input Range
TRACK = 0.4V
RFBHI
Resistor Between VOUT and FB Pins
∆VPGOOD
PGOOD Range
RPGOOD
PGOOD Resistance
4.96
4.99
mV
0.8
V
5.02
kΩ
±7.5
Open-Drain Pull-Down
90
V
µA
30
0
V
V
%
150
Ω
4615fb
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3
LTM4615
Electrical
Characteristics
The
l denotes the specifications which apply over the full internal
operating temperature range (Note 2), otherwise specifications are at TA = 25°C, VIN = 5V, LDO_IN = 1.2V unless otherwise noted.
Per Typical Application Figure 12.
SYMBOL
PARAMETER
CONDITIONS
MIN
VLDO_IN
Operating Voltage
(Note 3)
IIN(LDO_IN)
Operating Current
IOUT = 0mA, VOUT = 1V, EN3 = 1.2V
IIN(SHDN)
Shutdown Current
EN3 = 0V, LDO_IN = 1.5V
VBOOST3
BOOST3 Output Voltage
EN3 = 1.2V
VBOOST3(UVLO)
Undervoltage Lockout
VFB3
FB3 Internal Reference Voltage
TYP
MAX
UNITS
VLDO Section
VLDO_OUT
Output Voltage Range
VDO
Dropout Voltage
l
3.5
1
l
0.6
20
µA
4.8
5
5.2
V
0.397
0.395
0.4
0.4
0.404
0.405
2.6
V
100
250
mV
4.99
5.02
kΩ
0.4
VLDO_IN = 1.5V, VFB3 = 0.38V, IOUT = 1.5A (Note 4)
LDO Top Feedback Resistor
IOUT
Output Current
VEN3 = 1.2V
4.96
ILIM
Output Current Limit
(Note 5)
l
en
Output Voltage Noise
Frequency = 10Hz to 1MHz, ILOAD = 1A
VIH_EN3
EN3 Input High Voltage
1.14V ≤ VLDO_IN ≤ 3.5V
VIL_EN3
EN3 Input Low Voltage
1.14V ≤ VLDO_IN ≤ 3.5V
IIN_EN3
EN3 Input Current
VOL_PGOOD3
PGOOD Low Voltage
IPGOOD3 = 2mA
PGOOD Threshold
Output Threshold
Relative to VFB3
PGOOD3 High to Low
PGOOD3 Low to High
l
V
1.5
2.5
A
300
µRMS
1
–14
–4
V
V
A
V
–1
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTM4615 is tested under pulsed load conditions such that
TJ ≈ TA. The LTM4615E is guaranteed to meet performance specifications
over the 0°C to 125°C internal operating temperature range. Specifications
over the –40°C to 125°C internal operating temperature range are assured
by design, characterization and correlation with statistical process
controls. The LTM4615I is guaranteed to meet specifications over the full
internal operating temperature range. Note that the maximum ambient
temperature is determined by specific operating conditions in conjunction
with board layout, the rated package thermal resistance and other
environmental factors.
V
mA
4.3
1mA ≤ IOUT ≤ 1.5A, 1.14V ≤ VLDO_IN ≤ 3.5V,
BOOST3 = 5V, 1V ≤ VOUT ≤ 2.59V
LDO_RHI
4
1.14
0.4
V
1
µA
0.1
0.4
V
–12
–3
–10
–2
%
%
Note 3: Minimum operating voltage required for regulation is:
VIN ≥ VOUT(MIN) + VDROPOUT
Note 4: Dropout voltage is the minimum input to output differential needed
to maintain regulation at a specified output current. In dropout the output
voltage will be equal to VIN – VDROPOUT .
Note 5: The LTM4615 has overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperatures will exceed 125°C when overtemperature is activated.
Continuous overtemperature activation can impair long-term reliability.
Note 6: See output current derating curves for different VIN, VOUT and TA.
4615fb
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LTM4615
Typical Performance Characteristics
Switching Regulators
Efficiency vs Output Current
VIN = 3.3V
95
95
95
90
90
90
85
80
65
0
1
85
80
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.5V
VOUT = 1.2V
VOUT = 0.8V
75
VOUT = 1.8V
VOUT = 1.5V
VOUT = 1.2V
VOUT = 0.8V
70
70
2
3
OUTPUT CURRENT (A)
4
EFFICIENCY (%)
100
75
65
0
1
3.0
2.5
80
2
4
3
OUTPUT CURRENT (A)
65
VOUT
20mV/DIV
1.0
20µs/DIV
VIN = 5V
VOUT = 1.2V
COUT = 100µF, 6.3V CERAMICS
0.5
0
4
ILOAD
2A/DIV
VOUT
20mV/DIV
1.5
1
2
3
OUTPUT CURRENT (A)
Load Transient Response
ILOAD
2A/DIV
2.0
0
4615 G03
Load Transient Response
VOUT = 3.3V
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.5V
VOUT = 1.2V
VOUT = 0.8V
VOUT = 3.3V
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.5V
VOUT = 1.2V
VOUT = 0.8V
75
4615 G02
Minimum Input Voltage
at 4A Load
3.5
85
70
4615 G01
VOUT (V)
Efficiency vs Output Current
VIN = 5V
100
EFFICIENCY (%)
EFFICIENCY (%)
Efficiency vs Output Current
VIN = 2.5V
20µs/DIV
VIN = 5V
VOUT = 1.5V
COUT = 100µF, 6.3V CERAMICS
4615 G05
4615 G06
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
VIN (V)
4615 G04
Load Transient Response
Load Transient Response
Load Transient Response
ILOAD
2A/DIV
ILOAD
2A/DIV
VOUT
20mV/DIV
ILOAD
2A/DIV
VOUT
20mV/DIV
VOUT
20mV/DIV
20µs/DIV
VIN = 5V
VOUT = 1.8V
COUT = 100µF, 6.3V CERAMICS
4615 G07
20µs/DIV
VIN = 5V
VOUT = 2.5V
COUT = 100µF, 6.3V CERAMICS
4615 G08
20µs/DIV
VIN = 5V
VOUT = 3.3V
COUT = 100µF, 6.3V CERAMICS
4615 G09
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5
LTM4615
Typical Performance Characteristics
Start-Up
Start-Up
806
VOUT
1V/DIV
VFB vs Temperature
804
VOUT
1V/DIV
VFB (mV)
802
IIN
1A/DIV
IIN
1A/DIV
800
798
4615 G10
VIN = 5V
200µs/DIV
VOUT = 2.5V
COUT = 100µF
NO LOAD
(0.01µF SOFT-START CAPACITOR)
VIN = 5V
200µs/DIV
VOUT = 2.5V
COUT = 100µF
4A LOAD
(0.01µF SOFT-START CAPACITOR)
4615 G11
796
794
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
4615 G12
Short-Circuit Protection
1.5V Short, No Load
Current Limit
Short-Circuit Protection
1.5V Short, 4A Load
1.6
1.4
1.2
VOUT
0.5V/DIV
VOUT
0.5V/DIV
IIN
1A/DIV
IIN
1A/DIV
VOUT (V)
1.0
0.8
0.6
VOUT = 1.5V
VIN = 5V
0.2
VIN = 3.3V
VIN = 2.5V
0
4
5
3
0.4
4615 G14
20µs/DIV
7
6
OUTPUT CURRENT (A)
4615 G15
100µs/DIV
8
4615 G13
VLDO
VFB3 vs Temperature
Dropout Voltage vs Input Voltage
200
404
180
403
10kHz
50
400
1.5A
399
140
120
100
80
60
398
VBOOST3 = 5V
VLDO_IN = 1.5V
VLDO_OUT =1.2V
397
–25
0
25
50
75
TEMPERATURE (°C)
100
125
4615 G16
RIPPLE REJECTION (dB)
1mA
DROPOUT (mV)
FB3 VOLTAGE (mV)
401
6
VFB3 = 0.38V
ILDO_OUT =1.5A
160
402
396
–50
Ripple Rejection
60
–40°C
25°C
85°C
125°C
40
20
0
1.2
1.4
1.6
1.8
2.0
VLDO_IN (V)
2.2
2.4
1MHz
40
100kHz
30
20
VBOOST3 = 5V
VLDO_OUT =1.2V
IOUT = 800mA
COUT = 10µF
10
2.6
4615 G17
0
1.2
1.4
1.6
1.8 2.0
2.2
VLDO_IN (V)
2.4
2.6
4615 G18
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LTM4615
Typical Performance Characteristics
Delay from Enable to Power Good
Output Current Limit
5.0
60
4.5
5.0
VLDO_OUT = 0V
TA = 25°C
4.0
30
VBOOST3 = 5V
VLDO_IN = 1.5V
VLDO_OUT =1.2V
IOUT = 800mA
COUT = 10µF
20
10
0
100
1000
10000
100000 1000000 1E+07
FREQUENCY (Hz)
3.5
3.5
DELAY (ms)
40
3.0
2.5
2.0
VLDO_OUT = 0.8V
RLDO_OUT = 8Ω
–40°C
25°C
85°C
4.5
4.0
50
ILDO_OUT (A)
RIPPLE REJECTION (dB)
Ripple Rejection
70
CURRENT LIMIT
4615 G19
2.5
2.0
1.5
1.0
THERMAL LIMIT
1.5
1.0
1.0
3.0
0.5
1.5
2.0
3.0
2.5
VLDO_IN (V)
3.5
0
1.0
1.5
2.5
2.0
VLDO_IN (V)
4615 G20
Output Load Transient Response
3.0
3.5
4615 G21
IN Supply Transient Response
1.5A
ILDO_OUT
2mA
2V
VLDO_IN
1.5V
VLDO_OUT
AC
20mV/DIV
VLDO_OUT
AC
10mV/DIV
VLDO_OUT = 1.5V 50µs/DIV
COUT = 10µF
VLDO_IN = 1.7V
VBOOST3 = 5V
VLDO_OUT = 1.2V 10µs/DIV
ILDO_OUT = 800mA
COUT = 10µF
VBOOST3 = 5V
TA = 25°C
4615 G22
BOOST3 Ripple and Feedthrough to
VLDO_OUT
BOOST3/OUT Start-Up
EN3
4615 G23
HI
LO
BOOST3
AC 20mV/DIV
5V
BOOST3
1V
1.5V
VLDO_OUT
AC 5mV/DIV
VLDO_OUT
0V
TA = 25°C
RLDO_OUT = 1Ω
VLDO_IN = 1.7V
200µs/DIV
4615 G24
VLDO_OUT = 1.2V 20µs/DIV
VLDO_IN = 1.5V
ILDO_OUT = 1A
COUT = 10µF
TA = 25°C
4615 G25
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7
LTM4615
Pin Functions
VIN1, VIN2 (J1-J5, K1-K5); (C1-C6, D1-D5): Power Input
Pins. Apply input voltage between these pins and GND
pins. Recommend placing input decoupling capacitance
directly between VIN pins and GND pins.
VOUT1, VOUT2 (K9-K12, L9-L12, M9-M12); (C9-C12,
D9-D12, E11-E12): Power Output Pins. Apply output load
between these pins and GND pins. Recommend placing
output decoupling capacitance directly between these pins
and GND pins. Review Table 4.
GND1, GND2, (H1, H7-H12, J6-J12, K6-K8 L1, L7-L8,
M1-M8); (A1-A12, B1, B7-B12, C7-C8, D6-D8, E1,
E8-E10): Power Ground Pins for Both Input and Output
Returns.
TRACK1, TRACK2 (L3, E3): Output Voltage Tracking Pins.
When the module is configured as a master output, then a
soft-start capacitor is placed on the RUN/SS pin to ground
to control the master ramp rate, or an external ramp can
be applied to the master regulator’s track pin to control it.
Slave operation is performed by putting a resistor divider
from the master output to ground, and connecting the
center point of the divider to this pin on the slave regulator.
If tracking is not desired, then connect the TRACK pin to
VIN. Load current must be present for tracking. See the
Applications Information section.
FB1, FB2 (L6, E6): The Negative Input of the Switching
Regulators’ Error Amplifier. Internally, these pins are connected to VOUT with a 4.99k precision resistor. Different
output voltages can be programmed with an additional
resistor between the FB and GND pins. Two power modules
can current share when this pin is connected in parallel
with the adjacent module’s FB pin. See the Applications
Information section.
FB3 (F6): The Negative Input of the LDO Error Amplifier.
Internally the pin is connected to LDO_OUT with a 4.99k
resistor. Different output voltages can be programmed with
an additional resistor between the FB3 and GND pins. See
the Applications Information section.
8
COMP1, COMP2 (L5, E5): Current Control Threshold
and Error Amplifier Compensation Point. The current
comparator threshold increases with this control voltage.
Two power modules can current share when this pin is
connected in parallel with the adjacent module’s COMP
pin. Each channel has been internally compensated. See
the Applications Information section.
PGOOD1, PGOOD2 (L4, E4): Output Voltage Power
Good Indicator. Open-drain logic output that is pulled to
ground when the output voltage is not within ±7.5% of
the regulation point.
RUN/SS1, RUN/SS2 (L2, E2): Run Control and Soft-Start
Pin. A voltage above 0.8V will turn on the module, and
below 0.5V will turn off the module. This pin has a 1M
resistor to VIN and a 1000pF capacitor to GND. See the
Applications Information section for soft-start information.
SW1, SW2 (H2-H6, B2-B6): The switching node of the
circuit is used for testing purposes. This can be connected
to copper on the board for improved thermal performance.
SW1 and SW2 must be floating on separate copper planes.
LDO_IN (G1-G4): VLDO Input Power Pins. Place input
capacitor close to these pins.
LDO_OUT (G9-G12): VLDO Output Power Pins. Place
output capacitor close to these pins. Minimum 1mA load
is necessary for proper output voltage accuracy.
BOOST3 (E7): Boost Supply for Driving the Internal VLDO
NMOS Into Full Enhancement. The pin is use for testing
the internal boost converter. The output is typically 5V.
GND3 (F1-F5, F7, F9-F12, G6-G8): The power ground pins
for both input and output returns for the internal VLDO.
PGOOD3 (G5): VLDO Power Good Pin.
EN3 (F8): VLDO Enable Pin.
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LTM4615
Simplified Block Diagram
Switching Regulator Block Diagram
VIN
PGOOD
RUN/SS
RSS
1M
CSS
1000pF
CSSEXT
TRACK
SUPPLY
4.99k
TRACK
5.76k
VIN
22µF 2.375V TO 5.5V
6.3V
4.7µF
6.3V
CONTROL, DRIVE
POWER FETS
COMP
M1
0.47µH
M2
470pF
VOUT
1.5V
4A
VOUT
4.7µF
6.3V
22µF
6.3V
×3
RFBHI
4.99k
INTERNAL
COMP
GND
FB
SW
4615 F01a
RFB
5.76k
VLDO Block Diagram
BOOST3
5V BOOST
VIN
1.14V TO 3.5V
4.7µF
LDO_IN
4.7µF
6.3V 0.4V
10µF
GND3
EN3
+
–
GND3
GND3
ENABLE
VOUT
1V
10µF 1.5A
LDO_OUT
CONTROL
LDO_RHI
4.99k
4.7µF
6.3V
GND3
POWER GOOD
FB3
RFBLDO
3.32k
PGOOD3
GND3
10k
4615 F01b
GND
1V
Figure 1. Simplified LTM4615 Block Diagram of Each Switching Regulator Channel and the VLDO
Decoupling Requirements
TA = 25°C. Use Figure 1 configuration for each channel.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
CIN
External Input Capacitor Requirement
(VIN = 2.375V to 5.5V, VOUT = 1.5V)
IOUT = 4A
22
COUT
External Output Capacitor Requirement
(VIN = 2.375V to 5.5V, VOUT = 1.5V)
IOUT = 4A
66
100
µF
LDO_IN
LDO Input Capacitance
IOUT = 1A
4.7
10
µF
LDO_OUT
LDO Output Capacitance
IOUT = 1A
10
µF
µF
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9
LTM4615
Operation
LTM4615 Power Module Description
Dual Switching Regulator Section
The LTM4615 is a standalone dual nonisolated switching
mode DC/DC power supply with an additional onboard
1.5A VLDO. It can deliver up to 4A of DC output current
for each channel with few external input and output capacitors. This module provides two precisely regulated
output voltages programmable via one external resistor
for each channel from 0.8V DC to 5V DC over a 2.375V
to 5.5V input voltage range. The VLDO is an independent
1.5A linear regulator that can be powered from either
switching converter. The typical application schematic is
shown in Figure 12.
The LTM4615 has two integrated constant frequency current mode regulators, with built-in power MOSFETs with
fast switching speed. The typical switching frequency is
1.25MHz. With current mode control and internal feedback
loop compensation, these switching regulators have sufficient stability margins and good transient performance
under a wide range of operating conditions, and with a
wide range of output capacitors, even all ceramic output
capacitors.
Current mode control provides cycle-by-cycle fast current
limit. Besides, current limiting is provided in an overcurrent condition with thermal shutdown. In addition, internal
overvoltage and undervoltage comparators pull the opendrain PGOOD outputs low if the particular output feedback
voltage exits a ±7.5% window around the regulation point.
Furthermore, in an overvoltage condition, internal top FET,
M1, is turned off and bottom FET, M2, is turned on and
held on until the overvoltage condition clears, or current
limit is exceeded.
Pulling each specific RUN/SS pin below 0.8V forces the
specific regulator controller into its shutdown state, turning off both M1 and M2 for each power stage. At low load
current, each regulator works in continuous current mode
by default to achieve minimum output voltage ripple.
The LTM4615 is internally compensated to be stable over
the operating conditions. Table 4 provides a guideline
for input and output capacitance for several operating
conditions. The LTpowerCAD™ Design Tool is provided
for transient and stability analysis.
The FB pins are used to program the specific output voltage with a single resistor to ground.
VLDO Section
The VLDO (very low dropout) linear regulator operates
from a 1.14V to 3.5V input. The VLDO uses an internal
NMOS transistor as the pass device in a source-follower
configuration. The BOOST3 pin is the output of an internal boost converter that supplies the higher supply drive
to the pass device for low dropout enhancement. The
internal boost converter operates on very low current,
thus optimizing high efficiency for the VLDO in close to
dropout operation.
An undervoltage lockout comparator on the LDO ensures
that the boost voltage is greater than 4.2V before enabling
the LDO, otherwise the LDO is disabled.
The LDO provides a high accuracy output capable of supply
1.5A of output current with a typical drop out of 100mV.
A single ceramic 10µF capacitor is all that is required
for output capacitor bypassing. A low reference voltage
allows the VLDO to have lower output voltages than the
commonly available LDO.
The device also includes current limit and thermal overload protection. The NMOS follower architecture has fast
transient response without the traditional high drive currents in dropout. The VLDO includes a soft-start feature
to prevent excessive current on the input during start-up.
When the VLDO is enabled, the soft-start circuitry gradually increases the reference voltage from 0V to 0.4V over
a period of approximately 200µs.
The TRACK pins are used for power supply tracking for
each specific regulator. See the Applications Information
section.
10
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LTM4615
Applications Information
Dual Switching Regulator
The typical LTM4615 application circuit is shown in Figure 12. External component selection is primarily determined by the maximum load current and output voltage.
Refer to Table 4 for specific external capacitor requirements
for a particular application.
VIN to VOUT Step-Down Ratios
There are restrictions in the maximum VIN to VOUT stepdown ratio that can be achieved for a given input voltage
on the two switching regulators. The LTM4615 is 100%
duty cycle, but the VIN to VOUT minimum dropout will be
a function the load current. A typical 0.5V minimum is
sufficient.
Each regulator channel has an internal 0.8V reference
voltage. As shown in the block diagram, a 4.99k internal
feedback resistor connects the VOUT and FB pins together.
The output voltage will default to 0.8V with no feedback
resistor. Adding a resistor RFB from the FB pin to GND
programs the output voltage:
4.99k +RFB
RFB
D=
VOUT
VIN
Without considering the inductor ripple current, the RMS
current of the input capacitor can be estimated as:
ICIN(RMS) =
IOUT(MAX)
η%
• D • (1– D)
In the above equation, η% is the estimated efficiency of
the power module. If a low inductance plane is used to
power the device, then no input capacitance is required. The
internal 4.7µF ceramics on each channel input are typically
rated for 1A of RMS ripple current up to 85°C operation.
The worse-case ripple current for the 4A maximum current
is 2A or less. An additional 10µF or 22µF ceramic capacitor
can be used to supplement the internal capacitor with an
additional 1A to 2A ripple current rating.
Output Capacitors
or equivalently,
RFB =
For a buck converter, the switching duty cycle can be
estimated as:
Output Voltage Programming
VOUT = 0.8V •
current requirements. A 47µF bulk capacitor can be used
for more input capacitance. This 47µF capacitor is only
needed if the input source impedance is compromised by
long inductive leads or traces. The bulk capacitor can be
a switcher-rated aluminum electrolytic OS-CON capacitor.
4.99k
VOUT
−1
0.8V
Table 1. FB Resistor Table vs Various Output Voltages
VOUT
0.8V
1.2V
1.5V
1.8V
2.5V
3.3V
FB
Open
10k
5.76k
3.92k
2.37k
1.62k
Input Capacitors
The LTM4615 module should be connected to a low AC
impedance DC source. One 4.7µF ceramic capacitor is
included inside the module for each regulator channel.
Additional input capacitors are needed if a large load step
is required, up to the full 4A level, and for RMS ripple
The LTM4615 switchers are designed for low output voltage ripple on each channel. The bulk output capacitors
are chosen with low enough effective series resistance
(ESR) to meet the output voltage ripple and transient
requirements. The output capacitors can be a low ESR
tantalum capacitor, low ESR polymer capacitor or ceramic
capacitor. The typical output capacitance range is 66µF
to 100µF. Additional output filtering may be required by
the system designer if further reduction of output ripple
or dynamic transient spikes is required. Table 4 shows a
matrix of different output voltages and output capacitors
to minimize the voltage droop and overshoot during a 2A/
µs transient. The table optimizes total equivalent ESR and
total bulk capacitance to maximize transient performance.
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11
LTM4615
Applications Information
Fault Conditions: Current Limit and Overtemperature
Protection
The LTM4615 has current mode control, which inherently limits the cycle-by-cycle inductor current not only
in steady-state operation, but also in transient.
Along with current limiting in the event of an overload
condition, the LTM4615 has overtemperature shutdown
protection that inhibits switching operation around 150°C
for each channel.
Run Enable and Soft-Start
The RUN/SS pins provide a dual function of enable and
soft-start control for each channel. The RUN/SS pins are
used to control turn on of the LTM4615. While each enable
pin is below 0.5V, the LTM4615 will be in a low quiescent
current state. At least a 0.8V level applied to the enable
pins will turn on the LTM4615 regulators. This pin can be
used to sequence the regulator channels. The soft-start
control is provided by a 1M pull-up resistor (RSS) and a
1000pF capacitor (CSS) as drawn in the block diagram
for each channel. An external capacitor can be applied to
the RUN/SS pin to increase the soft-start time. A typical
value is 0.01µF. The approximate equation for soft-start:
where RSS and CSS are shown in the block diagram of
Figure 1, and the 1.8V is soft-start upper range. The softstart function can also be used to control the output ramp-up
time, so that another regulator can be easily tracked to it.
Output Voltage Tracking
Output voltage tracking can be programmed externally
using the TRACK pins. Either output can be tracked up
or down with another regulator. The master regulator’s
output is divided down with an external resistor divider
that is the same as the slave regulator’s feedback divider
to implement coincident tracking. The LTM4615 uses a
very accurate 4.99k resistor for the internal top feedback
resistor. Figure 2 shows an example of coincident tracking.
Equations:
⎛
⎞
RFB1
TRACK1= ⎜
⎟ • Master
⎝ 4.99k +RFB1 ⎠
⎛ 4.99k ⎞
Slave = ⎜1+
⎟ • TRACK1
R
⎝
⎠
FB1
⎛ VIN ⎞
tSOFTSTART = In ⎜
⎟ • RSS • CSS
⎝ VIN – 1.8V ⎠
VIN 3V TO 5.5V
C1
PGOOD1 10µF
6.3V
R3
10k
SLAVE
1.2V
4A
C10
22µF
6.3V
C3
22µF
6.3V
C9
22µF
6.3V
1.5V
RTB
4.99k
L1 0.2µH*
1.2V
C4
22µF
6.3V
RFB1
10k
RTA
10k
C12
10µF
*FAIR-RITE 0805 2508056007Y6
OPTIONAL FILTER
C2
10µF
PGOOD2
6.3V
VIN2
VIN1
PGOOD1
PGOOD2
VOUT1
VOUT2
FB1
FB2
COMP1
COMP2
TRACK1
TRACK2
LTM4615
RUN/SS2
RUN/SS1
LDO_OUT
LDO_IN
FB3
EN3
PGOOD3
BOOST3
GND1
GND3
GND2
R4
10k
MASTER
1.5V
4A
RFB2
5.76k
VIN OR A CONTROL RAMP
1V LOW NOISE AT 1A
R6
10k
PGOOD3
R5
3.32k
1V
LOW NOISE
C11
10µF
6.3V
C5
22µF
6.3V
C6
22µF
6.3V
C8
22µF
6.3V
C7
22µF
6.3V
C13
CSSEXT
4615 F02
Figure 2. Dual Outputs (1.5V and 1.2V) with Tracking
12
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LTM4615
Applications Information
TRACK1 is the track ramp applied to the slave’s track pin.
TRACK1 applies the track reference for the slave output up
to the point of the programmed value at which TRACK1
proceeds beyond the 0.8V reference value. The TRACK1
pin must go beyond the 0.8V to ensure the slave output
has reached its final value.
Ratiometric tracking can be achieved by a few simple
calculations and the slew rate value applied to the master’s
TRACK pin. As mentioned above, the TRACK pin has a
control range from 0V to 0.8V. The control ramp slew rate
applied to the master’s TRACK pin is directly equal to the
master’s output slew rate in Volts/Time.
The equation:
where MR is the master’s output slew rate and SR is the
slave’s output slew rate in Volts/Time. When coincident
tracking is desired, then MR and SR are equal, thus RTB
is equal to 4.99k. RTA is derived from equation:
In ratiometric tracking, a different slew rate maybe desired
for the slave regulator. RTB can be solved for when SR is
slower than MR. Make sure that the slave supply slew
rate is chosen to be fast enough so that the slave output
voltage will reach it final value before the master output.
For example, MR = 2.5V/ms and SR = 1.8V/1ms. Then
RTB = 6.98k. Solve for RTA to equal to 3.24k. The master
output must be greater than the slave output for the
tracking to work. Output load current must be present
for tracking to operate properly during power-down.
Power Good
MR
• 4.99k = RTB
SR
RTA =
Figure 3 shows the output voltage tracking waveform for
coincident tracking.
0.8V
VFB VTRACK
VFB
+
–
4.99k RFB
RTB
where VFB is the feedback voltage reference of the regulator, and VTRACK is 0.8V. Since RTB is equal to the 4.99k top
feedback resistor of the slave regulator in equal slew rate
or coincident tracking, then RTA is equal to RFB with VFB =
VTRACK. Therefore RTB = 4.99k and RTA = 10k in Figure 2.
OUTPUT VOLTAGE (V)
MASTER OUTPUT
SLAVE OUTPUT
PGOOD1 and PGOOD2 are open-drain pins that can be
used to monitor valid output voltage regulation. These
pins monitor a ±7.5% window around the regulation point.
If the output is disabled, the respective pin will go low.
COMP Pin
This pin is the external compensation pin. The module
has already been internally compensated for all output
voltages. Table 4 is provided for most application requirements. The LTpowerCAD Design Tool is provided for other
control loop optimization. The COMP pins must be tied
together in parallel operation.
Parallel Switching Regulator Operation
The LTM4615 switching regulators are inherently current
mode control. Paralleling will have very good current sharing. This will balance the thermals on the design. Figure
13 shows a schematic of a parallel design. The voltage
feedback equation changes with the variable N as channels are paralleled.
The equation:
TIME
VOUT
4.99k
+RFB
N
= 0.8V •
RFB
N is the number of paralleled channels.
4615 F03
Figure 3. Output Voltage Coincident Tracking
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13
LTM4615
Applications Information
pacitance can be used, but a ceramic capacitor must be
used in parallel at the output.
VLDO Section
Adjustable Output Voltage
The output voltage is set by the ratio of two resistors. A
4.99k resistor is built onboard the module from LDO_OUT
to FB3. An additional resistor (RFBLDO)is required from FB3
to GND3 to set the output voltage over a range of 0.4V to
2.6V. Minimum output current of 1mA is required for full
output voltage range.
4.99k +RFBLDO
RFBLDO
or equivalently,
RFBLDO =
4.99k
V LDO _ OUT
0.4V
Short-Circuit/Thermal Protection
The VLDO has built-in short-circuit current limiting of
~3A as well as overtemperature protection. During shortcircuit conditions the device is in control to 3A, and as
the internal temperature rises to approximately 150°C,
then the internal boost and LDO are shut down until the
internal temperature drops back to 140°C. The device will
cycle in and out of this mode with no latchup or damage.
Long term over stress in this condition can degrade the
device over time.
The equation:
VLDO _ OUT = 0.4V •
Extra consideration should be given to the use of ceramic
capacitors related to dielectrics, temperature and DC bias
effects on the capacitor. The VLDO requires a minimum
10µF value. The X7R and X5R dielectrics are more stable
with DC bias and temperature, thus more preferred.
−1
Power Good Operation
Reverse Current Protection
The VLDO includes an open-drain power good (PGOOD3)
pin with hysteresis. If the VLDO is in shutdown or under
UVLO conditions (BOOST3 < 4.2V), then PGOOD3 is low
impedance to ground. PGOOD3 becomes high impedance when the VLDO output voltage rises to 93% of its
regulated voltage. PGOOD3 stays high impedance until
the output voltage falls to 91% of its regulated voltage. A
pull-up resistor can be inserted between the PGOOD3 pin
and a positive logic supply such as the VLDO output or
VIN. LDO_IN should be at least 1.14V or greater for power
good to operate properly.
The VLDO features reverse current protection to limit
current draw from any supplementary power source at
the output. Figure 4 shows the reverse input current limit
versus input voltage for a nominal VLDO_OUT setpoint of
1.5V. Note: Positive input current represents current flowing into the LDO_IN pin. With LDO_OUT held at or below
the output regulation voltage and LDO_IN varied, input
current flow will follow the Figure 4 curve. Input reverse
current ramps up to 16µA as LDO_IN approaches LDO_OUT.
The VLDO is designed to be stable with a wide range of
ceramic output capacitors. The ESR of the output capacitors affects stability, especially smaller value capacitors. An
output capacitor of 10µF or greater with an ESR of 0.05Ω
or less is recommended to ensure stability. Larger value
capacitors can be used to reduce the transient deviations
under load changes. Bypass capacitors that are used at
the load device can also increase the effective output
capacitance. High ESR tantalum or electrolytic bulk ca-
14
IN CURRENT
LIMIT ABOVE 1.45V
20
LDO_IN CURRENT (µA)
Output Capacitance and Transient Response
30
10
0
–10
–20
–30
0
0.3
0.9
0.6
1.2
LDO_IN VOLTAGE (V)
1.5
1.8
4615 F04
Figure 4. Reverse Current Limit for VLDO
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Applications Information
Reverse input current will spike up as LDO_IN gets to
within about 30mV of LDO_OUT as reverse current protection circuitry is disabled and normal operation resumes.
As LDO_IN transitions above LDO_OUT the reverse current
transitions into short circuit current as long as LDO_OUT
is held below the regulation voltage.
Thermal Considerations and Output Current Derating
The power loss curves in Figures 5 and 6 can be used
in coordination with the load current derating curves in
Figures 7 to 10 for calculating an approximate θJA thermal
resistance for the LTM4615 with various heat sinking and
airflow conditions. Both of the LTM4615 outputs are at full
4A load current, and the power loss curves in Figures 5
and 6 are combined power losses plotted for both output
voltages up to 4A each. The VLDO regulator is set to have
a power dissipation of 0.5W since it is generally used with
dropout voltages of 0.5V or less. For example: 1.2V to 1V,
1.5V to 1V, 1.5V to 1.2V and 1.8V to 1.5V. Other dropout
voltages can be supported at VLDO maximum load, but
further thermal analysis will be required for the VLDO.
The 4A output voltages are 1.2V and 3.3V. These voltages
are chosen to include the lower and higher output voltage
ranges for correlating the thermal resistance. Thermal
models are derived from several temperature measurements in a controlled temperature chamber along with
thermal modeling analysis. The junction temperatures are
monitored while ambient temperature is increased with and
without airflow. The junctions are maintained at ~120°C
2.5
while lowering output current or power with increasing
ambient temperature. The 120°C value is chosen to allow
for a 5°C margin window relative to the maximum 125°C
limit. The decreased output current will decrease the internal module loss as ambient temperature is increased. The
power loss curves in Figures 5 and 6 show this amount of
power loss as a function of load current that is specified
for both channels. The monitored junction temperature of
120°C minus the ambient operating temperature specifies
how much module temperature rise can be allowed. As
an example, in Figure 7 the load current is derated to 3A
for each channel with 0LFM at ~90°C and the power loss
for both channels at 5V to 1.2V at 3A output is ~1.4W.
Add the VDLO power loss of 0.5W to equal 1.9W. If the
90°C ambient temperature is subtracted from the 120°C
maximum junction temperature, then the difference of 30°C
divided by 1.9W equals a 15.7°C/W thermal resistance.
Table 2 specifies a 15°C/W value which is very close. Table
2 and Table 3 provide equivalent thermal resistances for
1.2V and 3.3V outputs with and without air flow and heat
sinking. The combined power loss for the two 4A outputs
plus the VLDO power loss can be summed together and
multiplied by the thermal resistance values in Tables 2 and
3 for module temperature rise under the specified conditions. The printed circuit board is a 1.6mm thick four layer
board with two ounce copper for the two outer layers and 1
ounce copper for the two inner layers. The PCB dimensions
are 95mm × 76mm. The BGA heat sinks are listed below
Table 3. The data sheet lists the θJC (Junction to Case)
thermal resistances under the Pin Configuration diagram.
3.0
VIN = 5V
POWER LOSS (W)
POWER LOSS (W)
2.0
1.5
1.0
0.5
0
VIN = 5V
2.5
2.0
1.5
1.0
0.5
0
1
2
3
4
0
0
LOAD CURRENT (A)
4615 F05
Figure 5. 1.2V Power Loss
1
2
3
LOAD CURRENT (A)
4
4615 F06
Figure 6. 3.3V Power Loss
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15
LTM4615
Applications Information
4.5
4.5
VIN = 5V
4.0
4.0
3.5
LOAD CURRENT (A)
LOAD CURRENT (A)
3.5
3.0
2.5
2.0
1.5
1.0
40
50
3.0
2.5
2.0
1.5
1.0
0LFM NO HEATSINK
200LFM NO HEATSINK
400LFM NO HEATSINK
0.5
0
VIN = 5V
0LFM HEATSINK
200LFM HEATSINK
400LFM HEATSINK
0.5
0
60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
40
60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
50
4615 F08
4615 F07
Figure 7. 1.2V No Heat Sink
4.5
4.0
Figure 8. 1.2V Heat Sink
4.5
VIN = 5V
4.0
3.5
LOAD CURRENT (A)
LOAD CURRENT (A)
3.5
3.0
2.5
2.0
1.5
1.0
40
50
3.0
2.5
2.0
1.5
1.0
0LFM NO HEATSINK
200LFM NO HEATSINK
400LFM NO HEATSINK
0.5
0
VIN = 5V
0LFM HEATSINK
200LFM HEATSINK
400LFM HEATSINK
0.5
60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
0
40
50
60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4615 F10
4615 F09
Figure 9. 3.3V No Heat Sink
16
Figure 10. 3.3V Heat Sink
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LTM4615
Applications Information
Table 2. 1.2V Output
DERATING CURVE
VIN (V)
POWER LOSS CURVE
AIRFLOW (LFM)
HEAT SINK
θJA (°C/W)
Figure 7
5
Figure 5
0
None
15
Figure 7
5
Figure 5
200
None
12
Figure 7
5
Figure 5
400
None
10
Figure 8
5
Figure 5
0
BGA Heat Sink
14
Figure 8
5
Figure 5
200
BGA Heat Sink
9
Figure 8
5
Figure 5
400
BGA Heat Sink
8
DERATING CURVE
VIN (V)
POWER LOSS CURVE
AIRFLOW (LFM)
HEAT SINK
θJA (°C/W)
Figure 9
5
Figure 6
0
None
15
Table 3. 3.3V Output
Figure 9
5
Figure 6
200
None
12
Figure 9
5
Figure 6
400
None
10
Figure 10
5
Figure 6
0
BGA Heat Sink
14
Figure 10
5
Figure 6
200
BGA Heat Sink
9
Figure 10
5
Figure 6
400
BGA Heat Sink
8
HEAT SINK MANUFACTURER
PART NUMBER
WEBSITE
Aavid
375424B00034G
www.aavid.com
Cool Innovations
4-050503P to 4-050508P
www.coolinnovations.com
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17
LTM4615
Applications Information
Safety Considerations
• Place high frequency ceramic input and output capacitors next to the VIN, GND and VOUT pins to minimize
high frequency noise.
The LTM4615 modules do not provide galvanic isolation
from VIN to VOUT . There is no internal fuse. If required,
a slow blow fuse with a rating twice the maximum input
current needs to be provided to protect each unit from
catastrophic failure.
• Place a dedicated power ground layer underneath the
unit.
• To minimize the via conduction loss and reduce module
thermal stress, use multiple vias for interconnection
between the top layer and other power layers.
Layout Checklist/Example
The high integration of LTM4615 makes the PCB board
layout very simple and easy. However, to optimize its electrical and thermal performance, some layout considerations
are still necessary.
• Do not put via directly on pads unless the via is capped.
Figure 11 gives a good example of the recommended layout.
• Use large PCB copper areas for high current path,
including VIN, GND and VOUT. It helps to minimize the
PCB conduction loss and thermal stress.
VOUT1
GND1 CONTROL
CIN1
GND1
M
COUT1 COUT2 V
OUT1
L
K
VIN1
SW1
J
GND1
C
LD0_IN IN2
CONTROL
GND1
H
COUT3
G
GND3
F
GND2
E
GND3
COUT4 COUT5
D
VIN2
LDO_OUT
VOUT2
C
B
GND2
GND2
A
CIN3
1
2
3
4
GND2
5
6
SW2
7
8
9
10 11 12
GND2
4615 F11
Figure 11. Recommended PCB Layout
18
4615fb
For more information www.linear.com/LTM4615
LTM4615
Applications Information
VIN 3V TO 5.5V
CIN2
10µF
PGOOD2
6.3V
CIN1
PGOOD1 10µF
6.3V
R3
10k
VOUT1
1.2V
4A
100µF
6.3V
22µF
6.3V
VIN
L1 0.2µH*
COUT1
22µF
6.3V
1.2V
RFB1
10k
C12
10µF
VIN2
VIN1
PGOOD1
PGOOD2
VOUT1
VOUT2
FB1
FB2
COMP1
COMP2
TRACK1
TRACK2
LTM4615
RUN/SS2
RUN/SS1
LDO_OUT
LDO_IN
FB3
EN3
PGOOD3
BOOST3
GND1
GND3
GND2
R4
10k
RFB2
5.76k
VIN
VOUT3
1V LOW NOISE AT 1A
R6
10k
*FAIR-RITE 0805 2508056007Y6
IF MORE FILTERING REQUIRED
PGOOD3
R5
3.32k
C11
10µF
6.3V
VOUT3
VOUT2
1.5V
4A
COUT2
100µF
6.3V
22µF
6.3V
22µF
6.3V
4615 F12
Figure 12. Typical 3V to 5.5VIN, 1.5V and 1.2V at 4A and 1V at 1A Design
Table 4. Output Voltage Response vs Component Matrix (Refer to Figure 12) 0A to 2.5A Load Step Typical Measured Values
COUT1 AND COUT2
CERAMIC VENDORS
VALUE
PART NUMBER
COUT1 AND COUT2
BULK VENDORS
VALUE
PART NUMBER
TDK
22µF 6.3V
C3216X7SOJ226M
Sanyo POSCAP
150µF 10V
10TPD150M
Murata
22µF 16V
GRM31CR61C226KE15L
Sanyo POSCAP
220µF 4V
4TPE220MF
TDK
100µF 6.3V
C4532X5R0J107MZ
CIN BULK VENDORS
VALUE
PART NUMBER
Murata
100µF 6.3V
GRM32ER60J107M
Sanyo POSCAP
100µF 10V
10CE100FH
VOUT
CIN
CIN
COUT1 AND COUT2 COUT1 AND COUT2
(V)
(CERAMIC) (BULK)*
(CER) EACH
(POSCAP) EACH
1.2
100µF
None
10µF ×2
100µF, 22µF ×2
1.2
100µF
220µF
10µF ×2
22µF ×1
1.2
100µF
None
10µF ×2
100µF, 22µF ×2
1.2
100µF
220µF
10µF ×2
22µF ×1
1.5
100µF
None
10µF ×2
100µF, 22µF ×2
1.5
100µF
220µF
10µF ×2
22µF ×1
1.5
100µF
None
10µF ×2
100µF, 22µF ×2
1.5
100µF
220µF
10µF ×2
22µF ×1
1.8
100µF
None
10µF ×2
100µF, 22µF ×2
1.8
100µF
220µF
10µF ×2
22µF ×1
1.8
100µF
220µF
10µF ×2
22µF ×1
2.5
None
None
10µF ×2
22µF ×1
2.5
100µF
150µF
10µF ×2
22µF ×1
2.5
100µF
150µF
10µF ×2
22µF ×1
3.3
100µF
150µF
10µF ×2
22µF ×1
*Bulk capacitance is optional if VIN has very low input impedance.
ITH
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
VIN
(V)
5
5
3.3
3.3
5
5
3.3
3.3
5
5
3.3
5
5
3.3
5
DROOP PEAK-TO-PEAK RECOVERY LOAD STEP
(mV)
DEVIATION
TIME (µs)
(A/µs)
33
68
11
2.5
25
50
9
2.5
33
68
8
2.5
25
50
10
2.5
30
60
11
2.5
28
60
11
2.5
30
60
10
2.5
27
56
10
2.5
34
68
12
2.5
30
60
12
2.5
30
60
12
2.5
50
90
10
2.5
33
60
10
2.5
50
95
12
2.5
50
90
12
2.5
RFB
(kΩ)
10
10
10
10
5.76
5.76
5.76
5.76
3.92
3.92
3.92
2.37
2.37
2.37
1.62
4615fb
For more information www.linear.com/LTM4615
19
LTM4615
Applications Information
VIN 3V TO 5.5V
C2
10µF
6.3V
C1
10µF
PGOOD1 6.3V
R3
10k
1.2V
FB2
L1*
0.2µH
COMP2
VIN
RUN/SS2
1.2V
R1
4.99k
VIN1
PGOOD1
VOUT1
FB1
COMP1
TRACK1
RUN/SS1
LDO_IN
EN3
BOOST3
GND1
C12
10µF
LTM4615
GND2
*FAIR-RITE 0805 2508056007Y6
IF MORE FILTERING REQUIRED
VIN2
PGOOD2
VOUT2
FB2
COMP2
TRACK2
RUN/SS2
LDO_OUT
FB3
PGOOD3
GND3
PGOOD1
FB2
COMP2
VIN
C5
100µF
6.3V
C6
100µF
6.3V
VOUT2
1.2V
8A
VOUT3 1V LOW NOISE AT 1A
R6
10k
PGOOD3
R5
3.32k
C11
10µF
6.3V
C13
0.01µF
1V
LOW NOISE
4615 F13
Figure 13. LTM4615 Parallel 1.2V at 8A Design, 1V at 1A Design
VIN 5V
C1
10µF
PGOOD1 6.3V
VOUT1
2.5V
4A
R3
10k
SLAVE
C3
22µF
6.3V
C9
22µF
6.3V
3.3V
RTB
4.99k
C4
22µF
6.3V
2.5V
RFB1
2.37k
RTA C12
2.37k 10µF
C1
10µF
6.3V PGOOD2
VIN2
VIN1
PGOOD2
PGOOD1
VOUT1
VOUT2
FB2
FB1
COMP2
COMP1
TRACK2
TRACK1
LTM4615
RUN/SS1
RUN/SS2
LDO_IN
LDO_OUT
EN3
FB3
BOOST3
PGOOD3
GND1
GND3
GND2
R4
10k
MASTER
VIN OR A CONTROL RAMP
VOUT3 1.8V AT 1A
R6
10k
PGOOD3
R5
1.43k
RFB2
1.62k
C6
22µF
6.3V
VOUT2
3.3V
4A
C5
C11 22µF
10µF 6.3V
6.3V
1.8V
4615 F14
Figure 14. 3.3V and 2.5V at 4A with Output Voltage Tracking Design, 1.8V at 1A
20
4615fb
For more information www.linear.com/LTM4615
4
For more information www.linear.com/LTM4615
3.1750
1.9050
3.1750
SUGGESTED PCB LAYOUT
TOP VIEW
0.6350
0.0000
0.6350
PACKAGE TOP VIEW
E
1.9050
PIN “A1”
CORNER
6.9850
5.7150
4.4450
4.4450
5.7150
6.9850
aaa Z
Y
6.9850
5.7150
4.4450
3.1750
1.9050
0.6350
0.0000
0.6350
1.9050
3.1750
4.4450
5.7150
6.9850
X
D
aaa Z
bbb Z
0.27
2.45
MIN
2.72
0.60
NOM
2.82
0.63
15.00
15.00
1.27
13.97
13.97
0.32
2.50
DIMENSIONS
eee S X Y
H1
SUBSTRATE
0.37
2.55
0.15
0.10
0.05
MAX
2.92
0.66
NOTES
DETAIL B
PACKAGE SIDE VIEW
A
TOTAL NUMBER OF LGA PADS: 144
SYMBOL
A
b
D
E
e
F
G
H1
H2
aaa
bbb
eee
DETAIL A
0.630 ±0.025 SQ. 143x
DETAIL B
H2
MOLD
CAP
Z
F
e
b
12
b
11
10
9
3x, C (0.22 x45°)
7
G
6
e
5
PACKAGE BOTTOM VIEW
8
4
3
1
DETAIL A
2
DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
4
7
TRAY PIN 1
BEVEL
!
PACKAGE IN TRAY LOADING ORIENTATION
LTMXXXXXX
µModule
A
B
C
D
E
F
G
H
J
K
L
M
7
SEE NOTES
DIA 0.630
PAD 1
LGA 144 1112 REV C
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
6. THE TOTAL NUMBER OF PADS: 144
5. PRIMARY DATUM -Z- IS SEATING PLANE
BALL DESIGNATION PER JESD MS-028 AND JEP95
3
2. ALL DIMENSIONS ARE IN MILLIMETERS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
COMPONENT
PIN “A1”
3
SEE NOTES
(Reference LTC DWG # 05-08-1816 Rev C)
LGA Package
144-Lead (15mm × 15mm × 2.82mm)
LTM4615
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
4615fb
21
LTM4615
Package Description
LTM4615 Component LGA Pinout
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
A1
GND2
B1
GND2
C1
VIN2
D1
VIN2
E1
GND2
F1
GND3
A2
GND2
B2
SW2
C2
VIN2
D2
VIN2
E2
RUN/SS2
F2
GND3
A3
GND2
B3
SW2
C3
VIN2
D3
VIN2
E3
TRACK2
F3
GND3
A4
GND2
B4
SW2
C4
VIN2
D4
VIN2
E4
PGOOD2
F4
GND3
A5
GND2
B5
SW2
C5
VIN2
D5
VIN2
E5
COMP2
F5
GND3
A6
GND2
B6
SW2
C6
VIN2
D6
GND2
E6
FB2
F6
FB3
A7
GND2
B7
GND2
C7
GND2
D7
GND2
E7
BOOST3
F7
GND3
A8
GND2
B8
GND2
C8
GND2
D8
GND2
E8
GND2
F8
EN3
A9
GND2
B9
GND2
C9
VOUT2
D9
VOUT2
E9
GND2
F9
GND3
A10
GND2
B10
GND2
C10
VOUT2
D10
VOUT2
E10
GND2
F10
GND3
A11
GND2
B11
GND2
C11
VOUT2
D11
VOUT2
E11
VOUT2
F11
GND3
A12
GND2
B12
GND2
C12
VOUT2
D12
VOUT2
E12
VOUT2
F12
GND3
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
G1
LDO_IN
H1
GND1
J1
VIN1
K1
VIN1
L1
GND1
M1
GND1
G2
LDO_IN
H2
SW1
J2
VIN1
K2
VIN1
L2
RUN/SS1
M2
GND1
G3
LDO_IN
H3
SW1
J3
VIN1
K3
VIN1
L3
TRACK1
M3
GND1
G4
LDO_IN
H4
SW1
J4
VIN1
K4
VIN1
L4
PGOOD1
M4
GND1
G5
PGOOD3
H5
SW1
J5
VIN1
K5
VIN1
L5
COMP1
M5
GND1
G6
GND3
H6
SW1
J6
GND1
K6
GND1
L6
FB1
M6
GND1
G7
GND3
H7
GND1
J7
GND1
K7
GND1
L7
GND1
M7
GND1
G8
GND3
H8
GND1
J8
GND1
K8
GND1
L8
GND1
M8
GND1
G9
LDO_OUT
H9
GND1
J9
GND1
K9
VOUT1
L9
VOUT1
M9
VOUT1
G10
LDO_OUT
H10
GND1
J10
GND1
K10
VOUT1
L10
VOUT1
M10
VOUT1
G11
LDO_OUT
H11
GND1
J11
GND1
K11
VOUT1
L11
VOUT1
M11
VOUT1
G12
LDO_OUT
H12
GND1
J12
GND1
K12
VOUT1
L12
VOUT1
M12
VOUT1
22
4615fb
For more information www.linear.com/LTM4615
LTM4615
Revision History
REV
DATE
DESCRIPTION
A
01/12
Added pin functions to the Pin Configuration diagram. Updated EN3 in the Absolute Maximum Ratings section.
Corrected the VOUT accuracy limit.
2
Clarified the SW1 and SW2 electrical connections.
8
B
07/13
PAGE NUMBER
Added the internal power inductor value to the Block Diagram.
9
Clarified the PGOOD behavior.
13
Clarified the reverse current protection behavior.
14
Added the suggested heat sink.
17
Changed “Overcurrent Foldback” to “Overtemperature”
12
4615fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LTM4615
23
LTM4615
Package Photograph
Related Parts
PART NUMBER
DESCRIPTION
COMMENTS
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1.5V ≤ VIN ≤ 5.5V, 0.8V ≤ VOUT ≤ 5V, PLL Input, Remote Sense Amplifier,
VOUT Tracking, 15mm × 15mm × 4.32mm LGA
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15mm × 15mm × 3.42mm BGA
LTM4601A
20V, 12A DC/DC Step-Down μModule Regulator
4.5V ≤ VIN ≤ 20V, 0.6V ≤ VOUT ≤ 5V, PLL Input, Remote Sense Amplifier,
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15mm × 15mm × 3.42mm BGA
LTM8027
60V, 4A DC/DC Step-Down μModule Regulator
4.5V ≤ VIN ≤ 60V, 2.5V ≤ VOUT ≤ 24V, CLK Input, 15mm × 15mm × 4.32mm LGA
LTM8033
36V, 3A EN55022 Class B DC/DC Step-Down
μModule Regulator
3.6V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 24V, Synchronizable,
11.25mm × 15mm × 4.32mm LGA
LTM8061
32V, 2A Step-Down μModule Battery Charger with
Programmable Input Current Limit
Compatible with Single Cell or Dual Cell Li-Ion or Li-Poly Battery Stacks
(4.1V, 4.2V, 8.2V, or 8.4V), 4.95V ≤ VIN ≤ 32V, C/10 or Adjustable Timer Charge
Termination, NTC Resistor Monitor Input, 9mm × 15mm × 4.32mm LGA
24 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTM4615
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
4615fb
LT 0713 REV B • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2009
工商网监
湘ICP备2023018690号
