LTM4620AEY#PBF

LTM4620A Dual 13A or Single 26A DC/DC µModule Regulator DESCRIPTION FEATURES n n n n n n n n n n n n n n n Dual 13A or Single 26A Output Wide Input Voltage Range: 4.5V to 16V Output Voltage Range: 0.6V to 5.3V ±1.5% Maximum Total DC Output Error Multiphase Current Sharing with Multiple LTM4620As Up to 100A Higher Efficiency and Wider VOUT Range Than LTM4620 Differential Remote Sense Amplifier Current Mode Control/Fast Transient Response Adjustable Switching Frequency Overcurrent Foldback Protection Frequency Synchronization Internal Temperature Monitor Output Overvoltage Protection Pin Compatible with the LTM4628 (Dual 8A) and LTM4620 (Dual 13A) Thermally Enhanced (15mm × 15mm × 4.41mm) LGA Package and (15mm × 15mm × 5.01mm) BGA Package The LTM®4620A is a complete dual 13A, or single 26A output switching mode DC/DC power supply with wider VOUT range and higher efficiency than the LTM4620. Included in the package are the switching controller, power FETs, inductors and all supporting components. Operating from an input voltage range of 4.5V to 16V, the LTM4620A supports two outputs each with an output voltage range of 0.6V to 5.3V, set by a single external resistor. Its high efficiency design delivers up to 13A continuous current for each output. Only a few input and output capacitors are needed. The device supports frequency synchronization, multiphase operation, Burst Mode® operation and output voltage tracking for supply rail sequencing and has an onboard temperature diode for device temperature monitoring. High switching frequency and a current mode architecture enable a very fast transient response to line and load changes without sacrificing stability. Fault protection features include overvoltage and overcurrent protection. The power module is offered in a proprietary space saving and thermally enhanced 15mm × 15mm × 4.41mm LGA package and 15mm × 15mm × 5.01mm BGA package. The LTM4620A is available with SnPb (BGA) or RoHS compliant terminal finish. APPLICATIONS Telecom and Networking Equipment Industrial Equipment n n L, LT, LTC, LTM, Linear Technology, the Linear logo, µModule, Burst Mode, LTpowerCAD and PolyPhase are registered trademarks of Analog Devices, Inc. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6304066 and 6580258. Other patents pending. TYPICAL APPLICATION 26A, 5V Output DC/DC µModule® Regulator INTVCC INTVCC VOUT VIN 7V TO 16V 10k* 22µF 25V ×4 MODE_PLLIN CLKOUT INTVCC VIN 120k 5.1V* EXTVCC PGOOD1 VOUT1 VOUTS1 RUN1 DIFFOUT RUN2 SW1 TRACK1 VFB1 LTM4620A 100 PGOOD TEMP TRACK2 0.1µF INTVCC 5V Efficiency vs IOUT 5k VFB2 f SET COMP1 PHASMD COMP2 8.25k VOUT2 100µF 6.3V ×2 SW2 SGND GND DIFFP DIFFN PGOOD2 90 85 VOUTS2 * PULL-UP RESISTOR AND ZENER ARE OPTIONAL 95 100µF 6.3V ×2 220pF EFFICIENCY (%) 4.7µF VOUT 5V 26A 8V TO 5V EFF (650kHz) 12V TO 5V EFF (750kHz) 80 1 3 5 8 10 12 14 16 19 21 23 TOTAL OUTPUT CURRENT (A) 4620A TA01b PGOOD 4620A TA01a For more information www.linear.com/LTM4620A 4620afc 1 LTM4620A ABSOLUTE MAXIMUM RATINGS (Note 1) VIN (Note 8)..................................................–0.3V to 18V VSW1, VSW2.....................................................–1V to 18V PGOOD1, PGOOD2, RUN1, RUN2, INTVCC , EXTVCC........................................... –0.3V to 6V MODE_PLLIN, fSET, TRACK1, TRACK2, DIFFOUT, PHASMD................................ –0.3V to INTVCC VOUT1, VOUT2, VOUTS1, VOUTS2...................... –0.3V to 6V DIFFP, DIFFN.......................................... –0.3V to INTVCC COMP1, COMP2, VFB1, VFB2 (Note 6)......... –0.3V to 2.7V INTVCC Peak Output Current.................................100mA Internal Operating Temperature Range (Note 2) E- and I-Grade.................................... –40°C to 125°C MP-Grade........................................... –55°C to 125°C Storage Temperature Range................... –55°C to 125°C Peak Package Body Temperature (Mount on Top Side of PCB Only).......................... 245°C PIN CONFIGURATION TOP VIEW TOP VIEW TEMP TEMP EXTVCC L L VIN J J PHASMD MODE_PLLIN TRACK1 VFB1 VOUTS1 VIN K K CLKOUT SW1 EXTVCC M M INTVCC SW2 PGOOD1 PGOOD2 RUN2 DIFFOUT DIFFP DIFFN H G RUN1 SGND F GND COMP1 COMP2 E SGND VFB2 TRACK2 D GND CLKOUT SW1 PHASMD MODE_PLLIN TRACK1 VFB1 fSET SGND VOUTS2 C VOUTS1 B VOUT1 G RUN1 SGND F GND COMP1 COMP2 E SGND VFB2 TRACK2 D GND fSET SGND VOUTS2 C B VOUT2 GND INTVCC SW2 PGOOD1 PGOOD2 RUN2 DIFFOUT DIFFP DIFFN H VOUT1 VOUT2 GND A A 1 2 3 4 5 6 7 8 9 10 11 1 12 2 TJMAX = 125°C, θJA = 7°C/W, θJCbottom = 1.5°C/W, θJCtop = 3.7°C/W, θJB + θBA ≅ 7°C/W θ VALUES DEFINED PER JESD 51-12 WEIGHT = 3.037g ORDER INFORMATION 4 5 6 7 8 9 10 11 12 TJMAX = 125°C, θJA = 7°C/W, θJCbottom = 1.5°C/W, θJCtop = 3.7°C/W, θJB + θBA ≅ 7°C/W θ VALUES DEFINED PER JESD 51-12 WEIGHT = 3.232g http://www.linear.com/product/LTM4620A#orderinfo PART MARKING* PART NUMBER LTM4620AEV#PBF 3 BGA PACKAGE 144-LEAD (15mm × 15mm × 5.01mm) LGA PACKAGE 144-LEAD (15mm × 15mm × 4.41mm) PAD OR BALL FINISH Au (RoHS) DEVICE LTM4620AV FINISH CODE e4 PACKAGE TYPE LGA MSL RATING 3 TEMPERATURE RANGE (Note 2) –40°C to 125°C LTM4620AIV#PBF Au (RoHS) LTM4620AV e4 LGA 3 –40°C to 125°C LTM4620AEY#PBF SAC305 (RoHS) LTM4620AY e1 BGA 3 –40°C to 125°C LTM4620AIY#PBF SAC305 (RoHS) LTM4620AY e1 BGA 3 –40°C to 125°C LTM4620AIY SnPb (63/37) LTM4620AY e0 BGA 3 –40°C to 125°C LTM4620AMPY#PBF SAC305 (RoHS) LTM4620AY e1 BGA 3 –55°C to 125°C LTM4620AMPY SnPb (63/37) LTM4620AY Consult Marketing for parts specified with wider operating temperature ranges. *Device temperature grade is indicated by a label on the shipping container. Pad or ball finish code is per IPC/JEDEC J-STD-609. • Terminal Finish Part Marking: www.linear.com/leadfree 2 e0 BGA 3 –55°C to 125°C • Recommended LGA and BGA PCB Assembly and Manufacturing Procedures: www.linear.com/umodule/pcbassembly • LGA and BGA Package and Tray Drawings: www.linear.com/packaging 4620afc For more information www.linear.com/LTM4620A LTM4620A ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal operating temperature range. Specified as each individual output channel. TA = 25°C (Note 2), VIN = 12V and VRUN1, VRUN2 at 5V unless otherwise noted. Per the typical application in Figure 26. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Input DC Voltage 4.5 16 V VOUT Output Voltage (Note 8) l 0.6 5.3 V VOUT1(DC), VOUT2(DC) Output Voltage, Total Variation with Line and Load CIN = 22µF × 3, COUT = 100µF × 1 Ceramic, 220µF POSCAP l 1.477 1.5 1.523 V RUN Pin On/Off Threshold RUN Rising 1.1 1.25 1.40 V l Input Specifications VRUN1, VRUN2 VRUN1HYS , VRUN2HYS RUN Pin On Hysteresis 150 mV IINRUSH(VIN) Input Inrush Current at Start-Up IOUT = 0A, CIN = 22µF ×3, CSS = 0.01µF, COUT = 100µF ×3, VOUT1 = 1.5V, VOUT2 = 1.5V, VIN = 12V 1 A IQ(VIN) Input Supply Bias Current VIN = 12V, VOUT = 1.5V, Burst Mode Operation VIN = 12V, VOUT = 1.5V, Pulse-Skipping Mode VIN = 12V, VOUT= 1.5V, Switching Continuous Shutdown, RUN = 0, VIN = 12V 5 15 65 50 mA mA mA µA IS(VIN) Input Supply Current VIN = 5V, VOUT = 1.5V, IOUT = 13A VIN = 12V, VOUT = 1.5V, IOUT = 13A IOUT1(DC), IOUT2(DC) Output Continuous Current Range VIN = 12V, VOUT = 1.5V (Notes 7, 8) ΔVOUT1(LINE) /VOUT1 ΔVOUT2(LINE) /VOUT2 Line Regulation Accuracy VOUT = 1.5V, VIN from 4.75V to 16V IOUT = 0A for Each Output, l 0.01 0.025 ΔVOUT1/VOUT1 ΔVOUT2 /VOUT2 Load Regulation Accuracy For Each Output, VOUT = 1.5V, 0A to 13A VIN = 12V (Note 7) l 0.35 0.5 4.6 1.853 A A Output Specifications 0 13 A %/V % VOUT1(AC), VOUT2(AC) Output Ripple Voltage For Each Output, IOUT = 0A, COUT = 100µF ×3/ X7R/Ceramic, 470µF POSCAP, VIN = 12V, VOUT = 1.5V, Frequency = 400kHz 15 mVP-P fS (Each Channel) Output Ripple Voltage Frequency VIN = 12V, VOUT = 1.5V, fSET = 1.25V (Note 4) 500 kHz fSYNC (Each Channel) SYNC Capture Range ∆VOUTSTART (Each Channel) Turn-On Overshoot COUT = 100µF/X5R/Ceramic, 470µF POSCAP, VOUT = 1.5V, IOUT = 0A VIN = 12V 10 10 mV mV tSTART (Each Channel) Turn-On Time COUT = 100µF/X5R/Ceramic, 470µF POSCAP, No Load, TRACK/SS with 0.01µF to GND, VIN = 12V 5 5 ms ms ∆VOUT(LS) (Each Channel) Peak Deviation for Dynamic Load Load: 0% to 50% to 0% of Full Load COUT = 22µF ×3/X5R/Ceramic, 470µF POSCAP VIN = 12V, VOUT = 1.5V 30 mV tSETTLE (Each Channel) Settling Time for Dynamic Load Step Load: 0% to 50% to 0% of Full Load, VIN = 12V, COUT = 100µF, 470µF POSCAP 20 µs IOUT(PK) (Each Channel) Output Current Limit VIN = 12V, VOUT = 1.5V 20 A Voltage at VFB Pins IOUT = 0A, VOUT = 1.5V 400 780 kHz Control Section VFB1, VFB2 IFB VOVL l 0.592 0.600 l 0.64 (Note 6) Feedback Overvoltage Lockout 0.606 V –5 –20 nA 0.66 0.68 V 4620afc For more information www.linear.com/LTM4620A 3 LTM4620A ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal operating temperature range. Specified as each individual output channel. TA = 25°C (Note 2), VIN = 12V and VRUN1, VRUN2 at 5V unless otherwise noted. Per the typical application in Figure 26. SYMBOL PARAMETER CONDITIONS TRACK1 (I), TRACK2 (I) Track Pin Soft-Start Pull-Up Current TRACK1 (I),TRACK2 (I) Start at 0V UVLO Undervoltage Lockout VIN Falling VIN Rising tON(MIN) Minimum On-Time (Note 6) RFBHI1, RFBHI2 Resistor Between VOUTS1, VOUTS2 and VFB1, VFB2 Pins for Each Output VPGOOD1, VPGOOD2 Low PGOOD Voltage Low IPGOOD = 2mA IPGOOD PGOOD Leakage Current VPGOOD = 5V VPGOOD PGOOD Trip Level VFB with Respect to Set Output Voltage VFB Ramping Negative VFB Ramping Positive MIN TYP MAX 1 1.25 1.5 3.3 3.9 UVLO Hysteresis 59.90 UNITS µA V V 0.6 V 90 ns 60.4 60.75 0.1 0.3 V ±5 µA –10 10 kΩ % % INTVCC Linear Regulator VINTVCC Internal VCC Voltage 6V < VIN < 16V VINTVCC Load Regulation INTVCC Load Regulation ICC = 0mA to 50mA VEXTVCC EXTVCC Switchover Voltage EXTVCC Ramping Positive VEXTVCC(DROP) EXTVCC Dropout ICC = 20mA, VEXTVCC = 5V VEXTVCC(HYST) EXTVCC Hysteresis 4.8 4.5 5 5.2 V 0.5 2 % 100 mV 4.7 50 V 200 mV Oscillator and Phase-Locked Loop Frequency Nominal Nominal Frequency fSET = 1.2V Frequency Low Lowest Frequency fSET = 0V (Note 5) 210 250 290 kHz Frequency High Highest Frequency fSET > 2.4V, Up to INTVCC 700 780 860 kHz fSET Frequency Set Current 10 11 RMODE_PLLIN MODE_PLLIN Input Resistance CLKOUT Phase (Relative to VOUT1) CLK High CLK Low Clock High Output Voltage Clock Low Output Voltage 450 9 PHASMD = GND PHASMD = Float PHASMD = INTVCC 500 550 kHz µA 250 kΩ 60 90 120 Deg Deg Deg 2 0.2 V V Differential Amplifier AV Differential Amplifier Gain RIN Input Resistance Measured at DIFFP Input VOS Input Offset Voltage VDIFFP = VDIFFOUT = 1.5V, IDIFFOUT = 100µA PSRR Differential Amplifier Power Supply Rejection Ratio 5V < VIN < 16V ICL Maximum Output Current VOUT(MAX) Maximum Output Voltage 4 1 IDIFFOUT = 300µA V 80 kΩ 3 INTVCC – 1.4 mV 90 dB 2 mA V 4620afc For more information www.linear.com/LTM4620A LTM4620A ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal operating temperature range. Specified as each individual output channel. TA = 25°C (Note 2), VIN = 12V and VRUN1, VRUN2 at 5V unless otherwise noted. Per the typical application in Figure 26. SYMBOL PARAMETER GBW Gain Bandwidth Product VTEMP Diode Connected PNP TC Temperature Coefficient CONDITIONS MIN TYP 3 I = 100µA 0.598 l Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTM4620A is tested under pulsed load conditions such that TJ ≈ TA. The LTM4620AE is guaranteed to meet specifications from 0°C to 125°C internal temperature. Specifications over the –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4620AI is guaranteed over the full –40°C to 125°C internal operating temperature range. The LTM4620AMP is tested and guaranteed over the –55°C to 125°C operating temperature range. For output current derating at high temperature, please refer to thermal conditions and output current derating discussion. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. 2.0 MAX UNITS MHz V mV/C Note 3: Two outputs are tested separately and the same testing condition is applied to each output. Note 4: The switching frequency is programmable from 400kHz to 750kHz. Note 5: The LTM4620A is designed to operate from 400kHz to 750kHz Note 6: These parameters are tested at wafer sort. Note 7: See output current derating curves for different VIN, VOUT and TA. Note 8: Output current limitations. For 10V ≤ VIN ≤ 16V, the 5V output current needs to be limited to 12A/channel, switching frequency = 750kHz. Derating curves apply. For 7V ≤ VIN ≤ 9V, the 5V output current needs to be limited to 13A/channel, switching frequency = 750kHz. Derating curves apply. All other input and output combinations are 13A/channel with recommended switching frequency included in the efficiency graphs. Derating curves apply. 4620afc For more information www.linear.com/LTM4620A 5 LTM4620A TYPICAL PERFORMANCE CHARACTERISTICS Efficiency vs Output Current, VIN = 12V 100 95 95 95 90 90 90 85 5V TO 1V (400kHz) 5V TO 1.2V (400kHz) 5V TO 1.5V (400kHz) 5V TO 1.8V (500kHz) 5V TO 2.5V (500kHz) 5V TO 3.3V (500kHz) 80 75 70 1 2.4 3.8 5.2 6.6 8.0 9.4 10.8 12.2 OUTPUT CURRENT (A) 85 8V TO 1V (400kHz) 8V TO 1.2V (400kHz) 8V TO 1.5V (500kHz) 8V TO 1.8V (600kHz) 8V TO 2.5V (650kHz) 8V TO 3.3V (700kHz) 8V TO 5V (750kHz) TIE 5VOUT TO EXTVCC 80 75 70 1 2.4 3.8 5.2 6.6 8.0 9.4 10.8 12.2 OUTPUT CURRENT (A) 4620A G01 EFFICIENCY (%) 100 EFFICIENCY (%) EFFICIENCY (%) 100 Efficiency vs Output Current, VIN = 8V Efficiency vs Output Current, VIN = 5V 85 12V TO 1V (400kHz) 12V TO 1.2V (400kHz) 12V TO 1.5V (500kHz) 12V TO 1.8V (600kHz) 12V TO 2.5V (650kHz) 12V TO 3.3V (700kHz) 12V TO 5V (750kHz) TIE 5VOUT TO EXTVCC 80 75 70 1 4620A G02 12V to 1V Load Step Response 4620A G03 12V to 1.2V Load Step Response 12V to 1.5V Load Step Response 20mV/DIV 20mV/DIV 50mV/DIV 5A/DIV 6A/µs STEP 5A/DIV 6A/µs STEP 5A/DIV 6A/µs STEP 50µs/DIV CFF = 150pF COUT = 2 × 470µF 9mΩ EACH POSCAP 1 × 100µF CERAMIC 4620A G04 50µs/DIV CFF = 150pF COUT = 2 × 470µF 9mΩ EACH POSCAP 1 × 100µF CERAMIC 12V to 1.8V Load Step Response 50mV/DIV 2.4 3.8 5.2 6.6 8.0 9.4 10.8 12.2 OUTPUT CURRENT (A) 4620A G05 50µs/DIV CFF = 47pF COUT = 220µF 9mΩ POSCAP 100µF CERAMIC 12V to 2.5V Load Step Response 4620A G06 12V to 3.3V Load Step Response 50mV/DIV 100mV/DIV 5A/DIV 6A/µs STEP 5A/DIV 6A/µs STEP 50µs/DIV CFF = 33pF COUT = 220µF 9mΩ POSCAP 100µF CERAMIC 6 4620A G07 5A/DIV 6A/µs STEP 50µs/DIV 4620A G08 CFF = 100pF COUT = 220µF 9mΩ POSCAP 100µF CERAMIC 50µs/DIV CFF = 33pF COUT = 100µF 15mΩ POSCAP 100µF CERAMIC 4620A G09 4620afc For more information www.linear.com/LTM4620A LTM4620A TYPICAL PERFORMANCE CHARACTERISTICS 12V to 5V Load Step Response Output Current Sharing 12V to 1.5V Start-Up, No Load 100mV/DIV 5A/DIV 6A/µs STEP 50µs/DIV 4620A G10 CFF = 47pF COUT = 100µF CERAMIC X7R EACH CHANNEL CURRENT (A) 12 11 10 500mV/DIV 9 8 7 6 5 4 10ms/DIV 12VIN, 1.5VOUT AT NO LOAD COUT = 2 × 470µF, 4V SANYO POSCAP, 1 × 100µF, 6.3V CERAMIC SOFT-START CAPACITOR = 0.01µF USE RUN PIN TO CONTROL START-UP 3 2 IOUT1 IOUT2 1 0 2 4 6 8 11 16 19 22 4620A G12 TOTAL OUTPUT CURRENT (A) 4620A G11 12V to 1.5V, 0A Load Short-Circuit Testing Single Phase Start-Up, 13A Load 500mV/DIV 12V to 1.5V, 13A No Load Short-Circuit Testing 500mV/DIV 500mV/DIV 10A/DIV 1A/DIV 10ms/DIV 12VIN, 1.5VOUT AT 13A LOAD COUT = 2 × 470µF, 4V SANYO POSCAP, 1 × 100µF, 6.3V CERAMIC SOFT-START CAPACITOR = 0.01µF USE RUN PIN TO CONTROL START-UP 4620A G13 25ms/DIV 12VIN, 1.5VOUT AT 0A LOAD COUT = 2 × 470µF, 4V SANYO POSCAP, 1 × 100µF, 6.3V X5R CERAMIC SOFT-START CAPACITOR = 0.01µF USE RUN PIN TO CONTROL START-UP 4620A G14 25ms/DIV 12VIN, 1.5VOUT AT 13A LOAD COUT = 2 × 470µF, 4V SANYO POSCAP, 1 × 100µF, 6.3V X5R CERAMIC SOFT-START CAPACITOR = 0.01µF USE RUN PIN TO CONTROL START-UP 4620A G15 4620afc For more information www.linear.com/LTM4620A 7 LTM4620A PIN FUNCTIONS (Recommended to Use Test Points to Monitor Signal Pin Connections.) PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY. VOUT1 (A1-A5, B1-B5, C1-C4): Power Output Pins. Apply output load between these pins and GND pins. Recommend placing output decoupling capacitance directly between these pins and GND pins. Review Table 5. See Note 8 in the Electrical Characteristics section for output current guideline. GND (A6-A7, B6-B7, D1-D4, D9-D12, E1-E4, E10-E12, F1-F3, F10-F12, G1, G3, G10, G12, H1-H7, H9-H12, J1, J5, J8, J12, K1, K5-K8, K12, L1, L12, M1 , M12): Power Ground Pins for Both Input and Output Returns. VOUT2 (A8-A12, B8-B12, C9-C12): Power Output Pins. Apply output load between these pins and GND pins. Recommend placing output decoupling capacitance directly between these pins and GND pins. Review Table 5. See Note 8 in the Electrical Characteristics section for output current guideline. VOUTS1, VOUTS2 (C5, C8): This pin is connected to the top of the internal top feedback resistor for each output. The pin can be directly connected to its specific output, or connected to DIFFOUT when the remote sense amplifier is used. In paralleling modules, one of the VOUTS pins is connected to the DIFFOUT pin in remote sensing or directly to VOUT with no remote sensing. It is very important to connect these pins to either the DIFFOUT or VOUT since this is the feedback path, and cannot be left open. See the Applications Information section. fSET (C6): Frequency Set Pin. A 10µA current is sourced from this pin. A resistor from this pin to ground sets a voltage that in turn programs the operating frequency. Alternatively, this pin can be driven with a DC voltage that can set the operating frequency. See the Applications Information section. SGND (C7, D6, G6-G7, F6-F7): Signal Ground Pin. Return ground path for all analog and low power circuitry. Tie a single connection to the output capacitor GND in the application. See layout guidelines in Figure 25. 8 VFB1, VFB2 (D5, D7): The Negative Input of the Error Amplifier for Each Channel. Internally, this pin is connected to VOUTS1 or VOUTS2 with a 60.4kΩ precision resistor. Different output voltages can be programmed with an additional resistor between VFB and GND pins. In PolyPhase® operation, tying the VFB pins together allows for parallel operation. See the Applications Information section for details. TRACK1, TRACK2 (E5, D8): Output Voltage Tracking Pin and Soft-Start Inputs. Each channel has a 1.3µA pull-up current source. When one channel is configured to be master of the two channels, then a capacitor from this pin to ground will set a soft-start ramp rate. The remaining channel can be set up as the slave, and have the master’s output applied through a voltage divider to the slave output’s track pin. This voltage divider is equal to the slave output’s feedback divider for coincidental tracking. See the Applications Information section. COMP1, COMP2 (E6, E7): Current control threshold and error amplifier compensation point for each channel. The current comparator threshold increases with this control voltage. Tie the COMP pins together for parallel operation. The device is internal compensated. DIFFP (E8): Positive input of the remote sense amplifier. This pin is connected to the remote sense point of the output voltage. Diffamp can be used for ≤3.3V outputs. See the Applications Information section. DIFFN (E9): Negative input of the remote sense amplifier. This pin is connected to the remote sense point of the output GND. Diffamp can be used for ≤3.3V outputs. See the Applications Information section. MODE_PLLIN (F4): Force Continuous Mode, Burst Mode Operation, or Pulse-Skipping Mode Selection Pin and External Synchronization Input to Phase Detector Pin. Connect this pin to SGND to force both channels into force continuous mode of operation. Connect to INTVCC to enable pulse-skipping mode of operation. Leaving the pin floating will enable Burst Mode operation. A clock on the pin will force both channels into continuous mode of operation and synchronized to the external clock applied to this pin. 4620afc For more information www.linear.com/LTM4620A LTM4620A PIN FUNCTIONS (Recommended to Use Test Points to Monitor Signal Pin Connections.) RUN1, RUN2 (F5, F9): Run Control Pin. A voltage above 1.25V will turn on each channel in the module. A voltage below 1.25V on the RUN pin will turn off the related channel. Each RUN pin has a 1µA pull-up current, once the RUN pin reaches 1.2V an additional 4.5µA pull-up current is added to this pin. DIFFOUT (F8): Internal Remote Sense Amplifier Output. Connect this pin to VOUTS1 or VOUTS2 depending on which output is using remote sense. In parallel operation connect one of the VOUTS pin to DIFFOUT for remote sensing. Diffamp can be used for ≤3.3V outputs. SW1, SW2 (G2, G11): Switching node of each channel that is used for testing purposes. Also an R-C snubber network can be applied to reduce or eliminate switch node ringing, or otherwise leave floating. See the Applications Information section. PHASMD (G4): Connect this pin to SGND, INTVCC, or floating this pin to select the phase of CLKOUT to 60 degrees, 120 degrees, and 90 degrees respectively. CLKOUT (G5): Clock output with phase control using the PHASMD pin to enable multiphase operation between devices. See the Applications Information section. INTVCC (H8): Internal 5V Regulator Output. The control circuits and internal gate drivers are powered from this voltage. Decouple this pin to PGND with a 4.7µF low ESR tantalum or ceramic. INTVCC is activated when either RUN1 or RUN2 is activated. TEMP (J6): Onboard Temperature Diode for Monitoring the VBE Junction Voltage Change with Temperature. See the Applications Information section. EXTVCC (J7): External power input that is enabled through a switch to INTVCC whenever EXTVCC is greater than 4.7V. Do not exceed 6V on this input, and connect this pin to VIN when operating VIN on 5V. An efficiency increase will occur that is a function of the (VIN – INTVCC) multiplied by power MOSFET driver current. Typical current requirement is 30mA. VIN must be applied before EXTVCC , and EXTVCC must be removed before VIN. A 5V output can be tied to this pin to increase efficiency. See Applications Information section. VIN (M2-M11, L2-L11, J2-J4, J9-J11, K2-K4, K9-K11): Power Input Pins. Apply input voltage between these pins and GND pins. Recommend placing input decoupling capacitance directly between VIN pins and GND pins. PGOOD1, PGOOD2 (G9, G8): Output Voltage Power Good Indicator. Open drain logic output that is pulled to ground when the output voltage is not within ±7.5% of the regulation point. 4620afc For more information www.linear.com/LTM4620A 9 LTM4620A SIMPLIFIED BLOCK DIAGRAM PGOOD1 TRACK1 VIN SS CAP VIN = 100µA VIN RT CIN1 22µF 25V 1µF GND RT TEMP MTOP1 SW1 CLKOUT 0.56µH RUN1 MODE_PLLIN VOUT1 2.2µF MBOT1 PHASEMD CIN2 22µF 25V + GND VOUT1 1.5V/13A COUT1 VOUTS1 COMP1 60.4k VFB1 INTERNAL COMP SGND RFB1 40.2k POWER CONTROL PGOOD2 TRACK2 SS CAP VIN INTVCC CIN3 22µF 25V 1µF 4.7µF GND EXTVCC MTOP2 SW2 0.56µH RUN2 CIN4 22µF 25V VOUT2 2.2µF MBOT2 GND + VOUT2 1.2V/13A COUT2 VOUTS2 60.4k COMP2 fSET RFSET SGND + – VFB2 RFB2 60.4k INTERNAL COMP INTERNAL FILTER DIFFOUT DIFFN DIFFP 4620A F01 Figure 1. Simplified LTM4620A Block Diagram DECOUPLING REQUIREMENTS TA = 25°C. Use Figure 1 configuration. SYMBOL PARAMETER CONDITIONS CIN1, CIN2 CIN3, CIN4 External Input Capacitor Requirement (VIN1 = 4.75V to 16V, VOUT1 = 1.5V) (VIN2 = 4.75V to 16V, VOUT2 = 1.2V) IOUT1 = 13A IOUT2 = 13A (Note 8) 22 22 µF µF COUT1 COUT2 External Output Capacitor Requirement (VIN1 = 4.75V to 16V, VOUT1 = 1.5V) (VIN2 = 4.75V to 16V, VOUT2 = 1.2V) IOUT1 = 13A IOUT2 = 13A (Note 8) 300 300 µF µF 10 MIN TYP MAX UNITS 4620afc For more information www.linear.com/LTM4620A LTM4620A OPERATION Power Module Description The LTM4620A is a dual-output standalone nonisolated switching mode DC/DC power supply. It can provide two 13A outputs with few external input and output capacitors and setup components. This module provides precisely regulated output voltages programmable via external resistors from 0.6VDC to 5.3VDC over 4.5V to 16V input voltages. The typical application schematic is shown in Figure 26. See Note 8 in the Electrical Characteristics section for output current guideline. The LTM4620A has dual integrated constant-frequency current mode regulators and built-in power MOSFET devices with fast switching speed. The typical switching frequency is 500kHz. For switching-noise sensitive applications, it can be externally synchronized from 400kHz to 780kHz. A resistor can be used to program a free run frequency on the fSET pin. See the Applications Information section. With current mode control and internal feedback loop compensation, the LTM4620A module has sufficient stability margins and good transient performance with a wide range of output capacitors, even with all ceramic output capacitors. Current mode control provides cycle-by-cycle fast current limit and foldback current limit in an overcurrent condition. Internal overvoltage and undervoltage comparators pull the open-drain PGOOD outputs low if the output feedback voltage exits a ±10% window around the regulation point. As the output voltage exceeds 10% above regulation, the bottom MOSFET will turn on to clamp the output voltage. The top MOSFET will be turned off. This overvoltage protect is feedback voltage referred. Pulling the RUN pins below 1.1V forces the regulators into a shutdown state, by turning off both MOSFETs. The TRACK pins are used for programming the output voltage ramp and voltage tracking during start-up or used for soft-starting the regulator. See the Applications Information section. The LTM4620A is internally compensated to be stable over all operating conditions. Table 5 provides a guide line for input and output capacitances for several operating conditions. LTpowerCAD® is available for transient and stability analysis. The VFB pin is used to program the output voltage with a single external resistor to ground. A differential remote sense amplifier is available for sensing the output voltage accurately on one of the outputs at the load point, or in parallel operation sensing the output voltage at the load point. Multiphase operation can be easily employed with the MODE_PLLIN, PHASMD, and CLKOUT pins. Up to 12 phases can be cascaded to run simultaneously with respect to each other by programming the PHMODE pin to different levels. See the Applications Information section. High efficiency at light loads can be accomplished with selectable Burst Mode operation or pulse-skipping operation using the MODE pin. These light load features will accommodate battery operation. Efficiency graphs are provided for light load operation in the Typical Performance Characteristics section. See the Applications Information section for details. A TEMP pin is provided to allow the internal device temperature to be monitored using an onboard diode connected PNP transistor. This diode connected PNP transistor is grounded in the module and can be used as a general temperature monitor using a device that is designed to monitor the single-ended connection. 4620afc For more information www.linear.com/LTM4620A 11 LTM4620A APPLICATIONS INFORMATION The typical LTM4620A application circuit is shown in Figure 26. External component selection is primarily determined by the maximum load current and output voltage. Refer to Table 5 for specific external capacitor requirements for particular applications. VIN to VOUT Step-Down Ratios There are restrictions in the maximum VIN and VOUT stepdown ratio that can be achieved for a given input voltage. Each output of the LTM4620A is capable of 95% duty cycle at 500kHz, but the VIN to VOUT minimum dropout is still shown as a function of its load current and will limit output current capability related to high duty cycle on the top side switch. Minimum on-time tON(MIN) is another consideration in operating at a specified duty cycle while operating at a certain frequency due to the fact that tON(MIN) < D/fSW, where D is duty cycle and fSW is the switching frequency. tON(MIN) is specified in the electrical parameters as 90ns. See Note 8 in the Electrical Characteristics section for output current guideline. Output Voltage Programming The PWM controller has an internal 0.6V reference voltage. As shown in the Block Diagram, a 60.4kΩ internal feedback resistor connects between the VOUTS1 to VFB1 and VOUTS2 to VFB2. It is very important that these pins be connected to their respective outputs for proper feedback regulation. Overvoltage can occur if these VOUTS1 and VOUTS2 pins are left floating when used as individual regulators, or at least one of them is used in paralleled regulators. The output voltage will default to 0.6V with no feedback resistor on either VFB1 or VFB2. Adding a resistor RFB from VFB pin to GND programs the output voltage: VOUT = 0.6V • resistors to the output. All of the VFB pins tie together with one programming resistor as shown in Figure 2. In parallel operation, the VFB pins have an IFB current of 20nA maximum each channel. To reduce output voltage error due to this current, an additional VOUTS pin can be tied to VOUT, and an additional RFB resistor can be used to lower the total Thevenin equivalent resistance seen by this current. For example in Figure 2, the total Thevenin equivalent resistance of the VFB pin is (60.4k//RFB), which is 30.2k where RFB is equal to 60.4k for a 1.2V output. Four phases connected in parallel equates to a worse case feedback current of 4 • IFB = 80nA maximum. The voltage error is 80nA • 30.2k = 2.4mV. If VOUTS2 is connected, as shown in Figure 2, to VOUT, and another 60.4k resistor is connected from VFB2 to ground, then the voltage error is reduced to 1.2mV. If the voltage error is acceptable then no additional connections are necessary. The onboard 60.4k resistor is 0.5% accurate and the VFB resistor can be chosen by the user to be as accurate as needed. All COMP pins are tied together for current sharing between the phases. The TRACK pins can be tied together and a single soft-start capacitor can be used to soft-start the regulator. The soft-start equation will need to have the soft-start current parameter increased by the number of paralleled channels. See TRACK/Soft-Start Pin section. COMP1 LTM4620A VOUT1 COMP2 VOUT2 60.4k TRACK1 1.2V 1.5V 1.8V 2.5V 3.3V 5V RFB Open 90.9k 60.4k 40.2k 30.2k 19.1k 13.3k 8.25k For parallel operation of multiple channels the same feedback setting resistor can be used for the parallel design. This is done by connecting the VOUTS1 to the output as shown in Figure 2, thus tying one of the internal 60.4k 12 60.4k VFB2 TRACK2 COMP1 LTM4620A VOUT1 COMP2 VOUT2 60.4k 1.0V OPTIONAL CONNECTION VFB1 Table 1. VFB Resistor Table vs Various Output Voltages 0.6V VOUTS1 VOUTS2 60.4k + RFB RFB VOUT 4 PARALLELED OUTPUTS FOR 1.2V AT 50A OPTIONAL RFB 60.4k USE TO LOWER TOTAL EQUIVALENT RESISTANCE TO LOWER IFB VOLTAGE ERROR VOUTS1 VOUTS2 VFB1 TRACK1 0.1µF TRACK2 60.4k VFB2 4620A F02 RFB 60.4k Figure 2. 4-Phase Parallel Configurations 4620afc For more information www.linear.com/LTM4620A LTM4620A APPLICATIONS INFORMATION Input Capacitors Output Capacitors The LTM4620A module should be connected to a low AC-impedance DC source. For the regulator input four 22µF input ceramic capacitors are used for RMS ripple current. A 47µF to 100µF surface mount aluminum electrolytic bulk capacitor can be used for more input bulk capacitance. This bulk input capacitor is only needed if the input source impedance is compromised by long inductive leads, traces or not enough source capacitance. If low impedance power planes are used, then this bulk capacitor is not needed. The LTM4620A is designed for low output voltage ripple noise and good transient response. The bulk output capacitors defined as COUT are chosen with low enough effective series resistance (ESR) to meet the output voltage ripple and transient requirements. COUT can be a low ESR tantalum capacitor, the low ESR polymer capacitor or ceramic capacitor. The typical output capacitance range for each output is from 200µF to 470µF. Additional output filtering may be required by the system designer, if further reduction of output ripples or dynamic transient spikes is required. Table 5 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 7A/µs transient. The table optimizes total equivalent ESR and total bulk capacitance to optimize the transient performance. Stability criteria are considered in the Table 5 matrix, and the LTpowerCAD will be provided for stability analysis. Multiphase operation will reduce effective output ripple as a function of the number of phases. Application Note 77 discusses this noise reduction versus output ripple current cancellation, but the output capacitance should be considered carefully as a function of stability and transient response. The LTpowerCAD can calculate the output ripple reduction as the number of implemented phases increases by N times. A small value 10Ω to 50Ω resistor can be place in series from VOUT to the VOUTS pin to allow for a bode plot analyzer to inject a signal into the control loop and validate the regulator stability. The same resistor could be place in series from VOUT to DIFFP and a bode plot analyzer could inject a signal into the control loop and validate the regulator stability. For a buck converter, the switching duty-cycle can be estimated as: D= VOUT VIN Without considering the inductor current ripple, for each output, the RMS current of the input capacitor can be estimated as: IOUT(MAX ) ICIN(RMS) = • D • (1− D) η% In the above equation, η% is the estimated efficiency of the power module. The bulk capacitor can be a switcherrated electrolytic aluminum capacitor, Polymer capacitor. 4620afc For more information www.linear.com/LTM4620A 13 LTM4620A APPLICATIONS INFORMATION Burst Mode Operation Forced Continuous Operation The LTM4620A is capable of Burst Mode operation on each regulator in which the power MOSFETs operate intermittently based on load demand, thus saving quiescent current. For applications where maximizing the efficiency at very light loads is a high priority, Burst Mode operation should be applied. Burst Mode operation is enabled with the MODE/PLLIN pin floating. During this operation, the peak current of the inductor is set to approximately one third of the maximum peak current value in normal operation even though the voltage at the COMP pin indicates a lower value. The voltage at the COMP pin drops when the inductor’s average current is greater than the load requirement. As the COMP voltage drops below 0.5V, the BURST comparator trips, causing the internal sleep line to go high and turn off both power MOSFETs. In applications where fixed frequency operation is more critical than low current efficiency, and where the lowest output ripple is desired, forced continuous operation should be used. Forced continuous operation can be enabled by tying the MODE/PLLIN pin to GND. In this mode, inductor current is allowed to reverse during low output loads, the COMP voltage is in control of the current comparator threshold throughout, and the top MOSFET always turns on with each oscillator pulse. During startup, forced continuous mode is disabled and inductor current is prevented from reversing until the LTM4620A’s output voltage is in regulation. Either regulator can be configured for force continuous mode. In sleep mode, the internal circuitry is partially turned off, reducing the quiescent current to about 450µA for each 22 output. The load current is now being supplied from the output capacitors. When the output voltage drops, causing COMP to rise above 0.5V, the internal sleep line goes low, and the LTM4620A resumes normal operation. The next oscillator cycle will turn on the top power MOSFET and the switching cycle repeats. Either regulator can be configured for Burst Mode operation. For output loads that demand more than 13A of current, two outputs in LTM4620A or even multiple LTM4620As can be paralleled to run out of phase to provide more output current without increasing input and output voltage ripples. The MODE/PLLIN pin allows the LTM4620A to synchronize to an external clock (between 400kHz and 780kHz) and the internal phase-locked-loop allows the LTM4620A to lock onto an incoming clock phase as well. The CLKOUT signal can be connected to the MODE/PLLIN pin of the following stage to line up both the frequency and the phase of the entire system. Tying the PHMODE pin to INTVCC, SGND, or (floating) generates a phase difference (between MODE/PLLIN and CLKOUT) of 120 degrees, 60 degrees, or 90 degrees respectively. A total of 12 phases can be cascaded to run simultaneously with respect to each other by programming the PHMODE pin of each LTM4620A channel to different levels. Figure 3 shows a 2-phase design, 4-phase design and a 6-phase design example for clock phasing with the PHASMD table. Pulse-Skipping Mode Operation In applications where low output ripple and high efficiency at intermediate currents are desired, pulse-skipping mode should be used. Pulse-skipping operation allows the LTM4620A to skip cycles at low output loads, thus increasing efficiency by reducing switching loss. Tying the MODE/PLLIN pin to INTVCC enables pulse-skipping operation. At light loads the internal current comparator may remain tripped for several cycles and force the top MOSFET to stay off for several cycles, thus skipping cycles. The inductor current does not reverse in this mode. This mode will maintain higher effective frequencies thus lower output ripple and lower noise than Burst Mode operation. Either regulator can be configured for pulse-skipping mode. 14 Multiphase Operation A multiphase power supply significantly reduces the amount of ripple current in both the input and output capacitors. The RMS input ripple current is reduced by, and the effective ripple frequency is multiplied by, the number of phases used (assuming that the input voltage 4620afc For more information www.linear.com/LTM4620A LTM4620A APPLICATIONS INFORMATION 2-PHASE DESIGN PHASMD FLOAT CLKOUT 0 PHASE MODE_PLLIN VOUT1 VOUT2 SGND FLOAT CONTROLLER1 0 0 0 CONTROLLER2 180 180 240 CLKOUT 60 90 120 180 PHASE INTVCC PHASMD 4-PHASE DESIGN 90 DEGREE CLKOUT 0 PHASE FLOAT CLKOUT MODE_PLLIN VOUT1 VOUT2 180 PHASE 90 PHASE FLOAT PHASMD MODE_PLLIN VOUT1 VOUT2 270 PHASE PHASMD 6-PHASE DESIGN 60 DEGREE 60 DEGREE CLKOUT 0 PHASE SGND CLKOUT MODE_PLLIN VOUT1 PHASMD VOUT2 180 PHASE 60 PHASE SGND CLKOUT MODE_PLLIN VOUT1 VOUT2 240 PHASE PHASMD 120 PHASE FLOAT MODE_PLLIN VOUT1 VOUT2 300 PHASE PHASMD 4620A F03 Figure 3. Examples of 2-Phase, 4-Phase, and 6-Phase Operation with PHASMD Table is greater than the number of phases used times the output voltage). The output ripple amplitude is also reduced by the number of phases used when all of the outputs are tied together to achieve a single high output current design. The LTM4620A device is an inherently current mode controlled device, so parallel modules will have very good current sharing. This will balance the thermals on the design. Figure 26 shows an example of parallel operation and pin connection. 4620afc For more information www.linear.com/LTM4620A 15 LTM4620A APPLICATIONS INFORMATION Input RMS Ripple Current Cancellation Application Note 77 provides a detailed explanation of multiphase operation. The input RMS ripple current cancellation mathematical derivations are presented, and a graph is displayed representing the RMS ripple current reduction as a function of the number of interleaved phases. Figure 4 shows this graph. Frequency Selection and Phase-Lock Loop (MODE/PLLIN and fSET Pins) The LTM4620A device is operated over a range of frequencies to improve power conversion efficiency. It is recommended to operate the lower output voltages or lower duty cycle conversions at lower frequencies to improve efficiency by lowering power MOSFET switching losses. Higher output voltages or higher duty cycle conversions can be operated at higher frequencies to limit inductor ripple current. The efficiency graphs will show an operating frequency chosen for that condition. Select frequency in reference to the highest output voltage. 0.60 1-PHASE 2-PHASE 3-PHASE 4-PHASE 6-PHASE 0.55 0.50 RMS INPUT RIPPLE CURRENT DC LOAD CURRENT 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 DUTY FACTOR (VOUT/VIN) 4620A F04 Figure 4. Input RMS Current Ratios to DC Load Current as a Function of Duty Cycle 16 4620afc For more information www.linear.com/LTM4620A LTM4620A APPLICATIONS INFORMATION Minimum On-Time 900 Minimum on-time tON is the smallest time duration that the LTM4620A is capable of turning on the top MOSFET on either channel. It is determined by internal timing delays, and the gate charge required turning on the top MOSFET. Low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: 800 FREQUENCY (kHz) 700 600 500 400 300 200 100 0 0 0.5 1 1.5 fSET PIN VOLTAGE (V) 2 2.5 4620A F05 Figure 5. Operating Frequency vs fSET Pin Voltage The LTM4620A switching frequency can be set with an external resistor from the fSET pin to SGND. An accurate 10µA current source into the resistor will set a voltage that programs the frequency or a DC voltage can be applied. Figure 5 shows a graph of frequency setting verses programming voltage. An external clock can be applied to the MODE/ PLLIN pin from 0V to INTVCC over a frequency range of 400kHz to 780kHz. The clock input high threshold is 1.6V and the clock input low threshold is 1V. The LTM4620A has the PLL loop filter components on board. The frequency setting resistor should always be present to set the initial switching frequency before locking to an external clock. Both regulators will operate in continuous mode while being externally clock. The output of the PLL phase detector has a pair of complementary current sources that charge and discharge the internal filter network. When the external clock is applied then the fSET frequency resistor is disconnected with an internal switch, and the current sources control the frequency adjustment to lock to the incoming external clock. When no external clock is applied, then the internal switch is on, thus connecting the external fSET frequency set resistor for free run operation. VOUT > t ON(MIN) VIN • FREQ If the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. The output voltage will continue to be regulated, but the output ripple will increase. The on-time can be increased by lowering the switching frequency. A good rule of thumb is to keep on-time longer than 110ns. Output Voltage Tracking Output voltage tracking can be programmed externally using the TRACK pins. The output can be tracked up and down with another regulator. The master regulator’s output is divided down with an external resistor divider that is the same as the slave regulator’s feedback divider to implement coincident tracking. The LTM4620A uses an accurate 60.4k resistor internally for the top feedback resistor for each channel. Figure 6 shows an example of coincident tracking. Equations:  60.4k   •V SLAVE =  1+  TRACK R TA   VTRACK is the track ramp applied to the slave’s track pin. VTRACK has a control range of 0V to 0.6V, or the internal reference voltage. When the master’s output is divided down with the same resistor values used to set the slave’s output, then the slave will coincident track with the master until it reaches its final value. The master will continue to its final value from the slave’s regulation point. Voltage tracking is disabled when VTRACK is more than 0.6V. RTA in Figure 6 will be equal to the RFB for coincident tracking. Figure 7 shows the coincident tracking waveforms. 4620afc For more information www.linear.com/LTM4620A 17 LTM4620A APPLICATIONS INFORMATION INTVCC INTVCC C10 4.7µF R2 10k PGOOD MODE_PLLIN 7V TO 16V INTERMEDIATE BUS VIN C4 22µF 25V R1* 10k C3 22µF 25V C2 22µF 25V C1 22µF 25V R6 100k CLKOUT INTVCC EXTVCC TEMP VOUTS1 RUN1 SW1 RUN2 VFB1 TRACK1 D1* 5.1V ZENER RTB 60.4k VOUT1 1.5V RTA 60.4k MASTER C6 100µF 6.3V VFB2 LTM4620A TRACK2 CSS 0.1µF PGOOD1 VOUT1 VIN RFB 60.4k COMP1 f SET COMP2 PHASMD VOUTS2 VOUT2 R4 121k PGOOD2 GND DIFFP DIFFN DIFFOUT VOUT1 1.5V AT 13A 40.2k SLAVE SW2 PGOOD SGND C8 470µF 6.3V C5 100µF 6.3V C7 470µF 6.3V VOUT2 1.2V AT 13A INTVCC R9 10k RAMP TIME tSOFTSTART = (CSS /1.3µA) • 0.6 * PULL-UP RESISTOR AND ZENER ARE OPTIONAL 4620A F06 Figure 6. Example of Output Tracking Application Circuit OUTPUT VOLTAGE MASTER OUTPUT SLAVE OUTPUT TIME 4620A F07 Figure 7. Output Coincident Tracking Waveform 18 4620afc For more information www.linear.com/LTM4620A LTM4620A APPLICATIONS INFORMATION The TRACK pin can be controlled by a capacitor placed on the regulator TRACK pin to ground. A 1.3µA current source will charge the TRACK pin up to the reference voltage and then proceed up to INTVCC. After the 0.6V ramp, the TRACK pin will no longer be in control, and the internal voltage reference will control output regulation from the feedback divider. Foldback current limit is disabled during this sequence of turn-on during tracking or soft-starting. The TRACK pins are pulled low when the RUN pin is below 1.2V. The total soft-start time can be calculated as:  C  t SOFT-START =  SS  • 0.6  1.3µA  Regardless of the mode selected by the MODE/PLLIN pin, the regulator channels will always start in pulseskipping mode up to TRACK = 0.5V. Between TRACK = 0.5V and 0.54V, it will operate in forced continuous mode and revert to the selected mode once TRACK > 0.54V. In order to track with another channel once in steady state operation, the LTM4620A is forced into continuous mode operation as soon as VFB is below 0.54V regardless of the setting on the MODE/PLLIN pin. Ratiometric tracking can be achieved by a few simple calculations and the slew rate value applied to the master’s TRACK pin. As mentioned above, the TRACK pin has a control range from 0 to 0.6V. The master’s TRACK pin slew rate is directly equal to the master’s output slew rate in Volts/Time. The equation: MR • 60.4k = R TB SR where MR is the master’s output slew rate and SR is the slave’s output slew rate in Volts/Time. When coincident tracking is desired, then MR and SR are equal, thus RTB is equal the 60.4k. RTA is derived from equation: R TA = 0.6V VFB VFB VTRACK + − 60.4k RFB R TB where VFB is the feedback voltage reference of the regulator, and VTRACK is 0.6V. Since RTB is equal to the 60.4k top feedback resistor of the slave regulator in equal slew rate or coincident tracking, then RTA is equal to RFB with VFB = VTRACK. Therefore RTB = 60.4k, and RTA = 60.4k in Figure 6. In ratiometric tracking, a different slew rate maybe desired for the slave regulator. RTB can be solved for when SR is slower than MR. Make sure that the slave supply slew rate is chosen to be fast enough so that the slave output voltage will reach it final value before the master output. For example, MR = 1.5V/1ms, and SR = 1.2V/1ms. Then RTB = 76.8k. Solve for RTA to equal to 49.9k. Each of the TRACK pins will have the 1.3µA current source on when a resistive divider is used to implement tracking on that specific channel. This will impose an offset on the TRACK pin input. Smaller values resistors with the same ratios as the resistor values calculated from the above equation can be used. For example, where the 60.4k is used then a 6.04k can be used to reduce the TRACK pin offset to a negligible value. Power Good The PGOOD pins are open drain pins that can be used to monitor valid output voltage regulation. This pin monitors a ±10% window around the regulation point. A resistor can be pulled up to a particular supply voltage no greater than 6V maximum for monitoring. Stability Compensation The module has already been internally compensated for all output voltages. Table 5 is provided for most application requirements. The LTpowerCAD will be provided for other control loop optimization. Run Enable The RUN pins have an enable threshold of 1.4V maximum, typically 1.25V with 150mV of hysteresis. They control the turn on each of the channels and INTVCC. These pins can be pulled up to VIN for 5V operation, or a 5V Zener diode can be placed on the pins and a 10k to 100k resistor can be placed up to higher than 5V input for enabling the channels. The RUN pins can also be used for output voltage sequencing. In parallel operation the RUN pins can be tie together 4620afc For more information www.linear.com/LTM4620A 19 LTM4620A APPLICATIONS INFORMATION and controlled from a single control. See the Typical Application circuits in Figure 26. INTVCC and EXTVCC The LTM4620A module has an internal 5V low dropout regulator that is derived from the input voltage. This regulator is used to power the control circuitry and the power MOSFET drivers. This regulator can source up to 70mA, and typically uses ~30mA for powering the device at the maximum frequency. This internal 5V supply is enabled by either RUN1 or RUN2. EXTVCC allows an external 5V supply to power the LTM4620A and reduce power dissipation from the internal low dropout 5V regulator. The power loss savings can be calculated by: (VIN – 5V) • 30mA = PLOSS EXTVCC has a threshold of 4.7V for activation, and a maximum rating of 6V. When using a 5V input, connect this 5V input to EXTVCC also to maintain a 5V gate drive level. EXTVCC must sequence on after VIN, and EXTVCC must sequence off before VIN. When designing a 5V output, connect this 5V output to EXTVCC. Use an external 5V bias on EXTVCC to improve efficiency. Differential Remote Sense Amplifier An accurate differential remote sense amplifier is provided to sense low output voltages accurately at the remote load points. This is especially true for high current loads. The amplifier can be used on one of the two channels, or on a single parallel output. It is very important that the DIFFP and DIFFN are connected properly at the output, and DIFFOUT is connected to either VOUTS1 or VOUTS2. In parallel operation, the DIFFP and DIFFN are connected properly at the output, and DIFFOUT is connected to one of the VOUTS pins. Review the parallel schematics in Figure 29 and review Figure 2. The diffamp can only be used for output voltage ≤3.3V. SW Pins The SW pins are generally for testing purposes by monitoring these pins. These pins can also be used to dampen out switch node ringing caused by LC parasitic in the 20 switched current paths. Usually a series R-C combination is used called a snubber circuit. The resistor will dampen the resonance and the capacitor is chosen to only affect the high frequency ringing across the resistor. If the stray inductance or capacitance can be measured or approximated then a somewhat analytical technique can be used to select the snubber values. The inductance is usually easier to predict. It combines the power path board inductance in combination with the MOSFET interconnect bond wire inductance. First the SW pin can be monitored with a wide bandwidth scope with a high frequency scope probe. The ring frequency can be measured for its value. The impedance Z can be calculated: Z(L) = 2πfL, where f is the resonant frequency of the ring, and L is the total parasitic inductance in the switch path. If a resistor is selected that is equal to Z, then the ringing should be dampened. The snubber capacitor value is chosen so that its impedance is equal to the resistor at the ring frequency. Calculated by: Z(C) = 1/(2πfC). These values are a good place to start with. Modification to these components should be made to attenuate the ringing with the least amount of power loss. Temperature Monitoring (TEMP) A diode connected PNP transistor is used for the TEMP monitor function by monitoring its voltage over temperature. The temperature dependence of this diode can be understood in the equation: D = nVTIn ID ,  IS Where VT is the thermal voltage (kT/q), and n, the ideality factor is 1 for the two diode connected PNPs being used in the LTM4620. Since ID has an exponential temperature dependence that can be understood from the typical empirical equation for IS: IS = I0 exp (–VG0/VT), Where Io is some process and geometry dependent current (Io is typically around 20 orders of magnitude larger than IS at room temperature, so Io is much larger than typical 4620afc For more information www.linear.com/LTM4620A LTM4620A APPLICATIONS INFORMATION If we take the IS equation and substitute into the VD equation, then we get: The expression shows that the junction voltage of the PNP connected diode decreases linearly if Io were constant from a value VG0 of 1.2V at absolute zero to a decreasing value with increased temperature. If we take this equation and differentiate it with respect to temperature T, then: This dVD dT change as a function of temperature is the typical ~–2mV/°C. This equation is simplified for the first order derivation. Solving for T, T = –(VG0 – VD)/ dVD provide the temperature. 1st Example: Figure 4 for 27°C, or 300°C Kelvin the diode voltage is 0.598V, thus, 300°C = –(1200mV – 598mV)/ –2mV/°C) 2nd Example: Figure 4 for 75°C, or 350°C Kelvin the diode voltage is 0.50V, thus, 350°C = –(1200mV – 500mV)/ –2mV/°C) Converting the Kelvin scale to Celsius is simply taking the Kelvin temp and subtracting –273°C Kelvin from it. A typical forward voltage is measured and placed in the electrical characteristics section of the data sheet, and Figure 8 is the plot of this forward voltage. Measure this forward voltage at 27°C to establish a reference point. Then use the above expression while measuring the ID = 100µA 0.7 0.6 0.5 0.4 0.3 –50  Kt  I0  kT ln VD = VG0 – , VT =  q   ID  q dVD = – ( VG0 – VD) / T dT 0.8 TEMP PIN DIODE VOLTAGE (V) values of ID), and VG0 is the band gap voltage of 1.2V extrapolated to absolute zero of –273°C Kelvin. Figure 8 shows a plot of the diode temperature characteristic of the diode connected PNP transistor biased with a 100µA current source. This plot would extend to the left back to 1.2V at –273°C Kelvin. This curve is stop at –55°C due to the test system limits. –25 50 25 0 75 TEMPERATURE (°C) 100 125 4620A F08 Figure 8. Diode Voltage VD vs Temperature T(°C) for Different Bias Currents forward voltage over temperature will provide a general temperature monitor. The diode connected PNP transistor can be pulled up to VIN with a resistor to set the current to 100µA for using this diode connected transistor as a general temperature monitor by monitoring the diode voltage drop with temperature. See Figure 27 for an example. Thermal Considerations and Output Current Derating The thermal resistances reported in the Pin Configuration section of the data sheet are consistent with those parameters defined by JESD 51-9 and are intended for use with finite element analysis (FEA) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation performed on a µModule package mounted to a hardware test board— also defined by JESD 51-9 (“Test Boards for Area Array Surface Mount Package Thermal Measurements”). The motivation for providing these thermal coefficients in found in JESD 51-12 (“Guidelines for Reporting and Using Electronic Package Thermal Information”). Many designers may opt to use laboratory equipment and a test vehicle such as the demo board to anticipate the µModule regulator’s thermal performance in their application at various electrical and environmental operating 4620afc For more information www.linear.com/LTM4620A 21 LTM4620A APPLICATIONS INFORMATION conditions to compliment any FEA activities. Without FEA software, the thermal resistances reported in the Pin Configuration section are in-and-of themselves not relevant to providing guidance of thermal performance; instead, the derating curves provided in the data sheet can be used in a manner that yields insight and guidance pertaining to one’s application-usage, and can be adapted to correlate thermal performance to one’s own application. The Pin Configuration section typically gives four thermal coefficients explicitly defined in JESD 51-12; these coefficients are quoted or paraphrased below: 1. θJA, the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclosure. This environment is sometimes referred to as “still air” although natural convection causes the air to move. This value is determined with the part mounted to a JESD 51-9 defined test board, which does not reflect an actual application or viable operating condition. 2. θJCbottom, the thermal resistance from junction to the bottom of the product case, is the junction-to-board thermal resistance with all of the component power dissipation flowing through the bottom of the package. In the typical µModule, the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient environment. As a result, this thermal resistance value may be useful for comparing packages but the test conditions don’t generally match the user’s application. 3. θJCtop, the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top 22 of the package. As the electrical connections of the typical µModule are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. As in the case of θJCbottom, this value may be useful for comparing packages but the test conditions don’t generally match the user’s application. 4. θJB, the thermal resistance from junction to the printed circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the µModule and into the board, and is really the sum of the θJCbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. The board temperature is measured a specified distance from the package, using a two sided, two layer board. This board is described in JESD 51-9. A graphical representation of the aforementioned thermal resistances is given in Figure 9; blue resistances are contained within the µModule regulator, whereas green resistances are external to the µModule. As a practical matter, it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by JESD 51-12 or provided in the Pin Configuration section replicates or conveys normal operating conditions of a µModule. For example, in normal board-mounted applications, never does 100% of the device’s total power loss (heat) thermally conduct exclusively through the top or exclusively through bottom of the µModule—as the standard defines for θJCtop and θJCbottom, respectively. In practice, power loss is thermally dissipated in both directions away from the package—granted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board. 4620afc For more information www.linear.com/LTM4620A LTM4620A APPLICATIONS INFORMATION Within a SIP (system-in-package) module, be aware there are multiple power devices and components dissipating power, with a consequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. To reconcile this complication without sacrificing modeling simplicity—but also, not ignoring practical realities—an approach has been taken using FEA software modeling along with laboratory testing in a controlled-environment chamber to reasonably define and correlate the thermal resistance values supplied in this data sheet: (1) Initially, FEA software is used to accurately build the mechanical geometry of the µModule and the specified PCB with all of the correct material coefficients along with accurate power loss source definitions; (2) this model simulates a software-defined JEDEC environment consistent with JESD 51-9 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the JEDEC-defined thermal resistance values; (3) the model and FEA software is used to evaluate the µModule with heat sink and airflow; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled-environment chamber while operating the device at the same power loss as that which was simulated. An outcome of this process and due-diligence yields a set of derating curves provided in other sections of this data sheet. After these laboratory test have been performed and correlated to the µModule model, then the θJB and θBA are summed together to correlate quite well with the µModule model with no airflow or heat sinking in a properly define chamber. This θJB + θBA value is shown in the Pin Configuration section and should accurately equal the θJA value because approximately 100% of power loss flows from the junction through the board into ambient with no airflow or top mounted heat sink. Each system has its own thermal characteristics, therefore thermal analysis must be performed by the user in a particular system. JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD) JUNCTION-TO-CASE (TOP) RESISTANCE CASE (TOP)-TO-AMBIENT RESISTANCE JUNCTION-TO-BOARD RESISTANCE JUNCTION CASE (BOTTOM)-TO-BOARD JUNCTION-TO-CASE (BOTTOM) RESISTANCE RESISTANCE AMBIENT BOARD-TO-AMBIENT RESISTANCE 4620A F10 µMODULE DEVICE Figure 9. Graphical Representation of JESD 51-12 Thermal Coefficients 4620afc For more information www.linear.com/LTM4620A 23 LTM4620A APPLICATIONS INFORMATION The LTM4620A module has been designed to effectively remove heat from both the top and bottom of the package. The bottom substrate material has very low thermal resistance to the printed circuit board and the exposed top metal is thermally connected to the power devices and the power inductors. An external heat sink can be applied to the top of the device for excellent heat sinking with airflow. Basically all power dissipating devices are mounted directly to the substrate and the top exposed metal. This provides two low thermal resistance paths to remove heat. Figure 10 shows a temperature plot of the LTM4620A with BGA heat sink and 200LFM airflow with ~5.3W of internal dissipation. Figure 10. LTM4620A 12V to 1.2V at 26A with 200LFM Airflow Figure 11 shows a temperature plot of the LTM4620A with no heat sink and 200LFM airflow with ~6.5W of internal dissipation. These plots equate to a paralleled 1.2V at 26A design, and a 5V at 25A design operating from a 12V input. Safety Considerations The LTM4620A modules do not provide isolation from VIN to VOUT. There is no internal fuse. If required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. The fuse or circuit breaker should be selected to limit the current to the regulator during overvoltage in case of an internal top MOSFET fault. If the internal top MOSFET fails, then turning it off will not resolve the overvoltage, thus the internal bottom MOSFET will turn on indefinitely trying to protect the load. Under this fault condition, the input voltage will source very large currents to ground through the failed internal top MOSFET and enabled internal bottom MOSFET. This can cause excessive heat and board damage depending on how much power the input voltage can deliver to this system. A fuse or circuit breaker can be used as a secondary fault protector in this situation. 24 Figure 11. LTM4620A 12V to 5V at 25A with 200LFM Airflow 4620afc For more information www.linear.com/LTM4620A LTM4620A APPLICATIONS INFORMATION The device does support over current protection. A temperature diode is provided for monitoring internal temperature, and can be used to detect the need for thermal shutdown that can be done by controlling the RUN pin. Power Derating The 1V, 2.5V and 5V power loss curves in Figures 12 to 14 can be used in coordination with the load current derating curves in Figures 15 to 24 for calculating an approximate θJA thermal resistance for the LTM4620A with various heat sinking and airflow conditions. The power loss curves are taken at room temperature, and are increased with a 1.35 to 1.4 multiplicative factor at 125°C. These factors come from the fact that the power loss of the regulator increases about 45% from 25°C to 150°C, thus a 45% spread over 125°C delta equates to ~0.35%/°C loss increase. A 125°C maximum junction minus 25°C room temperature equates to a 100°C increase. This 100°C increase multiplied by 0.35%/°C equals a 35% power loss increase at the 125°C junction, thus the 1.35 multiplier. The derating curves are plotted with CH1 and CH2 in parallel single output operation starting at 26A of load with low ambient temperature. The output voltages are 1V, 2.5V and 5V. These are chosen to include the lower and higher output voltage ranges for correlating the thermal resistance. Thermal models are derived from several temperature measurements in a controlled temperature chamber along with thermal modeling analysis. The junction temperatures are monitored while ambient temperature is increased with and without airflow. The power loss increase with ambient temperature change is factored into the derating curves. The junctions are maintained at ~120°C maximum while lowering output current or power while increasing ambient temperature. The decreased output current will decrease the internal module loss as ambient temperature is increased. The monitored junction temperature of 120°C minus the ambient operating temperature specifies how much module temperature rise can be allowed. As an example in Figure 15, the load current is derated to ~19A at ~80°C with no air or heat sink and the power loss for the 12V to 1.0V at 19A output is a ~5.1W loss. The 5.1W loss is calculated with the ~3.75W room temperature loss from the 12V to 1.0V power loss curve at 19A, and the 1.35 multiplying factor at 125°C ambient. If the 80°C ambient temperature is subtracted from the 120°C junction temperature, then the difference of 40°C divided 5.1W equals a 7.8°C/W θJA thermal resistance. Table 2 specifies a 6.5 to 7°C/W value which is pretty close. The airflow graphs are more accurate due to the fact that the ambient temperature environment is controlled better with airflow. As an example in Figure 16, the load current is derated to ~22A at ~90°C with 200LFM of airflow and the power loss for the 12V to 1.0V at 22A output is a ~5.94W loss. The 5.94W loss is calculated with the ~4.4W room temperature loss from the 12V to 1.0V power loss curve at 22A, and the 1.35 multiplying factor at 125°C ambient. If the 90°C ambient temperature is subtracted from the 120°C junction temperature, then the difference of 30°C divided 5.94W equals a 5.1°C/W θJA thermal resistance. Table 2 specifies a 5.5°C/W value which is pretty close. Tables 2-4 provide equivalent thermal resistances for 1.0V, 2.5V and 5V outputs with and without airflow and heat sinking. The derived thermal resistances in Tables 2-4 for the various conditions can be multiplied by the calculated power loss as a function of ambient temperature to derive temperature rise above ambient, thus maximum junction temperature. Room temperature power loss can be derived from the efficiency curves and adjusted with the above ambient temperature multiplicative factors. The printed circuit board is a 1.6mm thick four layer board with two ounce copper for the two outer layers and one ounce copper for the two inner layers. The PCB dimensions are 101mm × 114mm. The BGA heat sinks are listed below Table 4. 4620afc For more information www.linear.com/LTM4620A 25 LTM4620A APPLICATIONS INFORMATION Table 2. 1.0V Output VIN (V) 5, 12 5, 12 5, 12 5, 12 5, 12 5, 12 POWER LOSS CURVE Figure 12 Figure 12 Figure 12 Figure 12 Figure 12 Figure 12 AIRFLOW (LFM) 0 200 400 0 200 400 HEAT SINK None None None BGA Heat Sink BGA Heat Sink BGA Heat Sink LGA θJA (°C/W) 6.5 to 7 5.5 5 6.5 5 4 BGA θJA (°C/W) 6.5 to 7 5.5 5 6.5 5 4 VIN (V) 5, 12 5, 12 5, 12 5, 12 5, 12 5, 12 POWER LOSS CURVE Figure 13 Figure 13 Figure 13 Figure 13 Figure 13 Figure 13 AIRFLOW (LFM) 0 200 400 0 200 400 HEAT SINK None None None BGA Heat Sink BGA Heat Sink BGA Heat Sink LGA θJA (°C/W) 6.5 to 7 5.5 to 6 4.5 6.5 to 7 4 3.5 BGA θJA (°C/W) 6.5 to 7 5.5 to 6 4.5 6.5 to 7 4 3.5 DERATING CURVE VIN (V) POWER LOSS CURVE Figure 23 12 Figure 14 Figure 23 12 Figure 14 Figure 23 12 Figure 14 Figure 24 12 Figure 14 Figure 24 12 Figure 14 Figure 24 12 Figure 14 Connect 5V output to EXTVCC to increase efficiency. AIRFLOW (LFM) 0 200 400 0 200 400 HEAT SINK None None None BGA Heat Sink BGA Heat Sink BGA Heat Sink LGA θJA (°C/W) 6.5 to 7 5.5 to 6 4.5 6.5 to 7 4 3.5 BGA θJA (°C/W) 6.5 to 7 5.5 to 6 4.5 6.5 to 7 4 3.5 DERATING CURVE Figures 15, 16 Figures 15, 16 Figures 15, 16 Figures 17, 18 Figures 17, 18 Figures 17, 18 Table 3. 2.5V Output DERATING CURVE Figures 19, 20 Figures 19, 20 Figures 19, 20 Figures 21, 22 Figures 21, 22 Figures 21, 22 Table 4. 5V Output HEAT SINK MANUFACTURER PART NUMBER Aavid Thermalloy 375424B00034G www.aavid.com Cool Innovations 4-050503P 4-050508P www.coolinnovations.com 26 WEBSITE 4620afc For more information www.linear.com/LTM4620A LTM4620A APPLICATIONS INFORMATION Table 5. Output Voltage Response vs Component Matrix (Refer to Figure 23) 0A to 7A Load Step Typical Measured Values VENDORS TDK, COUT1 Ceramic Murata, COUT1 Ceramic AVX, COUT1 Ceramic VALUE 100µF 6.3V 100µF 6.3V 100µF 6.3V PART NUMBER C4532X5R0J107MZ GRM32ER60J107M 18126D107MAT ESR ~1mΩ ~1mΩ ~1mΩ Sanyo POSCAP, COUT2 Bulk 470µF 2R5 2R5TPD470M5 9mΩ 9mΩ Sanyo POSCAP, COUT2 Bulk 470µF 6.3V 6TPD470M Sanyo, CIN Bulk 56µF 25V 25SVP56M Sanyo, POSCAP COUT2 Bulk 100µF 6.3V 67PE100MI Sanyo, POSCAP COUT2 Bulk 220µF 2.5V 2R5TPE220M9 Sanyo, POSCAP COUT2 Bulk 220µF 6V 6TPF220ML VOUT CIN COUT1 COUT2 CFF CBOT CIN (pF) (pF) (V) (CERAMIC) (BULK)** (CERAMIC) (BULK) 1 22µF × 3 56µF 100µF 470µF × 2 None None 1 22µF × 3 56µF 100µF 470µF × 2 150 None 1 22µF × 3 56µF 100µF × 3 470µF 100 None 1.2 22µF × 3 56µF 100µF × 3 470µF 100 None 1.2 22µF × 3 56µF 100µF 470µF × 2 150 1.2 22µF × 3 56µF 100µF 470µF × 2 150 1.5 22µF × 3 56µF 100µF 470µF × 2 220 None 1.5 22µF × 3 56µF 100µF 470µF × 2 220 1.5 22µF × 3 56µF 100µF 220µF 47 1.8 22µF × 3 56µF 100µF 220µF 33 1.8 22µF × 3 56µF 100µF 220µF 33 1.8 22µF × 3 56µF 100µF × 3 None 100 2.5 22µF × 3 56µF 100µF × 3 None 150 None 2.5 22µF × 3 56µF 100µF × 3 None 150 None 3.3 22µF × 3 56µF 100µF 100µF 33 3.3 22µF × 3 56µF 100µF × 2 100 5 22µF × 3 56µF 100µF 47 5 22µF × 3 56µF 100µF **Bulk capacitance is optional if VIN has very low input impedance. CCOMP (pF) None None None None 47 47 VIN (V) 5 12 12 12 5 12 5 12 12 12 5 12 12 12 12 12 12 12 15mΩ to 18mΩ P-P DEVIATION RECOVERY LOAD DROOP AT 6A LOAD TIME STEP (mV) STEP (mV) (µs) (A/µs) 24 46 30 6 24 46 30 6 33 63 23 6 35 70 23 6 24 46 25 6 24 46 25 6 26 52 40 6 26 52 40 6 64 120 20 6 61 120 20 6 61 120 20 6 80 160 18 6 60 120 20 6 60 120 20 6 118 240 30 6 120 240 20 6 188 382 25 6 180 360 20 6 RFB (kΩ) 90.9 90.9 90.9 60.4 60.4 60.4 40.2 40.2 40.2 30.2 30.2 30.2 19.1 19.1 13.3 13.3 8.25 8.25 FREQ 400 400 400 500 500 500 550 550 500 600 600 600 650 650 700 700 750 750 4620afc For more information www.linear.com/LTM4620A 27 LTM4620A APPLICATIONS INFORMATION 5 4 3 2 1 8 12V TO 1V POWER LOSS CURVE 5V TO 1V POWER LOSS CURVE 6 POWER LOSS (W) POWER LOSS (W) 6 0 7 12V TO 2.5V POWER LOSS CURVE 5V TO 2.5V POWER LOSS CURVE 6 5 4 3 2 0 2 3 5 6 8 9 10 12 13 15 16 17 19 20 22 23 24 26 0 3 5 6 8 9 10 12 13 15 16 17 19 20 22 23 24 26 LOAD CURRENT (A) 4620A F13 Figure 13. 1V Power Loss Curve LOAD CURRENT (A) Figure 12. 2.5V Power Loss Curve LOAD CURRENT (A) 3 LOAD CURRENT (A) 4620A F12 400LFM 200LFM 0LFM 0 4 1 LOAD CURRENT (A) 26 24 22 20 18 16 14 12 10 8 6 4 2 0 5 2 1 2 3 5 6 8 9 10 12 13 15 16 17 19 20 22 23 24 26 12V TO 5V POWER LOSS CURVE 7 POWER LOSS (W) 7 80 20 40 60 100 AMBIENT TEMPERATURE (°C) 120 26 24 22 20 18 16 14 12 10 8 6 4 2 0 4620A F14 Figure 14. 5V Power Loss Curve 400LFM 200LFM 0LFM 0 80 20 40 60 100 AMBIENT TEMPERATURE (°C) 4620A F16 4620A F15 Figure 16. 5V to 1V Derating Curve, No Heat Sink CH1 AND CH2 COMBINED LOAD CURRENT (A) LOAD CURRENT (A) Figure 15. 12V to 1V Derating Curve, No Heat Sink 26 24 22 20 18 16 14 12 10 8 6 4 2 0 400LFM 200LFM 0LFM 0 80 20 40 60 100 AMBIENT TEMPERATURE (°C) 120 120 26 24 22 20 18 16 14 12 10 8 6 4 2 0 400LFM 200LFM 0LFM 0 80 20 40 60 100 AMBIENT TEMPERATURE (°C) 120 4620A F18 4620A F17 Figure 17. 12V to 1V Derating Curve, BGA Heat Sink 28 Figure 18. 5V to 1V Derating Curve, BGA Heat Sink 4620afc For more information www.linear.com/LTM4620A LTM4620A 30 30 25 25 LOAD CURRENT (A) LOAD CURRENT (A) APPLICATIONS INFORMATION 20 15 10 400LFM 200LFM 0LFM 5 0 0 20 20 15 10 400LFM 200LFM 0LFM 5 80 100 120 40 60 AMBIENT TEMPERATURE (°C) 0 140 0 20 80 100 120 40 60 AMBIENT TEMPERATURE (°C) 4620A F19 4620A F20 Figure 20. 5V to 2.5V Derating Curve, No Heat Sink 30 30 25 25 LOAD CURRENT (A) LOAD CURRENT (A) Figure 19. 12V to 2.5V Derating Curve, No Heat Sink 20 15 10 400LFM 200LFM 0LFM 5 0 0 20 20 15 10 400LFM 200LFM 0LFM 5 80 100 120 40 60 AMBIENT TEMPERATURE (°C) 0 140 0 20 80 100 120 40 60 AMBIENT TEMPERATURE (°C) 4620A F21 30 25 25 LOAD CURRENT (A) LOAD CURRENT (A) Figure 22. 5V to 2.5V Derating Curve, with Heat Sink 30 20 15 10 0 400LFM 200LFM 0LFM 0 20 15 10 400LFM 200LFM 0LFM 5 80 20 40 60 100 AMBIENT TEMPERATURE (°C) 120 0 0 80 20 40 60 100 AMBIENT TEMPERATURE (°C) 4620A F23 Figure 23. 12V to 5V Derating Curve, No Heat Sink 140 4620A F22 Figure 21. 12V to 2.5V Derating Curve, with Heat Sink 5 140 120 4620A F24 Figure 24. 12V to 5V Derating Curve, with Heat Sink 4620afc For more information www.linear.com/LTM4620A 29 LTM4620A APPLICATIONS INFORMATION Layout Checklist/Example The high integration of LTM4620A makes the PCB board layout very simple and easy. However, to optimize its electrical and thermal performance, some layout considerations are still necessary. • Use large PCB copper areas for high current paths, including VIN, GND, VOUT1 and VOUT2. It helps to minimize the PCB conduction loss and thermal stress. • Place high frequency ceramic input and output capacitors next to the VIN, PGND and VOUT pins to minimize high frequency noise. • Place a dedicated power ground layer underneath the unit. • Do not put via directly on the pad, unless they are capped or plated over. • Use a separated SGND ground copper area for components connected to signal pins. Connect the SGND to GND underneath the unit. • For parallel modules, tie the VOUT, VFB, and COMP pins together. Use an internal layer to closely connect these pins together. The TRACK pin can be tied a common capacitor for regulator soft-start. • Bring out test points on the signal pins for monitoring. Figure 25 gives a good example of the recommended layout. • To minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. 30 4620afc For more information www.linear.com/LTM4620A LTM4620A APPLICATIONS INFORMATION LGA CIN1 CIN2 VIN M L K GND GND J H G COUT1 SGND F COUT2 E D C B A 1 2 3 4 5 6 VOUT1 7 8 9 10 11 12 GND VOUT2 4620A F25A CNTRL CNTRL BGA CIN1 CIN2 VIN M L K GND GND J H G COUT1 SGND F COUT2 E D C B A 1 2 3 4 5 VOUT1 6 7 8 9 10 11 12 GND VOUT2 4620A F25b CNTRL CNTRL Figure 25. Recommended PCB Layout 4620afc For more information www.linear.com/LTM4620A 31 VIN + CIN (OPT) C4 22µF 25V 32 C2 22µF 25V C9 0.1µF TRACK2 C1 22µF 25V R4 121k R7 100k For more information www.linear.com/LTM4620A DIFFN VFB2 TRACK1 SGND VOUTS2 PHASMD PGOOD2 DIFFOUT SW2 VOUT2 COMP2 fSET DIFFP VFB1 RUN2 COMP1 SW1 RUN1 TRACK2 VOUTS1 TEMP GND EXTVCC PGOOD1 VOUT1 LTM4620A CLKOUT INTVCC R2 10k VIN MODE_PLLIN C10 4.7µF INTVCC Figure 26. Typical 5VIN to 16VIN, 1.5V and 1.2V Outputs *PULL-UP RESISTOR AND ZENER ARE OPTIONAL **SEE TABLE 5 D1* TRACK1 5.1V ZENER C5 0.1µF R1* 10k C3 22µF 25V 5V TO 16V INTERMEDIATE BUS INTVCC INTVCC R3 10k PGOOD2 CCOMP** PGOOD1 COUT3 100µF 6.3V 100pF RFB2** 60.4k COUT1 100µF 6.3V + CBOT** COUT4 470µF 6.3V ×2 4620A F26 VOUT2 1.2V AT 13A RFB1** 40.2k + CFF** 220pF VOUT1 1.5V COUT2 13A 470µF 6.3V ×2 LTM4620A APPLICATIONS INFORMATION 4620afc For more information www.linear.com/LTM4620A C3 22µF 25V D1* 5.1V ZENER R1* 10k 100µA VIN – 0.6V TRACK1 C11 22µF 25V C2 22µF 25V RT SGND DIFFN VOUTS2 DIFFOUT PGOOD2 SW2 VOUT2 COMP2 PHASMD COMP1 fSET TRACK2 DIFFP VFB1 RUN2 VFB2 SW1 RUN1 TRACK1 VOUT1 VOUTS1 GND EXTVCC PGOOD1 R2 5k INTVCC TEMP LTM4620A CLKOUT INTVCC 5V C10 4.7µF VIN MODE_PLLIN INTVCC PGOOD1 R5 8.25k PGOOD1 Figure 27. LTM4620A 2-Phase, 5V at 20A Design with Temperature Monitoring C9 INTVCC 0.1µF C1 22µF 25V 7V TO 16V INTERMEDIATE BUS * PULL-UP RESISTOR AND ZENER ARE OPTIONAL VIN A/D RT = VIN COUT3 100µF 6.3V COUT1 100µF 6.3V + + 4620A F27 COUT4 220µF 10V COUT2 220µF 10V VOUT 5V 26A LTM4620A TYPICAL APPLICATIONS 4620afc 33 VIN 34 For more information www.linear.com/LTM4620A R1* 10k R9 60.4k C2 22µF 25V VOUT1 3.3V C5 0.1µF C3 22µF 25V R7 90.9k C1 22µF 25V INTVCC R6 100k R2 10k DIFFN VFB2 TRACK1 SGND VOUTS2 PHASMD DIFFOUT PGOOD2 SW2 VOUT2 COMP2 fSET DIFFP VFB1 GND SW1 RUN2 COMP1 VOUTS1 RUN1 TRACK2 VOUT1 VIN TEMP LTM4620A CLKOUT INTVCC EXTVCC PGOOD1 C10 4.7µF INTVCC Figure 28. LTM4620A 3.3V and 2.5V Output Tracking * PULL-UP RESISTOR AND ZENER ARE OPTIONAL D1* 5.1V ZENER C4 22µF 25V 5V TO 16V INTERMEDIATE BUS MODE_PLLIN INTVCC 33pF INTVCC R3 10k PGOOD2 R8 19.1k PGOOD1 COUT3 100µF 6.3V R5 13.3k COUT1 100µF 6.3V + + COUT4 220µF 6.3V COUT2 100µF 6.3V 4620A F28 VOUT2 2.5V 13A 100pF VOUT1 3.3V 13A LTM4620A TYPICAL APPLICATIONS 4620afc LTM4620A TYPICAL APPLICATIONS INTVCC1 INTVCC C10 4.7µF CLK1 MODE_PLLIN 5V TO 16V INTERMEDIATE BUS VIN R1* 10k C3 22µF 25V C2 22µF 25V C1 22µF 25V R6 100k CLKOUT INTVCC PGOOD1 EXTVCC PGOOD1 VOUT1 VIN TEMP SW1 VFB VFB1 TRACK1 C20 0.22µF VFB2 LTM4620A TRACK2 INTVCC1 220pF VOUTS1 RUN1 RUN2 D1* 5.1V ZENER R2 5k R5 13.3k COMP1 fSET COMP2 PHASMD VOUTS2 COMP VOUT2 SW2 PGOOD2 SGND GND DIFFP DIFFN VOUT 3.3V 50A COUT1 100µF 6.3V ×2 PGOOD1 DIFFOUT COUT2 100µF 6.3V ×2 INTVCC2 C16 4.7µF CLK1 MODE_PLLIN 7V TO 16V INTERMEDIATE BUS C12 22µF 25V C15 22µF 25V C5 22µF 25V R9 100k CLKOUT INTVCC EXTVCC PGOOD1 VOUT1 VIN TEMP VOUTS1 RUN1 SW1 RUN2 VFB1 TRACK1 VFB2 LTM4620A TRACK2 INTVCC2 5k PGOOD2 COUT3 100µF 6.3V ×2 VFB COMP1 fSET COMP2 PHASMD VOUTS2 COMP VOUT2 SW2 PGOOD2 * PULL-UP RESISTOR AND ZENER ARE OPTIONAL SGND GND DIFFP DIFFN DIFFOUT PGOOD2 COUT4 100µF 6.3V ×2 4620A F29 Figure 29. 4-Phase, 3.3V at 50A, 750kHz 4620afc For more information www.linear.com/LTM4620A 35 LTM4620A PACKAGE DESCRIPTION PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY. LTM4620A Component LGA Pinout PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION A1 VOUT1 B1 VOUT1 C1 VOUT1 D1 GND E1 GND F1 GND A2 VOUT1 B2 VOUT1 C2 VOUT1 D2 GND E2 GND F2 GND A3 VOUT1 B3 VOUT1 C3 VOUT1 D3 GND E3 GND F3 GND A4 VOUT1 B4 VOUT1 C4 VOUT1 D4 GND E4 GND F4 MODE_PLLIN A5 VOUT1 B5 VOUT1 C5 VOUT1S D5 VFB1 E5 TRACK1 F5 RUN1 A6 GND B6 GND C6 fSET D6 SGND E6 COMP1 F6 SGND A7 GND B7 GND C7 SGND D7 VFB2 E7 COMP2 F7 SGND A8 VOUT2 B8 VOUT2 C8 VOUT2S D8 TRACK2 E8 DIFFP F8 DIFFOUT A9 VOUT2 B9 VOUT2 C9 VOUT2 D9 GND E9 DIFFN F9 RUN2 A10 VOUT2 B10 VOUT2 C10 VOUT2 D10 GND E10 GND F10 GND A11 VOUT2 B11 VOUT2 C11 VOUT2 D11 GND E11 GND F11 GND A12 VOUT2 B12 VOUT2 C12 VOUT2 D12 GND E12 GND F12 GND PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION G1 GND H1 GND J1 GND K1 GND L1 GND M1 GND G2 SW1 H2 GND J2 VIN K2 VIN L2 VIN M2 VIN G3 GND H3 GND J3 VIN K3 VIN L3 VIN M3 VIN G4 PHASEMD H4 GND J4 VIN K4 VIN L4 VIN M4 VIN G5 CLKOUT H5 GND J5 GND K5 GND L5 VIN M5 VIN G6 SGND H6 GND J6 TEMP K6 GND L6 VIN M6 VIN G7 SGND H7 GND J7 EXTVCC K7 GND L7 VIN M7 VIN G8 PGOOD2 H8 INTVCC J8 GND K8 GND L8 VIN M8 VIN G9 PGOOD1 H9 GND J9 VIN K9 VIN L9 VIN M9 VIN G10 GND H10 GND J10 VIN K10 VIN L10 VIN M10 VIN G11 SW2 H11 GND J11 VIN K11 VIN L11 VIN M11 VIN G12 GND H12 GND J12 GND K12 GND L12 GND M12 GND 36 4620afc For more information www.linear.com/LTM4620A For more information www.linear.com/LTM4620A 6.9850 5.7150 4.4450 3.1750 1.9050 0.6350 0.0000 0.6350 1.9050 3.1750 4.4450 5.7150 6.9850 4 PACKAGE TOP VIEW 3.1750 3.1750 SUGGESTED PCB LAYOUT TOP VIEW 1.9050 PAD 1 CORNER D 0.6350 0.0000 0.6350 aaa Z 1.9050 X E Y bbb Z 0.36 3.95 MIN 4.31 0.60 H1 SUBSTRATE NOM 4.41 0.63 15.00 15.00 1.27 13.97 13.97 0.41 4.00 DIMENSIONS eee S X Y Z 0.46 4.05 0.15 0.10 0.05 MAX 4.51 0.66 NOTES DETAIL B TOTAL NUMBER OF LGA PADS: 144 SYMBOL A b D E e F G H1 H2 aaa bbb eee DETAIL A 0.630 ±0.025 SQ. 143x aaa Z DETAIL B H2 MOLD CAP A (Reference LTC DWG # 05-08-1844 Rev C) LGA Package 144-Lead (15mm × 15mm × 4.41mm) e 3 PADS SEE NOTES F b 11 10 9 7 6 5 PACKAGE BOTTOM VIEW 8 G 4 b 3 2 1 DETAIL A A B C D E F G H J K L M DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE 4 TRAY PIN 1 BEVEL COMPONENT PIN “A1” 7 ! 6.9850 5.7150 4.4450 4.4450 5.7150 6.9850 PACKAGE IN TRAY LOADING ORIENTATION LTMXXXXXX µModule LGA 144 1112 REV C 7 SEE NOTES DIA 0.630 PAD 1 PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY 6. THE TOTAL NUMBER OF PADS: 144 5. PRIMARY DATUM -Z- IS SEATING PLANE LAND DESIGNATION PER JESD MO-222, SPP-010 3 2. ALL DIMENSIONS ARE IN MILLIMETERS NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 12 e 3x, C (0.22 x45°) LTM4620A PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LTM4620A#packaging for the most recent package drawings. 4620afc 37 0.630 ±0.025 Ø 144x 4 PACKAGE TOP VIEW 3.1750 3.1750 SUGGESTED PCB LAYOUT TOP VIEW 1.9050 PIN “A1” CORNER D 0.6350 0.0000 0.6350 aaa Z 1.9050 X For more information www.linear.com/LTM4620A 6.9850 5.7150 4.4450 3.1750 1.9050 0.6350 0.0000 0.6350 1.9050 3.1750 4.4450 5.7150 6.9850 E Y aaa Z b1 SYMBOL A A1 A2 b b1 D E e F G H1 H2 aaa bbb ccc ddd eee NOM 5.01 0.60 4.41 0.75 0.63 15.00 15.00 1.27 13.97 13.97 0.41 4.00 MAX 5.21 0.70 4.51 0.90 0.66 DIMENSIONS BALL DIMENSION PAD DIMENSION BALL HT NOTES DETAIL B PACKAGE SIDE VIEW Z SUBSTRATE THK 0.46 MOLD CAP HT 4.05 0.15 0.10 0.20 0.30 0.15 TOTAL NUMBER OF BALLS: 144 0.36 3.95 MIN 4.81 0.50 4.31 0.60 0.60 H1 SUBSTRATE ddd M Z X Y eee M Z DETAIL A Øb (144 PLACES) DETAIL B H2 MOLD CAP ccc Z A1 A2 A (Reference LTC DWG # 05-08-1880 Rev C) // bbb Z 38 Z BGA Package 144-Lead (15mm × 15mm × 5.01mm) e 12 11 10 9 7 6 5 PACKAGE BOTTOM VIEW 8 4 b 3 2 1 DETAIL A DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE 4 A B C D E F G H J K L M 7 TRAY PIN 1 BEVEL ! PACKAGE IN TRAY LOADING ORIENTATION LTMXXXXXX µModule 7 SEE NOTES PIN 1 BGA 144 1116 REV C PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY 6. SOLDER BALL COMPOSITION CAN BE 96.5% Sn/3.0% Ag/0.5% Cu OR Sn Pb EUTECTIC 5. PRIMARY DATUM -Z- IS SEATING PLANE BALL DESIGNATION PER JESD MS-028 AND JEP95 3 2. ALL DIMENSIONS ARE IN MILLIMETERS NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 COMPONENT PIN “A1” 3 SEE NOTES F b e G LTM4620A Please refer to http://www.linear.com/product/LTM4620A#packaging for the most recent package drawings. PACKAGE DESCRIPTION 4620afc 6.9850 5.7150 4.4450 4.4450 5.7150 6.9850 LTM4620A REVISION HISTORY REV DATE DESCRIPTION A 10/13 Added explanation for TEMP pin PAGE NUMBER B 03/14 Add SnPb BGA package option C 06/17 Added LTM4620AY MP-Grade to the Order Information Changed TEMP explanation and formulas 11 20, 21 1, 2 2 4620afc Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representaFor more www.linear.com/LTM4620A tion that the interconnection of itsinformation circuits as described herein will not infringe on existing patent rights. 39 LTM4620A PACKAGE PHOTO LGA BGA 4.41mm 15mm 15mm RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTM4628 Dual 8A, Single 16A µModule Regulator Pin Compatible with LTM4620A; 4.5V ≤ VIN ≤ 26.5V, 0.6V ≤ VOUT ≤ 5.5V, 15mm × 15mm × 4.32mm LTM4627 15A µModule Regulator 4.5V ≤ VIN ≤ 20V, 0.6V ≤ VOUT ≤ 5.5V, 15mm × 15mm × 4.32mm LTM4611 Ultralow VIN, 15A µModule Regulator 1.5V ≤ VIN ≤ 5.5V, 0.8V ≤ VOUT ≤ 5V, 15mm × 15mm × 4.32mm LTM4620 Dual 13A or Single 26A Lower Output Voltage Range, 0.6V to 2.5V, Pin Compatible LTM4637 20A µModule Regulator 4.5V ≤ VIN ≤ 20V, 0.6V ≤ VOUT ≤ 5.5V, 15mm × 15mm × 4.32mm DESIGN RESOURCES SUBJECT DESCRIPTION µModule Design and Manufacturing Resources Design: • Selector Guides • Demo Boards and Gerber Files • Free Simulation Tools µModule Regulator Products Search Manufacturing: • Quick Start Guide • PCB Design, Assembly and Manufacturing Guidelines • Package and Board Level Reliability 1. Sort table of products by parameters and download the result as a spread sheet. 2. Search using the Quick Power Search parametric table. TechClip Videos Quick videos detailing how to bench test electrical and thermal performance of µModule products. Digital Power System Management Linear Technology’s family of digital power supply management ICs are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature EEPROM for storing user configurations and fault logging. 40 4620afc LT 0617 REV C • PRINTED IN USA For more information www.linear.com/LTM4620A www.linear.com/LTM4620A  LINEAR TECHNOLOGY CORPORATION 2013