LTM4641
38V, 10A DC/DC µModule
Regulator with Advanced
Input and Load Protection
Description
Features
Wide Operating Input Voltage Range: 4.5V to 38V
10A DC Typical, 12A Peak Output Current
n Output Range: 0.6V to 6V
n ±1.5% Maximum Total Output DC Voltage Error
n Differential Remote Sense Amplifier for POL Regulation
n Internal Temperature, Analog Indicator Output
n Overcurrent Foldback and Overtemperature
Protection
n Current Mode Control/Fast Transient Response
n Parallelable for Higher Output Current
n Selectable Pulse-Skipping Operation
n Soft-Start/Voltage Tracking/Pre-Bias Start-Up
n 15mm × 15mm × 5.01mm BGA Package
n SnPb or RoHS Compliant Finish
Input Protection
n UVLO, Overvoltage Shutdown and Latchoff Thresholds
n N-Channel Overvoltage Power-Interrupt MOSFET Driver
n Surge Stopper Capable with Few External Components
Load Protection
n Robust, Resettable Latchoff Overvoltage Protection
n N-Channel Overvoltage Crowbar Power MOSFET Driver
The LTM®4641 is a switch mode step-down DC/DC
µModule® (micromodule) regulator with advanced input
and load protection features. Trip detection thresholds for
the following faults are customizable: input undervoltage,
overtemperature, input overvoltage and output overvoltage. Select fault conditions can be set for latchoff or
hysteretic restart response—or disabled. Included in the
package are the switching controller and housekeeping ICs,
power MOSFETs, inductor, overvoltage drivers, biasing
circuitry and supporting components. Operating from input
voltages of 4V to 38V (4.5V start-up), the device supports
output voltages from 0.6V to 6V, set by an external resistor network remote sensing the point-of-load’s voltage.
n
n
The LTM4641’s high efficiency design can deliver up to
10A continuous current with a few input and output capacitors. The regulator’s constant on-time current mode
control architecture enables high step-down ratios and
fast response to transient line and load changes. The
LTM4641 is offered in a 15mm × 15mm × 5.01mm with
SnPb or RoHS compliant terminal finish.
L, LT, LTC, LTM, µModule, Burst Mode, Linear Technology and the Linear logo are registered
trademarks and LTpowerCAD is a trademark of Linear Technology Corporation. All other
trademarks are the property of their respective owners. Protected by U.S. Patents including
5481178, 5847554, 6100678, 6304066, 6580258, 6677210, 8163643.
Applications
Ruggedized Electronics
Avionics and Industrial Equipment
n
Click to view associated TechClip Videos.
n
Typical Application
µModule Regulator with Input Disconnect and Fast Crowbar Output Overvoltage Protection
1V Load Protected from MTOP
Short-Circuit at 38VIN
4
VIN
4V TO 38V
4.5V START-UP
+
MSP*
10µF
50V
×2
100µF
50V
3
VING VINGP VINH MTOP
VOUT
VINL
750k
UVLO
INTVCC
DRVCC
RUN
TRACK/SS
10nF
MBOT
VOSNS+
LTM4641
VOSNS–
VOUT
1V
100µF 10A
2
×3
MCB**
CROWBAR
fSET
SHORT-CIRCUIT APPLIED
1
SW
5.49k
OVPGM
3
2
CROWBAR (5V/DIV)
1.1VOUT PEAK
5.49k
LOAD
GND
IOVRETRY OVLO FCB LATCH SGND
4
VINL, VINH (25V/DIV)
VOUT
(200mV/DIV)
1
4641 TA01a
5.6M
SGND CONNECTS TO GND INTERNAL TO µMODULE REGULATOR
* MSP: (OPTIONAL) SERIES-PASS OVERVOLTAGE POWER INTERRUPT MOSFET, NXP PSMN014-60LS
** MCB: (OPTIONAL) OUTPUT OVERVOLTAGE CROWBAR MOSFET, NXP PH2625L
4µs/DIV
TESTED AT WORST-CASE CONDITION: NO LOAD
4641 TA01b
4641fe
For more information www.linear.com/LTM4641
1
LTM4641
Table of Contents
Features...................................................... 1
Applications................................................. 1
Typical Application ......................................... 1
Description.................................................. 1
Absolute Maximum Ratings............................... 3
Order Information........................................... 3
Pin Configuration........................................... 3
Electrical Characteristics.................................. 4
Typical Performance Characteristics.................... 8
Pin Functions............................................... 10
Simplified Block Diagram................................ 15
Decoupling Requirements................................ 15
Operation................................................... 16
Introduction............................................................. 16
Motivation................................................................ 16
Power µModule Regulator Reliability....................... 16
Overview.................................................................. 16
Applications Information—Power Supply Features.. 17
Power (VINH) and Bias (VINL) Input Pins.................. 17
Switching Frequency (On Time) Selection and
Voltage Dropout Criteria (Achievable VIN-to-VOUT
Step-Down Ratios).................................................. 18
Setting the Output Voltage; the Differential
Remote Sense Amplifier.......................................... 21
Input Capacitors......................................................23
Output Capacitors and
Loop Stability/Loop Compensation..........................23
Pulse-Skipping Mode vs
Forced Continuous Mode ........................................ 24
Soft-Start, Rail-Tracking and Start-Up Into
Pre-Bias................................................................... 24
INTVCC and DRVCC................................................................ 27
1VREF.......................................................................................... 28
TEMP, OTBH and Overtemperature Protection......... 28
Input Monitoring Pins: UVLO, IOVRETRY, OVLO.....29
Applications Information—Input Protection
Features..................................................... 29
Start-Up/Shutdown and Run Enable;
Power-On Reset and Timeout Delay Time................ 31
Applications Information—Load Protection
Features..................................................... 32
Overcurrent Foldback Protection............................. 32
Power Good Indicator and Latching Output
Overvoltage Protection............................................ 32
Power-Interrupt MOSFET (MSP), CROWBAR Pin
and Output CROWBAR MOSFET (MCB)...................33
Fast Output Overvoltage Comparator Threshold......34
The Switching Node: SW Pin...................................35
Applications Information—EMI Performance......... 35
Applications Information—Multimodule
Parallel Operation......................................... 36
Applications Information—Thermal Considerations
and Output Current Derating............................. 38
Thermal Considerations and
Output Current Derating..........................................38
Applications Information—Output Capacitance
Table......................................................... 45
Applications Information—Safety and Layout
Guidance.................................................... 46
Safety Considerations..............................................46
Layout Checklist/Example.......................................46
Typical Applications....................................... 48
Appendices................................................. 56
Appendix A. Functional Block Diagram and
Features Quick Reference Guide..............................56
Appendix B. Start-Up/Shutdown State Diagram...... 57
Appendix C. Switching Frequency Considerations
and Usage of RfSET..................................................58
Appendix D. Remote Sensing in
Harsh Environments................................................ 59
Appendix E. Inspiration For Pulse-Skipping
Mode Operation.......................................................60
Appendix F. Adjusting the Fast Output Overvoltage
Comparator Threshold.............................................60
Package Description...................................... 63
Package Photo............................................. 63
Package Description...................................... 64
Revision History........................................... 65
Typical Application........................................ 66
Related Parts............................................... 66
4641fe
2
For more information www.linear.com/LTM4641
LTM4641
Absolute Maximum Ratings
Pin Configuration
(Note 1)
Terminal Voltages
VINL, VINH, SW, fSET................................ –0.3V to 40V
VOUT...................................................... –0.3V to 9.2V
VING............................................. –0.3V to VINH + 20V
INTVCC, DRVCC, RUN, TRACK/SS, PGOOD,
CROWBAR, HYST..................................... –0.3V to 6V
FCB, TMR................................-0.3V to INTVCC + 0.3V
COMP.................................................... –0.3V to 2.7V
VOSNS+, VORB+....................................... –0.6V to 9.7V
VOSNS –, VORB –...........VOSNS+ – 2.7V to VOSNS+ + 0.3V
OTBH, UVLO, IOVRETRY, OVLO,
LATCH.....................................................–0.3V to 7.5V
TEMP, OVPGM........................................ –0.3V to 1.5V
Terminal Currents
INTVCC (Continuous)....................................... –30mA
INTVCC (Continuous; CROWBAR
Sourcing 15mA)................................................–15mA
CROWBAR (Continuous)...................................–15mA
VINGP (Continuous)............................ –50mA to 15mA
1VREF (Continuous).................................–1mA to 1mA
Internal Operating Temperature Range (Note 2)
E- and I-Grades................................... –40°C to 125°C
MP-Grade........................................... –55°C to 125°C
Storage Temperature Range................... –55°C to 125°C
Peak Package Body Temperature (SMT Reflow).... 245°C
M
TRACK/SS
PGOOD L
SGND
K
COMP
J
fSET
VINL H
VOSNS+
VOSNS– G
VORB–
VING VINGP
VINH
FCB
DRVCC
GND
SW
GND
GND
F
VORB+
TOP VIEW
INTVCC
SGND
E
OTBH TMR RUN
D
VOUT
LATCH
C
SGND
B
1VREF
GND
A
1
2
3
UVLO
HYST
4
5
TEMP
6
7
8
9 10 11
IOVRETRY CROWBAR OVPGM
OVLO
12
BGA PACKAGE
144-LEAD (15mm × 15mm × 5.01mm)
TJMAX = 125°C, θJCtop = 11°C/W, θJCbottom = 2.5°C/W
θJB = 3°C/W, θJA = 10.4°C/W
θ VALUES DETERMINED PER JESD51-12
WEIGHT = 2.9 GRAMS
Order Information
PART NUMBER
PAD OR BALL FINISH
PART MARKING*
LTM4641EY#PBF
SAC305 (RoHS)
LTM4641Y
e1
BGA
4
–40°C to 125°C
LTM4641IY#PBF
SAC305 (RoHS)
LTM4641Y
e1
BGA
4
–40°C to 125°C
DEVICE
FINISH CODE
PACKAGE
TYPE
MSL
RATING
TEMPERATURE RANGE
(Note 2)
LTM4641IY
SnPb (63/37)
LTM4641Y
e0
BGA
4
–40°C to 125°C
LTM4641MPY#PBF
SAC305 (RoHS)
LTM4641Y
e1
BGA
4
–55°C to 125°C
LTM4641MPY
SnPb (63/37)
LTM4641Y
e0
BGA
4
–55°C to 125°C
Consult Marketing for parts specified with wider operating temperature
ranges. *Device temperature grade is indicated by a label on the shipping
container. Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures:
www.linear.com/umodule/pcbassembly
• Pb-free and Non-Pb-free Part Markings:
www.linear.com/leadfree
• LGA and BGA Package and Tray Drawings:
www.linear.com/packaging
4641fe
For more information www.linear.com/LTM4641
3
LTM4641
Electrical
Characteristics
The l denotes the specifications which apply over the full internal
operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = VINH = VINL = 28V, per the typical application
shown in Figure 45, unless otherwise noted.
SYMBOL
PARAMETER
VIN
Input DC Voltage
VOUT
Output Voltage Range
VOUT(DC)
CONDITIONS
MIN
TYP
MAX
UNITS
l
4.5
38
V
Use RSET1A = RSET1B ≤ 8.2kΩ. RfSET Values
Recommended in Table 1
l
0.6
6
V
Output Voltage, Total Variation with
Line and Load, and Prior to UVLO
4.5V ≤ VIN ≤ 38V, 0A ≤ IOUT ≤ 10A
VIN = 4V (Ramped Down from 4.5V), IOUT = 0A
l
l
1.773
1.773
1.800
1.800
1.827
1.827
V
V
VRUN(ON,OFF)
RUN On/Off Threshold
Run Rising, Turn On
Run Falling, Turn Off
l
l
0.8
1.25
1.15
2
V
V
IRUN(ON)
RUN Pull-Up Current
VRUN = 0V
VRUN = 3.3V
l
l
–580
–220
–520
–165
–460
–110
µA
µA
IRUN(OFF)
RUN Pull-Down Current, Switching
Inhibited
VRUN = 3.3V, UVLO = 0V (MHYST On)
VINL(UVLO)
VINL Undervoltage Lockout
VINL Rising
VINL Falling
Hysteresis
IINRUSH(VINH)
Input Inrush Current Through VINH,
at Start-Up
CSS = Open
230
mA
IQ(VINH)
Power Stage Bias Current (IVINH) at
No Load
IOUT = 0A and:
FCB ≥ 0.84V (Pulse-Skipping Mode)
FCB ≤ 0.76V (Forced Continuous Mode)
Shutdown, RUN = 0
8
29
0.2
mA
mA
mA
IQ(VINL)
Control Bias Current (IVINL)
INTVCC Connected to DRVCC and:
VIN = 28V, IOUT = 0A
VIN = 28V, IOUT = 10A
VIN = 28V, Shutdown, RUN = 0
14.5
15.5
5
mA
mA
mA
IS(VINH)
Power Stage Input Current (IVINH) at
Full Load
IOUT = 10A and:
VIN = 4.5V
VIN = 28V
VIN = 38V
4.65
790
590
A
mA
mA
IOUT(DC)
Output Continuous Current Range
(Note 3)
l
∆VOUT(LINE)/VOUT
Line Regulation Accuracy
VIN from 4.5V to 38V, IOUT = 0A
l
∆VOUT(LOAD)/VOUT
Load Regulation Accuracy
IOUT from 0A to 10A (Note 3)
l
VOUT(AC)
Output Voltage Ripple Amplitude
IOUT = 0A
16
mVP-P
fS
Output Voltage Ripple Frequency
IOUT = 0A
IOUT = 10A
290
330
kHz
kHz
VOUT(START)
Turn-On Overshoot
IOUT = 0A
10
mV
tSTART
VIN-to-VOUT Start-Up Time
RUN Electrically Open Circuit, Time Between
Application of VIN to VOUT Becoming Regulated,
OVPGM = 1.5V, CTMR = CSS = Open
3
ms
tRUN(ON-DELAY)
RUN-to-VOUT Turn-On Response
Time
VIN Established, (TMR-Set POR Time Expired)
Time Between RUN Releasing from GND to
PGOOD Going Logic High, CSS = Open,
OVPGM = 1.5V
175
∆VOUT(LS)
Peak Deviation for Dynamic Load
Step
IOUT from 0A to 5A at 5A/µs
IOUT from 5A to 0A at 5A/µs
40
40
mV
mV
tSETTLE(LS)
Settling Time for Dynamic Load Step IOUT from 0A to 5A at 5A/µs
IOUT from 5A to 0A at 5A/µs
20
20
μs
µs
Input Specifications
1
l
l
l
3.5
300
4.2
3.8
400
nA
4.5
4
V
V
mV
Output Specifications
0
10
A
0.02
0.15
%
0.04
0.15
400
%
μs
4641fe
4
For more information www.linear.com/LTM4641
LTM4641
Electrical
Characteristics
The l denotes the specifications which apply over the full internal
operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = VINH = VINL = 28V, per the typical application
shown in Figure 45, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
IOUT(PK)
Output Current Limit
5.1kΩ Pull-Up from PGOOD to 5V Source, IOUT
Ramped Up Until VOUT Below PGOOD Lower
Threshold, PGOOD Pulls Logic Low
24
A
IVINH(IOUT_SHORT)
Power Stage Input Current During
Output Short Circuit
VOUT Electrically Shorted to GND
45
mA
VFB
Differential Feedback Voltage from
VOSNS+ to VOSNS–
IOUT = 0A
ITRACK/SS
TRACK/SS Pull-Up Current
VTRACK/SS = 0V
VFCB
FCB Threshold
IFCB
FCB Pin Current
VFCB = 0.8V
tON(MIN)
Minimum On-Time
(Note 4)
tOFF(MIN)
Minimum Off-Time
(Note 4)
220
VOSNS(DM)
Remote Sense Pin-Pair Differential
Mode Input Range
VOSNS(CM)
Remote Sense Pin-Pair Common
Mode Input Range
RIN(VOSNS+)
Input Resistance
Valid Differential VOSNS+ -to- VOSNS– Range
(Use RSET1A = RSET1B ≤ 8.2k)
Valid VOSNS– Common Mode Range
Valid VOSNS+ Common Mode Range
(Use RSET1A = RSET1B ≤ 8.2k)
VOSNS+ to GND
Control Section
l
591
600
–0.45
–1
0.76
0.8
l
0
l
l
–0.3
609
mV
μA
0.84
V
0
±1
μA
43
75
ns
300
ns
2.7
V
3
V
V
16318
16400
16482
Ω
5.1
5.3
5.4
V
–0.7
–1
±2
±3
%
%
INTVCC, DRVCC, 1VREF
VINTVCC
Internal VCC Voltage
6V ≤ VIN ≤ 38V, INTVCC Not Connected to DRVCC, l
DRVCC = 5.3V
∆VINTVCC(LOAD)
INTVCC Load Regulation
RUN = 0V, INTVCC Not Connected to DRVCC,
DRVCC = 5.3V and:
IINTVCC Varied from 0mA to –20mA
IINTVCC Varied from 0mA to –30mA
VINTVCC
VINTVCC(LOWLINE)
INTVCC Voltage at Low Line
VIN = 4.5V, RSET1A = RSET1B = 0Ω (~0.6VOUT,
RfSET Value Recommended in Table 1)
l
4.2
4.3
DRVCC(UVLO)
DRVCC Undervoltage Lockout
DRVCC Rising
DRVCC Falling
l
l
3.9
3.2
4.05
3.35
4.2
3.5
V
V
IDRVCC
DRVCC Current
INTVCC Not Connected to DRVCC, DRVCC = 5.3V,
RSET1A, RSET1B and RSET2 Setting VOUT to:
1.8VOUT, RfSET = 2MΩ, 0A ≤ IOUT ≤ 10A
6.0VOUT, RfSET = Open, 0A ≤ IOUT ≤ 10A
(Use RSET1A = RSET1B ≤ 8.2k)
11
20
18
27
mA
mA
0.985
0.980
1.000
1.000
1.015
1.020
533
645
621
525
556
660
644
540
579
675
667
555
mV
mV
mV
mV
8
16
24
mV
75
400
mV
1VREF DC Voltage Regulation
I1VREF = 0mA
I1VREF = ±1mA
VPGOOD(TH)
Power Good Window, Logic State
Transition Thresholds
Ramping Differential VOSNS+ – VOSNS– Voltage:
Up, PGOOD Goes Logic Low → High
Up, PGOOD Goes Logic High → Low
Down, PGOOD Goes Logic Low → High
Down, PGOOD Goes Logic High → Low
VPGOOD(HYST)
Hysteresis
Differential VOSNS+ – VOSNS– Voltage Returning
VPGOOD(VOL)
Logic-Low Output Voltage
IPGOOD = 5mA
tPGOOD(DELAY)
PGOOD Logic-Low Blanking Time
Delay Between Differential VOSNS+ – VOSNS–
Voltage Exiting PGOOD Valid Window to PGOOD
Going Logic Low (Note 4)
V1VREF(DC)
l
l
V
V
V
PGOOD Output
l
12
μs
4641fe
For more information www.linear.com/LTM4641
5
LTM4641
Electrical
Characteristics
The l denotes the specifications which apply over the full internal
operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = VINH = VINL = 28V, per the typical application
shown in Figure 45, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
l
l
11.5
35
45
10.5
13.3
38.4
48.4
11.5
15.5
41
51.5
14.2
V
V
V
V
Power-Interrupt MOSFET Drive
VVING
Gate Drive Voltage for PowerInterrupt MOSFET, MSP
VIN = 4.5V, 0A ≤ IOUT ≤ 10A, VING Sourcing 1µA
VIN = 28V, 0A ≤ IOUT ≤ 10A, VING Sourcing 1µA
VIN = 38V, 0A ≤ IOUT ≤ 10A, VING Sourcing 1µA
VIN = 4V (Ramped Down from 4.5V), IOUT = 0A,
VING Sourcing 1µA
IVING(UP)
VING Pull-Up Current
VING Tied to VINGP, and:
VIN = 4.5V, VING Pulled to 6.5V
VIN = 28V, VING Pulled to 30V
l
l
350
425
475
550
600
675
µA
µA
VING Tied to VINGP, Pulled to 33V, and:
RUN Pulled to 0V (CROWBAR Inactive)
OVPGM Pulled to 0V (CROWBAR Active)
l
l
3
24
20
27
30
30
mA
mA
1.3
2.6
µs
IVING_DOWN(CROWBAR
VING Pull-Down Current
ACTIVE,CROWBAR
INACTIVE)
tVING(OVP_DELAY)
VING OVP Pull-Down Delay
OVPGM Driven from 650mV to 550mV, VING
Discharge Response Time
IVINGP(LEAK)
Zener Diode Leakage Current
VINGP Driven to (VINH + 10V)
1
nA
VINGP(CLAMP)
Zener Diode Breakdown Voltage
VINGP-to-VINH Differential Voltage; IVINGP = 5mA
15
V
l
Fault Pins and Functions
VOVPGM
Default Output Overvoltage Program OVPGM Electrically Open Circuit
Setting
l
650
666
680
IOVPGM(UP)
OVPGM Pull-Up Current
OVPGM = 0V
l
–2.07
–2
–1.91
μA
IOVPGM(DOWN)
OVPGM Pull-Down Current
OVPGM = 1V
l
0.945
1
1.06
μA
OVPTH
Output Overvoltage Protection
Inception Threshold
Ramping Up Differential VOSNS+-to-VOSNS–
Voltage Until CROWBAR Outputs Logic High
l
647
666
683
mV
OVPERR
Output Overvoltage Protection
Inception Error
Difference Between OVPTH and VOVPGM
(OVPTH-VOVPGM)
l
–12
0
12
mV
tCROWBAR(OVP_DELAY)
CROWBAR Response Time
OVPGM Driven from 650mV to 550mV
l
400
500
ns
VCROWBAR(OH)
CROWBAR Output, Active High
Voltage
OVPGM Pulled to 0V and:
ICROWBAR = –100μA, IINTVCC = –20mA
ICROWBAR = –4mA, IINTVCC = –20mA
l
l
4.65
4.55
5
4.9
V
V
CROWBAR Output, Passive Low
Voltage
ICROWBAR = 1μA
l
260
500
mV
VINL Ramped Up from/Down to 0V
l
550
900
mV
l
1.4
1.5
1.6
V
950
980
585
1010
mV
mV
VCROWBAR(OL)
VCROWBAR(OVERSHOOT) CROWBAR Peak Voltage Overshoot
at VINL Start-Up and Shutdown
4.3
4.2
mV
VCROWBAR(TH)
CROWBAR Latchoff Threshold
CROWBAR Ramped Up Until HYST Goes Logic
Low
VTEMP
TEMP Voltage
RUN = 0V, TA = 25°C
RUN = 0V, TA = 125°C
(See Figure 10 for Reference)
OTTH(INCEPTION)
TEMP Overtemperature Inception
Threshold
Ramping TEMP Downward Until HYST Outputs
Logic Low
l
428
438
448
mV
OTTH(RECOVER)
TEMP Overtemperature Recovery
Threshold
Ramping TEMP Upward Until HYST Outputs
Logic High
l
501
514
527
mV
UVOVTH
UVLO/OVLO/IOVRETRY
Undervoltage/Overvoltage Inception
Thresholds
Ramping UVLO, OVLO or IOVRETRY Positive
Until HYST Toggles Its State
l
488
500
512
mV
4641fe
6
For more information www.linear.com/LTM4641
LTM4641
Electrical
Characteristics
The l denotes the specifications which apply over the full internal
operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = VINH = VINL = 28V, per the typical application
shown in Figure 45, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
tUVOVD
UVLO/OVLO/IOVRETRY/ TEMP
Response Time
±50mV Overdrive (All Pins)
±5mV Overdrive, UVLO/OVLO/IOVRETRY Pins
Only (Note 4)
l
50
25
125
100
500
µs
µs
IUVOV
Input Current of UVLO, OVLO and
IOVRETRY
UVLO = 0.55V or OVLO = 0.45V or
IOVRETRY = 0.45V
l
±30
nA
VHOUSEKEEPING(UVLO)
Housekeeping Circuitry UVLO
Voltage on INTVCC, INTVCC Rising (Note 4)
Hysteresis, INTVCC Returning (Note 4)
VHYST(SWITCHING ON)
HYST Voltage (MHYST Off, RUN
Logic High)
RUN Electrically Open Circuit
RUN = 1.8V
VHYST(SWITCHING OFF,
RUN)
HYST Voltage (MHYST Off, RUN
Logic Low)
VHYST(SWITCHING OFF,
FAULT)
HYST Voltage, Switching Action
Inhibited (MHYST On)
TMRUOTO
Timeout and Power-On Reset Period CTMR = 1nF, Time from Fault Clearing to HYST
Being Released by Internal Circuitry
l
5
1.2
1.9
5
2
25
2.1
50
V
mV
l
l
4.9
1.85
5.1
2.1
5.25
2.35
V
V
RUN = 0V
l
170
350
480
mV
UVLO < UVOVTH or OVLO > UVOVTH or
IOVRETRY > UVOVTH or TEMP < OTTH(INCEPTION)
or CROWBAR > VCROWBAR(TH) or
DRVCC < DRVCCUVLO(FALLING)
(See Figures 62, 63)
l
30
65
mV
9
14
ms
VLATCH(IH)
LATCH Clear Threshold Input High
l
VLATCH(IL)
LATCH Clear Threshold Input Low
l
0.8
V
V
ILATCH
LATCH Input Current
VLATCH = 7.5V
l
±1
μA
ITMR(UP)
TMR Pull-Up Current
VTMR = 0V
l
–1.2
–2.1
–2.8
μA
ITMR(DOWN)
TMR Pull-Down Current
VTMR = 1.6V
l
1.2
2.1
2.8
μA
VTMR(DIS)
Timer Disable Voltage
Referenced to INTVCC
l
–180
–270
OTBHVIL
OTBH Low Level Input Voltage
OTBHVZ
OTBH Pin Voltage When Left
Electrically Open Circuit
–10μA ≤ IOTBH ≤ 10μA
l
IOTBH(MAX)
Maximum OTBH Current
OTBH Electrically Shorted to SGND
l
l
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
The LTM4641 SW absolute maximum rating of 40V is verified in ATE by
regulating VOUT while at 40VIN, in a controlled manner guaranteed to not
affect device reliability or lifetime. Static testing of SW leakage current at
40VIN is performed at control IC wafer level only.
Note 2: The LTM4641 is tested under pulsed load conditions such that
TJ ≈ TA. The LTM4641E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the
0.6
0.9
mV
0.4
V
1.2
V
30
μA
–40°C to 125°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
The LTM4641I is guaranteed over the –40°C to 125°C operating junction
temperature range. The LTM4641MP is tested and guaranteed over the
full –55°C to 125°C operating temperature range. Note that the maximum
ambient temperature consistent with these specifications is determined by
specific operating conditions in conjunction with board layout, the rated
package thermal impedance and other environmental factors.
Note 3: See output current derating curves for different VIN, VOUT and TA.
Note 4: 100% tested at wafer level only.
4641fe
For more information www.linear.com/LTM4641
7
LTM4641
Typical Performance Characteristics
(Figure 45 circuit with RfSET per Table 1 and RSET1A, RSET1B and RSET2 per Table 2, unless otherwise noted)
Efficiency vs Load Current at 24VIN
90
90
90
85
85
85
75
6.0VOUT
5.0VOUT
3.3VOUT
2.5VOUT
1.8VOUT
70
65
60
0
1
2
1.5VOUT
1.2VOUT
1.0VOUT
0.9VOUT
3
7 8
4 5 6
OUTPUT CURRENT (A)
9
EFFICIENCY (%)
95
80
80
75
6.0VOUT
5.0VOUT
3.3VOUT
2.5VOUT
1.8VOUT
70
65
60
10
0
1
2
1.5VOUT
1.2VOUT
1.0VOUT
0.9VOUT
3
7 8
4 5 6
OUTPUT CURRENT (A)
4641 G01
90
90
80
70
EFFICIENCY (%)
80
75
70
3.3VOUT
2.5VOUT
1.8VOUT
1.5VOUT
65
60
0
1
2
1.2VOUT
1.0VOUT
0.9VOUT
3
7 8
4 5 6
OUTPUT CURRENT (A)
9
10
60
65
60
10
0
1
2
3
7 8
4 5 6
OUTPUT CURRENT (A)
30
20
IOUT
2.5A/DIV
FCB = SGND
FORCED
CONTINUOUS
20µs/DIV
0A TO 5A LOAD STEPS AT 5A/µs
FRONT PAGE CIRCUIT WITH
OVPGM = OPEN CIRCUIT
10
0
0.001
10
9
4641 G03
50
40
1.5VOUT
1.2VOUT
1.0VOUT
0.9VOUT
1V Transient Response, 38VIN
FCB = INTVCC
(PULSE-SKIPPING)
0.1
0.01
1
OUTPUT CURRENT (A)
4641 G06
10
4641 G05
3.3V Transient Response,
28VIN to 3.3VOUT
1V Transient Response, 4.5VIN
VOUT
50mV/DIV
AC-COUPLED
VOUT
50mV/DIV
AC-COUPLED
IOUT
2.5A/DIV
IOUT
2.5A/DIV
4641 G07
6.0VOUT
5.0VOUT
3.3VOUT
2.5VOUT
1.8VOUT
70
VOUT
50mV/DIV
AC-COUPLED
4641 G04
20µs/DIV
0A TO 5A LOAD STEPS AT 5A/µs
FRONT PAGE CIRCUIT WITH
OVPGM = OPEN CIRCUIT
75
Pulse-Skipping vs Forced
Continuous Mode Efficiency,
28VIN to 3.3VOUT
95
85
9
80
4641 G02
Efficiency vs Load Current at 6VIN
EFFICIENCY (%)
Efficiency vs Load Current at 12VIN
95
EFFICIENCY (%)
EFFICIENCY (%)
Efficiency vs Load Current at 36VIN
95
Output Start-Up, No Load
VOUT
1V/DIV
IIN
200mA/DIV
RUN
5V/DIV
20µs/DIV
0A TO 5A LOAD STEPS AT 5A/µs
FIGURE 46 CIRCUIT
4641 G08
800µs/DIV
VIN = 24V
CIN(MLCC) = 2 × 10µF X7R
4641 G09
4641fe
8
For more information www.linear.com/LTM4641
LTM4641
Typical Performance Characteristics
(Figure 45 circuit with RfSET per Table 1 and RSET1A, RSET1B and RSET2 per Table 2, unless otherwise noted)
Output Start-Up,
Pre-Bias Condition
Output Start-Up, 10A Load
Output Short-Circuit,
No Initial Load
VOUT
1V/DIV
VOUT
1V/DIV
VOUT
1V/DIV
ILOAD
1mA/DIV
IIN
200mA/DIV
RUN
5V/DIV
IIN
1A/DIV
RUN
5V/DIV
800µs/DIV
VIN = 24V
CIN(MLCC) = 2 × 10µF X7R
800µs/DIV
VIN = 24V
CIN(MLCC) = 2 × 10µF X7R
4641 G10
Output Short-Circuit,
10A Initial Load
VIN
20V/DIV
VINH
2V/DIV
VOUT
1V/DIV
IIN
1A/DIV
Start-Up with VINH Shorted to SW
Node, 1VOUT(NOM)
Start-Up with VINH Shorted to SW
Node, 3.3VOUT(NOM)
VIN
10V/DIV
VINH
5V/DIV
VOUT
200mV/DIV
IIN
1A/DIV
VOUT
1V/DIV
CROWBAR
5V/DIV
CROWBAR
5V/DIV
Paralleled Modules, CurrentSharing Performance. cf.
Figure 66 Circuit. 28VIN
Autonomous Restart with VINH
Shorted to SW Node, 3.3VOUT(NOM)
12
CROWBAR
5V/DIV
4641 G16
100ms/DIV
FIGURE 46 CIRCUIT, SHORT CIRCUITING VINH
TO SW IN SITU, OPERATING AT 38VIN AND
NO LOAD. LATCH CONNECTED TO INTVCC AND
CTMR = 47nF
0.606
10
U1 IOUT
6
U2 IOUT
4
2
0
0
4
8
12
16
TOTAL OUTPUT CURRENT (A)
20
4641 G17
0.602
0.600
1.006
1.004
0.604
8
–2
Control IC Bandgap and 1VREF
Voltages vs Temperature. 28VIN
1.002
VFB
1.000
V1VREF(DC)
0.598
0.998
0.596
0.996
1VREF VOLTAGE (V)
VOUT
1V/DIV
4641 G15
800µs/DIV
FIGURE 46 CIRCUIT WITH VINH SHORT
CIRCUITED TO SW PRIOR TO POWER-UP.
APPLYING UP TO 38VIN. NO LOAD
4641 G14
400µs/DIV
FRONT PAGE CIRCUIT WITH VINH SHORT
CIRCUITED TO SW PRIOR TO POWER-UP.
APPLYING UP TO 38VIN. NO LOAD
MODULE OUTPUT CURRENT (A)
VIN
10V/DIV
VINH
10V/DIV
4641 G13
VFB BANDGAP VOLTAGE (V)
20µs/DIV
VIN = 24V
CIN(MLCC) = 2 × 10µF X7R
4641 G12
20µs/DIV
VIN = 24V
CIN(MLCC) = 2 × 10µF X7R
4641 G11
0.994
0.594
–75 –50 –25 0 25 50 75 100 125 150
JUNCTION TEMPERATURE (°C)
4641 G18
4641fe
For more information www.linear.com/LTM4641
9
LTM4641
Pin Functions
SGND (A1-A3; B1-B3; C1-C4; K1, K3; L3; M1-M3): Signal
Ground Pins. This is the return ground path for all analog
control and low power circuitry. SGND is tied to GND internal to the µModule regulator in a manner that promotes
the best internal signal integrity—therefore, SGND should
not be connected to GND in the user’s PCB layout. See
the Layout Checklist/Example section of the Applications
Information section for more information pertaining to
SGND and layout. All SGND pins are electrically connected
to each other, internally.
HYST (A4): Input Undervoltage Hysteresis Programming
Pin. Normally used as an output, but can be used as an
input. If the LTM4641’s inherent, default undervoltage
lockout (UVLO) settings are satisfactory, 4.5VIN(RISING,
MAX) and 4VIN(FALLING, MAX), HYST can be left electrically
open circuit. See the Applications Information section to
customize the LTM4641’s UVLO thresholds.
HYST is a logic-high output with moderate pull-up strength
that commands LTM4641’s internal control IC to regulate
the module’s output voltage when conditions on the RUN,
UVLO, OVLO, IOVRETRY, TEMP, CROWBAR, INTVCC
and DRVCC pins permit it (any recent latchoff events
notwithstanding, otherwise OTBH and LATCH can also
play a role). When a fault condition is detected, internal
circuitry (MHYST; see Figure 1) drives HYST logic low and
the LTM4641’s output is turned off. HYST can be used as
a fault-indicator. See the Applications Information section.
HYST is pulled low when the RUN pin is pulled low, via
an internal Schottky diode. HYST can be driven low by
external open-collector/open-drain circuitry directly—as
an alternate to the RUN pin interface. However, external
circuitry should never drive HYST high, since doing so
(indiscriminately) could cause thermal overstress to
MHYST, when MHYST is on.
TEMP (A5): Power Stage Temperature Indicator and
Overtemperature Detection Pin. When left electrically open
circuit, TEMP’s voltage varies according to an internal NTC
(negative temperature coefficient) thermistor, residing in
close proximity to LTM4641’s power stage. When TEMP
falls below 438mV (corresponding to a thermistor and
power stage temperature of ~145°C), the LTM4641 pulls
HYST low to inhibit regulation of its output voltage. HYST
may be deasserted when TEMP subsequently exceeds
514mV (nominally corresponding to a cool-off hysteresis
of ~10°C), depending on the OTBH setting. (See OTBH and
the Applications Information section.)
To disable the µModule regulator’s overtemperature
shutdown feature, connect the TEMP and 1VREF pins. The
thermal shutdown inception threshold can also be modified, see the Applications Information section.
IOVRETRY (A6): Nonlatching Input Overvoltage Threshold
Programming Pin. The LTM4641 pulls HYST low to inhibit
regulation of its output voltage when IOVRETRY exceeds
0.5V. The LTM4641 can resume switching action when
IOVRETRY is below 0.5V. If no nonlatching input overvoltage shutdown behavior is desired, connect this pin to
SGND. Do not leave this pin open circuit.
GND (A7-A12; B6-B8, B11-B12; C7-C8; D6-D8; E1-E8;
F1-F12; G1-G12; H3-H9, H11-H12; J5-J12; K5-K6, K11K12; L4-L6; M4-M6): Power ground pins for input and
output returns. See the Layout Checklist/Example section
of the Applications Information section. All GND pins are
electrically connected to each other, internally.
UVLO (B4): Input Undervoltage Lockout Programming
Pin. The LTM4641 pulls HYST low to inhibit regulation
of its output voltage whenever UVLO is less than 0.5V.
The LTM4641 can resume switching action when UVLO
exceeds 0.5V. Do not leave this pin open circuit.
If the LTM4641’s default UVLO settings are used,
4.5VIN(RISING, MAX) and 4VIN(FALLING, MAX), then the UVLO
pin should be electrically connected to 1VREF or INTVCC.
Otherwise, see HYST and the Applications Information
section for using a resistor-divider network to implement
personalized UVLO rising and UVLO falling settings.
OVLO (B5): Input Overvoltage Latchoff Programming Pin.
LTM4641 pulls HYST low to inhibit regulation of its output
voltage when OVLO exceeds 0.5V. If OVLO subsequently
falls below 0.5V, the module’s output remains latched
off; the LTM4641 cannot resume regulation of the output
voltage until either the LATCH pin is toggled high or VINL
is power cycled. If input overvoltage latchoff behavior is
not desired, electrically short this pin to SGND. Do not
leave this pin open circuit.
4641fe
10
For more information www.linear.com/LTM4641
LTM4641
Pin Functions
CROWBAR (B9): Crowbar Output Pin. Normally logic low,
with moderate pull-down strength to SGND.
When an output overvoltage (OOV) condition is detected,
the LTM4641’s fast OOV comparator pulls CROWBAR logic
high through a series-connected internal diode. If utilizing
LTM4641’s OOV feature, CROWBAR should connect to
the gate of a logic-level N-channel MOSFET configured to
crowbar the module’s output voltage (MCB, in Figure 1).
Furthermore, the LTM4641 latches off its output when
CROWBAR nominally exceeds 1.5V and latches HYST
logic low (see HYST).
If not using the OOV protection features of the LTM4641,
leave CROWBAR electrically open circuit.
OVPGM (B10): Output Overvoltage Threshold Programming
Pin. The voltage on this pin sets the trip threshold for the
inverting input pin of LTM4641’s fast OOV comparator.
When left electrically open circuit, resistors internal to the
LTM4641 nominally bias OVPGM to 666mV (OVPTH)—11%
above the nominal VFB feedback voltage (600mV) that the
control loop strives to present to the noninverting input pin
of LTM4641’s fast OOV comparator. The aforementioned
voltages correspond proportionally to the module’s OOV
inception threshold and VOUT’s nominal voltage of regulation, respectively. Altering the OVPGM voltage provides a
means to adjust the OOV threshold; its DC-bias setpoint
can be tightened with simple connections to external
components (see the Applications Information section).
Trace route lengths and widths to this sensitive analog
node should be minimized. Minimize stray capacitance to
this node unless altering the OOV threshold as described
in the Applications Information section and Appendix F.
LATCH (C5): Latchoff Reset Pin. When a latchoff fault occurs, the LTM4641 turns off its output and latches MHYST
on to indicate a fault condition has occurred (see HYST). To
configure the LTM4641 for latched off response to latchoff
faults, connect LATCH to SGND. As long as LATCH is logic
low, the LTM4641 will not unlatch. Regulation can be resumed by cycling VINL or by toggling LATCH from logic low
to high. It is also permissible to connect LATCH to INTVCC;
this configures the LTM4641 for autonomous restart with
a timeout delay (programmed by CTMR—see TMR).
If no latchoff faults are present when LATCH transitions
from logic low to logic high, the LTM4641 immediately unlatches. If any latchoff fault is present when LATCH is logic
high, a timeout delay timing requirement is imposed: the
LTM4641 will not unlatch until all latchoff fault-monitoring
pins meet operationally valid states for the full duration
of the timeout delay. If LATCH becomes logic low before
that timeout delay has expired, the LTM4641 remains
latched off and the timeout delay is reset. Unlatching the
LTM4641 can be reattempted by pulling LATCH logic high
at a later time.
The following are latchoff fault conditions:
• CROWBAR activates (see CROWBAR)
• Input latchoff overvoltage fault (see OVLO)
• Latchoff overtemperature fault (when OTBH is logic
low; see TEMP and OTBH)
LATCH is a high impedance input and must not be left electrically open circuit. LATCH can be driven by a μController
in intelligent systems: a reasonable implementation for
unlatching the LTM4641 is to pull LATCH logic high for
the maximum anticipated timeout delay time—after which,
HYST can be observed to indicate whether the LTM4641
has become unlatched.
1VREF (C6): Buffered 1V Reference Output Pin. Minimize
capacitance on this pin, to assure the OVPGM and TEMP
pins are operational in a timely manner at power-up. 1VREF
should never be externally loaded except as explained in
the Applications Information section.
VOUT (C9-C12; D9-D12; E9-E12): Power Output Pins of
the LTM4641 DC/DC Converter Power Stage. All VOUT
pins are electrically connected to each other, internally.
Apply output load between these pins and the GND pins.
It is recommended to place output decoupling capacitance
directly between these pins and the GND pins. Review
Table 9. See the Layout Checklist/Example section of the
Applications Information section.
VORB+ (D1): VOSNS+ Readback Pin. This pin connects to
VOSNS+ internal to the µModule regulator. It is recommended to route this pin (differentially with VORB–) to a test
point so as to allow the user a way to confirm the integrity
4641fe
For more information www.linear.com/LTM4641
11
LTM4641
Pin Functions
of the remote-sense connections prior to powering up the
LTM4641. VORB+ can also be connected as a redundant
feedback connection to VOSNS+ on the user’s motherboard.
VORB– (D2): VOSNS– Readback Pin. This pin connects to
VOSNS– internal to the µModule regulator. It is recommended to route this pin (differentially with VORB+) to a test
point so as to allow the user a way to confirm the integrity
of the remote-sense connections prior to powering up the
LTM4641. VORB– can also be connected as a redundant
feedback connection to VOSNS– on the user’s motherboard.
OTBH (D3): Overtemperature Behavior Programming
Pin. When an overtemperature condition is detected (see
TEMP), HYST pulls logic low to inhibit switching. If OTBH
is connected to SGND, the LTM4641 latches HYST low. If
OTBH is left floating, output voltage regulation can resume
when the overtemperature event clears.
TMR (D4): Timeout Delay Timer and Power-On Reset (POR)
Programming Pin. Connect a capacitor (CTMR) from TMR
to SGND to program the POR and timeout delay time of the
LTM4641; 9ms delay time per nanofarad of capacitance.
The minimum delay time is ~90μs, when TMR is left
electrically open circuit. Even though they use the same
capacitor, the power-on reset and timeout delay timers
operate independently of each other. Any nonlatching fault
or latching fault will reset the respective timer to the full
delay time without impacting the other timer.
The timeout delay time programmed by a CTMR capacitor
can be negated by pulling TMR to INTVCC.
RUN (D5): Run (On/Off) Control Pin. A RUN pin voltage
below 0.8V will turn off the module. A voltage above 2V
will command the module to turn on, if HYST is not asserted low by MHYST. The LTM4641 contains a moderate
(10k) pull-up resistor from HYST to INTVCC, and a pull-up
Schottky diode from RUN to HYST (see Figure 1). When
RUN is pulled logic low, HYST is pulled logic low via the
internal Schottky diode. RUN is compatible with directdrive (totem-pole output drive) as well as open-collector/
open-drain interfaces.
VOSNS+ (H1): Positive Input to the Remote Sense Differential Amplifier. This pin connects to the positive side of
the output voltage remote sense point (VOUT potential) via
a resistor (RSET1A). When regulating the output voltage,
the LTM4641 control loop drives the differential voltage
between VOSNS+ and VOSNS– to the lesser of TRACK/
SS and 0.6V. VOSNS+ is connected to VORB+ internal to
the module (see VORB+). A resistor may be needed from
VOSNS+ to VOSNS– for some output voltage settings. (See
the Applications Information section: Setting the Output
Voltage.) Minimize stray capacitance to this pin to protect
the integrity of the output voltage feedback signal.
VOSNS– (H2): Negative Input to the Remote Sense Differential Amplifier. This pin connects to the negative side
of the output voltage remote sense point (GND potential)
via a resistor (RSET1B). When switching action is on,
the LTM4641 control loop drives the differential voltage
between VOSNS+ and VOSNS– to the lesser of TRACK/
SS and 0.6V. VOSNS– is connected to VORB– internal to
the module (see VORB–). A resistor may be needed from
VOSNS+ to VOSNS– for some output voltage settings. (See
the Applications Information section.) Minimize stray capacitance to this pin to protect the integrity of the output
voltage feedback signal.
SW (H10): Switching Node of the Power Stage. Mainly
used for testing purposes, however, one may optionally
connect a snubber (series-configured capacitor CSW and
resistor RSW) from SW to GND to reduce radiated EMI—in
exchange for a minor compromise to power conversion
efficiency. (See the Applications Information section.)
COMP (J1): Current Control Threshold and Error Amplifier
Compensation Point. The current comparator threshold of
LTM4641’s valley current mode control loop—and correspondingly, the commanded trough of the power inductor
current—increases as this control voltage increases. It can
be useful to make COMP available for observation on a
PCB via or test pad with an oscilloscope probe. However,
stray capacitance and trace lengths to this sensitive analog
node should be minimized.
fSET (J2): Switching Frequency Setting and Adjustment Pin.
This pin interfaces directly to the ION pin of LTM4641’s
internal control IC. Current flow into the ION pin programs
the on-time of the control loop’s one-shot timer and power
control MOSFET, MTOP. Minimize stray capacitance and
any tracelengths to this pin.
For applications requiring regulated output voltages of 3V
or less at any time including during voltage rail tracking,
4641fe
12
For more information www.linear.com/LTM4641
LTM4641
Pin Functions
an on-time adjustment with a resistor to fSET is required.
Otherwise, fSET can be left open circuit. See the Applications Information section for details.
An undervoltage lockout detector monitors DRVCC. HYST is
pulled low and switching action is inhibited if DRVCC is less
than 4.2V rising (maximum) and 3.5V falling (maximum).
VINL (J3): Input Voltage Pin, Low Current for Power
Control and Logic Bias. Feeds LTM4641’s internal 5.3V
LDO (see INTVCC). Apply input voltage bias between this
pin and GND. Decouple to GND with a capacitor (0.1µF
to 1µF). This pin powers the heart of LTM4641’s DC/DC
controller and internal housekeeping ICs. VINL bias current is within ~5mA of the sum of INTVCC and CROWBAR
loading currents.
FCB (K2): Forced Continuous/Pulse-Skipping Mode Operation Programming Pin. Connect this pin to SGND to force
continuous mode operation of the synchronous power
MOSFETs (MTOP and MBOT) at all output load conditions.
Connect this pin to INTVCC to enable pulse-skipping mode
operation: the freewheeling power switching MOSFET
(MBOT) is turned off of to prevent reverse flow of output
current (IOUT) at light loads. See Appendix E for more
details. This is a high impedance input and must not be
left electrically open circuit.
If using the advanced output overvoltage (OOV) protection
features of the LTM4641, connect VINL to either the drain of
the external power-interrupt power MOSFET, identified on
the front page schematic as MSP, or a separate input bias
supply. If not making use of the advanced OOV protection
features, VINL and VINH can connect directly to the same
input power source.
LDO losses can be eliminated by connecting VINL, INTVCC,
and DRVCC if a low power auxiliary ~5V rail is available to
power the resulting node. (See the Applications Information section, Figure 47 and Figure 49.)
DRVCC (J4): Power MOSFET Driver Input Power Pin. DRVCC
is normally connected to INTVCC. It must be kept within two
diode drops (2 • VBE or ~1.2V at 25°C) of INTVCC. DRVCC
powers the internal MOSFET driver that interfaces to the
switching MOSFETs (MTOP and MBOT) within LTM4641’s
power stage. It is pinned out separately from INTVCC to
allow gate-driver current to be observed, and to allow an
auxiliary ~5V to 6V bias supply to optionally provide the
MOSFET driver bias current. The INTVCC/DRVCC pin pair
can be biased from up to 6V (absolute maximum) from
an external supply with 50mA peak sourcing capability, to
reduce the LTM4641’s INTVCC LDO losses (see Applications Information section and Figure 51). When DRVCC is
connected directly to INTVCC, no bypass capacitance is
needed except in rare applications where very fast output
voltage ramp up is required (e.g., no soft-start capacitor
on TRACK/SS, or rail-tracking rails with sub-60µs turn-on
rise-time). Otherwise, ~2.2µF to 4.7μF X7R MLCC local
bypassing to GND is recommended. Higher impedance
sources may require higher bypass capacitance, to mitigate
DRVCC sag during VOUT start-up.
INTVCC (K4): Internal 5.3V LDO Output. LDO operates off
of VINL. The INTVCC rail biases low power control and
housekeeping circuitry. INTVCC is usually connected to
DRVCC to power the MOSFET drivers interfacing to the
switching power MOSFETs. No decoupling capacitance is
needed on this pin unless it is being used to bias external
circuitry (not common); do not apply more than 4.7µF
(±20% tolerance) of external decoupling capacitance. The
INTVCC/DRVCC pin pair can be overdriven by an external
supply, from up to 6V (absolute maximum) with 50mA peak
sourcing capability, to eliminate power losses otherwise
incurred by the LTM4641’s VINL-to-INTVCC linear regulator
(see the Applications Information section and Figure 51).
VINH (K7-10; L7-12; M7-8, 11-12): Input Voltage Pin, High
Current to the Power Converter Stage of the LTM4641.
All VINH pins are electrically connected to each other internally. Devote a large copper plane to connect as many
of the VINH pins to each other as is feasible. This will help
form a low impedance electrical connection between the
input source and the LTM4641’s power stage. It will also
provide a thermal path for removing heat from the BGA
package and minimize junction temperature rise of the
LTM4641 for a given application.
If utilizing the advanced output overvoltage (OOV) protection features of the LTM4641, connect VINH to the source
pin(s) of the external power-interrupt MOSFET, identified on
the front page schematic as MSP, with a short wide trace,
or preferably a small copper plane capable of adequately
4641fe
For more information www.linear.com/LTM4641
13
LTM4641
Pin Functions
handling the input current to LTM4641’s power stage.
Do not decouple the VINH pins with any bypass capacitance
in this case. Instead, place all decoupling capacitance
directly between the drain of MSP to GND.
If not utilizing the advanced OOV protection features of
the LTM4641, do decouple the VINH pins to GND with
local ceramic and bulk decoupling capacitance (see the
Applications Information section).
PGOOD (L1): Output Voltage Power Good Indicator. This
is an open-drain logic output pin that is pulled to ground
when the output voltage (and accordingly, the divided-down
representation of the output voltage, VFB, as presented to
the control loop) is outside ±10% of the nominal target
for regulation.
TRACK/SS (L2): Output Voltage Tracking and Soft-Start
Programming Pin. This pin has a 1.0μA pull-up current
source, typical. A capacitor can be placed from this pin to
SGND to obtain an output voltage soft-start ramp-up rate
whose turn-on time is 0.6ms per nanofarad of capacitance.
Alternatively, when a voltage is applied to TRACK/SS
through a resistor-divider network from another rail, the
LTM4641 output is able to track the external voltage to
satisfy coincident and ratiometric rail-voltage sequencing
requirements. See the Applications Information section.
VING (M9): Gate Drive Output Pin. If utilizing the advanced
output overvoltage (OOV) protection features of the
LTM4641, connect VING to VINGP and to the gate of the
external power-interrupt N-channel MOSFET feeding VINH,
identified on the front page schematic as MSP; otherwise,
leave this pin electrically open circuit.
VINGP (M10): Gate Drive Protection Pin. If utilizing the advanced OOV protection features of the LTM4641, connect
VINGP to VING and to the gate of the external power-interrupt
N-channel MOSFET feeding VINH, MSP; otherwise, leave
this pin electrically open circuit.
4641fe
14
For more information www.linear.com/LTM4641
LTM4641
Simplified Block Diagram
VIN
RHYST
RTUV
VINL
INTVCC
UVLO
RBUV
0.1µF
10k
HYST
MHYST
ENABLE
SWITCHING
ACTION
VING
15V
ZENER
RMOV
IOVRETRY
CONSTANT
ON-TIME
VALLEY MODE
SYNCHRONOUS
BUCK
CONTROLLER
PROTECTION
COMPARATORS
AND
FAULT LATCHES
OVLO
1VREF
RBOV
TEMP
0.8µH
10µF
COUT(BULK)
VOUT
0.6V TO 6V
UP TO 10A
COUT(MLCC)
SGND
TMR
LATCH
FCB
COMP
DRVCC
FAST OUTPUT
OVERVOLTAGE
COMPARATOR
INTVCC
ENABLE
COVPGM
INTERNAL
COMP
499k
MCB
C
VORB–
+
REF
4µF
OVPGM
R
–
1VREF
CROWBAR
8.2k
TRACK/SS
RBOVPGM
+
MBOT
VFB
TO E/A
PGOOD
RTOVPGM
VINH
GND
OTBH
CSS
MSP
VINGP
VOUT
3.48k
OSC
CIN(BULK)
SW
NTC
CTMR
+
2.2µF
MTOP
RTOV
CIN(MLCC)
RfSET*
fSET
POWER
CONTROL
VIN
1.3M
ION
VIN
4V TO 38V
(4.5V START-UP)
8.2k
VOSNS–
8.2k
VOSNS+
8.2k
RSET1B
RSET2
RSET1A
VORB+
R
2 • RSET1A
VOUT = 0.6 1+ SET1A +
RSET2
8.2kΩ
1M
RUN
DASHED BOXES INDICATE OPTIONAL COMPONENTS
*RfSET REQUIRED FOR CERTAIN VIN/VOUT COMBINATIONS
SEE APPLICATIONS INFORMATION SECTION
SGND CONNECTS TO GND INTERNAL TO MODULE, KEEP SGND
ROUTES/PLANES SEPARATE FROM GND, ON MOTHERBOARD
4641 F01
USE RSET1A = RSET1B ≤8.2k
RSET2 REQUIRED FOR VOUT > 1.2V
RSET2 NOT NECESSARY FOR VOUT ≤ 1.2V
Figure 1. Simplified Block Diagram. cf. Functional Block Diagram in Appendix A, Figure 62
Decoupling Requirements
SYMBOL
PARAMETER
CONDITIONS
CIN(MLCC) +
CIN(BULK)
External Input Capacitor Requirement
IOUT = 10A, 2 × 10μF or 4 × 4.7μF
MIN
TYP
20
MAX
UNITS
μF
COUT(MLCC) +
COUT(BULK)
External Output Capacitor Requirement
IOUT = 10A, 3 × 100μF or 6 × 47μF
300
μF
4641fe
For more information www.linear.com/LTM4641
15
LTM4641
Operation
Introduction
Power µModule Regulator Reliability
The LTM4641 contains a buck-topology regulator employing a constant on-time current mode control scheme,
including built-in power MOSFET devices with fast
switching speed and a power inductor. In its most basic
configuration (see Figure 45), the module operates as a
standalone nonisolated switching mode DC/DC step-down
power supply. It can provide up to 10A of output current
with a few external input and output capacitors and output
feedback resistors. The supported output voltage range is
from 0.6V DC to 6V DC. The supported input voltage range
is 4V to 38V, with a maximum start-up voltage of 4.5V
(over temperature). Power conversion from lower input
voltages can be realized if an auxiliary bias supply is available to power LTM4641’s control and housekeeping bias
input pin, VINL. The LTM4641 Simplified Block Diagram is
found in Figure 1. For a more detailed look, the Functional
Block Diagram is found in Appendix A, Figure 62.
First and foremost, Linear Technology μModule products
adhere to rigorous testing and high reliability control,
fabrication, and manufacturing processes—as is required
of all its products. Furthermore, as part of its commitment to excellence, the Linear Technology Quality Control
program periodically updates its Reliability Data report
for LTM4600 series products to include cumulative data
obtained from ongoing and routine in-house testing relating
to operational life, highly accelerated stress, power and
temperature cycling, thermal and mechanical shock, and
much more. To view the latest report visit http://www.
linear.com/docs/13557.
The LTM4641 easily supports high step-down ratios
with few external components. The additional protection
features when implemented provide an extra degree of
insurance beyond other μModule regulators.
Overview
Motivation
Pulsed loading conditions and abnormal disturbances
within the electrical systems found in industrial, vehicle,
aeronautic, and military applications can induce wildly
varying voltage transients (surges) on what is nominally
a 24V DC to 28V DC distributed bus (28V DC bus). The
duration of such disturbances can extend for periods of
time between a millisecond to a minute in length, with
excursions sometimes reaching (or exceeding) 40V and
falling below 6V.
While switching buck regulators are of universal interest due to their compact size and ability to deliver DC/
DC power conversion at high efficiency, FMEA (failure
modes and effects analysis) leads one to believe that
there is no way to reduce the severity rating and effects
of an electrical short from the input source to the output
load—however improbable. The LTM4641 challenges
this notion by protecting the load from seeing excessive
voltage stress, even when its high side switching MOSFET
is short circuited.
When configured as shown in Figure 46, the LTM4641
can regulate an output voltage between 0.6V and 6V from
an input voltage between 4V and 38V (4.5VIN start-up,
maximum).
If an optional N-channel power MOSFET, MSP, is placed
between the input power source (VIN) and the power
stage input pins (VINH), MSP’s role becomes that of a
resettable electronic power-interrupt switch. The gate of
MSP is operated by VING, and its gate-to-source voltage
is assured to be clamped by a built-in 15V Zener diode
accessed via VINGP. When switching action is engaged,
VING charges the gate of MSP to nominally 10V above
VINH potential—suitable for driving a standard-logic MOSFET—and MSP becomes enhanced to pull VINH up to the
input source supply’s electrical potential. The switching
regulator steps down VINH potential to VOUT when MSP is
on. When switching action is inhibited by pulling the RUN
pin low or when a fault condition is detected by LTM4641’s
internal circuitry—such as an output overvoltage (OOV)
condition—the gate of MSP is discharged and MSP turns
off. The input source supply is thus disconnected from
LTM4641’s power stage input (VINH).
4641fe
16
For more information www.linear.com/LTM4641
LTM4641
Applications Information—Power Supply Features
The operation of MSP as a power interrupter provides a
critical element of robust OOV protection: it removes a
means for input power to flow through a damaged power
stage to any precious loads on the output voltage rail, even
when input power is cycled.
• Selectable pulse-skipping mode operation
• Output voltage soft-start and rail tracking
• Power-up into pre-biased conditions without sinking
current from the output capacitors
• Adjustable switching frequency
For even greater resilience to a short-circuit between VINH
and the SW switching node of the power stage, an external
logic-level N-channel power MOSFET, MCB, is optionally
placed—in a crowbar configuration—on the output of
the power module. When an OOV condition is detected,
CROWBAR turns on MCB (within 500ns, maximum) to
discharge the output capacitors and transform any residual
energy in LTM4641’s power stage into a trivial amount of
heat—energy which would otherwise have only served to
inject charge into (further pump up the voltage on) the
output capacitors, where precious loads reside.
Novel and simple circuit implementations with LTM4641
and a few external components enable surge ride-through
protection and overtemperature detection of a powerinterrupt MOSFET. (See Figure 47, for example.) The
aforementioned features enabled by LTM4641 are grouped
by function and described in the remainder of the Applications Information section.
The control and monitoring circuitry within the LTM4641
power module provide the following:
Power (VINH) and Bias (VINL) Input Pins
• Fast, accurate, latching output overvoltage detector
( 4.05V. In the circuits of Figures 45 and
46, this is guaranteed for VINL ≥ 4.5V, minimum. In
Figure 49, this requirement is met when the auxiliary
bias supply exceeds 4.05V.
b. UVLO > 500mV
The UVLO, IOVRETRY and OVLO pins do not require any
filter capacitance due to built-in filtering in the LTM4641’s
housekeeping IC. This results in glitch immunity with
characteristics shown in Figure 12.
600
500
The LTM4641 powers up its output when the following
conditions are met:
RESPECTIVE
FAULT CONDITION
BECOMES DETECTED
400
300
200
100
GLITCH
IGNORED
0
1
10
100
0.1
COMPARATOR OVERDRIVE PAST THRESHOLD (%)
4641 F12
Figure 12. Transient Duration vs Comparator Overdrive
Glitch Immunity Characteristics. Monitored Signals: UVLO,
IOVRETRY, OVLO, TEMP, CROWBAR and DRVCC
Start-Up/Shutdown and Run Enable; Power-On Reset
and Timeout Delay Time
The LTM4641 is a feature-rich and versatile self-contained
DC/DC converter system, and includes multiple on-board
supply monitors. The inputs to several monitors are available to the user for system customization (UVLO, OVLO,
IOVRETRY and TEMP).
c. IOVRETRY < 500mV
d. TEMP > 514mV (when OTBH is electrically open
circuit)
• No latchoff fault conditions are present, and the
LTM4641 is not in a “latched off” state from any previously detected latchoff fault condition. If a latchoff
fault condition occurs/occurred, the LTM4641 must
be unlatched by a logic high LATCH signal: if all latchoff fault-monitoring pins are in operationally valid
states when LATCH transitions from logic low to high,
the LTM4641 becomes immediately unlatched; if, instead, any latchoff fault-monitoring pin is outside its
operationally valid state when LATCH is logic high, the
LTM4641 becomes unlatched if LATCH remains logic
high after all latchoff fault-monitoring pins have been
in their operationally valid states for the full duration of
the timeout delay time (set optionally by CTMR). Explicit
pins and operationally valid thresholds follow:
a. OVLO < 500mV
b. TEMP > 514mV (when OTBH is logic low)
c. CROWBAR < 1.5V
The POR and timeout delay time is 9ms per nanofarad
of CTMR capacitance. If CTMR is not used, the POR and
timeout delay time is ~90μs.
For more information www.linear.com/LTM4641
4641fe
31
LTM4641
Applications Information—Load Protection Features
If any nonlatching fault conditions occur, internal circuitry
pulls HYST low and switching action is inhibited. The power
stage will be high impedance until the aforementioned startup conditions are met. If any latchoff fault condition occurs,
HYST is latched low and switching action is inhibited until
the LTM4641 is unlatched (by pulling LATCH logic high)
or VINL power is recycled (with INTVCC falling below 2V).
The LTM4641 can be configured to restart autonomously
after an adjustable timeout delay time—instead of exhibiting latchoff behavior—by leaving LATCH logic high (connected to INTVCC, for example) and setting the hiccup retry
timeout delay time with CTMR (see Figure 47). Be reminded
that use of CTMR also introduces POR behavior, yet the POR
and timeout delay timers operate independently. The effect
of CTMR can be negated by pulling the TMR pin to INTVCC.
Switching action will be inhibited if any of the following
occur:
• RUN is less than 1.15V (nominal; 0.8V, overtemperature). Not a fault; no POR or timeout delay time is
imposed.
• Any nonlatching faults occur:
a. DRVCC falls below 3.35V. In the Figure 45 and
Figure 46 circuits, this happens at VINL < 4V, maximum.
b. UVLO falls below 0.5V.
c. IOVRETRY exceeds 0.5V.
d. TEMP falls below 438mV when OTBH is electrically
open circuit.
• Any latchoff faults occur:
a. OVLO exceeds 0.5V.
b. CROWBAR exceeds 1.5V.
c. TEMP falls below 438mV when OTBH is logic low.
The LTM4641’s state diagram is provided in Appendix B.
Start-up and shutdown mechanisms for any given operating scenario are identified in the state diagram. The
TEMP and DRVCC pins have built-in hysteresis. The UVLO,
IOVRETRY, OVLO, TEMP, CROWBAR and DRVCC pins
connect to comparators with built-in glitch immunity, with
characteristics indicated in Figure 12.
Overcurrent Foldback Protection
The LTM4641 has overcurrent protection (OCP). In a short
circuit from VOUT to GND, the internal current comparator
threshold folds back during a short to reduce the output
current, progressively down to about one-third of its normal value (down from 24A to 8A, typical). To recover from
foldback current limit, the excessive load or low impedance short needs to be removed. Foldback current limiting
action is disabled during soft-start and tracking start-up.
Power Good Indicator and Latching Output
Overvoltage Protection
Internal overvoltage and undervoltage comparators assert
the open-drain PGOOD output logic low if the output voltage
is outside ±10% of nominal, after a 12μs “blanking time”.
The blanking time allows the output voltage to experience
brief excursions (due to large load-step transients, for
example) without nuisance-tripping PGOOD. The PGOOD
output is deasserted without any deliberate blanking time
when the output voltage returns to (or enters) the power
good window, with ~2% to 3% of hysteresis. If the feedback voltage exceeds the upper PGOOD valid limit, the
synchronous power MOSFET, MBOT, turns on (with no
blanking time)—to try sinking current from the output
to GND, through LTM4641’s power inductor—until the
output voltage returns to the PGOOD valid region. If the
output voltage exceeds an adjustable threshold set by
OVPGM, whose default value corresponds to 11% above
nominal, the LTM4641 pulls its CROWBAR output logic
high immediately (500ns response time, maximum) and
latches off its output voltage: the power stage becomes
high impedance, with both MTOP and MBOT turning off and
staying latched off; furthermore, MSP’s gate is pulled to
VINH potential rapidly ( 1.2V, select RSET1A not larger than that given by:
RSET1A = RSET1B =
8.2kΩ
n
(33)
Then, determine RSET2 by:
RSET2 =
2 • RSET1A
VOUT
R
– n • SET1A – 1
0.6
8.2kΩ
(34)
The output voltage setting can be double-checked by:
R
2 • RSET1A
VOUT = 0.6V 1+ n • SET1A +
8.2kΩ
RSET2
(35)
The voltage on the VOSNS+ pins of the modules during
regulation become:
∆V
0.6V
VVOSNS+ =
+ GND (36)
8.2kΩ || RSET1A || RSET2 RSET1A
n
16.4kΩ
• RSET1A ||
n
In multimodule parallel scenarios, VOSNS– and ∆VGND are
still given by Equations 12 and 13, respectively.
Lastly, be aware that the total charge current on the
TRACK/SS net will be n • 1μA.
4641fe
For more information www.linear.com/LTM4641
37
LTM4641
Applications Information—Thermal Considerations and
Output Current Derating
Thermal Considerations and Output Current Derating
The thermal resistances reported in the Pin Configuration
section of the data sheet are consistent with those parameters defined by JESD51-12 and are intended for use with
finite element analysis (FEA) software modeling tools that
leverage the outcome of thermal modeling, simulation,
and correlation to hardware evaluation performed on a
µModule package mounted to a hardware test board defined by JESD51-9 (“Test Boards for Area Array Surface
Mount Package Thermal Measurements”). The motivation
for providing these thermal coefficients is found in JESD
51-12 (“Guidelines for Reporting and Using Electronic
Package Thermal Information”).
Many designers may opt to use laboratory equipment and a
test vehicle such as the demo board to predict the µModule
regulator’s thermal performance in their application at
various electrical and environmental operating conditions
to compliment any FEA activities. Without FEA software,
the thermal resistances reported in the Pin Configuration
section are in-and-of themselves not relevant to providing
guidance of thermal performance; instead, the derating
curves provided later in this data sheet can be used in
a manner that yields insight and guidance pertaining to
one’s application-usage, and can be adapted to correlate
thermal performance to one’s own application.
The Pin Configuration section gives four thermal coefficients explicitly defined in JESD 51-12; these coefficients
are quoted or paraphrased below:
1 θJA, the thermal resistance from junction to ambient, is
the natural convection junction-to-ambient air thermal
resistance measured in a one cubic foot sealed enclosure. This environment is sometimes referred to as “still
air” although natural convection causes the air to move.
This value is determined with the part mounted to a
JESD 51-9 defined test board, which does not reflect
an actual application or viable operating condition.
2 θJCbottom, the thermal resistance from junction to the
bottom of the product case, is determined with all of
the component power dissipation flowing through the
bottom of the package. In the typical µModule regulator,
the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient
environment. As a result, this thermal resistance value
may be useful for comparing packages but the test
conditions don’t generally match the user’s application.
3 θJCtop, the thermal resistance from junction to top of
the product case, is determined with nearly all of the
component power dissipation flowing through the top of
the package. As the electrical connections of the typical
µModule regulator are on the bottom of the package, it
is rare for an application to operate such that most of
the heat flows from the junction to the top of the part.
As in the case of θJCbottom, this value may be useful
for comparing packages but the test conditions don’t
generally match the user’s application.
4 θJB, the thermal resistance from junction to the printed
circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the
bottom of the µModule regulator and into the board,
and is really the sum of the θJCbottom and the thermal
resistance of the bottom of the part through the solder
joints and through a portion of the board. The board
temperature is measured a specified distance from the
package, using a two sided, two layer board. This board
is described in JESD 51-9.
A graphical representation of the aforementioned thermal
resistances is given in Figure 17; blue resistances are
contained within the µModule regulator, whereas green
resistances are external to the µModule package.
As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
4641fe
38
For more information www.linear.com/LTM4641
LTM4641
Applications Information—Thermal Considerations and
Output Current Derating
parameters defined by JESD 51-12 or provided in the
Pin Configuration section replicates or conveys normal
operating conditions of a µModule regulator. For example,
in normal board-mounted applications, never does 100%
of the device’s total power loss (heat) thermally conduct
exclusively through the top or exclusively through bottom of the µModule package—as the standard defines
for θJCtop and θJCbottom, respectively. In practice, power
loss is thermally dissipated in both directions away from
the package—granted, in the absence of a heat sink and
airflow, a majority of the heat flow is into the board.
Within the LTM4641, be aware there are multiple power
devices and components dissipating power, with a consequence that the thermal resistances relative to different
junctions of components or die are not exactly linear with
respect to total package power loss. To reconcile this
complication without sacrificing modeling simplicity—but
also, not ignoring practical realities—an approach has been
taken using FEA software modeling along with laboratory
testing in a controlled-environment chamber to reasonably define and correlate the thermal resistance values
supplied in this data sheet: (1) Initially, FEA software is
used to accurately build the mechanical geometry of the
LTM4641 and the specified PCB with all of the correct
material coefficients along with accurate power loss source
definitions; (2) this model simulates a software-defined
JEDEC environment consistent with JSED 51-9 and
JESD 51-12 to predict power loss heat flow and temperature
readings at different interfaces that enable the calculation
of the JEDEC-defined thermal resistance values; (3) the
model and FEA software is used to evaluate the LTM4641
with heat sink and airflow; (4) having solved for and
analyzed these thermal resistance values and simulated
various operating conditions in the software model, a
thorough laboratory evaluation replicates the simulated
conditions with thermocouples within a controlled environment chamber while operating the device at the same
power loss as that which was simulated. The outcome of
this process and due diligence yields the set of derating
curves provided in later sections of this data sheet, along
with well-correlated JESD51-12-defined θ values provided
in the Pin Configuration section of this data sheet.
The 6V, 3.3V and 1.5V power loss curves in Figures 18,
19 and 20 respectively can be used in coordination with
the load current derating curves in Figures 21 to 42 for
calculating an approximate θJA thermal resistance for the
LTM4641 with various heat sinking and air flow conditions.
These thermal resistances represent demonstrated
JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)
JUNCTION-TO-CASE (TOP)
RESISTANCE
JUNCTION
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION-TO-CASE
CASE (BOTTOM)-TO-BOARD
(BOTTOM) RESISTANCE
RESISTANCE
AMBIENT
BOARD-TO-AMBIENT
RESISTANCE
4641 F17
µMODULE DEVICE
Figure 17. Graphical Representation of JESD51-12 Thermal Coefficients
4641fe
For more information www.linear.com/LTM4641
39
LTM4641
Applications Information—Thermal Considerations and
Output Current Derating
performance of the LTM4641 on DC1543 hardware; a
4-layer FR4 PCB measuring 96mm × 87mm × 1.6mm using
outer and inner copper weights of 2oz and 1oz, respectively.
The power loss curves are taken at room temperature,
and are increased with multiplicative factors with ambient
temperature. These approximate factors are listed in Table 3.
(Compute the factor by interpolation, for intermediate
temperatures.) The derating curves are plotted with the
output current starting at 10A and the ambient temperature
at 40°C. The output voltages are 6V, 3.3V and 1.5V. These are
chosen to include the lower and higher output voltage ranges
for correlating the thermal resistance. Thermal models
are derived from several temperature measurements in
a controlled temperature chamber along with thermal
modeling analysis. The junction temperatures are
monitored while ambient temperature is increased with and
without air flow, and with and without a heat sink attached
with thermally conductive adhesive tape. The BGA heat
sinks evaluated in Table 7 (and attached to the LTM4641
with thermally conductive adhesive tape listed in Table 8)
yield very comparable performance in laminar airflow
despite being visibly different in construction and form
factor. The power loss increase with ambient temperature
change is factored into the derating curves. The junctions
are maintained at 120°C maximum while lowering output
current or power while increasing ambient temperature. The
decreased output current will decrease the internal module
loss as ambient temperature is increased. The monitored
junction temperature of 120°C minus the ambient operating
temperature specifies how much module temperature
rise can be allowed. As an example in Figure 38, the load
current is derated to ~8A at ~81°C ambient with no air or
heat sink and the power loss for this 36VIN to 1.5VOUT at
8AOUT condition is ~3.1W. The 3.74W loss is calculated
with the ~3.1W room temperature loss from the 36VIN to
1.5VOUT power loss curve at 8A (Figure 20), and the 1.205
multiplying factor at 81°C ambient (interpolating from
Table 3). If the 81°C ambient temperature is subtracted
from the 120°C junction temperature, then the difference
of 39°C divided by 3.74W yields a thermal resistance, θJA,
of 10.4°C/W—in good agreement with Table 6. Tables 4,
5 and 6 provide equivalent thermal resistances for 6V,
3.3V and 1.5V outputs with and without air flow and heat
sinking. The derived thermal resistances in Tables 4, 5
and 6 for the various conditions can be multiplied by the
calculated power loss as a function of ambient temperature
to derive temperature rise above ambient, thus maximum
junction temperature. Room temperature power loss
can be derived from the efficiency curves in the Typical
Performance Characteristics section and adjusted with the
above ambient temperature multiplicative factors.
Table 3. Power Loss Multiplicative Factors vs Ambient
Temperature
AMBIENT TEMPERATURE
POWER LOSS MULTIPLICATIVE
FACTOR
Up to 40°C
1.00
50°C
1.05
60°C
1.10
70°C
1.15
80°C
1.20
90°C
1.25
100°C
1.30
110°C
1.35
120°C
1.40
4641fe
40
For more information www.linear.com/LTM4641
LTM4641
Applications Information—Thermal Considerations and
Output Current Derating
6
8
7
4.5
4.0
5
3.5
4
3
2
3
2
36VIN
24VIN
12VIN
1
0
1
2
3 4 5 6 7 8
OUTPUT CURRENT (A)
9
POWER LOSS (W)
5
0
4
POWER LOSS (W)
36VIN
24VIN
12VIN
6VIN
1
0
10
0
1
2
3 4 5 6 7 8
OUTPUT CURRENT (A)
4641 F18
1.5
36VIN
24VIN
12VIN
6VIN
1.0
0.5
0
10
10
9
9
8
8
8
4
3
2
400LFM
200LFM
0LFM
1
0
40
50
MAXIMUM LOAD CURRENT (A)
10
5
7
6
5
4
3
2
400LFM
200LFM
0LFM
1
0
60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
40
50
5
4
3
2
0
4146 F23
9
8
8
MAXIMUM LOAD CURRENT (A)
10
9
3
2
400LFM
200LFM
0LFM
1
0
40
50
6
5
4
3
2
400LFM
200LFM
0LFM
1
60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4146 F24
Figure 24. 12VIN to 6VOUT with Heat
Sink, fSW = 660kHz at Full Load
60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
Figure 23. 36VIN to 6VOUT, No Heat
Sink, fSW = 660kHz at Full Load
10
4
50
4146 F22
9
5
400LFM
200LFM
0LFM
40
10
6
0
40
50
8
7
6
5
4
3
2
400LFM
200LFM
0LFM
1
60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4146 F25
Figure 25. 24VIN to 6VOUT with Heat
Sink, fSW = 660kHz at Full Load
For more information www.linear.com/LTM4641
10
9
7
Figure 22. 24VIN to 6VOUT, No Heat
Sink, fSW = 660kHz at Full Load
7
8
6
1
60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4146 F21
Figure 21. 12VIN to 6VOUT, No Heat
Sink, fSW = 660kHz at Full Load
7
3 4 5 6 7
OUTPUT CURRENT (A)
4641 F20
9
7
2
Figure 20. 1.5VOUT Power Loss,
fSW = 315kHz at Full Load,
FCB Tied to SGND
10
6
1
0
Figure 19. 3.3VOUT Power Loss,
fSW = 360kHz at Full Load,
FCB Tied to SGND
MAXIMUM LOAD CURRENT (A)
MAXIMUM LOAD CURRENT (A)
2.0
4146 F19
Figure 18. 6VOUT Power Loss,
fSW = 660kHz at Full Load,
FCB Tied to SGND
MAXIMUM LOAD CURRENT (A)
9
3.0
2.5
MAXIMUM LOAD CURRENT (A)
POWER LOSS (W)
6
0
40
50
60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4146 F26
Figure 26. 36VIN to 6VOUT with Heat
Sink, fSW = 660kHz at Full Load
4641fe
41
LTM4641
10
10
10
9
9
9
7
6
5
4
3
2
400LFM
200LFM
0LFM
1
0
40
50
8
7
6
5
4
3
2
400LFM
200LFM
0LFM
1
0
60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
40
50
6
5
4
3
2
0
Figure 28. 12VIN to 3.3VOUT No Heat
Sink, fSW = 360kHz at Full Load
9
8
8
8
4
3
2
400LFM
200LFM
0LFM
1
0
40
50
7
6
5
4
3
2
400LFM
200LFM
0LFM
1
0
60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
MAXIMUM LOAD CURRENT (A)
10
9
MAXIMUM LOAD CURRENT (A)
10
5
40
50
7
5
4
3
2
0
8
8
2
400LFM
200LFM
0LFM
1
0
40
50
4146 F33
Figure 33. 24VIN to 3.3VOUT with Heat
Sink, fSW = 360kHz at Full Load
42
7
6
5
4
3
2
400LFM
200LFM
0LFM
1
60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
MAXIMUM LOAD CURRENT (A)
9
8
MAXIMUM LOAD CURRENT (A)
10
9
3
50
60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4146 F32
10
4
40
Figure 32. 12VIN to 3.3VOUT, with Heat
Sink, fSW = 360kHz at Full Load
9
5
400LFM
200LFM
0LFM
4146 F31
Figure 31. 6VIN to 3.3VOUT, with Heat
Sink, fSW = 360kHz at Full Load
10
7
60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
6
1
60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4146 F30
Figure 30. 36VIN to 3.3VOUT, No Heat
Sink, fSW = 360kHz at Full Load
6
50
Figure 29. 24VIN to 3.3VOUT No Heat
Sink, fSW = 360kHz at Full Load
9
7
40
4146 F29
10
6
400LFM
200LFM
0LFM
4146 F28
Figure 27. 6VIN to 3.3VOUT No Heat
Sink, fSW = 360kHz at Full Load
MAXIMUM LOAD CURRENT (A)
8
7
1
60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4146 F27
MAXIMUM LOAD CURRENT (A)
MAXIMUM LOAD CURRENT (A)
8
MAXIMUM LOAD CURRENT (A)
MAXIMUM LOAD CURRENT (A)
Applications Information—Thermal Considerations and
Output Current Derating
0
40
50
7
6
5
4
3
2
400LFM
200LFM
0LFM
1
60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4146 F34
Figure 34. 36VIN to 3.3VOUT with Heat
Sink, fSW = 360kHz at Full Load
For more information www.linear.com/LTM4641
0
40
50
60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4146 F35
Figure 35. 6VIN to 1.5VOUT No Heat
Sink, fSW = 315kHz at Full Load
4641fe
LTM4641
9
9
8
8
7
6
5
4
3
2
400LFM
200LFM
0LFM
1
0
40
50
10
9
7
6
5
4
3
2
400LFM
200LFM
0LFM
1
60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
MAXIMUM LOAD CURRENT (A)
10
MAXIMUM LOAD CURRENT (A)
10
0
40
50
10
10
9
9
6
5
4
3
2
400LFM
200LFM
0LFM
1
0
40
50
2
400LFM
200LFM
0LFM
40
50
60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4146 F40
Figure 40. 12VIN to 1.5VOUT, with
Heat Sink, fSW = 315kHz at Full Load
8
MAXIMUM LOAD CURRENT (A)
9
8
400LFM
200LFM
0LFM
1
0
40
50
7
6
5
4
3
2
400LFM
200LFM
0LFM
1
60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
0
40
50
4146 F41
Figure 41. 24VIN to 1.5VOUT, with Heat
Sink, fSW = 315kHz at Full Load
60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
3
10
2
50
4
9
3
40
5
10
4
400LFM
200LFM
0LFM
6
4146 F39
Figure 39. 6VIN to 1.5VOUT, with Heat
Sink, fSW = 315kHz at Full Load
5
2
8
0
60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
7
3
7
1
6
4
Figure 38. 36VIN to 1.5VOUT No Heat
Sink, fSW = 315kHz at Full Load
Figure 37. 24VIN to 1.5VOUT No Heat
Sink, fSW = 315kHz at Full Load
7
5
4146 F38
4146 F37
8
6
0
60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
MAXIMUM LOAD CURRENT (A)
MAXIMUM LOAD CURRENT (A)
Figure 36. 12VIN to 1.5VOUT No Heat
Sink, fSW = 315kHz at Full Load
8
7
1
4146 F36
MAXIMUM LOAD CURRENT (A)
MAXIMUM LOAD CURRENT (A)
Applications Information—Thermal Considerations and
Output Current Derating
60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4146 F42
Figure 42. 36VIN to 1.5VOUT with Heat
Sink, fSW = 315kHz at Full Load
4641fe
For more information www.linear.com/LTM4641
43
LTM4641
Applications Information—Thermal Considerations and
Output Current Derating
Table 4. 6V Output, Switching Frequency Nominally 660kHz at Full Load
DERATING CURVE
VIN
POWER LOSS CURVE
AIRFLOW (LFM)
HEAT SINK
θJA (°C/W)
Figure 21 to Figure 23
12V, 24V, 36V
Figure 18
0
None
10.1
Figure 21 to Figure 23
12V, 24V, 36V
Figure 18
200
None
8.2
Figure 21 to Figure 23
12V, 24V, 36V
Figure 18
400
None
6.8
Figure 24 to Figure 26
12V, 24V, 36V
Figure 18
0
BGA Heat Sink
8.1
Figure 24 to Figure 26
12V, 24V, 36V
Figure 18
200
BGA Heat Sink
6.5
Figure 24 to Figure 26
12V, 24V, 36V
Figure 18
400
BGA Heat Sink
5.5
Table 5. 3.3V Output, Switching Frequency Nominally 360kHz at Full Load
DERATING CURVE
VIN
POWER LOSS CURVE
AIRFLOW (LFM)
HEAT SINK
θJA (°C/W)
Figure 27 to Figure 30
6V, 12V, 24V, 36V
Figure 19
0
None
10.4
Figure 27 to Figure 30
6V, 12V, 24V, 36V
Figure 19
200
None
8.4
Figure 27 to Figure 30
6V, 12V, 24V, 36V
Figure 19
400
None
7.1
Figure 31 to Figure 34
6V, 12V, 24V, 36V
Figure 19
0
BGA Heat Sink
8.6
Figure 31 to Figure 34
6V, 12V, 24V, 36V
Figure 19
200
BGA Heat Sink
6.8
Figure 31 to Figure 34
6V, 12V, 24V, 36V
Figure 19
400
BGA Heat Sink
5.8
Table 6. 1.5V Output, Switching Frequency Nominally 315kHz at Full Load
DERATING CURVE
VIN
POWER LOSS CURVE
AIRFLOW (LFM)
HEAT SINK
θJA (°C/W)
Figure 35 to Figure 38
6V, 12V, 24V, 36V
Figure 20
0
None
10.3
Figure 35 to Figure 38
6V, 12V, 24V, 36V
Figure 20
200
None
8.4
Figure 35 to Figure 38
6V, 12V, 24V, 36V
Figure 20
400
None
7.2
Figure 39 to Figure 42
6V, 12V, 24V, 36V
Figure 20
0
BGA Heat Sink
9.0
Figure 39 to Figure 42
6V, 12V, 24V, 36V
Figure 20
200
BGA Heat Sink
7.0
Figure 39 to Figure 42
6V, 12V, 24V, 36V
Figure 20
400
BGA Heat Sink
5.8
Table 7. Heat Sink Vendors (with Thermally Conductive Adhesive Tape Pre-Attached)
HEAT SINK MANUFACTURER
PART NUMBER
WEBSITE
Wakefield Engineering
LTN20069
www.wakefield.com
Aavid Thermalloy
375424B00034G
www.aavid.com
Table 8. Thermally Conductive Adhesive Tape Vendor
THERMALLY CONDUCTIVE ADHESIVE
TAPE MANUFACTURER
PART NUMBER
WEBSITE
Chomerics
T411
www.chomerics.com
4641fe
44
For more information www.linear.com/LTM4641
LTM4641
Applications Information—Output Capacitance Table
Table 9. Transient Performance (Typical Values) vs Recommended Output Capacitance. Figure 45 and Figure 46 Circuits
COUT(MLCC)
COUT(BULK)
VOUT
VENDOR
PART NUMBER
VENDOR
≤ 3.3V
AVX
12106D107MAT2A (100µF, 6.3V, 1210 Case Size)
12066D226MAT2A (22µF, 6.3V, 1206 Case Size)
Sanyo POSCAP 6TPE680MI (680µF, 6.3V, 18mΩ ESR, D4 Case Size)
Taiyo Yuden
JMK325BJ107MM-T (100µF, 6.3V, 1210 Case Size)
JMK316BJ226ML-T (22µF, 6.3V, 1206 Case Size)
TDK
C3225X5R0J107MT (100µF, 6.3V, 1210 Case Size)
C3216X5R0J226MT (22µF, 6.3V, 1206 Case Size)
> 3.3V
VOUT
(V)
0.9
AVX
1206YD226MAT2A (22µF, 16V, 1206 Case Size)
Taiyo Yuden
LMK316BJ476ML-T (47µF, 10V, 1206 Case Size)
EMK316BJ226ML-T (22µF, 16V, 1206 Case Size)
TDK
C3216X5R1A476M (47µF, 10V, 1206 Case Size)
C3216X5R1C226M (22µF, 16V, 1206 Case Size)
VIN (V)
PART NUMBER
Sanyo POSCAP 10TPF150ML (150µF, 10V, 15mΩ ESR, D3L Case Size)
LOAD
STEP TRANSIENT
TRANSIENT,
SLEW DROOP, 0A PEAK-TO-PEAK,
RSET1A,
CIN
CIN*
COUT2
COUT1 CFFA, RATE TO 5A LOAD 0A TO 5A TO 0A RECOVERY
RfSET RSET1B RSET2
(MΩ) (kΩ) (kΩ) (CERAMIC) (BULK) (CERAMIC) (BULK) CFFB (A/µs) STEP (mV) STEP (mVPK-PK) TIME (µs)
5, 12, 24, 36 0.931
4.12
–
2 × 10µF
100µF
3 × 22µF
680µF
–
5
60
130
25
5, 12, 24, 36 0.931
4.12
–
2 × 10µF
100µF
4 × 100µF
–
–
5
60
140
25
1
5, 12, 24, 36
1.00
5.49
–
2 × 10µF
100µF
3 × 22µF
680µF
–
5
65
135
25
1
5, 12, 24, 36
1.00
5.49
–
2 × 10µF
100µF
4 × 100µF
–
–
5
70
150
25
1.2
5, 12, 24, 36
1.13
8.2
–
2 × 10µF
100µF
3 × 22µF
680µF
–
5
70
140
25
1.2
5, 12, 24, 36
1.13
8.2
–
2 × 10µF
100µF
4 × 100µF
–
–
5
80
170
30
1.5
5, 12, 24, 36
1.43
8.2
33.2
2 × 10µF
100µF
3 × 22µF
680µF
–
5
75
155
30
1.5
5, 12, 24, 36
1.43
8.2
33.2
2 × 10µF
100µF
4 × 100µF
–
220pF
5
90
190
30
1.8
5, 12, 24, 36
2.00
8.2
16.5
2 × 10µF
100µF
3 × 22µF
680µF
–
5
80
170
40
1.8
5, 12, 24, 36
2.00
8.2
16.5
2 × 10µF
100µF
3 × 100µF
–
220pF
5
100
215
30
2.5
5, 12, 24, 36
5.76
8.2
7.5
2 × 10µF
100µF
3 × 22µF
680µF
–
5
100
230
50
2.5
5, 12, 24, 36
5.76
8.2
7.5
2 × 10µF
100µF
3 × 100µF
–
220pF
5
140
290
30
3.3
5, 12, 24, 36
–
8.2
4.7
2 × 10µF
100µF
3 × 22µF
680µF
–
5
140
275
60
3.3
5, 12, 24, 36
–
8.2
4.7
2 × 10µF
100µF
3 × 100µF
–
100pF
5
200
420
30
5
12, 24, 36
–
8.2
2.61
2 × 10µF
100µF
2 × 22µF
150µF 220pF
5
12, 24, 36
–
8.2
2.61
2 × 10µF
100µF
3 × 47µF
6
12, 24, 36
–
8.2
2.05
2 × 10µF
100µF
2 × 22µF
6
12, 24, 36
–
8.2
2.05
2 × 10µF
100µF
3 × 47µF
0.9
5
220
450
50
100pF
5
250
570
30
150µF 220pF
5
240
500
55
5
300
660
30
–
–
100pF
*Bulk Capacitance is optional if VIN has very low input impedance.
4641fe
For more information www.linear.com/LTM4641
45
LTM4641
Applications Information—Safety and Layout Guidance
Safety Considerations
The LTM4641 modules do not provide galvanic isolation
from VIN to VOUT. There is no internal fuse. If fusing is
required, a slow blow fuse with a rating twice the maximum
input current needs to be provided. The LTM4641 supports overcurrent protection and two kinds of overvoltage
protection (see the Power Good Indicator and Latching
Output Overvoltage Protection section).
Layout Checklist/Example
The high integration of LTM4641 makes the PCB board
layout very straightforward. To optimize its electrical and
thermal performance, some layout considerations are
necessary. Figure 43 and Figure 44 show recommended
layouts for the circuits shown in Figure 45 and Figure 46,
respectively.
• Refer to the following document for device land pattern
and stencil design: http://www.linear.com/docs/40146.
• The gerber file for demo board DC1543 can be downloaded at http://www.linear.com/demo
• Use a solid copper GND plane directly underneath the
module. This will help form the return path electrical
connections to the input source and output load. It will
also provide a thermal path for removing heat from the
BGA package and minimize junction temperature rise
of the LTM4641 for a given application. For consistent
ripple and noise from application to application, connect
the output GND plane (the one that conducts load side
return current back to the module) and the input GND
plane (the one that conducts module return current
back to the input source) underneath the module, only.
• Use large PCB copper areas for high current paths,
including VINH and VOUT.
• Place high frequency ceramic input and output capacitors next to the VINH, GND and VOUT pins to minimize
high frequency noise. VINH exception: If MSP is used,
(1) place MSP as close to the VINH pins of the LTM4641
as possible and (2) bypass the drain of MSP—and not
VINH—to GND pins of the LTM4641. Only one or two
high frequency MLCCs (COUT(MLCC)) need be placed
directly next to the VOUT and GND pins of the LTM4641,
to minimize high frequency noise close to the source.
The majority of COUT(MLCC) should be located close to
the load to provide high quality bypassing.
• To minimize the via conduction loss and reduce module
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
• Do not put vias directly under any pads, unless they
are capped or plated over.
• Use a separated SGND ground copper area for components connecting to signal pins. Components connecting
to SGND should be placed as close to the module as
possible and routed with minimum trace lengths and
trace widths, for best noise immunity.
• Note that there are two clusters of SGND pins on the
module: one, formed by Pins A1-A3, B1-B3, C1-C4
(A1-quadrant); and a second formed by Pins K1, K3,
L3, and M1-M3 (M1-quadrant). It is good PCB design
practice to provide a copper plane connecting all
A1-quadrant SGND pins together and another plane
connecting all M1-quadrant SGND pins together. It is
not necessary to connect these two clusters of SGND
copper planes to each other in the PCB layout, because
all SGND pins are electrically connected to each other
internal to the module.
• Do not connect the any SGND pins or SGND plane(s)
to the GND plane; the electrical star connection is made
internal to the module.
• For parallel module operation, see the Multimodule
Parallel Operation section for a list of interconnecting
pins across paralleled modules. Circuit Figures 56 and
66 show four and two LTM4641 devices operating in
parallel, respectively. Route signal-level (non-power)
nets on an internal layer, with GND planes overlapping
signal routes to shield them from noise. It is even
more effective to surround module-to-module signal
connections on the internal layer containing the signal
routes with adjacent GND planes or routes, and periodically “punching-through” GND via connections to GND
plane shields on adjacent layers. This practice forms
the equivalent of a “coaxial cable” structure within the
PCB, and is highly effective at shielding sensitive signals
from noise sources. Maintain differential routing of the
VOSNS+/VOSNS– pin pair.
4641fe
46
For more information www.linear.com/LTM4641
LTM4641
Applications Information—Safety and Layout Guidance
• Place all feedback components as close to the module
as possible, giving layout priority first to capacitors
CFFA, CFFB, CCMA, CCMB and CDM (if used)—followed
next by RSET1A, RSET1B and RSET2 (if used). See Figure 5
in the Applications Information section and Figure 64
in Appendix D for more details. Maintain differential
routing of the remote-sense lines between the load
and the module. Form a “coaxial cable” structure that
surrounds the remote-sense lines with GND potential
within the PCB, to the extent that layout permits. See
an example of routing the VOUT/GND remote-sense
pin pair in Layer 3 of DC1543.
• To facilitate stuffing verification, and test and debug activities, consider routing control signals of the LTM4641
with short traces to localized test points, test pads or
test vias—as PCB layout space permits. Both in-house
and contract manufacturers enjoy gaining electrical
access to all non low impedance (≥10Ω) pins of an IC
or μModule regulator to improve in-circuit test (ICT)
coverage.
Figure 43. Recommended PCB Layout, Figure 45 Circuit. View of the LTM4641 from Top of Package
Figure 44. Recommended PCB Layout, Figure 46 Circuit. View of the LTM4641 from Top of Package
For more information www.linear.com/LTM4641
4641fe
47
LTM4641
Typical Applications
VIN
4V TO 38V
(4.5V START-UP)
+
CIN(BULK)
50V
RfSET
2M
CIN(MLCC)
10µF
50V
×2
VINL
VING VINGP VINH
SW
VOUT
COUT(MLCC)
47µF
10V
×6
RSET1A
8.2k
CROWBAR
fSET
UVLO
HYST
FCB
LATCH
VORB+
VOSNS+
LTM4641
INTVCC
DRVCC
VOSNS–
VORB–
TEMP
1VREF
OVPGM
OTBH
PGOOD
IOVRETRY
OVLO
RUN
TRACK/SS
TMR
COMP SGND
RSET2
16.4k
RSET1B
8.2k
LOAD
LOCAL HIGH
FREQUENCY
DECOUPLING
GND
CTMR
N/U
CSS
4.7nF
VOUT
1.8V
10A
4641 F45
SGND CONNECTS TO GND INTERNAL TO MODULE. KEEP SGND
ROUTES/PLANES SEPARATE FROM GND ON MOTHERBOARD
Figure 45. 4VIN to 38VIN, LTM4641 Basic Configuration, 1.8V Output at 10A
4.5V START-UP
OPERATION
UP TO 38VIN
+
MSP
CIN(BULK)
100µF
50V
CIN(MLCC)
10µF
50V
×2
VINL
VING VINGP VINH
SW
VOUT
MCB
CROWBAR
fSET
UVLO
HYST
FCB
LATCH
LTM4641
+
VOSNS
VOSNS–
VORB–
TEMP
1VREF
OVPGM
OTBH
PGOOD
IOVRETRY
OVLO
RUN
TRACK/SS
CSS
22nF
TMR
COMP SGND
100µF
6.3V
×3
RSET1A
8.2k
VORB+
INTVCC
DRVCC
CFFA
100pF
VOUT
3.3V
10A
RSET2
4.7k
GND
RSET1B
8.2k
LOAD
LOCAL HIGH
FREQUENCY
DECOUPLING
CFFB
100pF
MCB: NXP PSMN5R0-30YL
MSP: NXP PSMN7R0-60YS
4641 F46
SGND CONNECTS TO GND INTERNAL TO MODULE. KEEP SGND
ROUTES/PLANES SEPARATE FROM GND ON MOTHERBOARD
Figure 46. LTM4641 Delivering 3.3V Output at 10A, and Providing Robust Output Overvoltage
Protection from up to 38VIN. Dropout Operation May Occur Below 4.8VIN. See Figure 11 to
Implement Custom UVLO Rising/Falling Settings to Avoid Dropout Operation
4641fe
48
For more information www.linear.com/LTM4641
LTM4641
Typical Applications
R1
20k
4.5V START-UP
OPERATION UP TO 28VIN
CONTINUOUS, TRANSIENT
PROTECTED TO 80VIN
+
CIN(BULK)
100µF
100V
MSP
CIN(MLCC)
10µF
100V
×2
5V
D1
36V
2%
R2
8.25k
RfSET
1M
VING VINGP
VINL
D2 Enables Detection
of VIN UVLO Falling
D2
RBOV
29.4k
VINH
SW
fSET
VOUT
LATCH
VORB+
HYST
FCB
OUT
LT®3010-5
SHDN
SENSE
GND
LTM4641
+
VOSNS
–
INTVCC
DRVCC
IOVRETRY
VOSNS
VORB–
TEMP
1VREF
OVPGM
OTBH
PGOOD
OVLO
Switching Action Is
Temporarily Latched Off if
VIN Exceeds 80V; Autonomous
Restart Attemps Occur in
9 Second Intervals When Input
Voltage Returns Below 80V. Note
LT3010-5 is Rated for 80V, Absolute
Maximum. See Note 1.
MCB
CROWBAR
UVLO
R3
2.7M
VIN
RROV
4.7M
When VIN Exceeds ~36V, D1 Ensures MSP Is Operated
in Its Linear Region and Provides Rudimentary Surge
Ride-Through Protection for LTM4641.
Optional: RT1, R1, R2, R3.To Enable RT1’s Detection of
Thermal Overstress in MSP During Sustained Input Voltage
Surge Events, Place RT1 in Extremely Close Proximity to
MSP in PCB Layout. Experimentally Determine the Vaules
of R1, R2 and R3 That Yield Desired Overtemperature
Shutdown Inception and Restart Recovery Thresholds
Consistent with MSP’s Rated Operating Junction
Temperature and Safe Operating Area
RT1
NTC
RUN
TRACK/SS
CSS
1nF
TMR
COMP SGND
CTMR
1µF
5V
100µF
6.3V
×4
VOUT
1V
10A
RSET1A
5.49k
RSET1B
5.49k
GND
4641 F47
LOAD
LOCAL HIGH
FREQUENCY
DECOUPLING
MSP and Switching Action Are Temporarily
Latched Off When a Module Overtemperature
or Output Overvoltage (OOV) Condition is
Detected--Additionally, the Crowbar MOSFET MCB
is Turned On to Protect the Load Upon OOV Detection.
Autonomous Restart Attempts Occur in 9 Second
Intervals When Conditions Return to Normal
TechClip Available (Click to View)
D2: CENTRAL SEMI CMMSH1-100G
MCB: NXP PSMN5R0-30YL
MSP: NXP PSMN028-100YS
RT1: MURATA NCP15WM474J03RC
SGND CONNECTS TO GND INTERNAL TO MODULE. KEEP SGND
ROUTES/PLANES SEPARATE FROM GND ON MOTHERBOARD
Figure 47. LTM4641 Generating 1V Output at 10A, Surge Protected up to 80VIN Transients.
Start-Up and Shutdown Waveforms with TMR = INTVCC Shown In Figure 2
VIN
20V/DIV
VINH
20V/DIV
VOUT 20mV/DIV
AC-COUPLED
VINL/INTVCC/DRVCC/LATCH
5V/DIV
2ms/DIV
4641 F48
Figure 48. Oscilloscope Snap-Shot of Figure 47 Circuit Riding Through 80VIN
Transient While Delivering 1VOUT at 10A to the Load
4641fe
For more information www.linear.com/LTM4641
49
LTM4641
Typical Applications
3.3VIN NOMINAL
3VIN RISING START-UP
2.3VIN FALLING SHUTDOWN
5V
LOW POWER BIAS
2V or Floating = On
1.2V
RSET2 Not Necessary for VOUT ≤ 1.2V
R
2 •RSET1A
VOUT = 0.6V 1+n SET1A +
8.2kΩ
RSET2
4641 F62
COUT(MLCC)
Optional Power RC
Snubber for Reduced
EMI
High Current Path:
Input to SMPS DC/DC Converter Stage
COUT(BULK)
RSET1A
RSET2
Optional Series Pass
Electronic “Circuit Breaker”
N-Ch Protection MOSFET
10V Bias (VGS) Charge Pump and
Discharge Path for Optional
External Series Pass N-Ch FET
MSP
On-Time and Switching Frequency
Adjustment REQUIRED for VOUT ≤ 3V,
Rail Tracking Applications and When
VINL ≠ VINH
VIN
4V TO 38V
(4.5V START-UP)
CIN(MLCC) +
CIN(BULK)
RSET1B
MCB
+
RSW
RfSET
Low Current Path: Power
Control and Logic Bias Input
LTM4641
Appendices
Appendix A. Functional Block Diagram and Features Quick Reference Guide
4641fe
INTVCC > 2V, NOM
INTVCC < 2V, NOM
For more information www.linear.com/LTM4641
INTVCC < 2V, NOM
Figure 63. Start-Up/Shutdown State Diagram
4641 F63
INTVCC > 2V, NOM;
AND ANY OF THE FOLLOWING NONLATCHING CONDITONS APPEAR:
1. CUSTOM UVLO INPUT TOO LOW (VUVLO < UVOVTH, ~0.5VTH)
2. NONLATCHING INPUT OVERVOLTAGE (VIOVRETRY > UVOVTH, ~0.5VTH)
3. DRVCC TOO LOW (VDRVCC < DRVCC(UVLO_FALLING), ~3.35VTH)
4. NONLATCHING OVERTEMPERATURE
(OTBH = OPEN CIRCUIT AND VTEMP < OTTH(INCEPTION), ~438mVTH)
AND NO LATCHOFF FAULTS ARE PRESENT:
1. INPUT VOLTAGE O.K. (VOVLO < UVOVTH, ~0.5VTH)
2. CROWBAR O.K. (VCROWBAR < VCROWBAR(TH), ~1.5VTH)
3. TEMPERATURE O.K.
(OTBH = LOW AND VTEMP > OTTH(INCEPTION), ~438mVTH)
UVLO/IOVRETRY/OVLO/CROWBAR/TEMP/DRVCC MONITOR
OUTPUTS HAVE REMAINED CLEAR FOR THE FULL DURATION
OF THE TIMEOUT PERIOD
INTVCC < 2V, NOM
LTM4641 VERIFICATION
OF TIMEOUT PERIOD
EXPIRATION: HOUSEKEEPING
CIRCUITRY HOLDS HYST LOW
(MHYST IS ON) UNTIL AND
UNLESS THE UVLO/IOVRETRY/
OVLO/CROWBAR/TEMP/DRVCC
MONITOR OUTPUTS REMAIN
CLEAR FOR THE FULL DURATION
OF THE TIMEOUT PERIOD, AS SET
BY TMR PIN (CTMR); POWER
STAGE IS OFF; VING IS DISCHARGED
INTVCC > 2V, NOM;
AND ALL OF THE FOLLOWING FAULT FREE CONDITIONS
ARE PRESENT (OR RECENTLY APPEARED, EXITING LATCHOFF):
1. CUSTOM UVLO INPUT O.K. (VUVLO > UVOVTH, ~0.5VTH)
2. NO INPUT OVERVOLTAGE(S)
(VIOVRETRY < UVOVTH AND VOVLO < UVOVTH, ~0.5VTH)
3. CROWBAR INACTIVE (VCROWBAR < VCROWBAR(TH), ~1.5VTH)
4. TEMPERATURE O.K. (VTEMP > OTTH(RECOVER), ~514mVTH)
5. DRVCC ABOVE ITS UVLO
(VDRVCC > DRVCC(UVLO_RISING), ~4.05VTH)
INTVCC > 2V, NOM;
AND ANY OF THE FOLLOWING NONLATCHING CONDITONS APPEAR:
1. CUSTOM UVLO INPUT TOO LOW (VULVO < UVOVTH, ~0.5VTH)
2. NONLATCHING INPUT OVERVOLTAGE (VIOVRETRY > UVOVTH, ~0.5VTH)
3. DRVCC TOO LOW (VDRVCC < DRVCC(UVLO_RISING), ~3.9VTH)
4. NONLATCHING OVERTEMPERATURE
(OTBH = OPEN CIRCUIT AND VTEMP < OTTH(RECOVER), ~514mVTH)
AND NO LATCHOFF FAULTS ARE PRESENT:
1. INPUT VOLTAGE O.K. (VOVLO < UVOVTH, ~0.5VTH)
2. CROWBAR O.K. (VCROWBAR < VCROWBAR(TH), ~1.5VTH)
3. TEMPERATURE O.K.
(OTBH = LOW AND VTEMP > OTTH(RECOVER), ~514mVTH)
LTM4641 PRIMED TO
REGULATE: WAITING
ONLY FOR RUN PIN TO
TRANSISTION HIGH AND
INTVCC TO EXCEED 3.6VNOM;
SWITCHING ACTION NOT
INHIBITED BY HOUSEKEEPING
CIRCUITRY (MHYST IS OFF);
POWER STAGE IS OFF;
VING IS DISCHARGED
INTVCC > 2V, NOM
AND ANY LATCHOFF FAULTS ARE PRESENT:
1. LATCHOFF INPUT OVERVOLTAGE (VOVLO > UVOVTH, ~0.5VTH)
2. CROWBAR ACTIVE (VCROWBAR > VCROWBAR(TH), ~1.5VTH)
3. LATCHOFF OVERTEMPERATURE
(OTBH = LOW AND VTEMP < OTTH(RECOVER), ~514mVTH)
EITHER INTVCC > 3.2V NOM AND RUN = LOW (0.8VTH, MIN)—
OR 2V < INTVCC < 3.2V, NOM— AND ADDITIONALLY,
IN EITHER CASE, ALL OF THE FOLLOWING FAULT FREE
CONDITIONS EXIST:
1. CUSTOM UVLO INPUT O.K. (VUVLO > UVOVTH, ~0.5VTH)
2. NO INPUT OVERVOLTAGE(S)
(VIOVRETRY < UVOVTH AND VOVLO < UVOVTH, ~0.5VTH)
3. CROWBAR INACTIVE (VCROWBAR < VCROWBAR(TH), ~1.5VTH)
4. TEMPERATURE O.K. (VTEMP > OTTH(RECOVER), ~514mVTH)
5. DRVCC ABOVE ITS UVLO
(VDRVCC > DRVCC(UVLO_FALLING), ~3.35VTH)
INTVCC > 3.9V, NOM
AND ALL OF THE FOLLOWING
FAULT FREE CONDITIONS ARE PRESENT:
1. CUSTOM UVLO INPUT O.K. (VUVLO > UVOVTH, ~0.5VTH)
2. NO INPUT OVERVOLTAGE(S)
(VIOVRETRY < UVOVTH AND VOVLO < UVOVTH, ~0.5VTH)
3. CROWBAR INACTIVE (VCROWBAR < VCROWBAR(TH), ~1.5VTH)
4. TEMPERATURE O.K. (VTEMP > OTTH(RECOVER), ~514mVTH)
5. DRVCC ABOVE ITS UVLO
(VDRVCC > DRVCC(UVLO_RISING), ~4.05VTH)
6. RUN > VRUN(ON) (2VTH, MAX)
LTM4641 HOUSEKEEPING
ALIVE AND INHIBITING
SWITCHING ACTION:
HYST IS PULLED LOW
(MHYST IS ON); POWER
STAGE IS OFF; VING IS
DISCHARGED
LATCHOFF IS CLEARED WHEN INTVCC > 2V, NOM
AND LATCH TOGGLES FROM LOGIC LOW
TO HIGH AND NO LATCHOFF FAULTS ARE PRESENT:
1. INPUT VOLTAGE O.K. (VOVLO < UVOVTH, ~0.5VTH)
2. CROWBAR O.K. (VCROWBAR < VCROWBAR(TH), ~1.5VTH)
3. TEMPERATURE O.K.
(OTBH = LOW AND VTEMP > OTTH(RECOVER), ~514mVTH)
INTVCC < 2V, NOM
INTVCC > 2V, NOM AND
LATCH = LOW
TIMEOUT PERIOD
BECOMES RESET
LTM4641 LATCHOFF
CONDITION DETECTED:
HYST IS LATCHED LOW
(MHYST IS ON); POWER
STAGE IS OFF; VING IS
DISCHARGED
INTVCC > 2V, NOM
AND LATCH = LOW
INTVCC < 2V, NOM
LTM4641 TIMEOUT DELAY IMPOSED DURING LATCHOFF:
HOUSEKEEPING CIRCUITRY HOLDS HYST LOW (MHYST IS ON)
UNTIL AND UNLESS ALL LATCHOFF FAULT-MONITOR OUTPUTS
REMAIN CLEAR FOR THE FULL DURATION OF THE TIMEOUT
PERIOD, AS SET BY TMR PIN (CTMR)
Appendix B. Start-Up/Shutdown State Diagram
INTVCC > 3.2V, NOM
AND ALL OF THE FOLLOWING
FAULT FREE CONDITIONS ARE PRESENT:
1. CUSTOM UVLO INPUT O.K. (VUVLO > UVOVTH, ~0.5VTH)
2. NO INPUT OVERVOLTAGE(S)
(VIOVRETRY < UVOVTH AND VOVLO < UVOVTH, ~0.5VTH)
3. CROWBAR INACTIVE (VCROWBAR < VCROWBAR(TH), ~1.5VTH)
4. TEMPERATURE O.K. (VTEMP > OTTH(INCEPTION), ~438mVTH)
5. DRVCC ABOVE ITS UVLO
(VDRVCC > DRVCC(UVLO_FALLING), ~3.35VTH)
6. RUN > VRUN(ON) (2VTH, MAX)
LTM4641 POWER STAGE
SWITCHING ACTION
IS ON: MHYST IS OFF;
VING IS CHARGE PUMPED
ABOVE VINH; CONTROL
LOOP REGULATES VOUT
INTVCC > 2V, NOM
AND ANY OF THE FOLLOWING LATCHOFF FAULTS ARE PRESENT:
1. LATCHOFF INPUT OVERVOLTAGE (VOVLO > UVOVTH, ~0.5VTH)
2. CROWBAR ACTIVE (VCROWBAR > VCROWBAR(TH), ~1.5VTH)
3. LATCHOFF OVERTEMPERATURE
(OTBH = LOW AND VTEMP < OTTH(INCEPTION), ~438mVTH)
INTVCC < 2V, NOM
LTM4641 SHUT DOWN:
HOUSEKEEPING AND
CONTROL SECTIONS
ARE UNBIASED; POWER
STAGE IS OFF; VING IS
DISCHARGED
INTVCC > 2V, NOM AND LATCH = HIGH
AND ANY LATCHOFF FAULT IS PRESENT:
1. INPUT OVERVOLTAGE (VOVLO > UVOVTH, ~0.5VTH)
2. CROWBAR ACTIVE (VCROWBAR > VCROWBAR(TH), ~1.5VTH)
3. LATCHOFF OVERTEMPERATURE
(OTBH = LOW AND VTEMP < OTTH(RECOVER), ~514mVTH)
LATCHOFF IS CLEARED WHEN INTVCC > 2V, NOM AND LATCH = HIGH
AND ALL LATCHOFF FAULT-MONITOR OUTPUTS REMAIN OPERATIONALLY
VALID FOR THE FULL DURATION OF THE TIMEOUT PERIOD:
1. INPUT VOLTAGE O.K. (VOVLO < UVOVTH, ~0.5V OTTH(RECOVER), ~514mVTH)
LTM4641
Appendices
4641fe
57
LTM4641
Appendices
Appendix C. Switching Frequency Considerations and
Usage of RfSET
There exist many scenarios in which a resistor, RfSET,
should be connected externally to LTM4641’s fSET pin—to
decrease the on-time of MTOP: most commonly, when the
output voltage setting is less than or equal to 3V, and in
rail-tracking applications; and less commonly, when VINL
and VINH are operating from different source supplies. In
the former cases, RfSET is usually applied from fSET to VINL
(Figure 45 and front page application circuit); in the latter,
RfSET is usually applied from fSET to the voltage source
feeding LTM4641’s power stage—upstream of MSP, if a
power-interrupt input MOSFET is used (Figure 49). There
are several motivations and considerations behind this
guidance:
(1) Inherent to LTM4641’s constant on-time architecture, the switching frequency of LTM4641 decreases
as output voltage decreases. In order to maintain a
reasonable output capacitor value solution size and
output voltage ripple—even at lower output voltages
(≤3VOUT)—RfSET should be applied, so that the controller’s ION pin current and the resulting nominal switching
frequency is higher than the on-time dictated by the
internal VINL-to-fSET-connected 1.3MΩ resistor.
(2) The PFM control scheme employed by LTM4641 yields
a switching frequency at zero load current (“no-load
operation”) that is typically 20% to 25% lower than
what it is at full load. As a result, inductor ripple current is proportionally higher at no load than what it is
at heavy load. Recall that LTM4641 employs RDS(ON)
current sensing; furthermore, realize that it is essential
for the controller’s current-sense amplifier to be able to
perceive and command sufficiently negative inductor
trough current, enough to maintain a maximum average
inductor current of 0A, so that output voltage can be
properly regulated down to no load. A value of RfSET
should be used to assure that switching frequency is
high enough (or on-time is small enough) at no load
so that the current-sense information representing the
trough of choke current is never too large in amplitude. Figure 3 provides conservative guidance on the
maximum value of RfSET (or equivalently, the minimum
ION current) that assures proper no-load operation.
(3) In rail-tracking applications, LTM4641’s output voltage
must track a reference voltage not only during VOUT
ramp up but also during VOUT ramp down; fulfilling
the latter requires LTM4641 to sink current from the
output capacitors. A value of RfSET should be used
that assures the output voltage can be ramped down
to one’s minimum desired output voltage of regulation—not just the intended nominal output voltage.
Figure 3 provides this guidance.
(4) In order to maintain a relatively constant switching
frequency for a given output voltage (across the full
line voltage), the on-time of MTOP should be inversely
proportional to the voltage source feeding the VINH
power stage—upstream of MSP, if a power-interrupt
MOSFET is used (Figure 46). When VINL and VINH are
operated from different rails, this goal can be accomplished satisfactorily by placing RfSET between fSET
and the power VIN input source (see Figure 49: the
connection is to VIN and not VINL, and usually not VINH,
but see a counterexample in Figure 47 and explanation in item number 5 of this list). A minor error term
to the on-time is introduced by the internal 1.3MΩ
VINL-to-fSET-connected resistor in such scenarios, so
calculation of IION at all operating input voltage corner
cases (power, VINH and control bias, VINL extremes)
and the resulting switching frequency range of operation, given by Equation 6, should be considered.
(5) When MSP is used, and when VINL and VINH are
operated from different rails—here is the reason it
is recommended to connect RfSET from fSET to the
drain of MSP rather than VINH: prior to start-up, MSP
is off, and VINH is discharged. Connecting RfSET to
VINH would set the on-time at the instant switching
activity commenced to be much lower than intended.
The on-time would not reach its final settling value
until VING circuitry had turned on MSP enough for
VINH to become pulled up to VIN potential. It should
become apparent that a mechanism may exist for
dynamic interaction between how rapidly the output
voltage ramps up (depending on TRACK/SS pin usage)
versus how rapidly MSP might turn on. We know from
item number 2 of this list that on-time should not be
arbitrarily large. In general, to avoid any undesirable
4641fe
58
For more information www.linear.com/LTM4641
LTM4641
Appendices
Furthermore, using an RSET1A (and RSET1B) value of 8.2kΩ
for 1.2VOUT and larger assures that the common mode
range of the remote-sense pins is within their valid range
of –0.3V, minimum, to 3V, maximum—even if voltage
drop between the module’s ground deviates from the
POL’s ground by as much as ±0.6V.
interactions—which might at worst result in excessive output voltage ripple or non-monotonic output
voltage ramp-up, a sufficiently slow output voltage
ramp-up time can eliminate the danger of VINH and
on-time settling interactions influencing output voltage ripple—but properly, this requires investigation
and hardware evaluation on a case-by-case basis.
Figure 47 shows an example where RfSET connects
between fSET and VINH—rather than the input source
supply. Because MSP limits the VINH voltage during
the input voltage surge, the correct ION programming
current can only be made with a resistor interface to
VINH, in that example.
The differential remote-sense feedback signal is routed
from the load as a differential pair on PCB traces (or
twisted pair, if wires are used) to RSET1A/RSET1B feedback components. It is very important to place RSET1A/
RSET1B and all other components forming the feedback
impedance-divider network as close to LTM4641 as is
possible. Ground shielding of the differential remote-sense
signal is strongly recommended, to prevent stray noise
from contaminating the feedback information.
Appendix D. Remote Sensing in Harsh Environments
The rationale for using the symmetrical resistor network is
to provide a consistent feedback structure that enables fully
differential remote-sense of output voltages between 0.6V
and 6V with the flexibility to filter differential and common
mode noise in harsh environments. See Figure 64. The
use of not greater than 8.2kΩ nominal resistors for RSET1A
(and RSET1B) assures that the remote-sense signal is not
attenuated at frequencies of interest by the pole formed
by the feedback resistors and parasitic capacitances.
If good shielding of the feedback signals cannot be provided, it is proactive to leave space in one’s layout for a
small filter capacitor, CDM, placed directly between VOSNS+
and VOSNS–, as close to the pins of the module as possible—in anticipation of the possible need to attenuate
differential mode noise.
Finally, if the POL is very far from the LTM4641, such as:
the output power connection (VOUT and GND) is made
CCMA, CCMB: If Appreciable Cable Length Connects the LTM4641’s Output
to the Load (e.g., Through Several Feet of Wire), Leave Provision
for High Frequency Decoupling of Common Mode Ground Noise with
These Capacitors. These Are Not Needed in Purely PCB-Based Designs,
Where the LTM4641 Is Close to the Load
CFFA, CFFB: Feedforward Capacitors
Yeild Improved Transient Response
When Filtering VOUT with Only MLCC
Output Capacitors (COUT(MLCC))
VOUT
LTM4641
CFFA
VORB+
VFB
TO ERROR
AMPLIFIER
+
8.2k
8.2k VOSNS+
–
8.2k
TRUE DIFFERENTIAL REMOTE
SENSE AMPLIFIER
ICT
TEST
POINT
CCMA
CDM
8.2k
SGND
GND
SGND CONNECTS TO GND INTERNAL TO MODULE. KEEP SGND
ROUTES/PLANES SEPARATE FROM GND ON MOTHERBOARD
VOUT
COUT(BULK)
COUT(MLCC)
RSET1A
RSET2
LOAD
RSET1B
VOSNS–
VORB–
+
ICT
TEST
POINT
CCMB
CFFB
Place All Feedback
Components Local
To The LTM4641
4641 F064
Route Feedback Signals as
a Differential Pair (or
Twisted Pair if Using Wires).
Sandwich Between Ground
Planes to Form a Protective Shield,
Guarding Against Stray Noise
If Effective Ground Shielding of the Feedback Signals Cannot
Be Implemented, Leave Provision for a Small Capacitor (CDM)
To Attenuate Differential Mode Noise if Necessary
Figure 64. Feedback Remote Sense Connections and Techniques for Harshest Operating Environments
For more information www.linear.com/LTM4641
4641fe
59
LTM4641
Appendices
through a board-to-board connector; an inductive length
of cable (say, 50cm in length, or more); or, if the load is
highly inductive—then it is proactive to leave provision
in one’s layout for a pair of small filter capacitors, CCMA
and CCMB. CCMA and CCMB should be placed directly from
VOSNS+ to SGND and VOSNS– to SGND, respectively—as
close to the pins of the module as possible. Configured
in this manner, CCMA and CCMB can be used to attenuate
common mode noise in the remote-sense signal pin pair.
Appendix E. Inspiration For Pulse-Skipping Mode
Operation
When MTOP is turned on—for a duration of time proportional to IION current—inductor current is ramped upwards,
and energy is built up in the inductor’s B-field. Ultimately,
a “packet” of energy is transferred from the input capacitors to the output capacitors. In forced continuous mode
operation (FCB logic low), MTOP and MBOT are operated in
a purely synchronous fashion, meaning: when MTOP is on,
MBOT is off—and vice versa. Observe that when MTOP is
turned off, the B-field in the inductor cannot instantaneously
vanish: the collapsing B-field forces inductor current to
flow through MBOT’s on-die Schottky diode—resulting in
unwanted freewheeling diode power loss; MBOT is turned
on for lower power loss, instead. With MBOT on, inductor
current ramps downward as energy in its B-field wanes.
In steady-state forced continuous mode operation, the
inductor ripple current appears as a triangle waveform
whose average value equates to the load’s current. Forced
continuous mode operation (forcing synchronous operation of MTOP and MBOT) provides a mechanism for consistent output voltage ripple, regardless of the load current.
However, in this mode of operation, at light load currents
(say, less than 2A out), observe that the inductor current
is periodically negative—which means some packets of
energy that are transferred from the input capacitors to the
output are recirculated and transferred back to the input
capacitors. This is a source of inefficiency that brings
about the motivation for pulse-skipping mode operation,
to turn off MBOT when the inductor current ramps down
to 0A. This concept is also described in the industry as
“diode emulation”, because MBOT is made to mimic the
behavior of a Schottky rectifier. In pulse-skipping mode
operation (FCB logic high), the inductor ripple current at
light loads appears as an asymmetrical truncated triangle
waveform; inductor current does not go below 0A.
Appendix F. Adjusting the Fast Output Overvoltage
Comparator Threshold
The output overvoltage inception threshold (OVPGM voltage) can be adjusted or tightened from its default value.
The following guidelines must be followed, however:
• It is not recommended to change the OVPGM voltage
dynamically because the fast OOV comparator has no
glitch immunity beyond what is provided by OVPGM’s
internal 47pF capacitor, and routing of OVPGM can make
it vulnerable to electrostatic noise.
• The 15.6μs time constant filter formed by OVPGM’s internal 47pF capacitor and default 499kΩ||1MΩ resistordivider network should be maintained for practical values
of OVPGM voltage: 0.6V < VOVPGM < 0.9V. Capacitive
filtering of OVPGM must not be applied indiscriminately.
The OVPGM voltage must come up very rapidly with the
1VREF at start-up, to prevent a race condition that would
otherwise result in nuisance OOV detection and a faulty
latchoff event—so any externally applied capacitance
cannot be arbitrarily high. On the other hand, OVPGM
must have some filtering from switching noise sources
and should be sufficiently insulated from any possible
dynamic activity on 1VREF. (See Figure 9.)
• External resistor(s) applied between OVPGM and 1VREF/
SGND should be relatively high impedance, to minimize
loading on the 1VREF output. Then, small values of
COVPGM achieve a consistent time constant as OVPGM’s
resistance-divider network is altered.
Figure 65 shows the optional network one can apply to
alter or tighten the OVPGM setpoint.
1VREF
LTM4641
RTOVPGM
OVPGM
COVPGM
SGND
RBOVPGM
4641 F65
Figure 65. Optional OVPGM Network to Alter or Tighten VOVPGM
4641fe
60
For more information www.linear.com/LTM4641
LTM4641
Appendices
To nudge the OVPGM setpoint downward, to a new OOV
inception threshold voltage at OVPGM(NEW)—using an
RBOVPGM resistor, only—calculate:
RBOVPGM =
1
1V – OVPGM(NEW)
1
OVPGM(NEW) • 499kΩ 1MΩ
(37)
–
100kΩ, low T.C.R. resistor. Using tolerances of ±0.1%
and a T.C.R. of ±25ppm/°C can provide a considerable
improvement in accuracy over the default divider network,
over temperature. Next, decide the new value of VOVPGM
desired—OVPGM(NEW)—within a practical window of 0.6V <
OVPGM(NEW) < 0.9V. Then, compute RTOVPGM according to:
RTOVPGM =
The new OVPGM threshold can then be double-checked by
OVPGM(NEW) =
1V • (1MΩ || RBOVPGM )
(499kΩ + 1MΩ || R BOVPGM )
When lowering the OVPGM setpoint with application of
RBOVPGM only, it is not necessary to apply a COVPGM
capacitor, because: for an extreme OVPGM(NEW) setting
of 600mV, which is not practical since that is the voltage
of VFB during normal regulation, the time-constant of the
OVPGM network would have changed by less than 2μs
from its default value.
To nudge the OVPGM trip threshold upward to set a new
OOV inception threshold voltage at OVPGM(NEW)—using
an RTOVPGM resistor only—calculate:
RTOVPGM =
1
OVPGM(NEW)
(1V – OVPGM(NEW) )
1
499kΩ
• 1MΩ
(39)
–
The new OVPGM setting can then be double-checked by:
OVPGM(NEW) =
1V • 1MΩ
499kΩ
||
RTOVPGM + 1MΩ)
(
(1V – OVPGM(NEW) ) • (1MΩ|| RBOVPGM )
(38)
(40)
If RTOVPGM is computed in Equation 39 to be smaller than
10kΩ, connect OVPGM to 1VREF and do not apply any
COVPGM capacitor; this will yield an OOV setting of 167%
of nominal. Otherwise, use the next smallest standard
value of COVPGM available, computed by:
1
OVPGM(NEW)
–
(42)
1
499kΩ
The new OVPGM setting can be double-checked by:
OVPGM(NEW) =
1V • (1MΩ || RBOVPGM )
(43)
(499kΩ || RTOVPGM + 1MΩ || RBOVPGM )
Then, use the next smallest standard value of COVPGM
available, computed by:
COVPGM(NEW) =
15.6µs
– 47pF
(499kΩ || 1MΩ|| RTOVPGM || RBOVPGM )
(44)
For example, the OVPGM(NEW) setpoint can be kept at its
nominal value of 666mV—but with better accuracy—by
using ±0.1% precision resistors with ±25ppm/°C T.C.R.
for RBOVPGM = 100k and RTOVPGM = 49.9k, and bypassing OVPGM to SGND with COVPGM = 470pF. The resulting
VOVPGM OOV setpoint threshold becomes better than
±1.8%, over temperature. The vast majority of the remaining variation in the threshold setting comes variation of
the 1VREF—a ±1.5% reference, over temperature.
(41)
The extreme values of the OOV setpoint voltage, plus
the OVPERR term—which is the offset voltage of the fast
comparator (±12mV maximum, over temperature)—gives
guidance on what the minimum and maximum voltage VFB
can be at which the CROWBAR output would swing logic
high and invoke latchoff overvoltage protection.
The default VOVPGM setpoint is 665mV ±2.26%, over
temperature. To tighten the OVPGM setpoint, begin by
choosing RBOVPGM to be a commonly available precision
One must take care to set the OVPGM voltage to a practical
level and not too aggressively. If OVPGM is set too low,
the system will demonstrate nuisance output overvoltage
latchoff behavior. The output voltage of any switching
COVPGM =
15.6µs
– 47pF
(499kΩ || 1MΩ|| RTOVPGM )
4641fe
For more information www.linear.com/LTM4641
61
LTM4641
Appendices
regulator can witnesses transient excursions above its
ideal DC voltage operating point routinely, owing to:
• Control IC bandgap reference accuracy
• Output voltage ripple and noise
• Load current step-down transient events—including
recovery from a short-circuit condition
• Steep line voltage step-up
• Start-up overshoot (little or no soft-starting of VOUT),
or rail-tracking a fast master rail
The Linear Technology LTpowerCAD design tool can help
quantify some of these dynamic values; LTM4641’s total
DC error (including bandgap reference variation) is better
than ±1.5%, over temperature.
If OVPGM has been decreased to its lowest practical level
and output voltage overshoot during high side MOSFET
short-circuit testing (shorting VINH to SW on evaluation
hardware such as DC1543, for example) does not clamp
the output voltage to one’s satisfaction, be aware that
increasing output capacitance can reduce the maximum
output voltage excursion. The reason follows: the larger
the output capacitance, the longer it takes for the output
voltage to be ramped up, even in the extreme case of
deliberately short circuiting VINH to SW. The capacitance
on VOUT is mainly what prevents the output voltage from
shooting up to VINH—until CROWBAR turns on MCB.
Multimodule parallel applications also have better output
voltage overshoot during high side MOSFET short-circuit
testing, owing to the fact that the sibling modules whose
high side MOSFETs are not short circuited are able to help
pull the output voltage down by turning on their low side
power MOSFETs. Examples of paralleled LTM4641 powering and protecting loads are shown in Figures 56 and 66.
4641fe
62
For more information www.linear.com/LTM4641
LTM4641
LTM4641
Package Description
Table 10. LTM4641 Component BGA Pinout
PIN ID
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
FUNCTION
SGND
SGND
SGND
HYST
TEMP
IOVRETRY
GND
GND
GND
GND
GND
GND
PIN ID
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
FUNCTION
SGND
SGND
SGND
UVLO
OVLO
GND
GND
GND
CROWBAR
OVPGM
GND
GND
PIN ID
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
FUNCTION
SGND
SGND
SGND
SGND
LATCH
1VREF
GND
GND
VOUT
VOUT
VOUT
VOUT
PIN ID
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
FUNCTION
VORB+
VORB–
OTBH
TMR
RUN
GND
GND
GND
VOUT
VOUT
VOUT
VOUT
PIN ID
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
FUNCTION
GND
GND
GND
GND
GND
GND
GND
GND
VOUT
VOUT
VOUT
VOUT
PIN ID
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
FUNCTION
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PIN ID
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
FUNCTION
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PIN ID
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
FUNCTION
VOSNS+
VOSNS–
GND
GND
GND
GND
GND
GND
GND
SW
GND
GND
PIN ID
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
FUNCTION
COMP
fSET
VINL
DRVCC
GND
GND
GND
GND
GND
GND
GND
GND
PIN ID
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
K12
FUNCTION
SGND
FCB
SGND
INTVCC
GND
GND
VINH
VINH
VINH
VINH
GND
GND
PIN ID
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
FUNCTION
PGOOD
TRACK/SS
SGND
GND
GND
GND
VINH
VINH
VINH
VINH
VINH
VINH
PIN ID
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
FUNCTION
SGND
SGND
SGND
GND
GND
GND
VINH
VINH
VING
VINGP
VINH
VINH
Package Photo
4641fe
For more information www.linear.com/LTM4641
63
0.0
aaa Z
0.630 ±0.025 Ø 144x
4
E
PACKAGE TOP VIEW
3.1750
3.1750
SUGGESTED PCB LAYOUT
TOP VIEW
1.9050
PIN “A1”
CORNER
0.6350
0.0000
0.6350
Y
For more information www.linear.com/LTM4641
6.9850
5.7150
4.4450
3.1750
1.9050
0.6350
0.0000
0.6350
1.9050
3.1750
4.4450
5.7150
6.9850
X
D
aaa Z
NOM
5.01
0.60
4.41
0.75
0.63
15.00
15.00
1.27
13.97
13.97
0.41
4.00
MAX
5.21
0.70
4.51
0.90
0.66
NOTES
DETAIL B
PACKAGE SIDE VIEW
DIMENSIONS
b1
A
A2
0.46
4.05
0.15
0.10
0.20
0.30
0.15
TOTAL NUMBER OF BALLS: 144
0.36
3.95
MIN
4.81
0.50
4.31
0.60
0.60
DETAIL A
SYMBOL
A
A1
A2
b
b1
D
E
e
F
G
H1
H2
aaa
bbb
ccc
ddd
eee
H1
SUBSTRATE
A1
ddd M Z X Y
eee M Z
DETAIL B
H2
MOLD
CAP
ccc Z
Øb (144 PLACES)
// bbb Z
(Reference LTC DWG # 05-08-1914 Rev A)
144-Lead (15mm × 15mm × 5.01mm)
Z
Package
(Reference LTCBGA
DWG
# 05-08-1914 Rev A)
Z
64
1.9050
BGA Package
144-Lead (15mm × 15mm × 5.01mm)
e
b
11
10
9
7
G
6
e
5
PACKAGE BOTTOM VIEW
8
4
3
2
1
DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
4
7
TRAY PIN 1
BEVEL
!
PACKAGE IN TRAY LOADING ORIENTATION
LTMXXXXXX
µModule
A
B
C
D
E
F
G
H
J
K
L
M
7
SEE NOTES
PIN 1
BGA 144 1112 REV A
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu
5. PRIMARY DATUM -Z- IS SEATING PLANE
BALL DESIGNATION PER JESD MS-028 AND JEP95
3
2. ALL DIMENSIONS ARE IN MILLIMETERS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
COMPONENT
PIN “A1”
3
SEE NOTES
F
b
12
DETAIL A
LTM4641
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
4641fe
6.9850
5.7150
4.4450
4.4450
5.7150
6.9850
LTM4641
Revision History
(Revision history begins at Rev B)
REV
DATE
DESCRIPTION
B
02/13
Updated Figure 1.
C
05/13
Updated video play buttons.
D
10/13
E
02/14
PAGE NUMBER
15
1, 49
Added patent number 8163643.
1
Changed Figure 9 title from "Figure 43 Circuit” to "Figure 45 Circuit at 28VIN."
28
Added SnPb BGA package option
1, 3
4641fe
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representaFor more
information
www.linear.com/LTM4641
tion that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
65
LTM4641
Typical Application
4.5VIN START-UP
OPERATION UP TO 38V
AND DOWN TO 4V
CIN(BULK)
100µF
50V
×2
MSP
CIN(MLCC)
10µF
50V
×4
VINL
RfSET1
750k
VING VINGP VINH
SW
VOUT
1
LATCH
INTVCC
DRVCC
–
VOSNS
VORB–
TEMP
1VREF
OVPGM
OTBH
PGOOD
1
RUN
TRACK/SS
TO SYSTEM µP
(OPTIONAL)
FAULT INDICATOR
CSS
22nF
TMR COMP
CTMR1
N/U
PULL LATCH NORMALLY LOW FOR
LATCHOFF RESPONSE TO OUTPUT
OVERVOLTAGE AND OVERTEMPERATURE EVENTS. PULL
LATCH HIGH TO RESTART 1V OUTPUT
VINL
RfSET2
750k
ALTERNATIVELY, CONNECT LATCH
TO INTVCC AND INSTALL CTMR1 AND
CTMR2 TO SET 1V OUTPUT FOR TIMED
AUTONOMOUS RESTART AFTER
FAULT SHUTDOWN EVENTS
2
LOAD
LOCAL HIGH
FREQUENCY
DECOUPLING
CFF2
100pF
1
GND
1
VING VINGP VINH
SW
VOUT
CROWBAR
fSET
UVLO
HYST
FCB
MCB: NXP PSMN5R0-30YL
MSP: NXP PSMN7R0-60YS
RSET1B
2.74k
CDM1
22pF
1
1
LATCHOFF RESET
SGND
CMLCC(OUT)
100µF
6.3V
×6
RSET1A
2.74k
VORB+
VOSNS+
U1
LTM4641
IOVRETRY
OVLO
RUN ENABLE
MCB
CROWBAR
fSET
UVLO
HYST
FCB
VOUT
1V
20A
CFF1
100pF
LATCH
VORB+
VOSNS+
U2
LTM4641
INTVCC
DRVCC
VOSNS–
VORB–
TEMP
1VREF
OVPGM
OTBH
PGOOD
IOVRETRY
OVLO
2
RUN
TRACK/SS
TMR
CTMR2
N/U
COMP
SGND
CDM2
22pF
2
GND
2
4641 F66
2
U1 AND U2 SGND ( 1, 2) CONNECT TO GND INTERNAL TO THEIR RESPECTIVE MODULES. KEEP MODULE
SGND ROUTES/PLANES SEPARATE FROM OTHER MODULES AND FROM GND ON MOTHERBOARD
Figure 66. 1V, 20A Fault-Protected Load Powered by Paralleled LTM4641—from Up to 38VIN. cf. Typical Performance Characteristics
Related Parts
PART NUMBER
LTM4620
LTM4613
LTM4627
LTM8027
LTM4609
LT4356
DESCRIPTION
Dual 13A, Single 26A µModule
Regulator
EN55022B Certified 36V, 8A
Step-Down µModule Regulator
20V, 15A Step-Down µModule
Regulator
60V, 4A Step-Down µModule
Regulator
36V, 4A Buck-Boost µModule
Regulator
High Voltage Surge Stopper
COMMENTS
Up to 100A with Four Devices; 4.5V ≤ VIN ≤ 16V; 0.6V ≤ VOUT ≤ 2.5V. See LTM4620A for
Higher VOUT; 15mm × 15mm × 4.41mm LGA
5V ≤ VIN ≤ 36V; 3.3V ≤ VOUT ≤ 15V; Synchronizable, Parallelable,
15mm × 15mm × 4.32mm LGA
4.5V ≤ VIN ≤ 20V; 0.6V ≤ VOUT ≤ 5V; Synchronizable, Parallelable,
Remote Sensing, 15mm × 15mm × 4.32mm LGA or 15mm × 15mm × 4.92mm BGA
4.5V ≤ VIN ≤ 60V; 2.5V ≤ VOUT ≤ 24V; Synchronizable,
15mm × 15mm × 4.32mm LGA
4.5V ≤ VIN ≤ 36V; 0.8V ≤ VOUT ≤ 34V; Synchronizable, Parallelable, Up to 4A in Boost Mode
and 10A in Buck Mode, 15mm × 15mm × 2.82mm LGA or 15mm × 15mm × 3.42mm BGA
100VIN Overvoltage and Overcurrent Protection, Latchoff and Auto-Retry Options
4641fe
66 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTM4641
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTM4641
LT 0214 REV E • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2012
工商网监
湘ICP备2023018690号
