LTM4643
Ultrathin Quad µModule
Regulator with Configurable
3A Output Array
DESCRIPTION
FEATURES
Quad Output Step-Down µModule® Regulator with
3A per Output
n Wide Input Voltage Range: 4V to 20V
n 2.375V to 20V with External Bias
n 0.6V to 3.3V Output Voltage
n 3A DC Output Current Each Channel
n ±1.5% Total Output Voltage Regulation
n Current Mode Control, Fast Transient Response
n Parallelable for Higher Output Current
n Output Voltage Tracking
n Internal Temperature Sensing Diode Output
n External Frequency Synchronization
n Overvoltage, Current and Temperature Protection
n 9mm × 15mm × 1.82mm LGA and 9mm × 15mm ×
2.42mm BGA Packages
n
APPLICATIONS
The LTM®4643 is a quad DC/DC step-down µModule
(power module) regulator with 3A per output. Outputs can
be paralleled in an array for up to 12A capability. Included
in the package are the switching controllers, power FETs,
inductors and support components. Operating over an
input voltage range of 4V to 20V or 2.375V to 20V with
an external bias supply, the LTM4643 supports an output
voltage range of 0.6V to 3.3V each set by a single external
resistor. Its high efficiency design delivers 3A continuous
output current per channel. Only bulk input and output
capacitors are needed.
Fault protection features include overvoltage, overcurrent
and overtemperature protection. The LTM4643 is offered
in a 9mm ×15mm × 1.82mm LGA and 9mm × 15mm ×
2.42mm BGA packages with SnPb (BGA) or RoHS compliant terminal finish.
Configurable Output Array*
FPGAs, GPUs and ASICs Applications
n PCIe and Backside PCB Mounting
n
3A
3A
3A
3A
All registered trademarks and trademarks are the property of their respective owners.
6A
9A
3A
3A
12A
3A
* Note 4
TYPICAL APPLICATION
4V to 20V Input, Quad 0.9V, 1V, 1.2V and
1.5V Output DC/DC µModule Regulator
22µF
×2
25V
VIN1
SVIN1
RUN1
CLKIN
CLKOUT
VOUT1
FB1
PGOOD1
40.2k
LTM4643
VOUT2
FB2
PGOOD2
VIN3
SVIN3
RUN3
VOUT3
FB3
PGOOD3
VOUT4
FB4
PGOOD4
TEMP
SGND
1.2V/3A
60.4k
47µF
4V
90.9k
47µF
4V
1V/3A
1.6
90
1.4
85
1.2
80
1.0
75
0.8
70
0.6
65
0.9V/3A
121k
95
47µF
4V
GND
0.4
VIN = 5V
VIN = 12V
60
55
POWER LOSS (W)
VIN2
SVIN2
RUN2
VIN4
SVIN4
RUN4
NOT ALL PINS
ARE SHOWN
1.5V/3A
47µF
4V
EFFICIENCY (%)
4V to 20V
1.5V Output Efficiency and
Power Loss (Each Channel)
0
0.5
1
1.5
2
LOAD CURRENT (A)
2.5
0.2
3
0.0
4643 TA01b
4643 TA01a
Rev D
Document Feedback
For more information www.analog.com
1
LTM4643
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
VIN, SVIN (Per Channel)............................... –0.3V to 22V
VOUT (Per Channel) (Note 3).............–0.3V to SVIN or 6V
RUN (Per Channel)...................................... –0.3V to 22V
INTVCC (Per Channel)................................ –0.3V to 3.6V
PGOOD, MODE, TRACK/SS,
FB (Per Channel).................................... –0.3V to INTVCC
CLKOUT (Note 3), CLKIN........................ –0.3V to INTVCC
Internal Operating Temperature Range
(Notes 2, 5)............................................. –40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
Peak Solder Reflow Body Temperature.................. 260°C
TRACK/SS1
VIN1
1
2
3
4
VOUT1
5
6
7
FB1
GND
A
GND
B
COMP1
SVIN1
MODE1
RUN1
CLKIN
C
VOUT2
PGOOD2 PGOOD1 INTVCC1
TRACK/SS2
D
FB2
E
COMP2
GND
VIN2
VOUT3
RUN2
SGND
F
PGOOD3 TEMP
INTVCC2
TRACK/SS3
G
FB3
H
COMP3
GND
VIN3
VOUT4
SVIN2
MODE2
SVIN3
MODE3
RUN3
INTVCC3
FB4
J
PGOOD4 CLKOUT
TRACK/SS4
RUN4
K
INTVCC4
GND
L
COMP4
VIN4
SVIN4 MODE4
LGA PACKAGE (WEIGHT = 0.70g)
77-LEAD (9mm × 15mm × 1.82mm)
BGA PACKAGE (WEIGHT = 0.83g)
77-LEAD (9mm × 15mm × 2.42mm)
TJMAX = 125°C, θJCtop = 17°C/W, θJCbottom = 2.75°C/W,
θJB + θBA = 11°C/W, θJA = 10°C/W
θ VALUES PER JESD 51-12
ORDER INFORMATION
PART MARKING*
DEVICE
FINISH CODE
PACKAGE
TYPE
MSL
RATING
Au (RoHS)
LTM4643V
e4
LGA
3
–40°C to 125°C
LTM4643IV#PBF
Au (RoHS)
LTM4643V
e4
LGA
3
–40°C to 125°C
LTM4643MPV#PBF
Au (RoHS)
LTM4643V
e4
LGA
3
–55°C to 125°C
LTM4643EY#PBF
SAC305 (RoHS)
LTM4643Y
e1
BGA
3
–40°C to 125°C
LTM4643IY#PBF
SAC305 (RoHS)
LTM4643Y
e1
BGA
3
–40°C to 125°C
LTM4643MPY#PBF
SAC305 (RoHS)
LTM4643Y
e1
BGA
3
–55°C to 125°C
LTM4643IY
SnPb (63/37)
LTM4643Y
e0
BGA
3
–40°C to 125°C
LTM4643MPY
SnPb (63/37)
LTM4643Y
e0
BGA
3
–55°C to 125°C
PART NUMBER
PAD OR BALL FINISH
LTM4643EV#PBF
TEMPERATURE RANGE
(SEE NOTE 2)
• Contact the factory for parts specified with wider operating temperature • Recommended LGA and BGA PCB Assembly and Manufacturing
ranges. *Device temperature grade is indicated by a label on the shipping
Procedures
container. Pad or ball finish code is per IPC/JEDEC J-STD-609.
• LGA and BGA Package and Tray Drawings
2
Rev D
For more information www.analog.com
LTM4643
ELECTRICAL
CHARACTERISTICS
The
l denotes the specifications which apply over the specified internal
operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, per the typical application.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Switching Regulator Section: per Channel
VIN, SVIN
Input DC Voltage
SVIN = VIN
l
4
20
V
VOUT(RANGE)
Output Voltage Range
VOUT(DC)
Output Voltage, Total Variation
with Line and Load
CIN = 22µF, COUT = 100µF Ceramic, RFB = 40.2k,
MODE = INTVCC,VIN = 4V to 20V, IOUT = 0A to 3A (Note 4) l
l
0.6
3.3
V
V
VRUN
RUN Pin On Threshold
VRUN Rising
IQ(SVIN)
Input Supply Bias Current
VIN = 12V, VOUT = 1.5V, MODE = INTVCC
VIN = 12V, VOUT = 1.5V, MODE = GND
Shutdown, RUN = 0, VIN = 12V
IS(VIN)
Input Supply Current
VIN = 12V, VOUT = 1.5V, IOUT = 3A
IOUT(DC)
Output Continuous Current Range VIN = 12V, VOUT = 1.5V (Note 4)
ΔVOUT (Line)/VOUT
Line Regulation Accuracy
1.477
1.50
1.523
1.1
1.2
1.3
6
2
11
0.45
0
V
mA
mA
µA
A
3
A
VOUT = 1.5V, VIN = 4V to 20V, IOUT = 0A
l
0.01
0.05
ΔVOUT (Load)/VOUT Load Regulation Accuracy
VOUT = 1.5V, IOUT = 0A to 3A
l
0.5
1.0
VOUT(AC)
Output Ripple Voltage
IOUT = 0A, COUT = 100µF Ceramic, VIN = 12V,
VOUT = 1.5V
5
mV
ΔVOUT(START)
Turn-On Overshoot
IOUT = 0A, COUT = 100µF Ceramic, VIN = 12V,
VOUT = 1.5V
30
mV
tSTART
Turn-On Time
COUT = 100µF Ceramic, No Load, TRACK/SS = 0.01µF,
VIN = 12V, VOUT = 1.5V
2.5
ms
ΔVOUTLS
Peak Deviation for Dynamic Load
Load: 0% to 50% to 0% of Full Load, COUT = 47µF
Ceramic, VIN = 12V, VOUT = 1.5V
160
mV
tSETTLE
Settling Time for Dynamic Load
Step
Load: 0% to 50% to 0% of Full Load, COUT = 47µF
Ceramic, VIN = 12V, VOUT = 1.5V
40
µs
IOUTPK
Output Current Limit
VIN = 12V, VOUT = 1.5V
VFB
Voltage at FB Pin
IOUT = 0A, VOUT = 1.5V, –40°C to 125°C
IFB
Current at FB Pin
(Note 3)
RFBHI
Resistor Between VOUT and FB
Pins
ITRACK/SS
Track Pin Soft-Start Pull-Up
Current
TRACK/SS = 0V
VIN(UVLO)
VIN Undervoltage Lockout
VIN Falling
VIN Hysteresis
tON(MIN)
Minimum On-Time
(Note 3)
40
ns
tOFF(MIN)
Minimum Off-Time
(Note 3)
70
ns
VPGOOD
PGOOD Trip Level
VFB With Respect to Set Output
VFB Ramping Negative
VFB Ramping Positive
IPGOOD
PGOOD Leakage
VPGL
PGOOD Voltage Low
IPGOOD = 1mA
VINTVCC
Internal VCC Voltage
SVIN = 4V to 20V
VINTVCC Load Reg
INTVCC Load Regulation
ICC = 0mA to 20mA
0.5
%
fOSC
Oscillator Frequency
1.2
MHz
CLKIN
CLKIN Threshold
0.7
V
l
3.5
5
0.593
0.60
60.05
2.4
–13
7
3.1
%/V
%
A
0.607
V
±30
nA
60.40
60.75
kΩ
2.5
4
µA
2.6
350
2.8
V
mV
–10
10
–7
13
%
%
2
µA
0.02
0.1
V
3.3
3.4
V
Rev D
For more information www.analog.com
3
LTM4643
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTM4643 is tested under pulsed load conditions such that
TJ ≈ TA. The LTM4643E is guaranteed to meet performance specifications
over the 0°C to 125°C internal operating temperature range. Specifications
over the full –40°C to 125°C internal operating temperature range are
assured by design, characterization and correlation with statistical process
controls. The LTM4643I is guaranteed to meet specifications over the full
–40°C to 125°C internal operating temperature range. The LTM4643MP
is guaranteed to meet specifications over the full –55°C to 125°C internal
operating temperature range. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
resistance and other environmental factors.
Note 3: 100% tested at wafer level.
Note 4: See output current derating curves for different VIN, VOUT and TA.
Note 5: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Load Current from
5VIN (One Channel Operating)
(Per Channel)
Efficiency vs Load Current from
12VIN (One Channel Operating)
DCM Mode Efficiency from
1.5VOUT
100
95
90
90
90
85
85
80
75
3.3VOUT
2.5VOUT
1.8VOUT
1.5VOUT
1.2VOUT
1.0VOUT
70
65
60
0
0.5
2
1
1.5
OUTPUT CURRENT (A)
80
75
70
3.3VOUT
2.5VOUT
1.8VOUT
1.5VOUT
1.2VOUT
1.0VOUT
65
60
3
2.5
80
55
0
0.5
2
1
1.5
OUTPUT CURRENT (A)
4
50
40
30
5VIN
12VIN
10
0
0.001
0.1
1
0.01
LOAD CURRENT (A)
10
4643 G03
1.2V Output Transient Response
VOUT
50mV/DIV
AC-COUPLED
1.5V Output Transient Response
VOUT
50mV/DIV
AC-COUPLED
LOAD STEP
1A/DIV
LOAD STEP
1A/DIV
4643 G04
VIN = 12V
20µs/DIV
VOUT = 1.0V
OUTPUT CAPACITOR = 1 × 47µF CERAMIC CAP
LOAD STEP = 2A TO 3A WITH 1A/µS SLEW RATE
FEED FORWARD CAP = 100pF
60
4643 G02
1.0V Output Transient Response
LOAD STEP
1A/DIV
70
20
3
2.5
4643 G01
VOUT
50mV/DIV
AC-COUPLED
EFFICIENCY (%)
EFFICIENCY (%)
95
EFFICIENCY (%)
100
4643 G05
VIN = 12V
20µs/DIV
VOUT = 1.2V
OUTPUT CAPACITOR = 1 × 47µF CERAMIC CAP
LOAD STEP = 2A TO 3A WITH 1A/µS SLEW RATE
FEED FORWARD CAP = 100pF
4643 G06
VIN = 12V
20µs/DIV
VOUT = 1.5V
OUTPUT CAPACITOR = 1 × 47µF CERAMIC CAP
LOAD STEP = 2A TO 3A WITH 1A/µS SLEW RATE
FEED FORWARD CAP = 100pF
Rev D
For more information www.analog.com
LTM4643
TYPICAL PERFORMANCE CHARACTERISTICS
1.8V Output Transient Response
VOUT
50mV/DIV
AC-COUPLED
2.5V Output Transient Response
VOUT
50mV/DIV
AC-COUPLED
VOUT
50mV/DIV
AC-COUPLED
LOAD STEP
1A/DIV
LOAD STEP
1A/DIV
4643 G07
VIN = 12V
20µs/DIV
VOUT = 1.8V
OUTPUT CAPACITOR = 1 × 47µF CERAMIC CAP
LOAD STEP = 2A TO 3A WITH 1A/µS SLEW RATE
FEED FORWARD CAP = 100pF
LOAD STEP
1A/DIV
4643 G08
VIN = 12V
20µs/DIV
VOUT = 2.5V
OUTPUT CAPACITOR = 1 × 47µF CERAMIC CAP
LOAD STEP = 2A TO 3A WITH 1A/µS SLEW RATE
FEED FORWARD CAP = 100pF
Start-Up with No Load Applied
4643 G09
VIN = 12V
20µs/DIV
VOUT = 3.3V
OUTPUT CAPACITOR = 1 × 47µF CERAMIC CAP
LOAD STEP = 2A TO 3A WITH 1A/µS SLEW RATE
FEED FORWARD CAP = 100pF
Short-Circuit with No Load
Applied
Start-Up with 3A Load Applied
IIN
0.5A/DIV
IIN
0.5A/DIV
VOUT
0.5V/DIV
VOUT
0.5V/DIV
4643 G10
VIN = 12V
5ms/DIV
VOUT = 1.5V
INPUT CAPACITOR = 1 × 22µF CERAMIC CAP
OUTPUT CAPACITOR = 1 × 47µF CERAMIC CAP
SOFT START = 0.1µF
IIN
0.5A/DIV
VOUT
0.5V/DIV
4643 G11
VIN = 12V
5ms/DIV
VOUT = 1.5V
INPUT CAPACITOR = 1 × 22µF CERAMIC CAP
OUTPUT CAPACITOR = 1 × 47µF CERAMIC CAP
SOFT START = 0.1µF
Short-Circuit with 3A Load
Applied
4643 G12
5ms/DIV
VIN = 12V
VOUT = 1.5V
INPUT CAPACITOR = 1 × 22µF CERAMIC CAP
OUTPUT CAPACITOR = 1 × 47µF CERAMIC CAP
Short-Circuit with 3A Load
Applied
IIN
0.5A/DIV
IIN
0.5A/DIV
VOUT
0.5V/DIV
VOUT
0.5V/DIV
4643 G13
VIN = 12V
20µs/DIV
VOUT = 1.5V
INPUT CAPACITOR = 1 × 22µF CERAMIC CAP
OUTPUT CAPACITOR = 1 × 47µF CERAMIC CAP
3.3V Output Transient Response
Output Ripple
VOUT
5mV/DIV
AC-COUPLED
350kHz
BANDWIDTH
4643 G14
VIN = 12V
20µs/DIV
VOUT = 1.5V
INPUT CAPACITOR = 1 × 22µF CERAMIC CAP
OUTPUT CAPACITOR = 1 × 47µF CERAMIC CAP
4643 G15
2µs/DIV
VIN = 12V
VOUT = 1.5V
OUTPUT CAPACITOR = 2 × 47µF CERAMIC CAP
Rev D
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5
LTM4643
PIN FUNCTIONS
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
VOUT1 (A1, A2, A3), VOUT2 (C1, D1, D2), VOUT3 (F1,
G1, G2), VOUT4 (J1, K1, K2): Power Output Pins of Each
Switching Mode Regulator Channel. Apply output load
between these pins and GND pins. Recommend placing
output decoupling capacitance directly between these pins
and GND pins. See the Applications Information section
for paralleling outputs.
GND (A4-A5, B1-B2, C5, D3-D5, E1-E2, F5, G3-G5,
H1-H2, J5, K3-K4, L1-L2): Power Ground Pins for Both
Input and Output Returns. Use large PCB copper areas to
connect all GND together.
VIN1 (B3, B4), VIN2 (E3, E4), VIN3 (H3, H4), VIN4 (L3, L4):
Power input pins connect to the drain of the internal top
MOSFET for each switching mode regulator channel.
Apply input voltages between these pins and GND pins.
Recommend placing input decoupling capacitance directly
between each of VIN pins and GND pins.
PGOOD1, PGOOD2, PGOOD3, PGOOD4 (C3, C2, F2,
J2): Output Power Good with Open-Drain Logic of Each
Switching Mode Regulator Channel. PGOOD is pulled to
ground when the voltage on the FB pin is not within ±10%
of the internal 0.6V reference.
CLKOUT (J3): Output Clock Signal for PolyPhase® Operation of the Module. The phase of CLKOUT with respect to
CLKIN is set to 180°. CLKOUT’s peak-to-peak amplitude is
INTVCC to GND. See the Applications Information section
for details. Strictly output; do not drive this pin. CLKOUT
is only active when RUN4 is enabled.
INTVCC1, INTVCC2, INTVCC3, INTVCC4 (C4, F4, J4, K5):
Internal 3.3V Regulator Output of Each Switching Mode
Regulator Channel. The internal power drivers and control circuits are powered from this voltage. Each pin is
internally decoupled to GND with 1µF low ESR ceramic
capacitor already.
6
SVIN1, SVIN2, SVIN, SVIN4 (B5, E5, H5, L5): Signal VIN.
Filtered input voltage to the internal 3.3V regulator for
the control circuitry of each Switching mode Regulator
Channel. Tie this pin to the VIN pin respectively in most
applications. Connect SVIN to an external voltage supply
of at least 4V which must also be greater than VOUT.
TRACK/SS1, TRACK/SS2, TRACK/SS3, TRACK/SS4 (A6,
D6, G6, K6): Output Tracking and Soft-Start Pin of Each
Switching Mode Regulator Channel. Allows the user to
control the rise time of the output voltage. Putting a voltage below 0.6V on this pin bypasses the internal reference
input to the error amplifier, instead it servos the FB pin
to match the TRACK voltage. Above 0.6V, the tracking
function stops and the internal reference resumes control
of the error amplifier. There’s an internal 2.5µA pull-up
current from INTVCC on this pin, so putting a capacitor
here provides soft-start function.
MODE1, MODE2, MODE3, MODE4 (B6, E6, H6, L6):
Operation Mode Select for Each Switching Mode Regulator Channel. Tie this pin to INTVCC to force continuous
synchronous operation at all output loads. Tying it to
SGND enables discontinuous current mode operation at
light loads. Do not leave floating.
RUN1, RUN2, RUN3, RUN4 (C6, F6, J6, K7): Run Control
Input of Each Switching Mode Regulator Channel. Enable
regulator operation by tying the specific RUN pin above
1.2V. Pulling it below 1.1V shuts down the respective
regulator channel. Do not leave floating.
FB1, FB2, FB3, FB4 (A7, D7, G7, J7): The Negative Input
of the Error Amplifier for Each Switching Mode Regulator
Channel. Internally, this pin is connected to VOUT of each
channel with a 60.4kΩ precision resistor. Different output
voltages can be programmed with an additional resistor
between the FB and GND pins. In PolyPhase operation,
tying the FB pins together allows for parallel operation.
See the Applications Information section for details.
Rev D
For more information www.analog.com
LTM4643
PIN FUNCTIONS
COMP1, COMP2, COMP3, COMP4 (B7, E7, H7, L7): Current Control Threshold and Error Amplifier Compensation
Point of Each Switching Mode Regulator Channel. The
internal current comparator threshold is proportional to
this voltage. Tie the COMP pins together for parallel operation. The device is internally compensated.
CLKIN (C7): External Synchronization Input to Phase
Detector of the Module. This pin is internally terminated
to SGND with 20kΩ. The phase-locked loop will force
the channel 1 turn-on signal to be synchronized with the
rising edge of the CLKIN signal. Channel 2, channel 3 and
channel 4 will also be synchronized with the rising edge of
the CLKIN signal with a pre-determined phase shift. See
the Applications Information section for details.
SGND (F7): Signal Ground Connection. SGND is connected
to GND internally through single point. Use a separated
SGND ground copper area for the ground of the feedback
resistor and other components connected to signal pins.
A second connection between the PGND plane and SGND
plane is recommended on the backside of the PCB underneath the module.
TEMP (F3): Onboard Temperature Diode for Monitoring
the VBE Junction Voltage Change with Temperature. See
the Applications Information section.
Rev D
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7
LTM4643
BLOCK DIAGRAM
CLKIN
VOUT1
FB1
60.4k
PGOOD1
60.4k
VIN1
INTVCC1
0.22µF
1µF
1µH
MODE1
10µF
VOUT1
POWER CONTROL
TRACK/SS1
0.1µF
100k
SVIN1
1µF
RUN1
47µF
INTVCC1
VIN
4V TO 20V
VOUT1
1.2V
3A
GND
COMP1
CLKOUT
INTERNAL
COMP
SGND
INTERNAL
FILTER
GND
FREQ1
133k
PGOOD2
60.4k
FB2
40.2k
VOUT2
VIN2
INTVCC2
1µF
0.22µF
CLKIN
1µH
MODE2
1µF
RUN2
47µF
VOUT2
1.5V
3A
CLKOUT
INTERNAL
FILTER
FREQ2
133k
VOUT3
PGOOD3
60.4k
FB3
100k
SVIN3
VIN3
INTVCC3
1µF
0.22µF
CLKIN
1µH
MODE3
1µF
RUN3
INTVCC3
VIN
10µF
VOUT3
POWER CONTROL
TRACK/SS3
0.1µF
VIN
GND
COMP2
INTERNAL
COMP
30.1k
INTVCC2
10µF
VOUT2
POWER CONTROL
TRACK/SS2
0.1µF
100k
SVIN2
47µF
VOUT3
1.8V
3A
GND
COMP3
CLKOUT
INTERNAL
COMP
INTERNAL
FILTER
FREQ3
133k
PGOOD4
60.4k
FB4
90.9k
VOUT4
VIN4
INTVCC4
1µF
0.22µF
CLKIN
1µH
MODE4
1µF
RUN4
INTVCC4
VIN
10µF
VOUT4
POWER CONTROL
TRACK/SS4
0.1µF
100k
SVIN4
47µF
VOUT4
1V
3A
GND
COMP4
CLKOUT
INTERNAL
COMP
INTERNAL
FILTER
TEMP
FREQ4
133k
CLKOUT
4643 BD
8
Rev D
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LTM4643
DECOUPLING REQUIREMENTS
(per Channel)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
CIN
External Input Capacitor Requirement
(VIN = 4V to 20V, VOUT = 1.5V)
IOUT = 3A
4.7
10
µF
COUT
External Output Capacitor Requirement
(VIN = 4V to 20V, VOUT = 1.5V)
IOUT = 3A
22
47
µF
OPERATION
The LTM4643 is a quad output standalone non-isolated
switch mode DC/DC power supply in 9mm × 15mm
× 1.82mm ultrathin package. It has four separate regulator channels with each of them capable of delivering up
to 3A continuous output current with few external input
and output capacitors. Each regulator provides precisely
regulated output voltage programmable from 0.6V to
3.3V via a single external resistor over 4V to 20V input
voltage range. With an external bias voltage, this module
can operate from an input voltage as low as 2.375V. The
typical application schematic is shown in Figure 29.
The LTM4643 integrates four separate constant frequency
controlled on-time valley current mode regulators, power
MOSFETs, inductors, and other supporting discrete components. The typical switching frequency is set to 1.2MHz.
For switching noise-sensitive applications, the µModule
regulator can be externally synchronized to a clock from
850kHz to 1.5MHz. See the Applications Information
section.
With current mode control and internal feedback loop
compensation, the LTM4643 module has sufficient stability margins and good transient performance with a wide
range of output capacitors, even with all ceramic output
capacitors.
Current mode control provides the flexibility of paralleling
any of the separate regulator channels with accurate current sharing. With a built-in clock interleaving between
regulator channels, the LTM4643 can easily be configured
for 2+2, 3+1 or 4 channels parallel operation providing
more design flexibility for multirail POL applications. Furthermore, the LTM4643 has CLKIN and CLKOUT pins for
frequency synchronization or polyphasing multiple devices
which allow up to 8 phases cascaded to run simultaneously.
Current mode control also provides cycle-by-cycle fast
current monitoring. Foldback current limiting is provided
in an overcurrent condition to reduce the inductor valley
current to approximately 40% of the original value when
VFB drops. An internal overvoltage and undervoltage
comparators pull the open-drain PGOOD output low if
the output feedback voltage exits a ±10% window around
the regulation point. Continuous conduction mode (CCM)
operation is forced during OV and UV conditions except
during start-up when the TRACK pin is ramping up to 0.6V.
Pulling the RUN pin below 1.1V forces the controller into
its shutdown state, turning off both power MOSFETs and
most of the internal control circuitry. At light load currents, discontinuous conduction mode (DCM) operation
can be enabled to achieve higher efficiency compared to
continuous conduction mode (CCM) by setting the MODE
pin to SGND. The TRACK/SS pin is used for power supply
tracking and soft-start programming. See the Applications
Information section.
A temperature diode is included inside the module to monitor the temperature of the module. See the Applications
Information section for details.
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9
LTM4643
APPLICATIONS INFORMATION
The typical LTM4643 application circuit is shown in
Figure 29. External component selection is primarily
determined by the input voltage, the output voltage and
the maximum load current. Refer to Table 6 for specific
external capacitor requirements for a particular application.
VIN to VOUT Step-Down Ratios
There are restrictions in the maximum VIN and VOUT stepdown ratio that can be achieved for a given input voltage
due to the minimum off-time and minimum on-time limits
of each regulator. The minimum off-time limit imposes a
maximum duty cycle which can be calculated as:
DMAX = 1 – tOFF(MIN) • fSW
where tOFF(MIN) is the minimum off-time, 70ns typical for
LTM4643, and fSW is the switching frequency. Conversely
the minimum on-time limit imposes a minimum duty cycle
of the converter which can be calculated as:
DMIN = tON(MIN) • fSW
where tON(MIN) is the minimum on-time, 40ns typical for
LTM4643. In the rare cases where the minimum duty
cycle is surpassed, the output voltage will still remain
in regulation, but the switching frequency will decrease
from its programmed value. Note that additional thermal
derating may be applied. See the Thermal Considerations
and Output Current Derating section in this data sheet.
Output Voltage Programming
The PWM controller has an internal 0.6V reference voltage.
As shown in the Block Diagram, a 60.4k internal feedback
resistor connects each regulator channel from VOUT pin to
FB pin. Adding a resistor RFB from FB pin to GND programs
the output voltage:
R FB =
60.4k
VOUT
−1
0.6
Table 1. VFB Resistor Table vs Various Output Voltages
VOUT (V)
0.6
1.0
1.2
1.5
1.8
2.5
3.3
RFB (k)
Open
90.9
60.4
40.2
30.1
19.1
13.3
For parallel operation of N channels, use the following
equation can be used to solve for RFB. Tie the VOUT and
10
the FB and COMP pins together for each paralleled output
with a single resistor to GND as determined by:
RFB =
60.4k
N
VOUT
– 1
0.6
Input Decoupling Capacitors
The LTM4643 module should be connected to a low ACimpedance DC source. For each regulator channel, a 10µF
input ceramic capacitor is recommended for RMS ripple
current decoupling. A bulk input capacitor is only needed
when the input source impedance is compromised by long
inductive leads, traces or not enough source capacitance.
The bulk capacitor can be an electrolytic aluminum capacitor or polymer capacitor.
Without considering the inductor ripple current, the RMS
current of the input capacitor can be estimated as:
I CIN(RMS) =
I OUT(MAX )
η%
• D • (1− D)
where η% is the estimated efficiency of the power module.
Output Decoupling Capacitors
With an optimized high frequency, high bandwidth design,
only single piece of low ESR output ceramic capacitor is
required for each regulator channel to achieve low output
voltage ripple and very good transient response. Additional
output filtering may be required by the system designer,
if further reduction of output ripples or dynamic transient
spikes is required. Table 6 provides a reference matrix showing transient performance for different output capacitor configurations. Multiphase operation will reduce effective output ripple as a function of the number of phases. Application
Note 77 discusses this noise reduction versus output ripple
current cancellation, but the output capacitance will be
more a function of stability and transient response. The
LTpowerCAD® Design Tool is available to download online
for output ripple, stability and transient response analysis
and calculating the output ripple reduction as the number
of phases implemented increases by N times.
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LTM4643
APPLICATIONS INFORMATION
Discontinuous Conduction Mode (DCM)
In applications where low output ripple and high efficiency
at intermediate current are desired, discontinuous conduction mode (DCM) should be used by connecting the
MODE pin to SGND. At light loads the internal current
comparator may remain tripped for several cycles and
force the top MOSFET to stay off for several cycles, thus
skipping cycles. The inductor current does not reverse
in this mode.
Force Continuous Conduction Mode (CCM)
In applications where fixed frequency operation is more
critical than low current efficiency, and where the lowest
output ripple is desired, forced continuous conduction
mode operation should be used. Forced continuous operation can be enabled by tying the MODE pin to INTVCC. In
this mode, inductor current is allowed to reverse during
low output loads, the COMP voltage is in control of the
current comparator threshold throughout, and the top
MOSFET always turns on with each oscillator pulse. During
start-up, forced continuous mode is disabled and inductor
current is prevented from reversing until the LTM4643’s
output voltage is in regulation.
Operating Frequency
The operating frequency of the LTM4643 is optimized to
achieve the compact package size and the minimum output
ripple voltage while still keeping high efficiency. The default
operating frequency is internally set to 1.2MHz. In most
applications, no additional frequency adjusting is required.
If any operating frequency other than 1.2MHz is required
by application, the µModule regulator can be externally
synchronized to a clock from 850kHz to 1.5MHz.
Please note, a minimum switching frequency is required
for given VIN, VOUT operating conditions to keep a maximum peak-to-peak inductor ripple current below 2A for
the LTM4643. The peak-to-peak inductor ripple current
can be calculated as:
ΔIPK −PK =
VOUT
FS (MHz)
•
VIN – VOUT
VIN
The maximum 2A peak-to-peak inductor ripple current
is enforced due to the nature of the valley current mode
control to maintain output voltage regulation at no load.
Frequency Synchronization and Clock In
The power module has a phase-locked loop comprised
of an internal voltage controlled oscillator and a phase
detector. This allows all internal top MOSFET turn-on to
be locked to the rising edge of the same external clock.
The external clock frequency range must be within ±30%
around the 1.2MHz set frequency. A pulse detection circuit
is used to detect a clock on the CLKIN pin to turn on the
phase-locked loop. The pulse width of the clock has to
be at least 100ns. The clock high level must be above 2V
and clock low level below 0.3V. During the start-up of
the regulator, the phase-locked loop function is disabled.
Multichannel Parallel Operation
For loads that demand more than 3A of output current,
the LTM4643 multiple regulator channels can be easily
paralleled to provide more output current without increasing input and output voltage ripples. The LTM4643 has
preset built-in phase shift between each two of the four
regulator channels which is suitable to employ a 2+2, 3+1
or 4 channels parallel operation. Table 2 gives the phase
difference between regulator channels.
Table 2. Phase Difference Between Regulator Channels
CHANNEL
Phase Difference
CH1
CH2
180°
CH3
90°
CH4
180°
Figure 1 shows a 2+2 and a 4-channels parallel concept
schematic for clock phasing.
A multiphase power supply significantly reduces the
amount of ripple current in both the input and output capacitors. The RMS input ripple current is reduced by, and
the effective ripple frequency is multiplied by, the number
of phases used (assuming that the input voltage is greater
than the number of phases used times the output voltage).
The output ripple amplitude is also reduced by the number
of phases used when all of the outputs are tied together
to achieve a single high output current design.
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11
LTM4643
APPLICATIONS INFORMATION
CH1
(0°)
180°
VOUT1
CH3
(0°)
CH2
(180°)
VOUT2
FB4
TRACK/SS4
COMP4
RUN4
FB3
TRACK/SS3
COMP3
RUN3
RUNb
FB2
TRACK/SS2
COMP2
RUN2
FB1
TRACK/SS1
COMP1
RUN1
RUNa
180°
VOUT3
CH4
(180°)
VOUT4
Input RMS Ripple Current Cancellation
LTM4643
6A
6A
RUN
VOUT1
180°
CH2
(180°)
90°
VOUT2
CH3
(270°)
VOUT3
FB4
TRACK/SS4
COMP4
RUN4
FB3
TRACK/SS3
COMP3
RUN3
FB2
TRACK/SS2
COMP2
RUN2
FB1
TRACK/SS1
COMP1
RUN1
FB
CH1
(0°)
180°
The LTM4643 device is an inherently current mode controlled device, so parallel modules will have very good
current sharing. This will balance the thermals on the
design. Please tie the RUN, TRACK/SS, FB and COMP
pins of each paralleling channel together. Figure 31 and
Figure 32 show an example of parallel operation and pin
connection.
CH4
(90°)
Application Note 77 provides a detailed explanation of
multiphase operation. The input RMS ripple current cancellation mathematical derivations are presented, and a
graph is displayed representing the RMS ripple current
reduction as a function of the number of interleaved phases.
Figure 2 shows this graph.
Soft-Start and Output Voltage Tracking
VOUT4
LTM4643
4643 F01
12A
Figure 1. 2+2 and 4 Channels Parallel Concept Schematic
The TRACK/SS pin provides a means to either soft-start
of each regulator channel or track it to a different power
supply. A capacitor on the TRACK/SS pin will program the
ramp rate of the output voltage. An internal 2.5µA current
source will charge up the external soft-start capacitor
0.60
0.55
1-PHASE
2-PHASE
4-PHASE
0.50
RMS INPUT RIPPLE CURRENT
DC LOAD CURRENT
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
DUTY CYCLE (VOUT/VIN)
4643 F02
Figure 2. Normalized RMS Ripple Current for Single Phase or Polyphase Applications
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LTM4643
APPLICATIONS INFORMATION
towards the INTVCC voltage. When the TRACK/SS voltage
is below 0.6V, it will take over the internal 0.6V reference
voltage to control the output voltage. The total soft-start
time can be calculated as:
VOUT2 = 2.5V
OUTPUT VOLTAGE
t SS = 0.6 •
VOUT1 = 3.3V
C SS
2.5µA
VOUT3 = 1.8V
VOUT4 = 1.2V
where CSS is the capacitance on the TRACK/SS pin. Current foldback and forced continuous mode are disabled
during the soft-start process.
Output voltage tracking can also be programmed externally
using the TRACK/SS pin of each regulator channel. The
output can be tracked up and down with another regulator. Figure 3 and Figure 4 show an example waveform
and schematic of a ratiometric tracking where the slave
regulator’s (VOUT2 , VOUT3 and VOUT4) output slew rate is
proportional to the master’s (VOUT1).
Since the slave regulator’s TRACK/SS is connected to
the master’s output through a RTR(TOP)/RTR(BOT) resistor
divider and its voltage used to regulate the slave output
TIME
4643 F03
Figure 3. Output Ratiometric Tracking Waveform
voltage when TRACK/SS voltage is below 0.6V, the slave
output voltage and the master output voltage should satisfy
the following equation during the start-up.
VOUT(SL) •
R FB(SL)
R FB(SL) + 60.4k
= VOUT(MA ) •
R TR(BOT)
R TR(TOP) + R TR(BOT)
VIN4
SVIN4
RUN4
INTVCC4
MODE4
CH3
CH4
VOUT2
FB2
COMP2
TRACK/SS2
PGOOD2
VOUT3
FB3
COMP3
TRACK/SS3
PGOOD3
VOUT4
FB4
COMP4
TRACK/SS4
PGOOD4
RFB2
19.1k
RFB3
30.1k
RFB4
60.4k
3.3V/3A
RFB1
13.3k
2.5V/3A
CSS
0.1µF
RTR2(TOP)
60.4k
1.2V/3A
VIN3
SVIN3
RUN3
INTVCC3
MODE3
CH2
1.8V/3A
VIN2
SVIN2
RUN2
INTVCC2
MODE2
CH1
VOUT1
FB1
COMP1
TRACK/SS1
PGOOD1
VIN1
SVIN1
RUN1
INTVCC1
MODE1
VIN
5V TO 20V
4643 F04
RTR2(BOT)
13.3k
RTR3(TOP)
60.4k
RTR3(BOT)
13.3k
RTR4(TOP)
60.4k
RTR4(BOT)
13.3k
Figure 4. Output Ratiometric Tracking Schematic
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13
LTM4643
APPLICATIONS INFORMATION
The RFB(SL) is the feedback resistor and the RTR(TOP)/
RTR(BOT) is the resistor divider on the TRACK/SS pin of
the slave regulator, as shown in Figure 4.
Following the upper equation, the master’s output slew
rate (MR) and the slave’s output slew rate (SR) in volts/
time is determined by:
R FB(SL)
MR
SR
=
R TR(TOP) + R TR(BOT)
For example, VOUT(MA) = 3.3V, MR = 3.3V/ms and VOUT(SL)
= 1.2V, SR = 1.2V/ms as VOUT1 and VOUT4 shown in
Figure 4. From the equation, we could solve out that
RTR4(TOP) = 60.4k and RTR4(BOT) = 13.3k is a good combination. Follow the same equation, we can get the same
RTR(TOP) /RTR(BOT) resistor divider value for VOUT2 and
VOUT3.
The TRACK pins will have the 2.5µA current source on
when a resistive divider is used to implement tracking on
that specific channel. This will impose an offset on the
TRACK pin input. Smaller value resistors with the same
ratios as the resistor values calculated from the above
equation can be used. For example, where the 60.4k is
used then a 6.04k can be used to reduce the TRACK pin
offset to a negligible value.
The coincident output tracking can be recognized as a
special ratiometric output tracking which the master’s
output slew rate (MR) is the same as the slave’s output
slew rate (SR), as waveform shown in Figure 5.
R FB(SL) + 60.4k
=
R TR(BOT)
R TR(TOP) + R TR(BOT)
Power Good
The PGOOD pins are open drain pins that can be used
to monitor each valid output voltage regulation. This pin
monitors a ±10% window around the regulation point. A
resistor can be pulled up to a particular supply voltage for
monitoring. To prevent unwanted PGOOD glitches during transients or dynamic VOUT changes, the LTM4643’s
PGOOD falling edge includes a blanking delay of approximately 52 switching cycles.
Stability Compensation
The LTM4643 module internal compensation loop of each
regulator channel is designed and optimized for low ESR
ceramic output capacitors only application. Table 6 is
provided for most application requirements. An optional
100pF phase boost capacitor could help to boost up the
phase margin in all ceramic output capacitors application.
The LTpowerCAD Design Tool is available to download for
control loop optimization.
RUN Enable
Pulling the RUN pin of each regulator channel to ground
forces the regulator into its shutdown state, turning off both
power MOSFETs and most of its internal control circuitry.
Bringing the RUN pin above 0.7V turns on the internal
reference only, while still keeping the power MOSFETs
off. Further increasing the RUN pin voltage above 1.2V
will turn on the entire regulator channel.
VOUT1 = 3.3V
VOUT2 = 2.5V
OUTPUT VOLTAGE
R FB(SL)
For example, RTR4(TOP) = 60.4k and RTR4(BOT) = 60.4k is
a good combination for coincident tracking for VOUT(MA)
= 3.3V and VOUT(SL) = 1.2V application.
R FB(SL) + 60.4k
R TR(BOT)
VOUT3 = 1.8V
VOUT4 = 1.2V
TIME
From the equation we could easily find out that, in the
coincident tracking, the slave regulator’s TRACK/SS pin
resistor divider is always the same as its output voltage
divider.
4643 F05
Figure 5. Output Coincident Tracking Waveform
14
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APPLICATIONS INFORMATION
Pre-Biased Output Start-Up
Temperature Monitoring
There may be situations that require the power supply to
start up with some charge on the output capacitors. The
LTM4643 can safely power up into a pre-biased output
without discharging it.
A diode connected PNP transistor is used for the TEMP
monitor function by monitoring its voltage over temperature. The temperature dependence of this diode voltage
can be understood in the equation:
The LTM4643 accomplishes this by forcing discontinuous
mode (DCM) operation until the TRACK/SS pin voltage
reaches 0.6V reference voltage. This will prevent the BG
from turning on during the pre-biased output start-up
which would discharge the output.
Do not pre-bias LTM4643 with an output voltage higher
than INTVCC (3.3V).
where VT is the thermal voltage (kT/q), and n, the ideality
factor, is 1 for the diode connected PNP transistor being used in the LTM4643. IS is expressed by the typical
empirical equation:
Overtemperature Protection
The internal overtemperature protection monitors the junction temperature of the module. If the junction temperature
reaches approximately 160°C, both power switches will be
turned off until the temperature drops about 15°C cooler.
Low Input Application
The LTM4643 module has a separate SVIN pin for each
regulator channel which makes it compatible with operation from an input voltage as low as 2.375V. The SVIN pin
is the signal input of the regulator control circuitry while
the VIN pin is the power input which directly connected
to the drain of the top MOSFET. In most application with
input voltage ranges from 4V to 20V, connect the SVIN
pin directly to the VIN pin of each regulator channel. An
optional filter, consisting of a resistor (1Ω to 10Ω) between
SVIN and VIN ground, can be placed for additional noise
immunity. This filter is not necessary in most cases if
good PCB layout practices are followed (see Figure 28).
In a low input voltage (2.375V to 4V) application, or to
reduce power dissipation by the internal bias LDO, connect
SVIN to an external voltage higher than 4V with a 0.1µF
local bypass capacitor. Figure 30 shows an example of a
low input voltage application. Please note, SVIN voltage
cannot go below VOUT voltage.
⎛I ⎞
VD = nVT ln ⎜⎜ D ⎟⎟
⎜I ⎟
⎝ S⎠
⎛ –V ⎞
G0 ⎟
IS = I0 exp ⎜⎜
⎟
V
T
⎝
⎠
where I0 is a process and geometry dependent current, (I0
is typically around 20k orders of magnitude larger than IS
at room temperature) and VG0 is the band gap voltage of
1.2V extrapolated to absolute zero or –273°C.
If we take the IS equation and substitute into the VD equation, then we get:
⎛ kT ⎞ ⎛ I ⎞
⎟ ln ⎜ 0 ⎟ , V = kT
VD = VG0 – ⎜⎜
T
⎟ ⎜ ⎟
q
⎝ q ⎠ ⎝ ID ⎠
The expression shows that the diode voltage decreases
(linearly if I0 were constant) with increasing temperature
and constant diode current. Figure 6 shows a plot of VD
vs Temperature over the operating temperature range of
the LTM4643.
If we take this equation and differentiate it with respect to
temperature T, then:
dVD
dT
=–
VG0 – VD
T
This dVD/dT term is the temperature coefficient equal to
about –2mV/K or –2mV/°C. The equation is simplified for
the first order derivation.
Solving for T, T = –(VG0 – VD)/(dVD/dT) provides the
temperature.
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LTM4643
APPLICATIONS INFORMATION
1st Example: Figure 6 for 27°C, or 300K the diode
voltage is 0.598V, thus, 300K = –(1200mV – 598mV)/
–2.0 mV/K)
The motivation for providing these thermal coefficients in
found in JESD 51-12 (“Guidelines for Reporting and Using
Electronic Package Thermal Information”).
2nd Example: Figure 6 for 75°C, or 350K the diode
voltage is 0.50V, thus, 350K = –(1200mV – 500mV)/
–2.0mV/K)
Many designers may opt to use laboratory equipment
and a test vehicle such as the demo board to predict the
µModule regulator’s thermal performance in their application at various electrical and environmental operating
conditions to compliment any FEA activities. Without FEA
software, the thermal resistances reported in the Pin Configuration section are in-and-of themselves not relevant to
providing guidance of thermal performance; instead, the
derating curves provided in this data sheet can be used
in a manner that yields insight and guidance pertaining to
one’s application-usage, and can be adapted to correlate
thermal performance to one’s own application.
Converting the Kelvin scale to Celsius is simply taking the
Kelvin temp and subtracting 273 from it.
A typical forward voltage is given in the Electrical Characteristics section of the data sheet, and Figure 6 is the plot
of this forward voltage. Measure this forward voltage at
27°C to establish a reference point. Then using the above
expression while measuring the forward voltage over
temperature will provide a general temperature monitor.
Connect a resistor between TEMP and VIN to set the current to 100µA. See Figure 31 for an example.
0.8
ID = 100µA
1. θJA, the thermal resistance from junction to ambient, is the natural convection junction-to-ambient
air thermal resistance measured in a one cubic foot
sealed enclosure. This environment is sometimes
referred to as “still air” although natural convection
causes the air to move. This value is determined with
the part mounted to a JESD 51-9 defined test board,
which does not reflect an actual application or viable
operating condition.
DIODE VOLTAGE (V)
0.7
0.6
0.5
0.4
0.3
–50
–25
50
25
0
75
TEMPERATURE (°C)
100
125
4643 F06
Figure 6. Diode Voltage VD vs Temperature T(°C)
Thermal Considerations and Output Current Derating
The thermal resistances reported in the Pin Configuration section of the data sheet are consistent with those
parameters defined by JESD 51-12 and are intended for
use with finite element analysis (FEA) software modeling
tools that leverage the outcome of thermal modeling,
simulation, and correlation to hardware evaluation performed on a µModule package mounted to a hardware
test board: defined by JESD 51-9 (“Test Boards for Area
Array Surface Mount Package Thermal Measurements”).
16
The Pin Configuration section typically gives four thermal
coefficients explicitly defined in JESD 51-12; these coefficients are quoted or paraphrased below:
2. θJCbottom, the thermal resistance from junction to the
bottom of the product case, is determined with all of
the component power dissipation flowing through the
bottom of the page. In the typical µModule regulator,
the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient
environment. As a result, this thermal resistance value
may be useful for comparing packages but the test
conditions don’t generally match the user’s application.
3. θJCtop, the thermal resistance from junction to top of
the product case, is determined with nearly all of the
component power dissipation flowing through the top
of the package. As the electrical connections of the
typical µModule regulator are on the bottom of the
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LTM4643
APPLICATIONS INFORMATION
package, it is rare for an application to operate such
that most of the heat flows from the junction to the
top of the part. As in the case of θJCbottom, this value
may be useful for comparing packages but the test
conditions don’t generally match the user’s application.
4. θJB, the thermal resistance from junction to the printed
circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the
bottom of the µModule regulator and into the board,
and is really the sum of the θJCbottom and the thermal
resistance of the bottom of the part through the solder
joints and through a portion of the board. The board
temperature is measured a specified distance from
the package.
A graphical representation of the aforementioned thermal resistances is given in Figure 7; blue resistances are
contained within the μModule regulator, whereas green
resistances are external to the µModule package.
As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD 51-12 or provided in the
Pin Configuration section replicates or conveys normal
operating conditions of a μModule regulator. For example,
in normal board-mounted applications, never does 100%
of the device’s total power loss (heat) thermally conduct
exclusively through the top or exclusively through bottom of the µModule package—as the standard defines
for θJCtop and θJCbottom, respectively. In practice, power
loss is thermally dissipated in both directions away from
the package—granted, in the absence of a heat sink and
airflow, a majority of the heat flow is into the board.
Within the LTM4643, be aware there are multiple power
devices and components dissipating power, with a consequence that the thermal resistances relative to different
junctions of components or die are not exactly linear with
respect to total package power loss. To reconcile this
complication without sacrificing modeling simplicity—
but also, not ignoring practical realities—an approach
has been taken using FEA software modeling along with
laboratory testing in a controlled-environment chamber
to reasonably define and correlate the thermal resistance
values supplied in this data sheet: (1) Initially, FEA software
is used to accurately build the mechanical geometry of
the LTM4643 and the specified PCB with all of the correct material coefficients along with accurate power loss
source definitions; (2) this model simulates a softwaredefined JEDEC environment consistent with JESD 51-12
to predict power loss heat flow and temperature readings
at different interfaces that enable the calculation of the
JEDEC-defined thermal resistance values; (3) the model
and FEA software is used to evaluate the LTM4643 with
heat sink and airflow; (4) having solved for and analyzed
these thermal resistance values and simulated various
operating conditions in the software model, a thorough
laboratory evaluation replicates the simulated conditions
with thermocouples within a controlled-environment
chamber while operating the device at the same power loss
JUNCTION-TO-AMBIENT THERMAL RESISTANCE COMPONENTS
JUNCTION-TO-CASE (TOP)
RESISTANCE
JUNCTION
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION-TO-CASE
CASE (BOTTOM)-TO-BOARD
(BOTTOM) RESISTANCE
RESISTANCE
AMBIENT
BOARD-TO-AMBIENT
RESISTANCE
4643 F07
µMODULE DEVICE
Figure 7. Graphical Representation of JESD 51-12 Thermal Coefficients
Rev D
For more information www.analog.com
17
LTM4643
APPLICATIONS INFORMATION
as that which was simulated. An outcome of this process
and due diligence yields the set of derating curves shown
in this data sheet.
The 1V to 3.3V power loss curves in Figures 8 to 13 can
be used in coordination with the load current derating
curves in Figures 14 to 25 for calculating an approximate
θJA thermal resistance for the LTM4643 with various heat
sinking and airflow conditions. The power loss curves are
taken at room temperature, and are increased with a multiplicative factor according to the junction temperature. This
approximate factor is 1.3 for 120°C. The derating curves
are plotted with the output current starting at 12A and the
ambient temperature starting at 30°C. These are chosen
to include the lower and higher output voltage ranges
for correlating the thermal resistance. Thermal models
are derived from several temperature measurements in a
controlled temperature chamber along with thermal modeling analysis. The junction temperatures are monitored
while ambient temperature is increased with and without
airflow. The power loss increase with ambient temperature
change is factored into the derating curves. The junctions
are maintained at 120°C maximum while lowering output
current or power with increasing ambient temperature. The
decreased output current will decrease the internal module
loss as ambient temperature is increased. The monitored
junction temperature of 120°C minus the ambient operating temperature specifies how much module temperature
rise can be allowed. As an example, in Figure 19 the load
current is derated to 10A at ~67°C with 200LFM of airflow
and no heat sink and the power loss for the 12V to 1.5V
at 10A output is about 4.5W. The 4.5W loss is calculated
with 4 times the 0.87W room temperature loss from the
12V to 1.5V power loss curve each channel at 2.5A, and
the 1.3 multiplying factor at 120°C junction. If the 67°C
ambient temperature is subtracted from the 120°C junction
temperature, then the difference of 53°C divided by 4.5W
equals 11.7°C/W θJA thermal resistance. Table 3 specifies
a 12°C/W value which is very close. Tables 3 to 5 provide
equivalent thermal resistances for the different outputs
with and without airflow and heat sinking. The derived
thermal resistances in Tables 3 to 6 for the various condi-
18
tions can be multiplied by the calculated power loss as
a function of ambient temperature to derive temperature
rise above ambient, thus maximum junction temperature.
Room temperature power loss can be derived from the
efficiency curves in the Typical Performance Characteristics
section and adjusted with the above junction temperature
multiplicative factor. The printed circuit board is a 1.6mm
thick four layer board with two ounce copper for the two
outer layers and one ounce copper for the two inner layers.
The PCB dimensions are 95mm × 76mm.
The 12A represents all four channels in parallel at 3A each.
The four parallel channels have their currents reduced at
the same rate to develop an equivalent θJA circuit evaluation with thermal couples or IR camera used to validate
the thermal resistance values.
Maximum Operating Ambient Temperature
Figures 26 and 27 display the Maximum Power
Loss Allowance Curves vs ambient temperature
with various heat sinking and airflow conditions.
This data was derived from the thermal impedance generated by various thermal derating examinations with the
junction temperature measured at 120°C. This maximum
power loss limitation serves as a guideline when designing
multiple output rails with different voltages and currents
by calculating the total power loss.
For example, to determine the maximum ambient temperature when VOUT1 = 2.5V at 0.6A, VOUT2 = 3.3V at 3A,
VOUT3 = 1.8V at 1A, VOUT4 = 1.2V at 3A, without a heat
sink and 400LFM airflow, simply add up the total power
loss for each channel read from Figure 8 to Figure 13
which in this example equals 3.0W, then multiply by
the 1.3 coefficient for 120°C junction temperature and
compare the total power loss number, 3.9W, with Figure 26.
Figure 26 indicates with a 3.9W total power loss, the
maximum ambient temperature for this particular application is around 77°C. Also from Figure 26, it is easy
to determine with a 3.4W total power loss, the maximum
ambient temperature is around 63°C with no airflow and
73°C with 200LFM airflow.
Rev D
For more information www.analog.com
LTM4643
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
5VIN
12VIN
POWER LOSS (W)
POWER LOSS (W)
APPLICATIONS INFORMATION
0
0.5
1.5
2
1
LOAD CURRENT (A)
3
2.5
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
POWER LOSS (W)
POWER LOSS (W)
0.5
1.5
2
1
LOAD CURRENT (A)
2.5
3
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
POWER LOSS (W)
POWER LOSS (W)
0.5
1.5
2
1
LOAD CURRENT (A)
2.5
0
0.5
3
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
4643 F09
1.5
2
1
LOAD CURRENT (A)
3
2.5
4643 F11
5VIN
12VIN
0
0.5
4643 F12
Figure 12. Power Loss at 2.5V
Output, (Each Channel, 25°C)
3
2.5
Figure 11. Power Loss at 1.8V
Output, (Each Channel, 25°C)
5VIN
12VIN
0
1.5
2
1
LOAD CURRENT (A)
5VIN
12VIN
4643 F10
Figure 10. Power Loss at 1.5V
Output, (Each Channel, 25°C)
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.5
Figure 9. Power Loss at 1.2V
Output, (Each Channel, 25°C)
5VIN
12VIN
0
0
4643 F08
Figure 8. Power Loss at 1.0V
Output, (Each Channel, 25°C)
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
5VIN
12VIN
1.5
2
1
LOAD CURRENT (A)
2.5
3
4643 F13
Figure 13. Power Loss at 3.3V
Output, (Each Channel, 25°C)
Rev D
For more information www.analog.com
19
LTM4643
14
14
12
12
12
10
8
6
4
0LFM
200LFM
400LFM
2
0
30
40
MAX LOAD CURRENT (A)
14
MAX LOAD CURRENT (A)
MAX LOAD CURRENT (A)
APPLICATIONS INFORMATION
10
8
6
4
0LFM
200LFM
400LFM
2
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
0
30
40
4643 F14
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4643 F15
Figure 15. 12VIN to 1.0VOUT Derating
Curve, 4-Channel Paralleled,
No Heat Sink
14
14
12
12
10
8
6
4
0LFM
200LFM
400LFM
2
0
30
40
12
MAX LOAD CURRENT (A)
MAX LOAD CURRENT (A)
12
0
30
40
30
40
20
4643 F16
Figure 16. 5VIN to 1.0VOUT Derating
Curve, 4-Channel Paralleled,
BGA Heat Sink
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
10
8
6
4
0LFM
200LFM
400LFM
0
30
40
4643 F19
Figure 19. 12VIN to 1.5VOUT Derating
Curve, 4-Channel Paralleled,
No Heat Sink
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
0LFM
200LFM
400LFM
2
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
40
Figure 18. 5VIN to 1.5VOUT Derating
Curve, 4-Channel Paralleled,
No Heat Sink
14
2
30
4
14
0LFM
200LFM
400LFM
0
4643 F18
Figure 17. 12VIN to 1.0VOUT Derating
Curve, 4-Channel Paralleled,
BGA Heat Sink
4
0LFM
200LFM
400LFM
6
4643 F17
6
4
8
0
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
8
6
10
2
10
8
2
MAX LOAD CURRENT (A)
MAX LOAD CURRENT (A)
Figure 14. 5VIN to 1.0VOUT Derating
Curve, 4-Channel Paralleled,
No Heat Sink
10
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4643 F20
Figure 20. 5VIN to 1.5VOUT Derating
Curve, 4-Channel Paralleled,
BGA Heat Sink
For more information www.analog.com
Rev D
LTM4643
14
12
12
12
10
8
6
4
0LFM
200LFM
400LFM
2
0
30
40
10
8
6
4
0LFM
200LFM
400LFM
2
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
0
30
40
4643 F21
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4643 F22
Figure 22. 5VIN to 3.3VOUT Derating
Curve, 4-Channel Paralleled,
No Heat Sink
14
14
12
12
10
8
6
4
0LFM
200LFM
400LFM
2
0
30
40
9
POWER LOSS ALLOWANCE (W)
9
2
0LFM
200LFM
400LFM
1
0
30
40
30
40
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4643 F23
Figure 23. 12VIN to 3.3VOUT Derating
Curve, 4-Channel Paralleled,
No Heat Sink
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
8
7
6
5
4
3
2
0LFM
200LFM
400LFM
0
30
40
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4643 F27
4643 F26
Figure 26. Power Loss Allowance vs.
Ambient Temperature, No Heat Sink
40
0LFM
200LFM
400LFM
1
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
30
Figure 25. 12VIN to 3.3VOUT Derating
Curve, 4-Channel Paralleled,
BGA Heat Sink
10
3
0
4
10
4
0LFM
200LFM
400LFM
4643 F25
Figure 24. 5VIN to 3.3VOUT Derating
Curve, 4-Channel Paralleled,
BGA Heat Sink
5
4
6
4643 F24
6
6
8
0
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
7
8
10
2
8
10
2
MAX LOAD CURRENT (A)
MAX LOAD CURRENT (A)
Figure 21. 12VIN to 1.5VOUT Derating
Curve, 4-Channel Paralleled,
BGA Heat Sink
MAX LOAD CURRENT (A)
14
MAX LOAD CURRENT (A)
14
POWER LOSS ALLOWANCE (W)
MAX LOAD CURRENT (A)
APPLICATIONS INFORMATION
Figure 27. Power Loss Allowance vs.
Ambient Temperature, BGA Heat Sink
Rev D
For more information www.analog.com
21
LTM4643
APPLICATIONS INFORMATION
Table 3. 1.0V Output
DERATING CURVE
Figures 14,15
Figures 14, 15
Figures 14, 15
Figures 16, 17
Figures 16, 17
Figures 16, 17
VIN (V)
5, 12
5, 12
5, 12
5, 12
5, 12
5, 12
POWER LOSS CURVE
Figure 8
Figure 8
Figure 8
Figure 8
Figure 8
Figure 8
AIR FLOW (LFM)
0
200
400
0
200
400
HEAT SINK
None
None
None
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
ΘJA (°C/W)
14.5
12
11
13.5
10
9
DERATING CURVE
VIN (V)
POWER LOSS CURVE
AIR FLOW (LFM)
HEAT SINK
ΘJA (°C/W)
Figures 18, 19
Figures 18, 19
Figures 18, 19
Figures 20, 21
Figures 20, 21
Figures 20, 21
5, 12
5, 12
5, 12
5, 12
5, 12
5, 12
Figure 10
Figure 10
Figure 10
Figure 10
Figure 10
Figure 10
0
200
400
0
200
400
None
None
None
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
14.5
12
11
13.5
10
9
VIN (V)
5, 12
5, 12
5, 12
5, 12
5, 12
5, 12
POWER LOSS CURVE
Figure 13
Figure 13
Figure 13
Figure 13
Figure 13
Figure 13
AIR FLOW (LFM)
0
200
400
0
200
400
HEAT SINK
None
None
None
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
ΘJA (°C/W)
14.5
12
11
13.5
10
9
Table 4. 1.5V Output
Table 5. 3.3V Output
DERATING CURVE
Figures 22, 23
Figures 22, 23
Figures 22, 23
Figures 24, 25
Figures 24, 25
Figures 24, 25
22
Rev D
For more information www.analog.com
LTM4643
APPLICATIONS INFORMATION
Table 6.
CIN
PART NUMBER
VALUE
COUT1
(CERAMIC)
PART NUMBER
Murata
GRM21BR61E106KA73L
10µF, 25V,
0805, X5R
10µF, 25V,
0805, X5R
22µF, 25V,
1206, X5R
22µF, 25V,
1206, X5R
Murata
GRM21BR60J476ME15 47µF, 6.3V,
0805, X5R
JMK212BJ476MG-T
47µF, 6.3V,
0805, X5R
Taiyo Yuden TMK212BBJ106KG-T
Murata
GRM31CR61C226ME15L
Taiyo Yuden TMK316BBJ226ML-T
VOUT (V)
Taiyo Yuden
VALUE
COUT1
(POSCAP)
PART NUMBER
VALUE
Sanyo
4TPE100MZB
4V 100µF
CIN
(CERAMIC)
(µF)
COUT1
(µF)
CFF
(pF)
VIN
(V)
DROOP
(mv)
P-P DERIVATION
(mV)
RECOVERY
TIME
(µs)
LOAD STEP
(A)
LOAD STEP
SLEW RATE
(A/µs)
RFB
(kΩ)
10
10
10
10
10
10
47
47
47
47
47
47
100
100
100
100
100
100
5, 12
5, 12
5, 12
5, 12
5, 12
5, 12
1
1
1
1
2
3
59
59
66
75
108
111
40
40
40
40
50
60
2A to 3A
2A to 3A
2A to 3A
2A to 3A
2A to 3A
2A to 3A
0
0
0
0
0
0
90.9
60.4
40.2
30.1
19.1
13.3
10
10
10
10
10
10
100
100
100
100
100
100
5, 12
5, 12
5, 12
5, 12
5, 12
5, 12
1
1
1
1
2
3
89
94
108
120
144
161
40
40
40
40
50
60
2A to 3A
2A to 3A
2A to 3A
2A to 3A
2A to 3A
2A to 3A
0
0
0
0
0
0
90.9
60.4
40.2
30.1
19.1
13.3
CERAMIC ONLY
1
1.2
1.5
1.8
2.5
3.3
POSCAP
1
1.2
1.5
1.8
2.5
3.3
Rev D
For more information www.analog.com
23
LTM4643
APPLICATIONS INFORMATION
Safety Considerations
The LTM4643 modules do not provide galvanic isolation
from VIN to VOUT. There is no internal fuse. If required,
a slow blow fuse with a rating twice the maximum input
current needs to be provided to protect each unit from
catastrophic failure. The device does support thermal
shutdown and overcurrent protection.
Layout Checklist/Example
The high integration of LTM4643 makes the PCB board
layout very simple and easy. However, to optimize its electrical and thermal performance, some layout considerations
are still necessary.
• Use large PCB copper areas for high current paths,
including VIN1 to VIN4, GND, VOUT1 to VOUT4. It helps to
minimize the PCB conduction loss and thermal stress.
• Place high frequency ceramic input and output capacitors next to the VIN, GND and VOUT pins to minimize
high frequency noise.
• Place a dedicated power ground layer underneath the
unit.
• To minimize the via conduction loss and reduce module
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
• Do not put via directly on the pad, unless they are
capped or plated over.
• Use a separated SGND ground copper area for components connected to signal pins. Connect the SGND
to GND underneath the unit.
• For parallel modules, tie the VOUT, VFB, and COMP pins
together. Use an internal layer to closely connect these
pins together. The TRACK/SS pin can be tied a common
capacitor for regulator soft-start.
• Bring out test points on the signal pins for monitoring.
Figure 28 gives a good example of the recommended layout.
Figure 28. Recommended PCB Layout
24
Rev D
For more information www.analog.com
LTM4643
TYPICAL APPLICATIONS
4V to 20V
CLKIN
CLKOUT
VIN1
VOUT1
SVIN1
FB1
LTM4643
RUN1
COMP1
INTVCC1
TRACK/SS1
MODE1
PGOOD1
10µF
×4
25V
1206
VIN2
SVIN2
RUN2
INTVCC2
MODE2
VOUT2
FB2
COMP2
TRACK/SS2
PGOOD2
VIN3
SVIN3
RUN3
INTVCC3
MODE3
VOUT3
FB3
COMP3
TRACK/SS3
PGOOD3
VIN4
SVIN4
RUN4
INTVCC4
MODE4
VOUT4
FB4
COMP4
TRACK/SS4
PGOOD4
TEMP
SGND
3.3V/3A
47µF
6.3V
0805
13.3k
0.1µF
2.5V/3A
19.1k
47µF
4V
0805
60.4k
1.5V/3A
40.2k
47µF
4V
0805
13.3k
60.4k
1V/3A
90.9k
47µF
4V
0805
13.3k
60.4k
GND
13.3k
4643 F29
Figure 29. 4V to 20V Input, Quad 1.0V, 1.5V, 2.5V and 3.3V Output with Ratiometric Tracking
2.375V to 5V
10µF
×4
6.3V
1206
5V BIAS
1µF
6.3V
CLKIN
CLKOUT
VIN1
VOUT1
SVIN1
FB1
LTM4643
RUN1
COMP1
INTVCC1
TRACK/SS1
MODE1
PGOOD1
VIN2
SVIN2
RUN2
INTVCC2
MODE2
VOUT2
FB2
COMP2
TRACK/SS2
PGOOD2
VIN3
SVIN3
RUN3
INTVCC3
MODE3
VOUT3
FB3
COMP3
TRACK/SS3
PGOOD3
VIN4
SVIN4
RUN4
INTVCC4
MODE4
VOUT4
FB4
COMP4
TRACK/SS4
PGOOD4
TEMP
SGND
30.1k
47µF
4V
0805
40.2k
47µF
4V
0805
60.4k
47µF
4V
0805
90.9k
47µF
4V
0805
1.8V/3A
0.1µF
1.5V/3A
0.1µF
1.2V/3A
0.1µF
1V/3A
0.1µF
GND
4643 F30
Figure 30. 2.375V to 5V Input, Quad 1V, 1.2V, 1.5V, 1.8V Output
Rev D
For more information www.analog.com
25
LTM4643
TYPICAL APPLICATIONS
VIN
4V to 20V
CLKIN
CLKOUT
VIN1
VOUT1
SVIN1
FB1
LTM4643
RUN1
COMP1
INTVCC1
TRACK/SS1
MODE1
PGOOD1
22µF
×2
25V
1206
VIN
V – 0.6V
RT = IN
100µA
VIN2
SVIN2
RUN2
INTVCC2
MODE2
VOUT2
FB2
COMP2
TRACK/SS2
PGOOD2
VIN3
SVIN3
RUN3
INTVCC3
MODE3
VOUT3
FB3
COMP3
TRACK/SS3
PGOOD3
VIN4
SVIN4
RUN4
INTVCC4
MODE4
VOUT4
FB4
COMP4
TRACK/SS4
PGOOD4
TEMP
RT
SGND
15.1k
47µF
×3
4V
0805
1.2V/12A
0.1µF
GND
4643 F31
A/D
Figure 31. 4V to 20V Input, 4-Phase, 1.2V at 12A Design with Temperature Monitoring
26
Rev D
For more information www.analog.com
LTM4643
TYPICAL APPLICATIONS
5V
12V
22µF
×2
16V
1206
22µF
×2
16V
1206
CLKIN
CLKOUT
VIN1
VOUT1
SVIN1
FB1
LTM4643
RUN1
COMP1
INTVCC1
TRACK/SS1
MODE1
PGOOD1
VIN2
SVIN2
RUN2
INTVCC2
MODE2
VOUT2
FB2
COMP2
TRACK/SS2
PGOOD2
VIN3
SVIN3
RUN3
INTVCC3
MODE3
VOUT3
FB3
COMP3
TRACK/SS3
PGOOD3
VIN4
SVIN4
RUN4
INTVCC4
MODE4
VOUT4
FB4
COMP4
TRACK/SS4
PGOOD4
TEMP
SGND
30.2k
47µF
×2
4V
0805
6.65k
47µF
×2
6.3V
0805
1.2V/6A
0.1µF
3.3V/6A
0.1µF
GND
4643 F32
Figure 32. 12V and 5V Two Separate Input Rails, 1.2V at 6A and 3.3V at 6A Output
Rev D
For more information www.analog.com
27
LTM4643
PACKAGE DESCRIPTION
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
LTM4643 Component LGA and BGA Pinout
PIN
NAME
PIN
NAME
PIN
NAME
PIN
NAME
PIN
NAME
PIN
NAME
A1
VOUT1
B1
GND
C1
VOUT2
D1
VOUT2
E1
GND
F1
VOUT3
A2
VOUT1
B2
GND
C2
PGOOD2
D2
VOUT2
E2
GND
F2
PGOOD3
A3
VOUT1
B3
VIN1
C3
PGOOD1
D3
GND
E3
VIN2
F3
TEMP
A4
GND
B4
VIN1
C4
INTVCC1
D4
GND
E4
VIN2
F4
INTVCC2
A5
GND
B5
SVIN1
C5
GND
D5
GND
E5
SVIN2
F5
GND
A6
TRACK/SS1
B6
MODE1
C6
RUN1
D6
TRACK/SS2
E6
MODE2
F6
RUN2
A7
FB1
B7
COMP1
C7
CLKIN
D7
FB2
E7
COMP2
F7
SGND
PIN
NAME
PIN
NAME
PIN
NAME
PIN
NAME
PIN
NAME
G1
VOUT3
H1
GND
J1
VOUT4
K1
VOUT4
L1
GND
G2
VOUT3
H2
GND
J2
PGOOD4
K2
VOUT4
L2
GND
G3
GND
H3
VIN3
J3
CLKOUT
K3
GND
L3
VIN4
G4
GND
H4
VIN3
J4
INTVCC3
K4
GND
L4
VIN4
G5
GND
H5
SVIN3
J5
GND
K5
INTVCC4
L5
SVIN4
G6
TRACK/SS3
H6
MODE3
J6
RUN3
K6
TRACK/SS4
L6
MODE4
G7
FB3
H7
COMP3
J7
FB4
K7
RUN4
L7
COMP4
28
Rev D
For more information www.analog.com
0.630 ±0.025 Ø 77x
SUGGESTED PCB LAYOUT
TOP VIEW
2.540
PACKAGE TOP VIEW
1.270
4
0.3175
0.000
0.3175
PIN “A1”
CORNER
E
1.270
aaa Z
2.540
Y
For more information www.analog.com
6.350
5.080
3.810
2.540
1.270
0.000
1.270
2.540
3.810
5.080
6.350
D
X
aaa Z
// bbb Z
SYMBOL
A
b
D
E
e
F
G
H1
H2
aaa
bbb
eee
NOM
1.82
0.63
15.00
9.00
1.27
12.70
7.62
0.32
1.50
DIMENSIONS
0.37
1.55
0.15
0.10
0.15
MAX
1.92
0.66
NOTES
DETAIL B
TOTAL NUMBER OF LGA PADS: 77
0.27
1.45
MIN
1.72
0.60
H1
SUBSTRATE
Ø eee S Z X Y
Z
DETAIL A
0.630 ±0.025 Ø 77x
DETAIL B
H2
MOLD
CAP
A
(Reference LTC DWG# 05-08-1508 Rev Ø)
LGA Package
77-Lead (15.00mm × 9.00mm × 1.82mm)
F
e
7
5
4
3
2
PACKAGE BOTTOM VIEW
6
1
DETAIL A
3.810
3.810
L
K
J
H
G
F
E
D
C
B
A
PIN 1
DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
4
TRAY PIN 1
BEVEL
COMPONENT
PIN “A1”
7
!
LGA 77 0715 REV Ø
PACKAGE IN TRAY LOADING ORIENTATION
LTMXXXXXX
µModule
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
6. PAD FINISH: Au
5. PRIMARY DATUM -Z- IS SEATING PLANE
LAND DESIGNATION PER JESD MO-222, SPP-010
3
2. ALL DIMENSIONS ARE IN MILLIMETERS
7
SEE NOTES
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
b
3
SEE NOTES
G
LTM4643
PACKAGE DESCRIPTION
LGA Package
77-Lead (15.00mm × 9.00mm ×1.82mm)
(Reference LTC DWG # 05-08-1508 Rev Ø)
Rev D
29
0.630 ±0.025 Ø 77x
SUGGESTED PCB LAYOUT
TOP VIEW
2.540
PACKAGE TOP VIEW
1.270
4
0.3175
0.000
0.3175
PIN “A1”
CORNER
E
1.270
aaa Z
2.540
Y
For more information www.analog.com
6.350
5.080
3.810
2.540
1.270
0.000
1.270
2.540
3.810
5.080
6.350
D
X
aaa Z
SYMBOL
A
A1
A2
b
b1
D
E
e
F
G
H1
H2
aaa
bbb
ccc
ddd
eee
H1
SUBSTRATE
A1
NOM
2.42
0.60
1.82
0.75
0.63
15.00
9.00
1.27
12.70
7.62
0.32
1.50
MAX
2.62
0.70
1.92
0.90
0.66
NOTES
DETAIL B
PACKAGE SIDE VIEW
0.37
1.55
0.15
0.10
0.20
0.30
0.15
TOTAL NUMBER OF BALLS: 77
0.27
1.45
MIN
2.22
0.50
1.72
0.60
0.60
b1
DIMENSIONS
ddd M Z X Y
eee M Z
DETAIL A
Øb (77 PLACES)
DETAIL B
H2
MOLD
CAP
ccc Z
A2
A
Z
(Reference LTC DWG# 05-08-1559 Rev Ø)
// bbb Z
30
Z
BGA Package
77-Lead (15.00mm × 9.00mm × 2.42mm)
F
e
7
5
4
3
2
PACKAGE BOTTOM VIEW
6
1
DETAIL A
L
K
J
H
G
F
E
D
C
B
A
PIN 1
DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
4
TRAY PIN 1
BEVEL
COMPONENT
PIN “A1”
7
!
BGA 77 0916 REV Ø
PACKAGE IN TRAY LOADING ORIENTATION
LTMXXXXXX
µModule
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
6. SOLDER BALL COMPOSITION CAN BE 96.5% Sn/3.0% Ag/0.5% Cu
OR Sn Pb EUTECTIC
5. PRIMARY DATUM -Z- IS SEATING PLANE
BALL DESIGNATION PER JESD MS-028 AND JEP95
3
2. ALL DIMENSIONS ARE IN MILLIMETERS
7
SEE NOTES
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
b
3
SEE NOTES
G
LTM4643
PACKAGE DESCRIPTION
Rev D
3.810
3.810
LTM4643
REVISION HISTORY
REV
DATE
DESCRIPTION
A
03/17
Added the BGA package
PAGE NUMBER
B
6/17
Corrected Output Current from 4A to 3A on Figure 4
13
Corrected Output Voltage from 1.2V to 1.0V on Title of Figure 29
25
1, 2, 28, 30
C
5/18
Changed Storage Temperature Range: –65°C to 150°C
3
D
01/20
Added text to CLKOUT in Pin Functions
6
Rev D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
more by
information
www.analog.com
31
LTM4643
PACKAGE PHOTOS
DESIGN RESOURCES
SUBJECT
DESCRIPTION
µModule Design and Manufacturing Resources
Design:
• Selector Guides
• Demo Boards and Gerber Files
• Free Simulation Tools
Manufacturing:
• Quick Start Guide
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability
µModule Regulator Products Search
1. Sort table of products by parameters and download the result as a spread sheet.
2. Search using the Quick Power Search parametric table.
Digital Power System Management
Analog Devices’ family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.
RELATED PARTS
PART NUMBER
LTM4644
LTM4623
LTM4622
DESCRIPTION
Higher Power, Quad
Single, Ultrathin
Dual, Ultrathin
LTM4631
Higher Power, Dual, Ultrathin
32
COMMENTS
Quad 4A, Pin Compatible, 9mm × 15mm × 5.01mm BGA
3A, 6.25mm × 6.25mm × 1.8mm LGA and 6.25mm × 6.25mm × 2.42mm BGA
Dual 2.5A or Single 5A, , 6.25mm × 6.25mm × 1.8mm LGA and 6.25mm ×
6.25mm × 2.42mm BGA
Dual 10A or Single 20A, , 16mm × 16mm × 1.91mm LGA
Rev D
D16987-0-01/20
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For more information www.analog.com
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