LTM4650A
Dual 25A or Single 50A
DC/DC µModule Regulator
with 1% DC Accuracy
DESCRIPTION
FEATURES
Dual 25A or Single 50A Output
nn Input Voltage Range: 4.5V to 16V
nn Output Voltage Range: 0.6V to 5.5V
nn ±1% Maximum Total DC Output Error Over Line,
Load and Temperature
nn Higher Light Load Efficiency and Wider V
OUT Range
Than LTM4650-1
nn Differential Remote Sense Amplifier
nn Current Mode Control/Fast Transient Response
nn Multiphase Parallel Current Sharing Up to 300A
nn Internal Temperature Monitor
nn Pin Compatible with the LTM4620A (Dual 13A,
Single 26A) and LTM4630A (Dual 18A, Single 36A)
nn Adjustable Switching Frequency or Synchronization
nn Overcurrent Foldback Protection
nn Selectable Burst Mode® Operation, Pulse-Skipping
Mode Operation
nn Soft-Start/Voltage Tracking
nn Output Overvoltage Protection
nn 16mm × 16mm × 4.41mm LGA and
16mm × 16mm × 5.01mm BGA Packages
The LTM®4650A is a dual 25A or single 50A output switching
mode step-down DC/DC µModule® (micromodule) regulator with ±1% total DC output error. Included in the package
are the switching controllers, power FETs, inductors and
all supporting components. Operating from an input voltage range of 4.5V to 16V, the LTM4650A supports two
outputs with an output voltage range of 0.6V to 5.5V, each
set by a single external resistor. Its high efficiency design
delivers up to 25A continuous current for each output.
Fast internal control loop compensation allows for fast
transient response to minimize output capacitance when
powering FPGAs, ASICs, and processors.
nn
Fault protection features include overvoltage and overcurrent protection. The LTM4650A is offered in 16mm
× 16mm × 4.41mm LGA and16mm × 16mm × 5.01mm
BGA packages.
LTM4650 Product Family Selection Table
LTM4650
LTM4650-1B
LTM4650-1A
APPLICATIONS
LTM4650A
LTM4650A-1
Telecom and Networking Equipment
Storage and ATCA Cards
nn Industrial Equipment
VIN
RANGE
VOUT
RANGE
4.5V to
15V
0.6V to
1.8V
4.5V to
16V
0.6V to
5.5V
IOUT
COMPENDC VOUT
SATION ACCURACY
Internal
25A × 2
1.5%
External
0.8%
Internal
1%
External
nn
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. Patents, including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6304066
and 6580258. Other patents pending.
nn
TYPICAL APPLICATION
3.3VOUT Efficiency vs IOUT
50A, 3.3V Output DC/DC µModule Regulator
VIN
4.5V TO 16V
22µF
25V
×4
0.1µF
10k
4.7µF
VIN
INTVCC
PGOOD1
INTVCC
95
PGOOD2
VOUT1
VOUTS1
120k
TEMP
TRACK1
TRACK2
f SET
100
PGOOD
DIFFOUT
VFB1
LTM4650A
100µF
6.3V
VFB2
+
470µF
6.3V
VOUT
3.3V/50A
13.3k
COMP1
85
80
75
COMP2
PINS NOT USED IN
THIS CIRCUIT:
CLKOUT
EXTVCC
SW1
SW2
VOUTS2
90
EFFICIENCY (%)
INTVCC
VOUT2
RUN1
DIFFP
RUN2
PHASMD
DIFFN
SGND
GND
100µF
6.3V
+
70
470µF
6.3V
MODE_PLLIN
4650A TA01a
65
12VIN, 3.3VOUT, 600kHz
5VIN, 3.3VOUT, 600kHz
0
10
20
30
LOAD CURRENT (A)
40
50
4650A TA01b
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1
LTM4650A
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
DIFFP, DIFFN.......................................... –0.3V to INTVCC
COMP1, COMP2, VFB1, VFB2 (Note 6)......... –0.3V to 2.7V
INTVCC Peak Output Current...................................50mA
Internal Operating Temperature Range
(Note 2).............................................. –40°C to 125°C
Storage Temperature Range................... –55°C to 125°C
Peak Package Body Temperature........................... 245°C
VIN (Note 8)..................................................–0.3V to 18V
VSW1, VSW2.....................................................–1V to 18V
PGOOD1, PGOOD2, RUN1, RUN2,
INTVCC , EXTVCC........................................... –0.3V to 6V
MODE_PLLIN, fSET, TRACK1, TRACK2,
DIFFOUT, PHASMD................................ –0.3V to INTVCC
VOUT1, VOUT2, VOUTS1, VOUTS2 (Note 6)......... –0.3V to 6V
TOP VIEW
TOP VIEW
TEMP
TEMP
EXTVCC
L
L
VIN
K
K
J
J
CLKOUT
SW1
PHASMD
MODE_PLLIN
TRACK1
VFB1
VOUTS1
EXTVCC
M
M
INTVCC
SW2
PGOOD1
PGOOD2
RUN2
DIFFOUT
DIFFP
DIFFN
H
G
RUN1
SGND
F
GND
COMP1 COMP2
E
SGND VFB2 TRACK2
D
GND
CLKOUT
SW1
PHASMD
MODE_PLLIN
TRACK1
VFB1
fSET SGND VOUTS2
C
VOUTS1
B
VOUT1
G
RUN1
SGND
F
GND
COMP1 COMP2
E
SGND VFB2 TRACK2
D
GND
fSET SGND VOUTS2
C
B
VOUT2
GND
INTVCC
SW2
PGOOD1
PGOOD2
RUN2
DIFFOUT
DIFFP
DIFFN
H
VOUT2
GND
A
A
1
2
3
4
5
6
7
8
9
10
11
1
12
2
TJMAX = 125°C, θJA = 7°C/W, θJCbottom = 1.5°C/W, θJCtop = 3.7°C/W, θJB + θJBA ≅ 7°C/W
θ VALUES DEFINED PER JESD51-12
WEIGHT = 3.6g
ORDER INFORMATION
3
4
5
6
7
8
9
10
11
12
BGA PACKAGE
144-LEAD (16mm × 16mm × 5.01mm)
LGA PACKAGE
144-LEAD (16mm × 16mm × 4.41mm)
TJMAX = 125°C, θJA = 7°C/W, θJCbottom = 1.5°C/W, θJCtop = 3.7°C/W, θJB + θJBA ≅ 7°C/W
θ VALUES DEFINED PER JESD51-12
WEIGHT = 3.8g
http://www.linear.com/product/LTM4650A#orderinfo
PART MARKING*
DEVICE
FINISH CODE
PACKAGE
TYPE
MSL
RATING
TOTAL DC
ACCURACY
TEMPERATURE
RANGE (Note 2)
Au (RoHS)
LTM4650AV
e4
LGA
3
±1%
–40°C to 125°C
PART NUMBER
PAD OR BALL FINISH
LTM4650AEV#PBF
LTM4650AIV#PBF
Au (RoHS)
LTM4650AV
e4
LGA
3
±1%
–40°C to 125°C
LTM4650AEY#PBF
SAC305 (RoHS)
LTM4650AY
e1
BGA
3
±1%
–40°C to 125°C
LTM4650AIY#PBF
SAC305 (RoHS)
LTM4650AY
e1
BGA
3
±1%
–40°C to 125°C
LTM4650AIY
SnPb (63/37)
LTM4650AY
e0
BGA
3
±1%
–40°C to 125°C
Consult ADI Marketing for parts specified with wider operating temperature
ranges. *Device temperature grade is indicated by a label on the shipping
container. Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures:
www.linear.com/umodule/pcbassembly
• Terminal Finish Part Marking:
www.linear.com/leadfree
• LGA and BGA Package and Tray Drawings:
www.linear.com/packaging
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LTM4650A
ELECTRICAL
CHARACTERISTICS
The
l denotes the specifications which apply over the specified internal
operating temperature range. Specified as each individual output channel. TA = 25°C (Note 2), VIN = 12V and VRUN1, VRUN2 at 5V
unless otherwise noted. Per the typical application in Figure 34.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
VIN
Input DC Voltage
l
VOUT
Output Voltage
l
0.6
5.5
V
VOUT1(DC),
VOUT2(DC)
Output Voltage, Total DC Variation
with Line and Load (Note 8)
CIN = 22µF × 3, COUT = 100µF × 1 Ceramic,
470µF POSCAP
VIN = 4.5V to 16V,
VOUT = 1.2V, IOUT = 0A to 25A
l
1.188
1.2
1.212
V
RUN Pin On/Off Threshold
RUN Rising
1.1
1.25
1.40
V
4.5
MAX
16
UNITS
V
Input Specifications
VRUN1, VRUN2
VRUN1HYS , VRUN2HYS RUN Pin On Hysteresis
150
mV
IINRUSH(VIN)
Input Inrush Current at Start-Up
IOUT = 0A, CIN = 22µF ×3, CSS = 0.01µF,
COUT = 100µF ×3, VOUT1 = 1.2V, VOUT2 = 1.2V,
VIN = 12V
1
IQ(VIN)
Input Supply Bias Current
VIN = 12V, VOUT = 1.2V, Burst Mode Operation
VIN = 12V, VOUT = 1.2V, Pulse-Skipping Mode
VIN = 12V, VOUT= 1.2V, Switching Continuous
Shutdown, RUN = 0, VIN = 12V
4.5
19
115
35
mA
mA
mA
µA
VIN = 5V, VOUT = 1.2V, IOUT = 25A
VIN = 12V, VOUT = 1.2V, IOUT = 25A
8.2
3.1
A
A
(Both Channels On)
IS(VIN)
Input Supply Current
A
Output Specifications
IOUT1(DC), IOUT2(DC)
Output Continuous Current Range
VIN = 12V, VOUT = 1.2V (Note 7)
25
A
ΔVOUT1(LINE)/VOUT1
ΔVOUT2(LINE)/VOUT2
Line Regulation Accuracy
For Each Output, VOUT = 1.2V, IOUT = 0A,
VIN from 4.5V to 16V
l
0
0.02
0.1
%/V
ΔVOUT1/VOUT1
ΔVOUT2/VOUT2
Load Regulation Accuracy
For Each Output, VIN = 12V, VOUT = 1.2V,
IOUT from 0A to 25A (Note 7)
l
0.1
0.4
%
VOUT1(AC), VOUT2(AC) Output Ripple Voltage
For Each Output, VIN = 12V, VOUT = 1.2V,
Frequency = 450kHz, IOUT = 0A, COUT =
100µF ×3 Ceramic, 470µF POSCAP
15
mVP-P
fS (Each Channel)
Output Ripple Voltage Frequency
VIN = 12V, VOUT = 1.2V, fSET = 1.25V (Note 4)
500
kHz
fSYNC
(Each Channel)
SYNC Capture Range
∆VOUTSTART
(Each Channel)
Turn-On Overshoot
COUT = 100µF ×3 Ceramic, 470µF POSCAP,
VIN = 12V , VOUT = 1.2V, IOUT = 0A
10
mV
tSTART
(Each Channel)
Turn-On Time
COUT = 100µF ×3 Ceramic, 470µF POSCAP,
VIN = 12V, No Load, TRACK/SS with 0.01µF
to GND
5
ms
∆VOUT(LS)
(Each Channel)
Peak Deviation for Dynamic Load
Load: 0% to 50% to 0% of Full Load
COUT = 100µF ×3 Ceramic, 470µF POSCAP,
VIN = 12V, VOUT = 1.2V
30
mV
tSETTLE
(Each Channel)
Settling Time for Dynamic Load
Step
Load: 0% to 50% to 0% of Full Load,
VIN = 12V, COUT = 100µF ×3 Ceramic,
470µF POSCAP
20
µs
IOUT(PK)
(Each Channel)
Output Current Limit
VIN = 12V, VOUT = 1.2V
30
A
Voltage at VFB Pins
IOUT = 0A, VOUT = 1.2V
250
780
kHz
Control Section
VFB1, VFB2
0.595
(Note 6)
IFB
VOVL
l
Feedback Overvoltage Lockout
l
0.64
0.600
0.605
V
–5
–20
nA
0.66
0.68
V
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3
LTM4650A
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified internal
operating temperature range. Specified as each individual output channel. TA = 25°C (Note 2), VIN = 12V and VRUN1, VRUN2 at 5V
unless otherwise noted. Per the typical application in Figure 34.
SYMBOL
PARAMETER
CONDITIONS
ITRACK1,
ITRACK2
Track Pin Soft-Start Pull-Up Current
TRACK1,TRACK2 Start at 0V
UVLO
Undervoltage Lockout (Falling)
MIN
TYP
MAX
1
1.25
1.5
UVLO Hysteresis
tON(MIN)
Minimum On-Time
(Note 6)
RFBHI1, RFBHI2
Resistor Between VOUTS1, VOUTS2
and VFB1, VFB2 Pins for Each Output
VPGOOD1, VPGOOD2
Low
PGOOD Voltage Low
IPGOOD = 2mA
IPGOOD
PGOOD Leakage Current
VPGOOD = 5V
VPGOOD
PGOOD Trip Level
VFB with Respect to Set Output Voltage
VFB Ramping Negative
VFB Ramping Positive
60.05
UNITS
µA
3.3
V
0.6
V
90
ns
60.4
60.75
0.1
0.3
V
±5
µA
–10
10
kΩ
%
%
INTVCC Linear Regulator
VINTVCC
Internal VCC Voltage
6V < VIN < 16V
VINTVCC
Load Regulation
INTVCC Load Regulation
ICC = 0mA to 50mA
VEXTVCC
EXTVCC Switchover Voltage
EXTVCC Ramping Positive
VEXTVCC(DROP)
EXTVCC Dropout
ICC = 20mA, VEXTVCC = 5V
VEXTVCC(HYST)
EXTVCC Hysteresis
4.8
4.5
5
5.2
V
0.5
2
%
4.7
50
V
100
220
mV
mV
Oscillator and Phase-Locked Loop
Frequency Nominal
Nominal Frequency
fSET = 1.2V
450
Frequency Low
Lowest Frequency
fSET = 0V (Note 5)
210
250
290
kHz
Frequency High
Highest Frequency
fSET > 2.4V, Up to INTVCC
700
780
860
kHz
fSET
Frequency Set Current
10
11
RMODE_PLLIN
MODE_PLLIN Input Resistance
CLKOUT
Phase (Relative to VOUT1)
CLK High
CLK Low
Clock High Output Voltage
Clock Low Output Voltage
9
PHASMD = GND
PHASMD = Float
PHASMD = INTVCC
500
550
kHz
µA
250
kΩ
60
90
120
Deg
Deg
Deg
2
0.2
V
V
Differential Amplifier
AV Differential
Amplifier
Gain
RIN
Input Resistance
Measured at DIFFP Input
VOS
Input Offset Voltage
VDIFFP = VDIFFOUT = 1.2V, IDIFFOUT = 100µA
PSRR Differential
Amplifier
Power Supply Rejection Ratio
4.5V < VIN < 16V
ICL
Maximum Output Current
VOUT(MAX)
Maximum Output Voltage
GBW
Gain Bandwidth Product
VTEMP
Diode Connected PNP
TC
Temperature Coefficient
1
V/V
80
kΩ
3
IDIFFOUT = 300µA
90
dB
3
mA
INTVCC – 1.4
V
3
I = 100µA
l
mV
MHz
0.6
V
–2.2
mV/C
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LTM4650A
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTM4650A is tested under pulsed load conditions such that
TJ ≈ TA. The LTM4650AE is guaranteed to meet specifications from
0°C to 125°C internal temperature. Specifications over the –40°C to
125°C internal operating temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTM4650AI is guaranteed over the full –40°C to 125°C internal operating
temperature range. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
impedance and other environmental factors.
Note 3: Two outputs are tested separately and the same testing condition
is applied to each output.
Note 4: The switching frequency is programmable from 250kHz to 780kHz.
Note 5: LTM4650A device is designed to operate from 250kHz to 780kHz
Note 6: These parameters are tested at wafer sort.
Note 7: See output current derating curve for different ambient
temperature.
Note 8: Total DC output voltage error includes all errors over
temperature – reference, line and load regulation as well as the tolerance
of the integrated top feedback resistor.
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5
LTM4650A
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Output Current,
VIN = 12V
100
95
95
90
90
85
80
1.0VOUT, 300kHz
1.2VOUT, 400kHz
1.5VOUT, 400kHz
1.8VOUT, 500kHz
2.5VOUT, 500kHz
3.3VOUT, 600kHz
75
70
65
0
5
10
15
LOAD CURRENT (A)
20
80
85
80
1.0VOUT, 300kHz
1.2VOUT, 400kHz
1.5VOUT, 400kHz
1.8VOUT, 500kHz
2.5VOUT, 500kHz
3.3VOUT, 600kHz
5.0VOUT, 750kHz
70
65
0
5
10
15
LOAD CURRENT (A)
4650A G01
20
70
60
50
40
30
20
10
25
0
0.01
Burst Mode OPERATION
PULSE-SKIP MODE
CCM
0.1
1
LOAD CURRENT (mA)
10
4650A G03
4650A G02
1V Dual Phase Single Output
Load Transient Response
(Ceramic Cap)
1.2V Dual Phase Single Output
Load Transient Response
(Ceramic Cap)
1.5V Dual Phase Single Output
Load Transient Response
(Ceramic Cap)
VOUT (AC)
50mV/DIV
VOUT (AC)
50mV/DIV
VOUT (AC)
50mV/DIV
LOAD STEP
10A/DIV
LOAD STEP
10A/DIV
LOAD STEP
10A/DIV
50µs/DIV
Burst Mode and Pulse-Skip Mode
Efficiency VIN=12V, VOUT = 1.2V,
fS = 300kHz
90
75
25
100
EFFICIENCY (%)
100
EFFICIENCY (%)
EFFICIENCY (%)
Efficiency vs Output Current,
VIN = 5V
50µs/DIV
4650A G04
50µs/DIV
4650A G05
4650A G06
12VIN, 1VOUT, 300kHz,
DUAL PHASE SINGLE OUTPUT
25%, 12.5A LOAD STEP-UP AND
STEP-DOWN, 10A/μs SLEW RATE
COUT = 16× 100μF CERAMIC CAP
CFF = 47pF
12VIN, 1.2VOUT, 400kHz,
DUAL PHASE SINGLE OUTPUT
25%, 12.5A LOAD STEP-UP AND
STEP-DOWN, 10A/μs SLEW RATE
COUT = 16× 100μF CERAMIC CAP
CFF = 47pF
12VIN, 1.5VOUT, 400kHz,
DUAL PHASE SINGLE OUTPUT
25%, 12.5A LOAD STEP-UP AND
STEP-DOWN, 10A/μs SLEW RATE
COUT = 16× 100μF CERAMIC CAP
CFF = 47pF
1.8V Dual Phase Single Output
Load Transient Response
(Ceramic Cap)
2.5V Dual Phase Single Output
Load Transient Response
(Ceramic Cap)
3.3V Dual Phase Single Output
Load Transient Response
(Ceramic Cap)
VOUT (AC)
50mV/DIV
VOUT (AC)
50mV/DIV
VOUT (AC)
100mV/DIV
LOAD STEP
10A/DIV
LOAD STEP
10A/DIV
LOAD STEP
10A/DIV
50µs/DIV
12VIN, 1.8VOUT, 500kHz,
DUAL PHASE SINGLE OUTPUT
25%, 12.5A LOAD STEP-UP AND
STEP-DOWN, 10A/μs SLEW RATE
COUT = 16× 100μF CERAMIC CAP
CFF = 47pF
4650A G07
50µs/DIV
4650A G08
12VIN, 2.5VOUT, 500kHz,
DUAL PHASE SINGLE OUTPUT
25%, 12.5A LOAD STEP-UP AND
STEP-DOWN, 10A/μs SLEW RATE
COUT = 16× 100μF CERAMIC CAP
CFF = 47pF
50µs/DIV
4650A G09
12VIN, 3.3VOUT, 600kHz,
DUAL PHASE SINGLE OUTPUT
25%, 12.5A LOAD STEP-UP AND
STEP-DOWN, 10A/μs SLEW RATE
COUT = 16× 100μF CERAMIC CAP
CFF = 47pF
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LTM4650A
TYPICAL PERFORMANCE CHARACTERISTICS
1V Dual Phase Single Output
Load Transient Response
(POSCAP)
5V Dual Phase Single Output
Load Transient Response
(Ceramic Cap)
1.2V Dual Phase Single Output
Load Transient Response
(POSCAP)
VOUT (AC)
100mV/DIV
VOUT (AC)
50mV/DIV
VOUT (AC)
50mV/DIV
LOAD STEP
10A/DIV
LOAD STEP
10A/DIV
LOAD STEP
10A/DIV
50µs/DIV
50µs/DIV
4650A G10
50µs/DIV
4650A G11
4650A G12
12VIN, 5VOUT, 750kHz,
DUAL PHASE SINGLE OUTPUT
25%, 12.5A LOAD STEP-UP AND
STEP-DOWN, 10A/μs SLEW RATE
COUT = 16× 100μF CERAMIC CAP
CFF = 47pF
12VIN, 1VOUT, 300kHz,
DUAL PHASE SINGLE OUTPUT
25%, 12.5A LOAD STEP-UP AND
STEP-DOWN, 10A/μs SLEW RATE
COUT = 4× 470μF POSCAP + 8× 100µF CERAMIC
NO CFF
12VIN, 1.2VOUT, 400kHz,
DUAL PHASE SINGLE OUTPUT
25%, 12.5A LOAD STEP-UP AND
STEP-DOWN, 10A/μs SLEW RATE
COUT = 4× 470μF POSCAP + 8× 100µF CERAMIC
NO CFF
1.5V Dual Phase Single Output
Load Transient Response
(POSCAP)
1.8V Dual Phase Single Output
Load Transient Response
(POSCAP)
2.5V Dual Phase Single Output
Load Transient Response
(POSCAP)
VOUT (AC)
50mV/DIV
VOUT (AC)
50mV/DIV
VOUT (AC)
50mV/DIV
LOAD STEP
10A/DIV
LOAD STEP
10A/DIV
LOAD STEP
10A/DIV
50µs/DIV
50µs/DIV
4650A G13
12VIN, 1.5VOUT, 400kHz,
DUAL PHASE SINGLE OUTPUT
25%, 12.5A LOAD STEP-UP AND
STEP-DOWN, 10A/μs SLEW RATE
COUT = 4× 470μF POSCAP + 8× 100µF CERAMIC
NO CFF
12VIN, 1.8VOUT, 500kHz,
DUAL PHASE SINGLE OUTPUT
25%, 12.5A LOAD STEP-UP AND
STEP-DOWN, 10A/μs SLEW RATE
COUT = 4× 470μF POSCAP + 8× 100µF CERAMIC
NO CFF
3.3V Dual Phase Single Output
Load Transient Response
(POSCAP)
VOUT (AC)
100mV/DIV
LOAD STEP
10A/DIV
LOAD STEP
10A/DIV
12VIN, 2.5VOUT, 500kHz,
DUAL PHASE SINGLE OUTPUT
25%, 12.5A LOAD STEP-UP AND
STEP-DOWN, 10A/μs SLEW RATE
COUT = 4× 470μF POSCAP + 8× 100µF CERAMIC
NO CFF
50µs/DIV
4650A G16
12VIN, 3.3VOUT, 600kHz,
DUAL PHASE SINGLE OUTPUT
25%, 12.5A LOAD STEP-UP AND
STEP-DOWN, 10A/μs SLEW RATE
COUT = 4× 470μF POSCAP + 8× 100µF CERAMIC
NO CFF
4650A G15
5V Dual Phase Single Output
Load Transient Response
(POSCAP)
VOUT (AC)
100mV/DIV
50µs/DIV
50µs/DIV
4650A G14
4650A G17
12VIN, 5VOUT, 750kHz,
DUAL PHASE SINGLE OUTPUT
25%, 12.5A LOAD STEP-UP AND
STEP-DOWN, 10A/μs SLEW RATE
COUT = 4× 470μF POSCAP + 8× 100µF CERAMIC
NO CFF
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7
LTM4650A
TYPICAL PERFORMANCE CHARACTERISTICS
Single Phase Start-Up with No load
Single Phase Start-Up with 25A Load
SW
10V/DIV
SW
10V/DIV
VOUT
0.5V/DIV
INPUT
CURRENT
0.2A/DIV
VOUT
0.5V/DIV
20ms/DIV
4650A G18
INPUT
CURRENT
2A/DIV
20ms/DIV
12VIN, 1.2VOUT, 400kHz
COUT = 2× 470μF
SPCAP + 4× 100µF CERAMIC CAP
CSS = 0.1µF
12VIN, 1.2VOUT, 400kHz
COUT = 2× 470μF
SPCAP + 4× 100µF CERAMIC CAP
CSS = 0.1µF
Single Phase Short-Circuit
Protection with No load
Single Phase Short-Circuit
Protection with 25A Load
SW
10V/DIV
SW
10V/DIV
VOUT
0.5V/DIV
VOUT
0.5V/DIV
INPUT
CURRENT
5A/DIV
INPUT
CURRENT
2A/DIV
100μs/DIV
12VIN, 1.2VOUT, 400kHz
COUT = 2× 470μF
SPCAP + 4× 100µF CERAMIC CAP
4650A G20
100μs/DIV
4650A G19
4650A G21
12VIN, 1.2VOUT, 400kHz
COUT = 2× 470μF
SPCAP + 4× 100µF CERAMIC CAP
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LTM4650A
PIN FUNCTIONS
(Recommended to Use Test Points to Monitor Signal Pin Connections.)
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
VOUT1 (A1–A5, B1–B5, C1–C4): Power Output Pins. Apply
output load between these pins and GND pins. Recommend
placing output decoupling capacitance directly between
these pins and GND pins. Review Table 6.
GND (A6–A7, B6–B7, D1–D4, D9–D12, E1–E4, E10–E12,
F1–F3, F10–F12, G1, G3, G10, G12, H1–H7, H9–H12,
J1, J5, J8, J12, K1, K5–K8, K12, L1, L12, M1 , M12):
Power Ground Pins for Both Input and Output Returns.
VOUT2 (A8–A12, B8–B12, C9–C12): Power Output Pins.
Apply output load between these pins and GND pins. Recommend placing output decoupling capacitance directly
between these pins and GND pins. Review Table 6.
VOUTS1, VOUTS2 (C5, C8): This pin is connected to the top
of the internal top feedback resistor for each output. The
pin can be directly connected to its specific output, or
connected to DIFFOUT when the remote sense amplifier
is used. In paralleling modules, one of the VOUTS pins is
connected to the DIFFOUT pin in remote sensing or directly
to VOUT with no remote sensing. It is very important to
connect these pins to either the DIFFOUT or VOUT since
this is the feedback path, and cannot be left open. See the
Applications Information section.
fSET (C6): Frequency Set Pin. A 10µA current is sourced
from this pin. A resistor from this pin to ground sets a
voltage that in turn programs the operating frequency.
Alternatively, this pin can be driven with a DC voltage
that can set the operating frequency. See the Applications
Information section.
SGND (C7, D6, G6–G7, F6–F7): Signal Ground Pin. Return
ground path for all analog and low power circuitry. Tie a
single connection to the output capacitor GND in the application. See layout guidelines in Figure 13.
VFB1, VFB2 (D5, D7): The Negative Input of the Error Amplifier for Each Channel. Internally, this pin is connected
to VOUTS1 or VOUTS2 with a 60.4kΩ precision resistor.
Different output voltages can be programmed with an additional resistor between VFB and GND pins. In PolyPhase®
operation, tying the VFB pins together allows for parallel
operation. See the Applications Information section for
details. Do not drive this pin.
TRACK1, TRACK2 (E5, D8): Output Voltage Tracking Pin
and Soft-Start Inputs. Each channel has a 1.3µA pull-up
current source. When one channel is configured to be
master of the two channels, then a capacitor from this pin
to ground will set a soft-start ramp rate. The remaining
channel can be set up as the slave, and have the master’s
output applied through a voltage divider to the slave output’s track pin. This voltage divider is equal to the slave
output’s feedback divider for coincidental tracking. See
the Applications Information section.
COMP1, COMP2 (E6, E7): Current control threshold and
error amplifier compensation point for each channel. The
current comparator threshold increases with this control
voltage. This device is internal compensated. See Applications Information section. Tie the COMP pins together for
parallel operation. Do not drive this pin.
DIFFP (E8): Positive input of the remote sense amplifier.
This pin is connected to the remote sense point of the
output voltage. Diffamp can be used for ≤3.3V outputs.
See the Applications Information section.
DIFFN (E9): Negative input of the remote sense amplifier.
This pin is connected to the remote sense point of the
output GND. Diffamp can be used for ≤3.3V outputs. See
the Applications Information section.
MODE_PLLIN (F4): Force Continuous Mode, Burst Mode
Operation, or Pulse-Skipping Mode Selection Pin and
External Synchronization Input to Phase Detector Pin.
Connect this pin to SGND to force both channels into
force continuous mode of operation. Connect to INTVCC
to enable pulse-skipping mode of operation. Leaving the
pin floating will enable Burst Mode operation. A clock on
the pin will force both channels into continuous mode of
operation and synchronized to the external clock applied
to this pin.
RUN1, RUN2 (F5, F9): Run Control Pin. A voltage above
1.25V will turn on each channel in the module. A voltage
below 1.25V on the RUN pin will turn off the related channel. Each RUN pin has a 1µA pull-up current, once the
RUN pin reaches 1.2V an additional 4.5µA pull-up current
is added to this pin.
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9
LTM4650A
PIN FUNCTIONS
(Recommended to Use Test Points to Monitor Signal Pin Connections.)
DIFFOUT (F8): Internal Remote Sense Amplifier Output.
Connect this pin to VOUTS1 or VOUTS2 depending on which
output is using remote sense. In parallel operation connect one of the VOUTS pin to DIFFOUT for remote sensing.
SW1, SW2 (G2, G11): Switching node of each channel
that is used for testing purposes. Also an R-C snubber
network can be applied to reduce or eliminate switch node
ringing, or otherwise leave floating. See the Applications
Information section.
PHASMD (G4): Connect this pin to SGND, INTVCC, or floating this pin to select the phase of CLKOUT to 60 degrees,
120 degrees, and 90 degrees respectively.
CLKOUT (G5): Clock output with phase control using the
PHASMD pin to enable multiphase operation between
devices. See the Applications Information section.
PGOOD1, PGOOD2 (G9, G8): Output Voltage Power
Good Indicator. Open drain logic output that is pulled to
ground when the output voltage is not within ±10% of
the regulation point.
TEMP (J6): Temperature Monitor. An internal diode connected NPN transistor connected between TEMP and SGND
pins. See the Applications Information section.
EXTVCC (J7): External power input that is enabled through
a switch to INTVCC whenever EXTVCC is greater than 4.7V.
Do not exceed 6V on this input, and connect this pin to
VIN when operating VIN on 5V. An efficiency increase will
occur that is a function of the (VIN – INTVCC) multiplied by
power MOSFET driver current. Typical current requirement
is 30mA. VIN must be applied before EXTVCC , and EXTVCC
must be removed before VIN.
VIN (M2–M11, L2–L11, J2–J4, J9–J11, K2–K4, K9–K11):
Power Input Pins. Apply input voltage between these pins
and GND pins. Recommend placing input decoupling
capacitance directly between VIN pins and GND pins.
Heat Sink (Top Exposed Metal): The top exposed metal
is electrically unconnected.
INTVCC (H8): Internal 5V Regulator Output. The control
circuits and internal gate drivers are powered from this
voltage. Decouple this pin to PGND with a 4.7µF low ESR
tantalum or ceramic. INTVCC is activated when either RUN1
or RUN2 is activated.
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LTM4650A
SIMPLIFIED BLOCK DIAGRAM
PGOOD1
TRACK1
SS CAP
VIN
= 100µA VIN
RT
OR TEMP
MONITORS
RT
VIN
4.5V TO 16V
VIN
CIN1
22µF
25V
0.1µF
GND
TEMP
MTOP1
SW1
CLKOUT
0.22µH
RUN1
MODE_PLLIN
VOUT1
1.5V
25A
VOUT1
0.22µF
MBOT1
PHASEMD
CIN2
22µF
25V
+
GND
COUT1
VOUTS1
COMP1
SGND
60.4k
VFB1
INTERNAL
COMP
RFB1
40.2k
POWER
CONTROL
PGOOD2
TRACK2
SS CAP
VIN
INTVCC
CIN3
22µF
25V
0.1µF
4.7µF
GND
EXTVCC
MTOP2
SW2
0.22µH
RUN2
CIN4
22µF
25V
VOUT2
0.22µF
MBOT2
GND
+
VOUT2
3.3V
25A
COUT2
VOUTS2
60.4k
COMP2
fSET
RFSET
SGND
+ –
VFB2
RFB2
13.3k
INTERNAL
COMP
INTERNAL
FILTER
DIFFOUT
DIFFN
DIFFP
4650A BD
Figure 1. Simplified LTM4650A Block Diagram
DECOUPLING REQUIREMENTS
TA = 25°C. Use Figure 1 configuration.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
CIN1, CIN2
CIN3, CIN4
External Input Capacitor Requirement
(VIN1 = 4.5V to 16V, VOUT1 = 1.2V)
(VIN2 = 4.5V to 16V, VOUT2 = 3.3V)
IOUT1 = 25A
IOUT2 = 25A
22
22
66
66
µF
µF
COUT1
COUT2
External Output Capacitor Requirement
(VIN1 = 4.5V to 16V, VOUT1 = 1.2V)
(VIN2 = 4.5V to 16V, VOUT2 = 3.3V)
IOUT1 = 25A
IOUT2 = 25A
300
300
600
600
µF
µF
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11
LTM4650A
OPERATION
Power Module Description
The LTM4650A is a dual-output standalone nonisolated
switching mode DC/DC power supply with ±1% total DC
output error over line, load and temperature variation. It
can provide two 25A outputs or single 50A output with
few external input and output capacitors and setup components. This module provides precisely regulated output
voltages programmable via external resistors from 0.6VDC
to 5.5VDC over 4.5V to 16V input voltages. The typical
application schematic is shown in Figure 32.
The LTM4650A has dual integrated constant-frequency
current mode regulators and built-in power MOSFET
devices with fast switching speed. The typical switching
frequency is 300kHz to 750kHz depending on different
input and output conditions. For switching-noise sensitive applications, it can be externally synchronized from
250kHz to 780kHz. A resistor can be used to program a
free run frequency on the fSET pin. See the Applications
Information section.
With current mode control, multi LTM4650As can be easily
paralleled to provide up to 300A current with guaranteed
perfect current sharing. Also, with current mode control,
the LTM4650A module is able to achieve sufficient stability
margins and a fast transient response with a minimum
number of output capacitors, even with all ceramic output
capacitors. See Applications Information section.
Current mode control provides cycle-by-cycle fast current
limit and foldback current limit in an overcurrent condition.
Internal overvoltage and undervoltage comparators pull
the open-drain PGOOD outputs low if the output feedback
voltage exits a ±10% window around the regulation point.
As the output voltage exceeds 10% above regulation, the
bottom MOSFET will turn on to clamp the output voltage.
The top MOSFET will be turned off. This overvoltage protect
is feedback voltage referred.
Pulling the RUN pins below 1.1V forces the regulators into
a shutdown state, by turning off both MOSFETs. The TRACK
pins are used for programming the output voltage ramp and
voltage tracking during start-up or used for soft-starting
the regulator. See the Applications Information section.
The LTM4650A is internally compensated to be stable over
all operating conditions. Table 6 provides a guideline for
input and output capacitances for several operating conditions. The LTpowerCAD™ will be provided for transient
and stability analysis. The VFB pin is used to program the
output voltage with a single external resistor to ground.
A differential remote sense amplifier is available for sensing the output voltage accurately on one of the outputs at
the load point, or in parallel operation sensing the output
voltage at the load point.
High efficiency at light loads can be accomplished with
selectable Burst Mode operation or pulse-skipping operation using the MODE_PLLIN pin. These light load features
will accommodate battery operation. Efficiency graphs are
provided for light load operation in the Typical Performance
Characteristics section. See the Applications Information
section for details.
A general purpose temperature diode is included inside
the module to monitor the temperature of the module. See
the Applications Information section for details.
The switch pins are available for functional operation
monitoring and a resistor-capacitor snubber circuit can
be careful placed on the switch pin to ground to dampen
any high frequency ringing on the transition edges. See
the Applications Information section for details.
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LTM4650A
APPLICATIONS INFORMATION
The typical LTM4650A application circuit is shown in
Figure 32. External component selection is primarily
determined by the maximum load current and output
voltage. Refer to Table 6 for specific external capacitor
requirements for particular application.
COMP2
VOUT2
VFB1
VFB2
Output Voltage Programming
The PWM controller has an internal 0.6V reference voltage.
As shown in the Block Diagram, a 60.4kΩ internal feedback
resistor connects between the VOUTS1 to VFB1 and VOUTS2
to VFB2. It is very important that these pins be connected
to their respective outputs for proper feedback regulation.
Overvoltage can occur if these VOUTS1 and VOUTS2 pins are
left floating when used as individual regulators, or at least
one of them is used in paralleled regulators. The output
voltage will default to 0.6V with no feedback resistor on
either VFB1 or VFB2. Adding a resistor RFB from VFB pin to
GND programs the output voltage:
60.4k + RFB
RFB
Table 1. VFB Resistor Table vs Various Output Voltages
VOUT
0.6V
1.0V
1.2V
1.5V
1.8V
2.5V
3.3V
5V
RFB
Open
90.9k
60.4k
40.2k
30.2k
19.1k
13.3k
8.25k
For parallel operation of multiple channels the same feedback setting resistor can be used for the parallel design.
This is done by connecting the VOUTS1 to the output as
shown in Figure 2, thus tying one of the internal 60.4k
COMP1 LTM4650A
VOUT1
COMP2
VOUT2
60.4k
VOUTS1
VOUTS2
VFB1
TRACK1
TRACK2
OPTIONAL CONNECTION
60.4k
TRACK2
0.1µF
4 PARALLELED OUTPUTS
FOR 1.2V AT 100A
VOUTS1
VOUTS2
TRACK1
There are restrictions in the maximum VIN and VOUT stepdown ratio that can be achieved for a given input voltage.
Each output of the LTM4650A is capable of 98% duty
cycle, but the VIN to VOUT minimum dropout is still shown
as a function of its load current and will limit output current capability related to high duty cycle on the top side
switch. Minimum on-time tON(MIN) is another consideration
in operating at a specified duty cycle while operating at
a certain frequency due to the fact that tON(MIN) < D/fSW,
where D is duty cycle and fSW is the switching frequency.
tON(MIN) is specified in the electrical parameters as 90ns.
VOUT1
60.4k
VIN to VOUT Step-Down Ratios
VOUT = 0.6V •
COMP1 LTM4650A
OPTIONAL
RFB
60.4k
USE TO LOWER
TOTAL EQUIVALENT
RESISTANCE TO LOWER
IFB VOLTAGE ERROR
60.4k
VFB2
4650A F02
RFB
60.4k
Figure 2. 4-Phase Parallel Configurations
resistors to the output. All of the VFB pins tie together with
one programming resistor as shown in Figure 2.
In parallel operation, the VFB pins have an IFB current of 20nA
maximum each channel. To reduce output voltage error due
to this current, an additional VOUTS pin can be tied to VOUT,
and an additional RFB resistor can be used to lower the total
Thevenin equivalent resistance seen by this current. For
example in Figure 2, the total Thevenin equivalent resistance
of the VFB pin is (60.4k//RFB), which is 30.2k where RFB is
equal to 60.4k for a 1.2V output. Four phases connected
in parallel equates to a worse case feedback current of
4 • IFB = 80nA maximum. The voltage error is 80nA • 30.2k
= 2.4mV. If VOUTS2 is connected, as shown in Figure 2, to
VOUT, and another 60.4k resistor is connected from VFB2 to
ground, then the voltage error is reduced to 1.2mV. If the
voltage error is acceptable then no additional connections
are necessary. The onboard 60.4k resistor is 0.5% accurate
and the VFB resistor can be chosen by the user to be as
accurate as needed. All COMP pins are tied together for
current sharing between the phases. The TRACK/SS pins
can be tied together and a single soft-start capacitor can
be used to soft-start the regulator. The soft-start equation
will need to have the soft-start current parameter increased
by the number of paralleled channels. See Output Voltage
Tracking section.
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13
LTM4650A
APPLICATIONS INFORMATION
Input Capacitors
The LTM4650A module should be connected to a low ACimpedance DC source. For the regulator input, two 22µF
input ceramic capacitors per channel are used for RMS
ripple current. A 47µF to 100µF surface mount aluminum
electrolytic bulk capacitor can be used for more input bulk
capacitance. This bulk input capacitor is only needed if
the input source impedance is compromised by long inductive leads, traces or not enough source capacitance.
If low impedance power planes are used, then this bulk
capacitor is not needed.
For a buck converter, the switching duty-cycle can be
estimated as:
V
D = OUT
VIN
Without considering the inductor current ripple, for each
output, the RMS current of the input capacitor can be
estimated as:
ICIN(RMS) =
IOUT(MAX)
η%
• D • ( 1− D )
In the above equation, η% is the estimated efficiency of
the power module. The bulk capacitor can be a switcherrated electrolytic aluminum capacitor, Polymer capacitor.
Output Capacitors
The LTM4650A is designed for low output voltage ripple
noise and good transient response. The bulk output
capacitors defined as COUT are chosen with low enough
effective series resistance (ESR) to meet the output voltage ripple and transient requirements. COUT can be a low
ESR tantalum capacitor, the low ESR polymer capacitor or
ceramic capacitor. The typical output capacitance range for
each output is from 300µF to 800µF per output channel.
Additional output filtering may be required by the system
designer, if further reduction of output ripples or dynamic
transient spikes is required. Table 6 shows a matrix of
different output voltages and output capacitors to minimize the voltage droop and overshoot during a 25% load
step. The table optimizes total equivalent ESR and total
bulk capacitance to optimize the transient performance.
Stability criteria are considered in the Table 6 matrix,
and the Analog Devices LTpowerCAD Design Tool will be
provided for stability analysis. Multiphase operation will
reduce effective output ripple as a function of the number of phases. Application Note 77 discusses this noise
reduction versus output ripple current cancellation, but
the output capacitance should be considered carefully as
a function of stability and transient response. The Analog
Devices µModule Power Design Tool can calculate the
output ripple reduction as the number of implemented
phases increases by N times. A small value 10Ω to 50Ω
resistor can be place in series from VOUT to the VOUTS pin
to allow for a bode plot analyzer to inject a signal into the
control loop and validate the regulator stability. The same
resistor could be place in series from VOUT to DIFFP and
a bode plot analyzer could inject a signal into the control
loop and validate the regulator stability.
Burst Mode Operation
The LTM4650A is capable of Burst Mode operation on
each regulator in which the power MOSFETs operate intermittently based on load demand, thus saving quiescent
current. For applications where maximizing the efficiency
at very light loads is a high priority, Burst Mode operation
should be applied. Burst Mode operation is enabled with
the MODE_PLLIN pin floating. During this operation, the
peak current of the inductor is set to approximately one
third of the maximum peak current value in normal operation even though the voltage at the COMP pin indicates
a lower value. The voltage at the COMP pin drops when
the inductor’s average current is greater than the load
requirement. As the COMP voltage drops below 0.5V, the
BURST comparator trips, causing the internal sleep line
to go high and turn off both power MOSFETs.
In sleep mode, the internal circuitry is partially turned off.
The load current is now being supplied from the output
capacitors. When the output voltage drops, causing COMP
to rise above 0.5V, the internal sleep line goes low, and
the LTM4650A resumes normal operation. The next oscillator cycle will turn on the top power MOSFET and the
switching cycle repeats.
Pulse-Skipping Mode Operation
In applications where low output ripple and high efficiency at intermediate currents are desired, pulse-skipping
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LTM4650A
APPLICATIONS INFORMATION
mode should be used. Pulse-skipping operation allows
the LTM4650A to skip cycles at low output loads, thus
increasing efficiency by reducing switching loss. Tying
the MODE_PLLIN pin to INTVCC enables pulse-skipping
operation. At light loads the internal current comparator
may remain tripped for several cycles and force the top
MOSFET to stay off for several cycles, thus skipping cycles.
The inductor current does not reverse in this mode. This
mode will maintain higher effective frequencies thus lower
output ripple and lower noise than Burst Mode operation.
voltage is in regulation. Either regulator can be configured
for force continuous mode.
Multiphase Operation
For output loads that demand more than 25A of current,
two outputs in LTM4650A or even multiple LTM4650As can
be paralleled to run out of phase to provide more output
current without increasing input and output voltage ripples.
The MODE_PLLIN pin allows the LTM4650A to synchronize
to an external clock (between 250kHz and 780kHz) and the
internal phase-locked-loop allows the LTM4650A to lock
onto incoming clock phase as well. The CLKOUT signal
can be connected to the MODE_PLLIN pin of the following
stage to line up both the frequency and the phase of the
entire system. Tying the PHASMD pin to INTVCC, SGND, or
(floating) generates a phase difference (between
MODE_PLLIN and CLKOUT) of 120 degrees, 60 degrees,
or 90 degrees respectively. A total of 12 phases can be
cascaded to run simultaneously with respect to each other
by programming the PHASMD pin of each LTM4650A channel to different levels. Figure 3 shows a 2-phase design,
4-phase design and a 6-phase design example for clock
phasing with the PHASMD table.
Forced Continuous Operation
In applications where fixed frequency operation is more
critical than low current efficiency, and where the lowest
output ripple is desired, forced continuous operation
should be used. Forced continuous operation can be
enabled by tying the MODE_PLLIN pin to GND. In this
mode, inductor current is allowed to reverse during low
output loads, the COMP voltage is in control of the current
comparator threshold throughout, and the top MOSFET
always turns on with each oscillator pulse. During start-up,
forced continuous mode is disabled and inductor current
is prevented from reversing until the LTM4650A’s output
2-PHASE DESIGN
PHASMD
FLOAT
CLKOUT
0 PHASE
MODE_PLLIN
VOUT1
VOUT2
SGND
FLOAT
INTVCC
CONTROLLER1
0
0
0
CONTROLLER2
180
180
240
CLKOUT
60
90
120
180 PHASE
PHASMD
4-PHASE DESIGN
90 DEGREE
CLKOUT
0 PHASE
FLOAT
CLKOUT
MODE_PLLIN
VOUT1
VOUT2
180 PHASE
90 PHASE
FLOAT
PHASMD
MODE_PLLIN
VOUT1
VOUT2
270 PHASE
PHASMD
6-PHASE DESIGN
60 DEGREE
60 DEGREE
CLKOUT
0 PHASE
SGND
CLKOUT
MODE_PLLIN
VOUT1
PHASMD
VOUT2
180 PHASE
60 PHASE
SGND
CLKOUT
MODE_PLLIN
VOUT1
VOUT2
240 PHASE
PHASMD
120 PHASE
FLOAT
MODE_PLLIN
VOUT1
VOUT2
300 PHASE
PHASMD
4650A F03
Figure 3. Examples of 2-Phase, 4-Phase, and 6-Phase Operation with PHASMD Table
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15
LTM4650A
APPLICATIONS INFORMATION
A multiphase power supply significantly reduces the
amount of ripple current in both the input and output capacitors. The RMS input ripple current is reduced by, and
the effective ripple frequency is multiplied by, the number
of phases used (assuming that the input voltage is greater
than the number of phases used times the output voltage).
The output ripple amplitude is also reduced by the number
of phases used when all of the outputs are tied together
to achieve a single high output current design.
The LTM4650A device is an inherently current mode controlled device, so parallel modules will have very good current sharing. This will balance the thermals on the design.
Connect the COMP pins, FB pins, TRACK/SS pin and VOUT
pins from different modules together. See Figure 33 and
35 for examples of parallel operation.
Input RMS Ripple Current Cancellation
Application Note 77 provides a detailed explanation of
multiphase operation. The input RMS ripple current cancellation mathematical derivations are presented, and a
graph is displayed representing the RMS ripple current
reduction as a function of the number of interleaved phases.
Figure 4 shows this graph.
0.60
1-PHASE
2-PHASE
3-PHASE
4-PHASE
6-PHASE
0.55
0.50
RMS INPUT RIPPLE CURRENT
DC LOAD CURRENT
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0.1 0.15
0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
DUTY FACTOR (VOUT/VIN)
4650A F04
Figure 4. Input RMS Current Ratios to DC Load Current as a Function of Duty Cycle
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LTM4650A
APPLICATIONS INFORMATION
Frequency Selection and Phase-Lock Loop
(MODE_PLLIN and fSET Pins)
The LTM4650A device is operated over a range of frequencies to improve power conversion efficiency. It is recommended to operate the module at 300kHz to 750kHz over
different input and output range for the best efficiency and
inductor current ripple.
The LTM4650A switching frequency can be set with an
external resistor from the fSET pin to SGND. An accurate
10µA current source into the resistor will set a voltage
that programs the frequency or a DC voltage can be
applied. Figure 5 shows a graph of frequency setting
verses programming voltage. An external clock can be
applied to the MODE_PLLIN pin from 0V to INTVCC over
a frequency range of 250kHz to 780kHz. The clock input
high threshold is 1.6V and the clock input low threshold
is 1V. The LTM4650A has the PLL loop filter components
on board. The frequency setting resistor should always
be present to set the initial switching frequency before
locking to an external clock. Both regulators will operate
in continuous mode while being externally clock.
900
800
FREQUENCY (kHz)
700
600
Minimum On-Time
Minimum on-time tON is the smallest time duration that
the LTM4650A is capable of turning on the top MOSFET on
either channel. It is determined by internal timing delays,
and the gate charge required turning on the top MOSFET.
Low duty cycle applications may approach this minimum
on-time limit and care should be taken to ensure that:
VOUT
VIN • FREQ
> t ON(MIN)
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the output ripple and current will increase. The on-time
can be increased by lowering the switching frequency. A
good rule of thumb is to keep on-time longer than 110ns.
Soft-Start And Output Voltage Tracking
500
400
300
200
100
0
The output of the PLL phase detector has a pair of complementary current sources that charge and discharge the
internal filter network. When the external clock is applied
then the fSET frequency resistor is disconnected with
an internal switch, and the current sources control the
frequency adjustment to lock to the incoming external
clock. When no external clock is applied, then the internal
switch is on, thus connecting the external fSET frequency
set resistor for free run operation.
0
0.5
1
1.5
fSET PIN VOLTAGE (V)
2
2.5
4650A F05
Figure 5. Operating Frequency vs fSET Pin Voltage
The TRACK/SS pin provides a means to either soft-start
the regulator or track it to a different power supply. A capacitor on the TRACK/SS pin will program the ramp rate
of the output voltage. An internal 1.3µA current source
will charge up the external soft-start capacitor towards
INTVCC voltage. When the TRACK/SS voltage is below
0.6V, it will take over the internal 0.6V reference voltage
to control the output voltage. The total soft-start time can
be calculated as:
t SS = 0.6 •
C SS
1.3µA
where CSS is the capacitance on the TRACK/SS pin. Current foldback and forced continuous mode are disabled
during the soft-start process.
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LTM4650A
APPLICATIONS INFORMATION
Output voltage tracking can also be programmed externally
using the TRACK/SS pin. The output can be tracked up and
down with another regulator. Figure 6 shows an example
waveform where the slave regulator’s output slew rate is
proportional to the master’s.
Since the slave regulator’s TRACK/SS is connected to
the master’s output through a RTR(TOP)/RTR(BOT) resistor
divider and its voltage used to regulate the slave output
voltage when TRACK/SS voltage is below 0.6V, the slave
output voltage and the master output voltage should satisfy
the following equation during start-up:
VOUT(SL) •
R FB(SL)
R FB(SL) + 60.4k
VOUT(MA) •
=
R TR(BOT)
R TR(TOP) +R TR(BOT)
Following the previous equation, the ratio of the master’s
output slew rate (MR) to the slave’s output slew rate (SR)
is determined by:
R FB(SL)
SR
=
The TRACK/SS pin will have the 2µA current source on
when a resistive divider is used to implement tracking
on the slave regulator. This will impose an offset on the
TRACK/SS pin input. Smaller value resistors with the same
ratios as the resistor values calculated from the above
equation can be used. For example, where the 60.4k is
used then a 6.04k can be used to reduce the TRACK/SS
pin offset to a negligible value.
Coincident output tracking can be recognized as a special
ratiometric output tracking in which the master’s output
slew rate (MR) is the same as the slave’s output slew rate
(SR), waveform as shown in Figure 8.
The RFB(SL) is the feedback resistor and the RTR(TOP)/
RTR(BOT) is the resistor divider on the TRACK/SS pin of
the slave regulator, as shown in Figure 7.
MR
For example, VOUT(MA)=1.5V, MR = 1.5V/1ms and VOUT(SL)
= 3.3V, SR = 3.3V/1ms. From the equation, we could solve
that RTR(TOP) = 60.4k and RTR(BOT) = 40.2k are a good
combination for the ratiometric tracking.
R FB(SL) + 60.4k
From the equation, we could easily find that, in coincident
tracking, the slave regulator’s TRACK/SS pin resistor divider
is always the same as its feedback divider:
R FB(SL)
R FB(SL) + 60.4k
=
R TR(BOT)
R TR(TOP) +R TR(BOT)
For example, RTR(TOP) = 60.4k and RTR(BOT) = 13.3k is a
good combination for coincident tracking for a VOUT(MA)
= 1.5V and VOUT(SL) = 3.3V application.
R TR(BOT)
R TR(TOP) +R TR(BOT)
OUTPUT VOLTAGE
MASTER OUTPUT
SLAVE OUTPUT
TIME
4650A F06
Figure 6. Output Ratiometric Tracking Waveform
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INTVCC
C10
4.7µF
R2
10k
PGOOD1
MODE_PLLIN
4.5V TO 16V INTERMEDIATE BUS
C4
22µF
25V
C3
22µF
25V
C2
22µF
25V
C1
22µF
25V
R6
100k
CSS
C6
100µF
6.3V
×3
VOUTS1
RUN1
RTR(BOT)
40.2k
VOUT1
(MASTER)
1.5V
PGOOD1
VOUT1
TEMP
RUN2
VFB1
TRACK1
VFB2
LTM4650A
TRACK2
RTR(TOP)
60.4k
INTVCC
VIN
f SET
COMP2
PHASMD
VOUTS2
VOUT2
R4
140k
RAMP TIME
tSOFTSTART = (CSS /1.3µA) • 0.6
RFB(SL)
13.3k
COMP1
SLAVE
PGOOD2
PGOOD2
SGND
GND
DIFFP
DIFFN DIFFOUT
C5
100µF
6.3V
×3
VOUT1
(MASTER)
1.5V
25A
C8
470µF
6.3V
C7
470µF
6.3V
40.2k
VOUT2
(SLAVE)
3.3V
25A
INTVCC
R9
10k
PINS NOT USED IN THIS CIRCUIT: CLKOUT
EXTVCC, SW1, SW2
4650A F07
Figure 7. Example of Output Tracking Application Circuit
OUTPUT VOLTAGE
MASTER OUTPUT
SLAVE OUTPUT
TIME
4650A F08
Figure 8. Output Coincident Tracking Waveform
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LTM4650A
APPLICATIONS INFORMATION
Power Good
The PGOOD pins are open drain pins that can be used to
monitor valid output voltage regulation. This pin monitors
a 10% window around the regulation point. A resistor can
be pulled up to a particular supply voltage no greater than
6V maximum for monitoring.
Stability Compensation
The module has already been internally compensated for
all output voltages. Table 6 is provided for most application requirements. LTpowerCAD will be provided for other
control loop optimization.
Run Enable
The RUN pins have an enable threshold of 1.4V maximum,
typically 1.25V with 150mV of hysteresis. They control
the turn on each of the channels and INTVCC. These pins
can be pulled up to VIN for 5V operation, or a 5V Zener
diode can be placed on the pins and a 10k to 100k resistor can be placed up to higher than 5V input for enabling
the channels. There is 1µA pull-up current for each RUN
pin. The LTM4650A will turn on with RUN floating. Please
note RUN has a 6V Abs Max voltage rating. The RUN
pins can also be used for output voltage sequencing.
In parallel operation the RUN pins can be tie together and
controlled from a single control. See the Typical Application circuits in Figure 32.
INTVCC and EXTVCC
The LTM4650A module has an internal 5V low dropout
regulator that is derived from the input voltage. This regulator is used to power the control circuitry and the power
MOSFET drivers. This regulator can source up to 70mA,
and typically uses ~30mA for powering the device at the
maximum frequency. This internal 5V supply is enabled
by either RUN1 or RUN2.
EXTVCC allows an external 5V supply to power the
LTM4650A and reduce power dissipation from the internal
low dropout 5V regulator. The power loss savings can be
calculated by:
EXTVCC has a threshold of 4.7V for activation, and a
maximum rating of 6V. When using a 5V input, connect
this 5V input to EXTVCC also to maintain a 5V gate drive
level. EXTVCC must sequence on after VIN, and EXTVCC
must sequence off before VIN.
Differential Remote Sense Amplifier
An accurate differential remote sense amplifier is provided
to sense low output voltages accurately at the remote
load points. This is especially true for high current loads.
The amplifier can be used on one of the two channels, or
on a single parallel output. It is very important that the
DIFFP and DIFFN are connected properly at the output,
and DIFFOUT is connected to either VOUTS1 or VOUTS2.
In parallel operation, the DIFFP and DIFFN are connected
properly at the output, and DIFFOUT is connected to
one of the VOUTS pins. Review the parallel schematics in
Figure 33 and review Figure 2. Please note Diffamp can
be used for ≤3.3V outputs.
SW Pins
The SW pins are generally for testing purposes by monitoring these pins. These pins can also be used to dampen
out switch node ringing caused by LC parasitic in the
switched current paths. Usually a series R-C combination is used called a snubber circuit. The resistor will
dampen the resonance and the capacitor is chosen to
only affect the high frequency ringing across the resistor.
If the stray inductance or capacitance can be measured or
approximated then a somewhat analytical technique can
be used to select the snubber values. The inductance is
usually easier to predict. It combines the power path board
inductance in combination with the MOSFET interconnect
bond wire inductance.
First the SW pin can be monitored with a wide bandwidth
scope with a high frequency scope probe. The ring frequency can be measured for its value. The impedance Z
can be calculated:
Z(L) = 2πfL,
(VIN – 5V) • 30mA = PLOSS
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0.8
where f is the resonant frequency of the ring, and L is the
total parasitic inductance in the switch path. If a resistor
is selected that is equal to Z, then the ringing should be
dampened. The snubber capacitor value is chosen so that
its impedance is equal to the resistor at the ring frequency.
Calculated by: Z(C) = 1/(2πfC). These values are a good
place to start with. Modification to these components
should be made to attenuate the ringing with the least
amount of power loss.
DIODE VOLTAGE (V)
0.7
0.5
0.3
–50
⎛I ⎞
VD = nVT ln ⎜ D ⎟
⎝I ⎠
–25
50
25
0
75
TEMPERATURE (°C)
100
125
4650A F09
Figure 9. Diode Voltage VD vs Temperature T(K)
for Different Bias Currents
If we take this equation and differentiate it with respect to
temperature T, then:
S
V –V
= – G0 D
dT
T
dVD
where VT is the thermal voltage (kT/q), and n, the ideality
factor, is 1 for the diode connected PNP transistor being
used in the LTM4650A. IS is expressed by the typical
empirical equation:
⎛ –V ⎞
G0 ⎟
IS = I0 exp ⎜⎜
⎜ V ⎟⎟
⎝ T ⎠
This dVD/dT term is the temperature coefficient equal to
about –2mV/K or –2mV/°C. The equation is simplified for
the first order derivation.
Solving for T, T = –(VG0 – VD)/(dVD/dT) provides the
temperature.
where I0 is a process and geometry dependent current, (I0
is typically around 20k orders of magnitude larger than IS
at room temperature) and VG0 is the band gap voltage of
1.2V extrapolated to absolute zero or –273°C.
If we take the IS equation and substitute into the VD equation, then we get:
0.6
0.4
Temperature Monitoring
A diode connected PNP transistor is used for the TEMP
monitor function by monitoring its voltage over temperature. The temperature dependence of this diode voltage
can be understood in the equation:
ID = 100µA
kT
⎛ kT ⎞ ⎛ I ⎞
VD = VG0 – ⎜ ⎟ ln ⎜ 0 ⎟ , VT =
⎝ q ⎠ ⎝ ID ⎠
q
The expression shows that the diode voltage decreases
(linearly if I0 were constant) with increasing temperature
and constant diode current. Figure 9 shows a plot of VD
vs Temperature over the operating temperature range of
the LTM4650A.
1st Example: Figure 9 for 27°C, or 300K the diode
voltage is 0.598V, thus, 300K = –(1200mV – 598mV)/
–2.0 mV/K)
2nd Example: Figure 9 for 75°C, or 350K the diode
voltage is 0.50V, thus, 350K = –(1200mV – 500mV)/
–2.0mV/K)
Converting the Kelvin scale to Celsius is simply taking the
Kelvin temp and subtracting 273 from it.
A typical forward voltage is given in the electrical characteristics section of the data sheet, and Figure 9 is the plot
of this forward voltage. Measure this forward voltage at
27°C to establish a reference point. Then using the above
expression while measuring the forward voltage over
temperature will provide a general temperature monitor.
Connect a resistor between TEMP and VIN to set the current to 100µA. See Figure 33 for an example.
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LTM4650A
APPLICATIONS INFORMATION
Thermal Considerations and Output Current Derating
The thermal resistances reported in the Pin Configuration
section of the data sheet are consistent with those parameters defined by JESD51-9 and are intended for use with
finite element analysis (FEA) software modeling tools that
leverage the outcome of thermal modeling, simulation,
and correlation to hardware evaluation performed on a
µModule package mounted to a hardware test board—also
defined by JESD51-9 (“Test Boards for Area Array Surface
Mount Package Thermal Measurements”). The motivation
for providing these thermal coefficients is found in JESD
51-12 (“Guidelines for Reporting and Using Electronic
Package Thermal Information”).
Many designers may opt to use laboratory equipment
and a test vehicle such as the demo board to anticipate
the µModule regulator’s thermal performance in their application at various electrical and environmental operating
conditions to compliment any FEA activities. Without FEA
software, the thermal resistances reported in the Pin Configuration section are in-and-of themselves not relevant to
providing guidance of thermal performance; instead, the
derating curves provided in the data sheet can be used in
a manner that yields insight and guidance pertaining to
one’s application-usage, and can be adapted to correlate
thermal performance to one’s own application.
The Pin Configuration section typically gives four thermal
coefficients explicitly defined in JESD 51-12; these coefficients are quoted or paraphrased below:
1. θJA, the thermal resistance from junction to ambient, is the natural convection junction-to-ambient
air thermal resistance measured in a one cubic foot
sealed enclosure. This environment is sometimes
referred to as “still air” although natural convection
causes the air to move. This value is determined with
the part mounted to a JESD 51-9 defined test board,
which does not reflect an actual application or viable
operating condition.
2. θJCbottom, the thermal resistance from junction to the
bottom of the product case, is the junction-to-board
thermal resistance with all of the component power
dissipation flowing through the bottom of the package.
In the typical µModule, the bulk of the heat flows out
the bottom of the package, but there is always heat
flow out into the ambient environment. As a result, this
thermal resistance value may be useful for comparing
packages but the test conditions don’t generally match
the user’s application.
3. θJCTOP, the thermal resistance from junction to top of
the product case, is determined with nearly all of the
component power dissipation flowing through the top
of the package. As the electrical connections of the
typical µModule are on the bottom of the package, it
is rare for an application to operate such that most of
the heat flows from the junction to the top of the part.
As in the case of θJCBOTTOM, this value may be useful
for comparing packages but the test conditions don’t
generally match the user’s application.
4. θJB, the thermal resistance from junction to the
printed circuit board, is the junction-to-board thermal
resistance where almost all of the heat flows through
the bottom of the µModule and into the board, and
is really the sum of the θJCbottom and the thermal resistance of the bottom of the part through the solder
joints and through a portion of the board. The board
temperature is measured a specified distance from
the package, using a two sided, two layer board. This
board is described in JESD 51-9.
A graphical representation of the aforementioned thermal
resistances is given in Figure 10; blue resistances are
contained within the µModule regulator, whereas green
resistances are external to the µModule.
As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD 51-12 or provided in the
Pin Configuration section replicates or conveys normal
operating conditions of a µModule. For example, in normal
board-mounted applications, never does 100% of the
device’s total power loss (heat) thermally conduct exclusively through the top or exclusively through bottom of the
µModule—as the standard defines for θJCtop and θJCbottom,
respectively. In practice, power loss is thermally dissipated
in both directions away from the package—granted, in the
absence of a heat sink and airflow, a majority of the heat
flow is into the board.
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LTM4650A
APPLICATIONS INFORMATION
JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-CASE (TOP)
RESISTANCE
JUNCTION
JUNCTION-TO-BOARD RESISTANCE
AMBIENT
JUNCTION-TO-CASE
CASE (BOTTOM)-TO-BOARD
(BOTTOM) RESISTANCE
RESISTANCE
BOARD-TO-AMBIENT
RESISTANCE
4650A F10
µModule DEVICE
Figure 10. Graphical Representation of JESD51-12 Thermal Coefficients
Within a SIP (system-in-package) module, be aware there
are multiple power devices and components dissipating
power, with a consequence that the thermal resistances
relative to different junctions of components or die are not
exactly linear with respect to total package power loss. To
reconcile this complication without sacrificing modeling
simplicity—but also, not ignoring practical realities—an
approach has been taken using FEA software modeling
along with laboratory testing in a controlled-environment
chamber to reasonably define and correlate the thermal
resistance values supplied in this data sheet: (1) Initially,
FEA software is used to accurately build the mechanical
geometry of the µModule and the specified PCB with all
of the correct material coefficients along with accurate
power loss source definitions; (2) this model simulates
a software-defined JEDEC environment consistent with
JESD51-9 to predict power loss heat flow and temperature
readings at different interfaces that enable the calculation of
the JEDEC-defined thermal resistance values; (3) the model
and FEA software is used to evaluate the µModule with
heat sink and airflow; (4) having solved for and analyzed
these thermal resistance values and simulated various
operating conditions in the software model, a thorough
laboratory evaluation replicates the simulated conditions
with thermocouples within a controlled-environment
chamber while operating the device at the same power loss
as that which was simulated. An outcome of this process
and due-diligence yields a set of derating curves provided
in other sections of this data sheet. After these laboratory
test have been performed and correlated to the µModule
model, then the θJB and θBA are summed together to correlate quite well with the µModule model with no airflow or
heat sinking in a properly define chamber. This θJB + θBA
value is shown in the Pin Configuration section and should
accurately equal the θJA value because approximately
100% of power loss flows from the junction through the
board into ambient with no airflow or top mounted heat
sink. Each system has its own thermal characteristics,
therefore thermal analysis must be performed by the user
in a particular system.
The LTM4650A module has been designed to effectively
remove heat from both the top and bottom of the package. The bottom substrate material has very low thermal
resistance to the printed circuit board. An external heat
sink can be applied to the top of the device for excellent
heat sinking with airflow.
Figure 11 shows the thermal image of the LTM4650A,
without airflow, without heat sink, running paralleled from
12V to 1V at 50A with around 87.3% efficiency and 7.2W
power loss. Figure 12 shows the thermal image of the
LTM4650A, with 200LFM airflow and external heat sink,
running paralleled form 12V to 5V at 50A with around
95% efficiency and 13W power loss.
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LTM4650A
APPLICATIONS INFORMATION
Safety Considerations
The LTM4650A modules do not provide isolation from
VIN to VOUT. There is no internal fuse. If required, a slow
blow fuse with a rating twice the maximum input current
needs to be provided to protect each unit from catastrophic
failure. The device does support over current protection.
A temperature diode is provided for monitoring internal
temperature, and can be used to detect the need for thermal
shutdown that can be done by controlling the RUN pin.
Power Derating
The 1V, 1.8V, 3.3V and 5V power loss curves in Figures 14
to 17 can be used in coordination with the load current
derating curves in Figures 18 to 31 for calculating an approximate θJA thermal resistance for the LTM4650A with
various heat sinking and airflow conditions. The power loss
curves are taken at room temperature, and are increased
with a 1.2 multiplicative factor at 125°C.
The derating curves are plotted with CH1 and CH2 in parallel
single output operation starting at 50A of load with low
ambient temperature. The output voltages are 1V to 5V.
These are chosen to include the lower and higher output
voltage ranges for correlating the thermal resistance.
Thermal models are derived from several temperature
measurements in a controlled temperature chamber along
with thermal modeling analysis.
Figure 11. Thermal Image 12V to 1V, 50A
with No Airflow without Heat Sink
The junction temperatures are monitored while ambient
temperature is increased with and without airflow. The
power loss increase with ambient temperature change
is factored into the derating curves. The junctions are
maintained at ~120°C maximum while lowering output
current or power while increasing ambient temperature.
The decreased output current will decrease the internal
module loss as ambient temperature is increased.
The monitored junction temperature of 120°C minus
the ambient operating temperature specifies how much
module temperature rise can be allowed. As an example in
Figure 22, the load current is derated to ~25A at ~90°C with
no air or heat sink and the power loss for the 12V to 1.8V
at 25A output is a ~4.4W loss. The 4.4W loss is calculated
with the ~3.7W room temperature loss from the 12V to
1.8V power loss curve at 25A, and the 1.2 multiplying
factor at 120°C ambient. If the 90°C ambient temperature
is subtracted from the 120°C junction temperature, then
the difference of 30°C divided 4.4W equals a 6.8°C/W θJA
thermal resistance. Table 2 specifies a 7°C/W value which
is pretty close. The airflow graphs are more accurate due
to the fact that the ambient temperature environment
is controlled better with airflow. Tables 2 to 5 provide
equivalent thermal resistances for 1V to 5V outputs with
and without airflow and heat sinking.
Figure 12. Thermal Image 12V to 5V, 50A
with 200LFM Airflow without Heat Sink
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APPLICATIONS INFORMATION
The derived thermal resistances in Tables 2 and 3 for the
various conditions can be multiplied by the calculated
power loss as a function of ambient temperature to derive
temperature rise above ambient, thus maximum junction
temperature. Room temperature power loss can be derived
from the efficiency curves and adjusted with the above
ambient temperature multiplicative factors. The printed
circuit board is a 1.6mm thick four layer board with two
ounce copper for all four layers. The PCB dimensions are
101mm × 114mm. The BGA heat sinks are listed in Table 3.
•
Place high frequency ceramic input and output capacitors next to the VIN, PGND and VOUT pins to minimize
high frequency noise.
• Place a dedicated power ground layer underneath the
unit.
To minimize the via conduction loss and reduce module
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
•
• Do not put via directly on the pad, unless they are
capped or plated over.
Layout Checklist/Example
• Use a separated SGND ground copper area for components connected to signal pins. Connect the SGND
to GND underneath the unit.
The high integration of LTM4650A makes the PCB board
layout very simple and easy. However, to optimize its electrical and thermal performance, some layout considerations
are still necessary.
• Use large PCB copper areas for high current paths,
including VIN, GND, VOUT1 and VOUT2. It helps to
minimize the PCB conduction loss and thermal stress.
•
For parallel modules, tie the VOUT, VFB, and COMP pins
together. Use an internal layer to closely connect these
pins together. The TRACK pin can be tied a common
capacitor for regulator soft-start.
•
Bring out test points on the signal pins for monitoring.
Figure 13 gives a good example of the recommended layout.
CIN1
CIN2
VIN
M
GND
L
GND
K
J
H
G
SGND
F
COUT1
COUT2
E
D
C
B
A
VOUT1
1
2
3
4
5
6
7
8
9
10
11 12
GND
VOUT2
CNTRL
4650A F13
Figure 13. Recommended PCB Layout
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LTM4650A
APPLICATIONS INFORMATION
Table 2. 1.0V Output
DERATING CURVE
Figures 18, 19
Figures 18, 19
Figures 18, 19
Figures 20, 21
Figures 20, 21
Figures 20, 21
VIN (V)
5, 12
5, 12
5, 12
5, 12
5, 12
5, 12
POWER LOSS CURVE
Figure 14
Figure 14
Figure 14
Figure 14
Figure 14
Figure 14
AIRFLOW (LFM)
0
200
400
0
200
400
HEAT SINK
None
None
None
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
θJA (°C/W)
7
6
5.5
6.5
5
4
VIN (V)
POWER LOSS CURVE
AIRFLOW (LFM)
HEAT SINK
5, 12
5, 12
5, 12
5, 12
5, 12
5, 12
Figure 15
Figure 15
Figure 15
Figure 15
Figure 15
Figure 15
0
200
400
0
200
400
None
None
None
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
θJA (°C/W)
7
6
5.5
6.5
4
3.5
VIN (V)
5, 12
5, 12
5, 12
5, 12
5, 12
5, 12
POWER LOSS CURVE
Figure 16
Figure 16
Figure 16
Figure 16
Figure 16
Figure 16
AIRFLOW (LFM)
0
200
400
0
200
400
HEAT SINK
None
None
None
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
θJA (°C/W)
7
6
5.5
6.5
5
4
VIN (V)
POWER LOSS CURVE
AIRFLOW (LFM)
HEAT SINK
12
12
12
12
12
12
Figure 17
Figure 17
Figure 17
Figure 17
Figure 17
Figure 17
0
200
400
0
200
400
None
None
None
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
θJA (°C/W)
7
6
5.5
6.5
4
3.5
Table 3. 1.8V Output
DERATING CURVE
Figures 22, 23
Figures 22, 23
Figures 22, 23
Figures 24, 25
Figures 24, 25
Figures 24, 25
Table 4. 3.3V Output
DERATING CURVE
Figures 26, 27
Figures 26, 27
Figures 26, 27
Figures 28, 29
Figures 28, 29
Figures 28, 29
Table 5. 5V Output
DERATING CURVE
Figures 30
Figures 30
Figures 30
Figures 31
Figures 31
Figures 31
HEAT SINK MANUFACTURER
PART NUMBER
WEBSITE
Aavid Thermalloy
375424B00034G
www.aavid.com
4650afb
26
For more information www.linear.com/LTM4650A
LTM4650A
APPLICATIONS INFORMATION
Table 6. Output Voltage Response vs Component Matrix (Refer to Figure 33) Load Step Typical Measured Values
2-Phase Single Output Solution
CIN (CERAMIC)
COUT (CERAMIC)
PART NUMBER
VENDORS
VALUE
COUT (BULK)
VENDORS
VALUE
MURATA
22μF, 16V, GRM32ER61C226KE20L MURATA
X5R, 1210
100μF, 6.3V, GRM32ER60J107ME20L Panasonic 470µF, 6.3V 6TPF470MAH1
X5R, 1210
10mΩ
PART NUMBER
MURATA
22μF, 16V, GRM31CR61C226KE15K MURATA
X5R, 1206
220μF, 4V,
X5R, 1206
TDK
22μF, 16V, C3225X5R1C226M250AA Taiyo Yuden 100μF, 6.3V, JMK325BJ107MM-T
X5R, 1210
X5R, 1210
Taiyo Yuden 220µF, 4V,
X5R, 1210
VENDORS VALUE
PART NUMBER
Panasonic 470µF, 2.5V EEFGX0E4TIR2
3mΩ
GRM31CR60G227M
AMK325ABJ227MM-T
25% Load Step (0A to 12.5A), Ceramic Output Cap Only Solutions
VIN
VOUT
CIN 3
(BULK)
CIN
(CERAMIC)
COUT
(BULK)
PEAK-PEAK SETTLING
COUT
FEED-FORWARD DEVIATION
TIME
LOAD LOAD STEP
(CERAMIC) CAPACITOR (CFF) (VPK-PK)
(tSETTLE) STEP SLEW RATE
RFB
(kΩ)
FREQ
(kHz)
12V
1V
150µF
22µF ×4
None
100µF×16
47pF
102mV
50µs
12.5A
10A/µs
90.9
300kHz
12V
1.2V
150µF
22µF ×4
None
100µF×16
47pF
92mV
50µs
12.5A
10A/µs
60.4
400kHz
12V
1.5V
150µF
22µF ×4
None
100µF×16
47pF
105mV
50µs
12.5A
10A/µs
40.2
400kHz
12V
1.8V
150µF
22µF ×4
None
100µF×16
47pF
109mV
50µs
12.5A
10A/µs
30.2
500kHz
12V
2.5V
150µF
22µF ×4
None
100µF×16
47pF
134mV
60µs
12.5A
10A/µs
19.1
500kHz
12V
3.3V
150µF
22µF ×4
None
100µF×16
47pF
161mV
60µs
12.5A
10A/µs
13.3
600kHz
12V
5V
RFB
(kΩ)
FREQ
(kHz)
Suggest to Use POSCAP + Ceramic Cap
25% Load Step (0A to 12.5A), POSCAP+Ceramic Output Cap Solutions
VIN
VOUT
12V
1V
150µF
22µF ×4
470µF×42
100µF×8
None
82mV
50µs
12.5A
10A/µs
90.9
300kHz
12V
1.2V
150µF
22µF ×4
470µF×42
100µF×8
None
80mV
50µs
12.5A
10A/µs
60.4
400kHz
22µF ×4
470µF×42
100µF×8
None
92mV
60µs
12.5A
10A/µs
40.2
400kHz
22µF ×4
470µF×42
100µF×8
None
97mV
70µs
12.5A
10A/µs
30.2
500kHz
12V
12V
1.5V
1.8V
150µF
150µF
CIN
(CERAMIC)
COUT
(BULK)
PEAK-PEAK SETTLING
COUT
FEED-FORWARD DEVIATION
TIME
LOAD LOAD STEP
(CERAMIC) CAPACITOR (CFF) (VPK-PK)
(tSETTLE) STEP SLEW RATE
CIN 3
(BULK)
12V
2.5V
150µF
22µF ×4
470µF×42
100µF×8
None
117mV
70µs
12.5A
10A/µs
19.1
500kHz
12V
3.3V
150µF
22µF ×4
470µF×41
100µF×8
None
127mV
80µs
12.5A
10A/µs
13.3
600kHz
22µF ×4
470µF×41
100µF×8
None
167mV
100µs
12.5A
10A/µs
8.25
700kHz
12V
5V
150µF
Notes 1 and 2. Different (BULK) COUT are used. See part number in Table 6.
Note 3. CIN (BULK) may be required with long PCB traces.
4650afb
For more information www.linear.com/LTM4650A
27
LTM4650A
10
10
12
9
9
11
8
8
10
7
7
6
5
4
3
9
POWER LOSS (W)
POWER LOSS (W)
POWER LOSS (W)
APPLICATIONS INFORMATION
6
5
4
3
VIN = 5V
VIN = 12V
1
0
0
5
10 15 20 25 30 35 40 45 50
LOAD CURRENT (A)
0
5
LOAD CURRENT (A)
LOAD CURRENT (A)
POWER LOSS (W)
50
40
30
20
0LFM
200LFM
400LFM
30
40
30
20
0
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
LOAD CURRENT (A)
50
LOAD CURRENT (A)
50
40
40
30
20
0LFM
200LFM
400LFM
10
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
0
30
40
40
30
20
0LFM
200LFM
400LFM
10
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4650A F20
Figure 20. 12V to 1V Derating
Curve, BGA Heat Sink
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4650A F19
50
30
40
Figure 19. 5V to 1V Derating
Curve, No Heat Sink
60
0
30
4650A F18
60
0LFM
200LFM
400LFM
0LFM
200LFM
400LFM
10
60
10
10 15 20 25 30 35 40 45 50
LOAD CURRENT (A)
40
Figure 18. 12V to 1V Derating
Curve, No Heat Sink
20
5
4650A F16
50
4650A F17
30
0
Figure 16. 3.3VOUT Power
Loss Curve
60
Figure 17. 5VOUT Power Loss
Curve
LOAD CURRENT (A)
0
60
0
10 15 20 25 30 35 40 45 50
LOAD CURRENT (A)
40
VIN = 5V
VIN = 12V
4650A F15
VIN = 12V
5
4
Figure 15. 1.8VOUT Power Loss
Curve
10
0
5
1
10 15 20 25 30 35 40 45 50
LOAD CURRENT (A)
4650A F14
Figure 14. 1.0VOUT Power Loss
Curve
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
6
2
VIN = 5V
VIN = 12V
1
0
7
3
2
2
8
0
30
40
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4650A F21
Figure 21. 5V to 1V Derating
Curve, BGA Heat Sink
4650A F22
Figure 22. 12V to 1.8V
Derating Curve, No Heat Sink
4650afb
28
For more information www.linear.com/LTM4650A
LTM4650A
60
60
50
50
50
40
30
20
0LFM
200LFM
400LFM
10
0
30
40
LOAD CURRENT (A)
60
LOAD CURRENT (A)
LOAD CURRENT (A)
APPLICATIONS INFORMATION
40
30
20
0LFM
200LFM
400LFM
10
0
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
30
40
0LFM
200LFM
400LFM
0
30
60
50
50
50
20
0LFM
200LFM
400LFM
10
0
30
40
LOAD CURRENT (A)
60
30
40
30
20
0LFM
200LFM
400LFM
10
0
50 60 70 80 90 100 110
AMBIENT TEMPERATURE (°C)
30
40
4650A F26
40
30
20
0
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
Figure 27. 5V to 3.3V Derating
Curve, No Heat Sink
50
50
0LFM
200LFM
400LFM
0
30
40
LOAD CURRENT (A)
50
LOAD CURRENT (A)
60
10
40
30
20
0LFM
200LFM
400LFM
10
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
0
30
40
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
40
30
20
0LFM
200LFM
400LFM
10
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4650A F29
Figure 29. 5V to 3.3V Derating
Curve, BGA Heat Sink
40
Figure 28. 12V to 3.3V Derating
Curve, BGA Heat Sink
60
20
30
4650A F28
60
30
0LFM
200LFM
400LFM
10
4650A F27
Figure 26. 12V to 3.3V Derating
Curve, No Heat Sink
40
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
Figure 25. 5V to 1.8V Derating
Curve, BGA Heat Sink
60
40
40
4650A F25
Figure 24. 12V to 1.8V Derating
Curve, BGA Heat Sink
LOAD CURRENT (A)
LOAD CURRENT (A)
20
4650A F24
Figure 23. 5V to 1.8V Derating
Curve, No Heat Sink
LOAD CURRENT (A)
30
10
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4650A F23
40
0
30
40
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4650A F31
4650A F30
Figure 30. 12V to 5V Derating
Curve, No Heat Sink
Figure 31. 12V to 5V Derating
Curve, BGA Heat Sink
4650afb
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29
LTM4650A
TYPICAL APPLICATIONS
INTVCC
C10
4.7µF
R2
10k
PGOOD1
VIN
4.5V TO 16V
MODE_PLLIN
4.5V TO 16V INTERMEDIATE BUS
+
CIN
(OPT)
CIN
22µF
25V
×4
R7
100k
TEMP
VOUTS1
CFF1*
47pF
RUN1
RUN2
VFB1
TRACK1
VFB2
LTM4650A
TRACK2
TRACK2
RFB2
60.4k
COMP1
C9
0.1µF
VOUT1
COUT1 1.5V AT 25A
100µF
6.3V
×8
VOUT1
VIN
TRACK1
C5
0.1µF
PGOOD1
INTVCC
COMP2
RFB1
40.2k
CFF2*
47pF
VOUTS2
VOUT2
fSET
R4
90.9k
PHASMD
SGND
GND
DIFFP
DIFFN
PGOOD2
DIFFOUT
VOUT2
1.2V AT 25A
INTVCC
R3
10k
PGOOD2
COUT1
100µF
6.3V
×8
*SEE TABLE 4
PINS NOT USED IN THIS CIRCUIT: CLKOUT,
EXTVCC, SW1, SW2
4650A F32
Figure 32. Typical 4.5VIN to 16VIN, 1.5V and 1.2V at 25A Outputs
4650afb
30
For more information www.linear.com/LTM4650A
LTM4650A
TYPICAL APPLICATIONS
VIN
RT =
µC
RT
VIN
100µA
INTVCC
INTVCC
A/D
C10
4.7µF
R2
10k
PGOOD
MODE_PLLIN
VIN
4.5V TO 16V
CIN
22µF
25V
×4
RUN
TRACK
VOUT2
TEMP
VOUT1
RUN1
RUN2
VOUTS1
47pF
TRACK1
VFB1
LTM4650A
TRACK2
C9
0.1µF
PGOOD1
INTVCC
VIN
VOUT
1V
50A
COUT1
100µF
6.3V
×16
R5
90.9k
VFB2
COMP1
LOAD
1V AT 50A
COMP2
fSET
PGOOD2
PGOOD
PHASMD
R4
75k
SGND
GND
DIFFN
DIFFP
DIFFOUT
PINS NOT USED IN THIS CIRCUIT: CLKOUT,
EXTVCC, SW1, SW2, VOUTS2
4650A F33
Figure 33. LTM4650A 2-Phase, 1V at 50A Design
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31
LTM4650A
TYPICAL APPLICATIONS
INTVCC
C10
4.7µF
R2
10k
PGOOD1
VIN
4.5V TO
16V
MODE_PLLIN
C4
22µF
25V
C3
22µF
25V
C2
22µF
25V
C1
22µF
25V
R6
100k
TEMP
VOUTS1
R7
13.3k
VFB1
LTM4650A
TRACK2
R9
60.4k
PGOOD1
VOUT1
TRACK1
C5
0.1µF
INTVCC
VIN
VOUTS2
RUN1
RUN2
VOUT2
COMP2
fSET
R4
140k
PHASMD
SGND
+
470µF
4V
LOAD
2.5V AT 25A
R5
19.1k
DIFFOUT
COMP1
VOUT1
2.5V
COUT1
220µF
4V
×2
VOUT1
2.5V
25A
GND
PGOOD2
DIFFN
VFB2
DIFFP
COUT1
220µF
4V
×2
+
470µF
4V
VOUT2
3.3V AT 25A
LOAD
3.3V AT 25A
13.3k
PGOOD2
PINS NOT USED IN THIS CIRCUIT: CLKOUT,
EXTVCC, SW1, SW2,
10k
INTVCC
4650A F34
Figure 34. LTM4650A 2.5V and 3.3V Output with Tracking Function
4650afb
32
For more information www.linear.com/LTM4650A
LTM4650A
TYPICAL APPLICATIONS
INTVCC
C10
4.7µF
CLK1
PGOOD
MODE_PLLIN CLKOUT INTVCC
VIN
4.5V TO 16V
C2
22µF
25V
×3
PGOOD1
VIN
R6
100k
TEMP
RUN
RUN2
R2
5k
VOUT1
VOUTS1
47pF
RUN1
TRACK
TRACK1
LTM4650A
U1
TRACK2
COMP1
COMP
VFB1
VFB
VFB2
R5
60.4k
COUT1
100µF
4V
×16
VOUTS2
COMP2
VOUT2
fSET
PGOOD2
PHASMD
R4
75k
SGND
GND
DIFFP
DIFFN
PGOOD
DIFFOUT
VOUT
1.2V
100A
C16
4.7µF
CLK1
MODE_PLLIN CLKOUT
C15
22µF
25V
×3
R9
100k
PGOOD1
INTVCC
VOUT1
VIN
TEMP
RUN
TRACK
VOUTS1
RUN1
RUN2
VFB1
TRACK1
VFB2
LTM4650A
U2
TRACK2
COMP
R10
75k
VOUT2
PGOOD2
PHASMD
SGND
VFB
COUT1
100µF
4V
×16
VOUTS2
COMP1
COMP2
fSET
C19
0.22µF
PGOOD
GND
DIFFP
PGOOD
DIFFN
4650A F35
PINS NOT USED IN CIRCUIT LTM4650A U1:
EXTVCC, SW1, SW2
INTVCC
PINS NOT USED IN CIRCUIT LTM4650A U2:
DIFFOUT, EXTVCC, SW1, SW2
Figure 35. LTM4650A 4-Phase, 1.2V at 100A
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33
LTM4650A
PACKAGE DESCRIPTION
LTM4650A Component LGA and BGA Pinout
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
A1
VOUT1
B1
VOUT1
C1
VOUT1
D1
GND
E1
GND
F1
GND
A2
VOUT1
B2
VOUT1
C2
VOUT1
D2
GND
E2
GND
F2
GND
A3
VOUT1
B3
VOUT1
C3
VOUT1
D3
GND
E3
GND
F3
GND
A4
VOUT1
B4
VOUT1
C4
VOUT1
D4
GND
E4
GND
F4
MODE_PLLIN
A5
VOUT1
B5
VOUT1
C5
VOUT1S
D5
VFB1
E5
TRACK1
F5
RUN1
A6
GND
B6
GND
C6
fSET
D6
SGND
E6
COMP1
F6
SGND
A7
GND
B7
GND
C7
SGND
D7
VFB2
E7
COMP2
F7
SGND
A8
VOUT2
B8
VOUT2
C8
VOUT2S
D8
TRACK2
E8
DIFFP
F8
DIFFOUT
A9
VOUT2
B9
VOUT2
C9
VOUT2
D9
GND
E9
DIFFN
F9
RUN2
A10
VOUT2
B10
VOUT2
C10
VOUT2
D10
GND
E10
GND
F10
GND
A11
VOUT2
B11
VOUT2
C11
VOUT2
D11
GND
E11
GND
F11
GND
A12
VOUT2
B12
VOUT2
C12
VOUT2
D12
GND
E12
GND
F12
GND
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
G1
GND
H1
GND
J1
GND
K1
GND
L1
GND
M1
GND
G2
SW1
H2
GND
J2
VIN
K2
VIN
L2
VIN
M2
VIN
G3
GND
H3
GND
J3
VIN
K3
VIN
L3
VIN
M3
VIN
G4
PHASEMD
H4
GND
J4
VIN
K4
VIN
L4
VIN
M4
VIN
G5
CLKOUT
H5
GND
J5
GND
K5
GND
L5
VIN
M5
VIN
G6
SGND
H6
GND
J6
TEMP
K6
GND
L6
VIN
M6
VIN
G7
SGND
H7
GND
J7
EXTVCC
K7
GND
L7
VIN
M7
VIN
G8
PGOOD2
H8
INTVCC
J8
GND
K8
GND
L8
VIN
M8
VIN
G9
PGOOD1
H9
GND
J9
VIN
K9
VIN
L9
VIN
M9
VIN
G10
GND
H10
GND
J10
VIN
K10
VIN
L10
VIN
M10
VIN
G11
SW2
H11
GND
J11
VIN
K11
VIN
L11
VIN
M11
VIN
G12
GND
H12
GND
J12
GND
K12
GND
L12
GND
M12
GND
4650afb
34
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LTM4650A
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTM4650A#packaging for the most recent package drawings.
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35
aaa Z
0.630 ±0.025 Ø 144x
E
PACKAGE TOP VIEW
3.1750
3.1750
SUGGESTED PCB LAYOUT
TOP VIEW
1.9050
4
0.6350
0.0000
0.6350
PIN “A1”
CORNER
1.9050
For more information www.linear.com/LTM4650A
6.9850
5.7150
4.4450
3.1750
1.9050
0.6350
0.0000
0.6350
1.9050
3.1750
4.4450
5.7150
6.9850
Y
X
D
b1
DETAIL B
H2
MOLD
CAP
ccc Z
SYMBOL
A
A1
A2
b
b1
D
E
e
F
G
H1
H2
aaa
bbb
ccc
ddd
eee
H1
SUBSTRATE
A1
NOM
5.01
0.60
4.41
0.75
0.63
16.00
16.00
1.27
13.97
13.97
0.41
4.00
MAX
5.21
0.70
4.51
0.90
0.66
BALL DIMENSION
PAD DIMENSION
BALL HT
NOTES
SUBSTRATE THK
0.46
MOLD CAP HT
4.05
0.15
0.10
0.20
0.30
0.15
TOTAL NUMBER OF BALLS: 144
0.36
3.95
MIN
4.81
0.50
4.31
0.60
0.60
A
A2
DETAIL B
PACKAGE SIDE VIEW
DIMENSIONS
ddd M Z X Y
eee M Z
DETAIL A
Øb (144 PLACES)
aaa Z
// bbb Z
(Reference LTC DWG # 05-08-1523 Rev A)
Z
36
Z
BGA Package
144-Lead (16mm × 16mm × 5.01mm)
e
L
b
K
J
G
G
F
E
e
PACKAGE BOTTOM VIEW
H
D
C
B
DETAIL A
A
DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
BALL DESIGNATION PER JESD MS-028 AND JEP95
6
TRAY PIN 1
BEVEL
!
PACKAGE IN TRAY LOADING ORIENTATION
LTMXXXXXX
µModule
12
11
10
9
8
7
6
5
4
3
2
1
3
SEE NOTES
PIN 1
6
SEE NOTES
BGA 144 0517 REV A
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
5. PRIMARY DATUM -Z- IS SEATING PLANE
4
3
2. ALL DIMENSIONS ARE IN MILLIMETERS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
COMPONENT
PIN “A1”
F
b
M
LTM4650A
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTM4650A#packaging for the most recent package drawings.
4650afb
6.9850
5.7150
4.4450
4.4450
5.7150
6.9850
LTM4650A
REVISION HISTORY
REV
DATE
DESCRIPTION
A
07/17
Added Pin Compatible feature
B
10/17
Added LGA Package
PAGE NUMBER
1
1, 2, 35, 38
4650afb
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license
is granted
by implication
or otherwise under any patent or patent rights of Analog Devices.
For more
information
www.linear.com/LTM4650A
37
LTM4650A
PACKAGE PHOTO
LGA
BGA
DESIGN RESOURCES
SUBJECT
DESCRIPTION
µModule Design and Manufacturing Resources
Design:
• Selector Guides
• Demo Boards and Gerber Files
• Free Simulation Tools
µModule Regulator Products Search
1. Sort table of products by parameters and download the result as a spread sheet.
Manufacturing:
• Quick Start Guide
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability
2. Search using the Quick Power Search parametric table.
TechClip Videos
Quick videos detailing how to bench test electrical and thermal performance of µModule products.
Digital Power System Management
Analog Devices’s family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.
RELATED PARTS
PART
NUMBER
LTM4630A
DESCRIPTION
COMMENTS
Lower Current than LTM4650A; Up to 5.3VOUT,
Dual 18A or Single 36A
Pin Compatible with LTM4650A; 4.5V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 5.3V,
16mm × 16mm × 4.41mm (LGA)
LTM4630-1 Lower Current and lower VOUT(MAX) than LTM4650A with
External Compensation. Dual 18A or Single 36A. ±0.8%
(–1A) or ±1.5% (–1B) VOUT accuracy
4.5V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 1.8V, 16mm × 16mm × 5.01mm (BGA)
LTM4630
Lower Current, Lower VOUT(MAX) than LTM4650A;
Dual 18A or Single 36A
Pin Compatible with LTM4650A; 4.5V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 1.8V,
16mm × 16mm × 4.41mm (LGA), 16mm × 16mm × 5.01mm (BGA)
LTM4620A
Lower Current than LTM4650A; Up to 5.3VOUT,
Dual 13A or Single 26A.
Pin Compatible with LTM4650A. 4.5V ≤ VIN ≤ 16V, 0.6V ≤ VOUT ≤ 5.3V,
15mm × 15mm × 4.41mm (LGA), 15mm × 15mm × 5.01mm (BGA)
LTM4636
Single 40A µModule Regulator
4.7V ≤ VIN ≤ 15V. 0.6V ≤ VOUT ≤ 3.3V. 16mm × 16mm × 7.07mm (BGA)
LTM4677
Dual 18A or Single 36A with PSM
4.5V ≤ VIN ≤ 16V, 0.5V ≤ VOUT ≤ 1.8V. 16mm × 16mm × 5.01mm (BGA)
LTM4644
Quad 4A
4V ≤ VIN ≤ 14V, 0.6V ≤ VOUT ≤ 5.5V. 9mm × 15mm × 5.01mm (BGA)
LTM4639
Lower VIN (2.375V ≤ VIN ≤ 7V), 20A
0.6V ≤ VOUT ≤ 5.5V. 15mm × 15mm × 4.92mm (BGA)
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38
LT 1017 REV B • PRINTED IN USA
www.linear.com/LTM4650A
For more information www.linear.com/LTM4650A
ANALOG DEVICES, INC. 2017
工商网监
湘ICP备2023018690号
