LTM4652
Source/Sink Dual ±25A or Single ±50A µModule
Regulator with Input Overvoltage Protection
FEATURES
DESCRIPTION
Dual ±25A or Single ±50A Output Source/Sink
n Input Voltage Range: 4.5V to 18V (20V Abs Max)
n Output Voltage Range: 0.6V to 7.5V (8V Abs Max)
n ±1.5% Maximum Total DC Output Error Over Line,
Load and Temperature
n Adjustable Control Loop Compensation
n Differential Remote Sense Amplifier
n Current Mode Control/Fast Transient Response
n Multiphase Parallel Current Sharing Up to ±300A
n Internal Temperature Monitor
n Adjustable Switching Frequency or Synchronization
n Overcurrent Foldback Protection
n Selectable Pulse-Skipping Mode Operation
n Soft-Start/Voltage Tracking
n Input and Output Overvoltage Protection
n 16mm × 16mm × 4.92mm BGA Package
The LTM®4652 is a source/sink dual ±25A or single ±50A
output switching mode step-down DC/DC µModule®
(micromodule) regulator with ±1.5% total DC output
error. Included in the package are the switching controllers, power MOSFETs, inductors and all supporting
components. Operating from an input voltage range of
4.5V to 18V, the LTM4652 supports two outputs with an
output voltage range of 0.6V to 7.5V, each set by a single
external resistor. Its high efficiency design delivers up to
±25A continuous current for each output. Only a few input
and output capacitors are needed. Adjustable control loop
compensation allows for fast transient response to minimize output capacitance when powering FPGAs, ASICs,
and processors.
n
APPLICATIONS
Fault protection features include input and output overvoltage and bidirectional overcurrent protection. The
LTM4652 is offered in a 16mm × 16mm × 4.92mm
BGA package.
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. Patents, including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6304066
and 6580258. Other patents pending.
Test and Measurement Instrumentation
n Telecom and Networking Equipment
n Industrial Equipment
n
TYPICAL APPLICATION
±50A, 3.3V Bidirectional Output DC/DC µModule Regulator
with Input Overvoltage Protection
10k
VIN
4.5V TO 18V
4.7µF
22µF
25V
×4
VIN
PGOOD1
VINOVP
TRACK1
TRACK2
f SET
140k
DIFFOUT
VFB1
LTM4652
98
PGOOD2
VOUT1
VOUTS1
845k
0.1µF
VFB2
100µF
6.3V
+
470µF
6.3V
VOUT
3.3V
±50A
13.3k
COMP1
RTH
CTH
PINS UNUSED IN
THIS APPLICATION:
CLKOUT, EXTVCC,
SW1, SW2, VOUTS2,
TEMP+, TEMP–
INTVCC
PGOOD
96
EFFICIENCY (%)
INTVCC
3.3VOUT Efficiency vs IOUT
100
94
92
90
88
86
84
COMP2
RUN1
VOUT2
RUN2
PHASMD
DIFFN
DIFFP
SGND
100µF
6.3V
+
GND MODE_PLLIN
4652 TA01a
470µF
6.3V
82
5VIN
12VIN
80
–50 –40 –30 –20 –10 0 10 20 30 40 50
OUTPUT CURRENT (A)
4652 TA01b
Rev. 0
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1
LTM4652
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
VIN.............................................................. –0.3V to 20V
PGOOD1, PGOOD2, RUN1, RUN2,
INTVCC, EXTVCC........................................... –0.3V to 6V
MODE_PLLIN, fSET, TRACK1, TRACK2,
DIFFOUT, PHASMD................................ –0.3V to INTVCC
VOUT1, VOUT2, VOUTS1, VOUTS2 (Note 5)......... –0.3V to 8V
DIFFP, DIFFN, VINOVP............................ –0.3V to INTVCC
COMP1, COMP2, VFB1, VFB2 (Note 5)......... –0.3V to 2.7V
INTVCC Peak Output Current...................................50mA
Internal Operating Temperature Range
(Note 2)................................................... –40°C to 125°C
Storage Temperature Range................... –55°C to 125°C
Peak Package Body Temperature........................... 245°C
M
VIN
L
VIN
VIN
K
GND
+
TEMP
EXTVCC
J
VINOVP
H
SW1
–
INTVCC
TEMP
PHASMD CLKOUT
SW2
PGOOD2 PGOOD1
G
MODE_
PLLIN RUN1
SGND
DIFFOUT
RUN2
F
GND
TRACK1 COMP1 COMP2 DIFFP
DIFFN
E
VFB1
SGND
VOUTS1
fSET
VFB2
GND
TRACK2
D
SGND VOUTS2
C
B
VOUT1
GND
VOUT2
A
1
2
3
4
5
6
7
8
9
10
11
12
BGA PACKAGE
144-LEAD (16mm × 16mm × 4.92mm)
TJMAX = 125°C, θJA = 7°C/W, θJCtop = 5.8°C/W, θJCbot = 1.7°C/W, WEIGHT = 3.8 GRAMS
NOTES: 1) θ VALUES ARE DETERMINED BY SIMULATION PER JESD51 CONDITIONS.
2) θJA VALUE IS OBTAINED WITH DEMO BOARD.
3) REFER TO APPLICATION INFORMATION SECTION FOR LAB MEASUREMENT
AND DERATING INFORMATION.
ORDER INFORMATION
PART MARKING*
PART NUMBER
LTM4652EY#PBF
LTM4652IY#PBF
PAD OR BALL FINISH
SAC305 (RoHS)
DEVICE
FINISH CODE
PACKAGE TYPE
MSL RATING
TEMPERATURE
RANGE (NOTE 2)
LTM4652Y
e1
BGA
4
–40°C to 125°C
• Contact the factory for parts specified with wider operating temperature ranges.
*Device temperature grade is indicated by a label on the shipping container.
Pad or ball finish code is per IPC/JEDEC J-STD-609.
2
• Recommended LGA and BGA PCB Assembly and
Manufacturing Procedures
• LGA and BGA Package and Tray Drawings
Rev. 0
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LTM4652
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified internal
operating temperature range. Specified as each individual output channel (Note 3). TA = 25°C (Note 2), VIN = 12V, VRUN1, VRUN2 at 5V
and IOUT1, IOUT2 at 0A unless otherwise noted. Per the typical application in Figure 31.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
VIN
Input DC Voltage
l
VOUT
Output Voltage
l
0.6
7.5
V
VOUT1(DC), VOUT2(DC)
Output Voltage, Total DC Variation
with Line and Load (Note 7)
CIN = 22µF ×3, COUT = 100µF ×1 Ceramic,
470µF POSCAP, VIN = 4.5V to 18V,
VOUT = 1.2V, IOUT = 0A to ±25A
l
1.182
1.2
1.218
V
VRUN1, VRUN2
RUN Pin Off Threshold
RUN Rising
1.1
1.22
1.4
V
VRUN1HYS , VRUN2HYS
RUN Pin On Hysteresis
VVINOVP
VINOVP Pin OVP Inception Threshold
VOVP_HYS
VINOVP Pin OVP Inception Hysteresis
IINRUSH(VIN)
Input Inrush Current at Start-Up
IQ(VIN)
IS(VIN)
4.5
MAX
18
UNITS
V
Input Specifications
135
VINOVP Rising
1.1
1.22
mV
1.4
V
10
mV
IOUT = 0A, CIN = 22µF ×3, CSS = 0.01µF,
COUT = 100µF ×3, VOUT1 = 1.2V, VOUT2 = 1.2V,
VIN = 12V
1
A
Input Supply Bias Current (Both
Channels On)
VIN = 12V, VOUT = 1.2V, Pulse-Skipping Mode
VIN = 12V, VOUT= 1.2V, Switching Continuous
Shutdown, RUN = 0, VIN = 12V
22
135
35
mA
mA
µA
Input Supply Current
VIN = 4.5V, VOUT = 1.2V, IOUT = 25A
VIN = 12V, VOUT = 1.2V, IOUT = 25A
VIN = 4.5V, VOUT = 1.2V, IOUT = –25A
VIN = 12V, VOUT = 1.2V, IOUT = –25A
8.0
3.0
–5.2
–1.9
A
A
A
A
Output Specifications
IOUT1(DC), IOUT2(DC)
Output Continuous Current Range
VIN = 12V, VOUT = 1.2V (Note 6)
25
A
ΔVOUT1(LINE)/VOUT1
ΔVOUT2(LINE)/VOUT2
Line Regulation Accuracy
For Each Output, VOUT = 1.2V, IOUT = 0A,
VIN from 4.5V to 18V
l
0.02
0.1
%/V
ΔVOUT1/VOUT1
ΔVOUT2/VOUT2
Load Regulation Accuracy
For Each Output, VIN = 12V, VOUT = 1.2V,
IOUT from 0A to ±25A
l
0.2
0.75
%
VOUT1(AC), VOUT2(AC)
Output Ripple Voltage
For Each Output, VIN = 12V, VOUT = 1.2V,
Frequency = 450kHz, IOUT = 0A, COUT =
100µF ×3 Ceramic, 470µF POSCAP
15
mVP-P
fSW (Each Channel)
Output Ripple Voltage Frequency
VIN = 12V, VOUT = 1.2V, fSET = 1.2V (Note 4)
500
kHz
fSYNC (Each Channel)
Phase-Locked Loop Synchronization
Capture Range
(Note 4)
∆VOUTSTART
(Each Channel)
Turn-On Overshoot
COUT = 100µF ×3 Ceramic, 470µF POSCAP,
VIN = 12V , VOUT = 1.2V, IOUT = 0A
10
mV
tSTART
(Each Channel)
Turn-On Time
COUT = 100µF ×4 Ceramic,
VIN = 12V, No Load, TRACK with 0.01µF to GND
5
ms
∆VOUT(LS)
(Each Channel)
Peak Deviation for Dynamic Load
Load: 0% to 50% to 0% of Full Load,
COUT = 100µF ×3 Ceramic, 470µF POSCAP,
VIN = 12V, VOUT = 1.2V (Note 8)
30
mV
tSETTLE
(Each Channel)
Settling Time for Dynamic Load Step
Load: 0% to 50% to 0% of Full Load,
VIN = 12V, COUT = 100µF ×3 Ceramic,
470µF POSCAP (Note 8)
20
µs
VIN = 12V, VOUT = 1.2V
35
A
IOUT(PK) (Each Channel) Output Current Limit
–25
400
780
kHz
Rev. 0
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3
LTM4652
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified internal
operating temperature range. Specified as each individual output channel (Note 3). TA = 25°C (Note 2), VIN = 12V, VRUN1, VRUN2 at 5V
and IOUT1, IOUT2 at 0A unless otherwise noted. Per the typical application in Figure 31.
SYMBOL
PARAMETER
CONDITIONS
Voltage at VFB Pins
IOUT = 0A, VOUT = 1.2V
MIN
TYP
MAX
UNITS
0.594
0.600
0.606
V
–5
–30
nA
0.64
0.66
0.68
V
1
1.25
1.5
µA
Control Section
VFB1, VFB2
l
(Note 5)
IFB
VOVL
Feedback Overvoltage Lockout
ITRACK1, ITRACK2
Track Pin Soft-Start Pull-Up Current
UVLO
Undervoltage Lockout (Falling)
l
TRACK1, TRACK2 Start at 0V
UVLO Hysteresis
tON(MIN)
Minimum On-Time
(Note 5)
RFBHI1, RFBHI2
Resistor Between VOUTS1, VOUTS2 and
VFB1, VFB2 Pins for Each Output
60.05
VPGOOD1, VPGOOD2 Low
PGOOD Voltage Low
IPGOOD = 2mA
IPGOOD
PGOOD Leakage Current
VPGOOD = 5V
VPGOOD
PGOOD Trip Level
VFB with Respect to Set Output Voltage
VFB Ramping Negative
VFB Ramping Positive
Internal VCC Voltage
6V < VIN < 18V
3.4
V
0.6
V
90
ns
60.4
60.75
0.1
0.3
V
±5
µA
–10
10
kΩ
%
%
INTVCC Linear Regulator
VINTVCC
VINTVCC Load Regulation INTVCC Load Regulation
4.75
5
5.2
V
0.5
2
%
4.5
4.7
ICC = 0mA to 50mA
VEXTVCC
EXTVCC Switchover Voltage
EXTVCC Ramping Positive
VEXTVCC(DROP)
EXTVCC Dropout
ICC = 20mA, VEXTVCC = 5V
VEXTVCC(HYST)
EXTVCC Hysteresis
50
V
100
220
mV
mV
Oscillator
Frequency Nominal
Nominal Frequency
fSET = 1.2V
Frequency Low
Lowest Frequency
fSET = 0.93V
fSET = 0V (Note 5)
fSET > 2.4V, Up to INTVCC
Frequency High
Highest Frequency
fSET
Frequency Set Current
RMODE_PLLIN
MODE_PLLIN Input Resistance
CLKOUT
Phase (Relative to VOUT1)
CLK High
CLK Low
Clock High Output Voltage
Clock Low Output Voltage
450
500
550
400
250
kHz
kHz
780
8.5
PHASMD = GND
PHASMD = Float
PHASMD = INTVCC
9.5
kHz
kHz
11
µA
250
kΩ
60
90
120
Deg
Deg
Deg
2
0.4
V
V
Differential Amplifier
AV Differential Amp
Gain
RIN
Input Resistance
Measured at DIFFP Input
VOS
Input Offset Voltage
VDIFFP = VDIFFOUT = 1.5V, IDIFFOUT = 100µA
PSRR Differential Amp
Power Supply Rejection Ratio
4.5V < VIN < 18V
ICL
Maximum Output Current
4
1
V/V
80
kΩ
3
mV
90
dB
3
mA
Rev. 0
For more information www.analog.com
LTM4652
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified internal
operating temperature range. Specified as each individual output channel (Note 3). TA = 25°C (Note 2), VIN = 12V, VRUN1, VRUN2 at 5V
and IOUT1, IOUT2 at 0A unless otherwise noted. Per the typical application in Figure 31.
SYMBOL
PARAMETER
CONDITIONS
IDIFFOUT = 300µA
VOUT(MAX)
Maximum Output Voltage
GBW
Gain Bandwidth Product
�VTEMP
Diode Connected PNP
TC
Temperature Coefficient
η
Ideality Factor
MIN
TYP
MAX
UNITS
INTVCC – 1.4
V
3
ITEMP+ = 100µA, ITEMP– = –100µA
l
MHz
0.6
V
–2.2
mV/C
1.004
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTM4652 is tested under pulsed-load conditions such that
TJ ≈ TA. The LTM4652E is guaranteed to meet performance specifications
over the 0°C to 125°C internal operating temperature range. Specifications
over the –40°C to 125°C internal operating temperature range are assured
by design, characterization and correlation with statistical process
controls. The LTM4652I is guaranteed to meet specifications over the
full –40°C to 125°C internal operating temperature range. Note that the
maximum ambient temperature consistent with these specifications
is determined by specific operating conditions in conjunction
with board layout, the rated package thermal resistance and other
environmental factors.
Note 3: Two outputs are tested separately and the same testing condition
is applied to each output.
Note 4: The LTM4652 device is designed to operate best from 400kHz
to 780kHz. For some applications such as 1VOUT, operation at 300kHz is
acceptable—but not ATE-tested in production.
Note 5: These parameters are tested at wafer sort.
Note 6: See output current derating curve for different ambient
temperature.
Note 7: Total DC output voltage error includes all errors over
temperature—reference, line and load regulation as well as the tolerance
of the integrated top feedback resistor.
Note 8: Transient response and load step performance are layout
dependent and thus application-specific. Typical values are
reported from lab Demo Board evaluation. Evaluation in application
demonstrates capability.
Rev. 0
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5
LTM4652
TYPICAL PERFORMANCE CHARACTERISTICS
Pulse-Skipping Mode Efficiency
VIN = 12V, VOUT = 1.2V,
fS = 400kHz, Outputs Paralleled
Efficiency vs Output Current,
VIN = 12V, Outputs Paralleled
100
100
98
98
90
96
96
80
94
94
70
92
90
88
86
EFFICIENCY (%)
100
EFFICIENCY (%)
EFFICIENCY (%)
Efficiency vs Output Current,
VIN = 5V, Outputs Paralleled
TA = 25°C, unless otherwise noted.
92
90
88
86
60
50
40
30
84
84
20
82
82
10
80
–50 –40 –30 –20 –10 0 10 20 30 40 50
LOAD CURRENT (A)
80
–50 –40 –30 –20 –10 0 10 20 30 40 50
LOAD CURRENT (A)
4652 G01
1.0VOUT, 300kHz
1.2VOUT, 400kHz
1.5VOUT, 400kHz
0
0.001
4652 G03
4652 G02
1.0VOUT, 300kHz
1.2VOUT, 400kHz
1.5VOUT, 400kHz
1.8VOUT, 500kHz
1.8VOUT, 500kHz
2.5VOUT, 500kHz
3.3VOUT, 600kHz
1V Dual Phase Single Output
Load Transient Response
(Ceramic Output Capacitor Only)
2.5VOUT, 500kHz
3.3VOUT, 600kHz
5.0VOUT, 750kHz
PULSE-SKIPPING MODE, SOURCING CURRENT
FORCED CONTINUOUS MODE, SOURCING CURRENT
FORCED CONTINUOUS MODE, SINKING CURRENT
1.2V Dual Phase Single Output
Load Transient Response
(Ceramic Output Capacitor Only)
1.5V Dual Phase Single Output
Load Transient Response
(Ceramic Output Capacitor Only)
VOUT (AC)
50mV/DIV
VOUT (AC)
50mV/DIV
VOUT (AC)
50mV/DIV
LOAD STEP
10A/DIV
LOAD STEP
10A/DIV
LOAD STEP
10A/DIV
100µs/DIV
12VIN, 1VOUT, 300kHz
25%, 12.5A LOAD STEP-UP AND
STEP-DOWN, 10A/μs SLEW RATE
COUT = 220μF ×8 CERAMIC CAP
RTH = 3.32k, CTH = 6800pF, CFF = 68pF
6
4652 G04
0.01
0.1
1
10
100
MAGNITUDE OF OUTPUT CURRENT (A)
100µs/DIV
12VIN, 1.2VOUT, 400kHz
25%, 12.5A LOAD STEP-UP AND
STEP-DOWN, 10A/μs SLEW RATE
COUT = 220μF ×8 CERAMIC CAP
RTH = 3.32k, CTH = 6800pF, CFF = 68pF
4652 G05
100µs/DIV
4652 G06
12VIN, 1.5VOUT, 400kHz
25%, 12.5A LOAD STEP-UP AND
STEP-DOWN, 10A/μs SLEW RATE
COUT = 220μF ×8 CERAMIC CAP
RTH = 3.32k, CTH = 6800pF, CFF = 68pF
Rev. 0
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LTM4652
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
2.5V Dual Phase Single Output
Load Transient Response
(Ceramic Output Capacitor Only)
1.8V Dual Phase Single Output
Load Transient Response
(Ceramic Output Capacitor Only)
3.3V Dual Phase Single Output
Load Transient Response
(Ceramic Output Capacitor Only)
VOUT (AC)
50mV/DIV
VOUT (AC)
50mV/DIV
VOUT (AC)
50mV/DIV
LOAD STEP
10A/DIV
LOAD STEP
10A/DIV
LOAD STEP
10A/DIV
100µs/DIV
4652 G07
100µs/DIV
4652 G08
100µs/DIV
4652 G09
12VIN, 1.8VOUT, 500kHz
25%, 12.5A LOAD STEP-UP AND
STEP-DOWN, 10A/μs SLEW RATE
COUT = 220μF ×8 CERAMIC CAP
RTH = 3.32k, CTH = 6800pF, CFF = 68pF
12VIN, 2.5VOUT, 500kHz
25%, 12.5A LOAD STEP-UP AND
STEP-DOWN, 10A/μs SLEW RATE
COUT = 220μF ×8 CERAMIC CAP
RTH = 3.32k, CTH = 6800pF, CFF = 68pF
12VIN, 3.3VOUT, 600kHz
25%, 12.5A LOAD STEP-UP AND
STEP-DOWN, 10A/μs SLEW RATE
COUT = 220μF ×8 CERAMIC CAP
RTH = 3.32k, CTH = 6800pF, CFF = 68pF
1V Dual Phase Single Output
Load Transient Response
(Bulk Output Capacitor)
1.2V Dual Phase Single Output
Load Transient Response
(Bulk Output Capacitor)
1.5V Dual Phase Single Output
Load Transient Response
(Bulk Output Capacitor)
VOUT (AC)
50mV/DIV
VOUT (AC)
50mV/DIV
VOUT (AC)
50mV/DIV
LOAD STEP
10A/DIV
LOAD STEP
10A/DIV
LOAD STEP
10A/DIV
100µs/DIV
12VIN, 1VOUT, 300kHz
25%, 12.5A LOAD STEP-UP AND
STEP-DOWN, 10A/μs SLEW RATE
COUT = 220μF ×4 CERAMIC CAP
+ 470μF ×2, 2.5V SPCAP
CTHP = 10pF, RTH = 4.65k
CTH = 4700pF, CFF = 10pF
4652 G10
100µs/DIV
12VIN, 1.2VOUT, 400kHz
25%, 12.5A LOAD STEP-UP AND
STEP-DOWN, 10A/μs SLEW RATE
COUT = 220μF ×4 CERAMIC CAP
+ 470μF ×2, 2.5V SPCAP
CTHP = 10pF, RTH = 4.65k
CTH = 4700pF, CFF = 10pF
4652 G11
100µs/DIV
4652 G12
12VIN, 1.5VOUT, 400kHz
25%, 12.5A LOAD STEP-UP AND
STEP-DOWN, 10A/μs SLEW RATE
COUT = 220μF ×4 CERAMIC CAP
+ 470μF ×2, 2.5V SPCAP
CTHP = 10pF, RTH = 4.65k
CTH = 4700pF, CFF = 10pF
Rev. 0
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7
LTM4652
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
2.5V Dual Phase Single Output
Load Transient Response
(Bulk Output Capacitor)
1.8V Dual Phase Single Output
Load Transient Response
(Bulk Output Capacitor)
VOUT (AC)
50mV/DIV
VOUT (AC)
50mV/DIV
LOAD STEP
10A/DIV
LOAD STEP
10A/DIV
100µs/DIV
4652 G13
100µs/DIV
12VIN, 1.8VOUT, 500kHz
25%, 12.5A LOAD STEP-UP AND
STEP-DOWN, 10A/μs SLEW RATE
COUT = 220μF ×4 CERAMIC CAP
+ 470μF ×2, 2.5V SPCAP
CTHP = 10pF, RTH = 4.65k
CTH = 4700pF, CFF = 10pF
12VIN, 2.5VOUT, 500kHz
25%, 12.5A LOAD STEP-UP AND
STEP-DOWN, 10A/μs SLEW RATE
COUT = 220μF ×4 CERAMIC CAP
+ 470μF ×2, 2.5V SPCAP
CTHP = 10pF, RTH = 4.65k
CTH = 4700pF, CFF = 10pF
3.3V Dual Phase Single Output
Load Transient Response
(Bulk Output Capacitor)
5V Dual Phase Single Output
Load Transient Response
(Bulk Output Capacitor)
VOUT (AC)
50mV/DIV
VOUT (AC)
50mV/DIV
LOAD STEP
10A/DIV
LOAD STEP
10A/DIV
100µs/DIV
4652 G15
4652 G16
12VIN, 5VOUT, 750kHz
25%, 12.5A LOAD STEP-UP AND
STEP-DOWN, 10A/μs SLEW RATE
COUT = 220μF ×4 CERAMIC CAP
+ 470μF ×2, 6.3V POSCAP
CTHP = 10pF, RTH = 9.09k
CTH = 4700pF, CFF = NONE
12VIN, 3.3VOUT, 600kHz
25%, 12.5A LOAD STEP-UP AND
STEP-DOWN, 10A/μs SLEW RATE
COUT = 220μF ×4 CERAMIC CAP
+ 470μF ×2, 6.3V POSCAP
CTHP = 10pF, RTH = 9.09k
CTH = 4700pF, CFF = NONE
8
100µs/DIV
4652 G14
Rev. 0
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LTM4652
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
Single Phase Start-Up with
25A Load
Single Phase Start-Up with
No Load
SW
10V/DIV
SW
10V/DIV
VOUT
0.5V/DIV
VOUT
0.5V/DIV
INPUT
CURRENT
0.2A/DIV
INPUT
CURRENT
2A/DIV
20ms/DIV
4652 G17
20ms/DIV
12VIN, 1.2VOUT, 400kHz
COUT = 470μF ×2
SPCAP + 100µF ×4 CERAMIC CAP
CSS = 0.1µF
12VIN, 1.2VOUT, 400kHz
COUT = 470μF ×2
SPCAP + 100µF ×4 CERAMIC CAP
CSS = 0.1µF
Single Phase Short-Circuit
Protection with No Load
Single Phase Short-Circuit
Protection with 25A Load
SW
10V/DIV
SW
10V/DIV
VOUT
0.5V/DIV
VOUT
0.5V/DIV
INPUT
CURRENT
5A/DIV
INPUT
CURRENT
2A/DIV
100μs/DIV
4652 G19
12VIN, 1.2VOUT, 400kHz
COUT = 470μF ×2
SPCAP + 100µF ×4 CERAMIC CAP
100μs/DIV
4652 G18
4652 G20
12VIN, 1.2VOUT, 400kHz
COUT = 470μF ×2
SPCAP + 100µF ×4 CERAMIC CAP
Rev. 0
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9
LTM4652
PIN FUNCTIONS
(Recommended to use test points to monitor signal pin connections.)
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
VOUT1 (Pins A1–A5, B1–B5, C1–C4): Power Output Pins.
Apply output load between these pins and GND pins.
Recommend placing output decoupling capacitance
directly between these pins and GND pins. Review Table 6.
GND (Pins A6–A7, B6–B7, D1–D4, D9–D12, E1–E4, E10–
E12, F1–F3, F10–F12, G1, G3, G10, G12, H1–H4, H7, H9–
H12, J1, J5, J8, J12, K1, K5–K8, K12, L1, L12, M1, M12):
Power Ground Pins for Both Input and Output Returns.
VOUT2 (Pins A8–A12, B8–B12, C9–C12): Power Output
Pins. Apply output load between these pins and GND
pins. Recommend placing output decoupling capacitance
directly between these pins and GND pins. Review Table 6.
VOUTS1, VOUTS2 (Pins C5, C8): This pin is connected
to the top of the internal top feedback resistor for each
output. The pin can be directly connected to its specific
output, or connected to DIFFOUT when the remote sense
amplifier is used. In paralleling modules, one of the VOUTS
pins is connected to the DIFFOUT pin in remote sensing or
directly to VOUT with no remote sensing. It is very important to connect these pins to either the DIFFOUT or VOUT
since this is the feedback path, and cannot be left open.
See the Applications Information section.
fSET (Pin C6): Frequency Set Pin. A 9.5µA current is
sourced from this pin. A resistor from this pin to ground
sets a voltage that in turn programs the operating frequency. Alternatively, this pin can be driven with a DC
voltage that can set the operating frequency. See the
Applications Information section.
SGND (Pins C7, D6, G6–G7, F6–F7): Signal Ground Pin.
Return ground path for all analog and low power circuitry.
Tie a single connection to the output capacitor GND in the
application. See layout guidelines in Figure 30.
VFB1, VFB2 (Pins D5, D7): The Negative Input of the
Error Amplifier for Each Channel. Internally, this pin is
connected to VOUTS1 or VOUTS2 with a 60.4k precision
resistor. Different output voltages can be programmed
with an additional resistor between VFB and GND pins. In
10
PolyPhase® operation, tying the VFB pins together allows
for parallel operation. See the Applications Information
section for details. Do not drive this pin.
TRACK1, TRACK2 (Pins E5, D8): Output Voltage Tracking
Pin and Soft-Start Inputs. Each channel has a 1.25µA
pull-up current source. When one channel is configured to
be master of the two channels, then a capacitor from this
pin to ground will set a soft-start ramp rate. The remaining
channel can be set up as the slave, and have the master’s
output applied through a voltage divider to the slave output’s TRACK pin. This voltage divider is equal to the slave
output’s feedback divider for coincidental tracking. See
the Applications Information section.
COMP1, COMP2 (Pins E6, E7): Current control threshold
and error amplifier compensation point for each channel. The current comparator threshold increases with this
control voltage. COMP pin internal has 10pF filter cap to
SGND. An external RC filter circuit is required for control
loop compensation. See Applications Information section.
Tie the COMP pins together for parallel operation. Do not
drive this pin.
DIFFP (Pin E8): Positive input of the remote sense amplifier. This pin is connected to the remote sense point of the
output voltage. Diffamp can be used for ≤3.3V outputs.
See the Applications Information section.
DIFFN (Pin E9): Negative input of the remote sense amplifier. This pin is connected to the remote sense point of the
output GND. Diffamp can be used for ≤3.3V outputs. See
the Applications Information section.
MODE_PLLIN (Pin F4): Forced Continuous Mode or PulseSkipping Mode Selection Pin and External Synchronization
Input to Phase Detector Pin. Connect this pin to SGND to
force both channels into forced continuous mode of operation. Connect to INTVCC to enable pulse-skipping mode
of operation. A clock on the pin will force both channels
into continuous mode of operation and synchronized to
the external clock applied to this pin.
Note that this module is designed to conduct bidirectional
output current. When pulse-skipping mode is selected,
there is no way for the control loop to command instantaneous inductor current below 0A except by deliberately
Rev. 0
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LTM4652
PIN FUNCTIONS
(Recommended to use test points to monitor signal pin connections.)
allowing the output voltage to rise high enough (~10%
above nominal regulation) to induce an output overvoltage response. Transient and sustained operation in this
manner is strongly not recommended.
Thus, in applications where transient and/or sustained
negative (sinking) output current is expected, the
LTM4652 must be operated in forced continuous mode.
RUN1, RUN2 (Pins F5, F9): Run Control Pin. A voltage
above 1.22V will turn on each channel in the module. A
voltage below 1.085V (135mV hysteresis, typ.) on the
RUN pin will turn off the related channel. Each RUN pin
has a 1µA pull-up current, once the RUN pin reaches
1.22V an additional 4.5µA pull-up current is added to
this pin.
DIFFOUT (Pin F8): Internal Remote Sense Amplifier
Output. Connect this pin to VOUTS1 or VOUTS2 depending on which output is using remote sense. In parallel
operation connect one of the VOUTS pin to DIFFOUT for
remote sensing.
SW1, SW2 (Pins G2, G11): Switching node of each channel that is used for testing purposes. Also an R-C snubber
network can be applied to reduce or eliminate switch node
ringing, or otherwise leave floating. See the Applications
Information section.
PHASMD (Pin G4): Connect this pin to SGND, INTVCC,
or floating this pin to select the phase of CLKOUT to 60
degrees, 120 degrees, and 90 degrees respectively.
CLKOUT (Pin G5): Clock output with phase control using
the PHASMD pin to enable multiphase operation between
devices. See the Applications Information section.
PGOOD1, PGOOD2 (Pins G9, G8): Output Voltage Power
Good Indicator. Open drain logic output that is pulled to
ground when the output voltage is not within ±10% of
the regulation point.
VINOVP (Pin H5): VIN Overvoltage Protection (OVP)
Comparator Input. Internally, this pin connects to SGND
through a 60.4k resistor. If desired, apply resistor RVINOVP
from VIN to VINOVP to set VIN(OVP), the VIN overvoltage
inception threshold. VIN(OVP) is given by Equation 1.
VIN(OVP) = 1.22V • 1 +
RVINOVP
60.4k
(1)
See Figure 1 and the Applications Information section.
When VINOVP is detected (VVINOVP > 1.22V), all power
MOSFETs in both channels are turned off and remain off
until the module is restarted. The module can be restarted
by either cycling the RUN pins below their RUN thresholds
or cycling the TRACK pins to SGND. Leave VINOVP open
circuit or connect to SGND when this feature is not used.
TEMP– (Pin H6): Temperature Monitor, Negative Terminal.
See TEMP+.
INTVCC (Pin H8): Internal 5V Regulator Output. The control circuits and internal gate drivers are powered from
this voltage. Decouple this pin to PGND with a 4.7µF low
ESR tantalum or ceramic. INTVCC is activated when either
RUN1 or RUN2 is activated.
TEMP+ (Pin J6): Temperature Monitor, Positive Terminal.
An internal diode-configured PNP transistor connected
between TEMP+ and TEMP– pins. See the Applications
Information section.
EXTVCC (Pin J7): External power input that is enabled
through a switch to INTVCC whenever EXTVCC is greater
than 4.7V. Do not exceed 6V on this input, and connect
this pin to VIN when operating VIN on 5V. An efficiency
increase will occur, corresponding to a power loss reduction of (VIN – INTVCC) multiplied by power MOSFET driver
current. Typical current requirement is 30mA. VIN must
be applied before EXTVCC , and EXTVCC must be removed
before VIN.
VIN (Pins M2–M11, L2–L11, J2–J4, J9–J11, K2–K4,
K9–K11): Power Input Pins. Apply input voltage between
these pins and GND pins. Recommend placing input
decoupling capacitance directly between VIN pins and
GND pins.
Heat Sink (Top Exposed Metal): The top exposed metal
is electrically unconnected.
Rev. 0
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11
LTM4652
SIMPLIFIED BLOCK DIAGRAM
PGOOD1
TRACK1
VIN
PGOOD1
SS CAP
DIODE-CONNECTED PNP
TEMPERATURE SENSOR
TEMP+
TEMP–
MTOP1
RUN1
MODE_PLLIN
1.22V
PHASEMD
+
–
SW1
0.22µH
VOUT1
1µF
MBOT1
COMP1
CTH1
CTHP1
10pF
60.4k
TRACK2
VIN
POWER
CONTROL
INTVCC
4.7µF
RVINOVP
COUT1
VFB1
RFB1
40.2k
PGOOD2
VIN
EXTVCC
CIN3
22µF
25V
1µF
GND
VINOVP
60.4k
+
GND
VOUT1
1.5V
±25A
VOUTS1
SGND
SS CAP
CIN2
22µF
25V
GND
CLKOUT
RTH1
CIN1
22µF
25V
1µF
VIN
4.5V TO
18V
470pF
1.22V
+
–
1.22V
+
–
RUN2
COMP2
MTOP2
CIN4
22µF
25V
SW2
0.22µH
MBOT2
VOUT2
1µF
GND
+
VOUT2
3.3V
±25A
COUT2
VOUTS2
10pF
CTHP2
RTH2
CTH2
RFSET
SGND
60.4k
+ –
fSET
VFB2
RFB2
13.3k
INTERNAL
FILTER
DIFFOUT
DIFFN
DIFFP
4652 BD
Figure 1. Simplified LTM4652 Block Diagram
DECOUPLING REQUIREMENTS
TA = 25°C. Use Figure 1 configuration.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
CIN1, CIN2
CIN3, CIN4
External Input Capacitor Requirement
(VIN1 = 4.5V to 18V, VOUT1 = 1.2V)
(VIN2 = 4.5V to 18V, VOUT2 = 3.3V)
IOUT1 = ±25A
IOUT2 = ±25A
22
22
66
66
µF
µF
COUT1
COUT2
External Output Capacitor Requirement
(VIN1 = 4.5V to 18V, VOUT1 = 1.2V)
(VIN2 = 4.5V to 18V, VOUT2 = 3.3V)
IOUT1 = ±25A
IOUT2 = ±25A
300
300
600
600
µF
µF
12
MAX
UNITS
Rev. 0
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LTM4652
OPERATION
Power Module Description
The LTM4652 is a bidirectional dual-output standalone
nonisolated switching mode DC/DC power supply with
±1.5% total DC output error over line, load and temperature
variation. It can provide two ±25A outputs or single ±50A
output with few external input and output capacitors and
setup components. This module provides precisely regulated output voltages programmable via external resistors
from 0.6VDC to 7.5VDC over 4.5V to 18V input voltages.
The typical application schematic is shown in Figure 31.
The LTM4652 has dual integrated constant-frequency
current mode regulators and built-in power MOSFET
devices with fast switching speed. The typical switching
frequency is 300kHz* to 780kHz depending on different
input and output conditions. For switching-noise sensitive applications, it can be externally synchronized from
300kHz* to 780kHz. A resistor can be used to program a
free run frequency on the fSET pin. See the Applications
Information section.
With current mode control, multiple LTM4652s can be
easily paralleled to provide up to ±300A current with
excellent current sharing. Also, with current mode control,
the LTM4652 module is able to achieve sufficient stability
margins and a very fast ±3% output transient response
with a minimum number of output capacitors, even with
all ceramic output capacitors. This makes LTM4652 the
best candidate when powering FPGAs, ASICs and processors in terms of DC accuracy, AC transient response,
high output current and accuracy current sharing. See
Applications Information section.
Current mode control provides cycle-by-cycle fast current
limit and foldback current limit in an overcurrent condition. Internal overvoltage and undervoltage comparators
pull the open-drain PGOOD outputs low if the output
feedback voltage exits a ±10% window around the regulation point. As the output voltage exceeds 10% above
regulation, the bottom MOSFET will turn on to clamp the
output voltage. The top MOSFET will be turned off. This
overvoltage protection is feedback voltage referred.
If desired, latch-off input overvoltage protection can
be implemented by connecting an appropriate resistor,
*Note that synchronization below 400kHz is not tested in ATE.
RVINOVP, from VIN to VINOVP. When the VINOVP pin
exceeds 1.22V, switching action ceases, i.e., both the top
MOSFET and bottom MOSFET are latched off. The module
can be restarted by cycling the RUN pins below their RUN
thresholds, or by cycling the TRACK pins to SGND or by
cycling VIN altogether.
Pulling the RUN pins below 1.1V forces the regulators
into a shutdown state, by turning off both MOSFETs.
The TRACK pins are used for programming the output
voltage ramp and voltage tracking during start-up or
used for soft-starting the regulator. See the Applications
Information section.
The LTM4652 has a built-in 10pF high frequency filter
cap from COMP to SGND for each channel. An external RC filtering circuit is required to achieve fast Type II
control loop compensation. Table 6 provides a guide line
for input, output capacitances and R-C values on COMP
pin for several operating conditions. The Analog Devices
µModule Power Design Tool (LTpowerCAD®) provides for
transient and stability analysis. The VFB pin is used to program the output voltage with a single external resistor to
ground. A differential remote sense amplifier is available
for sensing the output voltage accurately on one of the
outputs at the load point, or in parallel operation sensing
the output voltage at the load point.
High efficiency at light loads can be accomplished with
selectable pulse-skipping operation using the MODE_
PLLIN pin. This light load feature will accommodate battery operation. Efficiency graphs are provided for light load
operation in the Typical Performance Characteristics section. See the Applications Information section for details.
A general purpose diode-configured PNP temperature
sensor is included inside the module to monitor the temperature of the module. See the Applications Information
section for details.
The switch pins, SW1 and SW2, are available for functional operation monitoring and a resistor-capacitor
snubber circuit can be careful placed on the switch pin
to ground to dampen any high frequency ringing on the
transition edges. See the Applications Information section
for details.
Rev. 0
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13
LTM4652
APPLICATIONS INFORMATION
The typical LTM4652 application circuit is shown in
Figure 31. External component selection is primarily
determined by the maximum load current and output
voltage. Refer to Table 6 for specific external capacitor
requirements for a 25% or a 50% load step application.
Output Total DC Accuracy and AC Transient
Performance
For example, in an FPGA core voltage application, for a 12V
input, 1.0V output at 100A design, a total overall ±3% total
voltage regulation window is required in responding to a
25% load step transient. Figure 3 illustrates the benefit of
overall output capacitor reduction versus improved total
DC accuracy by using 100µF ceramic output capacitors.
In modern ASIC and FPGA power supply designs, a tight
total voltage regulation window, ±3% for example, is
required of the supply powering the core and periphery. To
meet this requirement, the supply’s DC voltage variance
plus any AC voltage variation which may occur during any
load step transient must fall within this allowed window.
The DC voltage variance is determined by the accuracies
of the supply’s reference voltage, resistor divider, load
regulation and line regulation over the operating temperature range. The AC voltage variance is determined by the
supply’s output voltage overshoot and undershoots in
response to a load transient condition for a given output
capacitor network.
Figure 2 shows a typical load step transient response
waveform together with DC voltage accuracy variance. For
a given allowable voltage regulation window, a tighter DC
voltage accuracy allows more margin for the AC variation
due to a load transient response. This increased margin
for AC variation allows for a reduction in the total output capacitance required to meet the regulation window
requirement. This allows for a reduced total solution cost
and footprint area.
LOAD STEP
REQUIRED OUTPUT CAPACITANCE (µF)
9000
8000
8000
7000
6000
5400
5000
4000
3700
4000
4500
3000
2000
1000
0
0.8
1.2
1.0
1.5
TOTAL DC ACCURACY (%)
2.0
4652 F03
Figure 3. Overall Output Capacitor vs Total
DC Accuracy
VIN to VOUT Step-Down Ratios
There are restrictions in the maximum VIN and VOUT stepdown ratio that can be achieved for a given input voltage.
Each output of the LTM4652 is capable of 98% duty cycle,
but the VIN to VOUT minimum dropout is still shown as a
function of its load current and will limit output current
capability related to high duty cycle on the top side switch.
Minimum on-time tON(MIN) is another consideration in
operating at a specified duty cycle while operating at a
certain frequency due to the fact that tON(MIN) < D/fSW,
where D is duty cycle and fSW is the switching frequency.
tON(MIN) is specified in the electrical parameters as 90ns.
Output Voltage Programming
AC OVERSHOOT
ALLOWABLE
REGULATION
WINDOW
DC ACCURACY
AC UNDERSHOOT
4652 F02
Figure 2. Typical Load Step Transient Response with
DC Voltage Accuracy Variance
14
The PWM controller has an internal 0.6V reference voltage.
As shown in the Figure 1 (Simplified Block Diagram), a
60.4k internal feedback resistor connects between the
VOUTS1 to VFB1 and VOUTS2 to VFB2. It is very important
that these pins be connected to their respective outputs
for proper feedback regulation. Overvoltage can occur if
these VOUTS1 and VOUTS2 pins are left floating when used
as individual regulators, or at least one of them is used
Rev. 0
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LTM4652
APPLICATIONS INFORMATION
in paralleled regulators. The output voltage will default
to 0.6V with no feedback resistor on either VFB1 or VFB2.
Adding a resistor RFB from VFB pin to GND programs the
output voltage given by Equation 2. (See Table 1.)
VOUT
60.4k + RFB
= 0.6V •
RFB
COMP1
2.5k
LTM4652
VOUT2
COMP2
6800pF
60.4k
VOUTS1
VOUTS2
VFB1
(2)
TRACK1
4 PARALLELED OUTPUTS
FOR 1.2V AT 100A
VOUT1
OPTIONAL CONNECTION
60.4k
VFB2
TRACK2
Table 1. VFB Resistor Table vs Various Output Voltages
VOUT
0.6V
1.0V
1.2V
1.5V
1.8V
2.5V
3.3V
5V
RFB
Open
90.9k
60.4k
40.2k
30.2k
19.1k
13.3k
8.25k
COMP1
VOUT1
VOUT2
COMP2
For parallel operation of multiple channels the same feedback setting resistor can be used for the parallel design.
This is done by connecting the VOUTS1 to the output as
shown in Figure 4, thus tying one of the internal 60.4k
resistors to the output. All of the VFB pins tie together with
one programming resistor as shown in Figure 4.
In parallel operation, the VFB pins have an IFB current of
30nA per channel, maximum. To reduce output voltage
error due to this current, an additional VOUTS pin can be
tied to VOUT, and an additional RFB resistor can be used
to lower the total Thevenin equivalent resistance seen by
this current. For example in Figure 4, the total Thevenin
equivalent resistance of the VFB pin is (60.4k//RFB), which
is 30.2k where RFB is equal to 60.4k for a 1.2V output.
Four phases connected in parallel equates to a worse case
feedback current of 4 • IFB = 120nA maximum. The voltage
error is 120nA • 30.2k = 3.6mV. If VOUTS2 is connected, as
shown in Figure 4, to VOUT, and another 60.4k resistor is
connected from VFB2 to ground, then the voltage error is
reduced to 1.8mV. If the voltage error is acceptable then
no additional connections are necessary. The onboard
60.4k resistor is 0.5% accurate and the VFB resistor can
be chosen by the user to be as accurate as needed. All
COMP pins are tied together for current sharing between
the phases. The TRACK pins can be tied together and a
single soft-start capacitor can be used to soft-start the
regulator. Equation 6 in the Soft-Start And Output Voltage
Tracking section will need to have the soft-start current
parameter increased by the number of paralleled channels.
LTM4652
60.4k
VOUTS1
VOUTS2
VFB1
TRACK1
0.1µF
TRACK2
OPTIONAL
RFB
60.4k
USE TO LOWER
TOTAL EQUIVALENT
RESISTANCE TO LOWER
IFB VOLTAGE ERROR
60.4k
VFB2
4652 F04
RFB
60.4k
Figure 4. 4-Phase Parallel Configurations
Input Capacitors
The LTM4652 module should be connected to a low
AC-impedance DC source. For each channel input,
two 22µF input ceramic capacitors are used for RMS ripple current. A 47µF to 100µF surface mount aluminum
electrolytic bulk capacitor can be used for more input
bulk capacitance. This bulk input capacitor is only needed
if the input source impedance is compromised by long
inductive leads, traces or not enough source capacitance.
If low impedance power planes are used, then this bulk
capacitor is not needed.
For a buck converter, the switching duty-cycle can be estimated using Equation 3.
D=
VOUT
VIN
(3)
Without considering the inductor current ripple, for each
output, the RMS current of the input capacitor can be
estimated using Equation 4.
ICIN(RMS) =
IOUT(MAX)
• D • (1− D)
η%
(4)
Rev. 0
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15
LTM4652
APPLICATIONS INFORMATION
In Equation 4, η% is the estimated efficiency of the power
module. The bulk capacitor can be a switcher-rated electrolytic aluminum capacitor, Polymer capacitor.
Output Capacitors
The LTM4652 is designed for low output voltage ripple noise and good transient response. The bulk output
capacitors defined as COUT are chosen with low enough
effective series resistance (ESR) to meet the output
voltage ripple and transient requirements. COUT can be a
low ESR tantalum capacitor, the low ESR polymer capacitor or ceramic capacitor. The typical output capacitance
range for each output is from 300µF to 800µF per output
channel. Additional output filtering may be required by
the system designer, if further reduction of output ripples
or dynamic transient spikes is required. Table 6 shows a
matrix of different output voltages and output capacitors
to minimize the voltage droop and overshoot during a
25% load step. In multi LTM4652 paralleling applications,
Table 6 RC compensation value is still valid in terms of
having one set of RC filters on each of the paralleling
modules while connecting all the COMP, FB and VOUT
pins together. See Figure 34 and Multiphase Operation
section. The table optimizes total equivalent ESR and
total bulk capacitance to optimize the transient performance. Stability criteria are considered in the Table 6
matrix, and the Analog Devices LTpowerCAD Design Tool
provides for stability analysis. Multiphase operation will
reduce effective output ripple as a function of the number of phases. Application Note 77 discusses this noise
reduction versus output ripple current cancellation, but
the output capacitance should be considered carefully as
a function of stability and transient response. The Analog
Devices µModule Power Design Tool can calculate the
output ripple reduction as the number of implemented
phases increases by N times. A small value 10Ω to 50Ω
resistor can be placed in series from VOUT to the VOUTS pin
to allow for a bode plot analyzer to inject a signal into the
control loop and validate the regulator stability. The same
resistor could be placed in series from VOUT to DIFFP and
a bode plot analyzer could inject a signal into the control
loop and validate the regulator stability.
Pulse-Skipping Mode Operation
In applications where low output ripple and high efficiency
at intermediate currents are desired, pulse-skipping
mode should be used. Pulse-skipping operation allows
the LTM4652 to skip cycles at low output loads, thus
increasing efficiency by reducing switching loss. Tying
the MODE_PLLIN pin to INTVCC enables pulse-skipping
operation. At light loads the internal current comparator may remain tripped for several cycles and force the
top MOSFET to stay off for several cycles, thus skipping
cycles. The inductor current does not reverse in this mode.
Applications with transient and/or sustained negative (sinking) output current should operate the LTM4652 in forced
continuous mode, since there is no way for the control
loop to command reverse (negative) inductor current in
pulse-skipping operation except by deliberately allowing
the output voltage to rise high enough (~10% above nominal regulation) to activate an output overvoltage response.
Forced Continuous Operation
In applications where fixed frequency operation is more
critical than low current efficiency, and where the lowest output ripple is desired, forced continuous operation
should be used. Forced continuous operation can be
enabled by tying the MODE_PLLIN pin to SGND. In this
mode, inductor current is allowed to reverse during low
output loads, the COMP voltage is in control of the current
comparator threshold throughout, and the top MOSFET
always turns on with each oscillator pulse. During start-up,
forced continuous mode is disabled and inductor current
is prevented from reversing until the LTM4652’s output
voltage is in regulation. Either regulator can be configured
for forced continuous mode.
Multiphase Operation
For output loads that demand more than ±25A of current,
two outputs in LTM4652 or even multiple LTM4652s can
be paralleled to run out of phase to provide more output
current without increasing input and output voltage ripples.
The MODE_PLLIN pin allows the LTM4652 to synchronize
to an external clock (between 300kHz* and 780kHz) and
the internal phase-locked-loop allows the LTM4652 to lock
*Note that synchronization below 400kHz is not tested in ATE.
16
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LTM4652
APPLICATIONS INFORMATION
In multi LTM4652s parallel applications, CTH and RTH values in Table 6 are still valid to achieve transient response in
a 25% load step. Connect one set of RC (RTH and CTH) network to the COMP pin of each paralleling module like a dual
phase single output setup. Then connect the COMP pins,
FB pins, TRACK pins and VOUT pins from different modules together. See Figure 32, Figure 34 and Figure 35 for
examples of parallel operation. LTpowerCAD Power Design
Tool can also be used to optimize loop compensation and
transient performance if only one set of RC (RTH and CTH)
network is to be added to the common COMP pins.
onto incoming clock phase as well. The CLKOUT signal
can be connected to the MODE_PLLIN pin of the following
stage to line up both the frequency and the phase of the
entire system. Tying the PHASMD pin to INTVCC, SGND, or
(floating) generates a phase difference (between
MODE_PLLIN and CLKOUT) of 120 degrees, 60 degrees,
or 90 degrees respectively. A total of 12 phases can be
cascaded to run simultaneously with respect to each other
by programming the PHASMD pin of each LTM4652 channel to different levels. Figure 5 shows a 2-phase design,
4-phase design and a 6-phase design example for clock
phasing with the PHASMD table.
The LTM4652 device is an inherently current mode controlled device, so parallel modules will have very good current sharing. This will balance the thermals on the design.
A multiphase power supply significantly reduces the
amount of ripple current in both the input and output
capacitors. The RMS input ripple current is reduced by,
and the effective ripple frequency is multiplied by, the
number of phases used (assuming that the input voltage is
greater than the number of phases used times the output
voltage). The output ripple amplitude is also reduced by
the number of phases used when all of the outputs are tied
together to achieve a single high output current design.
Input RMS Ripple Current Cancellation
Application Note 77 provides a detailed explanation of
multiphase operation. The input RMS ripple current cancellation mathematical derivations are presented, and a
graph is displayed representing the RMS ripple current
reduction as a function of the number of interleaved
phases. Figure 6 shows this graph.
2-PHASE DESIGN
PHASMD
FLOAT
CLKOUT
0-PHASE
MODE_PLLIN
VOUT1
VOUT2
SGND
FLOAT
INTVCC
CONTROLLER1
0
0
0
CONTROLLER2
180
180
240
CLKOUT
60
90
120
180-PHASE
PHASMD
4-PHASE DESIGN
90-DEGREE
CLKOUT
0-PHASE
FLOAT
CLKOUT
MODE_PLLIN
VOUT1
VOUT2
180-PHASE
90-PHASE
FLOAT
PHASMD
MODE_PLLIN
VOUT1
VOUT2
270-PHASE
PHASMD
6-PHASE DESIGN
60-DEGREE
60-DEGREE
CLKOUT
0-PHASE
SGND
CLKOUT
MODE_PLLIN
VOUT1
PHASMD
VOUT2
180-PHASE
60-PHASE
SGND
CLKOUT
MODE_PLLIN
VOUT1
VOUT2
240-PHASE
PHASMD
120-PHASE
FLOAT
MODE_PLLIN
VOUT1
VOUT2
300-PHASE
PHASMD
4652 F05
Figure 5. Examples of 2-Phase, 4-Phase, and 6-Phase Operation with PHASMD Table
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17
LTM4652
APPLICATIONS INFORMATION
0.60
1-PHASE
2-PHASE
3-PHASE
4-PHASE
6-PHASE
0.55
0.50
RMS INPUT RIPPLE CURRENT
DC LOAD CURRENT
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0.1 0.15
0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
DUTY FACTOR (VOUT/VIN)
4652 F06
Figure 6. Input RMS Current Ratios to DC Load Current as a Function of Duty Cycle
900
Frequency Selection and Phase-Lock Loop
(MODE_PLLIN and fSET Pins)
800
The LTM4652 switching frequency can be set with an
external resistor from the fSET pin to SGND. An accurate
9.5µA current source into the resistor will set a voltage
that programs the frequency or a DC voltage can be
applied. Figure 7 shows a graph of frequency setting
verses programming voltage. An external clock can be
applied to the MODE_PLLIN pin from 0V to INTVCC over
a frequency range of 300kHz* to 780kHz. The clock input
700
FREQUENCY (kHz)
The LTM4652 device is operated over a range of frequencies to improve power conversion efficiency. It is recommended to operate the module at 300kHz* to 780kHz over
different input and output range for the best efficiency and
inductor current ripple.
600
500
400
300
200
100
0
0
0.5
1
1.5
fSET PIN VOLTAGE (V)
2
2.5
4652 F07
Figure 7. Operating Frequency vs fSET Pin Voltage
*Note that synchronization below 400kHz is not tested in ATE.
18
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APPLICATIONS INFORMATION
high threshold is 1.6V and the clock input low threshold
is 1V. The LTM4652 has the PLL loop filter components
on board. The frequency setting resistor should always
be present to set the initial switching frequency before
locking to an external clock. Both regulators will operate
in forced continuous mode while being externally clocked.
take over the internal 0.6V reference voltage to control the
output voltage. The total soft-start time can be calculated
using Equation 6.
The output of the PLL phase detector has a pair of complementary current sources that charge and discharge
the internal filter network. When the external clock is
applied then the fSET frequency resistor is disconnected
with an internal switch, and the current sources control
the frequency adjustment to lock to the incoming external
clock. When no external clock is applied, then the internal
switch is on, thus connecting the external fSET frequency
set resistor for free run operation.
where CSS is the capacitance on the TRACK pin. Current
foldback and forced continuous mode are disabled during
the soft-start process.
tSS = 0.6V•
CSS
1.25µA
(6)
Output voltage tracking can also be programmed externally using the TRACK pin. The output can be tracked
up and down with another regulator. Figure 8 shows an
example waveform where the slave regulator’s output
slew rate is proportional to the master’s.
Minimum On-Time
Minimum on-time tON is the smallest time duration that
the LTM4652 is capable of turning on the top MOSFET
on either channel. It is determined by internal timing
delays, and the gate charge required turning on the top
MOSFET. Low duty cycle applications may approach
this minimum on-time limit and care should be taken to
ensure Equation 5.
VOUT
>t
VIN •FREQ ON(MIN)
OUTPUT VOLTAGE
MASTER OUTPUT
SLAVE OUTPUT
(5)
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the output ripple and current will increase. The on-time
can be increased by lowering the switching frequency. A
good rule of thumb is to keep on-time longer than 110ns.
TIME
Figure 8. Output Ratiometric Tracking Waveform
Since the slave regulator’s TRACK is connected to the
master’s output through a RTR(TOP)/RTR(BOT) resistor
divider and its voltage used to regulate the slave output
voltage when TRACK voltage is below 0.6V, the slave output voltage and the master output voltage should satisfy
Equation 7 during start-up:
Soft-Start And Output Voltage Tracking
The TRACK pin provides a means to either soft-start the
regulator or track it to a different power supply. A capacitor on the TRACK pin will program the ramp rate of the
output voltage. An internal 1.25µA current source will
charge up the external soft-start capacitor towards INTVCC
voltage. When the TRACK voltage is below 0.6V, it will
4652 F08
VOUT(SL) •
RFB(SL)
RFB(SL) +60.4k
VOUT(MA) •
=
(7)
R TR(BOT)
R TR(TOP) +R TR(BOT)
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LTM4652
APPLICATIONS INFORMATION
The RFB(SL) is the feedback resistor and the RTR(TOP)/
RTR(BOT) is the resistor divider on the TRACK pin of the
slave regulator, as shown in Figure 9.
Following Equation 7, the ratio of the master’s output
slew rate (MR) to the slave’s output slew rate (SR) is
determined by Equation 8.
RFB(SL)
RFB(SL) +60.4k
R TR(BOT)
MR
=
SR
(8)
R TR(TOP) +R TR(BOT)
For example, VOUT(MA)=1.5V, MR = 1.5V/1ms and VOUT(SL)
= 3.3V, SR = 3.3V/1ms. From Equation 8, we could solve
that RTR(TOP) = 60.4k and RTR(BOT) = 40.2k are a good
combination for the ratiometric tracking.
The TRACK pin will have the 1.25µA current source on
when a resistive divider is used to implement tracking
on the slave regulator. This will impose an offset on
the TRACK pin input. Smaller value resistors with the
same ratios as the resistor values calculated from the
Equation 8 can be used. For example, where the 60.4k is
used then a 6.04k can be used to reduce the TRACK pin
offset to a negligible value.
Coincident output tracking can be recognized as a special
ratiometric output tracking in which the master’s output
slew rate (MR) is the same as the slave’s output slew rate
(SR), waveform as shown in Figure 10.
From Equation 8, we could easily find that, in coincident tracking, the slave regulator’s TRACK pin resistor
divider is always the same as its feedback divider given
by Equation 9.
RFB(SL)
R TR(BOT)
=
RFB(SL) +60.4k R TR(TOP) +R TR(BOT)
(9)
INTVCC
C10
4.7µF
R2
10k
PGOOD1
MODE_PLLIN CLKOUT INTVCC EXTVCC PGOOD1
4.5V TO 18V INTERMEDIATE BUS
C4
22µF
25V
C3
22µF
25V
C2
22µF
25V
C1
22µF
25V
R6
845k
VOUT1
VIN
VINOVP
SW1
RUN1
RUN2
LTM4652
TRACK2
RTR(TOP)
60.4k
RTR(BOT)
40.2k
f SET
VFB2
RFB(SL)
13.3k
COMP1
COMP2
10k
TEMP+
PHASMD
VOUTS2
VOUT2
R4
140k
SW2
3.3nF
SLAVE
C5
100µF
6.3V
×3
PGOOD2
PGOOD2
SGND
GND
DIFFP
40.2k
10k
4.7nF
TEMP–
VOUT1
(MASTER)
1.5V
C8
470µF
6.3V
VFB1
TRACK1
CSS
C6
100µF
6.3V
×3
VOUTS1
VOUT1
(MASTER)
1.5V
±25A
DIFFN DIFFOUT
4652 F09
C7
470µF
6.3V
VOUT2
(SLAVE)
3.3V
±25A
INTVCC
R9
10k
RAMP TIME
tSOFTSTART = (CSS /1.25µA) • 0.6V
Figure 9. Example of Output Tracking Application Circuit
20
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APPLICATIONS INFORMATION
pin. The LTM4652 will turn on with RUN floating. Please
note RUN has a 6V Abs Max voltage rating. The RUN
pins can also be used for output voltage sequencing.
In parallel operation the RUN pins can be tied together
and controlled from a single control. See the Typical
Applications circuits in Figure 31.
OUTPUT VOLTAGE
MASTER OUTPUT
SLAVE OUTPUT
INTVCC and EXTVCC
TIME
4652 F10
Figure 10. Output Coincident Tracking Waveform
For example, RTR(TOP) = 60.4k and RTR(BOT) = 13.3k is a
good combination for coincident tracking for a VOUT(MA)
= 1.5V and VOUT(SL) = 3.3V application.
Power Good
The PGOOD pins are open drain pins that can be used to
monitor valid output voltage regulation. This pin monitors
a 10% window around the regulation point. A resistor can
be pulled up to a particular supply voltage no greater than
6V maximum for monitoring.
Stability Compensation
The LTM4652 has a built-in 10pF high frequency filter
capacitor from COMP to SGND on each output channel. An external R-C filtering circuit is required to add
from COMP to SGND to achieve fast Type II control loop
compensation. Table 6 is provided for most application requirements. The Analog Devices µModule Power
Design Tool (LTpowerCAD) provides for other control loop
optimization.
Run Enable
The RUN pins have an enable threshold of 1.4V maximum,
typically 1.22V with 135mV of hysteresis. They control the
turn on of each of the channels and INTVCC. These pins
can be pulled up to VIN for 5V operation, or a 5V Zener
diode can be placed on the pins and a 10k to 100k resistor can be placed up to higher than 5V input for enabling
the channels. There is 1µA pull-up current for each RUN
The LTM4652 module has an internal 5V low dropout
regulator that is derived from the input voltage. This regulator is used to power the control circuitry and the power
MOSFET drivers. This regulator can source up to 50mA,
and typically uses ~30mA for powering the device at the
maximum frequency. This internal 5V supply is enabled
by either RUN1 or RUN2.
EXTVCC allows an external 5V supply to power the
LTM4652 and reduce power dissipation from the internal
low dropout 5V regulator. The power loss savings can be
calculated using Equation 10.
(VIN – 5V) • 30mA = PLOSS
(10)
EXTVCC has a threshold of 4.7V for activation, and a maximum rating of 6V. When using a 5V input, connect this
5V input to EXTVCC also to maintain a 5V gate drive level.
EXTVCC must sequence on after VIN, and EXTVCC must
sequence off before VIN.
Differential Remote Sense Amplifier
An accurate differential remote sense amplifier is provided
to sense low output voltages accurately at the remote
load points. This is especially true for high current loads.
The amplifier can be used on one of the two channels, or
on a single parallel output. It is very important that the
DIFFP and DIFFN are connected properly at the output,
and DIFFOUT is connected to either VOUTS1 or VOUTS2.
In parallel operation, the DIFFP and DIFFN are connected
properly at the output, and DIFFOUT is connected to
one of the VOUTS pins. Review the parallel schematics in
Figure 32 and Figure 34 and review Figure 4. Please note
the differential amplifier can be used for ≤3.3V outputs.
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LTM4652
APPLICATIONS INFORMATION
The SW pins are generally for testing purposes by monitoring these pins. These pins can also be used to dampen
out switch node ringing caused by LC parasitic in the
switched current paths. Usually a series R-C combination
is used called a snubber circuit. The resistor will dampen
the resonance and the capacitor is chosen to only affect
the high frequency ringing across the resistor. If the stray
inductance or capacitance can be measured or approximated then a somewhat analytical technique can be used
to select the snubber values. The inductance is usually
easier to predict. It combines the power path board inductance in combination with the MOSFET interconnect bond
wire inductance.
First the SW pin can be monitored with a wide bandwidth
scope with a high frequency scope probe. The ring frequency can be measured for its value. The impedance Z
can be calculated using Equation 11.
Z(L) = 2πfL,
(11)
where f is the resonant frequency of the ring, and L is the
total parasitic inductance in the switch path. If a resistor
is selected that is equal to Z, then the ringing should be
dampened. The snubber capacitor value is chosen so that
its impedance is equal to the resistor at the ring frequency.
Calculated by: Z(C) = 1/(2πfC). These values are a good
place to start with. Modification to these components
should be made to attenuate the ringing with the least
amount of power loss.
Temperature Monitoring
A diode connected PNP transistor is used for the TEMP+/
TEMP– monitor function by monitoring its voltage over
temperature. The temperature dependence of this diode
voltage can be understood in Equation 12.
⎛I ⎞
VD = nVT ln ⎜ D ⎟
⎝ IS ⎠
(12)
where VT is the thermal voltage (kT/q), and n, the ideality
factor, is 1 for the diode connected PNP transistor being
22
used in the LTM4652. IS is expressed by the typical empirical Equation 13.
⎛ –V ⎞
IS =I0 exp ⎜ G0 ⎟
⎝ VT ⎠
(13)
where I0 is a process and geometry dependent current, (I0
is typically around 20k orders of magnitude larger than IS
at room temperature) and VG0 is the band gap voltage of
1.2V extrapolated to absolute zero or –273°C.
If we take the IS Equation 13 and substitute into the
Equation 14, then we get:
⎛ kT ⎞ ⎛ I ⎞
kT
VD = VG0 – ⎜ ⎟ ln ⎜ 0 ⎟ , VT =
⎝ q ⎠ ⎝ ID ⎠
q
(14)
0.8
ID = 100µA
0.7
DIODE VOLTAGE (V)
SW Pins
0.6
0.5
0.4
0.3
–50
–25
50
25
0
75
TEMPERATURE (°C)
100
125
4652 F11
Figure 11. Diode Voltage VD vs Temperature T(K)
for Different Bias Currents
The expression shows that the diode voltage decreases
(linearly if I0 were constant) with increasing temperature
and constant diode current. Figure 11 shows a plot of VD
vs Temperature over the operating temperature range of
the LTM4652.
If we take Equation 14 and differentiate it with respect to
temperature T, then Equation 15 gives:
V –V
dVD
= – G0 D
T
dT
(15)
This dVD/dT term is the temperature coefficient equal to
about –2mV/K or –2mV/°C. Equation 15 is simplified for
the first order derivation.
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Solving for T, T = –(VG0 – VD)/(dVD/dT) provides the
temperature.
1st Example: Figure 11 for 27°C, or 300K the diode
voltage is 0.598V, thus, 300K = –(1200mV – 598mV)/
–2.0mV/K).
2nd Example: Figure 11 for 75°C, or 350K the diode
voltage is 0.50V, thus, 350K = –(1200mV – 500mV)/
–2.0mV/K).
Converting the Kelvin scale to Celsius is simply taking the
Kelvin temp and subtracting 273 from it.
A typical forward voltage is given in the electrical characteristics section of the data sheet, and Figure 11 is the
plot of this forward voltage. Measure this forward voltage
at 27°C to establish a reference point. Then using the
above expression while measuring the forward voltage
over temperature will provide a general temperature monitor. A bias current on the order of 100µA is appropriate
for generating a typical forward voltage. If preferred,
LTC2997 and similar temperature-monitoring ICs can be
used, instead (see Figure 33).
Thermal Considerations and Output Current Derating
The thermal resistances reported in the Pin Configuration
section of the data sheet are consistent with those parameters defined by JESD51-9 and are intended for use with
finite element analysis (FEA) software modeling tools that
leverage the outcome of thermal modeling, simulation,
and correlation to hardware evaluation performed on a
µModule package mounted to a hardware test board—
also defined by JESD51-9 (Test Boards for Area Array
Surface Mount Package Thermal Measurements). The
motivation for providing these thermal coefficients is
found in JESD51-12 (Guidelines for Reporting and Using
Electronic Package Thermal Information).
Many designers may opt to use laboratory equipment and
a test vehicle such as the demo board to anticipate the
µModule regulator’s thermal performance in their application at various electrical and environmental operating
conditions to compliment any FEA activities. Without
FEA software, the thermal resistances reported in the
Pin Configuration section are in-and-of themselves not
relevant to providing guidance of thermal performance;
instead, the derating curves provided in the data sheet can
be used in a manner that yields insight and guidance pertaining to one’s application-usage, and can be adapted to
correlate thermal performance to one’s own application.
The Pin Configuration section typically gives three thermal
coefficients explicitly defined in JESD51-12; these coefficients are quoted or paraphrased below:
1. θJA, the thermal resistance from junction to ambient, is
the natural convection junction-to-ambient air thermal
resistance measured in a one cubic foot sealed enclosure. This environment is sometimes referred to as
“still air” although natural convection causes the air to
move. This value is determined with the part mounted
to a Demo Board.
2. θJCbot, the thermal resistance from junction to the
bottom of the product case, is the junction-to-board
thermal resistance with all of the component power
dissipation flowing through the bottom of the package.
In the typical µModule, the bulk of the heat flows out
the bottom of the package, but there is always heat
flow out into the ambient environment. As a result, this
thermal resistance value may be useful for comparing
packages but the test conditions don’t generally match
the user’s application.
3. θJCtop, the thermal resistance from junction to top of
the product case, is determined with nearly all of the
component power dissipation flowing through the top
of the package. As the electrical connections of the
typical µModule are on the bottom of the package, it
is rare for an application to operate such that most
of the heat flows from the junction to the top of the
part. As in the case of θJCbot, this value may be useful
for comparing packages but the test conditions don’t
generally match the user’s application.
A graphical representation of the aforementioned thermal
resistances is given in Figure 12; blue resistances are
contained within the µModule regulator, whereas green
resistances are external to the µModule.
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LTM4652
APPLICATIONS INFORMATION
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-CASE (TOP)
RESISTANCE
JUNCTION
AMBIENT
JUNCTION-TO-CASE
(BOTTOM) RESISTANCE
µModule DEVICE
BOARD-TO-AMBIENT
RESISTANCE
4652 F12
Figure 12. Graphical Representation of JESD51-12 Thermal Coefficients
As a practical matter, it should be clear to the reader
that no individual or sub-group of the four thermal resistance parameters defined by JESD51-12 or provided in
the Pin Configuration section replicates or conveys normal operating conditions of a µModule. For example, in
normal board-mounted applications, never does 100%
of the device’s total power loss (heat) thermally conduct
exclusively through the top or exclusively through bottom
of the µModule—as the standard defines for θJCtop and
θJCbot, respectively. In practice, power loss is thermally
dissipated in both directions away from the package—
granted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board.
Within a SIP (system-in-package) module, be aware there
are multiple power devices and components dissipating
power, with a consequence that the thermal resistances
relative to different junctions of components or die are not
exactly linear with respect to total package power loss. To
reconcile this complication without sacrificing modeling
simplicity—but also, not ignoring practical realities—an
approach has been taken using FEA software modeling
along with laboratory testing in a controlled-environment
chamber to reasonably define and correlate the thermal
resistance values supplied in this data sheet: (1) Initially,
FEA software is used to accurately build the mechanical
geometry of the µModule and the specified PCB with all
of the correct material coefficients along with accurate
power loss source definitions; (2) this model simulates
a software-defined JEDEC environment consistent with
JESD51-9 to predict power loss heat flow and temperature
24
readings at different interfaces that enable the calculation
of the JEDEC-defined thermal resistance values; (3) the
model and FEA software is used to evaluate the µModule with heat sink and airflow; (4) having solved for and
analyzed these thermal resistance values and simulated
various operating conditions in the software model, a
thorough laboratory evaluation replicates the simulated
conditions with thermocouples within a controlled-environment chamber while operating the device at the same
power loss as that which was simulated. The outcome
of this process and due diligence yields the set of derating curves provided in later sections of this data sheet,
along with well-correlated JESD51-12-defined θ values
provided in the Pin Configuration section of this data
sheet. Each system has its own thermal characteristics,
therefore thermal analysis must be performed by the user
in a particular system.
The LTM4652 module has been designed to effectively
remove heat from both the top and bottom of the package. The bottom substrate material has very low thermal
resistance to the printed circuit board. An external heat
sink can be applied to the top of the device for excellent
heat sinking with airflow.
Figure 13 shows the thermal image of the LTM4652,
without airflow, without heat sink, running paralleled
from 12V to 1V at 50A with around 85.3% efficiency and
8.6W power loss. Figure 14 shows the thermal image of
the LTM4652, with 200LFM airflow, without heat sink,
running paralleled from 12V to 3.3V at 50A with around
92.2% efficiency and 14W power loss.
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APPLICATIONS INFORMATION
4652 F13
Figure 13. Thermal Image 12V to 1.0V,
50A with No Airflow without Heat Sink
Safety Considerations
The LTM4652 modules do not provide isolation from VIN
to VOUT. There is no internal fuse. If required, a slow blow
fuse with a rating twice the maximum input current needs
to be provided to protect each unit from catastrophic failure. The device does support over current protection. A
temperature diode is provided for monitoring internal temperature, and can be used to detect the need for thermal
shutdown that can be done by controlling the RUN pin.
Power Derating
The 1.0V, 1.8V, 3.3V and 5V power loss curves in
Figure 15 to Figure 17 can be used in coordination with
the load current derating curves in Figure 18 to Figure 29
for calculating an approximate θJA thermal resistance for
the LTM4652 with various heat sinking and airflow conditions. The power loss curves are taken at room temperature, and are increased with a 1.2 multiplicative factor
at 125°C.
The derating curves are plotted with CH1 and CH2 in parallel single output operation starting at ±50A of load with
low ambient temperature. The output voltages are 1V to
3.3V. These are chosen to include the lower and higher
output voltage ranges for correlating the thermal resistance. Thermal models are derived from several temperature measurements in a controlled temperature chamber
along with thermal modeling analysis.
4652 F14
Figure 14. Thermal Image 12V to 3.3V,
50A with 200LFM Airflow without Heat Sink
The junction temperatures are monitored while ambient
temperature is increased with and without airflow. The
power loss increase with ambient temperature change
is factored into the derating curves. The junctions are
maintained at ~120°C maximum while lowering output
current or power while increasing ambient temperature.
The decreased output current will decrease the internal
module loss as ambient temperature is increased.
The monitored junction temperature of 120°C minus the
ambient operating temperature specifies how much module temperature rise can be allowed. As an example in
Figure 26, the load current is derated to ~36A at ~50°C
with no air or heat sink and the power loss for the 12V
to 3.3V at 36A output is a ~8.8W loss. The 8.8W loss is
calculated with the ~8.4W room temperature loss from
the 12V to 3.3V power loss curve at 36A, and applying a
1.05 multiplying factor at 50°C ambient (see Figure 17).
If the 50°C ambient temperature is subtracted from the
120°C junction temperature, then the difference of 70°C
divided by 8.8W yields a 7.95°C/W θJA thermal resistance.
Table 2 specifies a 7.9°C/W value which is pretty close.
The airflow graphs are more accurate due to the fact that
the ambient temperature environment is controlled better
with airflow. Table 2 to Table 4 provide equivalent thermal
resistances for 1.0V to 3.3V outputs with and without
airflow and heat sinking.
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LTM4652
APPLICATIONS INFORMATION
10
VIN = 12V
VIN = 5V
9
10
5
4
3
12
8
POWER LOSS (W)
POWER LOSS (W)
6
7
6
5
4
3
8
6
2
1
1
0
–50 –40 –30 –20 –10 0 10 20 30 40 50
LOAD CURRENT (A)
0
–50 –40 –30 –20 –10 0 10 20 30 40 50
LOAD CURRENT (A)
4652 F15
0
–50 –40 –30 –20 –10 0 10 20 30 40 50
LOAD CURRENT (A)
4652 F16
4652 F17
Figure 16. 1.8VOUT Power Loss Curve
Figure 17. 3.3VOUT and 5VOUT
Power Loss Curves
50
50
40
40
40
30
20
10
0LFM
200LFM
400LFM
0
–10
–20
–30
30
20
10
0
–20
–30
–40
–50
–50
50
60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
0LFM
200LFM
400LFM
–10
–40
40
MAXIMUM LOAD CURRENT (A)
50
MAXIMUM LOAD CURRENT (A)
30
20
10
0
0LFM
200LFM
400LFM
–10
–20
–30
–40
40
50
–50
60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
40
Figure 20. 12V to 1V Derating
Curve, BGA Heat Sink
50
50
40
40
40
MAXIMUM LOAD CURRENT (A)
50
20
10
0LFM
200LFM
400LFM
0
–10
–20
–30
30
20
10
–10
–20
–30
–40
–50
–50
50
60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4652 F21
Figure 21. 5V to 1V Derating
Curve, BGA Heat Sink
26
0LFM
200LFM
400LFM
0
–40
40
60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4652 F20
Figure 19. 5V to 1V Derating
Curve, No Heat Sink
30
50
4652 F19
4652 F18
Figure 18. 12V to 1V Derating
Curve, No Heat Sink
MAXIMUM LOAD CURRENT (A)
MAXIMUM LOAD CURRENT (A)
10
4
2
Figure 15. 1.0VOUT Power Loss Curve
VIN = 12V, VOUT = 5V
VIN = 12V, VOUT = 3.3V
VIN = 5V, VOUT = 3.3V
14
9
7
2
MAXIMUM LOAD CURRENT (A)
16
VIN = 12V
VIN = 5V
11
8
POWER LOSS (W)
Switching frequency set per Table 6.
12
30
20
10
0LFM
200LFM
400LFM
0
–10
–20
–30
–40
30
40
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4652 F22
Figure 22. 12V to 1.8V Derating
Curve, No Heat Sink
–50
40
50
60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4652 F23
Figure 23. 5V to 1.8V Derating
Curve, No Heat Sink
Rev. 0
For more information www.analog.com
LTM4652
Switching frequency set per Table 6.
50
40
40
40
30
20
10
0LFM
200LFM
400LFM
0
–10
–20
–30
30
20
10
–10
–20
–30
–40
–50
–50
40
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
0LFM
200LFM
400LFM
0
–40
30
MAXIMUM LOAD CURRENT (A)
50
50
MAXIMUM LOAD CURRENT (A)
MAXIMUM LOAD CURRENT (A)
APPLICATIONS INFORMATION
20
10
–10
–20
–30
40
50
–50
60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
40
0LFM
200LFM
400LFM
–10
–20
–30
30
20
10
–10
–20
–30
–40
–50
–50
40
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
0LFM
200LFM
400LFM
0
–40
30
30
20
10
0LFM
200LFM
400LFM
0
–10
–20
–30
–40
20
30
40 50 60 70 80 90 100 110
AMBIENT TEMPERATURE (°C)
4652 F28
4652 F27
Figure 27. 5V to 3.3V Derating
Curve, No Heat Sink
MAXIMUM LOAD CURRENT (A)
40
MAXIMUM LOAD CURRENT (A)
40
0
40 50 60 70 80 90 100 110
AMBIENT TEMPERATURE (°C)
4652 F26
50
10
30
Figure 26. 12V to 3.3V Derating
Curve, No Heat Sink
50
20
20
4652 F25
Figure 25. 5V to 1.8V Derating
Curve, BGA Heat Sink
50
30
0LFM
200LFM
400LFM
0
–40
4652 F24
Figure 24. 12V to 1.8V Derating
Curve, BGA Heat Sink
MAXIMUM LOAD CURRENT (A)
30
Figure 28. 12V to 3.3V Derating
Curve, BGA Heat Sink
–50
30
40
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4652 F29
Figure 29. 5V to 3.3V Derating
Curve, BGA Heat Sink
Rev. 0
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27
LTM4652
APPLICATIONS INFORMATION
• Place high frequency ceramic input and output capacitors next to the VIN, PGND and VOUT pins to minimize
high frequency noise.
The derived thermal resistances in Table 2 to Table 4 for
the various conditions can be multiplied by the calculated power loss as a function of ambient temperature to
derive temperature rise above ambient, thus maximum
junction temperature. Room temperature power loss can
be derived from the efficiency curves and adjusted with
the above ambient temperature multiplicative factors. The
printed circuit board is a 1.6mm thick four layer board
with two ounce copper for all four layers. The PCB dimensions are 101mm × 114mm. The BGA heat sinks are listed
in Table 5.
• Place a dedicated power ground layer underneath
the unit.
• To minimize the via conduction loss and reduce module
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
• Do not put via directly on the pad, unless they are
capped or plated over.
• Use a separated SGND ground copper area for components connected to signal pins. Connect the SGND
to GND underneath the unit.
Layout Checklist/Example
The high integration of LTM4652 makes the PCB board
layout very simple and easy. However, to optimize its
electrical and thermal performance, some layout considerations are still necessary.
• For parallel modules, tie the VOUT, VFB, and COMP pins
together. Use an internal layer to closely connect these
pins together. The TRACK pin can be tied a common
capacitor for regulator soft-start.
• Use large PCB copper areas for high current paths,
including VIN, GND, VOUT1 and VOUT2. It helps to minimize the PCB conduction loss and thermal stress.
• Bring out test points on the signal pins for monitoring.
Figure 30 gives a good example of the recommended layout.
CIN1
CIN2
VIN
M
GND
L
GND
K
J
H
G
SGND
F
COUT1
COUT2
E
D
C
B
A
VOUT1
1
2
3
4
5
6
7
8
9
10
11 12
GND
VOUT2
CNTRL
4652 F30
Figure 30. Recommended PCB Layout
28
Rev. 0
For more information www.analog.com
LTM4652
APPLICATIONS INFORMATION
Table 2. 1.0V Output
VIN (V)
POWER LOSS CURVE
AIRFLOW (LFM)
HEAT SINK
θJA (°C/W)
Figure 18, Figure 19
DERATING CURVE
5, 12
Figure 15
0
None
8.0
Figure 18, Figure 19
5, 12
Figure 15
200
None
6.6
Figure 18, Figure 19
5, 12
Figure 15
400
None
5.6
Figure 20, Figure 21
5, 12
Figure 15
0
BGA Heat Sink
7.6
Figure 20, Figure 21
5, 12
Figure 15
200
BGA Heat Sink
5.9
Figure 20, Figure 21
5, 12
Figure 15
400
BGA Heat Sink
5.0
VIN (V)
POWER LOSS CURVE
AIRFLOW (LFM)
HEAT SINK
θJA (°C/W)
Figure 22, Figure 23
5, 12
Figure 16
0
None
8.0
Figure 22, Figure 23
5, 12
Figure 16
200
None
6.3
Figure 22, Figure 23
5, 12
Figure 16
400
None
5.3
Table 3. 1.8V Output
DERATING CURVE
Figure 24, Figure 25
5, 12
Figure 16
0
BGA Heat Sink
7.6
Figure 24, Figure 25
5, 12
Figure 16
200
BGA Heat Sink
5.5
Figure 24, Figure 25
5, 12
Figure 16
400
BGA Heat Sink
4.6
Table 4. 3.3V Output
VIN (V)
POWER LOSS CURVE
AIRFLOW (LFM)
HEAT SINK
θJA (°C/W)
Figure 26, Figure 27
DERATING CURVE
5, 12
Figure 17
0
None
7.9
Figure 26, Figure 27
5, 12
Figure 17
200
None
6.0
Figure 26, Figure 27
5, 12
Figure 17
400
None
5.1
Figure 28, Figure 29
5, 12
Figure 17
0
BGA Heat Sink
7.6
Figure 28, Figure 29
5, 12
Figure 17
200
BGA Heat Sink
5.4
Figure 28, Figure 29
5, 12
Figure 17
400
BGA Heat Sink
4.2
Table 5. Heat Sink and Thermally Conductive Adhesive Tape Part Numbers
MANUFACTURER
DEVICE
PART NUMBER
WEBSITE
Boyd Corp.
Heat Sink
375424B00034G
www.boydcorp.com
Chomerics
Tape
T411
www.chomerics.com
Rev. 0
For more information www.analog.com
29
LTM4652
APPLICATIONS INFORMATION
Table 6. Output Voltage Response vs Component Matrix (Refer to Figure 31) Load Step Typical Measured Values
(2-Phase Single Output Solution)
CIN (CERAMIC)
VENDOR VALUE
COUT (CERAMIC)
PART NUMBER
COUT (BULK)
VENDOR
VALUE
PART NUMBER
Murata
22μF, 16V, X5R, 1210 GRM32ER61C226KE20L
Murata
100μF,
6.3V,
X5R,
1210
GRM32ER60J107ME20L Panasonic 470μF, EEFGX0E4TIR
2.5V,
3mΩ
Murata
22μF, 16V, X5R, 1206 GRM31CR61C226KE15K
Murata
TDK
22μF, 16V, X5R, 1210 C3225X5R1C226M250AA
Taiyo Yuden
Taiyo Yuden
VENDOR
220μF, GRM31CR60G227M
4V, X5R,
1206
100μF,
6.3V,
X5R,
1210
VALUE PART NUMBER
Panasonic 470μF, 6TPF470MAH
6.3V,
10mΩ
JMK325BJ107MM-T
220µF, AMK325ABJ227MM-T
4V, X5R,
1210
25% Load Step (0A to 12.5A) Ceramic Output Capacitor Only Solutions
COMP PIN
COMP PIN COMP PIN PARALLELING
FEEDPEAK- SETTLING
LOAD STEP
CIN**
CIN
COUT RESISTOR CAPACITOR CAPACITOR FORWARD
PEAK
TIME LOAD
SLEW
VIN VOUT BULK CERAMIC COUT CERAMIC
RTH
CTH
CTHP
CAPACITOR DEVIATION tSETTLE STEP
RATE
(V) (V) (μF)
(μF)
(BULK)
(μF)
(kΩ)
(pF)
(pF)
CFF (pF)
(mV)
(μs)
(A)
(A/μs)
RFB
(kΩ)
FREQ
(kHz)
12
150
22 ×4
None
220 ×8
3.32
6800
None
68
62
40
12.5
10
90.9
300
12 1.2 150
22 ×4
None
220 ×8
3.32
6800
None
68
51
40
12.5
10
60.4
400
12 1.5 150
22 ×4
None
220 ×8
3.32
6800
None
68
61
40
12.5
10
40.2
400
12 1.8 150
22 ×4
None
220 ×8
3.32
6800
None
68
58
40
12.5
10
30.2
500
12 2.5 150
22 ×4
None
220 ×8
3.32
6800
None
68
70
50
12.5
10
19.1
500
12 3.3 150
22 ×4
None
220 ×8
3.32
6800
None
68
70
60
12.5
10
13.3
600
COMP PIN
COMP PIN COMP PIN PARALLELING
FEEDPEAK- SETTLING
LOAD STEP
CIN**
CIN
COUT RESISTOR CAPACITOR CAPACITOR FORWARD
PEAK
TIME LOAD
SLEW
VIN VOUT BULK CERAMIC COUT CERAMIC
RTH
CTH
CTHP
CAPACITOR DEVIATION tSETTLE STEP
RATE
(V) (V) (μF)
(μF)
(BULK)
(μF)
(kΩ)
(pF)
(pF)
CFF (pF)
(mV)
(μs)
(A)
(A/μs)
RFB
(kΩ)
FREQ
(kHz)
12
12
1
5
Suggest to Use POSCAP + Ceramic Cap
25% Load Step (0A to 12.5A) Bulk + Ceramic Output Capacitor Solutions
150
22 ×4 470 ×2 100 ×4
4.64
4700
10
68
54
30
12.5
10
90.9
300
12 1.2 150
1
22 ×4 470 ×2 100 ×4
4.64
4700
10
68
50
30
12.5
10
60.4
400
12 1.5 150
22 ×4 470 ×2 100 ×4
4.64
4700
10
68
57
30
12.5
10
40.2
400
12 1.8 150
22 ×4 470 ×2 100 ×4
4.64
4700
10
68
57
40
12.5
10
30.2
500
12 2.5 150
22 ×4 470 ×2 100 ×4
4.64
4700
10
68
72
50
12.5
10
19.1
500
12 3.3 150
22 ×4 470 ×2 100 ×4
9.09
4700
10
None
89
60
12.5
10
13.3
600
12
22 ×4 470 ×2 100 ×4
9.09
4700
10
None
90
60
12.5
10
8.25
750
5
150
*Different Bulk COUT1 used. See Part Number above.
**CIN (BULK) may be required with long PCB traces.
30
Rev. 0
For more information www.analog.com
LTM4652
TYPICAL APPLICATIONS
INTVCC
R2
10k
C10
4.7µF
VIN
4.5V TO 18V
4.5V TO 18V INTERMEDIATE BUS
+
CIN
(OPT)
TRACK1
C5
0.1µF
CIN
22µF
25V
×4
R7
845k
PINS NOT USED IN
THIS CIRCUIT:
CLKOUT, EXTVCC,
SW1, SW2,
RUN1, RUN2,
TEMP+, TEMP–
PGOOD1
INTVCC
VIN
VOUT1
VOUTS1
VINOVP
VFB2
TRACK2
RTH
6.65k
CTH
3300pF
LTM4652
COMP1
RTH
6.65k
CTH
3300pF
COMP2
VOUTS2
R4
120k
RFB2
60.4k
VOUT2
PHASMD
PGOOD2
SGND
GND
DIFFP
VOUT1
1.5V AT
±25A
RFB1
40.2k
CFF2*
68pF
VOUT2
1.2V AT ±25A
DIFFOUT
fSET
COUT1
220µF
4V
×4
CFF1*
68pF
VFB1
TRACK1
TRACK2
C9
0.1µF
MODE_PLLIN
PGOOD1
INTVCC
R3
10k
PGOOD2
COUT1
220µF
4V
×4
DIFFN
4652 F31
*SEE TABLE 6.
Figure 31. Typical 4.5VIN to 18VIN, 1.5V and 1.2V at ±25A Outputs
Rev. 0
For more information www.analog.com
31
LTM4652
TYPICAL APPLICATIONS
INTVCC
INTVCC
C10
4.7µF
R2
10k
PGOOD
MODE_PLLIN
VIN
4.5V TO 18V
CIN
22µF
25V
×4
PGOOD1
VOUT2
VIN
VOUT1
RUN1
RUN2
RUN
VOUTS1
TRACK1
R5
90.9k
VFB2
COMP1
RTH
3.32k
CTH
6800pF
CFF
68pF
VFB1
LTM4652
TRACK2
C9
0.1µF
PINS NOT USED IN
THIS CIRCUIT:
CLKOUT, EXTVCC,
SW1, SW2, VOUTS2,
TEMP+, TEMP–,
VINOVP
INTVCC
COUT1
220µF
4V
×8
VOUT
1V
±50A
LOAD
1V AT ±50A
COMP2
fSET
PGOOD2
PGOOD
PHASMD
R4
75k
SGND
GND
DIFFN
DIFFP
DIFFOUT
4652 F32a
VOUT (AC)
50mV/DIV
LOAD STEP
10A/DIV
100µs/DIV
4652 F32b
(b) 25% Load Step Transient Response; 12VIN, 1.0VOUT,
50A per Above Circuit
GAIN (dB)
PHASE (Deg)
FREQUENCY (Hz)
(c) 12VIN, 1.0VOUT, 50A Bode Plot per Above Circuit
Figure 32. LTM4652 2-Phase, 1V at 50A
32
Rev. 0
For more information www.analog.com
LTM4652
TYPICAL APPLICATIONS
INTVCC
C10
4.7µF
R2
10k
PGOOD1
VIN
4.5V TO
18V
MODE_PLLIN
C4
22µF
25V
C5
0.1µF
C3
22µF
25V
C2
22µF
25V
C1
22µF
25V
R6
845k
INTVCC
PGOOD1
VOUT1
VIN
VOUTS1
VINOVP
VFB1
TRACK1
TRACK2
R9
60.4k
VOUT1
2.5V
R7
13.3k
RTH
9.31k
CTH
2200pF
VOUTS2
LTM4652
VOUT2
COMP2
RTH
18.2k
CTH
2200pF
COUT1
220µF
4V
×2
VFB2
VOUT1
2.5V
±25A
470µF
4V
LOAD
2.5V AT ±25A
+
LOAD
3.3V AT ±25A
4652 F36
PHASMD
VOUT2
3.3V AT
±25A
470µF
4V
13.3k
fSET
SGND
+
DIFFOUT
COMP1
R4
140k
COUT1
220µF
4V
×2
R5
19.1k
DIFFP
GND TEMP– TEMP+ PGOOD2
DIFFN
4652 F33
PGOOD2
10k
PINS NOT USED IN
THIS CIRCUIT:
CLKOUT, EXTVCC,
SW1, SW2, RUN
INTVCC
10Ω
0.1µF
VCC
D+
470pF
D–
VREF
LTC2997*
GND VPTAT
4mV/K >1k
VPTAT(FILTER)
CFILTER
*PLACE 470pF DIRECTLY ACROSS THE LTC2997’S D+/D– PINS.
ROUTE TEMP+/TEMP– DIFFERENTIALLY TO D+/D– AND PROTECT FROM NOISE WITH GROUND SHIELDING.
TERMINATE (CONNECT) THE D+/D– GROUND SHIELD AT THE LTC2997 GND PIN, ONLY.
FOR BEST VPTAT PERFORMANCE, THE VCC PIN OF THE LTC2997 MUST BE LOCALLY BYPASSED AND QUIET.
SEE LTC2997 DATA SHEET AND APRIL 2017 LT JOURNAL TECHNICAL ARTICLES.
OPTIONAL ANALOG OUTPUT
TEMPERATURE INDICATOR
Figure 33. LTM4652 2.5V and 3.3V Output with Tracking Function
Rev. 0
For more information www.analog.com
33
LTM4652
TYPICAL APPLICATIONS
INTVCC
C10
4.7µF
CLK1
PGOOD
MODE_PLLIN CLKOUT INTVCC
VIN
4.5V TO 18V
C2
22µF
25V
×4
EXTVCC PGOOD1
VOUT1
VIN
R6
845k
VINOVP
RUN
RUN2
VOUTS1
RUN1
TRACK
R2
5k
68pF
SW1
VFB1
TRACK1
VFB2
LTM4652
TRACK2
VFB
COUT1
220µF
4V
×8
R5
60.4k
COMP1
COMP
RTH
3.32k
CTH
6800pF
COMP2
VOUTS2
VOUT2
SW2
fSET
PGOOD2
PHASMD
R4
75k
SGND
GND
DIFFP
DIFFN
PGOOD
DIFFOUT
VOUT
1.2V
±100A
C16
4.7µF
CLK1
MODE_PLLIN CLKOUT INTVCC
C15
22µF
25V
×4
R9
845k
VOUT1
VINOVP
TRACK
VOUTS1
RUN1
SW1
RUN2
VFB1
TRACK1
VFB2
LTM4652
TRACK2
COMP
C19
0.22µF
PINS NOT USED IN
THIS CIRCUIT:
TEMP+, TEMP–
EXTVCC PGOOD1
VIN
RUN
RTH
3.32k
CTH
6800pF
R10
75k
PGOOD
COMP1
VOUTS2
COMP2
fSET
VOUT2
SW2
PGOOD2
PHASMD
SGND
VFB
COUT1
220µF
4V
×8
GND
DIFFP
DIFFN
DIFFOUT
PGOOD
4652 F34
INTVCC
Figure 34. LTM4652 4-Phase, 1.2V at 100A
34
Rev. 0
For more information www.analog.com
LTM4652
TYPICAL APPLICATIONS
INTVCC
INTVCC
C10
4.7µF
VOUT–
CIN
22µF
16V
×8
CINOUT
22µF
25V
×2
RUN
–
VOUT
INTVCC
PGOOD1
EXTVCC
VIN
VOUT1
RUN1
RUN2
VOUT1
LTM4652
TRACK2
VFB1
COMP1
RTH
2k
CTH
47nF
COUT1
220µF
6.3V
×8
VOUTS1
TRACK1
C9
0.1µF
PGOOD
VOUT–
MODE_PLLIN
VIN
4.5V TO 13V
R2
10k
LOAD
VFB2
COMP2
R5
8.25k
CTHP
330pF
INTVCC
VOUT–
–5V
(UP TO ±32A, 9VIN)
fSET
PGOOD2
PGOOD
PHASMD
SGND
GND
DIFFN
DIFFP
DIFFOUT
4652 F35
PINS NOT USED IN THIS CIRCUIT:
CLKOUT, SW1, SW2, VOUTS2, TEMP+, TEMP–, VINOVP
Figure 35. LTM4652 Regulating –5V at Up to ±32A (at 9VIN); See Demo Boards DC3230A and DC3195A for More
Details (Including Performance of PolyPhase and Multimodule Parallel Applications)
Rev. 0
For more information www.analog.com
35
LTM4652
PACKAGE DESCRIPTION
LTM4652 Component BGA Pinout
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
A1
VOUT1
B1
VOUT1
C1
VOUT1
D1
GND
E1
GND
F1
GND
A2
VOUT1
B2
VOUT1
C2
VOUT1
D2
GND
E2
GND
F2
GND
A3
VOUT1
B3
VOUT1
C3
VOUT1
D3
GND
E3
GND
F3
GND
A4
VOUT1
B4
VOUT1
C4
VOUT1
D4
GND
E4
GND
F4
MODE_PLLIN
A5
VOUT1
B5
VOUT1
C5
VOUT1S
D5
VFB1
E5
TRACK1
F5
RUN1
A6
GND
B6
GND
C6
fSET
D6
SGND
E6
COMP1
F6
SGND
A7
GND
B7
GND
C7
SGND
D7
VFB2
E7
COMP2
F7
SGND
A8
VOUT2
B8
VOUT2
C8
VOUT2S
D8
TRACK2
E8
DIFFP
F8
DIFFOUT
A9
VOUT2
B9
VOUT2
C9
VOUT2
D9
GND
E9
DIFFN
F9
RUN2
A10
VOUT2
B10
VOUT2
C10
VOUT2
D10
GND
E10
GND
F10
GND
A11
VOUT2
B11
VOUT2
C11
VOUT2
D11
GND
E11
GND
F11
GND
A12
VOUT2
B12
VOUT2
C12
VOUT2
D12
GND
E12
GND
F12
GND
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
G1
GND
H1
GND
J1
GND
K1
GND
L1
GND
M1
GND
G2
SW1
H2
GND
J2
VIN
K2
VIN
L2
VIN
M2
VIN
G3
GND
H3
GND
J3
VIN
K3
VIN
L3
VIN
M3
VIN
G4
PHASEMD
H4
GND
J4
VIN
K4
VIN
L4
VIN
M4
VIN
G5
CLKOUT
H5
VINOVP
J5
GND
K5
GND
L5
VIN
M5
VIN
G6
SGND
H6
TEMP–
J6
TEMP+
K6
GND
L6
VIN
M6
VIN
G7
SGND
H7
GND
J7
EXTVCC
K7
GND
L7
VIN
M7
VIN
G8
PGOOD2
H8
INTVCC
J8
GND
K8
GND
L8
VIN
M8
VIN
G9
PGOOD1
H9
GND
J9
VIN
K9
VIN
L9
VIN
M9
VIN
G10
GND
H10
GND
J10
VIN
K10
VIN
L10
VIN
M10
VIN
G11
SW2
H11
GND
J11
VIN
K11
VIN
L11
VIN
M11
VIN
G12
GND
H12
GND
J12
GND
K12
GND
L12
GND
M12
GND
36
Rev. 0
For more information www.analog.com
aaa Z
0.630 REF Ø 144x
E
3.1750
SUGGESTED PCB LAYOUT
TOP VIEW
3.1750
PACKAGE TOP VIEW
1.9050
4
0.6350
0.0000
0.6350
PIN 1
CORNER
1.9050
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
more by
information
www.analog.com
6.9850
5.7150
4.4450
3.1750
1.9050
0.6350
0.0000
0.6350
1.9050
3.1750
4.4450
5.7150
6.9850
Y
X
D
// bbb Z
b1
NOM
4.92
0.60
4.32
0.75
0.63
16.00
16.00
1.27
13.97
13.97
0.32 REF
4.00 REF
MAX
5.12
0.70
4.42
0.90
0.66
DIMENSIONS
SUBSTRATE THK
MOLD CAP HT
BALL DIMENSION
PAD DIMENSION
BALL HT
NOTES
DETAIL B
PACKAGE SIDE VIEW
0.15
0.10
0.20
0.30
0.15
TOTAL NUMBER OF BALLS: 144
MIN
4.72
0.50
4.22
0.60
0.60
DETAIL A
SYMBOL
A
A1
A2
b
b1
D
E
e
F
G
H1
H2
aaa
bbb
ccc
ddd
eee
H1
SUBSTRATE
A1
ddd M Z X Y
eee M Z
DETAIL B
H2
MOLD
CAP
ccc Z
Øb (144 PLACES)
aaa Z
Z
6.9850
5.7150
4.4450
4.4450
5.7150
6.9850
A
A2
Z
(Reference DWG # 05-08-7064)
F
e
b
b
11
10
8
7
G
6
5
e
4
PACKAGE BOTTOM VIEW
9
3
2
1
DETAIL A
M
L
K
J
H
G
F
E
D
C
B
A
3
SEE NOTES
PIN 1
DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PIN 1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
!
TRAY PIN 1
BEVEL
COMPONENT
PIN 1
6
PACKAGE IN TRAY LOADING ORIENTATION
LTMXXXXXX
µModule
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
5. PRIMARY DATUM -Z- IS SEATING PLANE
4
BALL DESIGNATION PER JEP95
2. ALL DIMENSIONS ARE IN MILLIMETERS
3
6
SEE NOTES
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
12
03-10-2022-A
BGA Package
144-Lead (16mm × 16mm × 4.92mm)
LTM4652
PACKAGE DESCRIPTION
Rev. 0
37
LTM4652
PACKAGE PHOTOS
Part marking is either ink mark or laser mark
DESIGN RESOURCES
SUBJECT
DESCRIPTION
µModule Design and Manufacturing Resources
Design:
• Selector Guides
• Demo Boards and Gerber Files
• Free Simulation Tools
µModule Regulator Products Search
1. Sort table of products by parameters and download the result as a spread sheet.
Manufacturing:
• Quick Start Guide
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability
2. Search using the Quick Power Search parametric table.
Digital Power System Management
Analog Devices’ family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTM8064
58VIN, ±6A, CVCC µModule Regulator
6V ≤ VIN ≤ 58V, 1.2V ≤ VOUT ≤ 36V; 16mm × 11.9mm × 4.92mm (BGA)
LTM8052
36VIN, ±5A, CVCC µModule Regulator
6V ≤ VIN ≤ 36V, 1.2V ≤ VOUT ≤ 24V; 15mm × 11.25mm × 2.82mm (LGA),
15mm × 11.25mm × 3.42mm (BGA)
LTM4650
Dual 25A or Single 50A µModule Regulator
4.5V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 1.8V; 16mm × 16mm × 5.01mm (BGA)
LTM4650A
Dual 25A or Single 50A µModule Regulator; Up to
5.5VOUT
4.5V ≤ VIN ≤ 16V, 0.6V ≤ VOUT ≤ 5.5V; 16mm × 16mm × 5.01mm (BGA)
LTM4650A-1
Dual 25A or Single 50A µModule Regulator; Up to
5.5VOUT and External Compensation
4.5V ≤ VIN ≤ 16V, 0.6V ≤ VOUT ≤ 5.5V; 16mm × 16mm × 5.01mm (BGA)
LTM4630A
Lower Current and Higher VOUT than LTM4650; Up to
5.3VOUT, Dual 18A or Single 36A
Pin Compatible with LTM4650; 4.5V ≤ VIN ≤ 18V, 0.6V ≤ VOUT ≤ 8V;
16mm × 16mm × 4.41mm (LGA), 16mm × 16mm × 5.01mm (BGA)
LTM4620A
Lower Current and Higher VOUT than LTM4650; Up to
5.3VOUT, Dual 13A or Single 26A
Pin Compatible with LTM4650; 4.5V ≤ VIN ≤ 16V, 0.6V ≤ VOUT ≤ 5.3V; 15mm
15mm × 4.41mm (LGA), 15mm × 15mm × 5.01mm (BGA)
38
Rev. 0
09/22
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For more information www.analog.com
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