LTM4655
EN55022B Compliant 40V, Dual 4A or Single 8A
Step‑Down or 50W Inverting µModule Regulator
FEATURES
DESCRIPTION
Dual 4A/Single 8A Low EMI Switch Mode Power Supply
n EN55022 Class B Compliant
n Two Fully Independent Channels, Each
Configurable for Positive or Negative Output
Voltage Polarity
+
–
n Output Voltage Range: 0.5V ≤ |V
OUTn – VOUTn | ≤ 26.5V
n Wide Input Voltage Range: Up to 40V
n 3.1V or 3.6V Start-Up, Configuration-Dependent
n ±1.67% Total DC Output Voltage Error Over Line,
Load and Temperature
n Analog Output Current Indicator (Positive-V
OUT Only)
n LDO
:
5V
Fixed,
25mA
Capable
LDO
OUT
n Parallelable with LTM4651/LTM4653
n Constant-Frequency Current Mode Control
n Power Good Indicators and Programmable Soft-Start
n Overcurrent and Overtemperature Protection
n 16mm × 16mm × 5.01mm BGA Package
The LTM®4655 is an ultralow noise 40V, dual 4A or single
8A DC/DC μModule® regulator designed to meet the radiated emissions requirements of EN55022. Its channels
are fully independent, parallelable and capable of delivering positive or negative output polarity. Conducted emission requirements can be met by adding standard filter
components. Included in the package are the switching
controllers, power MOSFETs, inductors, filters and support components. A 5V, 25mA LDO and clock generator
enable phase interleaving of the power switching stages,
for improved EMC performance.
APPLICATIONS
The LTM4655 is offered in a 16mm × 16mm × 5.01mm
BGA package with SnPb or RoHS compliant terminal finish.
n
The LTM4655 can regulate positive VOUTn+ voltages
between 0.5V and 26.5V from a 3.1V to 40V input. The
LTM4655 can regulate negative VOUTn– voltages between
–0.5V and –26.5V from a maximum input range of 3.6V to
40V, with the span from VINn to VOUTn– not to exceed 40V. A
switching frequency range of 250kHz to 3MHz is supported.
Automated Test and Measurement
Avionics and Industrial Control Systems
n Video, Imaging and Instrumentation
n
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. Patents, including 5481178, 5705919, 5847554, 6580258.
n
TYPICAL APPLICATION
Concurrent, ±12V Output DC/DC μModule Regulator*
VIN
13V TO 28V
4.7μF
4.7μF
124k
4.7μF
4.7μF
240k
VOSNS1+
SVOUT1–
VOUT1–
SVIN1
VD1
fSET1
IMON1a
IMON1b
VIN2
SVIN2
VD2
124k
VOUT1+
VIN1
LTM4655
LOAD1
22µF
×2
RUN1,2
5V/DIV
5VOUT
UP TO 25mA
VOUT1+
5V/DIV
VOUT2–
5V/DIV
LOAD2
VOUT2–
SVOUT2–
ISET1a
Output Voltage
Start-Up Waveforms
CHANNEL 1 ANALOG OUTPUT
CURRENT INDICATOR
VIMON1 = 0.25Ω • IOUT1
VOSNS2+
ISET2a
ISET1b
12VOUT
UP TO 4A
VOUT2+
fSET2
ISET2b
240k
LDOOUT
IOUT1
IOUT2
47µF
×2
–12VOUT
UP TO 2.9A**
PGOOD1,2
5V/DIV
2ms/DIV
4655 TA01b
GND
4655 TA01a
* FOR COMPLETE CIRCUIT, SEE FIGURE 50.
** FOR CHANNELS CONFIGURED TO REGULATE NEGATIVE VOUTn−: CURRENT LIMIT FREQUENCY-FOLDBACK INCEPTION IS
A FUNCTION OF VINn, VOUTn-, AND fSWn. CONTINUOUS OUTPUT CURRENT CAPABILITY IS SUBJECT TO DETAILS OF
APPLICATION IMPLEMENTATION. SEE NOTES 2 AND 3 AND THE APPLICATIONS INFORMATION SECTION, FOR DETAILS.
Rev. B
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1
LTM4655
TABLE OF CONTENTS
Features...................................................... 1
Applications................................................. 1
Typical Application ......................................... 1
Description.................................................. 1
Absolute Maximum Ratings............................... 3
Pin Configuration........................................... 3
Order Information........................................... 4
Electrical Characteristics.................................. 4
Typical Performance Characteristics................... 10
Pin Functions............................................... 14
Simplified Block Diagram................................ 21
Test Circuit.................................................. 22
Decoupling Requirements................................ 24
Operation................................................... 25
Power Module Overview..........................................25
VIN to VOUT Conversion Ratios.................................26
Input Capacitors, Positive-VOUT Operation..............26
Output Capacitors, Positive-VOUT Operation............ 27
Forced Continuous Operation.................................. 27
Output Voltage Programming, Tracking and
Soft-Start................................................................. 27
Frequency Adjustment............................................. 28
Applications Information................................. 29
Power Module Protection........................................29
RUN Pin Enable........................................................29
2
Loop Compensation.................................................29
Hot Plugging Safely.................................................30
Input Disconnect/Input Short Considerations..........30
INTVCCn and EXTVCCn Connection..........................30
Multiphase Operation............................................... 31
Negative Output Current Capability Varies as a
Function of VINn to VOUTn – Conversion Ratios,
Negative-VOUT– Operation........................................ 32
Input Capacitors, Negative-VOUT– Operation............33
Output Capacitors, Negative-VOUT– Operation.........34
Optional Diodes to Guard Against Overstress,
Negative-VOUT– Operation........................................34
Frequency Adjustment, Negative-VOUT–
Operation.................................................................35
Radiated EMI Noise.................................................36
Thermal Considerations and Output
Current Derating......................................................36
Safety Considerations.............................................. 47
Layout Checklist/Example....................................... 47
Typical Applications....................................... 48
Package Description...................................... 53
Revision History........................................... 55
Package Photos............................................ 56
Design Resources......................................... 56
Related Parts............................................... 56
Rev. B
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LTM4655
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1 and Note 5)
Channel 1 Terminal Voltages (All Channel 1 Terminal
Voltages Relative to VOUT1– Unless Otherwise Indicated)
VIN1, VD1, SVIN1, SVINF1, SW1..................... –0.3V to 42V
GND, EXTVCC1, VOUT1+, VOSNS1+,
ISET1a , ISET1b...................................... –0.3V to 28V
INTVCC1, PGDFB1, VINREG1, COMP1a,
IMON1a, IMON1b...................................... –0.3V to 4V
fSET1..................................................... –0.3V to INTVCC1
RUN1....................................GND–0.3V to VOUT1– + 32V
PGOOD1, CLKIN1 (Relative to GND).............. –0.3V to 6V
TOP VIEW
VIN1
A
VIN2
VIN2, VD2, SVIN2, SVINF2, SW2.................... –0.3V to 42V
GND, EXTVCC2, VOUT2+, VOSNS2+,
ISET2a, ISET2b....................................... –0.3V to 28V
INTVCC2, PGDFB2, VINREG2, COMP2a,
IMON2a, IMON2b..................................... –0.3V to 4V
fSET2..................................................... –0.3V to INTVCC2
RUN2....................................GND–0.3V to VOUT2– + 32V
PGOOD2, CLKIN2 (Relative to GND)............. –0.3V to 6V
LDO and Clock Generator Voltages (All LDO and Clock
Generator Terminal Voltages Relative to GND Unless
Otherwise Indicated)
VD2
B
C
D
E
F
G
IMON1b IMON1a SVIN1
IMON2b IMON2a SVIN2
PGOOD1 PGDFB1 VINREG1 GND
PGOOD2 PGDFB2 VINREG2 GND
VOUT2– SV
INF1 LDOIN
SVINF2 CLKOUT2
GND
COMP1b COMP1a fSET1 SVOUT1– VOUT1– COMP2b COMP2a fSET2 SVOUT2–
ISET1b ISET1a EXTVCC1 RUN1
ISET2b
VOUT1–
VOSNS1+ SVOUT1– INTVCC1
VOSNS1+ SVOUT1–
Channel 2 Terminal Voltages (All Channel 2 Terminal
Voltages Relative to VOUT2– Unless Otherwise Indicated)
VOUT1– CLKIN2 CLKOUT2
VD1
CLKIN1 CLKOUT1
NC
NC
VOUT1–
VOUT2–
VOSNS2+ SVOUT2– INTVCC2
H
J
VOUT2–
ISET2a EXTVCC2 RUN2
VOSNS2+ SVOUT2–
SW1
MOD
TEMP+ TEMP–
CLKSET
LDOOUT
SW2
VOUT2–
NC
NC
VOUT1–
K
VOUT1+
VOUT2–
VOUT2+
L
VOUT1–
M
1
2
3
4
5
6
7
8
9
10
11
12
BGA PACKAGE
144-LEAD (16mm × 16mm × 5.01mm)
TJ(MAX) = 125°C; θJA = 11.9°C/W;
θJCtop = 10°C/W; θJCbot = 2.6°C/W;
WEIGHT = 3.3 GRAMS
NOTES:
1) θ VALUES ARE DETERMINED BY SIMULATION PER JESD51 CONDITIONS.
2) θJA VALUE IS OBTAINED WITH DEMO BOARD.
3) REFER TO APPLICATION INFORMATION SECTION FOR LAB MEASUREMENT
AND DERATING INFORMATION.
LDOIN.......................................................... –0.3V to 42V
CLKSET, MOD............................–0.3V to LDOOUT + 0.3V
Terminal Currents
INTVCCn Peak Output Current (Note 10).................30mA
TEMP+.......................................................–1mA to 10mA
TEMP–......................................................–10mA to 1mA
Temperatures Internal Operating Temperature
Range (Note 2 and Note 9)
E- and I-Grade.................................... –40°C to 125°C
MP-Grade........................................... –55°C to 125°C
Storage Temperature Range................... –55°C to 125°C
Peak Package Body Temperature During Reflow... 245°C
Rev. B
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3
LTM4655
ORDER INFORMATION
PART MARKING*
PART NUMBER
PAD OR BALL FINISH
DEVICE
FINISH CODE
PACKAGE
TYPE
MSL
RATING
TEMPERATURE RANGE
(SEE NOTE 2)
LTM4655EY#PBF
SAC305 (RoHS)
LTM4655Y
e1
BGA
3
–40°C to 125°C
LTM4655IY#PBF
SAC305 (RoHS)
LTM4655Y
e1
BGA
3
–40°C to 125°C
LTM4655MPY#PBF
SAC305 (RoHS)
LTM4655Y
e1
BGA
3
–55°C to 125°C
LTM4655IY
SnPb (63/37)
LTM4655Y
e0
BGA
3
–40°C to 125°C
LTM4655MPY
SnPb (63/37)
LTM4655Y
e0
BGA
3
–55°C to 125°C
• Contact the factory for parts specified with wider operating temperature
ranges. *Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures
• LGA and BGA Package and Tray Drawings
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel (Note 5). TA = 25°C, Test Circuit 1 (positive-VOUT,
noninverting step-down configuration with VOUTn– = GND), VINn = SVINn = 36V, EXTVCCn = 24V, RUNn = 3.3V, RISETn = 480k, RfSETn+ =
57.6kΩ, fSWn = 1.5MHz (CLKINn driven with 1.5MHz clock signal) and voltages referred to GND unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
– = GND
SVINn(DC), VINn(DC)
Input DC Voltage in Positive-VOUT
Configuration
VOUTn
VOUTn(RANGE)+
Range of Positive Output Voltage
Regulation
0.5V ≤ ISETna–SVOUTn– ≤ 26.5V, IOUTn+ = 0A
(See Note 7)
VOUTn(24VDC)+
Output Voltage Total Variation with Line 29V ≤ VINn ≤ 40V, 0A ≤ IOUTn+ ≤ 4A, CINHn
and Load at VOUTn+ = 24V
= 4.7μF, CDn = 4.7μF, COUTHn = 2 × 47μF,
CLKINn Driven with 1.5MHz Clock
VOUTn(0.5VDC)+
Output Voltage Total Variation with Line Measuring VOSNSn+ to ISETna
and Load at VOUTn+ = 0.5V
3.1V ≤ VINn ≤ 13.2V, 0A ≤ IOUTn+ ≤ 4A, CINHn
= 4.7μF, CDn = 4.7μF, COUTHn = 2 × 47μF,
ISETna = 500mV, RfSETn = N/U (Note 6)
RSVINFn
Resistor Between SVINn and SVINFn
MIN
TYP
MAX
UNITS
l
3.1
40
V
l
0.5
26.5
V
l
23.6
24
24.4
V
l
–15
0
15
1
mV
Ω
Input Specifications
2.85
2.6
250
3.1
2.9
V
V
mV
VINn(UVLO)
SVINn Undervoltage Lockout Threshold
SVINn Rising
SVINn Falling
Hysteresis
IINRUSH(VINn)
Input Inrush Current at Start-Up
CINHn = 4.7μF, CDn = 4.7μF, COUTHn = 2 ×
47μF; IOUTn+ = 0A, ISETna Electrically
Connected to ISETnb
300
IQ(SVINn)
Input Supply Bias Current
Shutdown, RUNn = GND
RUNn = 3.3V
16
450
IS(VINn)
Input Supply Current
CLKINn Open Circuit, IOUTn+ = 4A
2.9
A
IS(VINn, SHUTDOWN)
Input Supply Current in Shutdown
Shutdown, RUNn = GND
4
µA
IOUTn+
VOUTn+ Output Continuous Current
Range
(Note 3)
∆VOUTn(LINE)+/
VOUTn+
Line Regulation Accuracy
IOUTn+ = 0A, 29V ≤ VINn ≤ 40V
l
∆VOUTn(LOAD)+/
VOUTn+
Load Regulation Accuracy
VINn = 36V, 0A ≤ IOUTn+ ≤ 4A
l
VOUTn(AC)+
Output Voltage Ripple, VOUTn+
VINn = 12V, ISETna = 5V
l
l
l
2.4
150
mA
30
μA
μA
Output Specifications
4
0
4
A
0.05
0.1
%
0.05
0.75
%
2
mVP-P
Rev. B
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LTM4655
The
l denotes the specifications which apply over the specified internal
ELECTRICAL
CHARACTERISTICS
operating temperature range (Note 2). Specified as each individual output channel (Note 5). TA = 25°C, Test Circuit 1 (positive-VOUTn+,
noninverting step-down configuration with VOUTn– = GND), VINn = SVINn = 36V, EXTVCCn = 24V, RUNn = 3.3V, RISETn = 480k, RfSETn+ =
57.6kΩ, fSWn = 1.5MHz (CLKINn driven with 1.5MHz clock signal) and voltages referred to GND unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
+ Ripple Frequency
RfSETn = 57.6k, CLKINn Open Circuit
MIN
TYP
MAX
1.7
1.95
2.2
UNITS
MHz
fSn
VOUTn
∆VOUTn(START)+
Turn-On Overshoot
tSTARTn
Turn-On Start-Up Time
Delay Measured from VINn Toggling from 0V l
to 36V to PGOODn Exceeding 3V; PGOODn.
Having a 100kΩ Pull-Up to 3.3V with Respect
to GND, VPGFBn Resistor Divider Network as
Shown in Test Circuit 1, RISETna = 480kΩ and
ISETna Electrically Connected to ISETnb and
CLKIN Driven with 1.5MHz Clock
∆VOUTn(LS)+
Peak Output Voltage Deviation for
Dynamic Load Step
IOUTn+: 0A to 2A and 2A to 0A Load Steps in
1μs, COUTHn = 47µF × 2
400
mV
tSETTLEn
Settling Time for Dynamic Load Step
IOUTn+: 0A to 2A and 2A to 0A Load Steps in
1μs, COUTHn = 47µF × 2
50
µs
IOUTn(OCL)+
IOUTn+ Output Current Limit
5.5
A
l
8
4
mV
9
ms
Control Section
IISETna
Reference Current of ISETna Pin
VISETna = 0.5V, 3.1V ≤ VINn ≤ 13.2V
VISETna = 24V, 29V ≤ VINn ≤ 40V
IVOSNSn+
VOSNSn+ Leakage Current
VVOSNSn+ = 28V
tONn(MIN)
Minimum On-Time
(Note 4)
VRUNn
RUNn Turn-On/-Off Thresholds
RUNn Input Turn-On Threshold, RUNn Rising l
RUNn Hysteresis
IRUNn
RUNn Leakage Current
RUNn = 3.3V
l
VINn = 12V, ISETna = 5V, and:
fSETn Open-Circuit
RfSETn = 57.6kΩ (See fSN Specification)
l
l
l
49.3
49
50
50
50.7
51
290
μA
60
1.08
µA
µA
ns
1.2
130
1.32
V
mV
0.1
50
nA
400
1.95
440
kHz
MHz
550
3
kHz
MHz
0.4
V
V
Oscillator and Phase-Locked Loop (PLL)
fOSCn
fSYNCn
Oscillator Frequency Accuracy
PLL Synchronization Capture Range
VINn = 12V, ISETna = 5V, CLKINn Driven with
a GND Referred Clock Toggling from 0.4V to
1.2V and Having a Clock Duty Cycle:
From 10% to 90%; fSETn Open Circuit
From 40% to 60%; RfSETn = 57.6kΩ
VCLKINn
CLKINn Input Threshold
VCLKINn Rising
VCLKINn Falling
ICLKINn
CLKINn Input Current
VCLKINn = 5V
VCLKINn = 0V
360
250
1.3
1.2
–20
230
–5
500
μA
μA
Power Good Feedback Input and Power Good Output
OVPGDFBn
Output Overvoltage PG00Dn Upper
Threshold
PGDFBn Rising
l
620
645
675
mV
UVPGDFBn
Output Undervoltage PGOODn Lower
Threshold
PGDFBn Falling
l
525
555
580
mV
∆VPGDFBn
PGOODn Hysteresis
PGDFBn Returning
RPGDFBn
Resistor Between PGDFB1n and SVOUTn–
RPGOODn
PGOODn Pull-Down Resistance
IPGOODn(LEAK)
PGOODn Leakage Current
8
4.94
mV
4.99
5.04
kΩ
VPGOODn = 0.1V, VPGDFBn < UVPGDFBn or
VPGDFBn > OVPGDFBn
700
1500
Ω
VPGOODn = 3.3V, UVPGDFBn < VPGDFBn <
OVPGDFBn
0.1
1
μA
Rev. B
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5
LTM4655
The
l denotes the specifications which apply over the specified internal
ELECTRICAL
CHARACTERISTICS
operating temperature range (Note 2). Specified as each individual output channel (Note 5). TA = 25°C, Test Circuit 1 (positive-VOUTn+,
noninverting step-down configuration with VOUTn– = GND), VINn = SVINn = 36V, EXTVCCn = 24V, RUNn = 3.3V, RISETn = 480k, RfSETn+ =
57.6kΩ, fSWn = 1.5MHz (CLKINn driven with 1.5MHz clock signal) and voltages referred to GND unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
tPGOODn(DELAY)
PGOODn Delay
PGOODn Low to High (Note 4)
PGOODn High to Low (Note 4)
MIN
TYP
MAX
UNITS
s
s
16/fSW(Hz)
64/fSW(Hz)
Current Monitor and Input Voltage Regulation Pins
hIMONna
IOUTn+/IIMONna
Ratio of VOUTn+ Output Current to IIMONna
Current, IOUTn+ = 4A
IOSn(IMON)
IIMONna Offset Current
IIMONna at IOUTn+ = 0A
IMONnb Resistor
Resistor Between IMONnb and SVOUTn–
9.8
VIMONna
IMONna Servo Voltage
IMONna Voltage During Output Current
Regulation
l
1.9
VVINREGn
VINREGn Servo Voltage
VINREGn Voltage During Output Current
Regulation
l
1.8
2.0
IVINREGn
VINREGn Leakage Current
VINREGn = 2V
VINTVCCn
Channel Internal VCC Voltage, No
INTVCCn Loading (IINTVCCn = 0mA)
3.6V ≤ SVINn ≤ 40V, EXTVCCn Open Circuit
5V ≤ SVINn ≤ 40V, 3.2V ≤ EXTVCCn ≤ 26.5V
VEXTVCCn(TH)
EXTVCCn Switchover Voltage
(Note 4)
∆VINTVCCn(LOAD)/
VINTVCCn
INTVCCn Load Regulation
0mA ≤ IINTVCCn ≤ 30mA
l
36
40
44
k
5
μA
10
10.2
kΩ
2.0
2.1
V
2.2
V
–5
1
nA
INTVCCn Regulator
3.15
2.85
3.4
3.0
3.65
3.15
V
V
3.15
–2
V
0.5
2
%
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel (Note 5). TA = 25°C, Test Circuit 2 (negativeVOUTn–, inverting buck-boost configuration with VOUTn+ = GND), VINn = 12V and electrically connected to SVINn, RUNn–GND = 3.3V,
ISETna–SVOUTn– = 24V, EXTVCCn = GND, CLKINn open circuit, RfSETn = 57.6kΩ and RISETn = 480kΩ and voltages referred to GND
unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
SVINn(DC), VINn(DC)
Input DC Voltage in
Negative-VOUT– Configuration
VINn+ |VOUTn–| ≤ 40V
l
3.6
40
V
VOUTn(RANGE)–
Range of Negative Output Voltage
Regulation
0.5V ≤ ISETna–SVOUTn– ≤ 26.5V
l
–26.5
–0.5
V
VOUTn(–24VDC)–
Output Voltage Total Variation with Line
and Load at VOUTn– = –24V
3.6V ≤ VINn ≤ 16V, 0A ≤ IOUTn– ≤ 0.3A, CLKINn
Driven per Note 8, CINHn = 4.7μF, CDn = 4.7μF × 2,
COUTHn = 47μF × 2
l
–24.4
–24
–23.6
V
VOUTn(–5VDC)–
Output Voltage Total Variation with Line
and Load at VOUTn– = –5V
Measuring VOSNSn+ – ISETna, 12V ≤ VINn ≤ 35V,
0A ≤ IOUT– ≤ 3A, CLKINn Driven by 550kHz Clock,
CINHn = 4.7μF, CDn = 4.7μF × 2, COUTHn = 47μF ×
2, ISETna–SVOUTn– = 5V
l
–15
0
15
RSVINFn
Resistor Between SVINn and SVINFn
6
MIN
TYP
1
MAX
UNITS
mV
Ω
Rev. B
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LTM4655
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel (Note 5). TA = 25°C, Test Circuit 2 (negativeVOUTn–, inverting buck-boost configuration with VOUTn+ = GND), VINn = 12V and electrically connected to SVINn, RUNn–GND = 3.3V,
ISETna–SVOUTn– = 24V, EXTVCCn = GND, CLKINn open circuit, RfSETn = 57.6kΩ and RISETn = 480kΩ and voltages referred to GND
unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
2.1
400
3.2
2.5
700
3.6
2.8
UNITS
VINn(UVLO)
SVINn Undervoltage Lockout Threshold
SVINn Rising
SVINn Falling
Hysteresis
IINRUSH(VINn)
Input Inrush Current at Start-Up
CINHn = 4.7μF, CDn = 4.7μF × 2, COUTHn = 47μF ×
2; IOUTn– = 0A, ISETna Electrically Connected to
ISETnb
1.1
IQ(SVINn)
Input Supply Bias Current
Shutdown, RUNn = GND
RUNn–GND = 3.3V
16
450
IS(VINn)
Input Supply Current
CLKINn Open Circuit, IOUTn– = 1.25A
3.0
A
IS(VINn, SHUTDOWN)
Input Supply Current in Shutdown
Shutdown, RUNn = GND
4
µA
IOUTn–
VOUTn– Output Continuous Current Range
VINn = 12V, Regulating VOUTn– = –24V at fSWn = 1MHz
VINn = 12V, Regulating VOUTn– = –5V at fSWn = 550kHz
(See Note 3. Capable of Up to 4A Output Current
for Some Combinations of VINn, VOUTn– and fSWn)
∆VOUTn(LINE)–/VOUTn–
Line Regulation Accuracy
IOUTn– = 0A, 3.6V ≤ VINn ≤ 16V, ISETna–SVOUTn– =
24V, CLKINn Driven by 1.8MHz Clock
∆VOUTn(LOAD)–/VOUTn–
Load Regulation Accuracy
VINn = 12V, 0A ≤ IOUTn– ≤ 1.25A, CLKINn Driven by
1.5MHz Clock, RfSETn = 57.6kΩ, and RISETn = 480kΩ
VOUTn(AC)–
Output Voltage Ripple, VOUTn–
VINn = 12V, ISETna–SVOUTn– = 5V
Input Specifications
l
l
l
V
V
mV
A
30
μA
μA
Output Specifications
– Ripple Frequency
– = 5V
0
0
1.25
3
A
A
l
0.05
0.25
%
l
0.05
0.75
%
10
fSN
VOUTn
∆VOUTn(START)–
Turn-On Overshoot
tSTARTn
Turn-On Start-Up Time
Delay Measured from VINn Toggling from 0V
to 12V to PGOODn Exceeding 3V Above GND;
PGOODn Having a 100kΩ Pull-Up to 3.3V with
Respect to GND, VPGFBn Resistor Divider Network
as Shown in Test Circuit 2, RISETna = 480kΩ,
ISETna Electrically Connected to ISETnb, and
CLKINn Driven with 1.2MHz Clock
∆VOUTn(LS)–
Peak Output Voltage Deviation for
Dynamic Load Step
IOUTn–: 0A to 1A and 1A to 0A Load Steps in 1μs,
COUTHn = 47µF × 2
400
mV
tSETTLEn
Settling Time for Dynamic Load Step
IOUTn–: 0A to 1A and 1A to 0A Load Steps in 1μs,
COUTH2 = 47µF × 2 X5R
50
µs
IOUTn(OCL)–
IOUTn– Output Current Limit
1.7
A
VINn = 12V, ISETna–SVOUTn
l
1.7
1.95
mVP-P
2.2
8
4
l
MHz
mV
9
ms
Control Section
IISETna
Reference Current of ISETna Pin
VISETna–SVOUTn– = 0.5V, 3.6V ≤ VINn ≤ 28V
0V ≤ VISETna–SVOUTn– ≤ VINn–SVOUT– ≤ 40V
IVOSNSn+
VOSNSn+ Leakage Current
VOSNSn+ – SVOUTn– = 28V
tONn(MIN)
Minimum On-Time
(Note 4 )
VRUNn
RUNn Turn-On/-Off Thresholds
RUNn Input Turn-On Threshold, RUNn Rising
RUNn Hysteresis
(RUNn Thresholds Measured with Respect to GND)
l
IRUNn
RUNn Leakage Current
VINn = 12V, RUNn–GND = 3.3V
l
l
l
49.3
49
1.08
50
50
50.7
51
µA
µA
290
μA
60
ns
1.2
130
1.32
V
mV
0.1
50
nA
Rev. B
For more information www.analog.com
7
LTM4655
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel (Note 5). TA = 25°C, Test Circuit 2 (negativeVOUTn–, inverting buck-boost configuration with VOUTn+ = GND), VINn = 12V and electrically connected to SVINn, RUNn–GND = 3.3V,
ISETna–SVOUTn– = 24V, EXTVCCn = GND, CLKINn open circuit, RfSETn = 57.6kΩ and RISETn = 480kΩ and voltages referred to GND
unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
360
400
1.95
440
kHz
MHz
550
3
kHz
MHz
0.4
V
V
Oscillator and Phase-Locked Loop (PLL)
fOSCn
fSYNCn
VINn = 12V, ISETna–SVOUTn– = 5V, and:
fSETn Open Circuit
RfSETn = 57.6kΩ (See fSN Specification)
Oscillator Frequency Accuracy
PLL Synchronization Capture Range
l
VINn = 12V, ISETna–SVOUTn– = 5V, CLKINn Driven
with a GND Referred Clock Toggling from 0.4V to
1.2V and Having a Clock Duty Cycle:
From 10% to 90%; fSETn Open Circuit
From 40% to 60%; RfSETn = 57.6kΩ
VCLKINn
CLKINn Input Threshold
VCLKINn Rising with Respect to GND
VCLKINn Falling with Respect to GND
ICLKINn
CLKINn Input Current
VCLKINn = 5V with Respect to GND
VCLKINn = 0V with Respect to GND
250
1.3
1.2
–20
230
–5
500
μA
μA
Power Good Feedback Input and Power Good Output
OVPGDFBn
Output Overvoltage PGOODn
Upper Threshold
PGDFBn Rising, Differential Voltage from PGDFBn
to SVOUTn–
l
620
645
675
mV
UVPGDFBn
Output Undervoltage PGOODn Lower
Threshold
PGDFBn Falling, Differential Voltage from PGDFBn
to SVOUTn–
l
525
555
580
mV
∆VPGDFBn
PGOODn Hysteresis
PGDFBn Returning
8
mV
RPGDFBn
Resistor Between PGDFBn and SVOUTn–
4.99
5.04
kΩ
RPGOODn
PGOODn Pull-Down Resistance
VPGOODn = 0.1V with Respect to GND,
VPGDFBn–SVOUTn– < UVPGDFBn or
VPGDFBn–SVOUTn– > OVPGDFBn
700
1500
Ω
IPGOODn(LEAK)
PGOODn Leakage Current
VPGOODn = 3.3V with Respect to GND,
UVPGDFBn < VPGDFBn–SVOUTn– < OVPGDFBn
0.1
1
μA
tPGOODn(DELAY)
PGOODn Delay
PGOODn Low to High (Note 4)
PGOODn High to Low (Note 4)
4.94
s
s
16/fSW(Hz)
64/fSW(Hz)
Input Voltage Regulation Pin
VVINREGn
VINREGn Servo Voltage
VINREGn Voltage During Output Current Regulation,
Measured with Respect to SVOUTn–
IVINREGn
VINREGn Leakage Current
VINREG–SVOUTn– = 2V
VINTVCCn
Channel Internal VCC Voltage, No
INTVCCn Loading (IINTVCCn = 0mA)
3.6V ≤ SVINn–SVOUTn– ≤ 40V, EXTVCCn = Open Circuit
5V ≤ SVINn–SVOUTn– ≤ 40V, 3.2V ≤ EXTVCCn–
VOUTn– ≤ 26.5V
(INTVCCn Measured with Respect to SVOUTn–)
VEXTVCCn(TH)
EXTVCCn Switchover Voltage
(EXTVCCn Measured with Respect to SVOUTn–)
(Note 4)
∆VINTVCCn(LOAD)/
VINTVCCn
INTVCCn Load Regulation
0mA ≤ IINTVCCn ≤ 30mA
l
1.8
2.0
2.2
1
V
nA
INTVCCn Regulator
8
3.15
2.85
3.4
3.0
3.65
3.15
3.15
–2
0.5
V
V
V
V
2
%
Rev. B
For more information www.analog.com
LTM4655
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2). TA = 25°C, Test Circuit 3 and voltages referred to GND unless otherwise noted.
SYMBOL
PARAMETER
LDOIN(DC)
VLDOOUT(DC)
LDO Input DC Voltage
LDO Output Voltage
VLDOOUT(AC)
Output Voltage Ripple
ILDOOUT(OCL)
Output Current Limit, 5V LDO
Clock Generator
∆fOUT
Clock-Generator Frequency Accuracy
RCLKSET(RANGE)
Frequency Setting Resistor Range
Period Variation (Frequency Spreading)
Duty Cycle
θCLKOUT1/
θCLKOUT2
VOH_CLKOUTn
Phase Relationship of CLKOUT2 to
CLKOUT1
CLKOUTn Output Voltage, Logic High
VOL_CLKOUTn
CLKOUTn Output Voltage, Logic Low
Temperature Sensor
∆VTEMP
Temperature Sensor Forward Voltage,
VTEMP+ to VTEMP–
TC∆V(TEMP)
∆VTEMP Temperature Coefficient
η
Ideality Factor
CONDITIONS
MIN
l
VLDOIN = 36V, 0mA ≤ ILDOOUT ≤ 25mA
VLDOIN = 4.5V, 0mA ≤ ILDOOUT ≤ 20mA
l
l
4.5
4.8
2.7
LDOIN = 36V
2.7V ≤ LDOOUT ≤ 5.2V, 200kHz ≤ fOUT ≤ 3MHz,
MOD Connected to CLKOUT2
RCLKSET Resistance for Which –7.5% ≤ ∆fOUT ≤
7.5%, Over 2.7V ≤ LDOOUT ≤ 5.2V,
MOD Electrically Connected to CLKOUT2
LDOOUT = 5V, RCLKSET = 100kΩ, MOD Open Circuit
2.7V ≤ LDOOUT ≤ 5.2V, 200kHz ≤ fOUT ≤ 3MHz,
MOD Electrically Connected to CLKOUT2
2.7V ≤ LDOOUT ≤ 5.2V, 200kHz ≤ fOUT ≤ 3MHz,
MOD Electrically Connected to CLKOUT2
CLKOUTn VOH Measured with Respect to LDOOUT,
2.7V ≤ LDOOUT ≤ 5.2V, ICLKOUTn = –100μA
CLKOUTn VOL Measured with Respect to GND, 2.7V
≤ LDOOUT ≤ 5.2V, ICLKOUTn = 100μA
ITEMP+ = 100µA and ITEMP– = –100μA at TA = 25°C
Note 1: Stresses beyond those listing under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating conditions for extended periods may affect device
reliability and lifetime.
Note 2: The LTM4655 is tested under pulsed load conditions such that TJ ≈
TA. The LTM4655E is guaranteed to meet performance specifications over
the 0°C to 125°C internal operating temperature range. Specifications over
the full –40°C to 125°C internal operating temperature range are assured by
design, characterization and correlation with statistical process controls.
The LTM4655I is guaranteed to meet specifications over the full –40°C to
125°C internal operating temperature range. The LTM4655MP is tested and
guaranteed over the full –55°C to 125°C operating temperature range. Note
that the maximum ambient temperature consistent with these specifications
is determined by specific operating conditions in conjunction with board
layout, the rated package thermal resistance and other environmental factors.
Note 3: See output current derating curves for different VIN, VOUT, and TA,
located in the Applications Information section.
Note 4: Minimum on-time, PGOOD delay, and EXTVCCn switchover
threshold are tested at wafer sort.
Note 5: The two power inputs—VIN1 and VIN2—and their respective
power outputs—VOUT1+ or VOUT1–, and VOUT2+ or VOUT2–, depending on
operational configuration—are tested independently in production, in both
positive-VOUT (noninverting step-down) and negative-VOUT– (inverting
buck-boost) configurations. On occasion, a shorthand notation is used in
this document that allows VINn to refer to both VIN1 and VIN2 by virtue of n
being permitted to take on a value of 1 or 2. This italicized n notation and
convention is extended to all such pin names.
TYP
5.0
4.1
2
140
±2.5
±2.5
l
l
33.2
l
40
MAX
40
5.2
UNITS
V
V
V
mVP-P
mA
±7.5
±3
499
%
%
kΩ
60
%
%
±10
180
Deg
–0.4
V
0.4
V
0.598
V
–2.0
1.004
mV/°C
Note 6: To ensure minimum on-time criteria is met, VOUTn (0.5VDC)+ high
line regulation is tested at 13.2VIN, with fSETn and CLKINn open circuit.
VOUTn (–0.5VDC)– low line regulation is tested at 3.6VIN, with fSETn and
CLKINn open circuit.
VOUTn (–0.5VDC)– high line regulation is tested at 28VIN, and with CLKINn
driven at 200kHz—so as to ensure minimum on-time criteria is met.
The LTM4655 is not recommended for applications where the minimum
on-time criteria (guardband to 90ns) is continuously violated. The
LTM4655 can ride through events (such as VIN surge) where the on-time
criteria is transiently violated. See the Applications Information section.
Note 7: See the Applications Information section for dropout criteria.
Note 8: VOUTn (–24VDC)– is tested at 3.6VIN and 16VIN, with CLKINn
driven with a 1.8MHz clock, ISETna to SVOUTn– = 12V, and RfSET = 57.6k.
It is also tested at 12VIN, with CLKINn driven with a 1.5MHz clock, RfSETn
= 57.6k, and RISETn = 480k.
Note 9: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 10: The INTVCCn Abs Max peak output current is specified as the sum
of current drawn by circuits internal to the module biased off of INTVCCn
and current drawn by external circuits biased off of INTVCCn. Specified
independently, for each channel. See the Applications Information section.
For more information www.analog.com
Rev. B
9
LTM4655
TYPICAL PERFORMANCE CHARACTERISTICS
95
TA = 25°C, single channel positive-VOUTn+
operation only, unless otherwise noted.
Efficiency vs Load Current at
12VIN, Forced Continuous Mode
Efficiency vs Load Current at
5VIN, Forced Continuous Mode
Efficiency vs Load Current at
15VIN, Forced Continuous Mode
100
95
90
90
85
85
95
80
3.3VOUT, 400kHz
2.5VOUT, 400kHz
1.8VOUT, 400kHz
1.5VOUT, 400kHz
1.2VOUT, 400kHz
1.0VOUT, 400kHz
75
70
65
0.5
1.0
1.5
2.0
2.5
80
75
70
3.0
LOAD CURRENT (A)
3.5
65
0.5
4.0
90
90
EFFICIENCY (%)
EFFICIENCY (%)
95
85
80
75
1.5
2.0
1.8VOUT, 400kHz
1.5VOUT, 400kHz
1.2VOUT, 400kHz
1.0VOUT, 400kHz
2.5
3.0
3.5
4.0
2.5
3.0
3.5
4.0
60
0.5
1.0
1.5
2.0
1.2VOUT, 400kHz
1.0VOUT, 400kHz
2.5
3.0
3.5
LOAD CURRENT (A)
4.0
4655 G03
1V Transient Response, 24VIN
VOUTn+
50mV/DIV
AC-COUPLED
85
80
75
IOUTn+
2A/DIV
24VOUT, 1.2MHz
15VOUT, 1.2MHz
12VOUT, 1.1MHz
5VOUT, 575kHz
65
60
55
0.5
1.0
1.5
2.0
3.3VOUT, 400kHz
2.5VOUT, 400kHz
1.8VOUT, 400kHz
1.5VOUT, 400kHz
2.5
3.0
3.5
4.0
LOAD CURRENT (A)
LOAD CURRENT (A)
4655 G05
4655 G04
10
65
1.2VOUT, 400kHz
1.0VOUT, 400kHz
70
15VOUT, 750kHz
12VOUT, 800kHz
5.0VOUT, 550kHz
3.3VOUT, 400kHz
2.5VOUT, 400kHz
1.0
2.0
12VOUT, 500kHz
5.0VOUT, 450kHz
3.3VOUT, 400kHz
2.5VOUT, 400kHz
1.8VOUT, 400kHz
1.5VOUT, 400kHz
70
Efficiency vs Load Current at
36VIN, Forced Continuous Mode
95
55
0.5
1.5
75
4655 G02
100
60
1.0
80
LOAD CURRENT (A)
100
65
5.0VOUT, 400kHz
3.3VOUT, 400kHz
2.5VOUT, 400kHz
1.8VOUT, 400kHz
1.5VOUT, 400kHz
4655 G01
Efficiency vs Load Current at
24VIN, Forced Continuous Mode
70
85
EFFICIENCY (%)
EFFICIENCY (%)
EFFICIENCY (%)
90
40µs/DIV
FIGURE 51 CIRCUIT, 24VIN,
CINHn = CDn = 4.7µF, COUTn = 3 x 100µF,
RfSETn = N/A, RISETn = 20kΩ,
CTHn = 6.8nF, RTHn = 681Ω,
REXTVCCn = N/A, CEXTVCCn = N/A,
2A to 4A LOAD STEP AT 2A/µs
4655 G06
Rev. B
For more information www.analog.com
LTM4655
TYPICAL PERFORMANCE CHARACTERISTICS
Start-Up, No Load
Start-Up, Pre-Bias
Start-Up, 4A Load
RUNn
2V/DIV
RUNn
2V/DIV
VOUTn+
5V/DIV
VOUTn+
5V/DIV
PGOODn
2V/DIV
PGOODn
2V/DIV
2ms/DIV
FIGURE 51 CIRCUIT, 36VIN,
CINHn = CDn = 4.7µF, COUTn = 2 x 22µF,
RfSETn = 124k, RISETn = 240kΩ,
RPGDFBn = 95.3kΩ,
CTHn = 10nF, RTHn = 562Ω,
REXTVCCn = 49.9Ω, CEXTVCCn = 1µF,
NO LOAD
TA = 25°C, single channel positive-VOUTn+
operation only, unless otherwise noted.
4655 G07
RUNn
2V/DIV
VOUTn+
5V/DIV
IDIODEn
1mA/DIV
PGOODn
2V/DIV
2ms/DIV
FIGURE 51 CIRCUIT, 36VIN,
CINHn = CDn = 4.7µF, COUTn = 2 x 22µF,
RfSETn = 124k, RISETn = 240kΩ,
RPGDFBn = 95.3kΩ,
CTHn = 10nF, RTHn = 562Ω,
REXTVCCn = 49.9Ω, CEXTVCCn = 1µF,
3Ω RESISTIVE LOAD
Short Circuit, No Load
4655 G08
2ms/DIV
FIGURE 51 CIRCUIT, 36VIN,
CINHn = CDn = 4.7µF, COUTn = 2 x 22µF,
RfSETn = 124k, RISETn = 240kΩ,
RPGDFBn = 95.3kΩ,
CTHn = 10nF, RTHn = 562Ω,
REXTVCCn = 49.9Ω, CEXTVCCn = 1µF,
VOUTn+ PRE-BIASED TO 5V
THROUGH 1N4148 DIODE
4655 G09
Short Circuit, 4A Load
VOUTn+
5V/DIV
VOUTn+
5V/DIV
IINn
1A/DIV
IINn
1A/DIV
10µs/DIV
FIGURE 51 CIRCUIT, 36VIN,
CINHn = CDn = 4.7µF, COUTn = 2 x 22µF,
RfSETn = 124k, RISETn = 240kΩ,
RPGDFBn = 95.3kΩ,
CTHn = 10nF, RTHn = 562Ω,
REXTVCCn = 49.9Ω, CEXTVCCn = 1µF,
NO LOAD PRIOR TO APPLICATION
OF OUTPUT SHORT-CIRCUIT
4655 G10
10µs/DIV
FIGURE 51 CIRCUIT, 36VIN,
CINHn = CDn = 4.7µF, COUTn = 2 x 22µF,
RfSETn = 124k, RISETn = 240kΩ,
RPGDFBn = 95.3kΩ,
CTHn = 10nF, RTHn = 562Ω,
REXTVCCn = 49.9Ω, CEXTVCCn = 1µF,
4Ω RESISTIVE LOAD PRIOR TO
APPLICATION OF OUTPUT
SHORT-CIRCUIT
4655 G11
Rev. B
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11
LTM4655
TYPICAL PERFORMANCE CHARACTERISTICS
–3.3V Efficiency vs Load Current
Output
Current
Capability*
OUTPUT
CURRENT
CAPABILITY*
95
2.0
VOUT– = –0.5V
VOUT– = –3.3V
VOUT– = –5V
VOUT– = –8V
VOUT– = –12V
VOUT– = –15V
VOUT– = –20V
VOUT– = –24V
1.5
1.0
0.5
0
0
5
10
15 20 25 30
INPUT VOLTAGE (V)
35
85
80
75
70
40
0
1
2
3
LOAD CURRENT (A)
–12V Efficiency vs Load Current
4
0
1
2
3
LOAD CURRENT (A)
4
4651 G14
–15V Efficiency vs Load Current
EFFICIENCY (%)
EFFICIENCY (%)
70
90
80
75
5VIN, 475kHz
12VIN, 825kHz
24VIN, 1.1MHz
0
0.5
1
1.5
2
2.5
LOAD CURRENT (A)
3
85
80
75
70
3.5
5VIN, 500kHz
12VIN, 875kHz
24VIN, 1.2MHz
0
0.5
1
1.5
2
LOAD CURRENT (A)
4651G15h
2.5
3
4655 G16
–24V Efficiency vs Load Current
Rated Operating Output Voltage
95
0
–5
OUTPUT VOLTAGE (V)
90
EFFICIENCY (%)
5VIN, 400kHz
12VIN, 550kHz
24VIN, 600kHz
36VIN, 600kHz
95
85
85
80
75
70
80
4651 G13
90
70
85
75
4655 G12
95
90
EFFICIENCY (%)
90
3.0
–5V Efficiency vs Load Current
95
5VIN, 400kHz
12VIN, 400kHz
24VIN, 450kHz
36VIN, 500kHz
3.5
EFFICIENCY (%)
CHANNEL OUTPUT CURRENT (A)
4.0
2.5
TA = 25°C, single channel negative-VOUTn–
operation only, unless otherwise noted.
0.5
1
1.5
LOAD CURRENT (A)
SAFE OPERATING AREA
–15
–20
–25
5VIN, 550kHz
12VIN, 1MHz
0
–10
2
–30
0
4655 G17
5
10
15 20 25 30
INPUT VOLTAGE (V)
35
40
4655 G18
*Current limit frequency-foldback activates at load currents higher than indicated curves. Continuous channel output current capability subject to details of
application implementation. Switching frequency set per Table 1. See Notes 2 and 3.
12
Rev. B
For more information www.analog.com
LTM4655
TYPICAL PERFORMANCE CHARACTERISTICS
–5V Transient Response, 24VIN
Start-Up, No Load
–24V Transient Response, 12VIN
VOUTn–
100mV/DIV
AC-COUPLED
VOUTn–
100mV/DIV
AC-COUPLED
IOUTn–
1A/DIV
IOUTn–
0.4A/DIV
40μs/DIV
TA = 25°C, single channel negative-VOUTn–
operation only, unless otherwise noted.
VINn
5V/DIV
VOUTn–
10V/DIV
RUNn
2V/DIV
PGOODn
5V/DIV
4655 G20
20μs/DIV
4655 G19
1ms/DIV
FIGURE 48 CIRCUIT,
0.625A TO 1.25A LOAD STEP AT 0.625A/μs
FIGURE 48 CIRCUIT, 24VIN,
CINOUTn = CINHn = CDGNDn = CDn = 4.7μF,
COUTn = 47μF ×2, RfSETn = 665kΩ,
RISETn = 100kΩ, RPGDFBn = 36.5kΩ,
REXTVCCn = 20Ω, 1.8A TO 3.8A LOAD STEP AT 2A/μs
Start-Up, 1.25A Load
4655 G21
FIGURE 48 CIRCUIT, APPLICATION OF 12VIN,
START-UP INTO NO LOAD
Start-Up, Pre-Bias
VINn
5V/DIV
VOUTn–
10V/DIV
VOUTn–
10V/DIV
IDIODEn
100mA/DIV
IOUTn–
500mA/DIV
RUNn
2V/DIV
PGOODn
2V/DIV
PGOODn
5V/DIV
4655 G22
1ms/DIV
1ms/DIV
4655 G23
FIGURE 48 CIRCUIT, APPLICATION OF 12VIN,
START-UP INTO 19.2Ω LOAD
FIGURE 48 CIRCUIT, VOUTn– PRE-BIASED
TO –5V THROUGH A 1N4148 DIODE PRIOR
TO RUNn TOGGLING HIGH
Short Circuit, No Load
Short Circuit, 1.25A Load
VOUTn–
10V/DIV
VOUTn–
10V/DIV
IINn
10A/DIV
IINn
10A/DIV
10μs/DIV
4655 G24
10μs/DIV
FIGURE 48 CIRCUIT,
NO LOAD PRIOR TO APPLICATION OF
VOUTn– SHORT-CIRCUIT
4655 G25
FIGURE 48 CIRCUIT,
19.2Ω LOAD PRIOR TO APPLICATION OF
VOUTn– SHORT-CIRCUIT
Rev. B
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13
LTM4655
PIN FUNCTIONS
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
VIN1 (A1–A3, B3): Channel 1 Power Input Pins. Apply
input voltage and input decoupling capacitance directly
between VIN1 and a power ground (PGND) plane. Either
connect PGND to VOUT1– in noninverting step-down applications, where VOUT1+ is the regulated positive output
voltage—or, connect PGND to VOUT1+ in inverting buckboost applications, where VOUT1– is the regulated negative
output voltage.
VD1 (A4, B4, C4): Drain of Channel 1’s Primary Switching
MOSFET. Apply at least one 4.7μF high frequency ceramic
decoupling capacitor directly from VD1 to VOUT1–. Give
this capacitor higher layout priority (closer proximity to
the module) than any VIN1 decoupling capacitors.
VOUT1– (A5, B5, C5, D5, E5, F5, G4–5, H3, H5, J3–5,
K4–5, L4–5, M4–5): Negative Power Output of Channel 1.
Either connect VOUT1– to a PGND plane in noninverting
step-down applications, where VOUT1+ is the regulated
positive output voltage—or, connect VOUT1+ to PGND in
inverting buck-boost applications, where VOUT1– is the
regulated negative output voltage.
VIN2 (A6–A8, B8): Channel 2 Power Input Pins. Apply
input voltage and input decoupling capacitance directly
between VIN2 and a power ground (PGND) plane. Either
connect PGND to VOUT2– in noninverting step-down applications, where VOUT2+ is the regulated positive output
voltage—or, connect PGND to VOUT2+ in inverting buckboost applications, where VOUT2– is the regulated negative
output voltage.
VD2 (A9, B9, C9): Drain of Channel 2’s Primary Switching
MOSFET. Apply at least one 4.7μF high frequency ceramic
decoupling capacitor directly from VD2 to VOUT2–. Give
this capacitor higher layout priority (closer proximity to
the module) than any VIN2 decoupling capacitors.
VOUT2– (A10–12, B10, C10, D10–11, E10–11, F10–11,
G9–11, H8, H10–12, J8–10, K9–12, L9–12, M9–12):
Negative Power Output of Channel 2. Either connect
VOUT2– to a PGND plane in noninverting step-down
applications, where VOUT2+ is the regulated positive output voltage—or, connect VOUT2+ to PGND in inverting
14
buck-boost applications, where VOUT2– is the regulated
negative output voltage.
CLKIN1 (B1): Channel 1 Mode Select and Oscillator
Synchronization Input. Referred to GND. Leave CLKIN1
open circuit for forced continuous mode operation.
Alternatively, this pin can be driven so as to synchronize
the switching frequency of channel 1 to a clock signal.
In this condition, channel 1 operates in forced continuous mode and the cycle-by-cycle turn-on of its primary
MOSFET is coincident with the rising edge of the clock
applied to CLKIN1. Note the synchronization range of
CLKIN1 is approximately ±40% of the oscillator frequency
programmed by the fSET1 pin. (See the Applications
Information section.) The LTM4655 contains a built-in
dual 180° out-of-phase clock generator. Electrically connect CLKIN1 to CLKOUT1 with a short trace, if desired,
to synchronize the switching frequency of channel 1
to CLKOUT1. If 0° phase interleaving is desired, connect
CLKOUT1 to both CLKIN1 and CLKIN2.
CLKOUT1 (B2): Squarewave Output of Clock Generator for
Channel 1. 180° out-of-phase from CLKOUT2. Minimize
stray capacitance to this pin. Connect CLKOUT1 to
CLKIN1, if desired, to synchronize channel 1 to CLKOUT1.
If 0° phase interleaving is desired, connect CLKOUT1 to
both CLKIN1 and CLKIN2.
CLKIN2 (B6): Channel 2 Mode Select and Oscillator
Synchronization Input. Referred to GND. Leave CLKIN2
open circuit for forced continuous mode operation.
Alternatively, this pin can be driven so as to synchronize
the switching frequency of channel 2 to a clock signal. In
this condition, channel 2 operates in forced continuous
mode and the cycle-by-cycle turn-on of its primary
MOSFET is coincident with the rising edge of the clock
applied to CLKIN2. Note the synchronization range of
CLKIN2 is approximately ±40% of the oscillator frequency
programmed by the fSET2 pin. (See the Applications
Information section.) The LTM4655 contains a built-in
dual 180° out-of-phase clock generator. Electrically
connect CLKIN2 to CLKOUT2 with a short trace, if desired,
to synchronize the switching frequency of channel 2
to CLKOUT2. If 0° phase interleaving is desired, connect
CLKOUT1 to both CLKIN1 and CLKIN2.
Rev. B
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LTM4655
PIN FUNCTIONS
CLKOUT2 (B7, C12): Squarewave Output of Clock
Generator for Channel 2. 180° out-of-phase from
CLKOUT1. Minimize stray capacitance to these pins.
Connect CLKOUT2 (pin B7, only) to CLKIN2, if desired,
to synchronize channel 2 to CLKOUT2. If 0° phase interleaving is desired, connect CLKOUT1 to both CLKIN1 and
CLKIN2.
To disable spread spectrum frequency modulation
(SSFM), connect CLKOUT2 (pin C12, only) to the MOD
pin (pin E12) with a short trace.
The CLKOUT2 pins at locations B7 and C12 are electrically connected together by a signal trace internal to the
module. It is pinned out as described purely to facilitate
routing of short traces to CLKIN2 and MOD. CLKOUT2
should be routed with minimal trace lengths. Minimize
stray capacitance to these pins.
SVINF1 (B11): Channel 1 Filtered Voltage Supply for Small
Signal Circuits. If powering the LTM4655’s 5V LDO from
channel 1’s supply for small signal circuits, electrically
connect SVINF1 and LDOIN with a short trace capable of
carrying up to 25mA.
LDOIN (B12): Input to 5V LDO. Connect LDOIN to either
SVINF1 or SVINF2 with a short trace capable of carrying up
to 25mA, depending on which input rail is better suited
for powering the 5V LDO. If LDOIN is being powered from
SVINF1 or SVINF2, no bypass capacitance from LDOIN to
GND is needed; otherwise, 0.1μF-to-1μF local bypass
capacitance is recommended.
IMON1b (C1): Channel 1 Power Inductor Analog Indicator
Current Default Termination R-C Network. A 10k resistor in parallel with a 10nF capacitor and terminating to
SVOUT1– connect to this pin. Connect IMON1b to IMON1a
to achieve default power inductor analog indicator current
characteristics: 1V (with respect to SVOUT1–) at full-scale
(4A) load current in positive-VOUT, noninverting stepdown applications. (See IMON1a.) If unused, IMON1b
can be left open circuit or connected to SVOUT1–.
IMON1a (C2): Channel 1 Power Inductor Current Analog
Indicator Pin and Current Limit Programming Pin. In
positive-VOUT step-down applications, only, the current
flowing out of this pin is equal to 1/40,000 of the average
channel 1 power inductor current. Optionally apply a parallel resistor-capacitor network to this pin and terminate
it to SVOUT1– in order to construct a voltage (VIMON1a–
SVOUT1–) that is proportional to channel 1’s power inductor current.
IMON1a can be connected to IMON1b if the default resistor capacitor termination network provided by IMON1b is
desired. If this analog indicator feature is not desired—
or, in negative-VOUT– buck-boost applications: connect
IMON1a to SVOUT1–.
If IMON1a–SVOUT1– exceeds a trip threshold of approximately 2V, an IMON1 control loop servos channel 1
power inductor current accordingly and thus regulates
IMON1a–SVOUT1– at 2V. In this manner, the current limit
inception threshold of channel 1 can be configured. (See
the Applications Information section.)
SVIN1 (C3): Channel 1 Input Voltage Supplies for Small
Signal Circuits. SVIN1 is the input to the INTVCC1 LDO.
Connect SVIN1 directly to VIN1.
IMON2b (C6): Channel 2 Power Inductor Analog Indicator
Current Default Termination R-C Network. A 10k resistor in parallel with a 10nF capacitor and terminating to
SVOUT2– connect to this pin. Connect IMON2b to IMON2a
to achieve default power inductor analog indicator current
characteristics: 1V (with respect to SVOUT2–) at full-scale
(4A) load current in positive-VOUT, noninverting stepdown applications. (See IMON2a.) If unused, IMON2b
can be left open circuit or connected to SVOUT2–.
IMON2a (C7): Channel 2 Power Inductor Current Analog
Indicator Pin and Current Limit Programming Pin. In
positive-VOUT step-down applications, only, the current
flowing out of this pin is equal to 1/40,000 of the average
channel 2 power inductor current. Optionally apply a parallel resistor-capacitor network to this pin and terminate
it to SVOUT2– in order to construct a voltage (VIMON2a–
SVOUT2–) that is proportional to channel 2’s power inductor current.
IMON2a can be connected to IMON2b if the default resistor capacitor termination network provided by IMON2b is
Rev. B
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15
LTM4655
PIN FUNCTIONS
desired. If this analog indicator feature is not desired—
or, in negative-VOUT– buck-boost applications: connect
IMON2a to SVOUT2–.
inductor current accordingly and thus regulates VINREG1
at 2V with respect to SVOUT1–. (See the Applications
Information section.)
If IMON2a–SVOUT2– exceeds a trip threshold of approximately 2V, an IMON2 control loop servos channel 2
power inductor current accordingly and thus regulates
IMON2a–SVOUT2– at 2V. In this manner, the current limit
inception threshold of channel 2 can be configured. (See
the Applications Information section.)
If this input voltage regulation feature is not desired on
channel 1, connect VINREG1 to INTVCC1.
SVIN2 (C8): Channel 2 Input Voltage Supplies for Small
Signal Circuits. SVIN2 is the input to the INTVCC2 LDO.
Connect SVIN2 directly to VIN2.
SVINF2 (C11): Channel 2 Filtered Voltage Supply for Small
Signal Circuits. If powering the LTM4655’s 5V LDO from
channel 2’s supply for small signal circuits, electrically
connect SVINF2 and LDOIN with a short trace capable of
carrying up to 25mA.
PGOOD1 (D1): Channel 1 Power Good Indicator, OpenDrain Output Pin. PGOOD1 is high impedance when
PGDFB1–SVOUT1– is within approximately ±7.5% of
0.6V. PGOOD1 is pulled to GND when PGDFB1 is outside
this range.
PGDFB1 (D2): Channel 1 Power Good Feedback
Programming Pin. Connect PGDFB1 to VOSNS1+ through a
resistor, RPGDFB1. RPGDFB1 configures the voltage threshold of (VOUT1+ – VOUT1–) for which PGOOD1 toggles its
state. If the PGOOD1 feature is used, set RPGDFB1 to:
RPGDFB1 =
VOUT1+ – VOUT1–
– 1 • 4.99k
0.6V
(1)
Otherwise, leave PGDFB1 open circuit.
A small filter capacitor (220pF) internal to the LTM4655
on this pin provides high frequency noise immunity for
the PGOOD1 output indicator.
VINREG1 (D3): Channel 1 Input Voltage Regulation
Programming Pin. Optionally connect this pin to the
midpoint node formed by a resistor divider between VD1
and VOUT1–. If VINREG1–SVOUT1– falls below approximately 2V, a VINREG1 control loop servos the power
16
GND (D4, D9, D12): Ground Pins. The logic thresholds
for RUNn, PGOODn, and CLKINn are electrically referred
to GND. GND is also the reference voltage for the 5V-fixed
LDO and the CLKOUTn clock generator. Connect all GND
pins to a solid ground plane, PGND.
PGOOD2 (D6): Channel 2 Power Good Indicator, OpenDrain Output Pin. PGOOD2 is high impedance when
PGDFB2–SVOUT2– is within approximately ±7.5% of
0.6V. PGOOD2 is pulled to GND when PGDFB2 is outside
this range.
PGDFB2 (D7): Channel 2 Power Good Feedback
Programming Pin. Connect PGDFB2 to VOSNS2+ through a
resistor, RPGDFB2. RPGDFB2 configures the voltage threshold of (VOUT2+ – VOUT2–) for which PGOOD2 toggles its
state. If the PGOOD2 feature is used, set RPGDFB2 according to Equation 2.
+
⎡V
– VOUT2– ⎤
RPGDFB2 = ⎢ OUT2
– 1⎥ • 4.99k
0.6V
⎢
⎥⎦
⎣
(2)
Otherwise, leave PGDFB2 open circuit.
A small filter capacitor (220pF) internal to the LTM4655
on this pin provides high frequency noise immunity for
the PGOOD2 output indicator.
VINREG2 (D8): Channel 2 Input Voltage Regulation
Programming Pin. Optionally connect this pin to the midpoint node formed by a resistor divider between VD2 and
VOUT2–. If VINREG2–SVOUT2– falls below approximately
2V, a VINREG2 control loop servos the power inductor
current accordingly and thus regulates VINREG2 at 2V
with respect to SVOUT2–. (See the Applications Information
section.)
If this input voltage regulation feature is not desired on
channel 2, connect VINREG2 to INTVCC2.
Rev. B
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LTM4655
PIN FUNCTIONS
COMP1b (E1): Channel 1 Internal Loop Compensation
Network. For a majority of applications, the internal,
default loop compensation of the LTM4655 is suitable to
apply “as is”, and yields very satisfactory results: apply
the default loop compensation to channel 1’s control loop
by simply connecting COMP1a to COMP1b. When more
specialized applications require a personal touch to the
optimization of control loop response, this can be easily
accomplished by connecting a series resistor-capacitor
network from COMP1a to SVOUT1– and leaving COMP1b
open circuit.
COMP2b (E6): Channel 2 Internal Loop Compensation
Network. For a majority of applications, the internal,
default loop compensation of the LTM4655 is suitable to
apply “as is”, and yields very satisfactory results: apply
the default loop compensation to channel 2’s control loop
by simply connecting COMP2a to COMP2b. When more
specialized applications require a personal touch to the
optimization of control loop response, this can be easily
accomplished by connecting a series resistor-capacitor
network from COMP2a to SVOUT2– and leaving COMP2b
open circuit.
COMP1a (E2): Current Control Threshold and Error
Amplifier Compensation Node for Channel 1. The trip
threshold of channel 1’s current comparator increases
with a respective rise in COMP1a voltage. A small filter
cap (10pF) internal to the LTM4655 on this pin introduces
a high frequency roll-off of the error amplifier response,
yielding good noise rejection in the control loop. Often,
COMP1a is electrically connected to COMP1b in one’s
application, thus applying default loop compensation.
Loop compensation (a series resistor capacitor) can be
applied externally from COMP1a to SVOUT1–, if desired or
needed, instead. (See COMP1b.)
COMP2a (E7): Current Control Threshold and Error
Amplifier Compensation Node for Channel 2. The trip
threshold of channel 2’s current comparator increases
with a respective rise in COMP2a voltage. A small filter
cap (10pF) internal to the LTM4655 on this pin introduces
a high frequency roll-off of the error amplifier response,
yielding good noise rejection in the control loop. Often,
COMP2a is electrically connected to COMP2b in one’s
application, thus applying default loop compensation.
Loop compensation (a series resistor capacitor) can be
applied externally from COMP2a to SVOUT2–, if desired or
needed, instead. (See COMP2b.)
fSET1 (E3): Channel 1 Oscillator Frequency Programming
Pin. The default switching frequency of channel 1 is
400kHz. If needed, the programmed frequency can be
increased by connecting a resistor between fSET1 and
SVOUT1–. Keep fSET1-related trace lengths short. (See the
Applications Information section.) Note the synchronization range of CLKIN1 is approximately ±40% of the oscillator frequency programmed by this fSET1 pin.
fSET2 (E8): Channel 2 Oscillator Frequency Programming
Pin. The default switching frequency of channel 2 is
400kHz. If needed, the programmed frequency can be
increased by connecting a resistor between fSET2 and
SVOUT2–. Keep fSET2-related trace lengths short. (See the
Applications Information section.) Note the synchronization range of CLKIN2 is approximately ±40% of the oscillator frequency programmed by this fSET2 pin.
SVOUT1– (E4, G2, H2): Signal Return of Channel 1. The
SVOUT1– pins are the reference node for channel 1’s control loop. A small island of SVOUT1– copper should be
extended from the module and used to shield sensitive
channel 1 pins and signals from noise—such as those
routing to fSET1, ISET1a/b, and COMP1a/b. All SVOUT1–
pins are connected to each other internal to the module.
Connect Pin H2 to VOUT1– directly under the LTM4655.
The remaining SVOUT1– pins can be used for redundant
connectivity or routed to an ICT test point for designfor-test considerations, as desired. See the Applications
Information section for the layout checklist.
SVOUT2– (E9, G7, H7): Signal Return of Channel 2. The
SVOUT2– pins are the reference node for channel 2’s control loop. A small island of SVOUT2– copper should be
extended from the module and used to shield sensitive
channel 2 pins and signals from noise—such as those
routing to fSET2, ISET2a/b, and COMP2a/b. All SVOUT2–
pins are connected to each other internal to the module.
Connect Pin H7 to VOUT2– directly under the LTM4655.
The remaining SVOUT2– pins can be used for redundant
connectivity or routed to an ICT test point for designfor-test considerations, as desired. See the Applications
Information section for the layout checklist.
Rev. B
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17
LTM4655
PIN FUNCTIONS
MOD (E12): Modulation Setting Input. This three-state
input selects among four modulation rate settings. The
MOD pin should be tied to GND for the fOUT/16 modulation
rate. Leaving the MOD pin open circuit selects the fOUT/32
modulation rate. The MOD pin should be electrically
connected to LDOOUT for the fOUT/64 modulation rate.
Electrically connecting CLKOUT2 (pin C12, only) to the
MOD pin (pin E12) turns the modulation off. Do not route
high speed digital logic or signals with fast edges near
MOD. Be advised that the fOUT/16, fOUT/32 and fOUT/64
modulation rates are not explicitly tested in factory ATE
to demonstrate their stated typical modulation rates; the
modulation off setting, however, is.
ISET1b (F1): 1.5nF Soft-Start Capacitor for Channel 1.
Connect ISET1b to ISET1a to achieve default soft-start
characteristics on channel 1, if desired. See ISET1a.
ISET1a (F2): Accurate 50μA Current Source. Positive
input to the error amplifier of channel 1. Connect a resistor RISET1a = ((VOUT1+ – VOUT1–)/50μA) from this pin
to SVOUT1– local to the module to program the desired
channel 1 output voltage magnitude, VOUT1+ – VOUT1–. A
capacitor can be connected from ISET1a to SVOUT1– to
soft-start channel 1’s output voltage, i.e., reduce its startup inrush current. Connect ISET1a to ISET1b in order to
achieve default soft-start characteristics if desired. (See
ISET1b.)
EXTVCC1 (F3): External Bias, Auxiliary Input to the
INTVCC1 Regulator. When EXTVCC1–VOUT1– > 3.2V and
SVIN1 > 5V and RUN1–GND > 1.2V, the INTVCC1 LDO
derives power from EXTVCC1 bias instead of SVIN1. This
technique reduces LDO losses considerably, resulting in
a corresponding reduction in module junction temperature. For applications in which 4V < VOUT1+ – VOUT1– <
28V, connect EXTVCC1 to VOUT1+ through a 15Ω~110Ω
resistor and locally decouple EXTVCC1 to VOUT1– with a
1μF ceramic capacitor. Otherwise, connect EXTVCC1 to
VOUT1– or leave EXTVCC1 open circuit. See the Applications
Information section.
RUN1 (F4): Channel 1 Run Control Pin. A voltage above
~1.2V (with respect to GND) commands the module to
regulate its output voltage. Undervoltage lockout (UVLO)
can be implemented by connecting RUN1 to the midpoint
18
node formed by a resistor divider between VIN1 and GND.
RUN1 features ~130mV of hysteresis.
ISET2b (F6): 1.5nF Soft-Start Capacitor for Channel 2.
Connect ISET2b to ISET2a to achieve default soft-start
characteristics on channel 2, if desired. See ISET2a.
In addition, the channel 1 output of the LTM4655 can
track a voltage applied to this pin. (See the Applications
Information section.)
ISET2a (F7): Accurate 50μA Current Source. Positive
input to the error amplifier of channel 1. Connect a resistor RISET2a = ((VOUT2+ – VOUT2–)/50μA) from this pin
to SVOUT2– local to the module to program the desired
channel 2 output voltage magnitude, VOUT2+ – VOUT2–. A
capacitor can be connected from ISET2a to SVOUT2– to
soft-start channel 2’s output voltage, i.e., reduce its startup inrush current. Connect ISET2a to ISET2b in order
to achieve default soft-start characteristics if desired.
(See ISET2b.)
In addition, the channel 2 output of the LTM4655 can
track a voltage applied to this pin. (See the Applications
Information section.)
EXTVCC2 (F8): External Bias, Auxiliary Input to the
INTVCC2 Regulator. When EXTVCC2–VOUT2– > 3.2V and
SVIN2 > 5V and RUN2–GND >1.2V, the INTVCC2 LDO
derives power from EXTVCC2 bias instead of SVIN2. This
technique reduces LDO losses considerably, resulting in
a corresponding reduction in module junction temperature. For applications in which 4V < VOUT2+ – VOUT2– <
28V, connect EXTVCC2 to VOUT2+ through a 15Ω~110Ω
resistor and locally decouple EXTVCC2 to VOUT2– with a
1μF ceramic capacitor. Otherwise, connect EXTVCC2 to
VOUT2– or leave EXTVCC2 open circuit. See the Applications
Information section.
RUN2 (F9): Channel 2 Run Control Pin. A voltage above
~1.2V (with respect to GND) commands the module to
regulate its output voltage. Undervoltage lockout (UVLO)
can be implemented by connecting RUN2 to the midpoint
node formed by a resistor divider between VIN2 and GND.
RUN2 features ~130mV of hysteresis.
Rev. B
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LTM4655
PIN FUNCTIONS
CLKSET (F12): Clock Generator Frequency Setting
Resistor Input. Apply a resistor, RCLKSET, between
LDOOUT and CLKSET. The clock frequency of CLKOUT1
and CLKOUT2 is set by RCLKSET, according Equation 3.
f(CLKOUT1, CLKOUT2) = 10MHz •
10kΩ
RCLKSET (kΩ)
(3)
INTVCC2 (G8): Channel 2 Internal Regulator, 3.3V Output
with Respect to VOUT2–. Channel 2 internal control circuits
and MOSFET drivers derive power from INTVCC2 bias.
Leave INTVCC2 open circuit. An LDO generates INTVCC2
from either SVIN2 or EXTVCC2, when RUN2 is logic high
(RUN2–GND > 1.2V). The INTVCC2 LDO is turned off when
RUN2 is logic low (RUN2–GND < 1.2V). (See EXTVCC2.)
Resistor values between 32.2k and 499k are supported,
corresponding to oscillator frequency settings of 3MHz
to 200kHz, respectively. Minimize stray capacitance to
this pin.
LDOOUT (G12): Output of the LTM4655’s GND Referenced
5V-Fixed LDO. No bypass capacitance is needed. Powers
the clock generator internal to the LTM4655. Can deliver
up to 25mA of current.
VOSNS1+ (G1, H1): Positive Voltage Sense Input for
Channel 1. Route a signal trace from VOSNS1+ to VOUT1+
at channel 1’s point-of-load (POL). This provides the feedback signal to channel 1’s control loop. In noisy environments, shield VOSNS1+ from electrical noise by sandwiching the trace between PGND copper. Pins G1 and H1 are
electrically connected to each other internal to the module, and thus it is only necessary to connect one VOSNS1+
pin to VOUT1+ at the POL. The remaining VOSNS1+ pin can
be used for redundant connectivity or routed to an ICT
test point for design-for-test considerations, as desired.
SW1 (H4): Switching Node of Channel 1 Switching
Converter Stage. Used for test purposes. May be routed
a short distance with a thin trace to a local test point to
monitor switching action of the converter, if desired, but
do not route near any sensitive signals; otherwise, leave
electrically open circuit.
INTVCC1 (G3): Channel 1 Internal Regulator, 3.3V Output
with Respect to VOUT1–. Channel 1 internal control circuits
and MOSFET drivers derive power from INTVCC1 bias.
Leave INTVCC1 open circuit. An LDO generates INTVCC1
from either SVIN1 or EXTVCC1, when RUN1 is logic high
(RUN1–GND > 1.2V). The INTVCC1 LDO is turned off when
RUN1 is logic low (RUN1–GND < 1.2V). (See EXTVCC1.)
VOSNS2+ (G6, H6): Positive Voltage Sense Input for
Channel 2. Route a signal trace from VOSNS2+ to VOUT2+
at channel 2’s point-of-load (POL). This provides the feedback signal to channel 2’s control loop. In noisy environments, shield VOSNS2+ from electrical noise by sandwiching the trace between PGND copper. Pins G6 and H6 are
electrically connected to each other internal to the module, and thus it is only necessary to connect one VOSNS2+
pin to VOUT2+ at the POL. The remaining VOSNS2+ pin can
be used for redundant connectivity or routed to an ICT
test point for design-for-test considerations, as desired.
SW2 (H9): Switching Node of Channel 2 Switching
Converter Stage. Used for test purposes. May be routed
a short distance with a thin trace to a local test point to
monitor switching action of the converter, if desired, but
do not route near any sensitive signals; otherwise, leave
electrically open circuit.
NC (J1–2, J11–12): No Connect Pins, i.e., Pins with No
Internal Connection. The NC pins predominantly serve to
provide improved mounting of the module to the board.
For drop-in compatibility of the LTM4651/LTM4653 into
either half of a LTM4655 layout, these NC are recommended to be left electrically open circuit.
TEMP+ (J6): Temperature Sensor, Positive Input. Emitter
of a 2N3906-genre PNP bipolar junction transistor (BJT).
Optionally interface to temperature monitoring circuitry
such as LTC®2997, LTC2990, LTC2974 or LTC2975.
Otherwise leave electrically open.
TEMP– (J7): Temperature Sensor, Negative Input. Collector
and base of a 2N3906-genre PNP bipolar junction transistor (BJT). Optionally interface to temperature monitoring circuitry such as LTC2997, LTC2990, LTC2974 or
LTC2975. Otherwise leave electrically open.
Rev. B
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19
LTM4655
PIN FUNCTIONS
VOUT1+ (K1–3, L1–3, M1–3): Positive Power Output of
Channel 1. Bypass VOUT1+ to VOUT1– local to the module with at least 1μF. The remainder of VOUT1+ to VOUT1–
bypass caps should be located near channel 1’s load.
Either connect VOUT1+ to a PGND plane in inverting buckboost applications, where VOUT1– is the regulated negative output voltage—or, connect VOUT1– to a PGND plane
noninverting step-down applications, where VOUT1+ is the
regulated positive output voltage.
20
VOUT2+ (K6–8, L6–8, M6–8): Positive Power Output of
Channel 2. Bypass VOUT2+ to VOUT2– local to the module with at least 1μF. The remainder of VOUT2+ to VOUT2–
bypass caps should be located near channel 2’s load.
Either connect VOUT2+ to a PGND plane in inverting buckboost applications, where VOUT2– is the regulated negative output voltage—or, connect VOUT2– to a PGND plane
noninverting step-down applications, where VOUT2+ is the
regulated positive output voltage.
Rev. B
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RUNn
IMONbn
IMONan
fSETn
VINREGn
INTVCCn
COMPnb
COMPna
ISETnb
ISETna
VOUTn+ – VOUTn–
50µA
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LDOIN
4.7nF
5V
LDO
10k
1μF
1.5nF
249k
10pF
2.2μF
+
–
+
–
IL ÷ 40000
2V
GND
100Ω
PGOOD
LOGIC
ERROR
AMPLIFIER
+
–
50µA
SVINFn
4.99k
MBn
MTn
0.1μF
220pF
ILn
0.1μF
CLOCK
OSCILLATOR
0.1μF
4μH
400nH BEAD
4655 BD
+
+
DOPT*
OPTIONAL
CDn
CINHn
TEMP–
TEMP+
MOD
CLKOUT2
CLKOUT1
CLKSET
LDOOUT
LOADn
CINLn
VOUTn– (NEGATIVE
VOUT CONFIGURATION)
UP TO –0.5V
DOWN TO (VINn – 40V),
NOT BEYOND
26.5V BELOW GND
UP TO 4A
GND (POSITIVE-VOUT
CONFIGURATION)
COUTHn
GND (NEGATIVE-VOUT
CONFIGURATION)
VOUTn+ (POSITIVE
VOUT CONFIGURATION)
UP TO 0.5V,
UP TO 0.94 • VINn,
UP TO 4A
OPTIONALLY CONNECT TO CLKIN2
OPTIONALLY CONNECT TO CLKIN1
5V WITH RESPECT TO GND
UP TO 25mA
RCLKSET
IS Hi-Z WHEN
(PGDFBn–SVOUTn– )
IS WITHIN 0.6V ± 7.5%
(CHANNEL n)
RPGDFBn
PGDFBn
PGOODn
SVOUTn–
VOUTn–
VOSNSn
VOUTn+
SWn
VOUTn–
VDn
VINn
SVINn
*IN NEGATIVE VOUT APPLICATIONS, APPLY A SUITABLE SCHOTTKY DIODE (DOPT) IF IT IS IMPORTANT TO MINIMIZE THE AMPLITUDE OF REVERSE POLARITY ON VOUTn–’s
START-UP WAVEFORM. SEE FIGURE 48 AND FIGURE 49.
SVINF1 OR SVINF2
10nF
50Ω
10nF
COMPn
BUFFER
TO CURRENT
COMPARATORS,
PWM, AND
FET-DRIVERS
POWER CONTROL
AND
ANAOLG CIRCUITS
1Ω
VIN
3.1V TO 40V (POSITIVE
VOUT CONFIGURATION)
3.6V TO 40V – |VOUTn–|
(NEGATIVE VOUT
CONFIGURATION)
SIMPLIFIED BLOCK DIAGRAM
TERMINATE IMONa TO
SVOUTn– WHEN
REGULATING
–
NEGATIVE VOUT– SVOUTn
RfSETn
RISETn
RISETn =
EXTVCCn
(REFERRED TO GND)
CLKINn
RUN – GND:
>1.2VTYP = ON
1.2VTYP = ON
1.2VTYP = ON
TON(MIN)n
(4)
where Dn (unitless) is the duty-cycle of MTn, given by
Equation 5:
Dn =
VOUTn + − VOUTn −
VINn − VOUTn −
(5)
In rare cases where the minimum on-time restriction
is violated, the channel n frequency of the LTM4655
automatically and gradually folds back down to approximately one-fifth of its programmed switching frequency
to allow VOUT to remain in regulation. See the Frequency
Adjustment section. Be reminded of Notes 2 and 3 in
the Electrical Characteristics section regarding output
current guidelines.
Input Capacitors, Positive-VOUT Operation
The LTM4655 achieves low input conducted EMI noise
due to tight layout and high frequency bypassing of
MOSFETs MTn and MBn within the module itself. A small
filter inductor (400nH) is integrated in the input line (from
VINn to VDn), providing further noise attenuation—again,
local to the switching MOSFETs. The VDn and VINn pins
are available for external input capacitors—CDn and
CINHn—to form a high-frequency π filter. As shown in
the Simplified Block Diagram, the ceramic capacitor CDn
on the LTM4655’s VDn pins handles the majority of the
RMS current into the DC/DC converter power stage and
requires careful selection, for that reason.
See Figure 7 through Figure 9 for demonstration of
LTM4655’s EMI performance, meeting the radiated emissions requirements of EN55022B.
The input capacitance, CDn, is needed to filter the pulsed
current drawn by MTn. To prevent excessive voltage sag
on VDn, a low-effective series resistance (low-ESR, such
as an X7R ceramic) input capacitor should be used, sized
appropriately for the maximum CDn RMS ripple current
(Equation 6)
ICDn(RMS) =
IOUTn(MAX)
ηn %
• Dn • (1–Dn )
(6)
where ηn% is the estimated efficiency of the channel n power module. (See Typical Performance
Characteristics graphs.)
Rev. B
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LTM4655
OPERATION
Several capacitors may be paralleled to meet the application’s target size, height, and CDn RMS ripple current
rating. For lower input voltage applications, sufficient bulk
input capacitance is needed to counteract line sag and
transient effects during output load changes. The bulk
capacitor can be a switcher-rated aluminum electrolytic
capacitor or a Polymer capacitor. Suggested values for
CDn and CINHn are found in Table 11.
A final precaution regarding ceramic capacitors concerns
the maximum input voltage rating of the LTM4655’s VINn,
SVINn, and VDn pins. A ceramic input capacitor combined
with trace or cable inductance forms a high Q (underdamped) tank circuit. If the LTM4655 circuit is plugged
into a live supply, the input voltage can ring to twice its
nominal value, possibly exceeding the device’s rating.
This situation is easily avoided; see the Hot Plugging
Safely section.
Output Capacitors, Positive-VOUT Operation
Output capacitors COUTHn and COUTLn are applied across
the LTM4655’s VOUTn+/VOUTn– power output pins.
Sufficient capacitance and low ESR are called for, to
meet the output voltage ripple, loop stability, and transient requirements. COUTLn can be a low ESR tantalum
or polymer capacitor. COUTHn is a ceramic capacitor. The
typical output capacitance is 22μF (type X5R material, or
better), if ceramic-only output capacitors are used.
Table 11 shows a matrix of suggested output capacitors
optimized for 2A transient step-loads applied at 2A/μs.
Additional output filtering may be required by the system
designer, if further reduction of output ripple or dynamic
transient spike is required. The LTpowerCAD design tool is
available for transient and stability analysis. Stability criteria are considered in the Table 11 matrix, and LTpowerCAD
is available for stability analysis. Multiphase operation will
reduce effective output ripple as a function of the number of phases. Application Note 77 discusses this noise
reduction versus output ripple current cancellation, but
the output capacitance should be considered carefully as a
function of stability and transient response. LTpowerCAD
can be used to calculate the output ripple reduction as the
number of implemented phases increases by N times.
External loop compensation can be applied from COMPna
to SVOUTn–, if needed, for transient response optimization.
Forced Continuous Operation
Leave the CLKINn pin open circuit to command channel n of the LTM4655 for forced continuous operation.
In this mode, the control loop is allowed to command the
inductor peak current to approximately –1A, allowing for
significant negative average current. Clocking the CLKINn
pin at a frequency within ±40% of the target switching frequency commanded by the fSETn pin synchronizes MTn’s
turn-on to the rising edge of the CLKINn pin.
Output Voltage Programming, Tracking and Soft-Start
The LTM4655 regulates its output voltage, VOUTn+ – VOUTn–,
according to the differential voltage present from ISETna to
SVOUTn–. In most applications, the output voltage is set by
simply connecting a resistor, RISETn, from ISETna to SVOUTn–,
according to Equation 7.
RISETn =
VOUTn + − VOUTn −
50µA
(7)
Since the LTM4655 control loop servos its output voltage
according to the voltage between ISETna and SVOUTn–:
placing a capacitor, CSSn, parallel to RISETn configures the
ramp-up rate of ISETna and thus the output. In the time
domain, the output voltage ramp-up after the RUNn pin is
toggled from low to high (t = 0s) is given by Equation 8.
t
⎛
⎞
–
R
• CSSn ⎟
ISETn
VOUTn (t) VOUTn (t) =IISETna •RISETn • ⎜ 1– e
⎜
⎟
⎝
⎠
+
−
(8)
The soft-start time, tSS, is defined as the time it takes for
channel n’s output voltage to ramp from 0V to 90% of its
final value (Equation 9 or Equation 10)
tSSn = –RISETn •CSSn •In (1– 0.9)
(9)
or
tSSn = 2.3 • RISETn •CSSn
(10)
Rev. B
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27
LTM4655
OPERATION
A default value of CSSn = 1.5nF can be implemented by
connecting ISETna to ISETnb. For other ramp-up rates,
connect an external CSS capacitor parallel to RISET.
The LTM4655’s minimum on-time, tONn(MIN), is specified
as 60ns. For a practical design, it is recommended to
guardband to 90ns.
When starting up into a pre-biased VOUT, the LTM4655
stays in a sleep mode, keeping MTn and MBn off until
VISETna equals VOSNSn+—after which, the DC/DC converter commences switching action and VOUT is ramped
according to the voltage commanded by ISETna.
To configure channel n of the LTM4655 for a higher
switching frequency than its default of 400kHz, apply
a resistor, RfSETn, between the fSETn pin and SVOUTn+.
RfSETn is given (in MΩ) by Equation 13.
The LTM4655 can track the mirror-image of a positive rail to generate the negative half of a split-supply, as seen in Figure 50 (note the use of RTRACK and
RISET2 = RISET1 || RTRACK).
Frequency Adjustment
The default switching frequency (fSWn) of channel n of the
LTM4655 is 400kHz. This is suitable for low-VIN (VINn ≤
5V) applications and low-VOUT (VOUTn+ – VOUTn– ≤ 3.3V)
applications. For a practical design, the LTM4655’s inductor ripple current (ΔInPK-PK) is suggested to be less than
~2APK-PK. Choose fSWn according to Equation 11.
fSWn =
VOUTn + − VOUTn − • (1− Dn )
L n • ∆InPK-PK
(11)
R fSETn (MΩ) =
1
10pF •[fSWn (MHz)– 0.4(MHz)]
(13)
The relationship of RfSETn to programmed fSWn is shown
in Figure 1. See Table 11 and Table 12 for recommended
fSWn and corresponding RfSETn values for various combinations of VINn, VOUTn+ and VOUTn–.
PROGRAMMED SWITCHING FREQUENCY (MHz)
Since the LTM4655 control loop servos its VOSNSn+ voltage to match that of ISETna’s, the LTM4655’s channel
n output can be configured to track any voltage applied
to ISETna, referenced to SVOUTn–. See Figure 52 for an
example of the LTM4655 configured as a DAC-controlled
bipolar-output programmable power supply.
10
RfSETn NOT USED
1
0.1
10
100
1k
RfSETn (kΩ)
10k
4655 F01
Figure 1. Relationship Between RfSETn and Target fSWn
where the value of LTM4655’s power inductor, Ln, is 4μH.
To avoid cycle-skipping, impose restrictions on fSWn, to
ensure minimum on-time criteria is met (Equation 12).
fSWn <
28
Dn
TONn(MIN)
(12)
Rev. B
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LTM4655
APPLICATIONS INFORMATION
Power Module Protection
The LTM4655’s current mode control architecture provides fast cycle-by-cycle current limit in an overcurrent condition, as shown in the Typical Performance
Characteristics section. If the output voltage collapses
sufficiently due to an overload or short-circuit condition,
minimum on-time will be violated and the internal oscillator will then fold-back automatically to one-fifth of the
LTM4655’s programmed switching frequency—thereby
reducing the output current and affording the load a
chance to recover.
The LTM4655 ceases channel n switching action if the
channel’s internal temperatures exceed 165°C. The channel’s control IC resumes operation after a 10°C cool-down
hysteresis. Note that these typical parameters are based
on measurements in a lab oven and are not production
tested. This overtemperature protection is intended to
protect the device during momentary overload conditions. The maximum rated junction temperature will be
exceeded when this overtemperature protection is active.
Continuous operation above the specified absolute maximum operating junction temperature may impair device
reliability or permanently damage the device. See Note 1
of the Electrical Characteristics table.
UVLO. Resistors are chosen by first selecting RBn (refer
to Figure 2 and Equation 14). Then:
VSUPPLY
RAn
RUNn PIN
RBn
4655 F02
Figure 2. Undervoltage Lockout Resistive Divider
⎛ VINn(ON) ⎞
R An = RBn • ⎜
– 1⎟
1.2V
⎠
⎝
(14)
where VINn(ON) is the input voltage at which the undervoltage lockout is overcome and the supply turns on. The
VINn turn-off voltage, VINn(OFF) is given by Equation 15.
⎛R
⎞
VINn(OFF) = 1.07V • ⎜ An +1⎟
⎝ RBn ⎠
(15)
If UVLO is not needed, RUNn can be connected to
LTM4655’s LDOOUT pin.
The LTM4655 does not feature any specialized output
overvoltage protection beyond what is inherent to the
control loop’s servo mechanism.
When RUNn is below its threshold, UVLO of channel n
is engaged, MTn and MBn are turned off, INTVCCn ceases
to be regulated, and ISETna is discharged to SVOUTn– by
internal circuitry.
RUN Pin Enable
Loop Compensation
The RUNn pin is used to enable the power module or
sequence the power module. The threshold is 1.2V. The
RUNn pin can be used to provide an undervoltage lockout
(UVLO) function by connecting a resistor divider from
the input supply to the RUNn pin, as shown in Figure 2.
Undervoltage lockout keeps channel n of the LTM4655
in shutdown until the supply input voltage is above a
certain voltage programmed by the user. The RUNn pin
hysteresis voltage prevents noise from falsely tripping
External loop compensation may be preferred for some
applications and can be implemented easily, as follows:
leave COMPnb open circuit; connect a series-RC network RTHn and CTHn from COMPnb to SVOUTn–; in some
instances, connect a capacitor (CTHPn) from COMPna to
SVOUTn– (paralleling the RTHn–CTHn series-RC network).
See Table 11 and Table 12 for suggested input and output capacitances for a variety of operating conditions.
Additionally, the LTpowerCAD design tool is available for
transient and stability analysis.
Rev. B
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29
LTM4655
APPLICATIONS INFORMATION
Hot Plugging Safely
The small size, robustness and low impedance of ceramic
capacitors make them an attractive option for the input
bypass capacitors (CDn and CINHn) of the LTM4655.
However, these capacitors can cause problems if the
LTM4655 is plugged into a live supply (see Analog Devices
Application Note 88 for a complete discussion). The low
loss ceramic capacitor combined with stray inductance in
series with the power source forms an under damped tank
circuit, and the voltage at the VINn pin of the LTM4655 can
ring to twice the nominal input voltage, possibly exceeding the LTM4655’s rating and damaging the part. If the
input supply is poorly controlled or the user will be plugging the LTM4655 into an energized supply, the input
network should be designed to prevent this overshoot by
introducing a damping element into the path of current
flow. This is often done by adding an inexpensive electrolytic bulk capacitor (CINLn) across the input terminals
of the LTM4655. The selection criteria for CINLn calls for:
an ESR high enough to damp the ringing; a capacitance
value several times larger than CINHn; a suitable ripple current rating. CINLn does not need to be located physically
close to the LTM4655; it should be located close to the
application board’s input connector, instead.
(Figure 4). Applications with loads that experience large
load-step release, load dump or other mechanisms that
invoke reverse energy flow in the Figure 3 circuit may
need a suitably-rated Zener diode protection clamp, to
limit the resulting transient voltage rise on SVINn/VINn
and CINHn.
VINn
SVINn
ZDn
OPT
However, if the SVINn/VINn pins are grounded while the
output is held high, regardless of the RUNn state, parasitic body diodes inside the LTM4655 will pull current
from the output through the VOUTn+ pins. Depending on
the size of the output capacitor and the resistivity of the
short, high currents may flow through the internal body
diode, and cause damage to the part. If discharge of
SVINn/VINn by the input source is possible, preventative
measures should be taken to prevent current flow through
the internal body diode. Simple solutions would be placing a Schottky diode in series with the supply (Figure 3),
or placing a Schottky diode from VOUTn+ to SVINn/VINn
30
LTM4655
CINHn
4.7µF
4655 F03
Figure 3. Schottky Diode in Series with the Supply
VINn
VINn
VOUTn+
VOUTn
SVINn
C INHn
4.7µF
LTM4655
COUTn
47µF
4655 F04
Figure 4. Schottky Diode from VOUTn+ to VINn
Input Disconnect/Input Short Considerations
If at any point the input supply is removed with the output
voltage still held high through its capacitor, power will be
drawn from the output capacitor to power the module,
until the output voltage drops below the minimum SVINn/
VINn requirements of the module.
VINn
INTVCCn and EXTVCCn Connection
When RUNn is logic high, an internal low dropout regulator regulates an internal supply, INTVCCn, that powers the
control circuitry for driving LTM4655’s channel n internal
MOSFETs. INTVCCn is regulated at 3.3V. In this manner,
the LTM4655’s INTVCCn is directly powered from SVINn,
by default. The gate driver current through the INTVCCn
LDO is about 20mA for a typical 1MHz application. The
internal LDO power dissipation can be calculated as
shown in Equation 16.
PLDO_LOSSn(INTVCC) = 20mA •(SVINn − − VOUTn − – 3V)
(16)
The LDO draws current off of EXTVCCn instead of SVINn
when EXTVCCn–VOUTn– exceeds 3.2V and SVINn–SVOUTn–
exceeds 5V. For output voltages of 4V and higher, EXTVCCn
Rev. B
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LTM4655
APPLICATIONS INFORMATION
+
−
PLDO_LOSSn(EXTVCC) = 20mA •(VOUTn − VOUTn − 3V)
(17)
The recommended value of the resistor between VOUTn+
and EXTVCCn is roughly (VOUTn+ – VOUTn–) • 4Ω/V. This
resistor, REXTVCCn, must be rated to continually dissipate
(0.02A)² • REXTVCCn. The primary purpose of this resistor
is to prevent EXTVCCn overstress under a fault condition.
For example, when an inductive short-circuit is applied
to the module’s output, VOUT+ may be briefly dragged
below VOUTn–—forward biasing the VOUTn–-to-EXTVCCn
body diode. This resistor limits the magnitude of current
flow in EXTVCCn. If the application requires a low resistive
path to EXTVCCn, apply a protective Schottky diode across
EXTVCCn and VOUTn–; see Figure 52. Bypass EXTVCCn to
VOUTn– with 1μF of X5R (or better) MLCC.
Multiphase Operation
Multiple LTM4655 channels and modules can be paralleled
for higher output current applications. For lowest input
and output voltage and current ripples, it is advisable to
synchronize paralleled LTM4655s to a clock (within ±40%
of the target switching frequency set by fSETn.
LTM4655 channels and modules can be paralleled without synchronizing circuits: just be aware that some beatfrequency ripple will be present in the output voltage and
reflected input current by virtue of the fact that such modules are not operating at identical, synchronized switching
frequencies.
The LTM4655 device is an inherently current mode controlled device, so parallel channels and modules will have
good current sharing as shown in Figure 45 and Figure 47.
To parallel LTM4655 channels and/or modules, connect the respective COMPna, ISETna, and VOSNSn+ pins
of each LTM4655 together to share the current evenly.
In addition, tie the respective RUNn pins of paralleled
LTM4655 channels and/or modules together, to ensure
proper start-up and shutdown behavior.
Note that for parallel applications, VOUT can be set by a single,
common resistor on the ISETna net (see Equation 18).
RISETn =
VOUTn + − VOUTn −
50µA •N
(18)
where N is the number of LTM4655 channels in parallel
configuration.
Depending on the duty cycle of operation, the output
voltage ripple achieved by paralleled, synchronized
LTM4655 modules may be considerably smaller than
what is yielded by a single-phase solution. Application
Note 77 provides a detailed explanation of multiphase
operation (relevant to parallel LTM4655 applications)
pertaining to noise reduction and output and input ripple
current cancellation. Regardless of ripple current cancellation, it remains important for the output capacitance of
paralleled LTM4655 applications to be designed for loop
stability and transient response. LTpowerCAD is available
for such analysis.
Figure 5 illustrates the RMS ripple current reduction as a
function of the number of interleaved (paralleled and synchronized) LTM4655 modules—derived from Application
Note 77.
0.60
0.55
0.50
1-PHASE
2-PHASE
3-PHASE
4-PHASE
6-PHASE
0.45
RMS INPUT RIPPLE CURRENT
DC LOAD CURRENT
can be connected to VOUTn+ through an RC-filter. When
the internal LDO derives power from EXTVCCn instead of
SVINn, the internal LDO power dissipation is shown in
Equation 17.
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
DUTY CYCLE (–VOUT– / VIN – VOUT–)
4655 F05
Figure 5. Normalized Input RMS Ripple Current vs Duty Cycle for
One to Six LTM4655 Channels (Phases)
Rev. B
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31
LTM4655
APPLICATIONS INFORMATION
Negative Output Current Capability Varies as a
Function of VINn to VOUTn– Conversion Ratios,
Negative-VOUT– Operation
In negative-VOUT operation, the output current capability of
the LTM4655 has a strong dependency on the operating
input (VINn) and output (VOUTn–) voltages. See Figure 6.
CHANNEL OUTPUT CURRENT (A)
VINn – VOUTn –
(19)
∆InPK-PK is the channel n inductor ripple current, in
amps, and ηn (unitless) is the channel efficiency of the
LTM4655.
3.5
3.0
2.5
2.0
For completeness, ∆InPK-PK is given by Equation 20.
VOUT– = –0.5V
VOUT– = –3.3V
VOUT– = –5V
VOUT– = –8V
VOUT– = –12V
VOUT– = –15V
VOUT– = –20V
VOUT– = –24V
1.5
1.0
0.5
0
5
10
15 20 25 30
INPUT VOLTAGE (V)
35
ΔInPK–PK =
40
4655 F06
Figure 6. Channel Output Current Capability*,
Negative-VOUT Operation
*Current limit frequency-foldback activates at load currents higher than indicated curves. Continuous channel
output current capability subject to details of application implementation. Switching frequency set per
Table 1. See Notes 2 and 3.
The reason for this is inherent in the two-switch buck-boost
topology employed by the LTM4655 when so-configured
for negative-VOUT operation. To protect the primary power
MOSFET (MTn) from overstress (see Simplified Block
Diagram), its peak current (InPK) is limited by control
circuitry to 6A. When MTn is on, observe that no current
flows to LTM4655’s output; furthermore, observe that
only when MTn is off does current flow to the output of
the LTM4655. As a consequence of this arrangement: for
a given output voltage, current limit inception activates
sooner at low line (higher, larger duty cycle) than at high
line (lower, smaller duty cycle). A further consequence
is: for a given input voltage, the output power capability
of the LTM4655 is higher for lower-magnitude VOUTn–
(lower, smaller duty cycle) than for higher-magnitude
VOUTn– (higher, larger duty cycle). The combination of
32
IOUTn(CAPABILITY) =
ΔI
⎛
⎞
VINn • ⎜ InPK – nPK–PK ⎟ • ηn
⎝
⎠
2
where:
4.0
0
these effects is shown the plots in Figure 6 and described
by Equation 19.
1
⎛ 1
1 ⎞
L n • fSWn • ⎜
–
–⎟
⎝ VINn VOUTn ⎠
(20)
where:
Ln is 4μH, the LTM4655 channel’s power inductor value,
and fSWn is the switching frequency of the LTM4655’s
channel, in MHz.
For a practical design, ∆InPK-PK is designed to be less
than ~2APK-PK.
For a practical design, the LTM4655’s on-time of MTn
each switching cycle should be designed to exceed the
LTM4655 control loop’s specified minimum on-time
of 60ns, tON(MIN), (guardband to 90ns). For example,
Equation 21.
Dn
fSWn
> TONn(MIN)
(21)
where Dn (unitless) is the duty-cycle of MTn, given by
Equation 22.
D=
VOUTn + – VOUTn –
VINn – VOUTn –
(22)
Combining Equation 22 with Equation 19, it can be illustrative to see Equation 23.
ΔI
⎛
⎞
IOUTn(CAPABILITY) = (1–Dn)• ⎜ InPK – nPK–PK ⎟ • ηn (23)
⎝
⎠
2
Rev. B
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LTM4655
APPLICATIONS INFORMATION
In rare cases where the minimum on-time restriction is violated, the frequency of the affected LTM4655
channel(s) automatically and gradually folds back down to
one-fifth of its programmed switching frequency to allow
VOUTn– to remain in regulation.
Be reminded of Notes 2, and 3 in the Electrical
Characteristics section regarding output current
guidelines.
Input Capacitors, Negative-VOUT– Operation
The LTM4655 achieves low input conducted EMI noise
due to tight layout and high-frequency bypassing of
MOSFETs MTn and MBn within the module itself. A small
AMPLITUDE (dBµV/m)
60
70
[1] HORIZONTAL
[2] VERTICAL
QPK LIMIT
+ FORMAL
MEAS DIST 10m
SPEC DIST 10m
50
To meet the radiated emissions requirements of
EN55022B, an additional filter capacitor, CINOUTn, is
needed—connecting from VINn to VOUTn–. See Figure 7
through Figure 9 for EMI performance.
60
AMPLITUDE (dBµV/m)
70
filter inductor (400nH) is integrated in the input line (from
VINn to VDn) provides further noise attenuation—again,
local to the switching MOSFETs. The VDn and VINn pins
are available for external input capacitors—CDn and
CINHn—to form a high-frequency � filter. As shown in
the Simplified Block Diagram, the ceramic capacitor CDn
on the LTM4655’s VDn pins handles the majority of the
RMS current into the DC/DC converter power stage and
requires careful selection, for that reason.
40
30
20
50
40
30
20
10
10
0
0
–10
30
130
230
330
430 530 630 730
FREQUENCY (MHz)
830
MEAS DIST 10m
SPEC DIST 10m
[1] HORIZONTAL
[2] VERTICAL
QPK LIMIT
+ FORMAL
–10
30
930 1000
130
230
330
4655 F06
Figure 7. Radiated Emissions Scan of the LTM4655. Producing
24VOUT at 7A, from 36VIN. DC2898A Hardware. fSW = 1.2MHz.
Measured in a 10m Chamber. Peak Detect Method
430 530 630 730
FREQUENCY (MHz)
830
930 1000
4655 F08
Figure 8. Radiated Emissions Scan of the LTM4655. Producing
–24VOUT at 2A, from 12VIN , DC2899A Hardware. fSW = 1.2MHz.
Measured in a 10m Chamber. Peak Detect Method
70
AMPLITUDE (dBµV/m)
60
MEAS DIST 10m
SPEC DIST 10m
50
40
30
20
10
[1] HORIZONTAL
[2] VERTICAL
QPK LIMIT
+ FORMAL
0
–10
30
130
230
330
430 530 630 730
FREQUENCY (MHz)
830
930 1000
4655 F09
Figure 9. Radiated Emissions Scan of the LTM4655. Producing
–12VOUT at 4A, from 12VIN. DC2899A Hardware. fSW = 700kHz.
Measured in a 10m Chamber. Peak Detect Method
Rev. B
For more information www.analog.com
33
LTM4655
APPLICATIONS INFORMATION
The input capacitance, CDn, is needed to filter the pulsed
current drawn by MTn. To prevent excessive voltage sag
on VDn, a low-effective series resistance (low-ESR) input
capacitor should be used, sized appropriately for the
maximum CDn RMS ripple current (see Equation 24).
ICDn(RMS) =InPK • Dn • (1–Dn )
(24)
I CDn(RMS) is maximum for D n = 1/2. For D n = 1/2,
I CDn(RMS) = 1/2 • I nPK or 3A. This simplification of the
worst-case condition is commonly used for design purposes because even significant deviations in Dn do not
offer much relief, in practice. Furthermore: note that ripple
current ratings from capacitor manufacturers are often
based on 2000 hours of life; therefore, it is advisable to
significantly over-design CDn, and/or choose a capacitor
rated at a higher temperature than required. Err on the
side of caution and contact the capacitor manufacturer to
understand the capacitor vendor’s derating methodology.
Several capacitors may be paralleled to meet the application’s target size, height, and CDn RMS ripple current
rating. For lower input voltage applications, sufficient bulk
input capacitance is needed for CINLn to counteract line
sag and transient effects during output load changes.
Suggested values for CDn and CINHn are found in Table 12.
Take note that CDn is connected from VDn to VOUTn–,
whereas CINHn and CINLn are connected from VINn to
power ground; this is deliberate.
A final precaution regarding ceramic capacitors concerns
the maximum input voltage rating of the LTM4655’s VINn,
SVINn, and VDn pins. A ceramic input capacitor combined
with trace or cable inductance forms a high Q (underdamped) tank circuit. If the LTM4655 circuit is plugged
into a live supply, the input voltage can ring to twice its
nominal value, possibly exceeding the device’s rating.
This situation is easily avoided; see the Hot Plugging
Safely section.
Output Capacitors, Negative-VOUT– Operation
Output capacitors COUTHn and COUTLn are applied across
the LTM4655’s VOUTn+/VOUTn– power output pins: sufficient capacitance and low ESR are called for, to meet the
output voltage ripple, loop stability, and transient requirements. COUTLn can be a low ESR tantalum or polymer
34
capacitor. COUTHn is a ceramic capacitor. The typical output capacitance is 22μF (type X5R material, or better), if
ceramic-only output capacitors are used.
For highest reliability designs, polarized output capacitors (COUTLn) are not recommended, as there is a possibility of a diode-drop of reverse voltage appearing transiently on VOUTn– during rapid application of input voltage or when RUNn is toggled logic high (see Figure 49).
When polarized capacitors are used on VOUTn–, contact
the capacitor vendor to understand what reverse voltage their polarized capacitor can withstand. Be advised,
polarized capacitor reverse voltage rating is sometimes
temperature-dependent.
Output voltage ripple (∆VOUTn(PK-PK)–) is governed by
charge lost in COUTHn and COUTLn while MTn is on, in
addition to the contribution of a resistive drop across
the ESR of the output capacitors. This is expressed by
Equation 25.
ΔVOUTn(PK–PK) ≈
ILOADn •D ILOADn •ESRn
+
(25)
COUTn • fSWn
Dn
Table 12 shows a matrix of suggested output capacitors
optimized for transient step-loads that are 50% of the full
load capability for that combination of VINn, VOUTn–, and
fSWn. The table optimizes total equivalent ESR and total
bulk capacitance to yield the stated transient-load performance. Additional output filtering may be required by
the system designer, if further reduction of output ripple
or dynamic transient spike is required. The LTpowerCAD
design tool is available for transient and stability analysis.
Optional Diodes to Guard Against Overstress,
Negative-VOUT– Operation
Just prior to output voltage start-up, a mechanism exists
whereby a diode-drop of reverse polarity can appear on
VOUTn–. See the Simplified Block Diagram and observe:
just prior to output voltage start-up, SVINn bias current
(ISVINn) flows through the module’s control IC, to SVOUTn–;
from there, the bias current (now ISVOUTn–) flows into
VOUTn– and through MBn’s body diode, to SWn. This current (now ILn) continues to flow—though the 4μH power
inductor—to VOUTn+ and thus ground, closing the control IC bias circuit’s path. It is this current through MBn’s
Rev. B
For more information www.analog.com
LTM4655
APPLICATIONS INFORMATION
body diode that creates a diode-drop of reverse polarity
(positive voltage) on VOUTn–, as shown in Figure 49. The
voltage excursion is highest when RUNn toggles high
because that is the instant when INTVCCn powers-up, with
a corresponding increase in ISVINn/ISVOUTn–/ILn current
flow. With higher current flow, the forward voltage drop
(VF) of MBn’s body diode—and thus, the positive voltage
excursion on VOUTn– is higher.
If this transient voltage excursion is unwelcome for the
load or polarized output capacitors, minimize it with a
low VF Schottky diode that straddles VOUTn– and VOUTn+
(see Figure 48 circuit and Figure 49 performance).
Additionally, the voltage excursion can be empirically
reduced by increasing output capacitance.
Lastly: in applications where it is anticipated that VINn
may be rapidly applied (e.g., 1.2VTYP = ON
1k
CFILTER
ISET1a ISET1b ISET2b ISET2a
4655 F45
240k
VPTAT(FILTER)
OPTIONAL ANALOG OUTPUT
TEMPERATURE INDICATOR
* PLACE 470pF DIRECTLY ACROSS THE LTC2997'S D+/D– PINS.
ROUTE TEMP+/TEMP– DIFFERENTIALLY TO D+/D– AND PROTECT FROM NOISE WITH GROUND SHIELDING.
TERMINATE (CONNECT) THE D+/D– GROUND SHIELD AT THE LTC2997 GND PIN, ONLY.
FOR BEST VPTAT PERFORMANCE, THE VCC PIN OF THE LTC2997 MUST BE LOCALLY BYPASSED AND QUIET.
SEE LTC2997 DATA SHEET AND APRIL 2017 LT JOURNAL TECHNICAL ARTICLES.
Figure 45. Single 8A, 24V Output DC/DC μModule Regulator with Optional Analog Temperature Indicator
48
Rev. B
For more information www.analog.com
LTM4655
TYPICAL APPLICATIONS
RUN
5V/DIV
VOUT
10V/DIV
PGOOD
5V/DIV
4655 F46
1ms/DIV
Figure 46. Start-Up Waveforms at 36VIN, Figure 45 Circuit
MODULE OUTPUT CURRENT (A)
5
4
3
2
1
0
–1
CHANNEL 1
CHANNEL 2
0
1
2
3
4
5
6
7
TOTAL OUTPUT CURRENT (A)
8
4655 F47
Figure 47. Current Sharing Performance of LTM4655 Channels in Figure 45 Circuit
Rev. B
For more information www.analog.com
49
LTM4655
TYPICAL APPLICATIONS
VIN
12V
CINOUTn
4.7μF
CINHn
4.7μF
VINn
PGOODn
SVINn
VOSNSn+
CDGNDn
4.7μF
CDn
4.7μF
3.3V
GND
VDn
RUNn
RPGOODn
100k
VOUTn+
RUNn
LTM4655**
D1*
VOUTn–
SVOUTn–
INTVCCn
RPGDFBn
196k
VINREGn
PGDFBn
COMPna
COMPnb
COUTn
10µF
×2
–24VOUT
UP TO 1.25A
LOAD
REXTVCCn
100Ω
EXTVCCn
fSETn
IMONna
ISETna ISETnb
CEXTVCCn
1µF
4655 F48
RfSETn
165k
RISETn
481k
*D1 OPTIONAL (SEE EFFECT IN FIGURE 49): CENTRAL SEMICONDUCTOR P/N CMMSH1-40L
**ONE CHANNEL SHOWN. PINS NOT USED AND NOT SHOWN IN THIS CIRCUIT: NC, SVINFn, IMONnb,
LDOIN, LDOOUT, CLKSET, MOD, CLKOUTn, CLKINn, TEMP+, TEMP–
Figure 48. 1.25A, –24V Output DC/DC μModule Regulator
RUNn, 5V/DIV
RUNn, 5V/DIV
PGOODn, 5V/DIV
PGOODn, 5V/DIV
VOUTn–
10V/DIV
VOUTn–
10V/DIV
VOUTn–
200mV/DIV
VOUTn–
200mV/DIV
1ms/DIV
4655 F49a
1ms/DIV
(a) Start-up Performance with D1 Not Installed.
VOUTn– Reverse-Polarity at Start-Up Transiently
Reaches 500mV
4655 F49b
(b) Start-up Performance with D1 Installed.
VOUTn– Reverse-Polarity at Start-Up is Transiently
Limited to 360mV
Figure 49. Start-Up Waveforms at 12VIN, Figure 48 Circuit
50
Rev. B
For more information www.analog.com
LTM4655
TYPICAL APPLICATIONS
VIN
13V TO 28V
VIN1
SVIN1
CINH1
4.7μF
CTH1
10nF
CINH2
4.7μF
CD2
4.7μF
VOSNS1+
SVOUT1–
VOUT1–
fSET1
INTVCC1
VINREG1
COMP1a
COMP1b
SVINF1
SVINF2
LDOIN
CLKOUT1
CLKIN1
VIN2
INTVCC1
INTVCC2
VINREG2
COMP2a
COMP2b
CLKOUT2
CLKIN2
MOD
GND ISET1a
RfSET2
124k
100k
REXTVCC1
49.9Ω
INTVCC1
5VOUT,
UP TO 25mA
RCLKSET
84.5k
COUTH2
47µF
×2
LOAD2
–12VOUT,
UP TO 2.9A
RPGDFB2
95.3k
PGDFB2
ISET1b
12VOUT,
UP TO 4A
CEXTVCC1
1μF
CLKSET
VOUT2+
VOSNS2+
SVOUT2–
VOUT2–
RUN2
fSET2
INTVCC2
LOAD1
PGDFB1
LTM4655
COUTH1
22µF
×2
RPGDFB1
95.3k
PGOOD1
EXTVCC1
IMON1a
IMON1b
LDOOUT
SVIN2
VD2
LDOOUT
VOUT1+
NC
RUN1
RTH1
499Ω
CDGND2
4.7μF
SW2
VD1
CD1
LDOOUT
4.7μF
RfSET1
124k
SW1
100k
PGOOD2
EXTVCC2
IMON2a
IMON2b
TEMP+
TEMP–
ISET2b ISET2a
REXTVCC2
49.9Ω
INTVCC2
RTRACK
10k
CEXTVCC2
1μF
4655 F50
RISET1
240k
RISET2
240k || 10k
(RISET2 = RISET1 || RTRACK)
Figure 50. Concurrent ±12V Output DC/DC μModule Regulator
VIN
13V TO 40V
VIN1
SVIN1
CINH1
4.7μF
CD1
4.7μF
RfSET1
124k
INTVCC1
CTH1
10nF
CINH2
4.7μF
RfSET2
124k
SW2
VOSNS1+
SVOUT1–
VOUT1–
RUN1
fSET1
INTVCC1
VINREG1
COMP1a
COMP1b
SVINF1
SVINF2
LDOIN
CLKOUT1
CLKIN1
VIN2
PGDFB1
PGOOD1
EXTVCC1
IMON1a
IMON1b
LDOOUT
LTM4655
SVIN2
VD2
LDOOUT
INTVCC2
RTH2
499Ω
CTH2
10nF
VOUT1+
NC
VD1
LDOOUT
RTH1
499Ω
CD2
4.7μF
SW1
RUN2
fSET2
INTVCC2
VINREG2
COMP2a
COMP2b
CLKOUT2
CLKIN2
MOD
GND ISET1a
CLKSET
VOUT2+
VOSNS2+
SVOUT2–
VOUT2–
PGDFB2
ISET1b
COUTH1
22µF
×2
LOAD1
12VOUT,
UP TO 4A
RPGDFB1
95.3k
100k
INTVCC1
REXTVCC1
49.9Ω
CEXTVCC1
1μF
5VOUT,
UP TO 25mA
RCLKSET
84.5k
5VOUT,
COUTH2 UP TO 4A
47µF
×2
LOAD2
RPGDFB2
36.5k
PGOOD2
EXTVCC2
IMON2a
IMON2b
TEMP+
TEMP–
ISET2b ISET2a
100k
INTVCC2
REXTVCC2
20Ω
CEXTVCC2
1μF
4655 F51
RISET1
240k
RISET2
100k
Figure 51. Dual 4A, 12V and 5V Output DC/DC μModule Regulator
Rev. B
For more information www.analog.com
51
LTM4655
TYPICAL APPLICATIONS
VIN
18V TO 24V
SW1
VIN1
CINH1
4.7µF
SW2
NC
VOSNS1+
VOUT1 +
SVIN1
CD1
4.7µF
VD1
LDOOUT
RfSET1
124k
SVOUT1
fSET1
PGDFB1
INTVCC1
PGOOD1
VINREG1
EXTVCC1
IMON1a
SVINF1
IMON1b
CLKOUT1
CLKIN1
VOUT2+
SVOUT2–
VD2
LDOOUT
RCLKSET
84.5k
COUTH2
100µF
×2
LOAD2
VOUT2–
RUN2
fSET2
PGDFB2
INTVCC2
PGOOD2
VINREG2
EXTVCC2
PMEG2005AEL
1Ω
COMP2a
VOUT–,
ADJUSTABLE,
–3V TO –15V,
UP TO 4A*
1µF
COMP2b
IMON2a
CLKOUT2
IMON2b
TEMP+
CLKIN2
TEMP–
MOD
GND
LDOOUT
VOSNS2+
SVIN2
RfSET2
124k
1Ω
CLKSET
LTM4655
VIN2
CD2
4.7µF
PMEG2005AEL
LDOOUT
LDOIN
CDGND2
4.7µF
LOAD1
VOUT+,
ADJUSTABLE,
3V TO 15V,
UP TO 4A
1µF
COMP1b
SVINF2
CINOUT2
4.7µF
COUTH1
100µF
×2
V OUT1 –
RUN1
COMP1a
RTH1
562
CTH1
10nF
CINH2
4.7µF
–
ISET1a
ISET1b
ISET2b
ISET2a
10Ω
26.7k
0.1%
1nF
10k
0.1%
LDOOUT
0.1µF
V+
1/2 LT6016
V–
+
|VTARGET(A,B)| = 3.67 • VDACOUT(A,B)
0.1µF
26.7k
0.1%
0.1µF
VCC
0.1µF
REF
SDI
SERIAL
BUS
VOUTA
LTC2632-HZ
SCK
CS/LD
GND
10Ω
VOUT–
0.1µF
P9
P3
VOUTB
1nF
LDOOUT
VCC
10k
0.1%
P1
LT1991
M1
M3
OUT
V+
1/2 LT6016**
V–
+
REF
VEE
M9
0.1µF
4655 F52
*SEE TABLE 6 AND APPLICATIONS INFORMATION SECTION FOR NEGATIVE OUTPUT CURRENT CAPABILITY
**BOTH HALVES OF LT6016 ON SAME SUPPLY
Figure 52. A DAC-Controlled Bipolar-Output Programmable Power Supply
52
Rev. B
For more information www.analog.com
LTM4655
PACKAGE DESCRIPTION
Table 13. LTM4655 Component BGA Pinout
PIN ID
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
FUNCTION
VIN1
VIN1
VIN1
VD1
VOUT1–
VIN2
VIN2
VIN2
VD2
VOUT2–
VOUT2–
VOUT2–
PIN ID
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
FUNCTION
CLKIN1
CLKOUT1
VIN1
VD1
VOUT1–
CLKIN2
CLKOUT2
VIN2
VD2
VOUT2–
SVINF1
LDOIN
PIN ID
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
FUNCTION
IMON1b
IMON1a
SVIN1
VD1
VOUT1–
IMON2b
IMON2a
SVIN2
VD2
VOUT2–
SVINF2
CLKOUT2
PIN ID
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
FUNCTION
PGOOD1
PGDFB1
VINREG1
GND
VOUT1–
PGOOD2
PGDFB2
VINREG2
GND
VOUT2–
VOUT2–
GND
PIN ID
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
FUNCTION
COMP1b
COMP1a
fSET1
SVOUT1–
VOUT1–
COMP2b
COMP2a
fSET2
SVOUT2–
VOUT2–
VOUT2–
MOD
PIN ID
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
FUNCTION
ISET1b
ISET1a
EXTVCC1
RUN1
VOUT1–
ISET2b
ISET2a
EXTVCC2
RUN2
VOUT2–
VOUT2–
CLKSET
PIN ID
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
FUNCTION
VOSNS1+
SVOUT1–
INTVCC1
VOUT1–
VOUT1–
VOSNS2+
SVOUT2–
INTVCC2
VOUT2–
VOUT2–
VOUT2–
LDOOUT
PIN ID
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
FUNCTION
VOSNS1+
SVOUT1–
VOUT1–
SW1
VOUT1–
VOSNS2+
SVOUT2–
VOUT2–
SW2
VOUT2–
VOUT2–
VOUT2–
PIN ID
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
FUNCTION
NC
NC
VOUT1–
VOUT1–
VOUT1–
TEMP+
TEMP–
VOUT2–
VOUT2–
VOUT2–
NC
NC
PIN ID
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
K12
FUNCTION
VOUT1+
VOUT1+
VOUT1+
VOUT1–
VOUT1–
VOUT2+
VOUT2+
VOUT2+
VOUT2–
VOUT2–
VOUT2–
VOUT2–
PIN ID
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
FUNCTION
VOUT1+
VOUT1+
VOUT1+
VOUT1–
VOUT1–
VOUT2+
VOUT2+
VOUT2+
VOUT2–
VOUT2–
VOUT2–
VOUT2–
PIN ID
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
FUNCTION
VOUT1+
VOUT1+
VOUT1+
VOUT1–
VOUT1–
VOUT2+
VOUT2+
VOUT2+
VOUT2–
VOUT2–
VOUT2–
VOUT2–
Rev. B
For more information www.analog.com
53
For more information www.analog.com
aaa Z
0.630 ±0.025 Ø 144x
4
3.1750
3.1750
SUGGESTED PCB LAYOUT
TOP VIEW
1.9050
PACKAGE TOP VIEW
E
0.6350
0.0000
0.6350
PIN “A1”
CORNER
1.9050
6.9850
5.7150
4.4450
3.1750
1.9050
0.6350
0.0000
0.6350
1.9050
3.1750
4.4450
5.7150
6.9850
Y
X
D
aaa Z
SYMBOL
A
A1
A2
b
b1
D
E
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F
G
H1
H2
aaa
bbb
ccc
ddd
eee
H1
MAX
5.21
0.70
4.51
0.90
0.66
Z
BALL DIMENSION
PAD DIMENSION
NOTES
DETAIL B
PACKAGE SIDE VIEW
DIMENSIONS
NOM
5.01
0.60
4.41
0.75
0.63
16.00
16.00
1.27
13.97
13.97
0.41
4.00
A
A2
0.46
4.05
0.15
0.10
0.20
0.30
0.15
TOTAL NUMBER OF BALLS: 144
0.36
3.95
MIN
4.81
0.50
4.31
0.60
0.60
DETAIL A
b1
SUBSTRATE
A1
ddd M Z X Y
eee M Z
DETAIL B
H2
MOLD
CAP
ccc Z
Øb (144 PLACES)
// bbb Z
(Reference DWG # 05-08-1551)
Z
54
e
11
b
10
8
7
G
6
5
e
4
PACKAGE BOTTOM VIEW
9
3
2
1
DETAIL A
M
L
K
J
H
G
F
E
D
C
B
A
3
SEE NOTES
PIN 1
6
SEE NOTES
4
6
TRAY PIN 1
BEVEL
!
PACKAGE IN TRAY LOADING ORIENTATION
LTMXXXXXX
µModule
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
5. PRIMARY DATUM -Z- IS SEATING PLANE
BALL DESIGNATION PER JESD MS-028 AND JEP95
DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
3
2. ALL DIMENSIONS ARE IN MILLIMETERS. DRAWING NOT TO SCALE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
COMPONENT
PIN “A1”
F
b
12
02-22-2022-A
BGA Package
144-Lead (16mm × 16mm × 5.01mm)
LTM4655
PACKAGE DESCRIPTION
Rev. B
6.9850
5.7150
4.4450
4.4450
5.7150
6.9850
LTM4655
REVISION HISTORY
REV
DATE
DESCRIPTION
A
01/22
Reordered pin names according to pin number instead of function.
B
03/22
PAGE NUMBER
14-20
Corrected SSFM acronym typo.
15
Corrected CLKSET-supported switching frequency range and corresponding resistor-setting values.
19
Corrected SW pin typo.
22
Corrected pin name typos to indicate italic “n” subscript suffix, where missing.
23
Clarified supported positive output voltage range.
25
Fixed Equation 5 typo.
26
Corrected numerical reference to Loop Compensation tables.
29
Fixed typo referencing fSW.
34
Amended POD.
54
Added ink marking statement to package photos.
56
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
more by
information
www.analog.com
55
LTM4655
PACKAGE PHOTOS
Part marking is either ink mark or laser mark
DESIGN RESOURCES
SUBJECT
DESCRIPTION
µModule Design and Manufacturing Resources
Design:
• Selector Guides
• Demo Boards and Gerber Files
• Free Simulation Tools
µModule Regulator Products Search
1. Sort table of products by parameters and download the result as a spread sheet.
Manufacturing:
• Quick Start Guide
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability
2. Search using the Quick Power Search parametric table.
Digital Power System Management
Analog Devices’ family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LTM4651
EN55022B Compliant 58VIN, 24W Inverting-Output DC/DC
μModule Regulator
3.6V ≤ VIN ≤ 58V, –26.5V ≤ VOUT ≤ –0.5V, IOUT ≤ 4A,
15mm × 9mm × 5.01mm BGA
LTM4653
EN55022B Compliant 58VIN, 4A Step-Down DC/DC
μModule Regulator
3.1V ≤ VIN ≤ 58V, 0.5V ≤ VOUT ≤ 0.94V • VIN,
15mm × 9mm × 5.01mm BGA
LTM8045
SEPIC or Inverting µModule DC/DC Converter
2.8V ≤ VIN ≤ 18V, ±2.5V ≤ VOUT ≤ ±15V. IOUT(DC) ≤ 700mA,
6.25mm × 11.25mm × 4.92mm BGA
LTM8053
40V, Dual 3.5A Silent Switcher Step-Down µModule Regulator
3.4V ≤ VIN ≤ 40V, 0.97V ≤ VOUT ≤ 15V,
6.25mm × 9mm × 3.32mm BGA
LTM8024
40V, 3.5A Silent Switcher Step-Down µModule Regulator
3V ≤ VIN ≤ 40V, 0.8V ≤ VOUT ≤ 8V,
9mm × 11.25mm × 3.32mm BGA
LTM8049
Dual, SEPIC and/or Inverting µModule DC/DC Converter
2.6V ≤ VIN ≤ 20V, ±2.5V ≤ VOUT ≤ ±24V. IOUT(DC) ≤ 1A/Channel,
9mm × 15mm × 2.42mm BGA
LTM8071
60V, 5A Silent Switcher® Step-Down µModule Regulator
3.6V ≤ VIN ≤ 60V, 0.97V ≤ VOUT ≤ 15V,
6.25mm × 9mm × 3.32mm BGA
LTM8073
60V, 3A Silent Switcher Step-Down µModule Regulator
3.4V ≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ 15V,
9mm × 11.25mm × 3.32mm BGA
56
Rev. B
03/22
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