LTM4660
60V, 300W Hybrid Step-Down
µModule Bus Converter
FEATURES
DESCRIPTION
Input Voltage Range: 30V to 60V (65V Abs. Max.)
n Wide Output Voltage: 4.5V to 18V (V
OUT < VIN/2)
n 97.3% Peak Efficiency (12V
OUT at 15A, 48VIN)
n ±1.5% Maximum Total DC Output Error
n Up to 300W Output Power
n Scalable: Parallel LTM4660s for Higher Power
n Fixed Frequency Current Mode Control
n Phase-Lockable External Synchronization from
200kHz to 1MHz
n Low Start-Up Inrush Current with Flying Capacitor
Voltage-Balancing Prior to DC/DC Switching Action
n Output Voltage Tracking with Soft-Start
n Short-Circuit Protection with Adjustable Retry-Timer
n Overcurrent and Overtemperature Protection
n Onboard Diode Temperature Monitor
n Optional External Reference Input
n Power Good and FAULT Indicators
n 16mm × 16mm × 10.34mm BGA Package
The LTM®4660 is a complete 300W output switching
mode hybrid-topology step-down DC/DC µModule®
(micromodule) nonisolated bus converter. Its exposed
power inductor resides on the top of the package, providing an intrinsic path for heat to dissipate up and out
of the module—away from one’s printed circuit board.
Included in the package are the switching controller IC,
power MOSFETs and supporting components. Only flying
(charge-pump) capacitors, bulk input and output bypass
capacitors, and a few configuration passives are needed.
n
The LTM4660 features frequency synchronization,
Burst Mode® operation and output voltage soft-start and
tracking. An onboard temperature diode is available for
temperature monitoring. The LTM4660 protects against
short-circuit, overcurrent, and overtemperature faults. For
higher power applications, multiple LTM4660 modules
can be easily paralleled.
The LTM4660 is offered in a 16mm × 16mm × 10.34mm
BGA package with RoHS compliant terminal finish.
APPLICATIONS
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. patents, including 9484799.
Telecom, Data Centers and Networking Equipment
n Industrial and Test Equipment
n
TYPICAL APPLICATION
12V, 25A DC/DC μModule Nonisolated Bus Converter
VIN
CIN 30V TO 60V
10µF
×2
VIN
RUN
INTVCC
VINSNS
EXT_REF
10k
LTM4660
C+
FAULT
PGOOD
PGOOD
C–
HYS_PRGM
100k
1µF
TIMER
MIDSNS
COMPa
MID
COMPb
FREQ
TRACK/SS
49.9k
VFB
0.1µF
4.32k
98
MODE/PLLIN
TEMP
SGND
CMID
10µF
50V
×12
PGND
COUT
22µF
×2
96
95
EXTVCC
VOUT
fSW = 350kHz
97
CFLY
10µF
50V
×12
EFFICIENCY (%)
10k
FAULT
Efficiency vs Load Current
VOUT = 12V
+
COUT
150µF
VOUT
12V
25A
94
VIN = 48V
VIN = 54V
0
5
10
15
LOAD CURRENT (A)
20
25
4660 TA01b
4660 TA01a
PINS NOT USED IN THIS CIRCUIT: CLKOUT, TEMP+, TEMP–
Rev. 0
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1
LTM4660
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
Terminal Voltages
VIN, VINSNS.............................................. –0.3V to 65V
VOUT, EXTVCC, PGOOD, FAULT................ –0.3V to 20V
MID, MIDSNS........................................ –0.3V to 32.5V
RUN, FREQ, HYS_PRGM, TEMP, VFB, TRACK/SS,
TIMER, MODE/PLLIN, EXT_REF........ –0.3V to INTVCC
Terminal Currents
TEMP+.....................................................–1mA to 1mA
TEMP–....................................................–1mA to 1mA
Temperatures
Internal Operating Temperature
Range (Note 2)................................... –40°C to 125°C
Storage Temperature Range............... –55°C to 125°C
Peak Package Body Temperature
During Reflow.................................................... 245°C
1
2
3
4
5
6
7
8
9
10
11
12
A
B
C–
VIN
VOUT
C
D
GND
E
MID
VINSNS
F
G
C–
C+
MID
H
MIDSNS
INTVCC
J
GND
TEMP+
FAULT
TEST
K
TEMP– EXTVCC TEMP
TIMER
SGND
L
COMPb
RUN
SGND
CLKOUT
M
PGOOD MODE/PLLIN
(All Voltages Relative to GND Unless Otherwise Indicated)
VFB
TRACK/SS
COMPa
EXT_REF
FREQ
HYS_PRGM
BGA PACKAGE
120-LEAD (16mm × 16mm × 10.34mm)
TJMAX = 125°C, θJCtop = 3.92°C/W, θJCbottom = 1.98°C/W, θJA = 7.3°C/W
θ VALUES DETERMINED PER JESD51-12 (SEE NOTE 9), WEIGHT = 9.3g
ORDER INFORMATION
PART MARKING
PART NUMBER
LTM4660EY#PBF
LTM4660IY#PBF
PAD OR BALL FINISH*
DEVICE
FINISH CODE
PACKAGE
TYPE
MSL
RATING
SAC305 (RoHS)
LTM4660Y
e1
BGA
4
• Contact the factory for parts specified with wider operating temperature
ranges. *Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Device temperature grade is indicated by a label on the shipping container.
2
TEMPERATURE RANGE
(SEE NOTE 2)
–40°C to 125°C
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures
• LGA and BGA Package and Tray Drawings
Rev. 0
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LTM4660
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over specified internal
operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = VINSNS = 54V, VOUT = 12V and EXTVCC = 12V
(see Note 4). Configured per Block Diagram circuit with no output load unless otherwise noted.
SYMBOL
PARAMETER
VIN(DC)
Input DC Voltage
VOUT(RANGE)
Output Voltage, Supported Range of
Regulation
VOUT(DC)
Output Voltage Variation
CONDITIONS
MIN
TYP
MAX
UNITS
l
30
60
V
VIN = 54V
l
4.5
18
V
VOUT = 12V, IOUT = 15A (Notes 3, 5)
l
11.8
12
12.2
V
l
8.8
0.38
9.4
V
V
Input Specifications
VIN(UVLO)
Undervoltage Lockout Threshold
VIN Rising
Hysteresis
IS(VIN, FCM)
Input Supply Power Current, in Forced
Continuous Mode
MODE/PLLIN = 0V, IOUT = 0A (Note 6)
MODE/PLLIN = 0V, IOUT = 0.5A
38
150
mA
mA
IS(VIN, PS)
Input Supply Power Current, in PulseSkipping Mode
MODE/PLLIN = INTVCC, IOUT = 0.5A
135
mA
IS(VIN, BM)
Input Supply Power Current, in Burst Mode MODE/PLLIN = Open Circuit, IOUT = 0.5A
120
mA
300
μA
IS(VIN, SHUTDOWN) Input Supply Power Current in Shutdown
Shutdown, VRUN = 0V
Output Specifications
IOUT(DC)
Output Continuous Current Range
(Note 3)
ΔVOUT/VOUT
Line Regulation Accuracy
30 ≤ VIN ≤ 60V, IOUT = 0A
Load Regulation Accuracy
IOUT =15A
30 ≤VIN ≤ 60V, 0A ≤ IOUT ≤ 25A (Note 7)
ΔVOUT(AC)
Output Voltage Ripple
fs
VOUT Ripple Frequency
tStart-Up
Turn-On Start-Up Time
0
0.003
l
0.5
25
A
0.2
%/V
1.5
%
%
150
mVP–P
RFREQ = 61.9kΩ, IOUT = 0A
450
kHz
Capacitor Balancing – Delay Measured from
Toggling RUN on to MID Reaching VIN/2,
CTIMER = 1.47µF, CMID and CFLY = 10µF ×12
Delay Measured from MID Reaching VIN/2 to
PGOOD Exceeding 3V, CTRACK/SS = 0.1µF
300
ms
5
ms
∆VOUT(LS)
Peak Output Voltage Deviation for Dynamic Load: 0W to 150W in 1μs and 150W to 0W in 1μs
Load Step
COUT =150µF ×2, 10µF ×3 (Note 7)
0.3
V
tSETTLE
Settling Time for Dynamic Load Step
Load: 0W to 150W in 1μs and 150W to 0W in 1μs
COUT =150µF ×2, 10µF ×3 (Note 7)
300
µs
VVFB
Regulated VFB Pin Feedback Voltage
IOUT = 0A, VOUT = 12V
IVFB
VFB Pin Leakage Current
(Note 8)
ITRACK/SS
Soft-Start Charge Current
VTRACK/SS = 0V
VINSNS Bias Current
VRUN = 5V, Normal Mode
VRUN = 0V, Shutdown
VRUN
RUN Turn-On Threshold
VRUN Rising
VRUN, HYS
RUN Hysteresis
IRUN
RUN Pull-Up Current
Control Section
l
0.792
0.8
0.808
V
–11
μA
±10
–9
–10
nA
Monitors
IVINSNS
1
45
mA
μA
RUN Enable Pins
VRUN = 0V
l
1.1
1.3
1.6
V
100
mV
1
μA
Rev. 0
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3
LTM4660
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over specified internal
operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = VINSNS = 54V, VOUT = 12V and EXTVCC = 12V
(see Note 4). Configured per Block Diagram circuit with no output load unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Capacitor Voltage-Balancing
VTIMER_LOW
Voltage at TIMER Pin to Start Capacitor
Balancing
0.5
V
VTIMER_HIGH
Voltage at TIMER Pin to Stop Capacitor
Balancing
1.25
V
ITIMER
TIMER Pin Charge Current
VTIMER = 0.9V
VTIMER = 2.8V
VHYS_PRGM
Capacitor Balancing Window Comparator
Threshold
VHYS_PRGM = 0V
VHYS_PRGM = 1.2V
VHYS_PRGM = INTVCC
IHYS_PRGM
HYS_PRGM Pin Current
VHYS_PRGM = 0V
VFAULT
FAULT Pin Voltage Low
IFAULT = 0.6mA
IFAULT
FAULT Leakage Current
VFAULT = 20V
IC+(SOURCE)
IC+(SINK)
IC–(SINK)
IC–(SOURCE)
Current Out of C+ During Capacitor Balancing
VC+ to VC– < VIN/2, VC– = 12V, VIN = 48V (Note 8)
VC+ to VC– > VIN/2, VC– = 12V, VIN = 48V (Note 8)
VC+ to VC– < VIN/2, VC– = 12V, VIN = 48V (Note 8)
VC+ to VC– > VIN/2, VC– = 12V, VIN = 48V (Note 8)
6
mA
IMID(SOURCE)
Current Out of MID During Capacitor Balancing VMID < VIN/2, VMID = VMID_SNS = 23V,
VC+ to VC– ≥ 27V, VC– = 12V, VIN = 48V (Note 8)
60
mA
IMID(SINK)
Current Into MID During Capacitor Balancing
40
mA
Current Into C+ During Capacitor Balancing
Current Into C– During Capacitor Balancing
Current Out of C– During Capacitor Balancing
l
–6
–3
–7
–3.5
–8
–4
±0.3
±1.2
±0.8
l
–9
VMID > VIN/2, VMID = VMID_SNS = 31V,
VC+ to VC– ≥ 27V, VC– = 12V, VIN = 48V (Note 8)
μA
μA
V
V
V
–10
–11
μA
0.2
0.4
V
1
μA
40
mA
6
mA
40
mA
Oscillator and Timer Circuits
fSYNC(RANGE)
External Frequency Synchronization Range
200
fSW
Nominal Switching Frequency
RFREQ = 61.9kΩ
IFREQ
FREQ Setting Current
VFREQ = 0V (Note 8)
RPGOOD
PGOOD Pull-Down Resistance
IPGOOD = 0.6mA
IPGOOD_LEAK
PGOOD Leakage Current
VPGOOD = 20V
1000
450
–9.5
–10
kHz
kHz
–10.5
µA
Power Good
650
Ω
±1
µA
5.95
V
0.8
±2
%
5.8
5.95
V
0.5
±2
%
INTVCC Regulator and EXTVCC Circuits
VINTVCC_INT
VINTVCC_EXT
INTVCC Voltage No Load
10V ≤ VIN ≤ 60V, VEXTVCC = 0V
INTVCC Load Regulation
IINTVCC = 0 to 50mA, VEXTVCC = 0V
INTVCC Voltage No Load with EXTVCC Bias
12V < VEXTVCC < 18V
INTVCC Load Regulation with EXTVCC Bias
IINTVCC = 0 to 50mA, VEXTVCC = 12V
EXTVCC Switchover Voltage
EXTVCC Ramping Positive
EXTVCC Hysteresis
l
5.65
5.65
7
V
200
mV
0.6
V
–2.0
mV/°C
Temperature Sensor
∆VTEMP
Temperature Sensor Forward Voltage,
VTEMP+ to VTEMP–
TC∆V(TEMP)
∆VTEMP Temperature Coefficient
4
ITEMP+ = 100µA and ITEMP– = –100 μA at
TA = 25°C
Rev. 0
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LTM4660
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listing under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating conditions for extended periods may affect device
reliability and lifetime.
Note 2: The LTM4660 is tested under pulsed load conditions such that TJ
≈ TA. The LTM4660E is guaranteed to meet performance specifications
over the 0°C to 125°C internal operating temperature range. Specifications
over the full –40°C to 125°C internal operating temperature range are
assured by design, characterization and correlation with statistical process
controls. The LTM4660I is guaranteed to meet specifications over the full
internal operating temperature range. Note that the maximum ambient
temperature consistent with these specifications is determined by specific
operating conditions in conjunction with board layout, the rated package
thermal resistance and other environmental factors.
Note 3: See output current derating curves for different VIN, VOUT, and TA,
located in the Applications Information section.
Note 4: To reduce internal module temperature rise, it is recommended to
bias EXTVCC. For applications where VOUT > 8V, tie VOUT to EXTVCC. For
applications where VOUT < 8V, it is strongly recommended to drive EXTVCC
with an auxiliary supply.
Note 5: Total DC output voltage error includes all errors over temperature:
line and load regulation as well as the tolerance of the 60.4kΩ feedback
resistor internally connecting VOUT to VFB.
Note 6: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency in forced continuous mode operation.
See Applications Information.
Note 7: Guaranteed by design. Validated from bench measurements.
Note 8: ATE-tested at wafer sort only.
Note 9: θJA value obtained from demo board DC2879A. Refer to Thermal
Considerations in Applications Information section.
Rev. 0
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5
LTM4660
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Output Current
VIN = 48V, VOUT = 12V
98
Efficiency vs Output Current
VIN = 54V, VOUT = 12V
98
fSW = 350kHz
Efficiency for
54VIN, CMID = CFLY = 10μF ×12
98
fSW = 350kHz
97
96
95
94
EFFICIENCY (%)
97
EFFICIENCY (%)
EFFICIENCY (%)
97
96
CFLY, CMID = 10µF ×12
CFLY, CMID = 10µF ×10
CFLY, CMID = 10µF ×8
0
5
10
15
LOAD CURRENT (A)
20
94
25
CFLY, CMID = 10µF ×12
CFLY, CMID = 10µF ×10
CFLY, CMID = 10µF ×8
0
5
10
15
LOAD CURRENT (A)
20
94
93
92
91
VIN = 48V
VIN = 54V
0
5
10
15
LOAD CURRENT (A)
92
25
20
4660 G04
5
10
15
LOAD CURRENT (A)
1800
800
1600
700
1400
1200
1000
800
600
400
0
0
0.5
1
1.5
2
FREQ PIN VOLTAGE (V)
20
25
Oscillator Frequency
vs Temperature
200
25
0
4660 G03
OSCILLATOR FREQUENCY (kHz)
SWITCHING FREQUENCY (kHz)
95
12VOUT, 350kHz
9VOUT, 450kHz
7.5VOUT, 400kHz
5VOUT, 250kHz
93
Switching Frequency
vs
vs FREQ
Voltage at FREQ Pin
96
EFFICIENCY (%)
94
4660 G02
Efficiency for
VOUT = 5V, fSW = 250kHz
6
95
95
4660 G01
90
96
2.5
4660 G05
600
500
400
300
200
100
0
–40
RFREQ = 61.9kΩ
–25
0
25
50
75
TEMPERATURE (°C)
100
125
4660 G06
Rev. 0
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LTM4660
TYPICAL PERFORMANCE CHARACTERISTICS
Steady State Waveforms
VIN = 48V, VOUT = 12V, FCM
Start-Up Characteristics
VIN
50V/DIV
VOUT Ripple
48V
TIMER
1V/DIV
VMID
20V/DIV
FCM
C+
12V/DIV
Burst
Mode
OPERATION
24V
VOUT
10V/DIV
PULSESKIPPING
MODE
C–
12V/DIV
0V
4660 G07
100ms/DIV
1μs/DIV
5μs/DIV
VIN = 48V
VOUT = 12V
COUT = 150μF ×2 + 10μF ×3
COMPa TIED TO COMPb
4660 G09
4660 G08
Line Transient
VIN Slew Rate 10V/ms
Load Transient
12.5A to 25A to 12.5A
VIN
10V/DIV
VOUT
500mV/DIV
AC-COUPLED
VMID
10V/DIV
VOUT
100mV/DIV
AC-COUPLED
ILOAD
10A/DIV
4660 G10
10ms/DIV
VOUT = 12V
POUT = 300W
CMID AND CFLY = 10μF ×12
1ms/DIV
VIN = 48V
VOUT = 12V
COUT = 150μF ×2 + 10μF ×3
COMPa TIED TO COMPb
4660 G11
Radiated EMI Performance (CISPR22 Radiated
Emission Test with Class B 3m Limits)
70
CISPR CLASS B 3M
VERTICAL
HORIZONTAL
AMPLITUDE (dBµV/m)
60
50
40
30
20
10
0
–10
30
130
230
330
430
530
630
FREQUENCY (MHz)
730
830
VIN = 54V
VOUT = 12V
POUT = 300W, fSW = 350kHz
DC2879A, MEASURED IN A 3m CHAMBER, PEAK DETECT METHOD
930 1000
4660 G12
Rev. 0
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7
LTM4660
PIN FUNCTIONS
VOUT (A1-3, B1-3, C1-3, D1-3, E3, F3, G3, H3): Output
Voltage. Bypass to ground with capacitors appropriate for
the application. See Decoupling Requirements.
b. During normal operation, the voltage deviates from
VIN/2 by a window amount set by the voltage on the
HYS_PRGM pin.
VIN (A5, B5, C5, D5, E5): Main Input Supply. Bypass
this pin to GND with at least 2 × 4.7µF X7R- or X7S-type
capacitors with appropriate voltage rating.
c. The die temperature exceeds its internally set limit or
the PTC resistor connected as the lower leg of a resistor
divider (if used) trips the TEMP pin threshold.
C+ (A6, B6, C6, D6, E6, F6, G5-6, H5-6, J6, K6, L6,
M6): Switch Node Connection to One Terminal of Flying
Capacitor. Voltage at this pin swings between VIN/2
and VIN.
During any of the aforementioned conditions, the TRACK/
SS pin will also be pulled low.
C– (A8-11, B8-11, C8-11, D8, E8, F8, G8, H8, J8, K8,
L8, M8): Switch Node Connection to Internal Power
Inductor and One Terminal of Flying Capacitor. Voltage at
this pin swings between ground and VIN/2.
GND (A12, B12, C12, D9-D12, E9-12, F9-12, G9, H9,
J1-2, K1-2, L1-2, M1): Power Ground. Connect all module GND pins to the application’s power ground plane.
MID (E1-2, F1-2, G1-2, G10-12, H1, H10-12, J10-12):
Half Supply from VIN. Do not use this to source current.
Connect MLCC bypass capacitors from this node to GND.
A minimum of 8 × 10µF X7R or X7S MLCC capacitors is
recommended. Higher efficiency can be achieved with
12 × 10µF X7R or X7S MLCC capacitors. All MID pins are
internally connected within the module, but in order for
the LTM4660 to achieve the best possible efficiency, it is
necessary to connect all MID pins together with large copper plane(s) external to the module. See the Applications
Information section.
VINSNS (F5): VIN Kelvin Sensing Input. Used to accurately
sense input voltage. Connect to VIN, under the module.
MIDSNS (H2): MID Kelvin Sensing Input. Used to accurately
sense MID voltage. Connect to MID under the module.
FAULT (J3): Open Drain Output pin. When the signal goes
low, it indicates one of the following conditions:
a. In the capacitor balancing phase, capacitors CFLY or
CMID (see Typical Applications) are not charged to
VIN/2. A low FAULT indicates an abnormal condition
that is preventing CFLY or CMID from being be charged
up to VIN/2.
8
INTVCC (J4): Internal Regulator Output. Powers control
circuits and gate drivers internal to the module. Leave
this pin floating.
TEMP+ (J9): Temperature Sensor, Positive Input. Emitter
of a 2N3906-genre PNP bipolar junction transistor (BJT).
Optionally interface to temperature monitoring circuitry
such as LTC®2997, LTC2990, LTC2974 or LTC2975.
Otherwise leave electrically open.
TEMP– (K9): Temperature Sensor, Negative Input.
Collector-base of a 2N3906-genre PNP bipolar junction
transistor (BJT). Optionally interface to temperature monitoring circuitry such as LTC2997, LTC2990, LTC2974 or
LTC2975. Otherwise leave electrically open.
TIMER (K3): Charge Balancing Timer Input. A capacitor connected from this pin to SGND sets the amount of
time allocated to charge CFLY and CMID to VIN/2 during
the capacitor balancing phase. It also sets the auto-retry
timeout, should the capacitors fail to reach this voltage
within the set time. Capacitors CFLY and CMID begin and
end charging when the TIMER voltage is between 0.5V
and 1.2V, respectively. If the capacitor is balanced before
the TIMER voltage reaches 1.2V, this voltage is reset to
ground and normal operation begins. However, if the balance is not reached when the voltage reaches 1.2V, then
the charging of the capacitors stops and the auto-retry
timeout period begins. The TIMER capacitor will now
slew at half the rate until it reaches 4V and then resets
to zero and begins to slew at 1× rate. Once it reaches
0.5V, the CFLY and CMID begin to charge again and the
process repeats.
TEST (K4): Test Pin. Used in ATE test, only. Leave
open circuit.
Rev. 0
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LTM4660
PIN FUNCTIONS
EXTVCC (K10): External Power Input to an Internal LDO
Connected to INTVCC. This LDO supplies INTVCC power,
bypassing the internal LDO powered from VIN whenever
EXTVCC is higher than 8V. Do not float or exceed 20V on
this pin. Connect EXTVCC to GND, if the features is unused.
To reduce internal module temperature rise, it is strongly
recommended to bias EXTVCC with 8VDC or higher. For
applications where VOUT ≥ 8V, there is an easy way: connect VOUT to EXTVCC. For applications where VOUT < 8V, it
is strongly recommended to drive EXTVCC to 8V (or higher)
with an external bias supply. When driving EXTVCC externally, take precautions to ensure EXTVCC ≤ VIN at all times.
TEMP (K11): Temperature Sensing Input. Using a PTC
resistor as the lower leg of a resistor divider, connect the
TEMP pin to the common point of the divider. The PTC
resistor is used to monitor a hot spot on the PCB. Once
it reaches the TEMP threshold of 1.22V, the LTM4660
stops switching for 100ms before retrying. Ground this
pin if not used.
VFB (K12): Error Amplifier Feedback Input. Connect resistor RVFB from this pin to SGND in order to configure the
VOUT output voltage setting. RVFB is given by Equation 1.
R VFB (kΩ) =
60.4
⎛ VOUT ⎞
− 1⎟
⎜⎝ V
⎠
VFB
(1)
When EXT_REF is connected to INTVCC, the module regulates the VFB pin at 0.8V, nominal. If EXT_REF is used or
TRACK/SS is externally driven to influence the VFB target servo voltage, the value of RVFB must be computed
accordingly. (See the Applications Information section.)
RUN (L3): Run Control Input. A voltage above 1.3V turns
the LTM4660 ON. A voltage below 1.1V causes the module to shutdown. There is a 1μA pull-up current on this
pin when its voltage is below 1.3V.
SGND (L4, L12, M12): Signal Ground. All small-signal
components and compensation components (if used)
should connect to this signal SGND, which connects to
GND internal to the module. It is not necessary to connect
SGND to GND externally.
TRACK/SS (L9): Output Voltage Tracking and Soft-Start
Input. The LTM4660 regulates the VFB voltage to the lowest of three voltages: 0.8V, the voltage on the EXT_REF
pin or the voltage on the TRACK/SS pin. An internal 10μA
pull-up current source is connected to this pin. A capacitor to SGND at this pin sets the ramp time to the final
regulated output voltage. Alternatively, a resistor divider
from another voltage supply connected to this pin allows
the LTM4660 output voltage to track the other supply
during start-up.
HYS_PRGM (L11): There is a 10μA current flowing out
of this pin. A voltage created by connecting a resistor
from this pin to SGND sets an equal amount of window
threshold around VIN/2 to a window comparator. When
the voltage at MIDSNS is not within this window threshold,
FAULT will be pulled low and switching will stop. CFLY and
CMID will be rebalanced to half of VIN before resuming
normal operation.
PGOOD (M2): Power Good Pin. This is an open drain
output. PGOOD is pulled to ground when voltage at VFB
pin falls below 7.5% or rises above 8.5% of its set point.
It will also be pulled low when FAULT is tripped.
MODE/PLLIN (M3): Mode Selection or External
Synchronization Input to Phase Detector. When external
synchronization is not used, this pin selects the operating
modes and can be tied to SGND, to INTVCC or left open
circuit. If the pin is connected to SGND, it enables forced
continuous mode while a connection to INTVCC enables
pulse-skipping mode. Floating the pin enables Burst Mode
operation. For external sync, apply a clock signal to this
pin. The integrated PLL along with its internal compensation network will synchronize the internal oscillator to
external clock. Forced continuous mode will be enabled
when an external clock is applied.
CLKOUT (M4): Clock Output Pin. This pin outputs a
clock 180° out of phase with the main operating clock
of the LTM4660.
EXT_REF (M9): External Reference Input. A voltage
applied to this pin forces the VFB to regulate to this voltage. Internal clamps set at 0.45V and 0.9V limit the lower
and upper bounds of VFB regulation that EXT_REF can
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9
LTM4660
PIN FUNCTIONS
command. Connecting this pin to INTVCC will cause the
internal reference to be used for output voltage regulation.
COMPb (L10): Default Loop Compensation Network.
Connect COMPa to COMPb for default loop compensation—or otherwise, leave open circuit.
COMPa (M10): Current Control Threshold and Error
Amplifier Compensation Point. The current comparator
threshold increases with its COMPa control voltage. Connect
COMPa to COMPb for default loop compensation—or
alternatively, connect a series R-C network from COMPa
to SGND, to apply application-specific loop compensation.
FREQ (M11): Frequency Set Pin. There is a 10μA current
flowing out of this pin. A resistor to ground sets a voltage which in turn programs the switching frequency of
the module.
BLOCK DIAGRAM
VINSNS
1k
4.7nF
RUN
>1.3VTYP = ON
100mVTYP HYSTERESIS
2.2Ω
VIN
CINH
4.7µF
×3
0.1µF
RUN
TEST
C+
EXT_REF
C–
INTVCC
RPGOOD
10k
RFAULT
10k
+
CINL
47µF
VIN
30V TO 60V
CFLY
10µF
×12
10µF
TEMP
PGOOD
FAULT
CLKOUT
POWER
CONTROL
MODE/PLLIN
MID
HYS_PRGM
1k
MIDSNS
CMID
10µF
×12
4.7nF
TIMER
TRACK/SS
1.5µH
VOUT
FREQ
1µF
COMPa
GND
COMPb
RHYS_PRGM
100k
CTRACK/SS
0.1µF
CTIMER
1µF
1µF
10k
RFREQ
61.9k
2.2Ω
SGND
CENTRALLY LOCATED
PNP TEMPERATURE
SENSOR
COUTL
150µF
12V
UP TO 25A
VFB
10nF
SGND
+
EXTVCC
60.4k
22pF
COUTH
22µF
×4
RVFB
4.32k
TEMP+
TEMP–
4660 BD
10
Rev. 0
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LTM4660
DECOUPLING REQUIREMENTS
TA = 25°C. Refer to Block Diagram.
SYMBOL
PARAMETER
CONDITIONS
CFLY
External Flying Capacitor Requirement, 30V ≤ VIN ≤ 60V, VOUT = 12V
CMID
COUT
MIN
TYP
MAX
UNITS
POUT = 300W (Note 3)
80
100
120
μF
External Midpoint Capacitor Requirement, 30V ≤ VIN ≤ 60V, VOUT = 12V POUT = 300W (Note 3)
External Output Capacitor Requirement, 30V ≤ VIN ≤ 60V, VOUT = 12V
POUT = 300W
80
100
120
μF
100
μF
OPERATION
Module Description
LTM4660 is a high efficient Intermediate Bus
Converter (IBC) utilizing a hybrid switched capacitor
topology. Four power switches along with capacitor
bank CFLY and CMID form a switched capacitor stage,
dividing the input voltage by two at MID. Voltage at MID
is further stepped down through a power inductor and
output capacitor, similar to a step down switching converter. LTM4660 employs peak current mode control of
the inductor current for pulse width modulation of the
switches and to maintain accurate output regulation. Soft
switching of the power switches results in excellent efficiency and EMI performance.
Current mode control enables fast cycle-by-cycle current
limiting of the inductor current and hence protects the
internal components of LTM4660 during short-circuit
conditions. With current mode control, LTM4660 exhibits good transient performance and stability margins for
wide range of output capacitors. An internal compensation network included inside LTM4660 is sufficient for
most typical applications. The VFB pin is used to program
the output voltage with a single resistor to ground.
Switching frequency can be programmed by a single
resistor connected between FREQ pin and SGND. Typical
switching frequency for IBC applications with LTM4660 is
300kHz to 500kHz. A phase-locked loop inside the module enables synchronizing the switching frequency to an
external clock.
Pulling the RUN pin below 1.1V forces the regulator into
a shutdown state by turning off all switching and internal
circuits. The TRACK/SS pin is used for programming the
output voltage ramp and voltage tracking during startup. Internal bandgap reference of 0.8V can be overridden
by applying a suitable voltage at EXT_REF pin. See the
Applications Information section.
A general purpose temperature diode is included to monitor internal temperature of the module. In addition, TEMP
pin of the module is used to program the OTP trip point.
Internal overvoltage and undervoltage comparators pull
the open-drain PGOOD output low if the output feedback
voltage exits the regulation window.
Capacitor banks CFLY and CMID connected external to the
µModule, are also part of the energy transfer elements.
LTM4660 utilizes these capacitor-banks to efficiently
deliver energy from input to output. These capacitors
are initially precharged in the Capacitor Balancing phase
using proprietary control techniques. This balancing eliminates large transient currents seen in similar switched
capacitor based topologies. Voltages of capacitor banks
are continuously monitored and balanced by LTM4660.
Dedicated pins TIMER and HYS_PRGM are provided to set
the balancing time interval and voltage window and can
be adjusted for each application of LTM4660. Following
balancing phase, regular switching action begins. During
each switching cycle, capacitor CFLY is connected either
in series with or in parallel to CMID. See Operation and
Applications Information section.
Capacitor Balancing Phase
During initial power up, voltage across the flying capacitor
(CFLY) and CMID are measured. If either of these voltages
are not at VIN/2, the TIMER’s capacitor will be allowed to
charge up. When the TIMER capacitor’s voltage reaches
0.5V, internal current sources to bring CFLY voltage to
VIN/2 are turned ON. After the CFLY voltage has reached
VIN/2, CMID will then be charged to VIN/2. The TRACK/SS
pin is pulled low during this duration. The FAULT pin will
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11
LTM4660
OPERATION
not be pulled low during this initial power up. If the voltages across CFLY and CMID reach VIN/2 before the TIMER
capacitor’s voltage reaches 1.2V, the TRACK/SS will be
released and allowed to charge up. The TIMER pin will
reset to ground and remain there. Normal operation will
begin (see Figure 1a).
PGOOD will also be pulled low. The TRACK/SS pin is also
allowed to charge up upon the completion of balancing
(see Figure 2). Connecting HYS_PRGM to INTVCC sets the
window threshold to ±0.8V around VIN/2.
If, however, the CFLY or CMID voltage is not at VIN/2 when
VTIMER reaches 1.2V, the internal current sources will be
turned OFF and the TIMER capacitor will be charged at half
the initial rate until it reaches 4V. Timer will then be reset
to zero, and the LTM4660 will repeat the above process
again until CFLY and CMID are at VIN/2. (See Figure 1b).
Once the capacitor balancing phase is complete, normal operation begins. Power switches are turned ON/
OFF based on peak current in the power inductor. Peak
inductor current is controlled by voltage on COMPa pin,
which is the output of a transconductance error amplifier.
The VFB pin receives the voltage feedback signal from
VOUT, which is compared to the internal reference voltage by the error amplifier. When load current increases, it
causes a slight decrease in VFB relative to the 0.8V reference voltage, which in turn causes the COMPa voltage to
increase until average inductor current matches the new
load current.
During normal operation, only CMID is monitored for
deviation away from VIN/2 by a window amount set by
a resistor connected from HYS_PRGM to ground. The
voltage across this resistor sets the same amount of window threshold above and below VIN/2. If VCMID leaves this
voltage window, all switching will stop, and the TRACK/
SS pin will be pulled low. Corresponding internal current
sources will be turned on to bring CFLY and CMID voltages
back to VIN/2. FAULT will be pulled low and released once
the balancing is complete. During this balancing period,
FAULT
Main Control Loop
During each switching cycle, capacitor CFLY is connected
in series with or parallel to CMID. Voltage at C+ alternates
between VIN and VIN/2 whereas voltage at C– alternates
between VIN/2 and ground. The voltage at MID and across
CFLY will each be approximately at VIN/2.
FAULT
0V
0V
4V
TIMER
1.2V
0.5V
TIMER
TRACK/SS
1.2V
0.5V
TRACK/SS
(b) More Than One Timer Period
(a) Balancing Completed within One Timer Period
4660 F01
Figure 1. Charge Balancing During Power-Up
FAULT
TIMER
FAULT
1.2V
0.5V
TIMER
1.2V
0.5V
TRACK/SS
TRACK/SS
(a) Balancing Completed within One Timer Period
(b) More Than One Timer Period
4660 F02
Figure 2. Charge Balancing During Normal Operation
12
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LTM4660
APPLICATIONS INFORMATION
The Typical Applications on the first page is a basic
LTM4660 application circuit.
INTVCC/EXTVCC Power
Power for power switch drivers and most internal circuitry
is derived from the INTVCC pin. When the EXTVCC pin is
grounded or tied to a voltage less than 7V, an internal
5.8V linear regulator supplies INTVCC power from VIN. If
EXTVCC is taken above 8V, this linear regulator is turned
OFF and another 5.8V linear regulator turns ON to provide
the INTVCC power from EXTVCC. Using the EXTVCC pin
allows the INTVCC power to be derived from a high efficiency external source, resulting in an overall increase in
LTM4660 efficiency. For LTM4660 applications where VOUT
is greater than 8V, EXTVCC can be directly tied to VOUT.
Shutdown and Start-Up
When RUN pin is below 1.1V, INTVCC linear regulator
along with all the internal circuitry including the main
control loop enters shutdown mode. Releasing the RUN
pin will allow a internal 1μA current source to pull this pin
up, thus enabling LTM4660. RUN pin can also be driven
directly by logic if this voltage does not exceed the absolute maximum rating of 6V.
The slew rate of the output voltage VOUT can be controlled by
the voltage on the TRACK/SS pin. When voltage on TRACK/
SS is less than internal reference voltage of 0.8V (or EXT_
REF if this feature is utilized), the LTM4660 regulates the VFB
voltage to the TRACK/SS voltage instead of to the reference
voltage. This allows TRACK/SS pin to be used to program
the soft-start period by connecting an external capacitor
from the TRACK/SS pin to SGND. After capacitor balancing
phase of LTM4660 is completed, an internal 10μA pull-up
current charges the soft-start capacitor, creating a voltage
ramp. As the voltage on this pin rises linearly from 0V to
the reference voltage (and beyond), output voltage VOUT
rises smoothly from zero to the final set value. Note that
soft-start is achieved not by limiting the maximum output
current of LTM4660 but by controlling the output ramp voltage according to the ramp rate at the TRACK/SS pin. The
total soft-start time can be calculated with Equation 2.
tSOFT-START = 0.8V or VEXT_REF •
Css
10µA
(2)
A 0.1µF capacitor connected between TRACK/SS pin and
SGND would be sufficient for most typical IBC applications with LTM4660.
Output Voltage Tracking
Alternatively, TRACK/SS pin allows start-up of VOUT to track
that of another supply. Typically, this requires connecting
to the TRACK/SS pin an external resistor divider from the
other supply to ground. Tracking can be configured to be
either coincident or ratiometric as shown in Figure 3. In
the following discussions, VOUT1 refers to another supply’s
output while VOUT2 refers to the LTM4660 output that tracks
VOUT1. To implement the coincident tracking in Figure 3a,
connect an additional resistive divider to VOUT1 and connect
its midpoint to the TRACK/SS pin of the LTM4660. The ratio
of this divider should be the same as that of the slave channel’s feedback divider shown in Figure 4a. In this tracking
mode, VOUT1 must be higher than VOUT2. This ensures the
final voltage on TRACK/SS pin is greater than 0.8V.
To implement ratiometric tracking shown in Figure 3b,
connect a resistor divider R1 and R2 from external supply
to TRACK/SS pin of LTM4660. Select R1 and R2 such that
when external supply reaches steady state, final voltage
on TRACK/SS is less than 0.8V. Use this final voltage to
select FB resistor R4 (see Figure 4b). Output voltage VOUT2
of LTM4660 which ratiometrically tracks external supply
voltage VOUT1 is given by Equation 3.
VOUT2 =
60.4k
R4
R1
1+
R2
VOUT1 1+
(3)
In order to track down another supply after the soft-start
has successfully reached 82.5% of 0.8V or VEXT_REF, it is
recommended to set the LTM4660 into forced continuous mode operation by setting the MODE/PLLIN = 0V. By
selecting different resistors, the LTM4660 can achieve different modes of tracking including the two in Figure 3. The
ratio-metric mode has lesser output accuracy on VOUT2
but is fully coupled to any variations in VOUT1. In both
modes, there is an error in output voltage setting caused
by the pin current of TRACK/SS. To minimize this error,
use smaller resistor values in the divider.
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13
LTM4660
APPLICATIONS INFORMATION
VOUT1
OUTPUT VOLTAGE
OUTPUT VOLTAGE
VOUT1
VOUT2
VOUT2
TIME
TIME
(a) Coincident Tracking
(b) Ratio-Metric Tracking
4660 F03
Figure 3. Two Different Methods of Output Voltage Tracking
VOUT1
EXTERNAL
SUPPLY
VOUT2
FROM LTM4660
R3
TO TRACK/SS
PIN OF LTM4660
60.4k (INTERNAL)
R1
TO TRACK/SS
PIN OF LTM4660
TO VFB PIN
OF LTM4660
R4
VOUT2
FROM LTM4660
VOUT1
EXTERNAL
SUPPLY
R4
R2
(a) Coincident Tracking Setup
60.4k (INTERNAL)
TO VFB2
PIN OF
LTM4660
R4
(b) Ratio-Metric Tracking Setup
4660 F04
Figure 4. Setup for Coincident and Ratio-Metric Tracking
Burst Mode Operation, Pulse-Skipping Mode, or
Forced Continuous Mode
The LTM4660 can be enabled to enter high efficiency
Burst Mode operation, constant-frequency pulse-skipping
mode, or forced continuous mode. To select forced continuous operation, tie the MODE/PLLIN pin to SGND. To
select pulse-skipping mode of operation, tie the MODE/
PLLIN pin to INTVCC. To select Burst Mode operation,
float the MODE/PLLIN pin. When the controller is enabled
for Burst Mode operation, if the average inductor current
is higher than the load current, the error amplifier will
decrease the voltage on the COMPa pin. When the COMPa
voltage drops below 0.5V, the internal sleep signal goes
high (enabling sleep mode) and switching is turned off.
In sleep mode, the load current is supplied by the output
capacitor. As the output voltage decreases, the voltage
on COMPa pin begins to rise. When the output voltage
drops enough, the sleep signal goes low, and the controller resumes normal operation by turning on the power
switches on the next cycle of the internal oscillator. When
14
a controller is enabled for Burst Mode operation, the controller operates in discontinuous operation. In forced continuous operation, the peak inductor current is determined
by the voltage on the COMPa pin. Switching frequency
is constant as set by RFREQ resistor and inductor current remains continuous through the switching period.
In this mode, the efficiency at light loads is lower than in
Burst Mode operation. However, continuous mode has
the advantages of faster response to load transients and
less interference with audio circuitry. When the MODE/
PLLIN pin is connected to INTVCC, the LTM4660 operates in PWM pulse-skipping mode at light loads. At very
light loads, switching is off for few numbers of cycles
(i.e., skipping pulses) and the part operates in discontinuous mode. This mode, like forced continuous operation, exhibits low output ripple as well as low audio noise
and reduced RF interference as compared to Burst Mode
operation. At light loads, pulse-skipping mode provides
higher efficiency than forced continuous mode, but not
nearly as high as Burst Mode operation. Regardless of the
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LTM4660
APPLICATIONS INFORMATION
mode selected by MODE/PLLIN pin, LTM4660 will always
operate in pulse-skipping mode during start-up.
Frequency Selection and Phase-Locked Loop
The switching frequency of the LTM4660 can be selected
using the FREQ pin. If the MODE/PLLIN pin is not being
driven by an external clock source, the FREQ pin can be
used to program the controller’s operating frequency
from 200kHz to 1MHz. There is a 10µA current flowing
out of the FREQ pin, so the user can program the controller’s switching frequency with a single resistor to SGND.
Figure 5 shows variation of switching frequency versus
resistor connected from FREQ pin to SGND. For typical
datacenter IBC applications of LTM4660 with VIN = 48V
or 54V bus voltage and with VOUT = 12V, choose FREQ
resistor to be 40k to 60k for maximum efficiency.
SWITCHING FREQUENCY (kHz)
1400
1200
1000
800
Temperature Monitoring
The LTM4660 can provide hotspot monitoring via the
TEMP pin. By using a PTC thermistor as the lower leg of a
resistor divider and connecting the common point of this
divider to the TEMP pin, the voltage increases drastically
when the temperature reaches beyond the Curie point of
the PTC thermistor as shown in Figure 6. The characteristic of the PTC thermistor is shown in Figure 7. When the
TEMP pin reaches 1.22V, all switching stops for 100ms.
The voltage on the TRACK/SS pin and FAULT is pulled
low and is released after 100ms (Figure 8) if the voltage
on the TEMP pin goes below 1.1V during this 100ms
timeout. If the TEMP pin voltage remains above 1.1V, the
timeout period will be extended until the voltage drops
below 1.1V. The temperature that is used to trigger the
hotspot protection will determine the thermistor selection.
This temperature will be the Curie point of the thermistor,
which is often defined as having two times its resistance
at 25°C. With the Curie point resistance of the thermistor
known, R2CURIE, the upper resistance, R1, can be selected
by Equation 4.
600
R1=
R2CURIE (VEXT – 1.22)
1.22
(4)
400
200
A diode-connected PNP transistor is connected internally between pins TEMP+ and TEMP–. The transistor is
centrally located inside LTM4660, in close proximity to
the hotspot. Voltage derived from the TEMP+ and TEMP–
pins provides a close estimate of the internal temperature
of LTM4660.
0
0
50
100
150
200
RESISTOR AT FREQ (kΩ)
4660 F05
Figure 5. Variation of Switching Frequency vs
Resistor Connected from FREQ Pin to SGND
A phase-locked loop (PLL) is integrated on the LTM4660
to synchronize the internal oscillator to an external clock
source that is connected to the MODE/PLLIN pin. Rising
edge of C– pin synchronizes to the rising edge of the
external clock source. The controller operates in forced
continuous mode when it is synchronized. The phaselocked loop is capable of locking any frequency within the
range of 200kHz to 1MHz. The frequency setting resistor
should always be present to set the controller’s initial
switching frequency before locking to the external clock.
VEXT
LTM4660
R1
TEMP
PTC
R2
4660 F06
Figure 6. Temperature Monitoring Setup
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15
LTM4660
RESISTANCE OF THERMISTOR (LOG Ω)
APPLICATIONS INFORMATION
Frequency Compensation
The LTM4660 μModule employs peak current mode control for pulse width modulation of the power switches.
This method of control simplifies the compensation
design by eliminating the dynamics of the power inductor
contributing to the closed loop response. A Type-II network is sufficient to compensate the LTM4660 feedback
loop. Such a network comprises of a resistor in series
with capacitor connected at COMPa pin—the output of
a transconductance error amplifier inside LTM4660, to
SGND. A high frequency roll-off capacitor of 22pF, as part
of the Type-II network is already connected at the COMPa
pin internal to LTM4660.
CURIE POINT
25°C
TEMPERATURE OF THERMISTOR (°C)
4660 F07
Figure 7. Characteristic of a Thermistor
TEMP TRIP LEVEL = 1.22V
TEMP
C–
100ms
TRACK/SS
FAULT
4660 F08
Figure 8. Temperature Trip Characteristic
Power Good
When VFB pin voltage falls below 7.5% or rises above
8.5% of the internal 0.8V reference or the reference set by
EXT_REF, the PGOOD pin is pulled low. The PGOOD pin is
also pulled low when the RUN pin is below 1.1V or when
the LTM4660 is in the soft-start or tracking phase. The
PGOOD pin will flag power good immediately when the
VFB pin is within the reference window. However, there is
an internal 50µs power bad mask when VFB goes out this
window. The PGOOD pin can be pulled up by an external
resistor to sources of up to 20V.
FAULT
During initial power up of the LTM4660 or when enabling
the part via the RUN pin, the FAULT pin will not be pulled
low even when CFLY and/or CMID need to be rebalanced to
VIN/2. But during normal operation, when rebalancing is
needed, the FAULT will be pulled low. Another condition
that causes the FAULT to go low is thermal shutdown,
either caused by the internal temperature reaching 150°C
or the voltage at TEMP pin reaching 1.22V. The FAULT
pin is allowed to be pulled up by an external resistor to
sources of up to 20V.
16
Choose the components of the Type-II network dependent
on the desired output response for line and load variations
as well as loop stability parameters phase margin and gain
margin of the feedback loop. In general, selecting a low
capacitance and a high resistance for the Type-II network
at COMPa pin leads to fast transient response but may
adversely affect the loop stability parameters.
A resistor capacitor network of 10k in series with 10nF is
connected from COMPb pin to SGND internal to LTM4660.
For most LTM4660 applications, it is sufficient to tie
COMPa and COMPb pins together to ensure closed loop
stability across line and load variations. Refer to LTM4660
model in LTspice® to fine tune and optimize the Type-II
network for each application circuit with LTM4660.
Input Capacitor Selection
The LTM4660 module should be connected to a low
AC-impedance DC source. For the regulator input, two
10μF input ceramic capacitors are required for RMS ripple
current. A 33μF or 47μF surface mount aluminum electrolytic bulk capacitor can be used for more input bulk
capacitance. This bulk input capacitance is only needed
if the input source impedance is compromised by long
inductive leads. If low impedance power planes are used,
then this bulk capacitor is not needed. For IBC applications with 48V or 54V bus, choose input capacitors rated
to at least 100V.
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LTM4660
APPLICATIONS INFORMATION
Without considering the inductor current ripple, the
RMS current of the input capacitor can be estimated by
Equation 5.
ICIN(RMS) =
IOUT(MAX)
2 • η%
•
(D
• D´ )
(5)
where D is 2 • VOUT/VIN and D’ = 1 – D
In the above equation, η% is the estimated efficiency of the
power module. The bulk capacitor can be a switcher-rated
electrolytic aluminum capacitor or Polymer capacitor.
the temperature rise of the capacitor to be below 20°C,
preferably 10°C. The temperature rise of the capacitor is
dependent on the amount of RMS current through the
capacitor and the operating frequency.
Ceramic capacitors also have a large voltage coefficient, losing close to half their capacitance when the DC bias across a
given capacitor is half its rated voltage. The DC bias effect on
a capacitor is greater when the case size is smaller. Factor in
these effects when deciding on the capacitance.
The ripple voltage on CFLY and CMID is given by Equation 6.
Output Capacitor Selection
The LTM4660 is designed to achieve good transient
response and low output voltage ripple. Choose COUT
with low ESR to meet the output ripple and transient performance requirements. Place at least two 10μF output
ceramic capacitors close to VOUT and GND pins. This lowers the output ripple by lowering the total ESR of COUT.
Aluminum electrolytic capacitors of 100μF or 150μF can
be placed further away as bulk output capacitors. Choose
enough bulk capacitance to meet the transient specification
demanded by downstream loads. When choosing COUT, be
aware of the impact of its ESR on loop stability. Refer to
LTM4660 model in LTspice to optimize and fine tune the
combination of COUT for each LTM4660 application.
CFLY and CMID Selection
For the LTM4660 μModule, capacitor banks CFLY and CMID
connected external to the μModule, are part of the energy
transfer elements. Therefore, ceramic capacitors are attractive since they have the lowest ESR. However, care should be
taken when choosing this type of capacitors. During operation
the DC voltage across CFLY and CMID is approximately half
the VIN supply, therefore the voltage rating of the capacitors
should be greater than that. As a general rule, select the voltage rating of the capacitor to be twice the operating voltage
of the capacitor. For the same voltage rating and capacitance,
a larger case size will have a lower failure rate.
In addition, the operating temperature of the capacitors needs to be considered. For operating temperature
above 85°C, capacitors with the X7R dielectric need to
be used while X5R dielectric is adequate for operation
below 85°C. For long term reliability of the capacitor, keep
VRIPPLE =
IOUT
2VOUT
CBANK • fSW VIN
(6)
where CBANK is either CFLY or CMID, IOUT is output current
and fSW is the switching frequency.
Ripple voltage on CFLY and CMID contributes significantly
to the power dissipated in LTM4660 (see Efficiency figures in Typical Performance Characteristics section). As a
good starting point, select enough capacitance such that
the ripple on each capacitor is less than 1% of the DC
bias voltage of the capacitor. For example, if the DC bias
voltage of the capacitor is 24V, keep the ripple to be less
than 240mV. To achieve lowest loss in LTM4660, select
the capacitance of CMID to be same as that of CFLY.
LTM4660 is designed to deliver 300W of output power
at 12VOUT. For maximum efficiency at 300W, use eight
to twelve 10μF ceramic capacitors each for CMID and
CFLY. Considering the voltage derating of ceramic capacitors, for bus voltages in range of 48VIN to 54VIN, choose
ceramic capacitors rated to at least 50V.
Timer and Hysteresis
The LTM4660 μModule uses a switched capacitor hybrid
topology where the switched capacitor stage consists of CFLY
and CMID capacitor banks connected alternately in series or in
parallel through the power switches inside LTM4660. During
start-up, CFLY and CMID capacitors are completely discharged.
Starting switching with the capacitors discharged may lead
to undesirably high currents through the power switches.
To circumvent this phenomenon, LTM4660 uses a patented
technology to balance the charge across the CFLY and CMID
to half of VIN during start-up.
Rev. 0
For more information www.analog.com
17
LTM4660
APPLICATIONS INFORMATION
A TIMER capacitor of 1μF is sufficient for VIN of up to 60V
and CMID = CFLY = 10μF • 12.
HYS_PRGM Voltage
The voltage on the HYS_PRGM pin sets a window centered on VIN/2 for fault protection purposes. During
operation, if the voltage at MID_SNS deviates beyond
this window, a fault is indicated, and capacitor balancing
begins. Therefore, setting the correct window is important as it adds another layer to of protection to LTM4660
application circuit.
given by Equation 7. Always set VOUT to be less than half
of the minimum expected input voltage.
60.4k ⎞
⎛
VOUT = 0.8V • ⎜ 1 +
⎟
⎝
R1 ⎠
(7)
Applying a voltage on EXT_REF pin between 0.45V and
0.9V allows LTM4660’s output to track the EXT_REF voltage, indicated by the characteristic in Figure 9.
0.9•(1+60.4k/R1)
VOUT
Capacitor connected at TIMER pin to SGND defines the
time-period during which LTM4660 enters capacitor
balancing phase. An internal current source at the pin
charges the TIMER capacitor generating a voltage ramp.
Capacitor balancing is initiated when the voltage at this
pin is between 0.5V and 1.2V. Choose this capacitor
based on the maximum input voltage and the capacitance
of capacitor banks CFLY and CMID. Higher input voltage
and higher capacitance indicates more time necessary for
LTM4660 to complete capacitor balancing, hence requiring a larger TIMER capacitor. Choosing a smaller TIMER
capacitor leads to LTM4660 using multiple TIMER cycles
to complete capacitor charge balancing leading to longer
start-up times.
0.45•(1+60.4k/R1)
0.45V
VEXT_REF
0.9V
4660 F09
Figure 9. Output Voltage Set by EXT_REF Pin
Due to its unique architecture, the optimal efficiency for
the LTM4660 is when VOUT = VIN/4. Efficiency for stepdown ratios higher or lower than 4:1 may be lower. For
applications that demand optimal efficiency within a range
of VIN, EXT_REF could be used to track this VIN variation
while maintaining a 4:1 step down ratio at the output. In
this type of setup, the output voltage will also change
with the input. Figure 10 shows a 48V to 12V setup that
accounts for VIN variation between 36V to 60V.
VIN
(36V TO 60V)
VOUT
(9V TO 14.9V)
During normal operation, voltage at MID may settle to
a voltage less than VIN/2 depending on the impedance
looking into MID and output current. In general, higher
the IOUT, higher would be the deviation of MID from
VIN/2. Similarly, lower the CMID and switching frequency,
higher the impedance looking into MID. In addition to
the DC offset of MID relative to VIN/2, the AC ripple on
CMID is also to be considered (Refer to Equation 6 in
CFLY and CMID Selection section) when choosing the
HYS_PRGM window.
Minimum On-Time Considerations
For most LTM4660 applications, a hysteresis window of
1V is sufficient to ensure proper operation. To set the
window to 1V, connect a 100k resistor from HYS_PRGM
to SGND.
Minimum on-time tON(MIN) is the smallest time duration
that LTM4660 is able to turn on its power switches. Low
duty cycle applications may approach minimum on-time
limit and care should be taken to ensure Equation 8.
R6
6.98k
18
TO
EXT_REF
PIN
TO
VFB
PIN
R2
3.98k
4660 F10
Figure 10. Output Voltage to Track VIN in 4:1 Ratio
Output Voltage Setting
The LTM4660 uses its internal reference of 0.8V
when EXT_REF is tied to INTVCC. The output voltage is
R1
60.4k (INTERNAL)
R5
464k
2VOUT
1
•
>t
VIN
fSW ON(MIN)
For more information www.analog.com
(8)
Rev. 0
LTM4660
APPLICATIONS INFORMATION
If duty cycle falls below what can be accommodated by the
minimum on-time, the LTM4660 will begin to skip cycles.
Output voltage will continue to be regulated but ripple
voltage and current will increase. tON(MIN) for LTM4660 is
210ns for 4:1 step-down ratios and it linearly increases for
higher step-down ratios. To avoid running into minimum
on-time of LTM4660 switching, it is recommended that
switching frequency be reduced to 200kHz to 400kHz for
input output step down ratios greater than 6:1.
Dual Phase Operation
For higher output power applications, two LTM4660s can
be easily paralleled to create a dual phase single output
configuration. Figure 23 shows the key signal connections
between the two LTM4660s.
Thermal Considerations
The thermal resistances reported in the Pin Configuration
section are consistent with those parameters defined by
JESD 51-9 and are intended for use with finite element
analysis (FEA) software modeling tools that leverage the
outcome of thermal modeling, simulation, and correlation
to hardware evaluation performed on a μModule package
mounted to a hardware test board—also defined by JESD
51-9 (“Test Boards for Area Array Surface Mount Package
Thermal Measurements”). The motivation for providing these thermal coefficients is found in JESD 51‑12
(“Guidelines for Reporting and Using Electronic Package
Thermal Information”).
Many designers may opt to use laboratory equipment and
a test vehicle such as the demo board to anticipate the
μModule regulator’s thermal performance in their application at various electrical and environmental operating
conditions to compliment any FEA activities. Without
FEA software, the thermal resistances reported in the
Pin Configuration section are in-and-of themselves not
relevant to providing guidance of thermal performance;
instead, the derating curves provided in the data sheet can
be used in a manner that yields insight and guidance pertaining to one’s application-usage and can be adapted to
correlate thermal performance to one’s own application.
The Pin Configuration section typically gives four thermal
coefficients explicitly defined in JESD 51-12; these coefficients are quoted or paraphrased below:
1. θJA, the thermal resistance from junction to ambient,
is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed
enclosure. This environment is sometimes referred to
as “still air” although natural convection causes the
air to move. This value is determined with the part
mounted to a JESD 51-9 defined test board, which
does not reflect an actual application or viable operating condition.
2. θJCbottom, the thermal resistance from junction to the
bottom of the product case, is the junction-to-board
thermal resistance with all of the component power
dissipation flowing through the bottom of the package.
In the typical μModule, the bulk of the heat flows out
the bottom of the package, but there is always heat
flow out into the ambient environment. As a result, this
thermal resistance value may be useful for comparing
packages, but the test conditions don’t generally match
the user’s application.
3. θJCtop, the thermal resistance from junction to top of
the product case, is determined with nearly all of the
component power dissipation flowing through the top
of the package. As the electrical connections of the
typical μModule are on the bottom of the package, it
is rare for an application to operate such that most of
the heat flows from the junction to the top of the part.
As in the case of θJCbottom, this value may be useful
for comparing packages, but the test conditions don’t
generally match the user’s application.
4. θJB, the thermal resistance from junction to the printed
circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the
bottom of the μModule and into the board and is really
the sum of the θJCbottom and the thermal resistance of
the bottom of the part through the solder joints and
through a portion of the board.
A graphical representation of the aforementioned thermal
resistances is given in Figure 11; blue resistances are
Rev. 0
For more information www.analog.com
19
LTM4660
APPLICATIONS INFORMATION
contained within the μModule regulator, whereas green
resistances are external to the μModule.
a software-defined JEDEC environment consistent with
JSED 51-9 to predict power loss heat flow.
As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD 51-12 or provided in the
Pin Configuration section replicates or conveys normal
operating conditions of a μModule. For example, in normal board-mounted applications, never does 100% of
the device’s total power loss (heat) thermally conduct
exclusively through the top or exclusively through bottom
of the μModule—as the standard defines for θJCtop and
θJCbottom, respectively. In practice, power loss is thermally dissipated in both directions away from the package granted, in the absence of a heat sink and airflow, a
majority of the heat flow is into the board.
The LTM4660 package has been designed such that
inductor on top also doubles as a heat sink, removing heat
from the power switches below. The bottom substrate
material has very low thermal resistance to the printed
circuit board. An external heat sink can be applied to the
top of the device for excellent heat sinking with airflow.
Within a SIP (system-in-package) module, be aware there
are multiple power devices and components dissipating
power, with a consequence that the thermal resistances
relative to different junctions of components or die are not
exactly linear with respect to total package power loss. To
reconcile this complication without sacrificing modeling
simplicity—but also, not ignoring practical realities—an
approach has been taken using FEA software modeling
along with laboratory testing in a controlled-environment
chamber to reasonably define and correlate the thermal
resistance values supplied in this data sheet: (1) Initially,
FEA software is used to accurately build the mechanical
geometry of the μModule and the specified PCB with all
of the correct material coefficients along with accurate
power loss source definitions; (2) this model simulates
Figure 12 shows a thermal capture of LTM4660 with 48V
input, 12V output at 25A without heat sink and 200LFM
airflow condition.
Recommended PCB footprint
The high integration of LTM4660 makes the PCB board
layout very simple and easy. However, to optimize its
electrical and thermal performance, some layout considerations are still necessary.
• Use large PCB copper areas for high current paths,
including VIN, GND, VOUT. It helps to minimize the PCB
conduction loss and thermal stress.
• Place high frequency ceramic input and output capacitors next to the VIN, MID, GND and VOUT pins to minimize high frequency noise.
• Use short loops to route CFLY capacitors from C+ to C–.
Reduce the parasitic trace inductance and resistance
in this loop.
θJA, JUNCTION-TO-AMBIENT RESISTANCE
μModule DEVICE
CASE (TOP)-TO-AMBIENT
RESISTANCE
θJCtop, JUNCTION-TO-CASE (TOP)
RESISTANCE
θJB, JUNCTION-TO-BOARD RESISTANCE
JUNCTION
θJCbot, JUNCTION-TO-CASE
(BOTTOM) RESISTANCE
CASE (BOTTOM)-TO-BOARD
RESISTANCE
AMBIENT
BOARD-TO-AMBIENT
RESISTANCE
4660 F11
Figure 11. Graphical Representation of Thermal Coefficients, Including JESD51-12 Terms
20
Rev. 0
For more information www.analog.com
LTM4660
APPLICATIONS INFORMATION
• Do not put via directly on the pad unless they are
capped or plated over.
• Use a separated SGND ground copper area for components connected to signal pins. SGND is connected
to GND internal to the module.
• For parallel modules, tie the VOUT, VFB, and COMP pins
together. Use an internal layer to closely connect these
pins together. The TRACK pin can be tied a common
capacitor for regulator soft-start.
• Bring out test points on the signal pins for monitoring.
4660 F12
Figure 12. Thermal Image 48V to 12V, 25A; 200LFM Airflow; No
Heat Sink (Based on 6-Layer PCB with 2oz Copper on All Layers)
• Place a dedicated power ground layer underneath
the unit.
• To minimize the via conduction loss and reduce module
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
Figure 13 gives a good example of the recommended
layout for input, output, CFLY and CMID capacitors on the
top layer. Pinout of LTM4660 is designed such that CFLY
capacitors can be conveniently placed on the bottom
layer right underneath the module, with minimal impact
to total PCB area. (See Figure 14 for example of bottom
layer layout).
GND
GND
MID
GND
CMID
CMID
CMID
CMID
CMID
CMID
CMID
CMID
MID
CFLY
12
12
11
11
10
10
9
9
8
8
7
C+ 6
7
5
5
4
4
3
3
2
2
CFLY
C–
CFLY
CFLY
VIN
CIN1
GND
CIN2
C–
CFLY
CFLY
CFLY
CFLY
C+
6
1
1
A
B
C
D
E
F
G
H
J
K
L
A
M
B
C
D
E
F
G
H
J
K
L
M
COUT1
COUT2
VOUT
GND
4660 F14
4660 F13
Figure 13. Recommended Layout for Top Layer
Figure 14. Recommended Layout for Bottom Layer
Rev. 0
For more information www.analog.com
21
LTM4660
APPLICATIONS INFORMATION
Table 1. Bulk and Ceramic Capacitor Manufacturers
CIN (BULK)
VENDORS
VALUE
Panasonic
33μF, 80V
COUT (BULK)
PART NUMBER
VENDORS
VALUE
EEHZA1K330
Panasonic
150μF, 16V
PART NUMBER
16SVPC150
CFLY, CMID
CIN (CERAMIC)
VENDORS
VALUE
PART NUMBER
VENDORS
VALUE
PART NUMBER
Murata
2.2μF, 100V, 1210, X7R
GRM32DR72A225KA12
Murata
10μF, 100V, 1210, X7S
GRM32EC72A106KE05
TDK
2.2μF, 100V, 1210, X7R
C3225X7R2A225K230AB
TDK
10μF, 100V, 1210, X7R
C3225X7R2A106K250AC
Murata
10μF, 50V, 1210, X7S
GCM32EC71H106KA03
VENDORS
VALUE
PART NUMBER
TDK
10μF, 50V, 1210, X7R
C3225X5R1H106K250AB
Murata
10μF, 25V, 1210, X7S
GCM32EC7YA106KA03
TDK
10μF, 25V, 1210, X7R
C3225X7R1E106K250AC
COUT (CERAMIC)
Table 2. Component Selection Table for Typical LTM4660 Applications
VIN
(V)
VOUT
(V)
IOUT = 25A
CIN
(BULK)
(μF)
CIN
(CERAMIC)
(μF)
COUT
(BULK)
(μF)
COUT
(CERAMIC)
(μF)
CFLY
(μF)
CMID
(μF)
RVFB
(kΩ)
RFREQ
(kΩ)
RHYS_PRGM
(kΩ)
TIMER
(μF)
48
12
33
10
150 ×2
10 ×3
10 ×10
10 ×10
4.32
49.9
100
1
54
12
22
10
150 ×2
10 ×3
10 ×12
10 ×12
4.32
49.9
100
1
48
5
33
10
100 ×2
10 ×2
10 ×12
10 ×12
11.49
39.9
100
1
54
9
22
10
100 ×2
10 ×2
10 ×10
10 ×10
5.92
43.2
100
1
Safety Considerations
Radiated EMI Noise
The LTM4660 does not provide galvanic isolation between
the input and output. There is no internal fuse. If required,
a slow blow fuse with a rating of twice the maximum input
current needs to be provided to protect each unit from
catastrophic failure. The device does support over current
protection. The temperature diode along with TEMP pin
can be used to detect the need for thermal shutdown that
can be done by controlling the RUN pin.
Potential for EM interference (EMI) is inherent to all
switching regulators. Fast switching turn-on and turnoff of the power MOSFETs—necessary for achieving
high efficiency—create high frequency (~30MHz +) di/dt
changes within DC/DC converters. This activity tends to
be the dominant source of high frequency EMI radiation in
such systems. The high level of device integration within
LTM4660 along with soft switching of power MOSFETs
delivers low radiated EMI noise performance. EMI graph
in the Typical Performance Characteristics section shows
an example of LTM4660 meeting radiation emission limits
established by CISPR22 Class B.
BGA pinout of LTM4660 is such that high voltage pins (VIN
and C+) have a clearance of one BGA ball from adjacent
lower voltage pins.
Power Derating
Derating curves in Figure 15 to Figure 20 can be used to
calculate approximate values of θJA thermal resistance
with various airflow conditions.
22
Rev. 0
For more information www.analog.com
LTM4660
(CMID and CFLY = 10μF × 12, unless otherwise specified)
30
30
25
25
25
20
15
10
0LFM
200LFM
400LFM
5
0
20
30
40
LOAD CURRENT (A)
30
LOAD CURRENT (A)
LOAD CURRENT (A)
APPLICATIONS INFORMATION
20
15
10
0LFM
200LFM
400LFM
5
0
50 60 70 80 90 100 110
TEMPERATURE (°C)
20
30
40
10
0
Figure 16. 54V to 12V Derating
Curve, No Heat Sink
25
25
0LFM
200LFM
400LFM
5
0
20
30
40
20
15
10
0LFM
200LFM
400LFM
5
50 60 70 80 90 100 110
TEMPERATURE (°C)
4660 F18
Figure 18. 48V to 5V Derating
Curve, No Heat Sink
LOAD CURRENT (A)
25
LOAD CURRENT (A)
30
10
30
40
50 60 70 80 90 100 110
TEMPERATURE (°C)
Figure 17. 48V to 15V Derating
Curve, No Heat Sink
30
15
20
4660 F17
30
20
0LFM
200LFM
400LFM
4660 F16
Figure 15. 48V to 12V Derating
Curve, No Heat Sink
LOAD CURRENT (A)
15
5
50 60 70 80 90 100 110
TEMPERATURE (°C)
4660 F15
20
0
20
30
40
20
15
10
0LFM
200LFM
400LFM
5
50 60 70 80 90 100 110
TEMPERATURE (°C)
4660 F19
Figure 19. 48V to 12V Derating
Curve, No Heat Sink, CFLY and
CMID = 10μF × 10
0
20
30
40
50 60 70 80 90 100 110
TEMPERATURE (°C)
4660 F20
Figure 20. 48V to 12V Derating
Curve, No Heat Sink, CFLY and
CMID = 10μF × 8
Rev. 0
For more information www.analog.com
23
LTM4660
TYPICAL APPLICATIONS
10k
VIN
VINSNS
RUN
INTVCC
EXT_REF
10k
C+
FAULT
PGOOD
HYS_PRGM
TIMER
COMPa
LTM4660
COMPb
100k
1µF
C–
MIDSNS
MID
FREQ
TRACK/SS
49.9k
VFB
0.1µF
EXTVCC
VOUT
MODE/PLLIN
4.32k
TEMP
SGND
PGND
10µF
×2
+
VIN
36V TO
60V
33µF
CFLY
10µF
50V
×12
CMID
10µF
50V
×12
22µF
×2
+
VOUT
12V
25A
150µF
×2
4660 F21
Figure 21. 12VOUT 25A Intermediate Bus Converter
10k
1µF
10µF
×2
C+
VFB
0.1µF
11.49k
MODE/PLLIN
C–
MIDSNS
MID
EXTVCC
VOUT
TEMP
SGND
PGND
33µF
95
8V
×2
12
96
CMID
10µF
50V
×12
+
22µF
Efficiency and Power Loss for 48V
to 5V vs Load Current
VIN
48V
CFLY
10µF
50V
×12
FREQ
TRACK/SS
39.9k
+
150µF
×2
VOUT
5V
25A
94
8
93
6
92
4
POWER LOSS
91
90
4660 F22a
10
EFFICIENCY
2
FCM
fSW = 250kHz
0
5
10
15
LOAD CURRENT (A)
20
POWER LOSS (W)
100k
FAULT
PGOOD
HYS_PRGM
TIMER
COMPa
LTM4660
COMPb
VIN
VINSNS
EFFICIENCY (%)
10k
RUN
INTVCC
EXT_REF
25
0
4660 F22b
Figure 22. A 48V to 5V Step-Down Converter
24
Rev. 0
For more information www.analog.com
LTM4660
TYPICAL APPLICATIONS
10k
10k
1µF
49.9k
2.16k
COMPa
COMPb
C–
U1
LTM4660
MIDSNS
MID
FREQ
TRACK/SS
EXTVCC
VFB
MODE/PLLIN
VOUT
SGND
CLKOUT
CFLY
10µF
50V
×12
10µF
×12
CMID
10µF
50V
×12
CMID
10µF
50V
×12
10µF
×12
150µF
×4
22µF
×2
VOUT
12V, 50A
PGND
RUN
INTVCC
EXT_REF
C+
CFLY
10µF
50V
×12
22µF
×2
TEMP
FAULT
PGOOD
HYS_PRGM
TIMER
C–
MIDSNS
MID
U2
LTM4660
COMPa
COMPb
100k
1µF
FREQ
TRACK/SS
EXTVCC
VOUT
VFB
100k
MODE/PLLIN
TEMP
PGND
SGND
4660 F23a
Current Sharing
25
MODULE OUTPUT CURRENT (A)
1µF
C+
VIN
VINSNS
10µF
×2
100µF
×2
VINSNS
FAULT
PGOOD
HYS_PRGM
TIMER
100k
VIN
36V TO 60V
VIN
RUN
INTVCC
EXT_REF
U1 OUTPUT CURRENT
U2 OUTPUT CURRENT
20
15
10
5
0
0
10
20
30
LOAD CURRENT (A)
40
50
4660 F23b
Figure 23. LTM4660 Configured for Dual Phase Operation: 48V to 12V at 50A Step-Down Converter
Rev. 0
For more information www.analog.com
25
LTM4660
PACKAGE DESCRIPTION
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
LTM4660 BGA Pinout
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
A1
VOUT
B1
VOUT
C1
VOUT
D1
VOUT
E1
MID
F1
MID
A2
VOUT
B2
VOUT
C2
VOUT
D2
VOUT
E2
MID
F2
MID
A3
VOUT
B3
VOUT
C3
VOUT
D3
VOUT
E3
VOUT
F3
VOUT
A4
(NO PIN)
B4
(NO PIN)
C4
(NO PIN)
D4
(NO PIN)
E4
(NO PIN)
F4
(NO PIN)
A5
VIN
B5
VIN
C5
VIN
D5
VIN
E5
VIN
F5
VINSNS
A6
C+
B6
C+
C6
C+
D6
C+
E6
C+
F6
C+
A7
(NO PIN)
B7
(NO PIN)
C7
(NO PIN)
D7
(NO PIN)
E7
(NO PIN)
F7
(NO PIN)
A8
C–
B8
C–
C8
C–
D8
C–
E8
C–
F8
C–
A9
C–
B9
C–
C9
C–
D9
GND
E9
GND
F9
GND
A10
C–
B10
C–
C10
C–
D10
GND
E10
GND
F10
GND
A11
C–
B11
C–
C11
C–
D11
GND
E11
GND
F11
GND
A12
GND
B12
GND
C12
GND
D12
GND
E12
GND
F12
GND
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
G1
MID
H1
MID
J1
GND
K1
GND
L1
GND
M1
GND
G2
MID
H2
MIDSNS
J2
GND
K2
GND
L2
GND
M2
PGOOD
G3
VOUT
H3
VOUT
J3
FAULT
K3
TIMER
L3
RUN
M3
MODE/PLLIN
G4
(NO PIN)
H4
(NO PIN)
J4
INTVCC
K4
TEST
L4
SGND
M4
CLKOUT
G5
C+
H5
C+
J5
(NO PIN)
K5
(NO PIN)
L5
(NO PIN)
M5
(NO PIN)
G6
C+
H6
C+
J6
C+
K6
C+
L6
C+
M6
C+
G7
(NO PIN)
H7
(NO PIN)
J7
(NO PIN)
K7
(NO PIN)
L7
(NO PIN)
M7
(NO PIN)
G8
C–
H8
C–
J8
C–
K8
C–
L8
C–
M8
C–
K9
TEMP–
L9
TRACK/SS
M9
EXT_REF
G9
GND
H9
GND
J9
TEMP+
G10
MID
H10
MID
J10
MID
K10
EXTVCC
L10
COMPb
M10
COMPa
G11
MID
H11
MID
J11
MID
K11
TEMP
L11
HYS_PRGM
M11
FREQ
G12
MID
H12
MID
J12
MID
K12
VFB
L12
SGND
M12
SGND
26
Rev. 0
For more information www.analog.com
X
15.40
0.630 ±0.025 Ø 120x
Y
E
D
15.40
PACKAGE TOP VIEW
3.1750
SUGGESTED PCB LAYOUT
TOP VIEW
3.1750
4
1.9050
PIN “A1”
CORNER
0.6350
0.0000
0.6350
aaa Z
1.9050
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
more by
information
www.analog.com
6.9850
5.7150
4.4450
3.1750
1.9050
0.6350
0.0000
0.6350
1.9050
3.1750
4.4450
5.7150
6.9850
Z
SYMBOL
A
A1
A2
b
b1
D
E
e
F
G
H1
H2
H3
aaa
bbb
ccc
ddd
eee
fff
DETAIL A
NOM
10.34
0.60
1.82
0.75
0.63
16.00
16.00
1.27
13.97
13.97
0.32
1.50
7.92
0.37
1.55
8.12
0.15
0.10
0.20
0.30
0.15
0.35
MAX
10.74
0.70
1.92
0.90
0.66
DIMENSIONS
DETAIL B
A2
SUBSTRATE THK
MOLD CAP HT
INDUCTOR HT
BALL DIMENSION
PAD DIMENSION
BALL HT
NOTES
PACKAGE SIDE VIEW
H3
INDUCTOR
A
TOTAL NUMBER OF BALLS: 120
0.27
1.45
7.72
MIN
9.94
0.50
1.72
0.60
0.60
ddd M Z X Y
eee M Z
H1
SUBSTRATE
DETAIL B
H2
MOLD
CAP
b1
ccc Z
A1
// f f f Z
6.9850
5.7150
4.4450
4.4450
5.7150
6.9850
(Reference LTC DWG # 05-08-1623 Rev Ø)
Øb (120 PLACES)
// bbb Z
BGA Package
120-Lead (16mm × 16mm × 10.34mm)
e
11
b
10
9
7
G
6
5
PACKAGE BOTTOM VIEW
8
4
e
3
2
1
DETAIL A
DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
4
6
TRAY PIN 1
BEVEL
!
PACKAGE IN TRAY LOADING ORIENTATION
LTMXXXX
µModule
PIN 1
6
3
SEE NOTES
M
L
K
J
H
G
F
E
D
C
B
A
SEE NOTES
BGA 120 0418 REV Ø
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
5. PRIMARY DATUM -Z- IS SEATING PLANE
BALL DESIGNATION PER JESD MS-028 AND JEP95
3
2. ALL DIMENSIONS ARE IN MILLIMETERS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
COMPONENT
PIN “A1”
F
b
12
LTM4660
PACKAGE DESCRIPTION
aaa Z
Rev. 0
27
Z
LTM4660
PACKAGE PHOTOS
Part marking is either ink mark or laser mark
DESIGN RESOURCES
SUBJECT
µModule Design and Manufacturing Resources
µModule Regulator Products Search
DESCRIPTION
Design:
• Selector Guides
• Demo Boards and Gerber Files
• Free Simulation Tools
Manufacturing:
• Quick Start Guide
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability
1. Sort table of products by parameters and download the result as a spread sheet.
2. Search using the Quick Power Search parametric table.
Digital Power System Management
Analog Devices’ family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTM4664
54VIN Dual 25A or Single 30A µModule Regulator
with PMBus Interface
30V ≤ VIN ≤ 58V, 0.5V ≤ VOUT ≤ 1.5V, 16mm × 16mm × 7.72mm BGA
LTM4664A
54VIN Dual 30A or Single 60A µModule Regulator
with PMBus Interface
30V ≤ VIN ≤ 58V, 0.5V ≤ VOUT ≤ 1.5V, 16mm × 16mm × 7.72mm BGA
LTM4681
Quad 31.25A or Single 125A µModule Regulator
with PMBus Interface
4.5V ≤ VIN ≤ 16V, 0.5V ≤ VOUT ≤ 3.3V, 15mm × 22mm × 8.17mm BGA
LTM4700
Dual 50A or Single 100A µModule Regulator
with PMBus Interface
4.5V ≤ VIN ≤ 16V, 0.5V ≤ VOUT ≤ 1.8V, 15mm × 22mm × 7.87mm BGA
LTM4680
Dual 30A or Single 60A µModule Regulator
with PMBus Interface
4.5V ≤ VIN ≤ 16V, 0.5V ≤ VOUT ≤ 3.3V, 16mm × 16mm × 7.82mm BGA
LTM4678
Dual 25A or Single 50A µModule Regulator
with PMBus Interface
4.5V ≤ VIN ≤ 16V, 0.5V ≤ VOUT ≤ 3.3V, 16mm × 16mm × 5.86mm BGA
LTM4650
Dual 25A or Single 50A µModule Regulator
4.5V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 1.8V, 16mm × 16mm × 5.01mm BGA
LTM4650A
Dual 25A or Single 50A µModule Regulator
with High VOUT Range
4.5V ≤ VIN ≤ 16V, 0.6V ≤ VOUT ≤ 5.5V, 16mm × 16mm × 5.01mm BGA,
16mm × 16mm × 4.41mm LGA
28
Rev. 0
04/22
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