LTM4662
Dual 15A or Single 30A
DC/DC µModule Regulator
FEATURES
DESCRIPTION
Dual 15A or Single 30A Output
nn Wide Input Voltage Range: 4.5V to 20V
nn 2.375V
MIN with CPWR Bias
nn Output Voltage Range: 0.6V to 5.5V
nn ±1.5% Maximum Total DC Output Error
nn Multiphase Current Sharing
nn Differential Remote Sense Amplifier, Each Channel
nn Current Mode Control/Fast Transient Response
nn Up to 96% Efficiency
nn Adjustable Switching Frequency (250kHz to 1MHz)
nn Frequency Synchronization
nn Overcurrent Foldback Protection
nn Output Overvoltage Protection
nn Internal or External Compensation
nn Built-In Temperature Monitor Diode
nn SnPb or RoHS Compliant Finish
nn Thermally Enhanced (11.25mm × 15mm × 5.74mm)
BGA Package
nn Pin-Compatible with the LTM4646
The LTM®4662 is a complete dual 15A output switching
mode DC/DC power supply. Included in the package are
the switching controller, power FETs, inductors, and all
supporting components. Operating from an input voltage
range of 4.5V to 20V, the LTM4662 supports two outputs
each with an output voltage range of 0.6V to 5.5V, set by
external resistors. Its high efficiency design delivers up to
15A continuous current for each output. Only a few input
and output capacitors are needed.
nn
APPLICATIONS
Point-of-Load Power Supplies
Telecom and Networking Equipment
nn Industrial and Medical Equipment
nn
The device supports frequency synchronization, multiphase
operation, high efficiency light load operation and output
voltage tracking for supply rail sequencing and has an
onboard temperature diode per channel for device temperature monitoring. High switching frequency and a current
mode architecture enable a very fast transient response to
line and load changes without sacrificing stability.
Fault protection features include overvoltage and overcurrent protection. The power module is offered in a small
footprint and thermally enhanced 11.25mm × 15mm ×
5.74mm BGA package. The LTM4662 is available with
SnPb or RoHS compliant terminal finish.
All registered trademarks and trademarks are the property of their respective owners.
nn
TYPICAL APPLICATION
10μF
×4
Efficiency,
12V to 0.9V, 1.2V at 15A Each
130k
VIN1 VIN2 CPWR
RUN1
INTVCC
RUN2
VOUT1
0.9V
AT 15A
DRVCC
VOUT1
LTM4662
VFB1
60.4k
VOUTS1–
0.1µF
VOUT2
1.2V
AT 15A
VFB2
121k
COMP1A
COMP1B
TRACK/SS1
90
4.7µF
VOUT2
VOUTS2
VOUTS1
100μF
×4
95
VRNG
MODE_PLLIN
30.1k
100µF
×4
VOUTS2–
FREQ
115k
SGND GND
85
80
75
COMP2A
COMP2B
TRACK/SS2
4662 TA01a
EFFICIENCY (%)
VIN
4.5V
TO 20V
0.1µF
PINS NOT USED IN THIS CIRCUIT:
PGOOD1, PGOOD2, EXTVCC,
TEMP1+, TEMP1–, TEMP2+, TEMP2–
PHASMD, CLKOUT, SW1, SW2
70
12VIN TO 0.9V EFF, 300kHz
12VIN TO 1.2V EFF, 350kHz
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
LOAD CURRENT (A)
4662 TA01b
Rev. A
Document Feedback
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1
LTM4662
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
CPWR, VIN1, VIN2........................................ –0.3V to 22V
VSW1, VSW2.................................................... –2V to 22V
PGOOD1, PGOOD2, RUN1, RUN2, DRVCC,
INTVCC, EXTVCC, VOUT1, VOUT2, VOUTS1,
VOUTS2...................................................... –0.3V to 6V
TRACK/SS1, TRACK/SS2.............................. –0.3V to 5V
FREQ, VRNG, PHASMD,
MODE_PLLIN.......................... –0.3V to (INTVCC+0.3)
VOUTS1– (Note 6)........................................ –0.3V to VFB1
VOUTS2–, VFB1 (Note 6)..............–0.3V to (INTVCC+0.3V)
COMP1A, COMP2A (Note 6)...................... –0.3V to 2.7V
COMP1B, COMP2B, VFB2........................... –0.3V to 2.7V
DRVCC Peak Output Current..................................100mA
Internal Operating Temperature
Range (Note 2)................................... –40°C to 125°C
Storage Temperature Range................... –55°C to 125°C
Peak Solder Reflow Package Body Temperature..... 245°C
1
2
3
TOP VIEW
4
5
6
7
A
VIN2
TEMP2+
B
VOUT2
8
TEMP2–
GND
C
D
E
F
G
–
SGND VOUTS2 RUN2
VRNG
COMP2B VOUTS2 COMP2A VFB2
GND
EXTVCC
PGOOD2
MODE_
FREQ TRACK/SS2 PLLIN CLKOUT
COMP1B VOUTS1 COMP1A VFB1
SW2
CPWR
INTVCC
PGOOD1
DRVCC
PHASMD SGND TRACK/SS1 RUN1
H
VOUTS1–
SW1
GND
J
VOUT1
TEMP1–
K
GND
VIN1
TEMP1+
L
BGA PACKAGE
88-LEAD (15mm × 11.25mm × 5.74mm)
TJMAX = 125°C, θJA = 7°C/W, θJCbottom = 1.5°C/W,
θJCtop = 3.7°C/W, θJB + θBA ≅ 7°C/W
θ VALUES DEFINED PER JESD51-12
WEIGHT = 2.2g
ORDER INFORMATION
PART MARKING*
PART NUMBER
LTM4662EY#PBF
LTM4662IY#PBF
LTM4662IY
BALL FINISH
SAC305 (RoHS)
SnPb (63/37)
DEVICE
FINISH CODE
LTM4662Y
LTM4662Y
LTM4662Y
• Contact the factory for parts specified with wider operating temperature
ranges. *Device temperature grade is indicated by a label on the shipping
container. Ball finish code is per IPC/JEDEC J-STD-609.
2
PACKAGE
TYPE
MSL
RATING
BGA
3
e1
TEMPERATURE RANGE
(SEE NOTE 2)
–40°C to 125°C
e0
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures
• LGA and BGA Package and Tray Drawings
Rev. A
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LTM4662
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel. TA = 25°C, VIN = 12V and VRUN1, VRUN2 at 5V
unless otherwise noted. Per the typical application in Figure 20.
SYMBOL
PARAMETER
CONDITIONS
MIN
VIN(DC)
Input DC Voltage
2.375V with 5V External Bias on CPWR, 4.5V
Min without Bias
VCPWR(DC)
Input Control Power Voltage
Input Range of Bias
Normally Connected to VIN
VOUT1, 2(Range)
Output Voltage Range
(Note 8)
l
0.6
VOUT1(DC),
VOUT2(DC)
Output Voltage, Total Variation
with Line and Load
CIN = 10µF ×4, COUT = 100µF ×4 Ceramic
VOUT = 1.5V
l
1.4775
RUN Pin On/Off Threshold
RUN Rising
l
TYP
MAX
UNITS
2.375
20
V
4.5
20
V
5.5
V
1.5
1.5225
V
1.2
1.3
Input Specifications
VRUN1, VRUN2
1.1
VRUN1HYS, VRUN2HYS RUN Pin On Hysteresis
V
160
mV
100
kΩ
RRUN1, RRUN2
RUN1, RUN2 Resistance
Pull-Down Resistance
IINRUSH(VIN)
Input Inrush Current at Start-Up
IOUT = 0A, CIN = 10µF ×4, CSS = 0.01µF,
COUT = 100µF ×4, VOUT1 = 1.5V, VOUT2 = 1.5V,
VIN = 12V
1
A
IQ(VIN)
Input Supply Bias Current
IOUT = 0.1A, fSW = 1MHz, Pulse-Skipping Mode
IOUT = 0.1A, fSW = 1MHz, Switching Continuous
Shutdown, RUN = 0, VIN = 12V
20
45
40
mA
mA
µA
IS(VIN)
Input Supply Current
VIN = 4.5V, VOUT = 1.5V, IOUT = 15A
VIN = 12V, VOUT = 1.5V, IOUT = 15A
IOUT1(DC), IOUT2(DC)
Output Continuous Current Range
VIN = 12V, VOUT = 1.5V (Notes 7, 8)
ΔVOUT1(LINE)/VOUT1
ΔVOUT2(LINE)/VOUT2
Line Regulation Accuracy
ΔVOUT1(LOAD)/VOUT1
ΔVOUT2(LOAD)/VOUT2
Load Regulation Accuracy
5.9
2.15
A
A
Output Specifications
0
15
VOUT = 1.5V, VIN from 4.5V to 20V
IOUT = 0A for Each Output
l
0.01
0.025
For Each Output, VOUT = 1.5V, 0A to 15A
VIN = 12V (Note 7)
l
0.15
0.3
A
%/V
%
VOUT1(AC), VOUT2(AC) Output Ripple Voltage
For Each Output, IOUT = 0A,
COUT = 100µF ×4, VIN = 12V,
VOUT = 1.5V, Frequency = 350kHz
15
mVP-P
fS (Each Channel)
Output Ripple Voltage Frequency
VIN = 12V, VOUT = 1.5V, RFREQ = 115kΩ (Note 4)
350
kHz
∆VOUTSTART
(Each Channel)
Turn-On Overshoot
COUT = 100µF ×4, VOUT = 1.5V, IOUT = 0A
VIN = 12V, CSS = 0.01µF
10
mV
tSTART
(Each Channel)
Turn-On Time
COUT = 100µF ×4, No Load,
TRACK/SS with 0.01µF to GND, VIN = 12V
5
ms
∆VOUT(LS)
(Each Channel)
Peak Deviation for Dynamic Load
Load: 0A to 6A to 0A
COUT = 100µF ×4,
VIN = 12V, VOUT = 1.5V
50
mV
tSETTLE
(Each Channel)
Settling Time for Dynamic Load Step Load: 0A to 6A to 0A
COUT = 100µF ×4,
VIN = 12V, VOUT = 1.5V
20
µs
IOUT(PK)
(Each Channel)
Output Current Limit
22
A
VIN = 12V, VOUT = 1.5V
Rev. A
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3
LTM4662
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel. TA = 25°C, VIN = 12V and VRUN1, VRUN2 at 5V
unless otherwise noted. Per the typical application in Figure 20.
SYMBOL
PARAMETER
CONDITIONS
VFB1
Voltage at VFB1 Pin
IOUT = 0A, VOUT = 1.5V
VFB2
Voltage at VFB2 Pin
IOUT = 0A, VOUT = 1.5V
VFB2 is Gained Back Up by 2× Internal to 0.6V
MIN
TYP
MAX
UNITS
l
0.592
0.600
0.608
V
l
0.296
0.3
0.304
V
0
±50
nA
l
0.630
0.315
0.645
0.323
0.660
0.330
V
V
Control Section
IFB1, IFB2
(Note 6)
VOVL1, VOVL2
Feedback Overvoltage Lockout
VFB1 Rising, VFB2 Rising
ITRACK/SS1,
ITRACK/SS2
Track Pin Soft-Start Pull-Up Current
TRACK/SS1,TRACK/SS2 = 0V
UVLO
INTVCC Undervoltage Lockout
INTVCC Falling VIN (Note 6)
INTVCC Rising VIN
tOFF(MIN)
Minimum Top Gate Off-Time
(Note 6)
tON(MIN)
Minimum Top Gate On-Time
(Note 6)
RFBHI1, RFBHI2
Resistor Between VOUTS1, VOUTS2
and VFB1, VFB2 Pins for Each Output
VPGOOD1, VPGOOD2
Low
PGOOD Voltage Low
IPGOOD = 2mA
IPGOOD
PGOOD Leakage Current
VPGOOD = 5V
VPGOOD
PGOOD Trip Level
VFB with Respect to Set Output Voltage
VFB Ramping Negative
VFB Ramping Positive
1.0
3.3
3.7
4.2
µA
4.5
90
ns
30
59.9
V
V
ns
60.4
60.9
kΩ
0.1
0.3
V
2
µA
–2
–7.5
7.5
%
%
Internal Linear Regulator
DRVCC
Internal DRVCC Voltage
6V < CPWR < 20V
DRVCC
Load Regulation
DRVCC Load Regulation
ICC = 0mA to 100mA
VEXTVCC
EXTVCC Switchover Voltage
EXTVCC Ramping Positive
VEXTVCC(DROP)
EXTVCC Dropout
ICC = 20mA, VEXTVCC = 5V
VEXTVCC(HYST)
EXTVCC Hysteresis
5.0
4.4
5.3
5.6
V
–1.3
–3.0
%
4.6
4.8
V
80
120
mV
200
mV
Frequency and Clock Synchronization
Frequency Nominal
Nominal Frequency
RFREQ = 115kΩ
Frequency Low
Lowest Frequency
RFREQ = 165kΩ (Note 5)
Frequency High
Highest Frequency
RFREQ = 39.2kΩ
RMODE_PLLIN
MODE_PLLIN Input Resistance
MODE_PLLIN to SGND
600
kΩ
Channel 2 Phase
VOUT2 Phase Relative to VOUT1
PHASMD = SGND
PHASMD = Float
PHASMD = INTVCC
180
180
240
Deg
Deg
Deg
CLKOUT Phase
Phase (Relative to VOUT1)
PHASMD = SGND
PHASMD = Float
PHASMD = INTVCC
60
90
120
Deg
Deg
Deg
VPLLIN High
VPLLIN Low
Clock Input High Level to MODE_PLLIN
Clock Input Low Level to MODE_PLLIN
4
300
350
400
250
900
2
1000
kHz
kHz
1100
0.5
kHz
V
V
Rev. A
For more information www.analog.com
LTM4662
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel. TA = 25°C, VIN = 12V and VRUN1, VRUN2 at 5V
unless otherwise noted. Per the typical application in Figure 20.
SYMBOL
PARAMETER
CONDITIONS
MIN
fSYNC
(Each Channel)
Frequency Sync Capture Range
MODE_PLLIN Clock Duty Cycle = 50%
250
VRNG ILIMIT
SET Current Limit
Per Channel
VRNG = INTVCC, IOUT to 15A, ILIMIT ~22A
VRNG = SGND, IOUT to 7.5A, ILIMIT ~11A
15
7.5
A
A
tD(PGOOD)
Delay from VFB Fault (OV/UV) to
PGOOD Falling
(Note 6)
50
μs
tD(PGOOD)
Delay from VFB Fault (OV/UV Clear)
to PGOOD
(Note 6)
20
μs
VTEMP1, VTEMP2
TEMP Diode Voltage
ITEMP = 100µA
0.598
V
TC VTEMP1,2
VTEMP Temperature Coefficient
–2.0
mV/°C
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTM4662 is tested under pulsed load conditions such
that TJ ≈ TA. The LTM4662E is guaranteed to meet specifications from
0°C to 125°C internal temperature. Specifications over the –40°C to
125°C internal operating temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTM4662I is guaranteed over the full –40°C to 125°C internal operating
temperature range. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
impedance and other environmental factors.
TYP
MAX
UNITS
1000
kHz
Note 3: Two outputs are tested separately and the same testing condition
is applied to each output.
Note 4: The switching frequency is programmable from 250kHz to 1000kHz.
Note 5: LTM4662 device is optimized to operate from 300kHz to 750kHz.
Note 6: These parameters are tested at wafer sort.
Note 7: See output current derating curves for different VIN, VOUT and TA.
Note 8: For 6V ≤ VIN ≤ 20V, the 3.3 to 5V output current needs to be
limited to 13A/channel. All other input and output combinations are 15A/
channel with recommended switching frequency included in the efficiency
graphs. Derating curves and airflow apply.
Rev. A
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5
LTM4662
TYPICAL PERFORMANCE CHARACTERISTICS
95
95
95
90
90
90
85
5VIN TO 0.9V EFF, 350kHz
5VIN TO 1.0V EFF, 350kHz
5VIN TO 1.2V EFF, 350kHz
5VIN TO 1.5V EFF, 350kHz
5VIN TO 1.8V EFF, 450kHz
5VIN TO 2.5V EFF, 450kHz
5VIN TO 3.3V EFF, 450kHz
80
75
70
85
80
75
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
LOAD CURRENT (A)
70
8VIN TO 0.9V EFF, 350kHz
8VIN TO 1.0V EFF, 350kHz
8VIN TO 1.2V EFF, 350kHz
8VIN TO 1.5V EFF, 450kHz
8VIN TO 1.8V EFF, 500kHz
8VIN TO 2.5V EFF, 600kHz
8VIN TO 3.3V EFF, 750kHz
8VIN TO 5.0V EFF, 950kHz
85
80
75
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
LOAD CURRENT (A)
4662 G01
70
12VIN TO 0.9V EFF, 300kHz
12VIN TO 1.0V EFF, 300kHz
12VIN TO 1.2V EFF, 350kHz
12VIN TO 1.5V EFF, 450kHz
12VIN TO 1.8V EFF, 500kHz
12VIN TO 2.5V EFF, 650kHz
12VIN TO 3.3V EFF, 800kHz
12VIN TO 5.0V EFF, 950kHz
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
LOAD CURRENT (A)
4662 G03
4662 G02
Dual Phase Single Output Efficiency
vs Output Current, VIN = 12V
100
EFFICIENCY (%)
100
EFFICIENCY (%)
100
100
EFFICIENCY (%)
Efficiency vs Output Current,
VIN = 12V
Efficiency vs Output Current,
VIN = 8V
Efficiency vs Output Current,
VIN = 5V
0.9V Single Phase Single Output
Load Transient Response
1V Single Phase Single Output
Load Transient Response
EXTVCC = 5V
EFFICIENCY (%)
95
90
IOUT
7.5A/DIV
IOUT
7.5A/DIV
0.9VOUT
50mV/DIV
1VOUT
50mV/DIV
85
12V–1V EFF, 300kHz
12V–1.2V EFF, 300kHz
12V–1.5V EFF, 350kHz
12V–1.8V EFF, 450kHz
12V–2.5V EFF, 650kHz
12V–3.3V EFF, 800kHz
12V–5V EFF, 950kHz
80
75
70
50µs/DIV
1 4 6 8 10 12 14 16 18 20 22 24 26 28 30
LOAD CURRENT (A)
50µs/DIV
4662 G05
4662 G06
COUT = 470µF POSCAP, 5mΩ,
100µF ×4, CERAMIC
CCOMP = 100pF,
f = 350kHz
COUT = 470µF POSCAP, 5mΩ,
100µF ×4, CERAMIC
CCOMP = 100pF,
f = 350kHz
1.5V Single Phase Single Output
Load Transient Response
1.8V Single Phase Single Output
Load Transient Response
4662 G04
1.2V Single Phase Single Output
Load Transient Response
IOUT
7.5A/DIV
IOUT
7.5A/DIV
IOUT
7.5A/DIV
1.2VOUT
50mV/DIV
1.5VOUT
50mV/DIV
1.8VOUT
50mV/DIV
50µs/DIV
COUT = 470µF POSCAP, 5mΩ,
100µF ×4, CERAMIC
CCOMP = 100pF,
f = 350kHz
6
4662 G07
50µs/DIV
COUT = 100µF ×3, CERAMIC
CCOMP = 100pF, CFF = 47pF
f = 450kHz
4662 G08
50µs/DIV
4662 G09
COUT = 100µF ×3, CERAMIC
CCOMP = 100pF, CFF = 47pF
f = 500kHz
Rev. A
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LTM4662
TYPICAL PERFORMANCE CHARACTERISTICS
2.5V Single Phase Single Output
Load Transient Response
IOUT
7.5A/DIV
2.5VOUT
100mV/DIV
50µs/DIV
3.3V Single Phase Single Output
Load Transient Response
5V Single Phase Single Output
Load Transient Response
IOUT
5A/DIV
IOUT
5A/DIV
3.3VOUT
100mV/DIV
5VOUT
100mV/DIV
50µs/DIV
4662 G10
50µs/DIV
4662 G11
4662 G12
COUT = 100µF ×2, CERAMIC
CCOMP = 100pF, CFF = 47pF
f = 500kHz
COUT = 100µF ×1, CERAMIC
CCOMP = 100pF, CFF = 47pF
f = 750kHz
COUT = 100µF ×1, CERAMIC
CCOMP = 100pF, CFF = 47pF
f = 950kHz
Single Phase Single Output
Start‑Up, No Load
Single Phase Single Output
Start‑Up, 15A Load
Two-Phase Switching and Ripple
VOUT
0.5V/DIV
VOUT
0.5V/DIV
VOUT
5V/DIV
VOUT
10mV/DIV
IOUT
10A/DIV
IOUT
1A/DIV
50ms/DIV
20ms/DIV
4662 G13
12VIN, 1.5VOUT AT NO LOAD
COUT = 470µF ×1, 2.5V, SANYO POSCAP,
100µF ×4, 6.3V, CERAMIC
SOFT-START CAPACITOR = 0.1µF
USE RUN PIN TO CONTROL START-UP
1µs/DIV
4662 G14
12VIN, 1.5VOUT AT 15A LOAD
COUT = 470µF ×1, 2.5V, SANYO POSCAP,
100µF ×4, 6.3V, CERAMIC
SOFT-START CAPACITOR = 0.1µF
USE RUN PIN TO CONTROL START-UP
Short-Circuit Protection, No Load
4662 G15
12V TO 1V AT 30A TWO-PHASE
12V TO 1V AT 350kHz
RIPPLE AT 30A LOAD
COUT = 330μF, 9mΩ, 100μF ×4, CERAMIC
Short-Circuit Protection, 15A Load
VOUT
500mV/DIV
VOUT
500mV/DIV
IIN
1A/DIV
IOUT
1A/DIV
VIN = 12V
VOUT = 1.5V
IOUT = NO LOAD
20ms/DIV
20ms/DIV
4662 G16
4662 G17
VIN = 12V
VOUT = 1.5V
IOUT = 15A
Rev. A
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7
LTM4662
PIN FUNCTIONS
(Recommended to Use Test Points to Monitor Signal Pin Connections.)
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
VOUT1 (H1, J1-J2, K1-K2, L1-L2): Power Output Pins.
Apply output load between these pins and GND pins.
Recommend placing output decoupling capacitance
directly between these pins and GND pins. There is a
49.9Ω resistor connected between VOUT1 and VOUTS1 to
protect the output from an open VOUTS1. Review Table 5.
See Note 8 in the Electrical Characteristics section for
output current guideline.
GND (A3, A6-A7, B3, B6-B7, C3-C7, D6-D7, E6, E8, F5,
F7, G6, G8, H6-H7, J4-J7, K3, K6-K7, L3, L6-L7 ): Power
Ground Pins for Both Input and Output Returns.
VOUT2 (A1-A2, B1-B2, C1-C2, D1): Power Output Pins.
Apply output load between these pins and GND pins.
Recommend placing output decoupling capacitance
directly between these pins and GND pins. There is a
49.9Ω resistor connected between VOUT2 and VOUTS2 to
protect the output from an open VOUTS2. Review Table 5.
See Note 8 in the Electrical Characteristics section for
output current guideline.
VOUTS1, VOUTS2 (G2, E2): These pins are connected to
the top of the internal top feedback resistor for each output. Each pin can be directly connected to its specific
output, or connected to the remote sense point of VOUT.
It is important to connect these pins to their designated
outputs for proper regulation.
In paralleling modules, the VOUTS1 pin is left floating, and
the VFB1 pin is connected to INTVCC. This will disable channel 1’s error amplifier and internally connect COMP1A to
COMP2A. The PGOOD1 and TRACK/SS1 will be disabled
in this mode. Channel 2’s error amplifier will regulate the
two channel single output. See VFB pin description and
Applications Information section.
FREQ (F1): Frequency Set Pin. A resistor from this pin to
SGND sets the operating frequency. The Equation:
41550
8
f(kHz)
– 2.2 = RFREQ (kΩ)
An external clock applied to MODE_PLLIN should be
within ±30% of this programmed frequency to ensure
frequency lock. See the Applications Information section.
SGND (D3, H3): Signal Ground Pin. Return ground path
for all analog and low power circuitry. Tie a single connection to the output capacitor GND in the application.
See layout guidelines in Figure 19.
VFB1 (G4): This pin is the + input to a unity gain differential amplifier. This pin is connected to VOUTS1 with a 60.4k
precision resistor internal. Different output voltages can be
programmed with an additional resistor between VFB1 and
VOUTS1– pins. The differential amplifier is feeding back the
divided down output voltage from a remote sense divider
network to compare to the internal 0.6V reference. In 2-phase
single output operation, tie the VFB1 pin to INTVCC. See
Figure 1 and Applications Information section for details.
VFB2 (E4): This pin is the + input to a non-inverting gain
of two amplifier utilizing three resistors in the feedback
network to develop a remote sense divider network. This
pin is connected to VOUTS2 with an internal 60.4k precision resistor. The VOUT2 voltage is divided down to 0.3V
then gained back up to 0.6V to compare with the internal
0.6V reference. This technique provides for equivalent
remote sensing on VOUT2. See Figure 1 and Applications
Information section for details.
TRACK/SS1,TRACK/SS2 (H4, F2): Output Voltage Tracking
Pin and Soft-Start Inputs. Each channel has a 1.0μA pull‑up
current source. Each pin can be programmed with a softstart ramp rate up to the 0.6V internal reference level, then
beyond this point the internal 0.6V reference will control
the feedback loop. When one channel is configured to be
master of the two channels, then a capacitor from this pin
to ground will set the soft-start ramp rate. The remaining
channel can be set up as the slave, and have the master’s
output applied through a voltage divider to the slave output’s track pin. This voltage divider is equal to the slave
output’s feedback divider for coincidental tracking. See the
Applications Information section. (Recommended to use
test points to monitor signal pin connections.)
DRVCC (G7): Internal 5.3V regulator output used to source
the power MOSFET drivers, and supply power to the
INTVCC input. A 4.7µF ceramic capacitor is needed on
this pin to GND.
Rev. A
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LTM4662
PIN FUNCTIONS
(Recommended to Use Test Points to Monitor Signal Pin Connections.)
CPWR (F8): Input Power to the Control IC, and Power
to the DRVCC Regulator. This pin is connected to VIN for
normal 4.5V to 20V operation. For lower voltage inputs
below 4.5V, CPWR can be powered with an external 5V
bias. See Application section.
COMP1A, COMP2A (G3, E3): Current Control Threshold.
These pins are the output of the error amplifier and the
switching regulator’s compensation point. The current
comparator threshold increases with this control voltage.
The voltage ranges from 0V to 2.4V.
COMP1B, COMP2B (G1, E1): Internal Compensation
Network .These pins are to be connected to their respected
COMPA pins. When Utilizing specific external compensation, then float these pins.
MODE_PLLIN (F3): Operation Mode Selection or External
Clock Synchronization Input. When this pin is tied to INTVCC,
forced continuous mode operation is selected. Tying this pin
to SGND allows discontinuous mode operation. When an
external clock is applied at this pin, both channels operate
in forced continuous mode and synchronize to the external
clock. This pin has an internal 600k pull-down resistor to
SGND. An external clock applied to MODE_PLLIN should
be within ±30% of this programmed frequency to ensure
frequency lock.
CLKOUT (F4): Clock output with phase control using the
PHASMD pin to enable multiphase operation between devices.
Its output level swings between INTVCC and SGND. If clock
input is present at the MODE_PLLIN pin, it will be synchronized to the input clock, with phase set by the PHASMD pin. If
no clock is present at MODE_PLLIN, its frequency will be set
by the FREQ pin. To synchronize other controllers, it can be
connected to their MODE_PLLIN pins. See the Applications
Information section.
RUN1, RUN2 (H5, D5): Run Control Pins. A voltage above
1.3V will turn on each channel in the module. A voltage below
1.0V on the RUN pin will turn off the related channel. Each
RUN pin has a 1.2μA pull-up current, once the RUN pin
reaches 1.2V an additional 4.5μA pull-up current is added
to this pin. A 100k resistor to ground is internal, and can be
used with a pull-up resistor to VIN to turn on the module using
the external and internal resistor to program under voltage
lockout. Otherwise, an external enable signal or source can
drive these pins directly below the 6V max. Enabling either
RUN pin will turn on the DRVCC, and turn on the INTVCC path
for operation. See Figure 1 and Applications section.
PHASMD (H2): Connect this pin to SGND, INTVCC, or
floating this pin to select the phase of CLKOUT and channel 2. See Electrical Characteristics table and Application
section.
PGOOD1, PGOOD2 (G5, E5): Output Voltage Power Good
Indicator. Open-drain logic output that is pulled to ground
when the output voltage is not within ±7.5% of the regulation point. See Applications section.
INTVCC (F6): Supply Input for Internal Circuitry (Not
Including Gate Drivers). This bias is derived from DRVCC
internally.
EXTVCC (E7): External Power Input. When EXTVCC exceeds
the switchover voltage (typically 4.6V), an internal switch
connects this pin to DRVCC and shuts down the internal
regulator so that INTVCC and gate drivers draw power
from EXTVCC. The VIN pin still needs to be powered up
but draws minimum current.
TEMP1+,TEMP1– and TEMP2+, TEMP2– (L8, K8 and
B8, A8): Onboard temperature diode for monitoring each
channel with differential connections for noise immunity.
VIN1 (K4-K5, L4-L5) and VIN2 (A4-A5, B4-B5): Power
Input Pins. Apply input voltage between these pins and
GND pins. Recommend placing input decoupling capacitance directly between VIN pins and GND pins.
VOUTS1– (J3): Differential Output Sense Amplifier (–) Input
of channel 1. Connect this pin to the negative terminal of
the output load capacitor of VOUT1.
VOUTS2– (D4): Differential Output Sense Amplifier (–)
Input of channel 2. Connect this pin to the negative terminal of the output load capacitor of VOUT2.
SW1 (H8, J8) and SW2 (C8, D8): Switching node of each
channel that is used for testing purposes. Also an R-C
snubber network can be applied to reduce or eliminate
switch node ringing, or otherwise leave floating. See the
Applications Information section.
VRNG (D2): Current Limit Adjustment Range. Tying this
pin to INTVCC sets full 15A current, or tying to SGND will
lower the current limit to 7.5A. Default to INTVCC.
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Rev. A
9
LTM4662
BLOCK DIAGRAM
CPWR
EXTVCC
DRVCC
LDO
DRVCC
4.7µF
CPWR
VIN
DRVCC
1µF
2Ω
VIN
1µF
TOP G
INTVCC
COMP1B
RUN1 AND RUN2
SEPARATE:
RPULLUP =
(
INTVCC
–
gm +
+
RUN1
100k
VFB1
+
–
RUN2
)
VIN(MIN) • 100k
1.3
SGND
130k
– 50k
POWER
CONTROL
LOGIC
BLOCK
MODE_PLLIN
( )
PHASMD
tSOFT-START =
VOUT1
1µA
0.645V
VFB1
470pF
–
VIN
MTOP2
SW2
0.47µH
GATE
DRIVE
50k
VOUT2
CIN4
10µF
25V
VOUT2 1.2V/15A
+
VFB2
0.6V
COUT2
+
–
TRACK/SS2
–
0.645V
PGOOD2 VFB1
+
BLOCK
–
+ 0.555V
VOUTS2–
×2
+
–
gm +
+
R7
50k
–
SGND
PGOOD2
CIN3
10µF
25V
GND
INTERNAL
COMP
1µA
GND
1µF
MBOT2
COMP2B
SS
TEMP SENSOR
TEMP1–
C8
1µF
DRVCC
COMP2A
TEMP1+
PGOOD1
+ PGOOD1
BLOCK
–
+
0.555V
VIN
CSS
SGND
VOUTS1
NPN
CSS
• 0.6V
1µA
TRACK/SS1
CSS
60.4k
LOCATED NEAR POWER STAGES
FREQ
SGND
VFB1
49.9Ω
( )
RFB1
40.2k
×1
115k
VRNG
350kHz INTVCC
SGND
VOUTS1–
SS
CLKOUT
41550
RFREQ =
– 2.2
f(kHz)
0.6V
REF
SGND
100k
– 100k
COUT1
GND
+
1.3
)
1.5V/15A
+
1µF
MBOT1
–
VIN(MIN) • 50k
BOT G
VOUT1
INTERNAL
COMP
VIN
100µF
25V
SW1
0.47µH
GATE
DRIVE
COMP1A
(
GND
MTOP1
1µF
RUN1 AND RUN2
TIED TOGETHER:
RPULLUP =
VIN 4.5V TO 20V
CIN1
CIN2 +
10µF
10µF
25V
25V
0.6V REF
SGND
VFB2
0.3V
VOUT2
49.9Ω
SGND
60.4k
VOUTS2
LOCATED NEAR
POWER STAGES
NPN
RFB2 R
FB3
60.4k 30.1k
TEMP2+
470pF
TEMP2–
TEMP SENSOR
4662 F01
Figure 1. Simplified LTM4662 Block Diagram
10
Rev. A
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LTM4662
DECOUPLING REQUIREMENTS
TA = 25°C. Use Figure 1 configuration.
SYMBOL
PARAMETER
CONDITIONS
CIN1, CIN2
CIN3, CIN4
External Input Capacitor Requirement
(VIN = 4.5V to 20V, VOUT1 = 1.5V)
(VIN = 4.5V to 20V, VOUT2 = 1.5V)
MIN
IOUT1 = 15A
IOUT2 = 15A
COUT1
COUT2
External Output Capacitor Requirement
(VIN = 4.5V to 20V, VOUT1 = 1.5V)
(VIN = 4.5V to 20V, VOUT2 = 1.5V)
IOUT1 = 15A
IOUT2 = 15A (Note 8)
10μF ×2
10μF ×2 (Note 8)
TYP
MAX
UNITS
20
20
µF
µF
400
400
µF
µF
OPERATION
Power Module Description
The LTM4662 is a dual-output standalone non-isolated
switching mode DC/DC power supply. It can provide two
15A outputs with few external input and output capacitors
and setup components. This module provides precisely
regulated output voltages programmable via external
resistors from 0.6VDC to 5.5VDC over 4.5V to 20V input
voltages. The typical application schematic is shown in
Figure 20. See Note 8 in the Electrical Characteristics section for output current guideline.
The LTM4662 has dual integrated controlled-on time current mode regulators and built-in power MOSFET devices
with fast switching speed. The controlled on-time, valley
current mode control architecture, allows for not only
fast response to transients without clock delay, but also
constant frequency switching at steady load condition.
The typical switching frequency is 400kHz. For switchingnoise sensitive applications, it can be externally synchronized from 250kHz to 1000kHz. A resistor can be used to
program a free run frequency on the FREQ pin. See the
Applications Information section.
With current mode control and internal feedback loop
compensation, the LTM4662 module has sufficient stability margins and good transient performance with a wide
range of output capacitors, even with all ceramic output
capacitors. Optimized external compensation is supported
by disconnecting the internal compensation.
Current mode control provides cycle-by-cycle fast current
limit and foldback current limit in an overcurrent condition. Internal overvoltage and undervoltage comparators
pull the open-drain PGOOD outputs low if the output feedback voltage exits a ±7.5% window around the regulation
point. As the output voltage exceeds 7.5% above regulation, the bottom MOSFET will turn on to clamp the output
voltage. The top MOSFET will be turned off. This overvoltage protect is feedback voltage referred.
Pulling the RUN pins below 1.3V forces the regulators
into a shutdown state, by turning off both MOSFETs.
The TRACK/SS pins are used for programming the output voltage ramp and voltage tracking during start-up or
used for soft-starting the regulator. See the Applications
Information section. The LTM4662 is internally compensated to be stable over all operating conditions. Table 5
provides a guideline for input and output capacitances
for several operating conditions. The LTpowerCAD® will
be provided for transient and stability analysis. The VFB1
pin is used to program the channel 1 output voltage with
a single external resistor to ground, and VFB2 pin requires
two resistors to program the output. Both channel 1 and 2
have remote sense capability.
Multiphase operation can be easily employed with the
MODE_PLLIN, PHASMD, and CLKOUT pins. Up to 6
phases can be cascaded to run simultaneously with
respect to each other by programming the PHASMD pin to
different levels. See the Applications Information section.
High efficiency at light loads can be accomplished
with selectable pulse-skipping operation using the
MODE_PLLIN. These light load features will accommodate battery operation. Efficiency graphs are provided
for light load operation in the Typical Performance
Characteristics section. Each channel has temperature
diode included inside the module to monitor the temperature of the module. See the Applications Information
section for details.
Rev. A
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11
LTM4662
APPLICATIONS INFORMATION
The typical LTM4662 application circuit is shown in
Figure 20. External component selection is primarily
determined by the maximum load current and output
voltage. Refer to Table 5 for specific external capacitor
requirements for particular applications.
VIN to VOUT Step-Down Ratios
There are restrictions in the maximum VIN and VOUT stepdown ratio that can be achieved for a given input voltage.
Each output of the LTM4662 is capable of a wide duty
cycle that is limited by the minimum on-time tON(MIN) of
30ns defined as tON(MIN) < D/fSW for narrow duty cycle,
where D is duty cycle (VOUT/VIN) and fSW is the switching frequency. The minimum off-time of 90ns tOFF(MIN)
tON(MIN)
VIN(MAX)
= DMAX
DMAX = 1 – FREQ • tOFF(MIN)
Rev. A
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LTM4662
APPLICATIONS INFORMATION
Output Voltage Soft Starting and Tracking
Output voltage tracking can be programmed externally
using the TRACK/SS pins. The output can be tracked up
and down with another regulator. The master regulator’s
output is divided down with an external resistor divider
that is the same as the slave regulator’s feedback divider
for to implement coincident tracking. The LTM4662 uses
an accurate 60.4k resistor internally for the top feedback
resistor for each channel. Figure 5 shows an example of
coincident tracking.
⎛
60.4k ⎞⎟
SLAVE = ⎜⎜ 1+
⎟ • VTRACK
⎜
R TB ⎟⎠
⎝
MR
The TRACK/SS pins can be controlled by a capacitor
placed on the regulator TRACK/SS pin to ground. A 1.0μA
current source will charge the TRACK/SS pin up to the
voltage reference and then proceed up to INTVCC. After the
0.6V ramp, the TRACK/SS pin will no longer be in control,
and the internal voltage reference will control output regulation from the feedback divider. Foldback current limit is
disabled during this sequence of turn-on during tracking
or soft-starting. The TRACK/SS pins are pulled low when
the RUN pin is below 1.2V. The total soft-start time can
be calculated as:
⎛ C
⎞
tSOFT-START = ⎜⎜ SS ⎟⎟ • 0.6V
⎝ 1.0µA ⎠
Ratiometric tracking can be achieved by a few simple calculations and the slew rate value applied to
the master’s TRACK/SS pin. As mentioned above, the
TRACK/SS pin has a control range from 0 to 0.6V.
The master’s TRACK/SS pin slew rate is directly equal
SR
• 60.4k = R TA
where MR is the master’s output slew rate and SR is the
slave’s output slew rate in Volts/second. When coincident
tracking is desired, then MR and SR are equal, thus RTA is
equal the 60.4k. RTB is derived from equation:
R TB =
VTRACK is the track ramp applied to the slave’s track pin.
VTRACK has a control range of 0V to 0.6V, or the internal
reference voltage. When the master’s output is divided
down with the same resistor values used to set the slave’s
output, then the slave will coincident track with the master
until it reaches its final value. The master will continue to
its final value from the slave’s regulation point. Voltage
tracking is disabled when VTRACK/SS is more than 0.6V.
RTB in Figure 5 will be equal to the RFB for coincident tracking. Figure 6 shows the coincident tracking waveforms.
to the master’s output slew rate in Volts/second. The
equation:
0.6V
V
VFB
V
+ FB − TRACK
60.4k RFB
R TA
where VFB is the feedback voltage reference of the regulator, and VTRACK/SS is 0.6V. Since RTA is equal to the 60.4k
top feedback resistor of the slave regulator in equal slew
rate or coincident tracking, then RTB is equal to RFB with
VFB = VTRACK/SS. In ratiometric tracking, a different slew
rate maybe desired for the slave regulator. RTB can be
solved for when SR is slower than MR. Make sure that the
slave supply slew rate is chosen to be fast enough so that
the slave output voltage will reach its final value before the
master output For example, MR = 20V/s, and SR = 15V/s.
Then RTA = 80.6k. Solve for RTB to equal to 80.6k.
Each of the TRACK/SS pins will have a 1.0μA current
source on when a resistive divider is used to implement
tracking on that specific channel. This will impose an offset on the TRACK/SS pin input. Smaller values resistors
with the same ratios as the resistor value calculated from
the above equation can be used. For example, where the
60.4k is used then a 6.04k can be used to reduce the
TRACK/SS pin offset to a negligible value.
Power Good
Each PGOOD pin is connected to an internal open-drain
N-channel MOSFET. An external resistor or current source
can be used to pull this pin up to 6V (e.g., VOUT1,2 or
DRVCC). Overvoltage or undervoltage comparators (OV,
UV) turn on the MOSFET and pull the PGOOD pin low
when the feedback voltage is outside the ±7.5% window
of the reference voltage. The PGOOD pin is also pulled low
when the channel’s RUN pin is below the 1.2V threshold
Rev. A
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LTM4662
APPLICATIONS INFORMATION
+
4.5V TO 20V
10μF
25V
×4 INTV
100μF
25V
4.7μF
130k
CC
10k
115k
FREQ VIN1 VIN2 CPWR
RUN1
RUN1
PGOOD1
470μF
2.5V
POSCAP
EXTVCC PHASMD
RUN2
SW1
SW2
VOUT1
VOUT2
–
VOUTS2–
COMP1A
COMP2A
COMP1B
100pF
VOUT2
0.9V AT 15A
RFB
121k
46.2k
100µF
×4
+
470μF
2.5V
POSCAP
REMOTE
SENSED GND
COMP2B
TRACK/SS1
INTVCC
PGOOD2
VFB2
VRNG
VOUTS1
10k
VOUTS2
LTM4662
VFB1
60.4k INTV
CC
INTVCC
RUN1
PGOOD2
VOUTS1
100μF
×4
DRVCC INTVCC
PGOOD1
VOUT1
1.2V AT 15A
+
INTVCC
TRACK/SS2
MODE_PLLIN TEMP1+ TEMP1– SGND GND TEMP2+ TEMP2–
CLKOUT
RTA
60.4k
0.1μF
CHANNEL 1 TEMP MONITOR DIODE
VOUT1
RTB
121k
100pF
CHANNEL 2 TEMP MONITOR DIODE
4662 F05
RAMP TIME
tSOFTSTART = (CSS/1.0μA) • 0.6V
Figure 5. Example of Output Tracking Application Circuit
OUTPUT VOLTAGE
MASTER OUTPUT
SLAVE OUTPUT
TIME
4662 F06
Figure 6. Output Coincident Tracking Waveform
18
Rev. A
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LTM4662
APPLICATIONS INFORMATION
(hysteresis applies), or in undervoltage lockout (UVLO).
In an overvoltage (OV) condition, MT is turned off and MB
is turned on immediately without delay and held on until
the overvoltage condition clears. This happens regardless
of any other condition as long as the RUN pin is enabled.
For example, upon enabling the RUN1 pin, if VOUT is prebiased at more than 7.5% above the programmed regulated
voltage, the OV stays triggered and BG forced on until
VOUT is pulled a ~2.5% hysteresis below the 7.5% OV
threshold.
Stability Compensation
The module has already been internally compensated for
all output voltages. Table 5 is provided for most application requirements. LTpowerCAD will be provided for other
control loop optimization. Use LTpowerCAD when tying
output in parallel for higher current. External compensation may be necessary.
Run Enable
The RUN pins have an enable threshold of 1.3V maximum,
typically 1.2V with 160mV of hysteresis. They control the
turn on each of the channels and DRVCC and INTVCC. A
100k resistor to ground is internal, and can be used with
a pull-up resistor to VIN to turn on the module using the
external and internal resistor to program under voltage
lock out. Otherwise an external enable signal or source
can drive these pins directly below the 6V max. The RUN
pins can also be used for output voltage sequencing.
In parallel operation the RUN pins can be tie together
and controlled from a single control. See the Typical
Application circuits in Figure 23.
DRVCC, INTVCC, and EXTVCC
The LTM4662 module has an internal 5.3V low dropout
regulator (DRVCC) that is derived from the input voltage
through the CPWR (control power) pin. This regulator is
used to power the INTVCC control circuitry and the power
MOSFET drivers. This regulator can source up to 100mA,
and typically uses ~50mA for powering the device at the
maximum frequency. This internal 5.3V supply is enabled
by either RUN1 or RUN2.
EXTVCC allows an external 5V supply to power the
LTM4662 and reduce power dissipation from the internal
low dropout 5V regulator. The power loss savings can be
calculated by:
(CPWR – 5V) • 50mA = PLOSS
EXTVCC has a threshold of 4.7V for activation, and a maximum rating of 6V. When using a 5V input, connect this
5V input to EXTVCC also to maintain a 5V gate drive level.
EXTVCC must sequence on after CPWR, and EXTVCC must
sequence off before CPWR.
CPWR (Control Power)
The LTM4662 module has a CPWR pin that is biased with
a supply voltage minimum of 4.5V, and up to VIN maximum in normal operation. When operating at lower input
voltages below the 4.5V minimum, this pin can biased
with an alternate source to power the controller section
while operating down to the 2.375V minimum.
For example, if 3.3V is supplied to VIN, and a 5V bias with
a 50mA capability was used to source the CPWR pin, then
3.3V input power conversion can be implemented. Even
though the CPWR can operate from 4.5V to 20V, a lower
bias will lower the power loss if the module. See Figure 23
for an example.
Output Remote Sense
The LTM4662’s differential output sensing schemes are
distinct from conventional schemes where the regulated
output and its ground reference are directly sensed with
a difference amplifier whose output is then divided down
with an external resistor divider and fed into the error
amplifier input. This conventional scheme is limited by
the common mode input range of the difference amplifier
and typically limits differential sensing to the lower range
of output voltages.
The LTM4662 allows for seamless differential output
sensing by sensing the resistively divided feedback voltage differentially. This allows for differential sensing in the
full output range from 0.6V to 5.5V. Channel 1’s difference
amplifier (DIFFAMP) has a bandwidth of around 8MHz,
and channel 2’s feedback amplifier has a bandwidth of
around 4MHz, both high enough so as to not affect main
loop compensation and transient behavior.
Rev. A
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19
LTM4662
APPLICATIONS INFORMATION
The LTM4662 differential output sensing can correct for
up to ±300mV of common-mode deviation in the output’s
power and ground lines on channel 1, and ±200mV on
channel 2.
To avoid noise coupling into the feedback voltages, the
resistor dividers should be placed close to the VOUTS1 and
VOUTS1–, or VOUTS2 and VOUTS2– pins. Remote output and
ground traces should be routed together as a differential
pair to the remote output. For best accuracy, these traces
to the remote output and ground should be connected as
close as possible to the desired regulation point. Review
the parallel schematics in Figure 22.
place to start with. Modification to these components
should be made to attenuate the ringing with the least
amount of power loss.
Temperature Monitoring (TEMP1 and TEMP2)
A diode connected NPN transistor is used for temperature monitoring. Measuring the absolute temperature of a
diode is possible due to the relationship between current,
voltage and temperature described by the classic diode
equation:
⎛ V ⎞
ID = IS • e ⎜ D ⎟
⎝ η • VT ⎠
or
OUTPUT CURRENT RANGE PIN (VRNG)
Tying the VRNG pin to SGND will set the output current to
7.5A, and ~10A current limit. Tying the VRNG pin to INTVCC
will set the output current to 15A, and ~20A current limit.
SW Pins
The SW pins are generally for testing purposes by monitoring these pins. These pins can also be used to dampen
out switch node ringing caused by LC parasitic in the
switched current paths. Usually a series R-C combination
is used called a snubber circuit. The resistor will dampen
the resonance and the capacitor is chosen to only affect
the high frequency ringing.
If the stray inductance or capacitance can be measured
or approximated then a somewhat analytical technique
can be used to select the snubber values. The inductance
is usually easier to predict. It combines the power path
board inductance in combination with the MOSFET interconnect bond wire inductance. First the SW pin can be
monitored with a wide bandwidth scope with a high frequency scope probe. The ring frequency can be measured
for its value. The impedance Z can be calculated:
I
VD = η • VT • ln D
IS
where ID is the diode current, VD is the diode voltage, η
is the ideality factor (typically close to 1.0) and IS (saturation current) is a process dependent parameter. VT can
be broken out to:
VT =
k•T
q
where T is the diode junction temperature in Kelvin, q is
the electron charge and k is Boltzmann’s constant. VT is
approximately 26mV at room temperature (298K) and
scales linearly with Kelvin temperature. It is this linear
temperature relationship that makes diodes suitable temperature sensors. The IS term in the equation above is the
extrapolated current through a diode junction when the
diode has zero volts across the terminals. The IS term
varies from process to process, varies with temperature,
and by definition must always be less than ID. Combining
all of the constants into one term:
KD =
η•k
Z(L) = 2πfL
where f is the resonant frequency of the ring, and L is the
total parasitic inductance in the switch path. If a resistor
is selected that is equal to Z, then the ringing should be
dampened. The snubber capacitor value is chosen so that
its impedance is equal to the resistor at the ring frequency.
Calculated by: Z(C) = 1/(2πfC). These values are a good
where KD = 8.62 – 5, and knowing ln(ID/IS) is always
positive because ID is always greater than IS, leaves us
with the equation that:
20
q
I
VD = T(KELVIN) • K D • ln D
IS
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Rev. A
LTM4662
APPLICATIONS INFORMATION
where VD appears to increase with temperature. It is common knowledge that a silicon diode biased with a current
source has an approximate –2mV/°C temperature relationship (Figure 7), which is at odds with the equation
term, increases with temperature, reducing the ln(ID/IS)
absolute value yielding an approximate –2mV/°C composite diode voltage slope.
1.0
DIODE VOLTAGE (V)
ID = 100µA
ID = 10µA
0.8
∆VD
0.6
0.4
–173
–73
27
TEMPERATURE (°C)
127
4662 F07
Figure 7. Diode Voltage VD vs Temperature T(°C)
for Different Bias Currents
To obtain a linear voltage proportional to temperature,
we cancel the IS variable in the natural logarithm term to
remove the IS dependency from the following equation.
This is accomplished by measuring the diode voltage at
two currents I1, and I2, where I1 = 10 • I2.
Subtracting we get:
I2
I
ΔVD = T(KELVIN) • K D • In 1 − T(KELVIN) • K D • In
IS
IS
Combining like terms, then simplifying the natural log
terms yields:
∆VD = T(KELVIN) • KD • In(10)
and redefining constant
K’D = KD • In(10) = 198µV/k
yields
∆VD = K’D • T(KELVIN)
Solving for temperature:
T(KELVIN) =
ΔVD
K'D
,
T(KELVIN) = [°C]+ 273.15,
[°C] = T(KELVIN) − 273.15
means that if we take the difference in voltage across the
diode measured at two currents with a ratio of 10, the
resulting voltage is 198μV per Kelvin of the junction with
a zero intercept at 0 Kelvin. The diode connected NPN
transistor at the TEMP+, TEMP–pins can be used to monitor the internal temperature of the LTM4662. A general
temperature monitor can be implemented by connecting
a resistor between TEMP+ and VIN to set the current to
100μA, grounding the TEMP– pin and then monitoring
the diode voltage drop with temperature. A more accurate
temperature monitor can be achieved with a circuit injecting two currents that are at a 10:1 ratio. See LTC2997
data sheet.
Thermal Considerations and Output Current Derating
The thermal resistances reported in the Pin Configuration
section of the data sheet are consistent with those parameters defined by JESD51-12 and are intended for use with
finite element analysis (FEA) software modeling tools that
leverage the outcome of thermal modeling, simulation,
and correlation to hardware evaluation performed on a
μModule® package mounted to a hardware test board.
The motivation for providing these thermal coefficients
is found in JESD51-12 (“Guidelines for Reporting and
Using Electronic Package Thermal Information”). Many
designers may opt to use laboratory equipment and a test
vehicle such as the demo board to anticipate the μModule
regulator’s thermal performance in their application at
various electrical and environmental operating conditions
to compliment any FEA activities. Without FEA software,
the thermal resistances reported in the Pin Configuration
section are in-and-of themselves not relevant to providing guidance of thermal performance; instead, the derating curves provided in the data sheet can be used in a
manner that yields insight and guidance pertaining to
one’s application-usage, and can be adapted to correlate thermal performance to one’s own application. The
Rev. A
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21
LTM4662
APPLICATIONS INFORMATION
Pin Configuration section gives four thermal coefficients
explicitly defined in JESD51-12; these coefficients are
quoted or paraphrased below:
1. θJA, the thermal resistance from junction to ambient,
is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed
enclosure. This environment is sometimes referred to
as “still air” although natural convection causes the
air to move. This value is determined with the part
mounted to a 95mm × 76mm PCB with four layers.
2. θJCbottom, the thermal resistance from junction to the
bottom of the product case, is determined with all
of the component power dissipation flowing through
the bottom of the package. In the typical μModule,
the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient environment. As a result, this thermal resistance
value may be useful for comparing packages but
the test conditions don’t generally match the user’s
application.
3. θJCtop, the thermal resistance from junction to top of
the product case, is determined with nearly all of the
component power dissipation flowing through the top
of the package. As the electrical connections of the
typical μModule are on the bottom of the package, it
is rare for an application to operate such that most of
the heat flows from the junction to the top of the part.
As in the case of θJCbottom, this value may be useful
for comparing packages but the test conditions don’t
generally match the user’s application.
4. θJB, the thermal resistance from junction to the
printed circuit board, is the junction-to-board thermal
resistance where almost all of the heat flows through
the bottom of the μModule and into the board, and
is really the sum of the θJCbottom and the thermal
resistance of the bottom of the part through the solder
joints and through a portion of the board. The board
temperature is measured a specified distance from
the package.
A graphical representation of the aforementioned thermal resistances is given in Figure 8; blue resistances are
contained within the μModule regulator, whereas green
resistances are external to the μModule package.
As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD51-12 or provided in the Pin
Configuration section replicates or conveys normal operating conditions of a μModule regulator. For example, in
normal board-mounted applications, never does 100%
of the device’s total power loss (heat) thermally conduct
exclusively through the top or exclusively through bottom of the μModule package—as the standard defines
for θJCtop and θJCbottom, respectively. In practice, power
loss is thermally dissipated in both directions away from
the package—granted, in the absence of a heat sink and
airflow, a majority of the heat flow is into the board.
JUNCTION-TO-AMBIENT THERMAL RESISTANCE COMPONENTS
JUNCTION-TO-CASE (TOP)
RESISTANCE
JUNCTION
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION-TO-CASE
CASE (BOTTOM)-TO-BOARD
(BOTTOM) RESISTANCE
RESISTANCE
AMBIENT
BOARD-TO-AMBIENT
RESISTANCE
4662 F08
µMODULE DEVICE
Figure 8. Graphical Representation of JESD51-12 Thermal Coefficients
22
Rev. A
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LTM4662
APPLICATIONS INFORMATION
Within the LTM4662, be aware there are multiple power
devices and components dissipating power, with a consequence that the thermal resistances relative to different junctions of components or die are not exactly linear
with respect to total package power loss. To reconcile this
complication without sacrificing modeling simplicity—
but also, not ignoring practical realities—an approach
has been taken using FEA software modeling along with
laboratory testing in a controlled-environment chamber
to reasonably define and correlate the thermal resistance
values supplied in this data sheet: (1) Initially, FEA software is used to accurately build the mechanical geometry
of the LTM4662 and the specified PCB with all of the correct material coefficients along with accurate power loss
source definitions; (2) this model simulates a softwaredefined JEDEC environment consistent with JESD51-12
to predict power loss heat flow and temperature readings
at different interfaces that enable the calculation of the
JEDEC-defined thermal resistance values; (3) the model
and FEA software is used to evaluate the LTM4662 with
heat sink and airflow; (4) having solved for and analyzed
these thermal resistance values and simulated various
operating conditions in the software model, a thorough
laboratory evaluation replicates the simulated conditions
with thermocouples within a controlled-environment
chamber while operating the device at the same power
loss as that which was simulated. The outcome of this
Figure 9. LTM4662 12V to 1V at 30A with
400LFM, 30°C Ambient, 30W
process and due diligence yields a set of derating curves
provided in other sections of this data sheet. After these
laboratory tests have been performed, then the θJB and
θBA are summed together to correlate quite well with the
LTM4662 model with no airflow or heat sinking in a define
chamber. This θJB + θBA value should accurately equal
the θJA value because approximately 100% of power loss
flows from the junction through the board into ambient
with no airflow or top mounted heat sink. Each system has
its own thermal characteristics, therefore thermal analysis
must be performed by the user in a particular system. The
LTM4662 has been designed to effectively remove heat
from both the top and bottom of the package. The bottom substrate material has very low thermal resistance
to the printed circuit board. An external heat sink can be
applied to the top of the device for excellent heat sinking
with airflow . Basically all power dissipating devices are
mounted directly to the substrate and the top exposed
metal. This provides two low thermal resistance paths to
remove heat.
Figure 9 shows a temperature plot of the LTM4662 with
400LFM airflow. Figure 10 shows a temperature plot of
the LTM4662 with 400LFM airflow. These plots equate to
a paralleled 1V at 30A and 5V at 22A design operating at
87% and 95% efficiency.
Figure 10. LTM4662 12V to 5V at 22A with
400LFM, 30°C Ambient, 110W
Rev. A
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23
LTM4662
APPLICATIONS INFORMATION
Power Derating
The 5V, 8V and 12V power loss curves in Figures 11
through 13 can be used in coordination with the load
current derating curves in Figures 14 to 18 for calculating
an approximate θJA thermal resistance for the LTM4662
with airflow conditions. The power loss curves are taken
at room temperature, and are increased with a 1.35 to 1.4
multiplicative factor at 125°C. These factors come from
the fact that the power loss of the regulator increases
about 45% from 25°C to 150°C, thus a 50% spread
over 125°C delta equates to ~0.35%/°C loss increase. A
125°C maximum junction minus 25°C room temperature
equates to a 100°C increase. This 100°C increase multiplied by 0.35%/°C equals a 35% power loss increase at
the 125°C junction, thus the 1.35 multiplier.
The derating curves are plotted with VOUT1 and VOUT2 in
parallel single output operation starting at 30A of load
with low ambient temperature. The output voltages are
1V, 2.5V and 5V. These are chosen to include the lower
and higher output voltage ranges for correlating the thermal resistance. Thermal models are derived from several
temperature measurements in a controlled temperature
chamber along with thermal modeling analysis.
The junction temperatures are monitored while ambient
temperature is increased with and without airflow. The
power loss increase with ambient temperature change
is factored into the derating curves. The junctions are
maintained at ~120°C maximum while lowering output
current or power while increasing ambient temperature.
The decreased output current will decrease the internal
module loss as ambient temperature is increased.
The monitored junction temperature of 120°C minus the
ambient operating temperature specifies how much temperature rise can be allowed. As an example in Figure 14,
the load current is derated to ~22.5A at ~80°C with no
air or heat sink and the power loss for the 12V to 1.0V
at 22.5A output is a ~4.05W loss. The 4.05W loss is
calculated with the ~3.0W room temperature loss from
the 12V to 1.0V power loss curve at 22.5A, and the 1.35
multiplying factor at 125°C ambient. If the 80°C ambient temperature is subtracted from the 125°C junction
24
temperature, then the difference of 45°C divided by 4.05W
equals a 11°C/W θJA thermal resistance. Table 2 specifies a 11°C/W value which is pretty close. The airflow
graphs are more accurate due to the fact that the ambient
temperature environment is controlled better with airflow.
As an example in Figure 15, the load current is derated
to ~24A at ~88°C with 200LFM of airflow and the power
loss for the 12V to 1.0V at 24A output is a ~4.35W loss.
The 4.35W loss is calculated with the ~3.2W room temperature loss from the 12V to 1.0V power loss curve at
24A, and the 1.35 multiplying factor at 125°C ambient.
If the 88°C ambient temperature is subtracted from the
125°C junction temperature, then the difference of 37°C
divided by 4.35W equals a 8.5°C/W θJA thermal resistance. Table 2 specifies a 8.5°C/W value which is pretty
close. Table 2 through Table 4 provide equivalent thermal
resistances for 2.5V and 5V outputs with and without
airflow and heat sinking.
The derived thermal resistances in Table 2 through Table 4
for the various conditions can be multiplied by the calculated power loss as a function of ambient temperature to
derive temperature rise above ambient, thus maximum
junction temperature. Room temperature power loss can
be derived from the power loss curves and adjusted with
the above ambient temperature multiplicative factors. The
printed circuit board is a 1.6mm thick four layer board
with two ounce copper for the two outer layers and one
ounce copper for the two inner layers.
Safety Considerations
The LTM4662 modules do not provide isolation from VIN
to VOUT. There is no internal fuse. If required, a slow blow
fuse with a rating twice the maximum input current needs
to be provided to protect each unit from catastrophic failure. The fuse or circuit breaker should be selected to limit
the current to the regulator during overvoltage in case of
an internal top MOSFET fault. If the internal top MOSFET
fails, then turning it off will not resolve the overvoltage,
thus the internal bottom MOSFET will turn on indefinitely
trying to protect the load. Under this fault condition, the
input voltage will source very large currents to ground
through the failed internal top MOSFET and enabled
Rev. A
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LTM4662
APPLICATIONS INFORMATION
Table 2. 1.0V Output
DERATING CURVE
Figures 14, 15
Figures 14, 15
Figures 14, 15
VIN (V)
5, 12
5, 12
5, 12
POWER LOSS CURVE
Figure 11, 13
Figure 11, 13
Figure 11, 13
AIRFLOW (LFM)
0
200
400
BGA
θJA (°C/W)
11
8.5
8
HEAT SINK
None
None
None
Table 3. 2.5V Output
DERATING CURVE
Figures 16, 17
Figures 16, 17
Figures 16, 17
VIN (V)
5, 12
5, 12
5, 12
POWER LOSS CURVE
Figure 11, 13
Figure 11, 13
Figure 11, 13
AIRFLOW (LFM)
0
200
400
LGA
θJA (°C/W)
6.5 to 7
5.5 to 6
4.5
HEAT SINK
None
None
None
BGA
θJA (°C/W)
11
8,5
8
Table 4. 5V Output
DERATING CURVE
Figures 18
Figures 18
Figures 18
VIN (V)
12
12
12
POWER LOSS CURVE
Figure 13
Figure 13
Figure 13
AIRFLOW (LFM)
0
200
400
HEAT SINK MANUFACTURER
PART NUMBER
WEBSITE
Aavid Thermalloy
375424B00034G
www.aavid.com
Cool Innovations
4-050503P to 4-050508P
www.coolinnovations.com
BGA
θJA (°C/W)
11
8,5
8
HEAT SINK
None
None
None
Table 5. Capacitor Matrix (All Parameters Are Typical and Dependent on Board Layout)
VENDORS
VALUE
PART NUMBER
VENDORS
VALUE
PART NUMBER
Taiyo Yuden
22μF, 25V
C3216X7S0J226M
Panasonic SP
470μF, 2.5V
EEFGX0E471R
Murata
22μF, 25V
GRM31CR61C226KE15L
Panasonic POSCAP
470μF, 2.5V
2R5TPD470M5
Murata
100μF, 6.3V
GRM32ER60J107M
Panasonic POSCAP
470μF, 6.3V
6TPD470M
AVX
100μF, 6.3V
18126D107MAT
Panasonic
100μF, 20V
20SEP100M
VOUT
CIN
COUT1
COUT2
CFF
CIN
(V) (CERAMIC) (BULK)** (CERAMIC) (CERAMIC/BULK) (pF)
0.9
22μF ×4
100μF
100μF ×4
470μF ×2
CCOMP
(pF)
VIN
(V)
100
5,12
DROOP P-P DEVIATION RECOVERY TIME LOAD STEP FREQ
(mV)
(mV)
(µs)
(A/µs)
(kHz)
39
78
30
7.5
350
1
22μF ×4
100μF
100μF ×4
470μF ×2
100
5,12
39
78
30
7.5
350
1.2
22μF ×4
100μF
100μF ×4
470μF ×2
100
5,12
44
88
30
7.5
350
1.5
22μF ×4
100μF
100μF ×3
None
100
5,12
65
130
25
7.5
450
47
1.8
22μF ×4
100μF
100μF ×3
None
47
100
5,12
65
130
25
7.5
500
2.5
22μF ×4
100μF
100μF ×2
None
47
100
5,12
80
160
25
7.5
650
3.3
22μF ×4
100μF
100μF ×1
None
47
100
5,12
100
200
20
5
750
5
22μF ×4
100μF
100μF ×1
None
47
100
5,12
100
280
20
5
950
**Bulk capacitance is optional if VIN has very low input impedance.
Rev. A
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25
LTM4662
APPLICATIONS INFORMATION
5
4
3
7
8V–0.9V, 350kHz
8V–1.0V, 350kHz
8V–1.2V, 350kHz
8V–1.5V, 450kHz
8V–1.8V, 500kHz
8V–2.5V, 600kHz
8V–3.3V, 750kHz
8V–5.0V, 950kHz
6
POWER LOSS (W)
6
POWER LOSS (W)
7
5V–0.9V, 350kHz
5V–1.0V, 350kHz
5V–1.2V, 350kHz
5V–1.5V, 350kHz
5V–1.8V, 450kHz
5V–2.5V, 450kHz
5V–3.3V, 450kHz
5
4
3
4
3
2
2
1
1
1
0
5
10
15
20
LOAD CURRENT (mA)
25
0
30
0
5
10
15
20
LOAD CURRENT (mA)
25
4662 F11
0
30
0
Figure 12. 8VIN Power Loss Curve
30
30
25
25
25
20
20
20
10
IOUT (A)
30
IOUT (A)
35
15
15
10
0LFM
200LFM
400LFM
0
20
40
80
100
0
120
20
40
60
TA (°C)
80
100
35
30
30
25
25
20
20
10
0
20
40
60
TA (°C)
80
100
120
4662 F16
Figure 16. 5V to 2.5V Derating
Curve, No Heat Sink
15
10
0LFM
200LFM
400LFM
5
0
20
40
0LFM
200LFM
400LFM
5
60
TA (°C)
80
100
120
0
0
4662 F17
Figure 17. 12V to 2.5V Derating
Curve, No Heat Sink
26
0
120
Figure 15. 12V to 1V Derating
Curve, No Heat Sink
15
0LFM
200LFM
400LFM
4662 F15
35
0
15
5
IOUT (A)
IOUT (A)
0
4662 F14
Figure 14. 5V to 1V Derating
Curve, No Heat Sink
30
10
0LFM
200LFM
400LFM
5
60
TA (°C)
25
Figure 13. 12VIN Power Loss Curve
35
0
10
15
20
LOAD CURRENT (mA)
4662 F13
35
5
5
4662 F12
Figure 11. 5VIN Power Loss Curve
IOUT (A)
5
2
0
12V–0.9V, 300kHz
12V–1.0V, 300kHz
12V–1.2V, 350kHz
12V–1.5V, 450kHz
12V–1.8V, 500kHz
12V–2.5V, 650kHz
12V–3.3V, 800kHz
12V–5.0V, 950kHz
6
POWER LOSS (W)
7
20
40
60
TA (°C)
80
100
120
4662 F18
Figure 18. 12V to 5V Derating
Curve, No Heat Sink
Rev. A
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LTM4662
APPLICATIONS INFORMATION
internal bottom MOSFET. This can cause excessive heat
and board damage depending on how much power the
input voltage can deliver to this system. A fuse or circuit
breaker can be used as a secondary fault protector in this
situation.
• Place high frequency ceramic input and output capacitors next to the VIN, PGND and VOUT pins to minimize
high frequency noise.
The device does support over current protection.
Temperature diodes are provided for monitoring internal temperature, and can be used to detect the need for
thermal shutdown that can be done by controlling the
RUN pin.
• To minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers.
Layout Checklist/Example
The high integration of LTM4662 makes the PCB board
layout very simple and easy. However, to optimize its
electrical and thermal performance, some layout considerations are still necessary.
• Use large PCB copper areas for high current paths,
including VIN, GND, VOUT1 and VOUT2. It helps to minimize the PCB conduction loss and thermal stress.
• Place a dedicated power ground layer underneath the
unit.
• Do not put vias directly on the pads, unless they are
capped or plated over.
Use a separated SGND ground copper area for components connected to signal pins. Connect the SGND to GND
underneath the unit.
• For parallel modules, tie the VOUT, VFB, and COMP
pins together. Use an internal layer to closely connect
these pins together. The TRACK/SS pin can be tied a
common capacitor for regulator soft-start.
• Bring out test points on the signal pins for monitoring.
Figures 19a and 19b give a good example of the recommended layout.
GND
GND
VIN2
VIN2
VIN2
VIN2
GND
GND
GND
GND
VOUT2
GND
VOUT1
VOUT2
GND
VOUT1
4662 F19a
(a)
TOP LAYER
15mm x 11.25mm x 5.74mm
4662 F19b
(b)
BOTTOM LAYER
15mm x 11.25mm x 5.74mm
Figure 19. Recommended PCB Layout
Rev. A
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27
LTM4662
TYPICAL APPLICATIONS
4.5V TO 20V
+
100μF
25V
10μF
25V
INTVCC
×4
10k
4.7μF
130k
FREQ VIN1 VIN2 CPWR
RUN1
RUN1
PGOOD1
EXTVCC
PHASMD
RUN2
100μF
×4
SW2
VOUT1
VOUT2
VRNG
VOUTS1–
VOUTS2–
COMP1A
COMP2A
PGOOD2
VOUT2
1.5V
AT 15A
RFB
40.2k
24.3k
REMOTE
SENSED
GND
TRACK/SS2
MODE/PLLIN TEMP1+ TEMP1– SGND GND TEMP2+ TEMP2–
CLKOUT
0.1μF
0.1μF
CHANNEL 1 TEMP MONITOR DIODE
100µF
×3
COMP2B
TRACK/SS1
INTVCC
10k
VFB2
COMP1B
100pF
CCOMP
RUN1
VOUTS2
LTM4662
VFB1
90.9k INTV
CC
INTVCC
PGOOD2
SW1
VOUTS1
470μF
2.5V
POSCAP
DRVCC INTVCC
PGOOD1
VOUT1
1V AT 15A
+
INTVCC
115k
100pF
CCOMP
CHANNEL 2 TEMP MONITOR DIODE
4662 F20
Figure 20. 4.5V to 20V Input to 1.0V and 1.5V at 15A Each
28
Rev. A
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LTM4662
TYPICAL APPLICATIONS
4.5V TO 14V
+
100μF
25V
10μF
25V
×4
4.7μF
130k
INTVCC
115k
FREQ VIN1 VIN2 CPWR
RUN1
RUN1
DRVCC INTVCC
EXTVCC
PHASMD
RUN2
PGOOD1
100μF
×3
SW1
SW2
VOUT1
VOUT2
PGOOD2
VOUT
0.75V
AT 30A
VOUTS2
VFB2
LTM4662
VFB1
240k
VRNG
VOUTS1–
VOUTS2–
COMP1A
COMP2A
COMP1B
100µF
×3
48.1k
+
REMOTE
SENSED
GND
COMP
470μF
2.5V
POSCAP
×2
COMP2B
TRACK/SS1
INTVCC
10k
PGOOD2
VOUTS1
INTVCC
INTVCC
RUN1
TRACK/SS2
MODE_PLLIN TEMP1+ TEMP1– SGND GND TEMP2+ TEMP2–
100pF
CLKOUT
0.1μF
CHANNEL 1 TEMP MONITOR DIODE
CHANNEL 2 TEMP MONITOR DIODE
7.15k
1500pF
CCOMP
4662 F21
Figure 21. 12V Input to 0.75V at 30A Two Phase
Rev. A
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29
LTM4662
TYPICAL APPLICATIONS
4.5V TO 16V
+
100μF
25V
10μF
25V
×3
4.7μF
64.9k
INTVCC_U1
115k
FREQ VIN1 VIN2 CPWR
RUN1
RUN
DRVCC INTVCC
EXTVCC
PHASMD
RUN2
PGOOD2
PGOOD1
SW2
VOUT2
SW1
VOUT1
VFB
VFB2
LTM4662, U1
VFB1
INTVCC
(U1)
1V AT 60A
VOUTS2
VOUTS1
100μF
×4
RUN
PGOOD
45.3k
VRNG
VOUTS1–
VOUTS2–
COMP1A
COMP2A
COMP1B
COMP2B
TRACK/SS1
INTVCC
(U1)
TRACK/SS2
MODE_PLLIN TEMP1+ TEMP1– SGND GND TEMP2+ TEMP2–
VOUTS2–
COMP
REMOTE
SENSED
GND
TRACK
CLKOUT
0.1μF
CLK
CHANNEL 1 TEMP MONITOR DIODE
100µF
×4
18.2k
100pF
CHANNEL 2 TEMP MONITOR DIODE
4.5V TO 16V
10μF
25V
×3
4.7μF
INTVCC_U2
INTVCC_U2
115k
RUN
FREQ VIN1 VIN2 CPWR
RUN1
DRVCC INTVCC
EXTVCC
PHASMD
RUN2
PGOOD1
100μF
×4
SW1
SW2
VOUT1
VOUT2
VOUTS1
INTVCC
(U2)
VFB1
PGOOD
100µF
×4
VOUTS2
LTM4662, U2
VFB2
VRNG
–
VOUTS1–
VOUTS2
COMP1A
COMP2A
COMP1B
VFB
+
470μF ×2
2.5V
POSCAP
VOUTS2–
COMP
COMP2B
TRACK/SS1
CLK
RUN
PGOOD2
TRACK/SS2
MODE_PLLIN TEMP1+ TEMP1– SGND GND TEMP2+ TEMP2–
TRACK
CLKOUT
4662 F22
CHANNEL 1 TEMP MONITOR DIODE
100pF
CHANNEL 2 TEMP MONITOR DIODE
Figure 22. Four Phase Design 1V at 60A
30
Rev. A
For more information www.analog.com
LTM4662
TYPICAL APPLICATIONS
VIN
220μF
6.3V
115k
3.3V
3.3V
49.9k
10k
PGOOD1
4.7μF
INTVCC
3.3V
FREQ VIN1 VIN2 CPWR
RUN1
DRVCC INTVCC
PGOOD1
EXTVCC PHASMD
RUN2
PGOOD2
SW1
VOUT1
2.5V
AT 15A
47pF
INTVCC
30.1k
VRNG
VOUTS1–
VOUTS2–
COMP1A
COMP2A
0.1μF
20k
100µF
×3
REMOTE
SENSED
GND
COMP2B
TRACK/SS1
INTVCC
VOUT2
1.8V
AT 15A
47pF
VFB2
LTM4662
COMP1B
100pF
PGOOD2
VOUTS2
VOUTS1
VFB1
19.1k
10k
VOUT2
VOUT1
100μF
×2
PGOOD1
SW2
TRACK/SS2
MODE_PLLIN TEMP1+ TEMP1– SGND GND TEMP2+ TEMP2–
CHANNEL 1 TEMP MONITOR DIODE
CLKOUT
100pF
0.1μF
CHANNEL 2 TEMP MONITOR DIODE
4662 F23
Figure 23. 3.3V to 1.8V, and 2.5V at 15A each with PGOOD Power Up Sequencing
100
95
EFFICIENCY (%)
+
5V BIAS AT 50mA
3.3V
22μF
6.3V
×4
90
85
80
75
70
3.3V TO 2.5V, 300kHz
3.3V TO 1.8V, 300kHz
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
LOAD CURRENT (A)
4662 F24
Figure 24. Efficiency, 3.3VIN
Rev. A
For more information www.analog.com
31
LTM4662
TYPICAL APPLICATIONS
VIN2
+
56μF
16V
5V
22μF
6.3V
×2
VIN1
+
56μF
16V
5V BIAS AT 50mA
12V
22μF
16V
×2 INTVCC
4.1μF
130k
INTVCC
115k
FREQ VIN1 VIN2 CPWR
RUN1
R4
10k
DRVCC INTVCC
EXTVCC
PGOOD1
100μF
×2
VFB2
LTM4662
30.1k
VRNG
VOUTS1–
VOUTS2–
COMP1A
COMP2A
TRACK/SS1
100pF
20k
VOUT2
1.8V
AT 15A
100µF
×3
REMOTE
SENSED
GND
COMP2B
COMP1B
INTVCC
47pF
VOUTS2
VOUTS1
VFB1
13.3k INTV
CC
PGOOD2
VOUT2
VOUT1
47pF
10k
SW2
SW1
VOUT1
3.3V
AT 15A
INTVCC
PHASMD
RUN2
PGOOD2
TRACK/SS2
MODE_PLLIN TEMP1+ TEMP1– SGND GND TEMP2+ TEMP2–
CLKOUT
0.1μF
CHANNEL 1 TEMP MONITOR DIODE
100pF
0.1μF
CHANNEL 2 TEMP MONITOR DIODE
4662 F25
Figure 25. 12V to 3.3V at 15A, 5V to 1.8V at 15A
32
Rev. A
For more information www.analog.com
LTM4662
PACKAGE DESCRIPTION
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
LTM4662 Component BGA Pinout
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
A1
VOUT2
B1
VOUT2
C1
VOUT2
D1
VOUT2
E1
COMP2B
F1
FREQ
A2
VOUT2
B2
VOUT2
C2
VOUT2
D2
VRNG
E2
VOUTS2
F2
TRACK/SS2
A3
GND
B3
GND
C3
GND
D3
SGND
E3
COMP2A
F3
MODE_PLLIN
A4
VIN2
B4
VIN2
C4
GND
D4
VOUTS2–
E4
VFB2
F4
CLKOUT
A5
VIN2
B5
VIN2
C5
GND
D5
RUN2
E5
PGOOD2
F5
GND
A6
GND
B6
GND
C6
GND
D6
GND
E6
GND
F6
INTVCC
A7
GND
B7
GND
C7
GND
D7
GND
E7
EXTVCC
F7
GND
A8
TEMP2–
B8
TEMP2+
C8
SW2
D8
SW2
E8
GND
F8
CPWR
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
G1
COMP1B
H1
VOUT1
J1
VOUT1
K1
VOUT1
L1
VOUT1
G2
VOUTS1
H2
PHASMD
J2
VOUT1
K2
VOUT1
L2
VOUT1
K3
GND
L3
GND
G3
COMP1A
H3
SGND
J3
–
VOUTS1
G4
VFB1
H4
TRACK/SS1
J4
GND
K4
VIN1
L4
VIN1
G5
PGOOD1
H5
RUN1
J5
GND
K5
VIN1
L5
VIN1
G6
GND
H6
GND
J6
GND
K6
GND
L6
GND
G7
DRVCC
H7
GND
J7
GND
K7
GND
L7
GND
K8
TEMP1–
L8
TEMP1+
G8
GND
H8
SW1
J8
SW1
Rev. A
For more information www.analog.com
33
For more information www.analog.com
aaa Z
0.630 ±0.025 Ø 88x
4
4.445
0.000
1.905
SUGGESTED PCB LAYOUT
TOP VIEW
0.635
PACKAGE TOP VIEW
E
(6.4)
0.635
(2.7)
1.905
(2.7)
(0.6)
(5.7)
(5.7)
(0.6)
3.175
PIN “A1”
CORNER
4.445
X
6.350
5.080
3.810
2.540
1.270
0.000
1.270
2.540
3.810
5.080
6.350
Y
D
aaa Z
SYMBOL
A
A1
A2
b
b1
D
E
e
F
G
H1
H2
H3
aaa
bbb
ccc
ddd
eee
DETAIL B
H2
b1
NOM
5.74
0.60
2.32
0.75
0.63
15.00
11.25
1.27
12.70
8.89
0.32
2.00
2.82
0.36
2.05
3.15
0.15
0.10
0.20
0.30
0.15
MAX
6.26
0.70
2.41
0.90
0.66
A2
SUBSTRATE THK
MOLD CAP HT
INDUCTOR HT
BALL DIMENSION
PAD DIMENSION
BALL HT
NOTES
DETAIL B
PACKAGE SIDE VIEW
EPOXY/SOLDER
TOTAL NUMBER OF BALLS: 88
0.28
1.95
2.70
MIN
5.43
0.50
2.23
0.60
0.60
H1
SUBSTRATE
DIMENSIONS
ddd M Z X Y
eee M Z
DETAIL A
Øb (88 PLACES)
H3
MOLD
CAP
ccc Z
A1
A
(Reference LTC DWG # 05-08-1526 Rev C)
// bbb Z
34
Z
BGA Package
88-Lead (15mm × 11.25mm × 5.74mm)
e
b
7
5
G
4
3
e
PACKAGE BOTTOM VIEW
6
2
1
L
K
J
H
G
F
E
D
C
B
A
DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
BALL DESIGNATION PER JESD MS-028 AND JEP95
TRAY PIN 1
BEVEL
COMPONENT
PIN “A1”
6
!
PACKAGE IN TRAY LOADING ORIENTATION
LTMXXXXXX
µModule
BGA 88 0517 REV C
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
5. PRIMARY DATUM -Z- IS SEATING PLANE
4
3
6
SEE NOTES
PIN 1
2. ALL DIMENSIONS ARE IN MILLIMETERS. DRAWING NOT TO SCALE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
3
SEE NOTES
F
b
8
DETAIL A
LTM4662
PACKAGE DESCRIPTION
Rev. A
Z
3.175
LTM4662
REVISION HISTORY
REV
DATE
DESCRIPTION
A
09/18
Changed Absolute Maximum voltage of VFBI from “–0.3V to 2.7V” to “–0.3V to (INTVCC to 0.3V).”
PAGE NUMBER
2
Changed RFBHI1, RFBHI2 from 60.5 (min) and 60.75 (max) to 59.9 (min) and 60.9 (max).
4
Corrected run enable hysteresis from 100mV to 160mV
19
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
more by
information
www.analog.com
35
LTM4662
PACKAGE PHOTO
BGA
DESIGN RESOURCES
SUBJECT
DESCRIPTION
µModule Design and Manufacturing Resources
Design:
• Selector Guides
• Demo Boards and Gerber Files
• Free Simulation Tools
µModule Regulator Products Search
1. Sort table of products by parameters and download the result as a spread sheet.
Manufacturing:
• Quick Start Guide
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability
2. Search using the Quick Power Search parametric table.
Digital Power System Management
Analog Devices’ family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTM4646
Pin-Compatible, Lower Current version
of the LTM4662
Dual 10A, Single 20A Step-Down µModule Regulator 4.5V ≤ VIN ≤ 20V, 0.6V ≤ VOUT
≤ 5.5V. 11.25mm × 15mm × 5.01mm BGA
LTM4628
Dual 8A or Single 16A Step-Down
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4.5V ≤ VIN ≤ 26.5V, 0.6V ≤ VOUT ≤ 5.5V. 15mm × 15mm × 4.32mm LGA 15mm ×
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LTM4620A
Dual 13A or Single 26A Step-Down
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15mm × 5.01mm BGA
LTM4630A
Dual 18A or Single 36A Step-Down
µModule Regulator
4.5V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 5.3V. 16mm × 16mm × 4.41mm LGA, 16mm ×
16mm × 5.01mm BGA
LTM4644
Quad 4A Step-Down µModule Regulator
4.5V ≤ VIN ≤ 14V, 0.6V ≤ VOUT ≤ 5.5V. 9mm × 15mm × 5.01mm BGA
LTM4637
Single 20A Step-Down µModule Regulator
4.5V ≤ VIN ≤ 20V, 0.6V ≤ VOUT ≤ 5.5V. 15mm × 15mm × 4.32mm LGA, 15mm ×
15mm × 4.92mm BGA
LTM4645
Single 25A Step-Down µModule Regulator
4.7V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 1.8V. 9mm × 15mm × 3.51mm BGA
LTM4647
Single 30A Step-Down µModule Regulator
4.7V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 1.8V. 9mm × 15mm × 5.01mm BGA
LTM4636
Single 40A Step-Down µModule Regulator
4.7V VIN 15V, 0.6V ≤ VOUT ≤ 3.3V. 16mm × 16mm × 7.07mm BGA.
36
Rev. A
09/18
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For more information www.analog.com
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