LTM4664AIY#PBF

LTM4664A 30V to 58V Input, Dual 30A, Single 60A µModule Regulator with Digital Power System Management FEATURES DESCRIPTION Complete 48V Input to Low Voltage Dual 30A Supply that Can Scale to 300A, Nonisolated n Dual Analog Loops with Digital Interface for Compensation, Control and Monitoring n Input Voltage Range: 30V to 58V n Output Voltage Range: 0.5V to 1.2V at 30A/Channel n ±3% Output Current Readback Accuracy (–20° to 125°C) n 87% Efficiency for 48V to 1V at 60A, 90% at 40A n ±0.5% Output Voltage Accuracy Over Temperature n 400kHz PMBus-Compliant I2C Serial Interface n 16mm × 16mm × 7.72mm BGA Package The LTM®4664A is a complete nonisolated 48V input high efficiency step-down µModule® regulator with dual 30A outputs. The switching controllers, power MOSFETs, inductors and supporting components are included. Only external capacitors are needed to complete the design. Operating over a 30V to 58V input voltage range, the LTM4664A supports an output voltage of 0.5V to 1.5V at up to 75W. An intermediate output at 25% • VIN is also available. The LTM4664A product video is available on the website. n The LTM4664A dual 30A regulators utilize digitally programmable analog control loops, precision data acquisition circuitry and EEPROM with ECC. The LTM4664A’s 2-wire serial interface allows the 30A outputs to be margined, tuned and ramped up and down at programmable slew rates and sequencing delay times. True input current sense, output currents and voltages, input and output power, temperatures, uptime and peak values are all readable for Dual 30A Power System Management (PSM) channels. APPLICATIONS 48V Systems Computer and Networking Equipment n Electronic Test Equipment n Storage Systems n n Click to view associated TechClip Videos. All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. Patents including 5408150, 5481178, 5705919, 5929620, 6144194, 6177787, 6580258, 7420359, 8163643. Licensed under U.S. Patent 7000125 and other related patents worldwide. TYPICAL APPLICATION 48V to VCORE at 60A 48V to 1V Up to 60A 95 INTVCCS1 CFLY2 CER CFLY1 CER 10k PGOOD_C0 PGOODVCORE 85 80 75 SWC0 FREQS1 RFREQS1 INTVCC RUNS1 SW1 VINS1 SW2 VOUT1 RUNS2 PGOODS1 VINS2F SW3 VINS2 SW4 ON/OFF VOUT2 CBULK 90 CBULK 10k PINS NOT SHOWN FOR 2-PHASE 60A SECTION: VOUTC0_CFG, VTRIMC0_CFG, VOUTC1_CFG, VTRIMC1_CFG, FSWPH_CFG, TSNSC0a, TSNSC0b, TSNSC1a, TSNSC1b, PWM_C0, PWM_C1, GL_C0, GL_C1, PHFLT_C0, PHFLT_C1, EXTVCC, SHARE_CLK, SCL, SDA, ALERT, SYNC VOUT2 48V CER EFFICIENCY (%) PINS NOT SHOWN FOR 4:1 VOLTAGE DIVIDER: VOUT2_SET, OVP_TRIP, VP_SET, INSNSS2+, INSNSS2–, UVS1, UVS2, HYS_PRGM1, HYS_PRGM2, TIMERS1, TIMERS2, INSNSS1+, INSNSS1–, FAULTS1, FAULTS2 VCORE 60A VOUTC0 FREQS2 GND RFREQS2 70 48VIN, 1.0VOUT EFFICIENCY 0 10 COUT3 20 30 40 OUTPUT CURRENT (A) 50 60 4664A TA01c SGND_C0_C1 4.7µF INTVCCS1 VOSNS+_C0 EXTVCCS1 VOUT2 1µF 4.7µF VOSNS–_C0 LTM4664A EXTVCCS2 PGOOD_C1 INTVCCS2 SWC1 VOUTC1 IN+ COUT4 LTM4664A 48VIN VDD25 INTVCC PGOODS2 4:1 DIVIDER VOUT1 VIN/2 VIN/4 DUAL PSM BUCK VOUTC0 VOUTC1 0.5V TO 1.2V/30A 0.5V TO 1.2V/30A VOUT2 4664A TA01b RSEL COMPH1 COMPH0 INTVCC PGOODS2 PGOODS2 RUN_C1 VDD33 VOSNS–_C1 COMP_C1a VOSNS+_C1 RUN_C0 VINS3_C1 COMP_C0a 10k VINS3_C0 COMP_C1b VDD33 LOAD SGND_C0_C1 COMP_C0b CER GND IN ASEL VOUT2 PGOODVCORE 4.7µF VDD25 4664A TA01a PMBus Rev. 0 Document Feedback For more information www.analog.com 1 LTM4664A TABLE OF CONTENTS Features...................................................... 1 Applications................................................. 1 Typical Application ......................................... 1 Description.................................................. 1 Absolute Maximum Ratings............................... 4 Pin Configuration........................................... 4 Order Information........................................... 5 Electrical Characteristics.................................. 5 Typical Performance Characteristics................... 15 4:1 Divider Block Diagram............................... 25 Dual 25A/30A Power System Management (PSM) Block Diagram.............................................. 26 4:1 Divider Operation..................................... 27 4:1 Divider Description............................................ 27 Main Control............................................................ 27 INTVCCS1,2 /EXTVCCS1,2 Power................................. 27 Start-Up and Shutdown........................................... 28 Fault Protection and Thermal Shutdown.................. 28 High Side Current Sensing....................................... 28 Frequency Selection................................................. 28 Power Good and UV (PGOODSn and UVSn pins)....29 Additional Overvoltage Protection...........................29 4:1 Divider Application Information..................... 30 Voltage Divider Pre-Balance Before Switching........30 Overcurrent Protection............................................ 31 Window Comparator Programming......................... 31 Effective Open Loop Output Resistance and Load Regulation....................................................... 32 Undervoltage Lockout.............................................. 32 Fault Response and Timer Programming................. 32 Design Example.......................................................33 Dual 25A/30A PSM Operation............................ 35 PSM Section Overview, Major Features...................35 EEPROM with ECC ..................................................36 Power-Up and Initialization ..................................... 37 Soft-Start ................................................................38 Time-Based Sequencing .........................................38 Voltage-Based Sequencing .....................................38 Shutdown ............................................................... 39 Light-Load Current Operation ................................. 39 Switching Frequency and Phase..............................40 PWM Loop Compensation ......................................40 Output Voltage Sensing ..........................................40 2 INTVCC/EXTVCC Power ...........................................40 Output Current Sensing and Sub Milliohm DCR Current Sensing ...................................................... 41 Input Current Sensing ............................................. 41 PolyPhase Load Sharing ......................................... 41 External/Internal Temperature Sense ...................... 42 RCONFIG (Resistor Configuration) Pins .................. 42 Fault Detection and Handling ..................................45 Status Registers and ALERT Masking .....................46 Mapping Faults to FAULT Pins ................................48 Power Good Pins ....................................................48 CRC Protection .......................................................48 Serial Interface .......................................................48 Communication Protection .....................................48 Device Addressing ..................................................48 Responses to VOUT and IIN/IOUT Faults ................... 49 Output Overvoltage Fault Response ........................ 49 Output Undervoltage Response ..............................50 Peak Output Overcurrent Fault Response ...............50 Responses to Timing Faults ....................................50 Responses to VIN OV Faults ....................................50 Responses to OT/UT Faults .....................................50 Internal Overtemperature Fault Response ...............50 External Overtemperature and Undertemperature Fault Response ..................................................... 51 Responses to Input Overcurrent and Output Undercurrent Faults ................................................ 51 Responses to External Faults .................................. 51 Fault Logging .......................................................... 51 Bus Timeout Protection .......................................... 51 Similarity Between PMBus, SMBus and I2C 2-Wire Interface ...................................................... 52 PMBus Serial Digital Interface ................................ 52 Figure 11 thru Figure 28 PMBus Protocols..............54 PMBus Command Summary............................. 57 PMBus Commands ................................................. 57 Dual 25A/30A PSM Applications Information.......... 63 VIN to VOUT Step-Down Ratios ................................63 Input Capacitors .....................................................63 Output Capacitors ...................................................63 Light Load Current Operation..................................63 Switching Frequency and Phase .............................64 Output Current Limit Programming ........................65 Rev. 0 For more information www.analog.com LTM4664A TABLE OF CONTENTS Minimum On-Time Considerations .........................66 Variable Delay Time, Soft-Start and Output Voltage Ramping ....................................................66 Digital Servo Mode .................................................66 Soft Off (Sequenced Off) ........................................ 67 Undervoltage Lockout .............................................68 Fault Detection and Handling ..................................68 Open-Drain Pins .....................................................68 Phase-Locked Loop and Frequency Synchronization ......................................................69 Input Current Sense Amplifier ................................. 70 Programmable Loop Compensation ....................... 70 Checking Transient Response ................................. 71 PolyPhase® Configuration ......................................72 Connecting the USB to I2C/SMBus/PMBus Controller to the LTM4664A In-System ...................................72 LTpowerPlay: An Interactive GUI for Digital Power..73 PMBus Communication and Command Processing .............................................73 Thermal Considerations and Output  Current Derating ..................................................... 75 Table 10 and Table 11: Output Current Derating (Based on Demo Board).......................................... 78 Dual 25A/30A PSM Applications Information– Derating Curves............................................ 81 EMI Performance ....................................................82 Safety Considerations .............................................82 Layout Checklist/Example ......................................83 Typical Applications....................................... 84 PMBus Command Details................................ 90 Addressing and Write Protect..................................90 General Configuration Commands...........................92 On/Off/Margin.........................................................93 PWM Configuration.................................................95 Voltage.....................................................................98 Input Voltage and Limits..........................................98 Output Voltage and Limits.......................................99 Output Current and Limits..................................... 102 Input Current and Limits ....................................... 104 Temperature........................................................... 105 External Temperature Calibration........................... 105 Timing................................................................... 106 Timing—On Sequence/Ramp................................ 106 Timing—Off Sequence/Ramp............................... 107 Precondition for Restart........................................ 108 Fault Response...................................................... 108 Fault Responses All Faults..................................... 108 Fault Responses Input Voltage.............................. 109 Fault Responses Output Voltage............................ 109 Fault Responses Output Current............................ 112 Fault Responses IC Temperature........................... 113 Fault Responses External Temperature.................. 114 Fault Sharing.......................................................... 115 Fault Sharing Propagation..................................... 115 Fault Sharing Response......................................... 117 Scratchpad............................................................ 117 Identification.......................................................... 118 Fault Warning and Status....................................... 119 Telemetry............................................................... 126 NVM Memory Commands..................................... 130 Store/Restore........................................................ 130 Fault Logging......................................................... 131 Block Memory Write/Read..................................... 135 Package Description.................................... 136 Typical Applications..................................... 138 Related Parts............................................. 138 Rev. 0 For more information www.analog.com 3 LTM4664A ABSOLUTE MAXIMUM RATINGS (Note 1) EXTVCC......................................................... –0.3V to 6V VOUTCn....................................................... –0.3V to 3.6V VOSNS+_Cn.................................................... –0.3V to 6V VOSNS –_Cn................................................. –0.3V to 0.3V RUN_Cn, SDA, SCL, ALERT....................... –0.3V to 5.5V FSWPH_CFG, VOUTCn_CFG, VTRIMCn_CFG, ASEL, COMP_1a, COMP_1b, COMP_0a, COMP_0b.........–0.3V to 2.75V FAULT_Cn, SYNC, SHARE_CLK, WP, PGOOD_Cn, PWM_Cn, PHFLT_Cn.................................. –0.3V to 3.6V TSNS_Cna,................................................ –0.3V to 2.2V TSNS_Cnb..................................... –0.3V to 0.8V, < 5mA OVP-SET IMAX Sink..................................... ………. 5mA INTVCC VDD33, VDD25 and GL_Cn are Outputs. Internal Operating Temperature Range (Notes 2, 14, 15).............................–40°C to 125°C Storage Temperature Range................... –55°C to 125°C Peak Solder Reflow (Package Body) Temperature. 245°C 4:1 Divider VINS1, SW1, SW2, INSNSS1+, INSNSS1–, FAULTS1, FAULTS2..............................................–0.3V to 60V VINS2, VINS2F, INSNSS2+, INSNSS2–, PGOODS1, PGOODS2, EXTVCCS1, EXTVCCS2, SW3, SW4, OVP_SET, VOUT2_SET, OVP_TRIP, VOUT1........–0.3V to 40V VOUT2............................................................ 0.3V to 20V INTVCCS1, INTVCCS2................OUTPUT ONLY, RATED 6V RUNS1, RUNS2............................................. –0.3V to 6V UVS1, UVS2, HYS_PRGMS1, HYS_PRGMS2, TIMERS1, TIMERS2, FREQS1, FREQS2......................–0.3V to INTVCCS1, –0.3 to INTVCCS2 DUAL 25A/30A PSM SECTION VINS3_Cn, IN+, IN–....................................... –0.3V to 18V (VINS3_Cn – IN+), (IN+ – IN–)...................... –0.3V to 0.3V SWC0, SWC1............... –1V to 18V, –5V to 18V Transient PIN CONFIGURATION TOP VIEW 1 2 3 4 5 A 6 7 8 9 10 11 VOUTC1 12 13 14 15 16 VOUTC0 B C – INSNSS2 OVP_SET VOUT2_SET HYS_PRGMS2 TIMERS2 SW4 RUNS2 VOUT2 D VOUT1 VINS2 SW3 VINS2F E INSNSS2+ INTVCCS1 PGOODS1 OVP_TRIP UVS1 FREQS1 EXTVCCS2 H FREQS2 INTVCCS2 PGOODS2 UVS2 FAULTS2 VOUTC0_CFG VOUTC1_CFG VDD25 VDD33 PHFLT_C1 L M N VOSNS+_C1 GL_C1 INSNSS1 VINS1 PWM_C1 SHARE_CLK SDA COMP_1b VINS3_C1 PGOOD_C1 TSNS_C1b T FAULT_C0 SCL TSNSC_0a VINS3_C0 SGN_DC0_C1 SGND_C0_C1 INTVCC EXTVCC SWC1 PHFLT_C0 TSNSC_1a FAULT_C1 PWM_C0 SYNC COMP_0b GL_C0 IN– P R FSWPH_CFG + INSNSS1 RUN_C0 WP RUN_C1 K VOSNS–_C1 SW1 – ALERT J VTRIMC0_CFG COMP_1a FAULTS1 HYS_PRGMS1 ASEL VTRIMC1_CFG EXTVCCS1 RUNS1 TIMERS1 F G SW2 + IN SWC0 COMP_0a VOSNS–_C0 PGOOD_C0 VOSNS+_C0 TSNS_C0b GND BGA PACKAGE 240-PIN (16mm × 16mm × 7.72mm) TJMAX = 125°C, θJCTOP = 5.47 C/W, θJCBOTTOM = 2.15 C/W, θJA = 5.3 C/W θJC VALUES ARE DETERMINED BY SIMULATION PER JESD51 CONDITIONS. θJA VALUE IS OBTAINED FROM MEASUREMENTS WITH DEMO BOARD. WEIGHT = 7.26 GRAMS. REFER TO PAGE 78 FOR LAB MEASUREMENT AND DERATING INFORMATION. NOTE: NOT RECOMMENDED FOR BACK-SIDE REFLOW SOLDERING. SEE WEBSITE FOR MORE INFORMATION. 4 Rev. 0 For more information www.analog.com LTM4664A ORDER INFORMATION PART MARKING PART NUMBER LTM4664AIY#PBF PAD OR BALL FINISH SAC305 (RoHS) DEVICE FINISH CODE PACKAGE TYPE MSL RATING e1 BGA 3 LTM4664AY • Contact the factory for parts specified with wider operating temperature ranges. *Pad or ball finish code is per IPC/JEDEC J-STD-609. TEMPERATURE RANGE (SEE NOTE 2) –40°C to 125°C • Recommended LGA and BGA PCB Assembly and Manufacturing Procedures • LGA and BGA Package and Tray Drawings ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the internal operating junction temperature. TA = 25°C, VINS1 = 48V, and RUNn = 5V where n = stage # unless otherwise noted. See Figure 46 configuration for setup. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VINS1 Input DC Voltage Stage 1 Note 4 30 58 V VINS2 Input DC Voltage Stage 2 Note 4 15 29 V VOUT1 Range VOUT1 Output Range Note 4 15 29 V 7.5V 14.5 V 75 W 4:1 Divider Section VOUT2 Range VOUT2 Output Range Note 4 Maximum Power Maximum Output Power All Conditions, Note 4 VOUT1(DC) VOUT1 OUTPUT Note 4, Based on Figure 49 VINS1 = 48V, RUN = 5V, IVOUT1 = 0A l 23.5 24 24.5 V VOUT2(DC) VOUT2 OUTPUT Note 4, Based on Figure 49 VINS2 = 24V, RUN = 5V, IVOUT2 = 0A l 11.5 12 12.5 V VUVLO Undervoltage Lockout INTVCC Falling INTVCC Rising 4.85 5.05 V V IQ VINSn VINS1, VINS2 Quiescent Current Each Stage RUNn = 0V RUNn = 5V, No Switching RUNn = 5V, Switching 150 1.6 44 µA mA mA Overcurrent Protection Section INSNSS1+ Stage 1 Current Sense+ INSNSS1+ = INSNSS1– = 60V VOUT1 = 30V, RUNS1 = 5V 220 350 µA INSNSS2+ Stage 2 Current Sense+ INSNSS2+ = INSNSS2– = 30V VOUT2 = 15V, RUNS2 = 5V 220 350 µA INSNSS1– Stage 1 Current Sense– INSNSS1+ = INSNSS1– = 60V, RUNS1 = 0V INSNSS2– Stage 2 Current Sense– INSNSS2+ = INSNSS2– = 30V, RUNS2 = 0V INSNSS1, INSNSS2 Current Limit Threshold Threshold for Each Stage l –5 1 5 µA l –5 1 5 µA l 45 50 55 mV Pre Charge Balance RVINS2F VINS2 Resistance to GND See Block Diagram (Note 10) 1 MΩ RVF2 Resistance Between Pins VINS2 to VINS2F See Block Diagram Part of a RC Filter Stage 2 1 kΩ INSNSS1+ Balance Current Stage 1 Current Sense + Source Pre-Balance Phase VINS1 = 60V INSNSS1+ = INSNSS1– = 60V, VOUT1 = 15V , Timer = 1V 95 mA INSNSS2+ Balance Current Stage 2 Current Sense + Source Pre-Balance Phase VINS2 = 30V INSNSS2+ = INSNSS2– = 30V, VOUT2 = 10V, Timer = 1V 95 mA ISOURCE VOUTn ISOURCE Current to Pre-Start Up Balance VOUTn and CFLYn, n = Stage # INSNSSn = VINSn = 24V VOUTn = 10V, Timer = 0.8V See Block Diagram 95 mA Rev. 0 For more information www.analog.com 5 LTM4664A ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the internal operating junction temperature. TA = 25°C, VINS1 = 48V, and RUNn = 5V where n = stage # unless otherwise noted. See Figure 46 configuration for setup. (Note 3) SYMBOL PARAMETER CONDITIONS ISINK VOUTn ISINK Current to Pre-Start Up Balance INSNSSn = VINSn = 24V VOUTn = 11V, Timer = 0.8V VOUTn and CFLYn, n = Stage # See Block Diagram MIN TYP MAX 50 UNITS mA RUNn Pins VTH_RUNn Run PIN Threshold n = Stage # VRUN Rising VRUNn HYS Run Pin Hysteresis n = Stage # 90 mV OVP-SET In OVP-SET Input Range MAX 25 V l 1.1 1.22 1.4 V OVP Comparator VOUT2-SET VOUT2-SET Range MAX 25 V IB Input Bias I VCM = 0V to 25V 30 mA VOS Input Offset 0.5V < VCM < 25V 3 mV PSRR Power Supply Rejection 0.5V < VCM < 25V (Note 10) 85 db CMRR Common Mode Rejection 0.5V < VCM < 25V (Note 10) 80 db Delay Propagation Delay 10 µs OVP_Trip Sink OVP_Trip Sink ISINK = 5mA (Note 10) 0.35 V Internal (LDO) Low Drop Out Regulator, n = Stage # 30V < VINS1 < 58V, VEXTVCCS1 = 0V, Stage 1 15V < VINS2 < 19V, VEXTVCCS2 = 0V, Stage 2 ICC = 50mA, VEXTVCCSn = 0V INTVCC Regulators VINTVCCSn VINTVCCSn Load LDO Load Regulation INTVCCSn IPeak INTVCC Stage Peak Output Current VINTVCCSn with EXTVCC LDO Output Range with EXTVCCn, n = Stage # 12V < VEXTVCCn < 24V, VINSn = 12V VINTVCCSn Load EXT LDO Load Regulation with EXTVCC ICC = 50mA, VEXTVCCn = 6.5V VEXTVCCn Threshold EXTVCCn Switch Over EXTVCCn Hysteresis VEXTVCCn HYS 5.4 5.6 5.9 0.5 2 150 VEXTVCCn Ramping Positive 5.4 6.3 V % mA 5.6 5.9 V 1 2 % 6.5 6.65 V 400 mV Switching Oscillator Frequency Range n Frequency Range n = Stage # 100 1000 kHz fNOM Stage 1 Optimized Efficiency Freq. Stage 1 FREQS1. Pin Resistor = 36.5k 100 kHz fNOM Stage 2 Optimized Efficiency Freq. Stage 2 FREQS2. Pin Resistor = 60.4k 200 kHz ΔVOUT/VOUT Stage 1 Stage 1 Load Regulation Accuracy VOUT1 = 24V, 0A to 3.2A Maximum = 75W VINS1 = 48V, FREQS1 = 100kHz CINB1 = 33µF (Bulk Input Capacitor) CIN1 = 2.2µF 100V Ceramic, CFLY1 = 10µF 50V X6 COUT1 = 10µF 50V 3.5 % VOUT1 Output Load VOUT1 Max Load Current (Note 4) VOUT1 = 24V, 0A to 3.2A Maximum = 75W VINS1 = 48V, FREQS1 = 100kHz CINB1 = 33µF (Bulk Input Capacitor) CIN1 = 2.2µF 100V Ceramic, CFLY1 = 10µF 50V X6 COUT1 = 10µF 50V M1-M4 RDS-ON Stage 1 MOSFET On Resistance VGS = 5V (Note 16) Output Specifications 6 3.2 18 A mΩ Rev. 0 For more information www.analog.com LTM4664A ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the internal operating junction temperature. TA = 25°C, VINS1 = 48V, and RUNn = 5V where n = stage # unless otherwise noted. See Figure 46 configuration for setup. (Note 3) SYMBOL PARAMETER CONDITIONS ΔVOUT/VOUT Stage 2 Stage 2 Load Regulation Accuracy VOUT2 = 12V, 0A to 6.3A Maximum = 75W VINS2 = 24V, FREQS2 = 200kHz CINB2 = 33µF (Bulk Input Capacitor) CIN2 = 10µF 50V Ceramic, CFLY2 = 22µF 25V X6, COUT2 = 22µF 25V VOUT2 Output Load VOUT1 Max Load Current (Note 4) VOUT2 = 12V, 0A to 6.3A Maximum = 75W VINS2 = 24V, FREQS2 = 200kHz CINB2 = 33µF (Bulk Input Capacitor) CIN2 = 10µF 50V Ceramic, CFLY2 = 22µF 25V X6, COUT2 = 22µF 25V M5-M8 RDS-ON VOUT1, (AC) Stage 2 MOSFET On Resistance Output Ripple Voltage 10 150 mΩ mVpk-pk VOUT2, (AC) Output Ripple Voltage 50 mVpk-pk tSTART Stage 1 Turn-on Time From RUN 1 VGS = 5V (Note 16) VOUT1 = 24V, 0A to 3A VINS1 = 48V, FREQS1 = 100kHz CINB1 = 33µF (Input Bulk Capacitor) CIN1 = 2.2µF 100V Ceramic, CFLY1 = 10µF 50V X6 COUT1 = 10µF 50V VOUT2 = 12V, 0A to 6A VINS2 = 12V, FREQS2 = 200kHz CINB2 = 33µF (Input Bulk Capacitor) CIN2 = 10µF 50V Ceramic, CFLY2 = 22µF 25V X6, COUT2 = 22µF 25V VOUT1 = 0V at Start Up to 24V, 0A, VINS1 = 48V, FREQS1 = 100kHz CINB1 = 33µF (Input Bulk Capacitor) CIN1 = 2.2µF 100V Ceramic, CFLY1 = 10µF 50V X6 COUT1 = 10µF 50V, CTIMERS1 = 0.22µF VOUT2 = 0V at Start Up to 12V, 0A, VINS2 = 24V, FREQS2 = 200kHz CINB2 = 33µF (Input Bulk Capacitor) CIN1 = 2.2µF 100V Ceramic, CFLY1 = 22µF, 25V X6 COUT2 = 22µF 25V, CTIMERS2 = 0.47µF 40 msec 75 msec IFAULT = 2mA VFAULT = 5V 0.2 tSTART Stage 2 Turn-on Time Stage 2 From RUN 2 MIN TYP MAX 5 UNITS % 6.3 A HYS_PRGMn and FAULTSn VFAULTSn IFAULT_LEAKSn IHYS_PRGMSn VFAULTSn VFAULTSn VFAULTSn FAULT Voltage Low FAULT Leakage Current HYS_PRGM Setting Current VOUTSn Fault Trip Level VOUTSn Fault Trip Level VOUTSn Fault Trip Level UV COMPARATORn and PGOODn Undervoltage Threshold VUVTHSSn Undervoltage Hysteresis VHYS_PRGMSn PGOOD Voltage Low VPGOODSn PGOOD Leakage Current IPGOODSn_LEAK TimerSn TimerSn Current ITIMERn VINSn = 24V, VOUTn, HYS_PRGMSn = 0V, VOUTSn Ramp Up VOUTSn Ramp Down VINSn = 24V, VOUTn, HYS_PRGMSn = 5V, VOUTSn Ramp Up VOUTSn Ramp Down VINSn = 24V, VOUTn, HYS_PRGMSn = 2.4V, VOUTSn Ramp Up VOUTSn Ramp Down UV Pin Voltage Rising IPGOOD = 2mA VPGOOD = 5V VTIMER < 0.5V or VTIMER > 1.2V 0.5V < VTIMER < 1.2V l 9 10 0.5 ±1 11 l l 12.2 11.6 12.3 11.7 12.45 11.8 V V l l 12.7 11.1 12.8 11.2 12.9 11.4 V V l 14.15 l 9.5 14.3 9.65 14.45 9.8 V V 0.99 1.01 120 0.35 1.03 V mV V µA 3.5 7 0.5 ±1 V µA µA µA µA Rev. 0 For more information www.analog.com 7 LTM4664A ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal operating temperature range (Note 1, 2, 3). Specified as each individual output channel designated with n (Note 3). TA = 25°C, VINS3 = 12V, RUN_Cn = 3.3V, EXTVCC = 0V, FREQUENCY_SWITCH = 350kHz and VOUTCn commanded to 1.000V unless otherwise noted. Configured with factory default EEPROM settings, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DUAL 25A/30A PSM OUTPUT VINS3 Input DC Voltage Operating VOUTCn Diff Sensed on VOSNS+_Cn/VOSNS–_Cn-Pin-Pair; l 7 16 V l 0.5 1.5 V 1.005 1.015 V V VOUTCn Range of Output Voltage Regulation VOUTCn(DC) Output Voltage, Total Variation with Line and Load l 0.995 1.000 Digital Servo Engaged (MFR_PWM_MODEn[6] = 1b) Digital Servo Disengaged (MFR_PWM_MODEn[6] = 0b) l 0.985 1.000 VOUTCn_CFG Commanded to 1.000V, VOUTCn Low Range (MFR_PWM_MODEn[1] = 1b) (Note 6) VINS3 UVLO Undervoltage Lockout Threshold VINTVCC Falling VINTVCC Rising 3.55 3.9 V V IINRUSH(VINS3) Input Inrush Current at Start-Up VOUTCn =1V, VINS3 = 12V; No Load Besides Capacitors; TON_RISEn = 3ms 400 mA IS(VINS3,DCM) Input Supply Current in Discontinuous Mode Operation Discontinuous Mode, MFR_PWM_MODEn[0] = 0b, IOUTCn = 100mA 60 mA IS(VINS3,FCM) Input Supply Current in Forced-Continuous Mode Operation Forced Continuous Mode, MFR_PWM_MODEn[0] = 1b IOUTn = 100mA IOUTn = 30A VINS3 = 12V, VOUTn = 1V 80 3.0 mA A Shutdown, RUN_Cn = 0V 25 mA IS(VINS3,SHUTDOWN) Input Supply Current in Shutdown Commanded by Serial Bus or with Resistors Present at Start-Up on VOUTCn_CFG, Differential Remote Sense Path Voltage (Notes 4, 6) Output Specifications ∆ ∆ IOUTCn Output Continuous Current Range Utilizing MFR_PWM_MODE[7] = 0 , and Using ~IOUT = 34A , Page103, (Note 4) ΔVOUTn (LINE) Line Regulation Accuracy Digital Servo Engaged (MFR_PWM_MODEn[6] = 0b) Digital Servo Disengaged (MFR_PWM_MODEn[6] = 0b) Open Circuit; IOUTCn = 0A, 7V ≤ VIN ≤ 16V, VOUT Low Range (MFR_PWM_MODEn[1] = 1b), FREQUENCY_SWITCH = 350kHz (Note 6) 0.03 0.03 ±0.2 %/V %/V Load Regulation Accuracy Digital Servo Engaged (MFR_PWM_MODEn[6] = 1b) Digital Servo Disengaged (MFR_PWM_MODEn[6] = 0b) l 0A ≤ IOUTn ≤ 30A, VOUT Low Range, (MFR_PWM_MODEn [1] = 1b) (Note 6) 0.03 0.2 0.5 % % VOUTn ΔVOUTn (LOAD) VOUTn VOUTn(AC) Output Voltage Ripple 0 30 10 fS (Each Channel) VOUTCn Ripple Frequency FREQUENCY_SWITCH Set to 350kHz (0xFABC) Turn-On Overshoot TON_RISEn = 3ms (Note 7) 8 mV tSTART Turn-On Start-Up Time Time from VIN Toggling from 0V to 12V to Rising Edge PGOOD_Cn, TON_DELAYn = 0ms, TON_RISEn = 3ms 30 ms tDELAY(0ms) Turn-On Delay Time Time from First Rising Edge of RUN_Cn to Rising Edge of PGOOD_Cn. TON_DELAYn = 0ms, TON_RISEn = 3ms, VINS3 Having Been Established for at Least 70ms ΔVOUTn(LS) Peak Output Voltage Deviation for Dynamic Load Step Load: 0A to 12.5A and 12.5A to 0A at 12.5A/μs, VOUTn = 1V, VINS3 = 12V (Note 7) See Load Transient Graph 40 mV tSETTLE Settling Time for Dynamic Load Step Load: 0A to 12.5A and 12.5A to 0A at 12.5A/μs, VOUTn = 1V, VINS3 = 12V (Note 7) See Load Transient Graph 30 µs 8 l 2.9 350 mV ΔVOUTCn(START) l 320 A 3.3 380 3.7 kHz ms Rev. 0 For more information www.analog.com LTM4664A ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal operating temperature range (Note 1, 2, 3). Specified as each individual output channel designated with n (Note 3). TA = 25°C, VINS3 = 12V, RUN_Cn = 3.3V, EXTVCC = 0V, FREQUENCY_SWITCH = 350kHz and VOUTCn commanded to 1.000V unless otherwise noted. Configured with factory default EEPROM settings, unless otherwise noted. SYMBOL PARAMETER CONDITIONS IOUTn(OCL_AVg) Output Current Limit, Time Averaged Time-Averaged Output Inductor Current Limit Inception Threshold, Commanded by IOUT_OC_FAULT_LIMITn (Note 7) Utilizing MFR_PWM_MODE[7] = 0b, and Using ~IOUT = 34A , Page103 MIN TYP MAX UNITS VFBCMn Feedback Input Common Mode Range VOSNS–_Cn Valid Input Range (Referred to SGND) VOSNS+_Cn Valid Input Range (Referred to SGND) VOUTn-RNGL Full-Scale Command Voltage Range Low (0.5V to 2.75V) Set Point Accuracy Resolution LSB Step Size Limit Design to 1.5V Operating for Module MFR_PWM_MODEn[1] = 1b, VOUTn Commanded to 2.75V (Notes 8, 10) –0.5 Full-Scale Command Voltage Range High (0.5V to 3.6V) Set Point Accuracy Resolution LSB Step Size Limit Design to 1.5V Operating for Module MFR_PWM_MODEn[1] = 0b, VOUTn Commanded to 3.60V (Notes 8, 10) –0.5 RVSENSEn+ VOSNS+_Cn Impedance to SGND 0.05V ≤ VVOSNS+_Cn – VSGND ≤ 3.3V 50 kΩ tON(MIN) Minimum On-Time (Note 10 ) 60 nsec gm0,1 Resolution Error Amplifier gm(max) Error Amplifier gm(min) LSB Step Size COMP0,1 = 1.35V, MFR_PWM_CONFIG[7:5] = 0 to 7 MFR_PWW_CONFIG Section (Note 10) 3 5.76 1 0.68 Bits mmho mmho mmho RCOMP0, 1 Resolution Compensation Resistor RCOMP(MAX) Compensation Resistor RCOMP(MIN) MFR_PWM_CONFIG[4:0] = 0 to 31 (See Figure 1, Note 10) 5 62 0.5 Bits kΩ kΩ 34 A Control Section VOUTn-RNGH l l –0.1 0.3 3.6 2.75 12 0.688 3.60 12 1.375 V V V % Bits mV 0.5 V % Bits mV 0.5 Analog OV/UV Ch 0,1(Overvoltage/Undervoltage) Output Voltage Supervisor Comparators (VOUT_OV/UV_FAULT_LIMIT and VOUT_OV/UV_WARN_ LIMIT Monitors) NOV/UV_COMP Resolution, Output Voltage Supervisors (Notes 9, 10) VOV-RNG Output OV Comparator Threshold Detection Range (Notes 9, 10) Limit Design to 1.5V Operating for Module Low Range Scale, MFR_PWM_MODEn[1] = 1b High Range Scale, MFR_PWM_MODEn[1] = 0b VOUSTP Output OV and UV Comparator Threshold Programming LSB Step Size (Notes 9, 10) Low Range Scale, MFR_PWM_MODEn[1] = 1b High Range Scale, MFR_PWM_MODEn[1] = 0b VOV-ACC-Cn Output OV Threshold Accuracy Range Low (Notes 9, 10) 0.5V ≤ VVOSNS+_Cn – VVOSNS–_Cn ≤ 2.7V, MFR_PWM_ MODEn[1] = 1b 1V ≤ VVOSNS+_Cn – VVOSNS–_Cn ≤ 3.6V, MFR_PWM MODEn[1] = 0b Range High 9 0.5 1 Bits 2.7 3.6 5.6 11.2 mV mV ±40 l ±1.5 V V mV % Rev. 0 For more information www.analog.com 9 LTM4664A ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal operating temperature range (Note 1, 2, 3). Specified as each individual output channel designated with n (Note 3). TA = 25°C, VINS3 = 12V, RUN_Cn = 3.3V, EXTVCC = 0V, FREQUENCY_SWITCH = 350kHz and VOUTCn commanded to 1.000V unless otherwise noted. Configured with factory default EEPROM settings, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN VUV-RNG Output UV Comparator Threshold Detection Range (Note 10) Limit Design to 1.5V Operating for Module Low Range Scale, MFR_PWM_MODEn[1] = 1b High Range Scale, MFR_PWM_MODEn[1] = 0b 0.5 1 VUV-ACC Cn Output UV Threshold Accuracy Range Low (Notes 9, 10) 0.5V ≤ VVOSNS+_Cn – VVOSNS–_Cn ≤ 2.7V, MFR_PWM_ MODEn[1] = 1b 1V ≤ VVOSNS+_Cn – VVOSNS–_Cn ≤ 3.6V, MFR_PWM_ MODEn[1] = 0b Range High TYP l MAX UNITS 2.7 3.6 V V ±40 mV ±1.5 % tPROP-OV Output OV Comparator Response Times Overdrive to 10% Above Programmed Threshold 100 µs tPROP-UV Output UV Comparator Response Times Underdrive to 10% Below Programmed Threshold 100 µs Analog OV/UV VINS3 Input Voltage Supervisor Comparators (Threshold Detectors for VIN_ON and VIN_OFF) NVINS3-OV/UV-COMP VINS3 OV/UV Comparator Threshold-Programming Resolution (Notes 9, 10) VINS3-OU-RANGE VINS3 OV/UV Comparator Threshold-Programming Range ABS MAX = 18V for Module Design VINS3-OU-STP VINS3 OV/UV Comparator Threshold-Programming LSB Step Size (Note 10) VINS3-OU-ACC VINS3 OV/UV Comparator Threshold Accuracy 4.5V < VINS3 ≤ 16V, Operating Range, 16V Max for Module tPROP-VINS3-LOW-VIN VINS3 OV/UV Comparator Response Time, High VIN Operating Configuration tPROP-VINS3-LOW-VIN VINS3 OV/UV Comparator Response Time, Low VIN Operating Configuration 9 l 4.5 Bits 16 76 V mV ±350 mV Test Circuit 1, and: VIN_ON = 9V; VINS3 Driven from 8.775V to 9.225V VIN_OFF = 9V; VINS3 Driven from 9.225V to 8.775V 100 100 µs µs Test Circuit 2, and: VIN_ON = 4.5V; VINS3 Driven from 4.225V to 4.725V VIN_OFF = 4.5V; VINS3 Driven from 4.725V to 4.225V 100 100 µs µs l Input Voltage (VINS3) Readback (READ_VIN) NVINS3-RB Input Voltage Readback Resolution and LSB Step Size (Notes 5, 10) 10 15.625 Bits mV VINS3-F/S Input Voltage Full-Scale Digitizable Range (Notes 7, 11) 18V for Module Design VINS3-RB-ACC Input Voltage Readback Accuracy READ_VIN, 4.5V ≤ VINS3 ≤ 16V, (VIN = VINS3) tCONVERT-VINS3-RB Input Voltage Readback Update Rate MFR_ADC_CONTROL = 0.00 (Notes 10, 12) MFR_ADC_CONTROL = 0.01 (Notes 10, 12) 90 8 ms ms 16 244 Bits µV 43 V 2 l % Channels 0 and 1 Output Voltage Readback (READ_VOUTn) NVO-RB Output Voltage Readback Resolution and LSB Step Size (Note 10) VO-F/S Output Voltage Full-Scale Digitizable Range VRUNn = 0V (Note 10) Design Limited to 1.5V VO-RB-AC-Cn Output Voltage Readback Accuracy 0.5V ≤ VVOSNS+_Cn – VVOSNS– _Cn ≤ 1.0V 1V ≤ VVOSNS+_Cn – VVOSNS – _Cn ≤ 3.6V 8 l V Within ± 5mV, Reading Within ± 0.5%, Reading Channels 0 and 1 Output Current (READ_IOUTn) NIO-RB Output Current Readback Resolution and LSB Step Size (Notes 5, 10) Based on MFR_PWM_MODE[7] = 1 Using the OUT_OC_FAULT_LIMIT of 34A 10 34.1 IO-F/S Output Current Full-Scale Digitizable Range (Notes 5, 10) Based on MFR_PWM_MODE[7] = 1 Using the IOUT_OC_FAULT_LIMIT of 40A 34 10 Bits mA A Rev. 0 For more information www.analog.com LTM4664A ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal operating temperature range (Note 1, 2, 3). Specified as each individual output channel designated with n (Note 3). TA = 25°C, VINS3 = 12V, RUN_Cn = 3.3V, EXTVCC = 0V, FREQUENCY_SWITCH = 350kHz and VOUTCn commanded to 1.000V unless otherwise noted. Configured with factory default EEPROM settings, unless otherwise noted. SYMBOL PARAMETER CONDITIONS IO-RB-ACC Output Current, Readback Accuracy READ_IOUTn, Channels 0 and 1, 0 ≤ IOUTn ≤ 25A, Forced-Continuous Mode, MFR_PWM_MODEn[0] = 1b l With Offset Adjustment (–20°C to 125°C) (Note 7) See Histograms in Typical Performance Characteristics Section MIN IO-RB(25A) Full Load Output Current Readback IOUTn = 30A Max by Module Design Up to 1.2V (Note 7) tCONVERT-IO-RB Output Current Readback Update Rate MFR_ADC_CONTROL = 0×00 (Notes 10, 12) MFR_ADC_CONTROL = 0×06 (CH0 IOUT)or 0×0A (CH1 IOUT) (Notes 9, 17) See MFR_ADC_CONTROL Section TYP MAX 5 3.5 25 30 UNITS % % A 90 8 ms ms 10 Bits 15.26 30.52 61 µV µV µV Input Current Readback Resolution (Notes 5, 10) VIINSTP LSB Step Size Full-Scale Range = 16mV LSB Step Size Full-Scale Range = 32mV LSB Step Size Full-Scale Range = 64mV IIN_TUE Total Unadjusted Error Gain = 8, 0V ≤ |VIIN+ – VIIN–| ≤ 5mV Gain = 4, 0V ≤ |VIIN+ – VIIN–| ≤ 20mV Gain = 2, 0V ≤ |VIIN+ – VIIN–| ≤ 50mV Gain = 8, 2.5mV ≤ |VIIN+ – VIIN–| (Note 13) Gain = 4, 4mV ≤ |VIIN+ – VIIN–| (Note 13) Gain = 2, 6mV ≤ |VIIN+ – VIIN–| (Note 13) VOS Zero-Code Offset Voltage (Note 10) tCONVERT Update Rate (Note 12) 90 ms (Notes 5,12) See MFR_ADC_CONTROL Section for Faster Update Rates 10 Bits 244 µV N l l l 3.5 2.5 1.8 % % % ±50 µV Internal Controller Supply Current Readback VINS3 N Resolution VICONTROL STP LSB Step Size Full-Scale Range = 256mV ICONTROL TUE Total Unadjusted Error 20mV ≤ |VIINS3_C1–SVIN| ≤ 150mV) tCONVERT Update Rate (Note 12) ±3 % See Block Diagram (Note 10) 90 ms Temperature Readback (TSNS_C0, TSNS_C1) TRES_T Resolution 0.25 °C T0_TUE External Temperature Total Unadjusted Readback Error Supporting Only Delta VBE Sensing (Note 13) 3 °C T1_TUE Internal TSNS TUE VRUN_C0,C1 = 0.0, fSYNC = 0kHz (Note 8) 3 °C tCONVERT Update Rate MFR_ADC_CONTROL = 0×04 or 0×0C (Notes 9, 12, 15) 90 8 ms ms INTVCC Regulator/EXTVCC VINTVCC Internal VCC Voltage No Load 6V ≤ VIN ≤ 16V VLDO_INT INTVCC Load Regulation ICC = 0mA to 20mA, 6V ≤ VIN ≤ 16V VEXTVCC EXTVCC Switchover Voltage VINS3_C1 ≥ 7V, EXTVCC Rising 5.25 4.5 5.5 5.75 V 0.5 ±2 % 4.7 4.9 V VLDO_HYS EXTVCC Hysteresis VLDO_EXT EXTVCC Voltage Drop ICC = 20mA, VEXTVCC = 5.5V 340 60 mV VIN_THR VIN Threshold to Enable EXTVCC Switchover VIN Rising 7.1 V VIN_THF_HYS VIN Hysteresis to Disable EXTVCC Switchover VIN Falling 600 mV 120 mV Rev. 0 For more information www.analog.com 11 LTM4664A ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal operating temperature range (Note 1, 2, 3). Specified as each individual output channel designated with n (Note 3). TA = 25°C, VINS3 = 12V, RUN_Cn = 3.3V, EXTVCC = 0V, FREQUENCY_SWITCH = 350kHz and VOUTCn commanded to 1.000V unless otherwise noted. Configured with factory default EEPROM settings, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX VDD33 Internal VDD33 Voltage 4.5V < VINTVCC or 4.8V < VEXTVCC 3.2 3.3 3.4 UNITS VDD33 Regulator V ILIM VDD33 Current Limit VDD33 = GND, VIN = INTVCC = 4.5V 100 mA VDD33_OV VDD33 Overvoltage Threshold (Note 10) 3.5 V VDD33_UV VDD33 Undervoltage Threshold (Note 10) 3.1 V 2.5 V 80 mA VDD25 Regulator VDD25 Internal VDD25 Voltage LIM VDD25 Current Limit VDD25 = GND, VIN = INTVCC = 4.5V Oscillator and Phase-Locked Loop fRANGE PLL SYNC Range Synchronized with Falling Edge of SYNC l l 250 1000 kHz ±7.5 % fOSC Oscillator Frequency Accuracy Frequency Switch = 250.0kHz to 1000.0kHz (Note 10) VTH(SYNC) SYNC Input Threshold VSYNC Falling VSYNC Rising 1 1.5 VOL(SYNC) SYNC Low Output Voltage ILOAD = 3mA 0.2 ILEAK(SYNC) SYNC Leakage Current in Slave Mode 0V ≤ VPIN ≤ 3.6V θSYNC-θ0 SYNC to Ch0 Phase Relationship MFR_PWM_CONFIG[2:0] = 0,2,3 Based on the Falling Edge of Sync and MFR_PWM_CONFIG[2:0] = 5 Rising Edge of SWC0) MFR_PWM_CONFIG[2:0] = 1 MFR_PWM_CONFIG[2:0]= 4,6 (Note 10) 0 60 90 120 Deg Deg Deg Deg θSYNC-θ1 SYNC to Ch1 Phase Relationship MFR_PWM_CONFIG[2:0] = 3 Based on the Falling Edge of Sync and MFR_PWM_CONFIG[2:0] = 0 Rising Edge of SWC1 MFR_PWM_CONFIG[2:0] = 2,4,5 MFR_PWM_CONFIG[2:0] = 1 MFR_PWM_CONFIG[2:0] = 6 (Note 10) 120 180 240 270 300 Deg Deg Deg Deg Deg V V 0.4 V ±5 µA EEPROM Characteristics Endurance (Notes 15, 16) 0°C < TJ < 85°C EEPROM Write Operations l 10,000 Retention (Notes 15, 16) TJ < 125°C l Mass_Write Mass Write Operation Time STORE_USER_ALL, 0°C < TJ < 85°C During EEPROM Write Operation l OV ≤ VPIN ≤ 5.5V OV ≤ VPIN ≤ 3.6V Cycles 10 Years 440 4100 ms l ±5 µA l ±2 µA 1.35 V Input Leakage Current SDA, SCL, ALERT, RUN IOL Input Leakage Current Leakage Current FAULTn, PGOOD_Cn ILEAK Input Leakage Current Digital Inputs SCL, SDA, RUN_Cn, FAULT_Cn (Note 10) VIH Input High Threshold Voltage l VIL Input Low Threshold Voltage l VHYST Input Hysteresis CPIN Input Capacitance SCL, SDA 0.8 V 0.08 V 10 pF Digital Input WP (Note 10) IPUWP Input Pull-Up Current WP 10 µA Open-Drain Outputs SCL, SDA, FAULT_Cn, ALERT, RUN_Cn, SHARE_CLK, PGOOD_Cn VOL 12 Output Low Voltage ISINK = 3mA 0.4 V Rev. 0 For more information www.analog.com LTM4664A ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal operating temperature range (Note 1, 2, 3). Specified as each individual output channel designated with n (Note 3). TA = 25°C, VINS3 = 12V, RUN_Cn = 3.3V, EXTVCC = 0V, FREQUENCY_SWITCH = 350kHz and VOUTCn commanded to 1.000V unless otherwise noted. Configured with factory default EEPROM settings, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX 1.5 1.8 UNITS Digital Inputs SHARE_CLK, WP (Note 10) VIH Input High Threshold Voltage VIL Input Low Threshold Voltage ISINK = 3mA l l 0.6 V 1 V 3 µs 60 µs 10 µs Digital Filtering of FAULTCn (Note 10) TFLTF Input Digital Filtering FAULTn Digital Filtering of PGOOD_Cn (Note 10) TPGF Output Digital Filtering PGOOD_Cn Digital Filtering of RUN_Cn (Note 10) TRUNF Input Digital Filtering RUN_Cn PMBus Interface Timing Characteristics (Note 10) fSCL Serial Bus Operating Frequency l 10 tBUF Bus Free Time Between Stop and Start l 1.3 400 kHz µs tHD(STA) Hold Time After Repeated Start Condition After This Period, the First Clock is Generated l 0.6 µs tSU(STA) Repeated Start Condition Setup Time l 0.6 tSU(ST0) Stop Condition Setup Time l 0.6 tHD(DAT) Date Hold Time Receiving Data Transmitting Data l l 0 0.3 tSU(DAT) Data Setup Time Receiving Data tTIMEOUT_SMB Stuck PMBus Timer Non-Block Reads Stuck PMBus Timer Block Reads tLOW Serial Clock Low Period l 1.3 tHIGH Serial Clock High Period l 0.6 10000 µs µs µs 0.9 0.1 Measured from the Last PMBus Start Event µs µs 3 255 ms ms 10000 µs µs Channel 0 and Channel 1 Power Stages (Note 10) PWM_Cn LOW PWM Drive Low Level, C0, C1 PWM_Cn HIGH PWM Drive High Level, C0, C1 PHFLT_Cn T Warning Temperature PHFLT_Cn ACC Thermal Warning Accuracy PHFLT_Cn HYS Hysteresis PHFLT_Cn Res On Resistance 0.6 2.6 PHFLT_Cn Pull-Up Pull-Up Resistor V 140 –10 C 10 10 Sink = 8mA PHFLT_Cn Leak Tied to VDD33 V Kelvin Kelvin 37.5 80 Ω 0.1 5 µA 10 kΩ Rev. 0 For more information www.analog.com 13 LTM4664A ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. All voltages are referred to GND pin unless otherwise specified. Note 2: The LTM4664A is tested under pulsed load conditions such that TJ ≈ TA. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. Note 3: All Currents into the device pins are positive, all currents out of the device are negative. Each channel of PSM is tested independently in production. A shorthand notation is used in this document that allows these parameters to be referred to by “VINS3_Cn" and “VOUTCn”, where n is permitted to take on a value of 0 or 1. This italicized “n” notation and convention is extended to encompass all such pin names, as well as register names with channel-specific, i.e., paged data. For example, VOUT_ COMMANDn refers to the VOUT_COMMAND command code data located in Pages 0 and 1, which in turn relate to channel 0 (VOUTC0) and channel 1 (VOUTC1). Registers containing non-page-specific data, i.e., whose data is “global” to the module or applies to both of the module’s channels lack the italicized, “n”, e.g., FREQUENCY_SWITCH. Note 4: See output current derating curves for different VIN, VOUT, Load Current and TA, located in the Dual 25A/30A PSM Applications Information section. For output voltage up to 1.2V, Dual 30A loads are rated. Note 5: The data format in PMBus is 5 bits exponent (signed) and 11 bits mantissa (signed). This limits the output resolution to 10 bits though the internal ADC is 16 bits and the calculations use 32-bit words. Note 6: VOUTCn (DC) and line and load regulation tests are performed in production with digital servo disengaged (MFR_PWM_MODEn[6] = 0b) and low VOUTCn range selected MFR_PWM_MODEn[1] = 1b. The digital servo control loop is exercised in production (setting MFR_PWM_ MODEn[6] = 1b), but convergence of the output voltage to its final settling value is not necessarily observed in final test—due to potentially long time constants involved—and is instead guaranteed by the output voltage readback accuracy specification. Evaluation in application demonstrates capability; see the Typical Performance Characteristics section. Note 7: These typical parameters are based on bench measurements and are not production tested. 14 Note 8: Even though VOUTC0 and VOUTC1 are specified for 3.6V absolute maximum, the maximum recommended command voltage to regulate output channels 0 and 1 is 1.5V with VOUT range-setting bit set using MFR_PWM_MODEn[1]. Note 9: Channel n OV/UV comparator threshold accuracy for MFR_PWM_ MODEn[1] = 1b tested in ATE at VVOSNS+_Cn – VVOSNS–Cn = 0.5V and 2.7V. MFR_PWM_MODEn[1] = 1b is the Low Range. Note 10: Tested at IC-level ATE Note 11: The absolute maximum rating for the VINS3 pin is 18V. Input voltage telemetry (READ_VIN) is obtained by digitizing a voltage scaled down from the VINS3 pin. Note 12: The data conversion is done by default in round robin fashion. All inputs signals are continuously converted for a typical latency of 90ms. Setting MFR_ADC_CONTRL value to be 0 to 12, LTM4664A can do fast data conversion with only 8ms to 10ms. See section PMBus Command for details. Note 13: Part tested with PWM disabled. Evaluation in application demonstrates capability. TUE(%) = ADC Gain Error (%) +100 • (Zero code Offset + ADC Linearity Error)/Actual Value. Note 14: EEPROM endurance and retention are guaranteed by wafer-level testing for data retention. The minimum retention specification applies for devices whose EEPROM has been cycled less than the minimum endurance specification, and whose EEPROM data was written to at 0°C ≤ TJ ≤ 85°C. The RESTORE_USER_ALL or MFR_RESET is valid over the entire operating temperature range and does not influence EEPROM characteristics. Note 15: Write operations above TJ = 85°C or below 0°C are possible although the Electrical Characteristics are not guaranteed and the EEPROM will be degraded. Read operations performed at temperatures below 125°C will not degrade the EEPROM Writing to the EEPROM above 85°C will result in a degradation of retention characteristics. Note 16: M1-M8 power MOSFET are final tested separately before assembly in to the µModule. Note 17: MFR_PWM_MODE[2] = 1 or 0 sets device in low DCR mode or regular DCR mode respectively. MFR_PWM_MODE[7]=1 or 0 sets device in high output current range or low current range. See “Output Current Sensing and sub milliohm DCR Current Sensing” in Operation Section for details. Only VILIMIT codes 2–8 are supported for DCR sensing. Rev. 0 For more information www.analog.com LTM4664A TYPICAL PERFORMANCE CHARACTERISTICS 1.2V Individual Single Output 1st Stage = 100kHz, 2nd Stage = 200kHz, Final 25A/30A Stages = 250kHz, EXTVCC = 5V 1V Individual Single Output 1st Stage = 100kHz, 2nd Stage = 200kHz, Final 25A/30A Stages = 250kHz, EXTVCC = 5V 95 95 90 90 90 85 80 75 5 10 15 20 OUTPUT CURRENT (A) 85 80 30V INPUT 36V INPUT 48V INPUT 54V INPUT 0 EFFICIENCY (%) 95 EFFICIENCY (%) EFFICIENCY (%) 0.9V Individual Single Output 1st Stage = 100kHz, 2nd Stage = 200kHz, Final 25A/30A Stages = 250kHz, EXTVCC = 5V 75 25 80 30V INPUT 36V INPUT 48V INPUT 54V INPUT 5 0 10 15 20 OUTPUT CURRENT (A) 4664A G01 75 25 95 85 EFFICIENCY (%) EFFICIENCY (%) 90 0 5 10 15 20 OUTPUT CURRENT (A) 25 10 15 20 OUTPUT CURRENT (A) FIRST STAGE SWITCH 20V/DIV 80 SECOND STAGE SWITCH 20V/DIV 75 70 0.9V OUTPUT 1V OUTPUT 1.2V OUTPUT 1.5V OUTPUT 65 60 25 VIN 30V TO 54V TRANSIENT 20V/DIV, 50ms/DIV 90 75 5 54V Input Voltage Change, No Load 95 30V INPUT 36V INPUT 48V INPUT 54V INPUT 0 4664A G03 54V Input, 2-Phase 50A Single Output 1st Stage = 100kHz, 2nd Stage = 200kHz, Final 25A/30A Stages = 350kHz, EXTVCC = 5V 85 30V INPUT 36V INPUT 48V INPUT 54V INPUT 4664A G02 1.5V Individual Single Output 1st Stage = 100kHz, 2nd Stage = 200kHz, Final 25A/30A Stages = 350kHz, EXTVCC = 5V 80 85 0 10 20 30 40 FINAL 25A/30 STAGES OUTPUT 1V/DIV 50 OUTPUT CURRENT (A) 4664A G04 4664A G06 54V TO 1V, NO LOAD 4:1 DIVIDER: FIRST STAGE 100kHz, SECOND STAGE 200kHz, FINAL 25A/30A STAGES 250kHz 4664A G05 54V Input Voltage Change, Load 25A Each Dual Output Tracking Start-Up/Shutdown VIN 30V TO 54V TRANSIENT 20V/DIV, 50ms/DIV VOUTC0 = 1V, VOUTC1 = 1.5V 500mV/DIV, 2ms/DIV FIRST STAGE SWITCH 20V/DIV IOUT0 5A/DIV SECOND STAGE SWITCH 20V/DIV RUN_Cn 5V/DIV FINAL 25A/30A STAGES OUTPUT 1V/DIV 4664A G07 54V TO 1V, 25A LOAD EACH 4:1 DIVIDER: FIRST STAGE 100kHz, SECOND STAGE 200kHz, FINAL 25A/30A STAGES 250kHz For more information www.analog.com 4664A G08 48VIN, 10A LOAD ON VOUT0, NO LOAD ON VOUTC1, TON_RISE 0 = 3ms, TON_RISE 1 = 4.5ms, TOFF_DELAY 1 = 0ms, TOFF_DELAY 0 = 1.5ms TOFF_FALL 1 = 4.5ms, TOFF_FALL 0 = 3ms, ON_OFF_CONFIGn = 0x1E Rev. 0 15 LTM4664A TYPICAL PERFORMANCE CHARACTERISTICS Dual Output Start-Up/Shutdown with a Prebiased Load Start-Up VOUTC1 = 1.5V 500mV/DIV INPUT VOLTAGE USED LAB SUPPLY SWITCH (HP6012B) 20V/DIV, 100ms/DIV VOUTC0 = 1V 500mV/DIV FIRST STAGE OUTPUT 20V/DIV, 100ms/DIV SECOND STAGE OUTPUT 10V/DIV IDIODE 20mA/DIV FINAL 25A/30A STAGE OUTPUTS 500mV/DIV RUN_Cn 5V/DIV 4664A G09 4664A G10 2mS/DIV 48VIN, 10A LOAD ON VOUT0, 7.5mA LOAD ON VOUT1, VOUT1 PREBIASED THROUGH A DIODE TON_RISE 0 = 3ms, TON_RISE 1 = 4.5ms, TOFF_DELAY 1 = 0ms, TOFF_DELAY 0 = 1.5ms TOFF_FALL 1 = 4.5ms, TOFF_FALL 0 = 3ms, ON_OFF_CONFIGn = 0x1E 48V TO 1V AT 0A LOAD, EACH 25A/30A STAGE FINAL STAGE TON DELAY AND TON RISE SET TO 100ms Shutdown Full Sequence Turn On INPUT VOLTAGE USED LAB SUPPLY SWITCH (HP6012B) 20V/DIV, 100ms/DIV RUNS1 2V/DIV, 50ms/DIV TIMERS1 = 0.047µF 0.5V/DIV 1ST STAGE SWITCH 20V/DIV FIRST STAGE OUTPUT 20V/DIV, 100ms/DIV SECOND STAGE OUTPUT 10V/DIV 1ST STAGE OUTPUT 20V/DIV FINAL 25A/30A STAGE OUTPUTS 500mV/DIV RUNS2 2V/DIV, 50ms/DIV TIMERS2 = 0.047µF 0.5V/DIV 4664A G11 48V TO 1V AT 0A LOAD, EACH 25A/30A STAGE FINAL STAGE TON DELAY AND TON RISE SET TO 100ms Full Sequence Turn Off 2ND STAGE SWITCH 10V/DIV 2ND STAGE OUTPUT 10V/DIV RUN_Cn 2V/DIV, 50ms/DIV RUNS1 2V/DIV, 50ms/DIV FINAL 25A/30A STAGE SWITCHS 10V/DIV TIMERS1 = 0.047µF 0.5V/DIV 1ST STAGE SWITCH 20V/DIV 1ST STAGE OUTPUT 20V/DIV RUNS2 5V/DIV, 50ms/DIV FINAL 25A/30A STAGE OUTPUTS 1V/DIV 48V TO 1V AT 50A LOAD 4664A G12 TIMERS2 = 0.047µF 0.5V/DIV 2ND STAGE SWITCH 10V/DIV 2ND STAGE OUTPUT 10V/DIV RUN_C1 2V/DIV, 50ms/DIV FINAL STAGE SWITCH 10V/DIV FINAL STAGE OUTPUT 1V/DIV 48V TO 1V AT 50A LOAD 16 4664A G13 Rev. 0 For more information www.analog.com LTM4664A TYPICAL PERFORMANCE CHARACTERISTICS VOUTCn (1V) Load Transient VOUTCn (1.5V) Load Transient VOUTCn 50mV/DIV AC-COUPLED VOUTCn 50mV/DIV AC-COUPLED IOUT 5A/DIV IOUT 5A/DIV 50µs/DIV 4664A G14 4664A G15 48V TO 1V SINGLE CHANNEL, 0A TO 12.5A/µs LOAD STEP COUT = 470µF ×2 POSCAP, 100µF ×5 CER, COMP_Cna = 2200pF, COMP_Cnb = 100pF, EA-GM = 3.69ms, RCOMP = 5k, PSM FREQ = 250kHz, ILIMIT RANGE = LOW VOUT RANGE = LOW 50µs/DIV 48V TO 1.5V SINGLE CHANNEL, 0A TO 12.5A/µs LOAD STEP COUT = 470µF ×1 POSCAP, 330µF ×2 CER, COMP_Cna = 2200pF, COMP_Cnb = 220pF, EA-GM = 3.02ms, RCOMP = 6k, PSM FREQ = 350kHz Dual Phase (50A/0.9V) Load Transient Dual Phase (50A/1V) Load Transient VOUT 50mV/DIV AC-COUPLED VOUT 50mV/DIV AC-COUPLED IOUT 10A/DIV IOUT 10A/DIV 4664A G17 4664A G16 50µs/DIV 48V TO 1V DUAL PHASE SINGLE OUTPUT, 0A TO 25A/µs LOAD STEP COUT = 470µF ×2 POSCAP, 5 × 330µF CER, COMP_C0,1 = 1500pF, COMP_C01b = 100pF, EA-GM = 4.36ms, RCOMP = 13k, PSM FREQ = 350kHz, ILIMIT RANGE = LOW VOUT RANGE = LOW 50µs/DIV 48V TO 0.9V DUAL PHASE SINGLE OUTPUT, 0A TO 25A/µs LOAD STEP COUT = 470µF ×2 POSCAP, 330µF ×5 CER, COMP_C0, 1 = 1500pF, COMP_C01b = 100pF, EA-GM = 4.36ms, RCOMP = 13k, PSM FREQ = 250kHz, ILIMIT RANGE = LOW VOUT RANGE = LOW 25A AC Ripple Noise SWC0 VOUTC0 10mV/DIV AC-COUPLED SWC1 VOUTC1 10mV/DIV AC-COUPLED 4664A G18 48V TO VOUTC0 = 1V, AND VOUTC1 = 1V Rev. 0 For more information www.analog.com 17 LTM4664A TYPICAL PERFORMANCE CHARACTERISTICS 48V to 1V, Second Stage (12V) Shorted 48V INPUT CURRENT 5A/DIV, 20µs/DIV 48V to 1V at 50A Shorted SWITCH VOUTC0 10V/DIV, 20µs/DIV SWITCH VOUTC1 10V/DIV, 20µs/DIV FINAL STAGE VOUT 0.5V/DIV, 20µs/DIV CURRENT ACROSS RSENSE 5A/DIV, 20µs/DIV SW1 20V/DIV, 20µs/DIV SW2 20V/DIV, 20µs/DIV FAULTS1 5V/DIV, 20µs/DIV FIRST STAGE VOUT1 20V/DIV, 20µs/DIV SW3 10V/DIV, 20µs/DIV SW4 10V/DIV, 20µs/DIV SECOND STAGE VOUT2 10V/DIV, 20µs/DIV FAULTS2 2V/DIV, 20µs/DIV SWITCH VOUTC0 10V/DIV, 20µs/DIV SWITCH VOUT1 10V/DIV, 20µs/DIV FINAL STAGE VOUTC0 AND VOUTC1 0.5V/DIV, 20µs/DIV PGOOD_C0 2V/DIV, 20µs/DIV PGOOD_C0 2V/DIV, 20µs/DIV SW3 10V/DIV, 20µS/DIV SW4 10V/DIV, 20µs/DIV SECOND STAGE VOUT2 10V/DIV, 20µs/DIV 4664A G20 48V TO 1V AT 50A SHORTED LAST STAGE 1V OUTPUT VOUTC0 AND VOUTC1 IN PARALLEL 4664A G19 48V TO 1V AT 50A VOUT2 STAGE 12V OUTPUT SHORTED READ_IOUT of 16 LTM4664A Channels 12VIN, 1VOUT, TJ = 125°C, IOUTn = 25A, System Having Reached Thermally Steady-State Condition, No Airflow READ_IOUT of 16 LTM4664A Channels 12VIN, 1VOUT, TJ = 25°C, IOUTn = 25A, System Having Reached Thermally Steady-State Condition, No Airflow 4 4 3 3 3 2 1 0 25.4 26.0 25.2 25.2 25.7 25.8 25.9 25.5 READ_IOUT CHANNEL READBACK (A) 4664A G21 18 NUMBER OF CHANNELS 4 NUMBER OF CHANNELS NUMBER OF CHANNELS READ_IOUT of 16 LTM4664A Channels 12VIN, 1VOUT, TJ = –40°C, IOUTn = 25A, System Having Reached Thermally Steady-State Condition, No Airflow 2 1 0 25.2 25.7 24.9 24.9 25.3 25.5 READ_IOUT CHANNEL READBACK (A) 4664A G22 2 1 0 24.4 25.0 24.2 24.6 24.7 24.9 24.3 24.3 READ_IOUT CHANNEL READBACK (A) 4664A G23 Rev. 0 For more information www.analog.com LTM4664A PIN FUNCTIONS 4:1 Divider Section (Stage 1) GND: (A8-A9, B1-B3, B8-B9, B14-B16, C4-C13, D4,D8,D9, D13, E1-E4, E8-E9, E13-E16, F1-F4, F8-F10, G4, G8-G11, H4, H9-H11, J1-J4, J11, K1-K4, K11, L3, L11, L14-L16, M3-M5, M11, M14, N1-N4, N7, N11-N16, P1-P4, P7-P9, P13-P15, R1-R6, R9, R13-16, T2-T3, T8-T9, T14-T15) Main ground pins for all ground returns. Input and output capacitors are connected to these pin. See recommended layout Figure 45. VOUT1: (C14-C16) 1st stage divide by two output pins. These pins connect to the 2nd stage VINS2 pins. Recommend placing output decoupling capacitance directly between these pins and GND pins. INTVCCS1: (D10) Output of the 5.5V internal linear low dropout regulator. The driver and control circuits are powered from this voltage source. Must be bypassed to power ground with a minimum of 4.7μF ceramic or other low ESR capacitor. Do not use the INTVCCS1 pin for any other ICs. EXTVCCS1: (D11) External Power Input to the Internal LDO Connected to INTVCCS1. This LDO supplies INTVCCS1 power, bypassing the internal LDO powered from VINS1 whenever EXTVCCS1 is higher than 6.5V and VINS1 is higher than 7V. Do not exceed 30V on this pin. This pin can be driven with the VOUT2 output to limit power loss in LDO with VINS1 at higher input voltage. See Applications section. PGOODS1: (D12) This is an open drain output pin. PGOODS1 is pulled to ground if there are any faults or the voltage at UVS1 pin is lower than 1V. Use PGOODS1 or FAULTS1 to sequence on RUNS2 for the second stage. UVS1: (E10) Undervoltage Comparator. If the UVS1 pin voltage is lower than 1V, the PGOODS1 pin is pulled down. If the UV pin voltage is higher than 1V and no faults, PGOODS1 pin is released. Connect to INTVCCS1 if not used. This pin is used to validate proper output regulation. FAULTS1: (E11) This is an open drain output pin. FAULTS1 is pulled to ground when the VOUT1 voltage is out of the (VINS1)/2 window threshold or the voltage between INSNSS1+ and INSNSS1– is higher than 50mV. FAULTS1 pin is released after INTVCCS1 starts up and passes UVLO. Use FAULTS1 or PGOODS1 to sequence on RUNS2 for the second stage. FREQS1: (E12) Frequency Set Pin. There is a precision 10μA current flowing out of this pin. A resistor to ground sets a voltage which in turn programs the frequency. See the 4:1 Divider Application Information section for detailed information. RUNS1: (F11) Stage 1 Run Control Input. Forcing RUNS1 below 1.2V shuts down the controller. When RUNS1 is higher than 1.2V, internal circuitry starts up. There is a 1μA pull-up current flowing out of RUNS1 pin when the RUNS1 pin voltage is below 1.2V and an additional 5μA current flowing out of RUNS1 pin when the RUNS1 pin voltage is above 1.2V. TIMERS1: (F12) Charge Balance and Fault Timer Control Input. A capacitor between this pin and ground sets the amount of time to charge VOUT1 to (VINS1)/2. It also sets the short-circuit retry time. See the 4:1 Divider Application Information. HYS_PRGMS1: (G12) A resistor connected between this pin and ground will set the window threshold of the window comparator that monitors the voltage difference between (VINS1)/2 and VOUT1. There is a 10μA current flowing out of this pin. See Applications section. SW1, SW2: (G14-G16), (D14-D16) Switching nodes for the 1st stage CFLY Flying capacitor. See Block Diagram. I INSNSS1–: (J13) Current sense comparator negative input, connected to the negative node of the current sensing resistor. Short to INSNSS1+ if not used. NSNSS1+: (J14) Current sense comparator positive input, connected to the positive node of the external current sensing resistor. The current sensing resistor has to be placed on the drain of the very top MOSFET. When the voltage between INSNSS1+ pin and INSNSS1– pin is higher than 50mV, the Stage 1 controller indicates an overcurrent fault by pulling the FAULTS1 pin down. The INSNSS1+ pin is also used to source 95mA current to the VOUT1 pin during the pre-balance time in divider applications. Connect directly to the drain of the very top MOSFET if not used. See application schematic section. Rev. 0 For more information www.analog.com 19 LTM4664A PIN FUNCTIONS VINS1: (J15-J16) Power input pins to the first stage divide by two. Place input capacitance between these pins and GND. 4:1 Divider Section (Stage 2) VINS2: (C1-C3) Power input pins to the second stage divide by two. Place input capacitance between these pin and GND. SW3, SW4: (D1-D3), (G1-G3) Switching nodes for the 2nd stage CFLY Flying capacitor. See Block Diagram. VINS2F: (D5) Input Voltage Sensing with Filtering. This pin has a 1kΩ resistor in series from VINS2, and a 4700pf capacitor to GND. The pin has a 1MΩ resistance to GND. See Block Diagram. INSNSS2–: (D6) Current sense comparator negative input, connected to the negative node of the current sensing resistor. Short to INSNSS2+ if not used. RBOT set to 7.5k. If not used, tie this pin to INTVCCS2. See 4:1 Divider Application Information section. OVP_TRIP: (E7) Open collector output that is used to trip off input power and clamp hold up energy during an over voltage fault on VOUT2. See Applications section. TIMERS2: (F5) Charge Balance and Fault Timer Control Input. A capacitor between this pin and ground sets the amount of time to charge VOUT2 to (VINS2)/2. It also sets the short-circuit retry time. See the 4:1 Divider Application Information. VOUT2_SET: (F6) External – comparator input for setting the VOUT2 trip reference level. This can be done with a resistor and 5.1V Zener from VIN. This secondary fault protection is in and above the Fault protection for Stage 1 and Stage 2. The overall input voltage is divided down by four, so VOUT2 will be 1/4 of VIN. The OVP_SET pin will have a voltage divider to monitor the VOUT2 voltage and set to trip when the divider midpoint on the OVP_SET pin exceeds the reference trip level. If not used, tie this pin to ground. See 4:1 Divider Application Information section. INSNSS2+: (D7) Current sense comparator positive input, connected to the positive node of the external current sensing resistor. The current sensing resistor has to be placed on the drain of the very top MOSFET. When the voltage between INSNSS2+ pin and INSNSS2– pin is higher than 50mV, the controller indicates an overcurrent fault by pulling the FAULTS2 pin down. The INSNSS2+ pin is also used to source 95mA current to the VOUT2 pin during the pre-balance time in divider applications. Connect directly to the drain of the very top MOSFET if not used. See Application Schematic section. EXTVCCS2: (F7) External Power Input to the Internal LDO Connected to INTVCCS2. This LDO supplies INTVCCS2 power, bypassing the internal LDO powered from VIN2 whenever EXTVCCS2 is higher than 6.5V and VINS2 is higher than 7V. Do not exceed 30V on this pin. This pin can be driven with the VOUT2 output to limit power loss in LDO with VINS2 at higher input voltage. See 4:1 Divider Application Information section. HYS_PRGMS2: (E5) A resistor connected between this pin and ground will set the window threshold of the window comparator that monitors the voltage difference between (VINS2)/2 and VOUT2. There is a 10μA current flowing out of this pin. See applications section. FREQS2: (G5) Frequency Set Pin. There is a precision 10μA current flowing out of this pin. A resistor to ground sets a voltage which in turn programs the frequency. See the 4:1 Divider Application Information section for detailed information. OVP_SET: (E6) External + input for setting the VOUT2 trip level. The OVP_SET pin will have a voltage divider to monitor the VOUT2 voltage and set to trip when the divider midpoint on the OVP_SET pin exceeds the reference trip level on the VOUT2_SET pin. For example, if the OVP_SET trip point was set for VTRIP, then RTOP = ((VTRIP/5.1V)-1) • 7.5K, with RTOP being the top resistor in the divider, and RBOT is the bottom resistor in the divider. RUNS2: (G6) Stage 2 Run Control Input. Forcing RUNS2 below 1.2V shuts down the controller. When RUNS2 is higher than 1.2V, internal circuitry starts up. There is a 1μA pull-up current flowing out of RUNS2 pin when the RUNS2 pin voltage is below 1.2V and an additional 5μA current flowing out of RUNS2 pin when the RUNS2 pin voltage is above 1.2V. Use PGOODS1, and FAULTS1 from stage one to enable stage 2. 20 Rev. 0 For more information www.analog.com LTM4664A PIN FUNCTIONS INTVCCS2: (G7) Output of the 5.5V internal linear low dropout regulator. The driver and control circuits are powered from this voltage source. Must be bypassed to power ground with a minimum of 4.7μF ceramic or other low ESR capacitor. Do not use the INTVCCS2 pin for any other ICs. VOUT2: (H1-H3) 2nd stage divide by two output pins. These pins connect to the VINS3 input of dual 25A/30A PMBus converter. Recommend placing output decoupling capacitance directly between these pins and GND pins. PGOODS2: (H5) This is an Open Drain Output Pin. PGOODS2 is pulled to ground if there are any faults or the voltage at UVS2 pin is lower than 1V. Use PGOOD2 or FAULTS2 to sequence on RUN_C0, and RUN_C1 for the dual 25A/30A stage. FAULTS2: (H6) This is an Open Drain Output Pin. FAULTS2 is pulled to ground when the VOUT2 voltage is out of the (VINS2)/2 window threshold or the voltage between INSNSS2+ and INSNSS2– is higher than 50mV. FAULTS2 pin is released after INTVCCS2 starts up and passes UVLO. Use FAULTS2 or PGOOD2 to sequence on RUN_C0, and RUN_C1 for the dual 25A/30A PSM stage. UVS2: (H7) Undervoltage Comparator. If the UVS2 pin voltage is lower than 1V, the PGOODS2 pin is pulled down. If the UV pin voltage is higher than 1V and no faults, PGOODS2 pin is released. Connect to INTVCCS2 if not used. This pin is used to validate proper output regulation. PMBus Dual 25A/30A Section VOUTC1 (A1-A7, B4-B7): Channel 1 Output Voltage. Place recommended output capacitors from this connection to GND. See recommended layout in Figure 45. VOUTC0: (A10-A16, B10-B13): Channel 0 Output Voltage. Place recommended output capacitors from this connection to GND. See recommended layout in Figure 45. FSWPH_CFG (H8): Switching Frequency, Channel Phase Interleaving Angle and Phase Relationship to SYNC Configuration Pin. If this pin is left open—or, if the dual 25A/30A regulator is configured to ignore pinstrap (RCONFIG) resistors, i.e., MFR_CONFIG_ALL[6] = 1b—then the LTM4664A’s switching frequency (FREQUENCY_SWITCH) and channel phase relationships (with respect to the SYNC clock; MFR_PWM_ CONFIG[2:0]) are dictated at SVIN power-up according to the LTM4664A’s NVM contents. Default factory values are: 350kHz operation; Channel 0 at 0°; and Channel 1 at 180°C (convention throughout this document: a phase angle of 0° means the channel’s switch node rises coincident with the falling edge of the SYNC pulse). Connecting a resistor divider from VDD25 to SGND_C0_C1, see page 4 (and using the factory default NVM setting of MFR_ CONFIG_ALL[6] = 0b) allows a convenient way to configure multiple LTM4664As with identical NVM contents for different switching frequencies of operation and phase interleaving angle settings of intra- and extra-module-paralleled channels—all, without GUI intervention or the need to “custom preprogram” module NVM contents. (See the Dual 25A/30A PSM Applications Information section.) Minimize capacitance—especially when the pin is left open—to assure accurate detection of the pin state. VTRIMC1_ CFG (J5): Output Voltage Select Pin for VOUTC1, Fine Setting. Works in combination with VOUTC1_CFG to affect the VOUT_COMMAND (and associated output voltage monitoring and protection/fault-detection thresholds) of Channel 1, at SVIN power-up. (See VOUTC1_CFG and the Dual 25A/30A PSM Applications Information section.) Minimize capacitance—especially when the pin is left open—to assure accurate detection of the pin state. Note that use of RCONFIGs on VOUTC1_CFG/VTRIMC1_ CFG can affect the VOUTC1 range setting (MFR_PWM_ MODE1 [1]) and loop gain. A resistor divider from VDD25 to SGND_C0_C1 can set the trim value, see page 43. VOUTC0_CFG (J6): Output Voltage Select Pin for VOUTC0, Coarse Setting. If the VOUTC0_CFG and VTRIMC0_CFG pins are both left open—or, if the LTM4664A is configured to ignore pin-strap (RCONFIG) resistors, i.e., MFR_CONFIG_ALL[6] = 1b—then the LTM4664A's target VOUTC0 output voltage setting (VOUT_COMMAND0) and associated power good and OV/UV warning and fault thresholds are dictated at SVIN power-up according to the LTM4664A’s NVM contents. A resistor connected from this pin to SGND—in combination with resistor pin settings on VTRIMC0_CFG, and using the factory-default NVM setting of MFR_CONFIG_ALL[6] = 0b—can be used Rev. 0 For more information www.analog.com 21 LTM4664A PIN FUNCTIONS to configure the LTM4664A’s Channel 0 output to power-up to a VOUT_COMMAND value (and associated output voltage monitoring and protection/fault-detection thresholds) different from those of NVM contents. (See the 4:1 Divider Application Information section.) Minimize capacitance especially when the pin is left open to assure accurate detection of the pin state. Note that use of RCONFIGs on VOUTC0_CFG/VTRIMC0_CFG can affect the VOUTC0 range setting (MFR_PWM_MODE0 [1]) and loop gain. VOUTC1_CFG (J7): Output Voltage Select Pin for VOUTC1, Coarse Setting. If the VOUTC1_CFG and VTRIMC1_CFG pins are both left open or, if the LTM4664A is configured to ignore pin-strap (RCONFIG) resistors, i.e., MFR_ CONFIG_ALL [6] = 1b then the LTM4664A’s target VOUTC1 output voltage setting (VOUT_COMMAND1) and associated OV/UV warning and fault thresholds are dictated at SVIN power up according to the LTM4664A’s NVM contents, in precisely the same fashion that the VOUTC1_CFG and VTRIMC1_CFG pins affect the respective settings of VOUT1/Channel 1. (See VOUTC1_CFG, VTRIMC1_CFG and the 4:1 Divider Application Information section.) Minimize capacitance—especially when the pin is left open—to assure accurate detection of the pin state. Note that use of RCONFIGs on VOUTC1_CFG/VTRIMC1_CFG can affect the VOUTC1 range setting (MFR_PWM_MODE1 [1]) and loop gain. A resistor divider from VDD25 to SGND_C0_C1. See page 43. ASEL (J8): Serial Bus Address Configuration Pin. On any given I2C/SMBus serial bus segment, every device must have its own unique slave address. If this pin is left open, the LTM4664A powers up to a slave address set by MFR_ADDRESS[6:0] (see Table  4). The factory-default setting is 0x4F (hexadecimal), i.e., 1001111b (industry standard convention is used throughout this document: 7-bit slave addressing). The lower four bits of the LTM4664A’s slave address can be altered from the NVM-set value by connecting a resistor from this pin to SGND. Minimize capacitance—especially when the pin is left open—to assure accurate detection of the pin state. See 4:1 Divider Application Information section. RUN_C0, RUN_C1 (J9, K8 Respectively): Enable Run Input for Channels 0 and 1, respectively. Open-drain input and output. Logic high on these pins enables the respective 22 outputs of the LTM4664A. These open-drain output pins hold the pin low until the LTM4664A is out of reset and VIN3_C1 is detected to exceed VIN_ON. A pull-up resistor to 3.3V is required in the application. The LTM4664A pulls RUN_C0 and/or RUN_C1 low, as appropriate, when a global fault and/or channel-specific fault occurs whose fault response is configured to latch off and cease regulation; issuing a CLEAR_FAULTS command via I2C or power cycling SVIN is necessary to restart the module, in such cases. Do not pull RUN logic high with a low impedance source. Use PGOODS2 and FAULTS2 to sequence on RUN_C0, and RUN_C1 for the dual 25A/30A stage. ALERT (J10): Open-Drain Digital Output. A pull-up resistor to 3.3V is required in the application only if SMBALERT interrupt detection is implemented in one’s SMBus system. VTRIMC0_CFG (K5): Output Voltage Select Pin for VOUTC0, Fine Setting. Works in combination with VOUTC0_CFG to affect the VOUT_COMMAND (and associated output voltage monitoring and protection/fault-detection thresholds) of Channel 0, at SVIN power-up. (See VOUTC0_CFG and the Dual 25A/30A PSM Applications Information section.) Minimize capacitance especially when the pin is left open to assure accurate detection of the pin state. Note that use of RCONFIGs on VOUTC0_CFG/VTRIMC0_CFG can affect the VOUTC0 range setting (MFR_PWM_MODE0 [1]) and loop gain. VDD25 (K6): Internally Generated 2.5V Power Supply Output Pin. Do not load this pin with external current; it is used strictly to bias internal logic and provides current for the internal pull-up resistors connected to the configuration-programming pins. No external decoupling is required. WP (K7): Write Protect Pin, Active High. An internal 10μA current source pulls this pin to VDD33. If WP is open circuit or logic high, only I2C writes to PAGE, OPERATION, CLEAR_FAULTS, MFR_CLEAR_PEAKS and MFR_EE_ UNLOCK are supported. Additionally, Individual faults can be cleared by writing 1b’s to bits of interest in registers prefixed with “STATUS”. If WP is low, I2C writes are unrestricted. Rev. 0 For more information www.analog.com LTM4664A PIN FUNCTIONS FAULT_C0/FAULT_C1 (K10/K9): Digital Programmable FAULT Inputs and Outputs. Open-drain output. A pull-up resistor to 3.3V is required in the application. VINS3_C1, VINS3_C0: (L1-L2, M1-M2), (L12-L13, M12M13): Main power input to channel 0, and channel  1 power stages. Provide sufficient decoupling capacitance in the form of multilayer ceramic capacitors (MLCCs) and low ESR electrolytic (or equivalent) to handle reflected input current ripple from the step-down switching stages. MLCCs should be placed as close to the VINS3 as physically possible. The VINS3_C1 input provides the input power for the INTVCC LDO regulator. See Layout Recommendations in the Dual 25A/30A PSM Applications Information section. VDD33 (L6): Internally Generated 3.3V Power Supply Output Pin. This pin should only be used to provide external current for the pull-up resistors required for FAULT_Cn, SHARE_CLK, and SYNC, and may be used to provide external current for pull-up resistors on RUN_Cn, SDA, SCL, ALERT and PGOOD_Cn. No external decoupling is required. SHARE_CLK (L7): Share_Clock, Bidirectional Open- Drain Clock Sharing Pin. Nominally 100kHz. Used for synchronizing the time base between multiple LTM4664As (and any other Analog Devices products with a SHARE_ CLK pin)—to realize well-defined rail sequencing and rail tracking. Tie the SHARE_CLK pins of all such devices together; all devices with a SHARE_CLK pin will synchronize to the fastest clock. A pull-up resistor to 3.3V is required. SDA (L8): Serial Bus Data Open-Drain Input and Output. A pull-up resistor to 3.3V is required in the application. SCL (L9): Serial Bus Clock Open-Drain Input (Can Be an Input and Output, if Clock Stretching is enabled). A pull-up resistor to 3.3V is required in the application for digital communication to the SMBus master(s) that nominally drive this clock. The LTM4664A will never encounter scenarios where it would need to engage clock stretching unless SCL communication speeds exceed 100kHz—and even then, LTM4664A will not clock stretch unless clock stretching is enabled by means of setting MFR_CONFIG_ ALL[1] = 1b. The factory-default NVM configuration setting has MFR_CONFIG_ALL [1] = 0b: clock stretching disabled. If communication on the bus at clock speeds above 100kHz is required, the user’s SMBus master(s) needs to implement clock stretching support to assure solid serial bus communications, and only then should MFR_CONFIG_ALL [1] be set to 1b. When clock stretching is enabled, SCL becomes a bidirectional, open-drain output pin on LTM4664A. TSNS_C0a, TSNS_C0b (L10 and T16, Respectively): Channel 0 Temperature Excitation/Measurement and Thermal Sensor Pins, respectively. Connect TSNS_C0a to TSNS_C0b. This allows the LTM4664A to monitor the Power Stage Temperature of Channel 0. SYNC (M8): External Clock Synchronization Input and Open-Drain Output Pin. If an external clock is present at this pin, the switching frequency will be synchronized to the external clock. If clock master mode is enabled, this pin will pull low at the switching frequency with a 500ns pulse to ground. A resistor pull-up to 3.3V is required in the application if the LTM4664A is the master. SGND_C0_C1 (M9, N8-N9): SGND_C0_C1 is the signal ground return path of the dual 25A/30A control. SGND_C0_ C1 is not internally connected to GND. Connect SGND_C0_C1 to GND at the A9, B9, and C9 pins that is close to the output capacitor ground connections. See recommended layout. TSNS_C1a, TSNS_C1b (M10 and T1, Respectively): Channel 1 Temperature Excitation/Measurement and Thermal Sensor Pins, respectively. In most applications, connect TSNS_C1a to TSNS_C1b. This allows the LTM4664A to monitor the Power Stage Temperature of Channel 1. See the Applications section. PWM_C0, PWM_C1 (M15, L4): PWM drive signal to Channel 0, Channel 1 power stage. Utilized for debugging or monitoring purposes. PHFLT_C0, PHFLT_C1 (M16, L5): Thermal Warning for Channel 0 and Channel 1. When the thermal protection threshold is tripped, the PHFLT_Cn pin is being pulled low. The power stage does not shut off, and is only a thermal monitor. These pins are internally pulled up to 3.3V through 10k resistor. COMP_0b/COMP_1b (N10/ M7): Current Control Threshold and Error Amplifier Compensation Nodes. Each associated channel’s current comparator tripping threshold increases with its Comp voltage. Each channel has a 22pF to SGND. Rev. 0 For more information www.analog.com 23 LTM4664A PIN FUNCTIONS VOSNS–_C1 (N6): Channel 1 Negative Differential. Voltage Sense Input. See VOSNS+_C1. VOSNS+_C1 (P6): Channel 1 Positive Differential Voltage Sense Input. Together, VOSNS+_C1 and VOSNS–_C1 serve to kelvin sense the VOUTC1 output voltage at VOUTC1’s point of load (POL) and provide the differential feedback signal directly to Channel 1’s feedback loop. Command VOUTC1’s target regulation voltage by serial bus. Its initial command value at VINS3 power-up is dictated by NVM (non-volatile memory) contents (factory default: 1.000V)—or, optionally, may be set by configuration resistors; see VOUTC1_ CFG and the 4:1 Divider Application Information section. IN– (P10): Negative Current Sense Amplifier Input. If the input current sense amplifier is not used, this pin must be shorted to the IN+ and VIN3 pins. See 4:1 Divider Application Information section for detail about the input current sensing. COMP_0a/COMP_1a (P11/M6): Loop Compensation Nodes. The internal PWM loop compensation resistors RCOMPn of the LTM4664A can be adjusted using bit [4:0] of the MFR_PWM_COMP command. The transconductance of the LTM4664A PWM error amplifier can be adjusted using bit [7:5] of the MFR_PWM_COMP command. These two loop compensation parameters can be programmed when device is in operation. Refer to the Programmable Loop Compensation subsection in the 4:1 Divider Application Information section for further details. See MFR_PWM_COMP section. VOSNS–_C0: (P12): Channel 0 Negative Differential Voltage Sense Input. See VOSNS+_C0. GL_C0, GL_C1 (P16, P5): Bottom MOSFET gate drive in the Channel 0 power stage, Channel 1 power stage. Utilized for debugging or monitoring purposes. INTVCC (R7): Internal Regulator, 5.5V output. When operating the VINS3 from 7V ≤ VINS3 ≤ 16V, a LDO generates INTVCC from VINS3_C1 to bias internal control circuits and the MOSFET drivers of the dual 25A/30A power supply. An external 2.2µF ceramic decoupling is required. INTVCC is regulated regardless of the RUN_Cn pin state. 24 EXTVCC (R8): External Power Input to an Internal Switch Connected to INTVCC. This switch closes and supplies the IC power, bypassing the internal regulator whenever EXTVCC is higher than 4.7V and VIN is higher than 7V. EXTVCC also powers up VDD33 when EXTVCC is higher than 4.7V and INTVCC is lower than 3.8V. Do not exceed 6V on this pin. Decouple this pin to PGND with a minimum of 4.7μF low ESR tantalum or ceramic capacitor. If the EXTVCC pin is not used to power INTVCC, the EXTVCC pin must be tied GND. Its recommended to use this pin if a bias is available to reduce power loss. IN+ (R10): Positive Current Sense Amplifier Input. If the input current sense amplifier is not used, this pin must be shorted to the IN– and VINS3 pins. See 4:1 Divider Application Information section for detail about the input current sensing. PGOOD_C0/PGOOD_C1 (R11/N5): Power Good Indicator Outputs. Open-drain logic output that is pulled to ground when the output exceeds the UV and OV regulation window. The output is deglitched by an internal 100μs filter. A pull-up resistor to 3.3V is required in the application. VOSNS+_C0: (R12) Channel 0 Positive Differential Voltage Sense Input. Together, VOSNS+_C0 and VOSNS–_C0 serve to kelvin-sense the VOUTC0 output voltage at VOUTC0’s point of load (POL) and provide the differential feedback signal directly to Channel 0’s feedback loop. Command VOUTC0’s target regulation voltage by serial bus. Its initial command value at VINS3 power-up is dictated by NVM (non-volatile memory) contents (factory default: 1.000V)—or, optionally, may be set by configuration resistors; see VOUTC0_ CFG and the 4:1 Divider Application Information section. SWC0, SWC1 (T10-T13), (T4-T7): Switching Node of Channel 0 and Channel 1. Used for test purposes or EMI snubbing. Rev. 0 For more information www.analog.com 100k INTVCCS1 10k PGOODS1 VOUT1 36.4k 100kHz 4.53k 0.068µF 100k FAULTS1 PGOODS1 UVS1 1V LEVEL D4 LEVEL D3 FROM OVER CURRENT, VOUT1_ SENSE1 VINS1_SENSE, INTVCC, AND TEMP FAULTS HYSTERESIS 100mV VOUT1 LEVEL DR2 LEVEL DR1 50mA 95mA CVF RVF VINS1 VOUT1_SENSE GATE DRIVE SECTION TIMERS1 ANTI-SHOOT THROUGH CONTROL LOGIC R2 500k VSENSE FILTER R3 500k ON/OFF 1µA ~ 5µA VINS1_SENSE RUNS1 FREQS1 VINS1 HYS_PRGMS1 Vhys_prgm VOUT1_SENSE For more information www.analog.com G4 G3 G2 M4 M3 M2 M1 STAGE 1 G1 1µF VIN 48V 39V 1.74k CVOUT1 10µF 50V ×3 24V RSENSE 10mΩ 0.1µF CFLY1 7.5k 16.2k 48V 49.9k USE 100V RESISTOR OVP_SET 10µF CFLY2 ×8 50V 10µF ×8 25V 5.1V VOUT2_SET SECONDARY OVP PROTECTION CIN 2.2µF 100V ×2 SET VOUT2_SET POINT AT 16V 4.7µF 12V VINS1 LDO GND SW2 VOUT1 SW1 VINS1 RSF INSNSS1– ISENSE FILTER 24V NPN 49.9k 12V CIN2 10µF 50V ×2 VINS2 LDO GND SW4 TO CIRCUIT BREAKER OVP_TRIP CVOUT2 10µF 25V ×4 VOUT2 SW3 VINS2 INSNSS2– ISENSE FILTER INSNSS2+ INTVCCS2 4.7µF G8 G7 G6 G5 0.22µF INTVCC 1µF 12V EXTVCC2 LDO DR8 DR7 DR6 DR5 EXTVCCS2 EXTVCC2>6.5V AND VINS2>7V M8 M7 M6 M5 50mV THRESHOLD PRE-CHARGE CHARGE BALANCE ISENSE– OVERCURRENT ISENSE+ COMPARATOR STAGE 2 INTVCCS2 RSF CSF Figure 1. Simplified LTM4664A 4:1 Divider Block Diagram INTVCCS1 EXTVCCS1 INTVCCS1 EXTVCC1>6.5V AND VINS1>7V DR4 DR3 DR2 DR1 EXTVCC1 LDO 0.22µF INTVCC1 12V Isense- PRE-CHARGE CHARGE BALANCE 50mV THRESHOLD OVERCURRENT ISENSE+ COMPARATOR INSNSS1+ CSF HYSTERESIS 100mV GATE DRIVE SECTION 1V VINS2 4664A BD01 FAULTS2 PGOODS2 UVS2 TIMERS2 ON/OFF RUNS2 FREQS2 HYS_PRGMS2 Vhys_prgm VOUT2_SENSE 1µA ~ 5µA VINS2_SENSE ANTI-SHOOT THROUGH CONTROL LOGIC R18 500k R17 500k FROM OVER CURRENT, VOUT2_SENSE1 VINS2_SENSE, INTVCC, AND TEMP FAULTS LEVEL D8 LEVEL D7 VINS2F VSENSE FILTER VOUT2_SENSE VOUT2 LEVEL DR6 LEVEL DR5 50mA 95mA RVF1 CVF VINS2 100k PGOODS2 10k VOUT2 0.068µF PGOODS1 60.4k 200kHz 100k LTM4664A 4:1 DIVIDER BLOCK DIAGRAM Rev. 0 25 CSNUB0 RSNUB0 SWC0 GL_C0 GND SGND_C0, C1 COUT1 For more information www.analog.com 10k VDD33 3.3V- TOLERANT PULL UP NOT SHOWN PGOODS2 COMP_0a COMP_0b VOSNS–_C0 SHARE_CLK FAULT_C1 FAULT_C0 RUN_C1 RUN_C0 WP ALERT SDA SCL CCOMPL PGOOD_C0 CCOMPH CLOAD0 5.5V- TOLERANT PULL UP NOT SHOWN LOAD0 VOSNS _C0 + TSNS_C0a READ_VOUT0, MFR_VOUT_PEAK, READ_ IOUT0) TSNS_C0b (VOUTC0 TELEMETRY: COUT2 VOUTC0 ADJ TO 1.5V MAX UP TO 25A, 30A UP TO 1.2VOUT VOUTC0 OPTIONAL SNUBBER PHFLT_C0 PWM_C0 UVLO ROM PROGRAM DIGITAL ENGINE, MAIN CONTROL VDD33 COMPARE PROG RCOMP EA0 EXTVCC 2µA TEMP MUX DIE TEMP SENSE SINC3 SPI MASTER SPI SLAVE ADC 10:1 MUX EEPROM SETPOINT, UV, OV, ILIM DACs RAM PWMC1 32µA READ_TEMPERATURE0 VBE SENSING PWMC0 AND POWER CONTROL LOGIC) UV/OV MONITORS, VCO AND PLL, MOSFET DRIVERS LINEAR REGULATORS, DACs, ADC, INTVCC GL_C1 PROG GM 32MHz OSC SYNC DRIVER MFR_PWM_COMP EA1 IOUT1 SENSE CCM CH1 I SIGNAL DRMOS BLK C1 DRIVERS LOGIC 2.2µF VDD33 330nH OVER TEMP MONITOR (140°C) REMOTE SENSE VDD33 14.3k 2.5V 2.2µF 4664A BD2 22pF 2.2µF READ_TEMPERATURE1 0.01µF TSNS1 CHANNEL 1 TEMP DRMOS C1 BOTTOM GATE MONITOR PROG RCOMP CONFIG DETECT X1 DCR SENSE Z OTM 10k VDD33 0.22µF VINS3_C1 Figure 2. LTM4664A PSM Section Dual Channel 25A/30A PSM Block Diagram CHANNEL TIMING MANAGEMENT PROG GM POWER MANAGEMENT DIGITAL SECTION 22pF X1 POWER CONTROL ANALOG SECTION 0.22µF 2.2µF ( CURRENT MODE PWM CNTL LOOPS, SVIN CHIP POWER IOUT0 SENSE CCM CH0 ISIGNAL DRMOS BLK C0 DRIVERS GL_C0 LOGIC INTVCC MFR_PWM_COMP OTM DCR SENSE Z 330nH 10k VDD33 I2C BASED SMBus INTERFACE WITH PMBus COMMANDS (10kHz TO 400kHz COMPATIBLE) 10µA VDD33 REMOTE SENSE READ_TEMPERATURE 0 0.01µF TSNS0 CHANNEL 0 TEMP DRMOS C0 BOTTOM GATE MONITOR OVER TEMP MONITOR (140°C) IIN READBACK 2.2µF 0.1µF READ_VIN, READ_VIN_PEAK INPUT CURRENT/ICHIP ( READ_IIN, MFR_READ_IIN_PEAK) PROG A 0.22µF VIN TELEMETRY: MFR_READ_ICHIP IIN Ω 1Ω VINS3 INTVCC ICHIP VINS3_C1 VINS3_C0 VIN CIN3 VOUTC0 IN– VOUTC1 IN+ IOUTC0 CIN2 IOUTC1 CIN1 TEMP RSENSE PWM0 26 PWM1 VOUT2 12V OPTIONAL SNUBBER COUT4 VOUTC1_CFG VOUTC0_CFG VTRIMC1_CFG VTRIMC0_CFG CONFIG RESISTORS NOT SHOWN NOT SHOWN CCOMPL CLOAD1 READ_IOUT1 3.3V– TOLERANT PULL UP FSWPH_CFG ASEL VDD25 SYNC PGOOD_C1 COMP_1a COMP_1b VOSNS–_C1 TSNS_C1a VOSNS+_C1 LOAD1 CCOMPH READ_VOUT1, MFR_VOUT_PEAK TSNS_C1b (VOUTC1_TELEMETRY: COUT3 VOUTC1 ADJ TO 1.5V MAX UP TO 25A, 30A UP TO 1.2VOUT SGND_CO_C1 GND VOUTC1 GL_C1 SWC1 PHFLT_C1 PWM_C1 CSNUB1 RSNUB1 LTM4664A DUAL 25A/30A POWER SYSTEM MANAGEMENT (PSM) BLOCK DIAGRAM Rev. 0 LTM4664A 4:1 DIVIDER OPERATION 4:1 DIVIDER DESCRIPTION The LTM4664A incorporates a high performance 4:1 switched capacitor divider that divides down the input voltage by a factor of four over an input voltage range of 30V to 58V. This 4:1 divider then powers a dual 25A/30A PMBus compliant core power rails that can regulate from 0.5V to 1.5V at up to 25A, per channel—and from 0.5V to 1.2V at up to 30A per channel. The LTM4664A will convert this high input range down directly to the low output voltages. MAIN CONTROL The LTM4664A internal 4:1 divider utilizes two constant frequency, open loop switched capacitor/charge pump stages for high voltage step down. The conversion efficiency is very high at ~ 99% for stage 1, and ~98.6% efficient for stage 2. Refer to Figure 1 for the block diagram. In stage 1 steady state operation, the N-channel MOSFETs M1 and M3 are turned on and off in the same phase with around 50% duty cycle at a pre-programmed 100kHz switching frequency. The N-channel MOSFETs M2 and M4 are turned on and off complementary to MOSFETs M1 and M3. The gate drive waveforms are shown in Figure 3. During phase 1, M1 and M3 are on and the flying capacitor CFLY1 is in series with COUT1. During phase 2, M2 and M4 are on and CFLY1 is in parallel with COUT1. The VOUT1 VGS M1 TS M2 M3 M4 PHASE 2 The VOUT2 (VINS1/4) is connected to the VINS3_Cn which is the inputs to the dual 25A/30A PMBus channels. This will be discussed in more detail in the dual 25A/30A operation section. There is a secondary fault protection comparator circuit that can be used to monitor VOUT2 for over voltage. This will be discussed in more detail in the application section. The LTM4664A can operate over a 30V to 58V input range that does have abrupt input voltage changes that move quicker than a few milliseconds after reaching steady state. See the window comparator section. INTVCCS1,2/EXTVCCS1,2 POWER ~ 50% DUTY CYCLE PHASE 1 voltage is always close to half of the top voltage at the drain of MOSFET M1 (refer to GND pin) and in steady state and it is not sensitive to variable loads due to the very low impedance at its output. Stage 2 operates exactly the same way, the N-channel MOSFETs M5 and M7 are turned on and off in the same phase with around 50% duty cycle at a pre-programmed 300kHz switching frequency. The N-channel MOSFETs M6 and M8 are turned on and off complementary to MOSFETs M5 and M7. The main input voltage rail is connected to VINS1, and VOUT1 is connected directly into the VINS2. The LTM4664A front end divider stages do not regulate the output voltage with a closedloop feedback system. However, it stops switching when fault conditions occur, such as VOUT pin overvoltage or undervoltage, an overcurrent event, or an over temperature protection event. PHASE 1 PHASE 2 4664A F03 Power for the quad N-channel MOSFET drivers and most other internal circuitry is derived from the INTVCCSn pin. Normally an internal 5.5V linear regulator supplies INTVCCS1, 2 power from either VINS1 or VINS2 as indicated in Figure 1. Both of these input supplies have high input voltage, and increases power loss due to the LDO drop. An optional external voltage source on EXTVCCS1,2 pin enables a second 5.5V linear regulator and supplies INTVCCS1,2 power from the EXTVCCS1,2 pin. To enable this more efficient second regulator, VINS1,2 has to be higher than 7V and the EXTVCCS1,2 pin voltage has to be higher than 6.5V. Do not exceed 40V on the EXTVCCSn pin. Figure 1 shows the VOUT2 supply (12V) connected to both EXTVCCS1 and EXTVCCS2 to lower power loss in the LDO after startup. Figure 3. Stage 1 MOSFET Switching Waveforms Rev. 0 For more information www.analog.com 27 LTM4664A 4:1 DIVIDER OPERATION Each of these can supply a peak current of 150mA. No matter what type of bulk capacitor is used, an additional 0.1μF ceramic capacitor placed directly adjacent to the INTVCCSn and GND pins is highly recommended. Good bypassing is needed to supply the high transient currents required by the MOSFET gate drivers. These high input voltages along with the power MOSFETs being driven at high frequencies may cause the maximum junction temperature rating for the LTM4664A to be exceeded. The INTVCCSn current, which is dominated by the gate charge current, may be supplied by either the 5.5V linear regulator from VINSn or the linear regulator from EXTVCCSn. When the voltage on the EXTVCCSn pin is less than 6.5V, the linear regulator from VINSn is enabled. Power dissipation for the internal controller in this case is highest and is equal to VINSn • IINTVCCSn. The gate charge current is dependent on operating frequency. This is why it is highly recommended to use the VOUT2 voltage to supply power to the EXTVCCS1,2 pins. START-UP AND SHUTDOWN The LTM4664A divider stages are in shutdown mode when their RUNS pins are pulled down and lower than 1.1V. In this mode, most internal circuitry is turned off including the INTVCCS1,2 regulators and the 4:1 divider consumes less than 200μA current per stage. All gates drives are actively pulled low to turn off the external power MOSFETs in shutdown. Releasing RUNS1,2 allows an internal 1μA current to pull up these pins and enable the controller stage. Once the RUNS1,2 pin raises above 1.22V, an additional 5μA is flowing out of the respective pin. Alternately, the RUNS pin may be externally pulled up or driven directly by logic. Do not exceed the Absolute Maximum Rating of 6V on these pins. After RUNS1,2 pin is released and the INTVCCS1,2 voltage passes UVLO, then that particular stage starts up and monitors the VINn and VOUTn voltage continuously. The LTM4664A divider stages start switching only if the VOUTn voltage is close to half of the VINSn voltage or both VOUTn and VINSn voltages are close to GND. In voltage divider applications, VOUT1,2 is pre-balanced to half the VINS1,2 voltage and the LTM4664A divider stages may start up with capacitors at different initial conditions and balancing will be invoked if necessary. 28 FAULT PROTECTION AND THERMAL SHUTDOWN The LTM4664A divider stages monitor system voltage, current and temperature for faults. The stage 1 or 2 stops switching and pulls down its FAULT pin when fault conditions occur. To clear voltage faults, the VOUTn pin voltage has to be within the programmed window around half of the VINSn voltage or the VINSn and VOUTSn voltages must be lower than 1V and 0.5V respectively. To clear current faults, the voltage drop from INSNSn+ pin to INSNSn– pin has to be lower than 50mV. To clear temperature faults, the IC temperature has to be lower than 165°C. The FAULT pin is allowed to be pulled up by external resistors to voltages up to 60V. It can also be used to control disconnect FETs that isolates the input and output during fault conditions. See Figure 1 block diagram. HIGH SIDE CURRENT SENSING For over current protection, the LTM4664A uses a sensing resistor RSENSE to monitor the current. The sensing resistor has to be placed at the drain of the very top MOSFET M1. See Typical Application section for examples. In most applications, the current through the sensing resistor is a pulse current and the peak value is much higher than the average load current. An internal RC filter on the ISENSE– pin, with a time constant lower than switching frequency, is used to set the precision average current protection. If over current protection is not desired, short the ISENSE+ and ISENSE– pins together and connect them to the drain of top MOSFET M1 directly. This is done in stage 2 since stage 1 already monitors for current faults. See Figure 1. FREQUENCY SELECTION The selection of switching frequency is a trade-off between efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching losses, but requires larger capacitance to maintain low output ripple voltage and low output impedance. The FREQSn pin can be used to program the controller’s operating frequency from 100kHz to 1MHz. There is a precision 10μA current flowing out of the FREQSn pin, so the user can program the controller’s switching frequency Rev. 0 For more information www.analog.com LTM4664A 4:1 DIVIDER OPERATION with a single resistor to GND. The voltage on the FREQSn pin is equal to the resistance multiplied by 10μA current (e.g. the voltage is 1V with a 100k resistor from the FREQSn pin to GND). A curve is provided below showing the relationship between the voltages on the FREQSn pin and switching frequency. Stage 1 is operated at 100kHz, and Stage 2 is operated at 200kHz for optimal efficiency. See Figure 4. SWITCHING FREQUENCY (kHz) 1400 1200 1000 800 600 400 200 0 0 0.5 1.5 1 2 FREQ PIN VOLTAGE (V) 2.5 4664A F04 Figure 4. Relationship Between Switching Frequency and Voltage at FREQ Pin fSW (kHz) = RFREQ (kΩ) • 8 – 317kHz POWER GOOD AND UV (PGOODSn AND UVSn PINS) When the UVSn pin voltage is lower than 1V, the PGOODSn pin is pulled low. The PGOODSn pin is also pulled low when the RUNSn pin is low or when the LTM4664A divider stages are starting up. The PGOODSn pin is released only when the LTM4664A stage is switching and UVSn pin is higher than 1V. The PGOODSn pin will flag power bad immediately when the UVSn pin is low. However, there is an internal 20μs power good mask and 100mV hysteresis when UVSn is higher than 1V. The PGOODSn pin is pulled up by external resistor to INTVCC. The UVS1 pin is used to monitor the VOUT1 level for proper regulation, the PGOODS1 signal is used to sequence on the stage 2's RUNS2 pin. Then PGOODS2 is used to sequence on the downstream dual 25A/30A regulators. Proper setup on the UV pin to set a specific regulation point will release the PGOODn pin when the output voltage is at that value. See Figure 1 block diagram. ADDITIONAL OVERVOLTAGE PROTECTION The OVP_SET, VOUT2_SET, and OVP_TRIP pins can be used to monitor the VOUT2 voltage for an overvoltage fault. These pins can be used in conjunction with the circuit in Figure 46 to provide a secondary OVP protection in and above the 4:1 divider fault protection. This feature can be used to trip off the input power, and further protect the low voltage outputs. Rev. 0 For more information www.analog.com 29 LTM4664A 4:1 DIVIDER APPLICATION INFORMATION A Typical Application in the Figure 1 block diagram shows the 4:1 voltage divider circuit. For the 1st stage voltage divider, the VINS1 input voltage is at the drain of very top MOSFET M1 and the output voltage is at the VOUT1 pin which is connected to the source of MOSFET M2 and the drain of MOSFET M3. The output voltage is around half of the input voltage in steady state. For the 2nd stage voltage divider, the VINS2 input voltage is at the drain of very top MOSFET M5 and the output voltage is at the VOUT2 pin which is connected to the source of MOSFET M6 and the drain of MOSFET M7. This completes the 4:1 divider. When switches M2 and M4 are on or it is limited by the power MOSFET saturation current in the 1st stage, and M6 and M8 in the 2nd stage: For divider applications, if the load current is applied before startup or heavy resistive loads are connected to the VOUTn pin, the divider stages may not start up due to the limited drive current of the pre-balance circuit. The LTM4664A provides a proprietary pre-balance method to minimize the inrush charging current in voltage divider applications. The LTM4664A controller detects the VOUTn pin voltage before switching and compares it with the VINSn /2 internally. If the VOUTn pin voltage is much lower than the VINSn /2, a current source will source 95mA current to the VOUTn pin to pull the VOUTn pin up. If the VOUTn pin voltage is much higher than the VINSn /2, another current source will sink 50mA from VOUTn pin to pull the VOUTn pin down. Therefore the PGOODS1 signal is used to sequence on stage 2 RUN2 pin, and the PGOODS2 pin is used to stage on the dual 25A/30A regulator. VOLTAGE DIVIDER PRE-BALANCE BEFORE SWITCHING In voltage divider applications, the VOUTn voltage should be always close to VINSn /2 in the steady state. The voltages on the flying capacitors (CFLYn) and VOUTn capacitors are all very close to each other and equal to the half of the input voltage. The charging inrush current is minimized during each switching cycle because the voltage difference between capacitors is small. However, without a special charging method such as the LTM4664A controller pre-charging circuitry, during start-up or fault conditions such as VOUTn short to GND, the difference between capacitors can be large and huge charging currents may be large enough to cause very large MOSFETs currents. When switches M1 and M3 are on in the 1st stage, and M5 and M7 are on in the 2nd stage. Ideally, the inrush charge current is: I= VINSn – VCFLYn – VOUTn RONMn +RONMn 30 I= VCFLYn – VOUTn RONMn +RONMn With very low RDS(ON) of the power MOSFETs, the inrush charge current could easily achieve several hundreds of Amperes which can be higher than the MOSFET’s Safe Operating Area (SOA). If the VOUTn pin voltage is close to VINSn/2 and within the pre-programmed window, both current sources are disabled and the divider stages start switching. After 68 switching cycles and the VOUTn pin is still within the window, the FAULTSn pin is released. For the 4:1 voltage divider with pre-balance startup, the LTM4664A assumes no load current or very small load current (less than 50mA) at the VOUTn (output) otherwise the VOUTn cannot reach VINSn /2 and LTM4664A never starts up. This no load condition can be achieved by connecting the PGOODn pin to the enable pins of the following electrical loads. If load current cannot be controlled off such as resistive loads, a disconnected FETs is required to disconnect the load to the VOUTn during startup as shown in the typical applications. The input power source can operate over the 30V to 58V range, but the supply variation needs to be constrained to move much slower than the switching frequency and not exceed the hysteresis set by the HYS_PRGMSn pin. Large fast voltage excursions changes will force the 4:1 divider into pre-balance phase. Rev. 0 For more information www.analog.com LTM4664A 4:1 DIVIDER APPLICATION INFORMATION OVERCURRENT PROTECTION The LTM4664A 4:1 divider provides overcurrent protection through a sensing resistor placed on the high voltage side. A precision rail to rail comparator monitors the differential voltage between INSNSSn + pin and INSNSSn – pin which are Kelvin connected to a sensing resistor. Whenever the INSNSSn + pin voltage is 50mV higher than INSNSSn – pin voltage, overcurrent fault is triggered and the FAULTSn pin is pulled down to ground. At the same time the divider stage stops switching and starts retry mode based on the timer pin setup. The overcurrent fault will be cleared when the TIMERSn pin voltage reaches 4V and the voltage across the sensing resistor is less than 50mV. The current through the sensing resistor is a pulse current during charging/discharging of the flying capacitors, which may result a voltage higher than the 50mV threshold at heavy loads. To prevent the inrush current from falsely triggering the overcurrent protection, an RC filter is required at the INSNSSn+ pin and INSNSSn– The RC filter timer constant has to be larger than a switching period. Typically a 100Ω and 0.1μF filter is good for most of applications, and this filter is already included inside the LTM4664A. The current limit can be selected by choosing different sense resistor values. For example, 10mΩ sensing resistor sets current limit at 50mV/10mΩ = 5A ideally. Due to the switching ripple, the actual current limit is always lower than the ideal case. In real circuits, the current limit is around 4.2A with the 0.1μF/100Ω filter and 200kHz switching frequency. If overcurrent protection is not used, short INSNSSn+ pin and INSNSSn– pin together and connect them to the drain of the top as shown in Figure 1 stage 2. Stage 2 current limit is not usually necessary since stage 1 already has it implemented. Also the dual 25A/30A regulators have overcurrent protection discussed later in the data sheet. WINDOW COMPARATOR PROGRAMMING In normal operation, VOUTn voltage should be always close to half of the VINSn voltage. A floating window comparator monitors the voltage on the VOUTn pin and compares it with VINSn /2. The window hysteresis voltage can be programmed and is equal to the voltage at the HYS_PRGMSn pin. There is a precision 10μA current flowing out of HYS_PRGMSn pin. A single resistor from HYS_PRGMSn pin to GND sets the HYS_PRGMSn pin voltage, which equals the resistor value multiplied by 10μA current (e.g. the voltage is 1V with a 100k resistor from the HYS_PRGMSn pin to GND). With a 100k resistor on the HYS_PRGMSn pin, the VINSn /2 voltage has to be within (VOUTn ± 1V) window during startup and normal operation, otherwise a fault is triggered and the LTM4664A divider stages stop switching. The window hysteresis voltage can be linearly programmed from 0.3V to 2.4V with different resistor values on HYS_PRGMNSn pin. If the HYS_PRGMSn pin is tied to INTVCC, a default 0.8V hysteresis window is applied internally. The hysteresis window voltage has to be programmed large enough to tolerate the VOUTn pin voltage ripple and voltage drop at maximum load conditions. See Figure 5. Small internal RC filters can be used on these two pins to reject noise higher than the switching frequency. 2.5 VOUTn_SENSE WINDOW VOLTAGE (V) Usually front end circuit breakers control the rate change and slew rate on the main input power which will eliminate this problem. As long as the input supply moves much slower than the operating frequency of the 4:1 divider, then the regulator will be able to balance without a need to pre-balance. 2 1.5 1 0.5 0 0 1 3 2 VHYS_PRGM (V) 4 5 4664A F05 Figure 5. Relationship Between HYS_PRGM Pin Voltage and VOUTn_SENSE Window Comparator Voltage Rev. 0 For more information www.analog.com 31 LTM4664A 4:1 DIVIDER APPLICATION INFORMATION EFFECTIVE OPEN LOOP OUTPUT RESISTANCE AND LOAD REGULATION The LTM4664A divider stages do not regulate the output voltage through a closed loop feedback system. However, the output voltage is not sensitive to load conditions due to the low output resistance when it is operating with a certain quantity of flying capacitors and high switching frequency. The Thevenin equivalent circuit of voltage divider circuit is shown in the Figure 6. RTH VIN UNDERVOLTAGE LOCKOUT G1 SW1 G2 MID CFLY VIN/2 CMID G3 CMID SW3 G4 4664A F06 Figure 6. When duty cycle is around 50%: – ROUT = 1 4f R The LTM4664A divider stages have a precision UVLO comparator constantly monitoring the INTVCCSn voltage to ensure that an adequate gate drive voltage is present. It locks out the switching action when INTVCCSn is below 4.9V. To prevent oscillation when there is a distuSrbance on the INTVCCSn, the UVLO comparator has 200mV of precision hysteresis. Another way to detect an under voltage condition is to monitor the input supply. Because the RUN pin has a precision turn-on reference of 1.22V, one can use a resistor divider to the VINSn to turn on the stage when the input voltage is high enough. An extra 5μA of current flows out of the RUN pin once the RUNSn pin voltage passes 1.22V. One can program the hysteresis of the RUNSn comparator by adjusting the values of the resistive divider. C 1+e S DS(ON) FLY 1 ⎛ ⎞ – ⎜ 4fS RDS(ON)C FLY ⎟ 4fSC FLY ⎜1– e ⎟ ⎜ ⎟ ⎝ ⎠ FAULT RESPONSE AND TIMER PROGRAMMING The LTM4664A divider stages stop switching and pull the FAULTSn pins low during fault conditions. A capacitor connected from the TIMERSn pin to GND sets retry time to start-up if fault conditions are removed. The typical waveform on TIMERSn pin during fault condition is shown in Figure 7. Where: fS is the switching frequency. CFLY is the flying capacitor. RDS(ON) is the on resistance of one MOSFET. At low switching frequencies, RTH = 1/(4fS CFLY). As frequency increases, the RTH will finally approach 2RDS(ON). In high power applications, it is suggested to select the switching frequency around 1/(16CFLY RDS(ON)) or higher for decent load regulation and efficiency. At heavy load 32 conditions, the output voltage will drop from VINSn /2 by RTH • ILOAD. In many applications, multi-layer ceramic capacitors (MLCC) are selected as flying capacitors. The voltage coefficients of MLCC capacitors strongly depend on the type and size of capacitors. Normally larger size X7R MLCC capacitors are better than X5R in terms of voltage coefficient. The capacitance still drops 20% to 30% capacitance with high DC bias voltage. Capacitance derating needs to be considered when estimating the output resistance of the switched capacitor circuits. After the FAULTSn pin is pulled low, a 3.5μA pull-up current flows out of TIMER pin and starts to charge the TIMERSn capacitor. The pull-up current increases to 7μA when then TIMERSn pin voltage is higher than 0.5V and back to 3.5μA when the TIMERSn pin voltage is higher than 1.2V. The TIMERSn pin will be strongly pulled down whenever the fault conditions are removed or the TIMERSn pin voltage is higher than 4V. When the TIMERSn pin voltage Rev. 0 For more information www.analog.com LTM4664A 4:1 DIVIDER APPLICATION INFORMATION 3.5µA CHARGE TIMER PIN 3.5µA CHARGE TIMER PIN 4V 7µA CHARGE TIMER PIN 1.2V 0.5V FAULT LOW FAULT RELEASE PRE-BALANCE TIME 4664A F07 TURN ON TIME Figure 7. Timer Behavior During Fault or Startup is between 0.5V and 1.2V, the internal pre-balance circuit will source or sink current to the VOUTn pin and regulate the VOUTn pin to VINSn /2 with around 95mA/50mA capability. The pre-balance time can be calculated based on the capacitor CTIMERSn on the TIMERSn pin: TPRE-BALANCE = CTIMER • 0.7V/7μA, so the pre-balance time is 100ms/μF (e.g. the pre-balance time is 10ms with 0.1μF CTIMER). For voltage divider applications, if the flying capacitor CFLYn and the VOUTn capacitor are very large and input voltage is high, it may take several pre-balance time periods to pre-balance the VOUTn pin to VINSn /2 with a fixed CTIMER. A longer start-up time is expected. Assuming zero initial conditions, the time to charge the capacitors, τcharge can be estimated from the equation: Design Example As a design example using LTM4664A divider stages for a the 4:1 divider at 72W, assume VINS1 = 48V (nominal), VINS1 = 60V (maximum), VOUT1 = 24V (nominal), IOUT1 = 3A (maximum) for stage 1. For high power and high voltage applications, always start with a low switching frequency e.g. 100kHz to minimize the switching losses. To set the stage 1 to 100kHz switching frequency, a 36.5k 1% resistor is connected from FREQS1 pin to ground. Set the CFLY1 voltage ripple to be 2% of the output voltage is a good starting point with tradeoff between efficiency and power density. The CFLY1 can be calculated based on the equation below: IOUT1(MAX) = 3A τCharge =(COUT +CFLY )•(VIN / 2 / 93mA) Keep in mind that the approximate capacitor value will be the value at both voltage bias and temperature, this information can be derived from the capacitor data sheet curves. Input/Output Capacitor and Flying Capacitor Selection In high power switched capacitor applications, large AC currents flow through the flying capacitors and input/ output capacitors. Low ESR ceramic capacitors are highly recommended for high power switch capacitor applications. Make sure the maximum RMS capacitor current is within the spec or higher rated capacitors are preferred. Note that capacitor manufacturers’ ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor. CFLY = IOUT1(MAX) 2 • fSW • VCFLY1(RIPPLE) ∼ 31µF = 3A 2 •100kHz • 0.48V Consider the ceramic capacitance derating at 24VDC bias voltage, 8 of 10μF/X7R/50V ceramic capacitors are paralleled as flying capacitors. The 4:1 divider at 72W, assume VINS2 = 24V (nominal), VIN = 30V (maximum), VOUT2 = 12V (nominal), IOUT2 = 6A (maximum) for stage 2. For stage 2 start with a switching frequency of 200kHz to minimize the switching losses. To set the 200kHz switching frequency, a 60.4k 1% resistor is connected from FREQS2 pin to ground. Set the CFLY2 voltage ripple to be 2% of the output voltage is a good starting point with trade-off between efficiency and Rev. 0 For more information www.analog.com 33 LTM4664A 4:1 DIVIDER APPLICATION INFORMATION power density. The CFLY2 can be calculated based on the equation below: IOUT2(MAX) = 6A CFLY = IOUT2(MAX) 2 • fSW • VCFLY2(RIPPLE) ∼ 62µF = 6A 2 • 200kHz • 0.24V The output capacitor selection is similar to the flying capacitor selection. More output capacitors result smaller output voltage ripple. The output capacitor has less than 1/3 the CFLY RMS current, and the output capacitor can be much less than the flying capacitor. Some of output capacitors may be connected between input and output to serve as input capacitors at the same time. However the voltage rating of those capacitors has to be selected based on the input voltage instead of the output voltage. Capacitors to use for 4:1 Divider Consider the ceramic capacitance derating at 12VDC bias voltage, 8 of 10μF/X7R/50V ceramic capacitors are paralleled as flying capacitors. CAPACITOR VENDOR VALUE (μF) VOLTAGE (V) PART NUMBER Murata 10 50 GRM32ER71H106KA12 Consider the ceramic capacitance derating at 24V and 12V DC bias voltage. TDK 10 50 C3225X7R1H106M250AC Murata 22 25 GRM32ER71G226KE15L Taiyo Yuden 22 25 TMK325BJ226MMHT The worst case RMS current may be 40% higher than the maximum output current. So the worst case RMS on each capacitor can be estimated by this equation: IRMS1(MAX) = IOUT1(MAX) • 140% N , N = # of CFLY1 capacitor s in parallel in stage1 0.525A = 3A •1.4 8 Each capacitor is rated for 2A IRMS, no issue IRMS2(MAX) = IOUT2(MAX) • 140% N , N = # of CFLY1 capacitor s in parallel in stage1 1.05A = 6A •1.4 8 Each capacitor is rated for 2A IRMS, no issue 34 Rev. 0 For more information www.analog.com LTM4664A DUAL 25A/30A PSM OPERATION The LTM4664A Power System Management (PSM) includes a highly configurable dual 25A/30A output standalone nonisolated switching mode step-down DC/DC power supply with built-in EEPROM NVM (nonvolatile memory) with ECC and I2C-based PMBus/ SMBus 2-wire serial communication interface capable of 400kHz SCL bus speed. Two output voltages can be regulated (VOUTC0, VOUTC1—collectively, VOUTn) with a few external input and output capacitors and pull-up resistors. Readback telemetry data of input and output voltages and input and output currents, and module temperatures are continually digitized cyclically by an integrated 16-bit ADC (analog-to-digital converter). Many fault thresholds and responses are customizable. Data can be autonomously saved to EEPROM when a fault occurs, and the resulting fault log can be retrieved over I2C at a later time, for analysis. See Figure 2 for Block Diagram. Programmable Input Voltage On and Off Threshold Voltage n Programmable Current Limit per channel n Programmable Switching Frequency n Programmable OV and UV Threshold voltage n Programmable ON and Off Delay Times n Programmable Output Rise/Fall Times n Phase-Locked Loop for Synchronous PolyPhase Operation (2, 3, 4 or 6 Phases) n Nonvolatile Configuration Memory with ECC n Optional External Configuration Resistors for Key Operating Parameters n Optional Timebase Interconnect for Synchronization Between Multiple Controllers n PSM SECTION OVERVIEW, MAJOR FEATURES n Major Features Include: n Stand Along Operation After User Factory Configuration Dedicated Power Good Indicators n PMBus, Version 1.2, 400kHz Compliant Interface n Direct Input and Chip Current Sensing n Programmable Loop Compensation Parameters n TINIT Start-Up Time: 30ms n PWM Synchronization Circuit, (See Frequency and Phasing Section for Details) MFR_ADC_CONTROL for Fast ADC Sampling of One Parameter (as Fast as 8ms) (See PMBus Command for Details) n Fully Differential Output Sensing for Both Channels; VOUT0/VOUT1 Both Programmable Up to 1.5V n Power-Up and Program EEPROM with EXTVCC n Input Voltage Up to 18V n ∆VBE Temperature Sensing n SYNC Contention Circuit (Refer to Frequency and Phase Section for Details) Fault Logging n Programmable Output Voltage The PMBus interface provides access to important power management data during system operation including: Internal Controller Temperature n n n WP Pin to Protect Internal Configuration Internal Power Channel Temperature Average Output Current n Average Output Voltage n Average Input Voltage n Average Input Current n Average Chip Input Current from VIN n Configurable, Latched and Unlatched Individual Fault and Warning Status n Individual channels are accessed through the PMBus using the PAGE command, i.e., PAGE 0 or 1. Fault reporting and shutdown behavior are fully configurable. Two individual FAULT_C0, FAULT_C1 outputs are provided, both of which can be masked independently. n Rev. 0 For more information www.analog.com 35 LTM4664A DUAL 25A/30A PSM OPERATION Three dedicated pins for ALERT, PGOOD_C0/PGOOD_C1 functions are provided. The shutdown operation also allows all faults to be individually masked and can be operated in either unlatched (hiccup) or latched modes. The degradation in EEPROM retention for temperatures >125°C can be approximated by calculating the dimensionless acceleration factor using the following equation: Individual status commands enable fault reporting over the serial bus to identify the specific fault event. Fault or warning detection includes the following: AF = e Output Undervoltage/Overvoltage n Input Undervoltage/Overvoltage n Input and Output Overcurrent n Internal Overtemperature n Communication, Memory or Logic (CML) Fault n EEPROM WITH ECC The LTM4664A PSM dual 25A/30A regulators contain internal EEPROM with ECC (Error Correction Coding) to store user configuration settings and fault log information. EEPROM endurance retention and mass write operation time are specified in the Electrical Characteristics and Absolute Maximum Ratings sections. Write operations above TJ = 85°C are possible although the Electrical Characteristics are not guaranteed and the EEPROM will be degraded. Read operations performed at temperatures between –40°C and 125°C will not degrade the EEPROM. Writing to the EEPROM above 85°C will result in a degradation of retention characteristics. The fault logging function, which is useful in debugging system problems that may occur at high temperatures, only writes to fault log EEPROM locations. If occasional writes to these registers occur above 85°C, the slight degradation in the data retention characteristics of the fault log will not take away from the usefulness of the function. It is recommended that the EEPROM not be written when the die temperature is greater than 85°C. If the die temperature exceeds 130°C, the LTM4664A PSM will disable all EEPROM write operations. All EEPROM write operations will be re-enabled when the die temperature drops below 125°C. (The controller will also disable all the switching when the die temperature exceeds the internal overtemperature fault limit 160°C with a 10°C hysteresis). 36 ⎡⎛ Ea ⎞ ⎛ ⎞⎤ 1 1 – ⎢⎜⎝ ⎟⎠ •⎜ ⎟⎠ ⎥ +273 +273 T T k ⎝ USE STRESS ⎦ ⎣ where: AF = acceleration factor Ea = activation energy = 1.4eV K = 8.617 • 10–5 eV/°K TUSE = 125°C specified junction temperature TSTRESS = actual junction temperature in °C Example: Calculate the effect on retention when operating at a junction temperature of 135°C for 10 hours. TSTRESS = 130°C TUSE = 125°C, –5) • (1/398 – 1/403)] ) AF = e([(1.4/8.617 • 10 = 16.6 The equivalent operating time at 125°C = 16.6 hours. Thus the overall retention of the EEPROM was degraded by 16.6 hours as a result of operating at a junction temperature of 130°C for 10 hours. The effect of the overstress is negligible when compared to the overall EEPROM retention rating of 87,600 hours at a maximum junction temperature of 125°C. The integrity of the entire onboard EEPROM is checked with a CRC calculation each time its data is to be read, such as after a power-on reset or execution of a RESTORE_USER_ ALL command. If a CRC error occurs, the CML bit is set in the STATUS_BYTE and STATUS_WORD commands, the EEPROM CRC Error bit in the STATUS_MFR_SPECIFIC command is set, and the ALERT and RUN pins pulled low (PWM channels off). At that point the device will only respond at special address 0x7C, which is activated only after an invalid CRC has been detected. The chip will also respond at the global addresses 0x5A and 0x5B, but use of these addresses when attempting to recover from a CRC issue is not recommended. All power supply rails associated with either PWM channel of a device reporting an invalid CRC should remain disabled until the issue is resolved. See the application Information section or contact Rev. 0 For more information www.analog.com LTM4664A DUAL 25A/30A PSM OPERATION the factory for details on efficient in-system EEPROM programming, including bulk EEPROM Programming, which the LTM4664A PSM also supports. The LTM4664A PSM contains dual integrated constant frequency current mode control buck regulators (channel 0 and channel 1) whose built-in power MOSFETs are capable of fast switching speed. The factory NVM-default switching frequency clocks SYNC at 350kHz, to which the regulators synchronize their switching frequency. The default phase-interleaving angle between the channels is 180°. A pin-strapping resistor on FSWPH_CFG configures the frequency of the SYNC clock (switching frequency) and the channel phase relationship of the channels to each other and with respect to the falling edge of the SYNC signal. (Most possible combinations of switching frequency and phase-angle assignments are settable by resistor pin programming; see Table 3. Configure the LTM4664A’s PSM NVM to implement settings not available by resistor-pin strapping.) When a FSWPH_CFG pin-strap resistor sets the channel phase relationship of the LTM4664A’s PSM channels, the SYNC clock is not driven by the module; instead, SYNC becomes strictly a high impedance input and channel switching frequency is then synchronized to SYNC provided by an externally-generated clock or sibling LTM4664A with pull-up resistor to VDD33. Switching frequency and phase relationship can be altered via the I2C interface, but only when switching action is off, i.e., when the module is not regulating either output. See the Dual 25A/30A PSM Applications Information section for details. Programmable analog feedback loop compensation for channel 0 and channel 1 is accomplished with a capacitor connection from COMP_C0a, 1a to SGND, and a capacitor from COMP_C0b, 1b to SGND.) The COMP_C0b, 1b pin is for the high frequency gain roll off and is the gm amplifier output that has a programmable range, and the COMP_C0a, 1a pin has the programmable resistor range along with a capacitor to SGND that sets the frequency compensation. See Programmable Loop Compensation section. The LTM4664A dual 25A/30A regulators module have sufficient stability margins and good transient performance with a wide range of output capacitors—even all-ceramic MLCCs. Table 12 provides guidance on input and output capacitors recommended for many common operating conditions along with the programmable compensation settings. The Analog Devices LTpowerCAD tool is available for transient and stability analysis, and experienced users who prefer to adjust the module’s feedback loop compensation parameters can use this tool. POWER-UP AND INITIALIZATION The LTM4664A dual 25A/30A regulators are designed to provide standalone supply sequencing and controlled turn-on and turn-off operation. It operates from a single input supply (4.5V to 16V) while three on-chip linear regulators generate internal 2.5V, 3.3V and 5.5V. The controller configuration is initialized by an internal threshold based UVLO where VIN must be approximately 4V and the 5.5V, 3.3V and 2.5V linear regulators must be within approximately 20% of the regulated values. In addition to the power supply, a PMBus RESTORE_USER_ALL or MFR_RESET command can initialize the part too. The EXTVCC pin is driven by an external regulator to improve efficiency of the circuit and minimize power loss when VINS3 is high. The EXTVCC pin must exceed approximately 4.7V, and VINS3 must exceed approximately 7V before the INTVCC LDO operates from the EXTVCC pin. To minimize application power, the EXTVCC pin can be supplied by a switching regulator. During initialization, the external configuration resistors are identified and/or contents of the NVM are read into the controller’s commands and the power train is held off. The RUN_Cn and FAULT_Cn and PGOOD_Cn are held low. The LTM4664A dual 25A/30A regulators will use the contents of Table 1 thru Table 5 to determine the resistor defined parameters. See the Resistor Configuration section for more details. The resistor configuration pins only control some of the preset values of the controller. The remaining values are programmed in NVM either at the factory or by the user. If the configuration resistors are not inserted or if the ignore RCONFIG bit is asserted (bit 6 of the MFR_CONFIG_ALL configuration command), the LTM4664A PSM will use only the contents of NVM to determine the DC/DC characteristics. The ASEL value read at power-up or reset is always respected unless the pin is open. The ASEL will set the bottom 4LSBs and the MSBs are set by NVM. See the Dual 25A/30A PSM Applications Information section for more details. For more information www.analog.com Rev. 0 37 LTM4664A DUAL 25A/30A PSM OPERATION After the part has initialized, an additional comparator monitors VINS3. The VIN_ON threshold must be exceeded before the output power sequencing can begin. After VIN is initially applied, the part will typically require 70ms to initialize and begin the TON_DELAY timer. The readback of voltages and currents may require an additional 0ms to 90ms. SOFT-START The method of start-up sequencing described below is time-based. The part must enter the run state prior to soft-start. Stage 2 of the 4:1 Divider will release RUN_C0 and RUN_C1 once it has reached regulation defined by the program valve set by UVS2, and FAULTn is released. The RUN_Cn pins are released by the LTM4664A PSM after the part is initialized and VINS3 is greater than the VIN_ON threshold. If multiple LTM4664A PSMs are used in an application, they all hold their respective RUN_Cn pins low until all devices are initialized and VINS3 exceeds the VIN_ON threshold for every device. The SHARE_CLK pin assures all the devices connected to the signal use the same time base. The SHARE_CLK pin is held low until the part has been initialized after VINS3 is applied. The LTM4664A PSM can be set to turn-off (or remain off) if SHARE_CLK is low (set bit 2 of MFR_CHAN_CONFIG to  1). This allows the user to assure synchronization across numerous PSM devices even if the RUN_Cn pins cannot be connected together due to board constraints. In general, if the user cares about synchronization between chips it is best not only to connect all the respective RUN_ Cn pins together but also to connect all the respective SHARE_CLK pins together and pulled up to VDD33 with a 10k resistor. This assures all chips begin sequencing at the same time and use the same time base. After the RUN_Cn pins release and prior to entering a constant output voltage regulation state, the LTM4664A PSM performs a monotonic initial ramp or “soft-start” on each of the 25A/30A outputs. Soft-start is performed by actively regulating the load voltage while digitally ramping the target voltage from 0V to the commanded voltage setpoint. Once the LTM4664A dual 25A/30A regulators are commanded to turn on (after power up and initialization), the controller waits for the user specified turn-on delay 38 (TON_DELAY) prior to initiating this output voltage ramp. The rise time of the voltage ramp can be programmed using the TON_RISE command to minimize inrush currents associated with the start-up voltage ramp. The softstart feature is disabled by setting the value of TON_RISE to any value less than 0.25ms. The LTM4664A PWM_Cn always uses discontinuous mode during the TON_RISE operation. In discontinuous mode, the bottom MOSFET is turned off as soon as reverse current is detected in the inductor. This will allow the regulator to start up into a prebiased load. When the TON_MAX_FAULT_LIMIT is reached, the part transitions to continuous mode, if so programmed. If TON_MAX_FAULT_LIMIT is set to zero, there is no time limit and the part transitions to the desired conduction mode after TON_RISE completes and VOUT has exceeded the VOUT_UV_FAULT_LIMIT and IOUT_OC is not present. However, setting TON_MAX_FAULT_LIMIT to a value of 0 is not recommended. TIME-BASED SEQUENCING The default mode for sequencing the outputs on and off is time-based. Each output is enabled after waiting TON_DELAY amount of time following either a RUN_Cn pin going high, a PMBus command to turn on or the VIN rising above a preprogrammed voltage. Off sequencing is handled in a similar way. To assure proper sequencing, make sure all ICs connect the SHARE_CLK pin together and RUN_Cn pins together. If the RUN_Cn pins cannot be connected together for some reasons, set bit 2 of MFR_CHAN_ CONFIG to 1. This bit requires the SHARE_CLK pin to be clocking before the power supply output can start. When the RUN_Cn pin is pulled low, the LTM4664A PSM will hold the pin low for the MFR_ RESTART_DELAY. The minimum MFR_RESTART_ DELAY is TOFF_DELAY + TOFF_FALL + 136ms. This delay assures proper sequencing of all rails. The LTM4664A PSM calculates this delay internally and will not process a shorter delay. However, a longer commanded MFR_RESTART_DELAY can be used by the part. The maximum allowed value is 65.52 seconds. VOLTAGE-BASED SEQUENCING The sequence can also be voltage-based. As shown in Figure  8, The PGOOD_Cn pins are asserted when the Rev. 0 For more information www.analog.com LTM4664A DUAL 25A/30A PSM OPERATION UV threshold is exceeded for each output. It is possible to feed the PGOOD_Cn pin from one LTM4664A PSM channel into the RUN_Cn pin of the next LTM4664A PSM channel in the sequence, especially across multiple LTM4664As. The PGOOD_Cn has a 60µs filter. If the VOUT voltage bounces around the UV threshold for a long period of time it is possible for the PGOOD_Cn output to toggle more than once. To minimize this problem, set the TON_RISE time under 100ms. If a fault in the string of rails is detected, only the faulted rail and downstream rails will fault off. The rails in the string of devices in front of the faulted rail will remain on unless commanded off. START PGOOD_C0 RUN_C0 LTM4664A RUN_C1 PGOOD_C1 RUN_C0 PGOOD_C0 There are two ways to respond to faults; which are retry mode and latched off mode. In retry mode, the controller responds to a fault by shutting down and entering the inactive state for a programmable delay time (MFR_RETRY_ DELAY). This delay minimizes the duty cycle associated with autonomous retries if the fault that causes the shutdown disappears once the output is disabled. The retry delay time is determined by the longer of the MFR_RETRY_ DELAY command or the time required for the regulated output to decay below 12.5% of the programmed value. If multiple outputs are controlled by the same FAULT_Cn pin, the decay time of the faulted output determines the retry delay. If the natural decay time of the output is too long, it is possible to remove the voltage requirement of the MFR_RETRY_DELAY command by asserting bit 0 of MFR_CHAN_CONFIG. Alternatively, latched off mode means the controller remains latched-off following a fault and clearing requires user intervention such as toggling RUN_Cn or commanding the part OFF then ON. LTM4664A RUN_C1 PGOOD_C1 4664A F08 TO NEXT CHANNEL IN THE SEQUENCE Figure 8. Event (Voltage) Based Sequencing SHUTDOWN The LTM4664A PSM Regulators supports two shutdown modes. The first mode is closed-loop shutdown response, with user defined turn-off delay (TOFF_DELAY) and ramp down rate (TOFF_FALL). The controller will maintain the mode of operation for TOFF_FALL. The second mode is discontinuous conduction mode, the controller will not draw current from the load and the fall time will be set by the output capacitance and load current, instead of TOFF_FALL. The shutdown occurs in response to a fault condition or loss of SHARE_CLK (if bit 2 of MFR_CHAN_ CONFIG is set to a 1) or VIN falling below the VIN_OFF threshold or FAULT pulled low externally (if the MFR_FAULT_ RESPONSE is set to inhibit). Under these conditions, the power stage is disabled in order to stop the transfer of energy to the load as quickly as possible. The shutdown state can be entered from the soft-start or active regulation states or through user intervention. LIGHT-LOAD CURRENT OPERATION The LTM4664A PSM Regulators have two modes of operation: high efficiency discontinuous conduction mode or forced continuous conduction mode. Mode selection is done using the MFR_PWM _MODE command (discontinuous conduction is always the start-up mode, forced continuous is the default running mode). If a controller is enabled for discontinuous operation, the inductor current is not allowed to reverse. The reverse current comparator’s output turns off the bottom MOSFET just before the inductor current reaches zero, preventing it from reversing and going negative. In forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. The peak inductor current is determined solely by the voltage on the COMP_Cn pins. In this mode, the efficiency at light loads is lower than in discontinuous mode operation. However, continuous mode exhibits lower output ripple and less interference with audio circuitry, but may result in reverse inductor current, which can cause the input supply to boost. The VIN_OV_FAULT_ LIMIT can detect this and turn off the offending channel. However, this fault is based on an ADC read and can take Rev. 0 For more information www.analog.com 39 LTM4664A DUAL 25A/30A PSM OPERATION up to tCONVERT to detect. If there is a concern about the input supply boosting, keep the part in discontinuous conduction mode. If the part is set to discontinuous mode operation, as the inductor average current increases, the controller will automatically modify the operation from discontinuous mode to continuous mode. SWITCHING FREQUENCY AND PHASE The switching frequency of the PWM_C1 can be established with an internal oscillator or an external time base. The internal phase-locked loop (PLL) synchronizes the PWM control to this timing reference with proper phase relation, whether the clock is provided internally or externally. The device can also be configured to provide the master clock to other devices through PMBus command, NVM setting, or external configuration resistors as outlined in Table 3. As clock master, a LTM4664A PSM device will drive its open-drain SYNC pin at the selected rate with a pulse width of 500ns. An external pull-up resistor between SYNC and VDD33 is required in this case. Only one device connected to SYNC should be designated to drive the pin. The other LTM4664A PSM devices will automatically revert to an external SYNC input, disabling its own SYNC, as long as the external SYNC frequency is greater than 80% of the programmed SYNC frequency. The external SYNC input shall have a duty cycle between 20% and 80%. Whether configured to drive SYNC or not, the LTM4664A PSM devices can continue PWM operation using its own internal oscillator if an external clock signal is subsequently lost. The device can also be programmed to always require an external oscillator for PWM operation by setting bit 4 of MFR_CONFIG_ALL. The status of the SYNC driver circuit is indicated by bit 10 of MFR_PADS. The MFR_PWM_CONFIG command can be used to configure the phase of each channel. Desired phase can also be set from EEPROM or external configuration resistors as outlined in Table 3. Designated phase is the relationship between the falling edge of SYNC and the internal clock 40 edge that sets the PWM latch to turn on the top power switch. Additional small propagation delays to the PWM control pins will also apply. Both PSM channels must be off before the FREQUENCY_SWITCH and MFR_PWM_ CONFIG commands can be written to the LTM4664A PSM. The phase relationships and frequency options provide for numerous application options. Multiple LTM4664A PSM channels modules can be synchronized to realize a PolyPhase array. In this case the phases should be separated by 360/n degrees, where n is the number of phases driving the output voltage rail. PWM LOOP COMPENSATION The internal PWM loop compensation resistors RCOMPna of the LTM4664A PSM can be adjusted using bit[4:0] of the MFR_PWM_COMP command. The transconductance (gm) of the LTM4664A PSM channel PWM error amplifier can be adjusted using bit[7:5] of the MFR_PWM_COMP command. These two loop compensation parameters can be programmed when the device is in operation. Refer to the Programmable Loop Compensation subsection in the Dual 25A/30A PSM Applications Information section for further details. OUTPUT VOLTAGE SENSING Both PSM channels in LTM4664A have differential amplifiers, which allow the remote sensing of the load voltage between V+ and V– pins. The telemetry ADC is also fully differential and makes measurements between VOSNS+_ Cn and VOSNS–_Cn voltages for both channels at the V+ and V– pins, respectively. The maximum allowed is 1.5V, but the LTM4664A design is limited to 1.8V. INTVCC/EXTVCC POWER Power for the internal MOSFET drivers and most other internal circuitry is derived from the INTVCC pin. When the EXTVCC pin is shorted to GND or tied to a voltage less than 4.7V, an internal 5.5V linear regulator supplies INTVCC power from VINS3. If EXTVCC is taken above approximately 4.7V and VINS3_C1 is higher than 7.0V, the 5.5V regulator is turned off and an internal switch is turned on, Rev. 0 For more information www.analog.com LTM4664A DUAL 25A/30A PSM OPERATION connecting EXTVCC to INTVCC. Using the EXTVCC allows the INTVCC power to be derived from a high efficiency external source such as a switching regulator output. EXTVCC can provide power to the internal 3.3V linear regulator even when VINS3 is not present, which allows the LTM4664A PSM to be initialized and programmed even without main power being applied. The INTVCC regulator is powered from the VINS3_C1 pin, the power through the IC is equal to VINS3_C1 • IINTVCC. The gate charge current is dependent on operating frequency. The INTVCC regulator can supply up to 100mA, and the typical INTVCC current for the LTM4664A PSM is ~50mA. A 12V input voltage would equate to a difference of 7V drop across the internal controller, when multiplied by 50mA equals a 350mW power loss. This loss can be eliminated by providing an external 5V bias on the EXTVCC pin. Do not tie INTVCC on the LTM4664A PSM to an external supply because INTVCC will attempt to pull the external supply high and hit current limit, significantly increasing the die temperature. OUTPUT CURRENT SENSING AND SUB MILLIOHM DCR CURRENT SENSING telemetry ADC with an input range of ±128mV, a noise floor of 7µVRMS, and a peak-peak noise of approximately 46.5µV. The LTM4664A PSM computes the inductor current using the DCR value stored in the IOUT_CAL_GAIN command and the temperature coefficient stored in command MFR_IOUT_ CAL_GAIN_TC. The resulting current value is returned by the READ_IOUT command. INPUT CURRENT SENSING To sense total input current consumed by the LTM4664A's 25A/30A two power stages , a sense resistor is placed between the supply voltage and VINS3 path. The IIN+ and IIN– pins are connected to the sense resistor. The filtered voltage is amplified by the internal high side current sense amplifier and digitized by the LTM4664A’s PSM telemetry ADC. The input current sense amplifier has three gain settings of 2x, 4x, and 8x set by the bit[6:5] of the MFR_PWM_CONFIG command. The maximum input sense voltage for the three gain settings is 50mV, 20mV, and 5mV respectively. The LTM4664A PSM computes the input current using the internal RSENSE value stored in the IIN_CAL_GAIN command. The resulting measured power stage current is returned by the READ_IIN command. The LTM4664A PSM channels use a unique sub-milliohm inductor current sensing technique that provides a high level signal to noise ratio while sensing very low signals in current mode operation. This enables higher conversion efficiencies with the use of the internal sub-milliohm inductors in heavy load applications. The current limit threshold can be accurately set with the MFR_PWM_MODE[7] for high and low range. The low range setting MFR_PWM_MODE [7] = 0 should be used (see page103). The LTM4664A uses a 1Ω resistor to measure the chip supply current being consumed by the LTM4664A PSM Controller. This value is returned by the MFR_READ_ICHIP command. The chip current is calculated by using the 1Ω value stored in the MFR_RVIN command. Refer to the subsection titled Input Current Sense Amplifier in the Dual 25A/30A PSM Applications Information section for further details. The internal DCR sensing network, thus current limit are calculated based on the DCR of the inductor at room temperature. The DCR of the inductor has a large temperature coefficient, approximately 3900ppm/°C. The temperature coefficient of the inductor is written to the MFR_IOUT_CAL_GAIN_TC register. The external temperature is sensed near the inductor and used to modify the internal current limit circuit to maintain an essentially constant current limit with temperature. The current sensed is then digitized by the LTM4664A PSM Multiple LTM4664As can be arrayed in order to provide a balanced load-share solution by bussing the necessary pins. Figure 48 illustrates a 4-Phase design sharing connections required for load sharing. PolyPhase LOAD SHARING If an external oscillator is not provided, the SYNC pin should only be enabled on one of the LTM4664A's PSM Channels. The other(s) should be programmed to disable SYNC using bit 4 of MFR_CONFIG_ALL. If an external oscillator is present, the chip with the SYNC Rev. 0 For more information www.analog.com 41 LTM4664A DUAL 25A/30A PSM OPERATION pin enabled will detect the presence of the external clock and disable its output. Multiple channels need to tie all the VOSNS+_Cn pins together, and all the VOSNS–_Cn pins together, COMP_na and COMP_nb pins together as well. Do not assert bit[4] of MFR_CONFIG_ALL except in a PolyPhase application. The user must share the SYNC, SHARE_CLK, FAULT_Cn, and ALERT pins of these parts. Be sure to use pull-up resistors on SYNC, FAULT_Cn, SHARE_CLK and ALERT. EXTERNAL/INTERNAL TEMPERATURE SENSE Temperature is measured using the internal diode-connected PNP transistors on either of the TSNS_C0b or TSNS_C1b pins corresponding to channel 0 or 1. TSNS_Cnb pins should be connected to their respective TSNS_Cna pins, and these returns are directly connected to the LTM4664A PSM SGND_C0_C1 pin. Two different currents are applied to the diode (nominally 2µA and 32µA) and the temperature is calculated from a ∆VBE measurement made with the internal 16-bit monitor ADC (see Figure 2, Block Diagram). The LTM4664A PSM channels will only implement ∆VBE temperature sensing, therefore MFR_PWM_MODE bit[5] is reserved. RCONFIG (RESISTOR CONFIGURATION) PINS There are six input pins utilizing 1% resistors for these pins to select key operating parameters. The pins are ASEL, FSWPH_CFG, VOUTC0_CFG, VOUTC1_CFG, VTRIMC0_ CFG, VTRIMC1_CFG. If pins are floated, the value stored in the corresponding NVM command is used. If bit 6 of the MFR_CONFIG_ALL configuration command is asserted in NVM, the resistor input is ignored upon power-up except for ASEL which is always respected. The resistor configuration pins are only measured during a power-up reset or after a MFR_RESET or after a RESTORE_USER_ALL command is executed. The VOUTn_CFG pin settings are described in Table 1. These pins set the LTM4664A VOUTC0 and VOUTC1 output voltage coarse settings. If the pin is open, the VOUT_ COMMAND command is loaded from NVM to determine the output voltage. The default setting is to have the 42 switcher off unless the voltage configuration pins are installed. The VTRIMn_CFG pins in Table 2 are used to set the output voltage fine adjustment setting. Both combine to offer several distinct output voltages. The following parameters are set as a percentage of the output voltage if the RCONFIG pins are used to determine the output voltage: n n n n n n VOUT_OV_FAULT_LIMIT.....................................+10% VOUT_OV_WARN_LIMIT.....................................+7.5% VOUT_MAX..........................................................+7.5% VOUT_MARGIN_HIGH.........................................+5% VOUT_MARGIN_LOW..........................................–5% VOUT_UV_FAULT_LIMIT.....................................–7% The FSWPH_CFG pin settings are described in Table 3. This pin selects the switching frequency and phase of each channel. The phase relationships between the two channels and SYNC pin are determined in Table 3. To synchronize to an external clock, the part should be put into external clock mode (SYNC output disabled but frequency set to the nominal value). If no external clock is supplied, the part will clock at the programmed frequency. If the application is multiphase and the SYNC signal between chips is lost, the parts will not operate at the designed phase even if they are programmed and trimmed to the same frequency. This may increase the ripple voltage on the output, possibly produce undesirable operation. If the external SYNC signal is being generated internally and external SYNC is not selected, bit 10 of MFR_PADS will be asserted. If no frequency is selected and the external SYNC frequency is not present, a PLL_FAULT will occur. If the user does not wish to see the ALERT from a PLL_FAULT even if there is not a valid synchronization signal at power-up, the ALERT mask for PLL_FAULT must be written. See the description on SMBALERT_MASK for more details. If the SYNC pin is connected between multiple ICs only one of the ICs should have the SYNC pin enabled using the MFR_CONFIG_ALL[4] =1, and all other ICs should be configured to have the SYNC pin disabled with MFR_ CONFIG_ALL[4] =0. The ASEL pin settings are described in Table 4. ASEL selects slave address for the LTM4664A PSM. For more detail, refer to Table 5. Rev. 0 For more information www.analog.com LTM4664A DUAL 25A/30A PSM OPERATION NOTE: Per the PMBus specification, pin programmed parameters can be overridden by commands from the digital interface with the exception of ASEL which is always honored. Do not set any part address to 0x5A or 0x5B because these are global addresses and all parts will respond to them. Table 2. VTRIMn_CFG Pin Strapping Look-Up Table for the LTM4664A’s PSM Output Voltages, Fine Adjustment Setting (Not Applicable if MFR_CONFIG_ALL[6] = 1b) RVTRIMn_CFG* BOT (kΩ) VTRIM (mV) FINE ADJUSTMENT TO VOUTn SETTING WHEN RESPECTIVE RVTRIMn_CFG TOP (kΩ) Open 0 14.3 32.4 99 14.3 22.6 86.625 14.3 18.0 74.25 14.3 15.4 61.875 14.3 12.7 49.5 14.3 37.125 14.3 Table 1. VOUTCn _CFG Pin Strapping Look-Up Table for the LTM4664A’s PSM Output Voltages, Coarse Setting (Not Applicable if MFR_CONFIG_ALL[6] = 1b) RVOUTn_CFG TOP (kΩ) RVOUTn_CFG* BOT (kΩ) VOUTn (V) SETTING COARSE 14.3 Open NVM NVM 10.7 14.3 32.4 NVM NVM 9.09 24.75 14.3 12.375 14.3 MFR_PWM MODEn[1] BIT 14.3 22.6 3.3 0 7.68 14.3 18.0 3.1 0 6.34 –12.375 14.3 –24.75 14.3 –37.125 14.3 14.3 15.4 2.9 0 5.23 14.3 12.7 2.7 0 4.22 14.3 10.7 2.5 0, if VTRIMn > 0mV 1, if VTRIMn ≤ 0mV 3.24 –49.5 14.3 2.43 –61.875 14.3 14.3 14.3 9.09 2.3 1 1.65 –74.25 14.3 7.68 2.1 1 0.787 –86.625 14.3 14.3 6.34 1.9 1 0 –99 14.3 14.3 5.23 1.7 1 14.3 4.22 1.5 1 14.3 3.24 1.3 1 14.3 2.43 1.1 1 14.3 1.65 0.9 1 14.3 0.787 0.7 1 14.3 0 0.5 1 *RVOUTCn_CFG value indicated is nominal. Select RVOUTCn_CFG from a resistor vendor such that its value is always within 3% of the value indicated in the table. Take into account resistor initial tolerance, T.C.R. and resistor operating temperatures, soldering heat/IR reflow, and endurance of the resistor over its lifetime. Thermal shock/cycling, moisture (humidity) and other effects (depending on one’s specific application) could also affect RVOUTCn_CFG’s value over time. All such effects must be taken into account in order for resistor pin strapping to yield the expected result at every SVIN power-up and/or every execution of MFR_RESET or RESTORE_ USER_ALL, over the lifetime of one’s product. *RVTRIMCn_CFG value indicated is nominal. Select RVTRIMCn_CFG from a resistor vendor such that its value is always within 3% of the value indicated in the table. Take into account resistor initial tolerance, T.C.R. and resistor operating temperatures, soldering heat/IR reflow, and endurance of the resistor over its lifetime. Thermal shock/cycling, moisture (humidity) and other effects (depending on one’s specific application) could also affect RVTRIMCn_CFG’s value over time. All such effects must be taken into account in order for resistor pin strapping to yield the expected result at every SVIN power-up and/or every execution of MFR_RESET, or RESTORE_USER_ALL over the lifetime of one’s product. Example: VDD25 ROUTCn_CFG TOP VOUTCn_CFG PIN ROUTCn_CFG BOT SGND_C0_C1 Rev. 0 For more information www.analog.com 43 LTM4664A DUAL 25A/30A PSM OPERATION Table 3. FSWPH_CFG Pin Strapping Look-Up Table to Set the LTM4664A’s PSM Switching Frequency and Channel Phase-Interleaving Angle (Not Applicable if MFR_CONFIG_ALL[6] = 1b) RFSWPH_CFG TOP (kΩ) RFSWPH_CFG* BOT (kΩ) SWITCHING FREQUENCY (kHz) θSYNC TO θ0 θSYNC TO θ1 bits [2:0] of MFR_PWM_CONFIG bit [4] of MFR_CONFIG_ALL 14.3 Open NVM; LTM4664A PSM Default = 500 NVM; LTM4664A Default = 0° NVM; LTM4664A PSM Default = 180° NVM; LTM4664A PSM Default = 000b NVM; LTM4664A PSM Default = 0b 14.3 32.4 250 0° 180° 000b 0b 14.3 22.6 350 0° 180° 000b 0b 14.3 18.0 425 0° 180° 000b 0b 14.3 15.4 575 0° 180° 000b 0b 14.3 12.7 650 0° 180° 000b 0b 14.3 10.7 750 0° 180° 000b 0b 14.3 7.68 500 120° 240° 100b 0b 14.3 6.34 500 90° 270° 001b 0b 14.3 5.23 External** 0° 240° 010b 1b 14.3 4.22 External** 0° 120° 011b 1b 14.3 3.24 External** 60° 240° 101b 1b 14.3 2.43 External** 120° 300° 110b 1b 14.3 1.65 External** 90° 270° 001b 1b 14.3 0.787 External** 0° 180° 000b 1b 14.3 0 External** 120° 240° 100b 1b *RFSWPH_CFG value indicated is nominal. Select RFSWPH_CFG from a resistor vendor such that its value is always within 3% of the value indicated in the table. Take into account resistor initial tolerance, T.C.R. and resistor operating temperatures, soldering heat/IR reflow, and endurance of the resistor over its lifetime. Thermal shock/cycling, moisture (humidity) and other effects (depending on one’s specific application) could also affect RFSWPH_CFG’s value over time. All such effects must be taken into account in order for resistor pin-strapping to yield the expected result at every SVIN power-up and/or every execution of MFR_RESET or RESTORE_USER_ALL, over the lifetime of one’s product. **External setting corresponds to FREQUENCY_SWITCH (Register 0x33) value set to 0x0000; the device synchronizes its switching frequency to that of the clock provided on the SYNC pin, provided MFR_CONFIG_ALL[4] = 1b. Example: VDD25 RFSWPH_CFG TOP FSWPH_CFG PIN RFSWPH_CFG BOT 44 Rev. 0 For more information www.analog.com LTM4664A DUAL 25A/30A PSM OPERATION Table 4. ASEL Pin Strapping Look-Up Table to Set the LTM4664A’s PSM Slave Address (Applicable Regardless of MFR_CONFIG_ALL[6] Setting) RASEL* (kΩ) Table 5. LTM4664A PSM MFR_ADDRESS Command Examples Expressed in 7- and 8-Bit Addressing HEX DEVICE ADDRESS SLAVE ADDRESS MFR_ADDRESS[6:0]_R/W DESCRIPTION 7-BIT 8-BIT 7 6 5 4 3 2 1 0 R/W MFR_ADDRESS[6:4]_1111_R/W Rail4 0x5A 0xB4 0 1 0 1 1 0 1 0 0 22.6 MFR_ADDRESS[6:4]_1110_R/W Global4 0x5B 0xB6 0 1 0 1 1 0 1 1 0 18.0 MFR_ADDRESS[6:4]_1101_R/W Default 0x4F 0x9E 0 1 0 0 1 1 1 1 0 15.4 MFR_ADDRESS[6:4]_1100_R/W Example 1 0x40 0x80 0 1 0 0 0 0 0 0 0 12.7 MFR_ADDRESS[6:4]_1011_R/W Example 2 0x41 0x82 0 1 0 0 0 0 0 1 0 MFR_ADDRESS[6:4]_1010_R/W Disabled2,3 1 0 0 0 0 0 0 0 0 9.09 MFR_ADDRESS[6:4]_1001_R/W 7.68 MFR_ADDRESS[6:4]_1000_R/W 6.34 MFR_ADDRESS[6:4]_0111_R/W 5.23 MFR_ADDRESS[6:4]_0110_R/W 4.22 MFR_ADDRESS[6:4]_0101_R/W 3.24 MFR_ADDRESS[6:4]_0100_R/W 2.43 MFR_ADDRESS[6:4]_0011_R/W 1.65 MFR_ADDRESS[6:4]_0010_R/W Note 1. This table can be applied to the MFR_RAIL_ADDRESSn commands, but not the MFR_ADDRESS command. Note 2. A disabled value in one command does not disable the device, nor does it disable the global address. Note 3. A disabled value in one command does not inhibit the device from responding to device addresses specified in other commands. Note 4. It is not recommended to write the value 0x00, 0x0C (7-bit), 0x5A (7-bit), 0x5B (7-bit) or 0x7C(7-bit) to the MFR_CHANNEL_ADDRESSn or the MFR_RAIL_ADDRESSn commands. 0.787 MFR_ADDRESS[6:4]_0001_R/W 0 MFR_ADDRESS[6:4]_0000_R/W Open 32.4 10.7 Where: R/W = Read/Write bit in control byte All PMBus device addresses listed in the specification are 7 bits wide unless otherwise noted. Note: The LTM4664A PSM will always respond to slave address 0x5A and 0x5B regardless of the NVM or ASEL resistor configuration values. *RCFG value indicated is nominal. Select RCFG from a resistor vendor such that its value is always within 3% of the value indicated in the table. Take into account resistor initial tolerance, T.C.R. and resistor operating temperatures, soldering heat/IR reflow, and endurance of the resistor over its lifetime. Thermal shock cycling, moisture (humidity) and other effects (depending on one’s specific application) could also affect RCFG’s value over time. All such effects must be taken into account in order for resistor pin-strapping to yield the expected result at every SVIN power-up and/or every execution of MFR_RESET or RESTORE_USER_ALL, over the lifetime of one’s product. Example: FAULT DETECTION AND HANDLING A variety of fault and warning reporting and handling mechanisms are available. Fault and warning detection capabilities include: Input OV FAULT Protection and UV Warning n Average Input OC Warn n Output OV/UV Fault and Warn Protection n Output OC Fault and Warn Protection n Internal control Die and Internal Module Overtemperature Fault and Warn Protection n Internal Undertemperature Fault and Warn Protection n CML Fault (Communication, Memory or Logic) n n BIT ASEL PIN RASEL SGND_C0_C1 External Fault Detection via the Bidirectional FAULT_Cn Pins In addition, the LTM4664A PSM can map any combination of fault indicators to their respective FAULT_Cn pin using the propagate FAULTn response commands, MFR_FAULT_ PROPAGATE. Typical usage of a FAULT_Cn pin is as a driver for an external crowbar device, overtemperature alert, overvoltage alert or as an interrupt Rev. 0 For more information www.analog.com 45 LTM4664A DUAL 25A/30A PSM OPERATION to cause a microcontroller to poll the fault commands. Alternatively, the FAULT_Cn pins can be used as inputs to detect external faults downstream of the controller that require an immediate response. Any fault or warning event will always cause the ALERT pin to assert low unless the fault or warning is masked by the SMBALERT_MASK. The pin will remain asserted low until the CLEAR_FAULTS command is issued, the fault bit is written to a 1 or bias power is cycled or a MFR_RESET command is issued, or the RUN pins are toggled OFF/ ON or the part is commanded OFF/ON via PMBus or an ARA command operation is performed. The MFR_FAULT_ PROPAGATE command determines if the FAULT_Cn pins are pulled low when a fault is detected. Output and input fault event handling is controlled by the corresponding fault response byte as specified in Table 3 thru 17. Shutdown recovery from these types of faults can either be autonomous or latched. For autonomous recovery, the faults are not latched, so if the fault conditions not present after the retry interval has elapsed, a new soft-start is attempted. If the fault persists, the controller will continue to retry. The retry interval is specified by the MFR_RETRY_DELAY command and prevents damage to the regulator components by repetitive power cycling, assuming the fault condition itself is not immediately destructive. The MFR_ RETRY_DELAY must be greater than 120ms. It can not exceed 83.88 seconds. Status Registers and ALERT Masking Figure 9 summarizes the internal LTM4664A PSM status registers accessible by PMBus command. These contain indication of various faults, warnings and other important operating conditions. As shown, the STATUS_BYTE and STATUS_WORD commands also summarize contents of other status registers. Refer to PMBus Command Summary for specific information. NONE OF THE ABOVE in the STATUS_BYTE indicates that one or more of the bits in the most-significant nibble of STATUS_WORD are also set. 46 In general, any asserted bit in a STATUS_x register also pulls the ALERT pin low. Once set, ALERT will remain low until one of the following occurs. n A CLEAR_FAULTS or MFR_RESET Command Is Issued The Related Status Bit Is Written to a One n The Faulted Channel Is Properly Commanded Off and Back On n The LTM4664A PSM Successfully Transmits Its Address During a PMBus ARA n Bias Power Is Cycled n With some exceptions, the SMBALERT_MASK command can be used to prevent the LTM4664A PSM from asserting ALERT for bits in these registers on a bit-by-bit basis. These mask settings are promoted to STATUS_WORD and STATUS_BYTE in the same fashion as the status bits themselves. For example, if ALERT is masked for all bits in channel 0 STATUS_VOUT, then ALERT is effectively masked for the VOUT bit in STATUS_WORD for PAGE 0. The BUSY bit in STATUS_BYTE also asserts ALERT low and cannot be masked. This bit can be set as a result of various internal interactions with PMBus communication. This fault occurs when a command is received that cannot be safely executed with one or both channels enabled. As discussed in the 4:1 Divider Application Information, BUSY faults can be avoided by polling MFR_COMMON before executing some commands. If masked faults occur immediately after power up, ALERT may still be pulled low because there has not been time to retrieve all of the programmed masking information from EEPROM. Status information contained in MFR_COMMON and MFR_PADS can be used to further debug or clarify the contents of STATUS_BYTE or STATUS_WORD as shown, but the contents of these registers do not affect the state of the ALERT pin and may not directly influence bits in STATUS_BYTE or STATUS_WORD. Rev. 0 For more information www.analog.com LTM4664A DUAL 25A/30A PSM OPERATION STATUS_WORD STATUS_VOUT* 7 6 5 4 3 2 1 0 VOUT_OV Fault VOUT_OV Warning VOUT_UV Warning VOUT_UV Fault VOUT_MAX Warning TON_MAX Fault TOFF_MAX Warning (reads 0) 15 14 13 12 11 10 9 8 VOUT IOUT INPUT MFR_SPECIFIC POWER_GOOD# (reads 0) (reads 0) (reads 0) 7 6 5 4 3 2 1 0 BUSY OFF VOUT_OV IOUT_OC (reads 0) TEMPERATURE CML NONE OF THE ABOVE STATUS_BYTE (PAGED) STATUS_IOUT 7 6 5 4 3 2 1 0 IOUT_OC Fault (reads 0) IOUT_OC Warning (reads 0) (reads 0) (reads 0) (reads 0) (reads 0) MFR_COMMON 7 6 5 4 3 2 1 0 STATUS_TEMPERATURE OT Fault OT Warning (reads 0) UT Fault (reads 0) (reads 0) (reads 0) (reads 0) (PAGED) STATUS_CML 7 6 5 4 3 2 1 0 Chip Not Driving ALERT Low Chip Not Busy Internal Calculations Not Pending Output Not In Transition EEPROM Initialized (reads 0) SHARE_CLK_LOW WP Pin High Invalid/Unsupported Command Invalid/Unsupported Data Packet Error Check Failed Memory Fault Detected Processor Fault Detected (reads 0) Other Communication Fault Other Memory or Logic Fault Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved EEPROM ECC Status Reserved Reserved Reserved Reserved DESCRIPTION 7 6 5 4 3 2 1 0 Internal Temperature Fault Internal Temperature Warning EEPROM CRC Error Internal PLL Unlocked Fault Log Present VDD33 UV or OV Fault VOUT Short Cycled FAULT Pulled Low By External Device (PAGED) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VDD33 OV Fault VDD33 UV Fault (reads 0) (reads 0) Invalid ADC Result(s) SYNC Clocked by External Source Channel 1 is POWER_GOOD Channel 0 is POWER_GOOD LTM4664A Forcing RUN1 Low LTM4664A Forcing RUN0 Low RUN1 Pin State RUN0 Pin State LTM4664A Forcing FAULT1 Low LTM4664A Forcing FAULT0 Low FAULT1 Pin State FAULT0 Pin State MFR_PADS MFR_INFO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VIN_OV Fault (reads 0) VIN_UV Warning (reads 0) Unit Off for Insuffcient VIN (reads 0) IIN_OC Warning (reads 0) STATUS_MFR_SPECIFIC (PAGED) (PAGED) 7 6 5 4 3 2 1 0 STATUS_INPUT 7 6 5 4 3 2 1 0 4664A F09 MASKABLE GENERATES ALERT BIT CLEARABLE General Fault or Warning Event General Non-Maskable Event Dynamic Status Derived from Other Bits Yes No No No Yes Yes No Not Directly Yes Yes No No Figure 9. LTM4664A PSM Status Register Summary Rev. 0 For more information www.analog.com 47 LTM4664A DUAL 25A/30A PSM OPERATION Mapping Faults to FAULT Pins Channel-to-channel fault (including channels from multiple LTM4664A PSMs) dependencies can be created by connecting FAULT_Cn pins together. In the event of an internal fault, one or more of the channels is configured to pull the bussed FAULT_Cn pins low. The other channels are then configured to shut down when the FAULT_Cn pins are pulled low. For autonomous group retry, the faulted channel is configured to let go of the FAULT_Cn pin(s) after a retry interval, assuming the original fault has cleared. All the channels in the group then begin a soft-start sequence. If the fault response is LATCH_OFF, the FAULT_Cn pin remains asserted low until either the RUN_Cn pin is toggled OFF/ON or the part is commanded OFF/ON. The toggling of the RUN_Cn either by the pin or OFF/ON command will clear faults associated with the channel. If it is desired to have all faults cleared when either RUN_Cn pin is toggled or, set bit 0 of MFR_CONFIG_ALL to a 1. The status of all faults and warnings is summarized in the STATUS_WORD and STATUS_BYTE commands. Additional fault detection and handling capabilities are: See Table 18. Power Good Pins The PGOOD_Cn pins of the LTM4664A PSM are connected to the open drains of internal MOSFETs. The MOSFETs turn on and pull the PGOOD_Cn pins low when the channel output voltage is not within the channel’s UV and OV voltage thresholds. During TON_DELAY and TON_RISE sequencing, the PGOOD_Cn pin is held low. The PGOOD_Cn pin is also pulled low when the respective RUN_Cn pin is low. The PGOOD_Cn pin response is deglitched by an internal 100µs digital filter. The PGOOD_Cn pin and PGOOD status may be different at times due to communication latency of up to 10µs. CRC Protection The integrity of the NVM memory is checked after a power on reset. A CRC error will prevent the controller from leaving the inactive state. If a CRC error occurs, the CML bit is set in the STATUS_BYTE and STATUS_WORD commands, the appropriate bit is set in the STATUS_MFR_SPECIFIC 48 command, and the ALERT pin will be pulled low. NVM repair can be attempted by writing the desired configuration to the controller and executing a STORE_USER_ALL command followed by a CLEAR_FAULTS command. The LTM4664A manufacturing section of the NVM is mirrored. If both copies are corrupted, the “NVM CRC Fault” in the STATUS_MFR_SPECIFIC command is set. If this bit remains set after being cleared by issuing a CLEAR_FAULTS or writing a 1 to this bit, an irrecoverable internal fault has occurred. The user is cautioned to disable both output power supply rails associated with this specific part. There are no provisions for field repair of NVM faults in the manufacturing section. SERIAL INTERFACE The LTM4664A serial interface is a PMBus compliant slave device and can operate at any frequency between 10kHz and 400kHz. The address is configurable using either the NVM or an external resistor divider. In addition the LTM4664A always responds to the global broadcast address of 0x5A (7-bit) or 0x5B (7-bit). The serial interface supports the following protocols defined in the PMBus specifications: 1) send command, 2) write byte, 3) write word, 4) group, 5) read byte, 6) read word and 7) read block. 8) write block. All read operations will return a valid PEC if the PMBus master requests it. If the PEC_REQUIRED bit is set in the MFR_CONFIG_ALL command, the PMBus write operations will not be acted upon until a valid PEC has been received by the LTM4664A. Communication Protection PEC write errors (if PEC_REQUIRED is active), attempts to access unsupported commands, or writing invalid data to supported commands will result in a CML fault. The CML bit is set in the STATUS_BYTE and STATUS_WORD commands, the appropriate bit is set in the STATUS_CML command, and the ALERT pin is pulled low. DEVICE ADDRESSING The LTM4664A PSM offers four different types of addressing over the PMBus interface, specifically: 1) global, 2) device, 3) rail addressing and 4) alert response address (ARA). Rev. 0 For more information www.analog.com LTM4664A DUAL 25A/30A PSM OPERATION Global addressing provides a means of the PMBus master to address all LTM4664A PSM devices on the bus. The LTM4664A PSM global address is fixed 0x5A (7-bit) or 0xB4 (8-bit) and cannot be disabled. Commands sent to the global address act the same as if PAGE is set to a value of 0xFF. Commands sent are written to both channels simultaneously. Global command 0x5B (7-bit) or 0xB6 (8-bit) is paged and allows channel specific command of all LTM4664A PSM devices on the bus. Other LTC device types may respond at one or both of these global addresses. Reading from global addresses is strongly discouraged. Device addressing provides the standard means of the PMBus master communicating with a single instance of an LTM4664A PSM. The value of the device address is set by a combination of the ASEL configuration pin and the MFR_ ADDRESS command. When this addressing means is used, the PAGE command determines the channel being acted upon. Device addressing can be disabled by writing a value of 0x80 to the MFR_ADDRESS. Rail addressing provides a means for the bus master to simultaneously communicate with all channels connected together to produce a single output voltage (PolyPhase). While similar to global addressing, the rail address can be dynamically assigned with the paged MFR_RAIL_ ADDRESS command, allowing for any logical grouping of channels that might be required for reliable system control. Reading from rail addresses is also strongly discouraged. All four means of PMBus addressing require the user to employ disciplined planning to avoid addressing conflicts. Communication to LTM4664A PSM devices at global and rail addresses should be limited to command write operations. RESPONSES TO VOUT AND IIN/IOUT FAULTS The digital processor within the LTM4664A PSM provides the ability to ignore the fault, shut down and latch off or shut down and retry indefinitely (hiccup). The retry interval is set in MFR_RETRY_ DELAY and can be from 120ms to 83.88 seconds in 1ms increments. The shutdown for OV/UV and OC can be done immediately or after a user selectable deglitch time. Output Overvoltage Fault Response A programmable overvoltage comparator (OV) guards against transient overshoots as well as long-term overvoltages at the output. In such cases, the top MOSFET is turned off and the bottom MOSFET is turned on. However, the reverse output current is monitored while device is in OV fault. When it reaches the limit, both top and bottom MOSFETs are turned off. The top and bottom MOSFETs will keep their state until the overvoltage condition is cleared regardless of the PMBus VOUT_OV_ FAULT_RESPONSE command byte value. This hardware level fault response delay is typically 2µs from the overvoltage condition to BG asserted high. Using the VOUT_ OV_FAULT_RESPONSE command, the user can select any of the following behaviors: OV Pull-Down Only (OV Cannot Be Ignored) n VOUT OV and UV conditions are monitored by comparators. The OV and UV limits are set in three ways: As a Percentage of the VOUT if Using the Resistor Configuration Pins n n The IIN and IOUT overcurrent monitors are performed by ADC readings and calculations. Thus these values are based on average currents and can have a time latency of up to tCONVERT. The IOUT calculation accounts for the DCR and their temperature coefficient. The input current is equal to the voltage measured across the RSENSE resistor divided by the resistors value as set with the MFR_IIN_CAL_GAIN command. If this calculated input current exceeds the IN_OC_WARN_LIMIT the ALERT pin is pulled low and the IIN_OC_WARN bit is asserted in the STATUS_INPUT command. In NVM if Either Programmed at the Factory or Through the GUI Shut Down (Stop Switching) Immediately—Latch Off n n Shut Down Immediately—Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY Either the Latch Off or Retry fault responses can be de-glitched in increments of (0-7) • 10µs. See Table 14. By PMBus Command n Rev. 0 For more information www.analog.com 49 LTM4664A DUAL 25A/30A PSM OPERATION Output Undervoltage Response The response to an undervoltage comparator output can be the following: Ignore n Shut Down Immediately—Latch Off n n Shut Down Immediately—Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY. The UV responses can be deglitched. See Table 14. Peak Output Overcurrent Fault Response Due to the current mode control algorithm, peak output current across the inductor is always limited on a cycle-by-cycle basis. The value of the peak current limit is specified in Electrical Characteristics table. The current limit circuit operates by limiting the COMP_Cn maximum voltage. Since internal DCR sensing is used, the COMP_Cn maximum voltage has a temperature dependency directly proportional to the TC of the DCR of the inductor. The LTM4664A PSM automatically monitors the external temperature sensors and modifies the maximum allowed COMP_Cn to compensate for this term. The IOUT_OC_FAULT_LIMIT section provides data points for IOUT Limiting on page103. The overcurrent fault processing circuitry can execute the following behaviors: Shut Down Immediately—Latch Off n Shut Down Immediately—Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY. The overcurrent responses can be deglitched in increments of (0-7) • 16ms. See Table 15. RESPONSES TO TIMING FAULTS TON_MAX_FAULT_LIMIT is the time allowed for VOUT to rise and settle at start-up. The TON_MAX_FAULT_LIMIT condition is predicated upon detection of the VOUT_UV_ FAULT_LIMIT as the output is undergoing a SOFT_START sequence. The TON_MAX_ FAULT_LIMIT time is started after TON_DELAY has been reached and a SOFT_START 50 Ignore n Shut Down (Stop Switching) Immediately—Latch Off n n Shut Down Immediately—Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY. This fault response is not deglitched. A value of 0 in TON_MAX_FAULT_LIMIT means the fault is ignored. The TON_MAX_FAULT_LIMIT should be set longer than the TON_RISE time. It is recommended TON_MAX_FAULT_ LIMIT always be set to a non-zero value, otherwise the output may never come up and no flag will be set to the user. See Table 16. RESPONSES TO VIN OV FAULTS VIN overvoltage is measured with the ADC. The response is naturally deglitched by the 100ms typical response time of the ADC. The fault responses are: Ignore n Shut Down Immediately—Latch Off n Shut Down Immediately—Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY. See Table 16. n Current Limit Indefinitely n n sequence is started. The resolution of the TON_MAX_ FAULT_LIMIT is 10µs. If the VOUT_UV_FAULT _LIMIT is not reached within the TON_MAX_FAULT_LIMIT time, the response of this fault is determined by the value of the TON_MAX_FAULT_RESPONSE command value. This response may be one of the following: RESPONSES TO OT/UT FAULTS Internal Overtemperature Fault Response An internal temperature sensor protects against NVM damage. Above 85°C, no writes to NVM are recommended. Above 130°C, the internal overtemperature warn threshold is exceeded and the part disables the NVM and does not re-enable until the temperature has dropped to 125°C. When the die temperature exceed 160°C the internal temperature fault response is enabled and the PWM is disabled until the die temperature drops below 150°C. Temperature is measured by the ADC. Internal Rev. 0 For more information www.analog.com LTM4664A DUAL 25A/30A PSM OPERATION temperature faults cannot be ignored. Internal temperature limits cannot be adjusted by the user. See Table 14. External Overtemperature and Undertemperature Fault Response Two internal temperature sensors are used to sense the temperature of critical circuit elements like inductors and power MOSFETs on each channel. The OT_FAULT_ RESPONSE and UT_FAULT_ RESPONSE commands are used to determine the appropriate response to an overtemperature and under temperature condition, respectively. If no external sense elements are used (not recommended) set the UT_FAULT_ RESPONSE to ignore—and set the UT_FAULT_LIMIT to 275°C. The fault responses are: Ignore n Shut Down Immediately—Latch Off n n Shut Down Immediately—Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY. See Table 16. RESPONSES TO INPUT OVERCURRENT AND OUTPUT UNDERCURRENT FAULTS Input overcurrent and output undercurrent are measured with the ADC. The fault responses are: Ignore FAULT LOGGING The LTM4664A PSM has fault logging capability. Data is logged into memory in the order shown in Table 19. The data is stored in a continuously updated buffer in RAM. When a fault event occurs, the fault log buffer is copied from the RAM buffer into NVM. Fault logging is allowed at temperatures above 85°C; however, retention of 10 years is not guaranteed. When the die temperature exceeds 130°C the fault logging is delayed until the die temperature drops below 125°C. The fault log data remains in NVM until a MFR_FAULT _LOG_CLEAR command is issued. Issuing this command re-enables the fault log feature. Before re-enabling fault log, be sure no faults are present and a CLEAR_FAULTS command has been issued. When the LTM4664A PSM powers-up or exits its reset state, it checks the NVM for a valid fault log. If a valid fault log exists in NVM, the “Valid Fault Log” bit in the STATUS_ MFR_SPECIFIC command will be set and an ALERT event will be generated. Also, fault logging will be blocked until the LTM4664A PSM has received a MFR_FAULT_LOG_ CLEAR command before fault logging will be re-enabled. The information is stored in EEPROM in the event of any fault that disables the controller on either channel. A FAULT_Cn being externally pulled low will not trigger a fault logging event. n BUS TIMEOUT PROTECTION Shut Down Immediately—Latch Off n Shut Down Immediately—Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY. See Table 15. n RESPONSES TO EXTERNAL FAULTS When either FAULT_Cn pin is pulled low, the OTHER bit is set in the STATUS_WORD command, the appropriate bit is set in the STATUS_MFR_SPECIFIC command, and the ALERT pin is pulled low. Responses are not deglitched. Each channel can be configured to ignore or shut down then retry in response to its FAULT_Cn pin going low by modifying the MFR_FAULT_RESPONSE command. To avoid the ALERT pin asserting low when FAULT_Cn is pulled low, assert bit 1 of MFR_CHAN_CONFIG, or mask the ALERT using the SMBALERT_MASK command. The LTM4664A PSM implements a timeout feature to avoid persistent faults on the serial interface. The data packet timer begins at the first START event before the device address write byte. Data packet information must be completed within 30ms or the LTM4664A PSM will three-state the bus and ignore the given data packet. If more time is required, assert bit 3 of MFR_CONFIG_ALL to allow typical bus timeouts of 255ms. Data packet information includes the device address byte write, command byte, repeat start event (if a read operation), device address byte read (if a read operation), all data bytes and the PEC byte if applicable. The LTM4664A PSM allows longer PMBus timeouts for block read data packets. This timeout is proportional to the length of the block read. The additional block read timeout applies primarily to the MFR_FAULT_LOG command. The timeout period defaults to 32ms. Rev. 0 For more information www.analog.com 51 LTM4664A DUAL 25A/30A PSM OPERATION The user is encouraged to use as high a clock rate as possible to maintain efficient data packet transfer between all devices sharing the serial bus interface. The LTM4664A PSM supports the full PMBus frequency range from 10kHz to 400kHz. signals on the bus. The two-bus lines, SDA and SCL, must be high when the bus is not in use. External pull-up resistors or current sources are required on these lines. The LTM4664A is a slave device. The master can communicate with the LTM4664A using the following formats: Master Transmitter, Slave Receiver n SIMILARITY BETWEEN PMBus, SMBus AND I2C 2-WIRE INTERFACE The PMBus 2-wire interface is an incremental extension of the SMBus. SMBus is built upon I2C with some minor differences in timing, DC parameters and protocol. The PMBus/SMBus protocols are more robust than simple I2C byte commands because PMBus/SMBus provide timeouts to prevent persistent bus errors and optional packet error checking (PEC) to ensure data integrity. In general, a master device that can be configured for I2C communication can be used for PMBus communication with little or no change to hardware or firmware. Repeat start (restart) is not supported by all I2C controllers but is required for SMBus/PMBus reads. If a general purpose I2C controller is used, check that repeat start is supported. The LTM4664A PSM supports the maximum SMBus clock speed of 100kHz and is compatible with the higher speed PMBus specification (between 100kHz and 400kHz) if MFR_ COMMON polling or clock stretching is enabled. For robust communication and operation refer to the Note section in the PMBus command summary. Clock stretching is enabled by asserting bit 1 of MFR_CONFIG_ALL. For a description of the minor extensions and exceptions PMBus makes to SMBus, refer to PMBus Specification Part 1 Revision 1.2: Paragraph 5: Transport. For a description of the differences between SMBus and I2C, refer to System Management Bus (SMBus) Specification Version 2.0: Appendix B—Differences Between SMBus and I2C. PMBus SERIAL DIGITAL INTERFACE Master Receiver, Slave Transmitter n The following PMBus protocols are supported: Write Byte, Write Word, Send Byte n Read Byte, Read Word, Block Read, Block Write n Alert Response Address n Figure 11 thru Figure 28 illustrate the aforementioned PMBus protocols. All transactions support PEC and GCP (group command protocol). The Block Read supports 255 bytes of returned data. For this reason, the PMBus timeout may be extended when reading the fault log. Figure 11 is a key to the protocol diagrams in this section. PEC is optional. A value shown below a field in the following figures is mandatory value for that field. The data formats implemented by PMBus are: Master transmitter transmits to slave receiver. The transfer direction in this case is not changed. n Master reads slave immediately after the first byte. At the moment of the first acknowledgment (provided by the slave receiver) the master transmitter becomes a master receiver and the slave receiver becomes a slave transmitter. n Combined format. During a change of direction within a transfer, the master repeats both a start condition and the slave address but with the R/Wbit reversed. In this case, the master receiver terminates the transfer by generating a NACK on the last byte of the transfer and a STOP condition. n The LTM4664A PSM communicates with a host (master) using the standard PMBus serial bus interface. The Timing Diagram, Figure 10, shows the timing relationship of the 52 Rev. 0 For more information www.analog.com LTM4664A DUAL 25A/30A PSM OPERATION Refer to Figure 11 for a legend. Handshaking features are included to ensure robust system communication. Please refer to the PMBus Communication and Command Processing subsection of the Dual 25A/30A PSM Applications Information section for further details. SDA tf tLOW tr tSU(DAT) tHD(SDA) tf tSP tr tBUF SCL tHD(STA) tHD(DAT) tSU(STA) tHIGH tSU(STO) 4664A F10 START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION Figure 10. PMBus Timing Diagram Table 6. Abbreviations of Supported Data Formats PMBus TERMINOLOGY SPECIFICATION LTC REFERENCE TERMINOLOGY DEFINITION EXAMPLE Floating point 16-bit data: value = Y • 2N, b[15:0] = 0x9807 = 10011_000_0000_0111 value = 7 • 2–13 = 854E-6 L11 Linear Part II ¶7.1 Linear_5s_11s L16 Linear VOUT_MODE Part II ¶8.2 Linear_16u Floating point 16-bit data: value = Y • 2–12, where Y = b[15:0], an unsigned integer b[15:0] = 0x4C00 = 0100_1100_0000_0000 value = 19456 • 2–12 = 4.75 CF DIRECT Part II ¶7.2 Varies 16-bit data with a custom format defined in the detailed PMBus command description Often an unsigned or two’s compliment integer Reg Register Bits Part II ¶10.3 Reg Per-bit meaning defined in detailed PMBus command description PMBus STATUS_BYTE command ASC Text Characters Part II ¶22.2.1 ASCII ISO/IEC 8859-1 [A05] LTC (0x4C5443) where N = b[15:11] and Y = b[10:0], both two’s compliment binary integers Rev. 0 For more information www.analog.com 53 LTM4664A DUAL 25A/30A PSM OPERATION FIGURE 11 THRU FIGURE 28 PMBus PROTOCOLS S START CONDITION Sr REPEATED START CONDITION Rd READ (BIT VALUE OF 1) Wr WRITE (BIT VALUE OF 0) A ACKNOWLEDGE (THIS BIT POSITION MAY BE 0 FOR AN ACK OR 1 FOR A NACK) P STOP CONDITION PEC PACKET ERROR CODE MASTER TO SLAVE SLAVE TO MASTER ... CONTINUATION OF PROTOCOL 4664A F11 Figure 11. PMBus Packet Protocol Diagram Element Key 1 7 S 1 1 SLAVE ADDRESS Rd/Wr A 1 P 4664A F12 Figure 12. Quick Command Protocol 1 7 S 1 1 8 1 1 SLAVE ADDRESS Wr A COMMAND CODE A P 4664A F13 Figure 13. Send Byte Protocol 1 S 7 1 1 8 1 SLAVE ADDRESS Wr A COMMAND CODE A 8 1 1 PEC A P 4664A F14 Figure 14. Send Byte Protocol with PEC 1 S 7 1 1 8 1 SLAVE ADDRESS Wr A COMMAND CODE A 8 1 1 DATA BYTE A P 4664A F15 Figure 15. Write Byte Protocol 1 S 7 1 1 8 1 SLAVE ADDRESS Wr A COMMAND CODE A 8 1 8 1 1 DATA BYTE A PEC A P 4664A F16 Figure 16. Write Byte Protocol with PEC 1 S 7 1 1 8 1 SLAVE ADDRESS Wr A COMMAND CODE A 8 1 8 1 1 DATA BYTE A DATA BYTE A P 4664A F17 Figure 17. Write Word Protocol 1 S 7 1 1 8 1 SLAVE ADDRESS Wr A COMMAND CODE A 8 1 8 1 8 1 1 DATA BYTE A DATA BYTE A PEC A P 4664A F18 Figure 18. Write Word Protocol with PEC 54 Rev. 0 For more information www.analog.com LTM4664A DUAL 25A/30A PSM OPERATION 1 7 S 1 1 8 1 1 1 7 1 SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A 8 1 1 DATA BYTE A P 4664A F19 Figure 19. Read Byte Protocol 1 S 7 1 1 8 1 1 7 1 8 1 DATA BYTE A 1 SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A PEC 1 1 A P 4664A F20 Figure 20. Read Byte Protocol with PEC 1 S 7 1 1 8 1 1 SLAVE ADDRESS Wr A COMMAND CODE A 7 1 1 Sr SLAVE ADDRESS Rd A 8 1 DATA BYTE LOW A 1 1 DATA BYTE HIGH A 8 P 4664A F21 Figure 21. Read Word Protocol 1 S 7 1 1 8 1 1 7 1 1 SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A 8 1 DATA BYTE LOW A 8 1 DATA BYTE HIGH A 8 1 1 PEC A P 4664A F22 Figure 22. Read Word Protocol with PEC 1 S 7 1 1 8 1 1 7 1 1 SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A 8 1 BYTE COUNT = N A 8 1 8 1 … 8 1 1 DATA BYTE 1 A DATA BYTE 2 A … DATA BYTE N A P … 4664A F23 Figure 23. Block Read Protocol 1 S 7 1 1 8 1 1 7 1 1 SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A 8 1 BYTE COUNT = N A 8 1 8 1 … 8 1 8 1 1 DATA BYTE 1 A DATA BYTE 2 A … DATA BYTE N A PEC A P … 4664A F24 Figure 24. Block Read Protocol with PEC Rev. 0 For more information www.analog.com 55 LTM4664A DUAL 25A/30A PSM OPERATION 1 S 7 1 1 8 1 8 1 SLAVE ADDRESS Wr A COMMAND CODE A BYTE COUNT = M A 8 1 DATA BYTE 2 1 7 1 8 A … 1 Sr SLAVE ADDRESS Rd A 8 1 DATA BYTE 1 A … 1 A … DATA BYTE M 8 1 BYTE COUNT = N A 8 1 1 DATA BYTE 1 A … 8 1 … 8 1 1 DATA BYTE 2 A … DATA BYTE N A P 4664A F25 Figure 25. Block Write – Block Read Process Call 1 S 7 1 1 8 1 8 1 SLAVE ADDRESS Wr A COMMAND CODE A BYTE COUNT = M A 8 1 DATA BYTE 2 1 7 1 8 A … 1 Sr SLAVE ADDRESS Rd A 8 1 DATA BYTE 1 A … 1 DATA BYTE M 8 A … 1 BYTE COUNT = N A 8 1 1 DATA BYTE 1 A … 8 1 … 8 1 8 1 1 DATA BYTE 2 A … DATA BYTE N A PEC A P 4678A F22 Figure 26. Block Write – Block Read Process Call with PEC 1 7 1 1 8 1 1 S ALERT RESPONSE Rd A DEVICE ADDRESS A ADDRESS P 4664A F27 Figure 27. Alert Response Address Protocol 1 7 1 1 8 1 S ALERT RESPONSE Rd A DEVICE ADDRESS A ADDRESS 8 1 1 PEC A P 4664A F28 Figure 28. Alert Response Address Protocol with PEC 56 Rev. 0 For more information www.analog.com LTM4664A PMBus COMMAND SUMMARY PMBus COMMANDS Table 7 lists supported PMBus commands and manufacturer specific commands. A complete description of these commands can be found in the “PMBus Power System Mgt Protocol Specification – Part II – Revision 1.2”. Users are encouraged to reference this specification. Exceptions or manufacturer specific implementations are listed in Table 7. Floating point values listed in the “DEFAULT VALUE” column are either Linear 16-bit Signed (PMBus Section 8.3.1) or Linear_5s_11s (PMBus Section 7.1) format, whichever is appropriate for the command. All commands from 0xD0 through 0xFF not listed in Table 7 are implicitly reserved by the manufacturer. Users should avoid blind writes within this range of commands to avoid undesired operation of the part. All commands from 0x00 through 0xCF not listed in Table 7 are implicitly not supported by the manufacturer. Attempting to access non-supported or reserved commands may result in a CML command fault event. All output voltage settings and measurements are based on the VOUT_MODE setting of 0x14. This translates to an exponent of 2–12. If PMBus commands are received faster than they are being processed, the part may become too busy to handle new commands. In these circumstances the part follows the protocols defined in the PMBus Specification v1.2, Part II, Section 10.8.7, to communicate that it is busy. The part includes handshaking features to eliminate busy errors and simplify error handling software while ensuring robust communication and system behavior. Please refer to the subsection titled PMBus Communication and Command Processing in the Dual 25A/30A PSM Applications Information section for further details. Table 7. PMBus Commands Summary (Note: The Data Format Abbreviations are Detailed in Table 8) COMMAND NAME CMD CODE DESCRIPTION PAGE 0x00 Provides integration with multi-page PMBus devices. R/W Byte N Reg OPERATION 0x01 Operating mode control. On/off, margin high and margin low. R/W Byte Y Reg ON_OFF_CONFIG 0x02 RUN pin and PMBus bus on/off command configuration. R/W Byte Y Reg CLEAR_FAULTS 0x03 Clear any fault bits that have been set. Send Byte N PAGE_PLUS_WRITE 0x05 Write a command directly to a specified page. W Block N 90 PAGE_PLUS_READ 0x06 Read a command directly from a specified page. Block R/W N 90 WRITE_PROTECT 0x10 Level of protection provided by the device against accidental changes. R/W Byte N STORE_USER_ALL 0x15 Store user operating memory to EEPROM. Send Byte RESTORE_USER_ALL 0x16 Restore user operating memory from EEPROM. Send Byte CAPABILITY 0x19 Summary of PMBus optional communication protocols supported by this device. R Byte N Reg SMBALERT_MASK 0x1B Mask ALERT activity Block R/W Y Reg VOUT_MODE 0x20 Output voltage format and exponent (2–12). VOUT_COMMAND 0x21 VOUT_MAX 0x24 TYPE DATA PAGED FORMAT UNITS NVM Reg DEFAULT VALUE PAGE 0x00 90 Y 0x80 94 Y 0x1E 94 NA 119 Y 0x00 91 N NA 130 N NA 130 0xB0 118 See CMD 119 2–12 100 Y R Byte Y Reg Nominal output voltage set point. R/W Word Y L16 V Y 1.0 0x1000 101 Upper limit on the commanded output voltage including VOUT_MARGIN_HI. R/W Word Y L16 V Y 1.8 0x1CCD 100 0x14 Rev. 0 For more information www.analog.com 57 LTM4664A PMBus COMMAND SUMMARY COMMAND NAME CMD CODE DESCRIPTION VOUT_MARGIN_HIGH 0x25 Margin high output voltage set point. Must be greater than VOUT_COMMAND. R/W Word Y L16 V Y 1.05 0x10CD 101 VOUT_MARGIN_LOW 0x26 Margin low output voltage set point. Must be less than VOUT_COMMAND. R/W Word Y L16 V Y 0.95 0x0F33 101 VOUT_TRANSITION_ RATE 0X27 Rate the output changes when VOUT commanded to a new value. R/W Word Y L11 V/ms Y 0.25 0x8042 107 FREQUENCY_SWITCH 0x33 Switching frequency of the controller. R/W Word N L11 kHz Y 350k 0xFABC 98 VIN_ON 0x35 Input voltage at which the unit should start R/W Word power conversion. N L11 V Y 4.75 0xCA60 99 VIN_OFF 0x36 Input voltage at which the unit should stop power conversion. R/W Word N L11 V Y 4.5 0xCA40 99 VOUT_OV_FAULT_LIMIT 0x40 Output overvoltage fault limit. R/W Word Y L16 V Y 1.1 0x119A 100 VOUT_OV_FAULT_ RESPONSE 0x41 Action to be taken by the device when an output overvoltage fault is detected. R/W Byte Y Reg Y 0xB8 109 VOUT_OV_WARN_LIMIT 0x42 Output overvoltage warning limit. R/W Word Y L16 V Y 1.075 0x1133 100 VOUT_UV_WARN_LIMIT 0x43 Output undervoltage warning limit. R/W Word Y L16 V Y 0.925 0x0ECD 101 VOUT_UV_FAULT_LIMIT 0x44 Output undervoltage fault limit. R/W Word Y L16 V Y 0.9 0x0E66 101 VOUT_UV_FAULT_ RESPONSE 0x45 Action to be taken by the device when an output undervoltage fault is detected. R/W Byte Y Reg Y 0xB8 110 IOUT_OC_FAULT_LIMIT 0x46 Output overcurrent fault limit. R/W Word Y L11 Y 40 0xE280 103 IOUT_OC_FAULT_ RESPONSE 0x47 Action to be taken by the device when an output overcurrent fault is detected. R/W Byte Y Reg Y 0x00 112 IOUT_OC_WARN_LIMIT 0x4A Output overcurrent warning limit. R/W Word Y L11 A Y 30.0 0xDBC0 104 OT_FAULT_LIMIT 0x4F External overtemperature fault limit. R/W Word Y L11 C Y 128 0xF200 105 OT_FAULT_RESPONSE 0x50 Action to be taken by the device when an external overtemperature fault is detected, R/W Byte Y Reg Y 0xB8 114 OT_WARN_LIMIT 0x51 External overtemperature warning limit. R/W Word Y L11 C Y 125 0xEBE8 105 UT_FAULT_LIMIT 0x53 External undertemperature fault limit. R/W Word Y L11 C Y –45 0xE530 106 UT_FAULT_RESPONSE 0x54 Action to be taken by the device when an external undertemperature fault is detected. R/W Byte Y Reg Y 0xB8 114 VIN_OV_FAULT_LIMIT 0x55 Input supply overvoltage fault limit. R/W Word N L11 Y 15.5 0xD3E0 100 VIN_OV_FAULT_ RESPONSE 0x56 Action to be taken by the device when an input overvoltage fault is detected. R/W Byte Y Reg Y 0x80 109 VIN_UV_WARN_LIMIT 0x58 Input supply undervoltage warning limit. R/W Word N L11 V Y 4.68 0xCA53 99 IIN_OC_WARN_LIMIT 0x5D Input supply overcurrent warning limit. R/W Word N L11 A Y 10.0 0xD280 104 58 TYPE DATA PAGED FORMAT UNITS NVM A V DEFAULT VALUE PAGE Rev. 0 For more information www.analog.com LTM4664A PMBus COMMAND SUMMARY COMMAND NAME CMD CODE DESCRIPTION TON_DELAY 0x60 Time from RUN and/or Operation on to output rail turn-on. R/W Word Y L11 ms Y 0.0 0x8000 106 TON_RISE 0x61 Time from when the output starts to rise until the output voltage reaches the VOUT commanded value. R/W Word Y L11 ms Y 3 0xC300 106 TON_MAX_FAULT_LIMIT 0x62 Maximum time from the start of TON_RISE for VOUT to cross the VOUT_UV_FAULT_LIMIT. R/W Word Y L11 ms Y 5 0xCA80 107 TON_MAX_FAULT_ RESPONSE 0x63 Action to be taken by the device when a TON_ MAX_FAULT event is detected. R/W Byte Y Reg Y 0xB8 112 TOFF_DELAY 0x64 Time from RUN and/or Operation off to the R/W Word start of TOFF_FALL ramp. Y L11 ms Y 0.0 0x8000 107 TOFF_FALL 0x65 Time from when the output starts to fall until the output reaches zero volts. R/W Word Y L11 ms Y 3 0xC300 107 TOFF_MAX_WARN_ LIMIT 0x66 Maximum allowed time, after TOFF_FALL completed, for the unit to decay below 12.5%. R/W Word Y L11 ms Y 0 0x8000 108 STATUS_BYTE 0x78 One byte summary of the unit’s fault condition. R/W Byte Y Reg NA 120 STATUS_WORD 0x79 Two byte summary of the unit’s fault condition. R/W Word Y Reg NA 121 STATUS_VOUT 0x7A Output voltage fault and warning status. R/W Byte Y Reg NA 121 STATUS_IOUT 0x7B Output current fault and warning status. R/W Byte Y Reg NA 122 STATUS_INPUT 0x7C Input supply fault and warning status. R/W Byte N Reg NA 122 STATUS_TEMPERATURE 0x7D External temperature fault and warning status for READ_TEMERATURE_1. R/W Byte Y Reg NA 123 STATUS_CML 0x7E Communication and memory fault and warning status. R/W Byte N Reg NA 123 STATUS_MFR_SPECIFIC 0x80 Manufacturer specific fault and state information. R/W Byte Y Reg NA 124 READ_VIN 0x88 Measured input supply voltage. R Word N L11 V NA 127 READ_IIN 0x89 Measured input supply current. R Word N L11 A NA 127 READ_VOUT 0x8B Measured output voltage. R Word Y L16 V NA 127 READ_IOUT 0x8C Measured output current. R Word Y L11 A NA 127 READ_TEMPERATURE_1 0x8D External temperature sensor temperature. This is the value used for all temperature related processing, including IOUT_CAL_GAIN. R Word Y L11 C NA 127 READ_TEMPERATURE_2 0x8E Internal die junction temperature. Does not affect any other commands. R Word N L11 C NA 127 READ_FREQUENCY 0x95 Measured PWM switching frequency. R Word Y L11 Hz NA 127 READ_POUT 0x96 Measured output power R Word Y L11 W N/A 127 READ_PIN 0x97 Calculated input power R Word Y L11 W N/A 128 PMBus_REVISION 0x98 PMBus revision supported by this device. Current revision is 1.2. R Byte N Reg 0x22 118 MFR_ID 0x99 The manufacturer ID of the LTM4664A in ASCII. R String N ASC LTC 118 TYPE DATA PAGED FORMAT UNITS NVM DEFAULT VALUE PAGE Rev. 0 For more information www.analog.com 59 LTM4664A PMBus COMMAND SUMMARY COMMAND NAME CMD CODE DESCRIPTION MFR_MODEL 0x9A Manufacturer part number in ASCII. R String N ASC MFR_VOUT_MAX 0xA5 Maximum allowed output voltage including VOUT_OV_FAULT_LIMIT. R Word Y L16 MFR_PIN_ACCURACY 0xAC Returns the accuracy of the READ_PIN command R Byte N % USER_DATA_00 0xB0 OEM RESERVED. Typically used for part serialization. R/W Word N Reg USER_DATA_01 0xB1 Manufacturer reserved for LTpowerPlay®. R/W Word Y USER_DATA_02 0xB2 OEM RESERVED. Typically used for part serialization R/W Word N USER_DATA_03 0xB3 An NVM word available for the user. R/W Word Y USER_DATA_04 0xB4 An NVM word available for the user. R/W Word N MFR_EE_UNLOCK 0xBD Contact factory. 135 MFR_EE_ERASE 0xBE Contact factory. 135 MFR_EE_DATA 0xBF Contact factory. MFR_CHAN_CONFIG 0xD0 Configuration bits that are channel specific. R/W Byte Y Reg Y 0x1D 92 MFR_CONFIG_ALL 0xD1 General configuration bits. R/W Byte N Reg Y 0x21 93 MFR_FAULT_ PROPAGATE 0xD2 Configuration that determines which faults are propagated to the FAULT pin. R/W Word Y Reg Y 0x6993 115 MFR_PWM_COMP 0xD3 PWM loop compensation configuration R/W Byte Y Reg Y 0x28 96 MFR_PWM_MODE 0xD4 Configuration for the PWM engine. R/W Byte Y Reg Y 0xC7 95 MFR_FAULT_RESPONSE 0xD5 Action to be taken by the device when the FAULT pin is externally asserted low. R/W Byte Y Reg Y 0xC0 113 MFR_OT_FAULT_ RESPONSE 0xD6 Action to be taken by the device when an internal overtemperature fault is detected. R Byte N Reg 0xC0 113 MFR_IOUT_PEAK 0xD7 Report the maximum measured value of READ_ IOUT since last MFR_CLEAR_PEAKS. R Word Y L11 NA 128 MFR_ADC_CONTROL 0xD8 ADC telemetry parameter selected for repeated fast ADC read back R/W Byte N Reg 0x00 129 MFR_RETRY_DELAY 0xDB Retry interval during FAULT retry mode. R/W Word Y L11 ms Y 250.0 0xF3E8 108 MFR_RESTART_DELAY 0xDC Minimum time the RUN pin is held low by the LTM4664A. R/W Word Y L11 ms Y 150 0xF258 108 MFR_VOUT_PEAK 0xDD Maximum measured value of READ_VOUT since last MFR_CLEAR_PEAKS. R Word Y L16 V NA 128 MFR_VIN_PEAK 0xDE Maximum measured value of READ_VIN since last MFR_CLEAR_PEAKS. R Word N L11 V NA 128 MFR_TEMPERATURE_1_ PEAK 0xDF Maximum measured value of external Temperature (READ_TEMPERATURE_1) since last MFR_CLEAR_PEAKS. R Word Y L11 C NA 128 MFR_READ_IIN_PEAK 0xE1 Maximum measured value of READ_IIN command since last MFR_CLEAR_PEAKS R Word N L11 A NA 128 MFR_CLEAR_PEAKS 0xE3 Clears all peak values. NA 120 MFR_READ_ICHIP 0xE4 Measured supply current of the SVIN pin L11 A NA 128 60 TYPE DATA PAGED FORMAT UNITS NVM DEFAULT VALUE PAGE LTM4664 118 1.8 0x1CCD 102 5.0% 128 Y NA 118 Reg Y NA 118 Reg Y NA 118 Reg Y 0x0000 118 Reg Y 0x0000 118 V 135 Send Byte N R Word N A Rev. 0 For more information www.analog.com LTM4664A PMBus COMMAND SUMMARY COMMAND NAME CMD CODE DESCRIPTION TYPE DATA PAGED FORMAT UNITS NVM MFR_IOUT_CAL_GAIN 0xDA The ratio of the voltage at the current sense pins to the sensed current. For devices using a fixed current sense resistor. It is the resistance value in mohm. OxAA8B set at factory R Word Y L11 MFR_PADS 0xE5 Digital status of the I/O pads. R Word N Reg Y MFR_ADDRESS 0xE6 Sets the 7-bit I2C address byte. Y MFR_SPECIAL_ID 0xE7 Manufacturer code representing the LTM4664A and revision MFR_IIN_CAL_GAIN 0xE8 MFR_FAULT_LOG_ STORE R/W Byte N Reg R Word N Reg The resistance value of the input current sense element in mΩ. R/W Word N L11 0xEA Command a transfer of the fault log from RAM to EEPROM. Send Byte MFR_INFO 0xB6 Contact factory. MFR_FAULT_LOG_ CLEAR 0xEC Initialize the EEPROM block reserved for fault logging. MFR_FAULT_LOG 0xEE MFR_COMMON DEFAULT VALUE PAGE 0.350mΩ 102 NA 124 0x4F 92 0x4100 118 2.0 0xC200 104 N NA 131 Send Byte N NA 135 Fault log data bytes. R Block N Reg NA 131 0xEF Manufacturer status bits that are common across multiple LTC chips. R Byte N Reg NA 125 MFR_COMPARE_USER_ ALL 0xF0 Compares current command contents with NVM. Send Byte N NA 130 MFR_TEMPERATURE_2_ PEAK 0xF4 Peak internal die temperature since last MFR_ CLEAR_PEAKS. R Word N L11 NA 129 MFR_PWM_CONFIG 0xF5 Set numerous parameters for the DC/DC controller including phasing. R/W Byte N Reg Y 0x10 97 MFR_IOUT_CAL_GAIN_ TC 0xF6 Temperature coefficient of the current sensing element. R/W Word Y CF ppm/ ˚C Y 3900 0x0F3C 102 MFR_RVIN 0xF7 The resistance value of the VIN pin filter element in mΩ. Set at Factory R Word N L11 mΩ N 1000 0x03E8 99 MFR_TEMP_1_GAIN 0xF8 Sets the slope of the external temperature sensor. R/W Word Y CF Y 0.9 0x3FAE 105 MFR_TEMP_1_OFFSET 0xF9 Sets the offset of the external temperature sensor with respect to –273.1°C R/W Word Y L11 Y 0.0 0x8000 105 MFR_RAIL_ADDRESS 0xFA Common address for PolyPhase outputs to adjust common parameters. R/W Byte Y Reg Y 0x80 92 MFR_REAL_TIME 0xFB 48-bit share-clock counter value. R Block N CF NA xx MFR_RESET 0xFD Commanded reset without requiring a power down. Send Byte N NA 94 mΩ Y 135 Y C C Note 1. Commands indicated with Y in the NVM column indicate that these commands are stored and restored using the STORE_USER_ALL and RESTORE_USER_ALL commands, respectively. Note 2. Commands with a default value of NA indicate “not applicable”. Commands with a default value of FS indicate “factory set on a per part basis”. Note 3. The LTM4664A contains additional commands not listed in Table 7. Reading these commands is harmless to the operation of the IC; however, the contents and meaning of these commands can change without notice. Note 4. Some of the unpublished commands are read-only and will generate a CML bit 6 fault if written. Note 5. Writing to commands not published in Table 7 is not permitted. Note 6. The user should not assume compatibility of commands between different parts based upon command names. Always refer to the manufacturer’s data sheet for each part for a complete definition of a command’s function. LTC strives to keep command functionality compatible between all LTC devices. Differences may occur to address specific product requirements. Rev. 0 For more information www.analog.com 61 LTM4664A PMBus COMMAND SUMMARY Table 8. Data Format Abbreviations L11 Linear_5s_11s PMBus data field b[15:0] Value = Y • 2N where N = b[15:11] is a 5-bit two’s complement integer and Y = b[10:0] is an 11-bit two’s complement integer Example: For b[15:0] = 0x9807 = ‘b10011_000_0000_0111 Value = 7 • 2–13 = 854 • 10–6 From “PMBus Spec Part II: Paragraph 7.1” L16 Linear_16u PMBus data field b[15:0] Value = Y • 2N where Y = b[15:0] is an unsigned integer and N = VOUT_MODE_PARAMETER is a 5-bit two’s complement exponent that is hardwired to –12 decimal Example: For b[15:0] = 0x9800 = ‘b1001_1000_0000_0000 Value = 19456 • 2–12 = 4.75 From “PMBus Spec Part II: Paragraph 8.2” Reg Register PMBus data field b[15:0] or b[7:0]. Bit field meaning is defined in detailed PMBus Command Description. L16 Integer Word PMBus data field b[15:0] Value = Y where Y = b[15:0] is a 16-bit unsigned integer Example: For b[15:0] = 0x9807 = ‘b1001_1000_0000_0111 Value = 38919 (decimal) CF Custom Format Value is defined in detailed PMBus Command Description. This is often an unsigned or two’s complement integer scaled by an MFR specific constant. ASC ASCII Format A variable length string of text characters conforming to ISO/IEC 8859-1 standard. 62 Rev. 0 For more information www.analog.com LTM4664A DUAL 25A/30A PSM APPLICATIONS INFORMATION VIN TO VOUT STEP-DOWN RATIOS OUTPUT CAPACITORS There are restrictions in the maximum VIN and VOUT stepdown ratio that can be achieved for a given input voltage. Each output of the LTM4664A PSM is capable of 95% duty cycle at 500kHz, but the VIN to VOUT minimum dropout is still a function of its load current and will limit output current capability related to high duty cycle on the topside switch. The LTM4664A PSM channel outputs are designed for low output voltage ripple noise and good transient response. The bulk output capacitors defined as COUT are chosen with low enough effective series resistance (ESR) to meet the output voltage ripple and transient requirements. COUT can be a low ESR tantalum capacitor, a low ESR polymer capacitor or ceramic capacitor. The typical output capacitance range for each output is from 400µF to 1000µF. Additional output filtering may be required by the system designer, if further reduction of output ripple or dynamic transient spikes is required. Table 12 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 12.5A to 25A step, 12A/µs transient each channel. Table 12 optimizes total equivalent ESR and total bulk capacitance to optimize the transient performance. Stability criteria are considered in the Table 12 matrix, and the LTpowerCAD Design Tool will be provided for stability analysis. Multiphase operation reduces effective output ripple as a function of the number of phases. Application Note 77 discusses this noise reduction versus output ripple current cancellation, but the output capacitance should be considered carefully as a function of stability and transient response. The LTpowerCAD Design Tool can calculate the output ripple reduction as the number of implemented phases increases by N times. A small value 10Ω resistor can be placed in series from VOUTn to the VOSNS0+ pin to allow for a bode plot analyzer to inject a signal into the control loop and validate the regulator stability. The LTM4664A PSM stability compensation can be adjusted using two external capacitors, and the MFR_PWM_COMP commands. Minimum on-time tON(MIN) is another consideration in operating at a specified duty cycle while operating at a certain frequency due to the fact that tON(MIN) < D/fSW, where D is duty cycle and fSW is the switching frequency. tON(MIN) is specified in the electrical parameters as 60ns. See Note 6 in the Electrical Characteristics section for output current guideline. Since the LTM4664A front end 4:1 divider feeds the two 25A/30A PSM channels with a VOUT2 range of 7.5V to 14.5V, there should be no minimum on time issue. INPUT CAPACITORS The LTM4664A PSM channels should be connected to a low AC impedance DC source. For the regulator input, four 22µF input ceramic capacitors are used to handle the RMS ripple current. A 47µF to 100µF surface mount aluminum electrolytic bulk capacitor can be used for more input bulk capacitance. This bulk input capacitor is only needed if the input source impedance is compromised by long inductive leads, traces or not enough source capacitance. If low impedance power planes are used, then this bulk capacitor is not needed. For a buck converter, the switching duty-cycle can be estimated as: VOUTn VINn Without considering the inductor current ripple, for each output, the RMS current of the input capacitor can be estimated as: Dn = IOUTn (MAX) • Dn • (1−Dn ) η% In the above equation, η% is the estimated efficiency of the power module. The bulk capacitor can be a switcher-rated electrolytic aluminum capacitor, or a polymer capacitor. ICINn (RMS) = LIGHT LOAD CURRENT OPERATION The LTM4664A PSM channels have two modes of operation including high efficiency, discontinuous conduction mode or forced continuous conduction mode. The mode of operation is configured by bit 0 of the MFR_PWM_MODEn command (discontinuous conduction is always the start-up mode, forced continuous is the default running mode). If a channel is enabled for discontinuous mode operation, the inductor current is not allowed to reverse. The reverse Rev. 0 For more information www.analog.com 63 LTM4664A DUAL 25A/30A PSM APPLICATIONS INFORMATION current comparator, IREV, turns off the bottom MOSFET (MBn) just before the inductor current reaches zero, preventing it from reversing and going negative. Thus, the controller can operate in discontinuous (pulse-skipping) operation. In forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. The peak inductor current is determined solely by the voltage on the COMP_Cna pin. In this mode, the efficiency at light loads is lower than in discontinuous mode operation. However, continuous mode exhibits lower output ripple and less interference with audio circuitry. Forced continuous conduction mode may result in reverse inductor current, which can cause the input supply to boost. The VIN_OV_FAULT_LIMIT can detect this on VIN3 and turn off the offending channel. However, this fault is based on an ADC read and can nominally take up to 100ms to detect. If there is a concern about the input supply boosting, keep the part in discontinuous conduction operation. SWITCHING FREQUENCY AND PHASE The switching frequency of the LTM4664A’s PSM channels is established by its analog phase-locked-loop (PLL) locking on to the clock present at the module’s SYNC pin. The clock waveform on the SYNC pin can be generated by the LTM4664A’s PSM internal circuitry when an external pull-up resistor to 3.3V (e.g., VDD33) is provided, in combination with the LTM4664A PSM control IC’s FREQUENCY_ SWITCH command being set to one of the following supported values: 250kHz, 350kHz, 425kHz, 500kHz, 575kHz, 650kHz, 750kHz. In this configuration, the module is called a “sync master”: (using the factory-default setting of MFR_ CONFIG_ALL[4]  =  0b), SYNC becomes a bidirectional open-drain pin, and the LTM4664A PSM pulls SYNC logic low for nominally 500ns at a time, at the prescribed clock rate. The SYNC signal can be bused to other LTM4664A PSM device modules (configured as “sync slaves”), for purposes of synchronizing switching frequencies of multiple modules within a system—but only one LTM4664A PSM devices should be configured as a “sync master”; the other LTM4664A(s) should be configured as “sync slaves”. The most straightforward way is to set its FREQUENCY_ SWITCH command to 0x0000 and 64 MFR_CONFIG_ALL[4] = 1b. This can be easily implemented with resistor pin-strap settings on the FSWPH_ CFG pin (see Table 3). Using MFR_CONFIG_ALL[4] = 1b, the LTM4664As SYNC pin becomes a high impedance input, only—i.e., it does not drive SYNC low. The module synchronizes its frequency to that of the clock applied to its SYNC pin. The only shortcoming of this approach is: in the absence of an externally applied clock, the switching frequency of the module will default to the low end of its frequency-synchronization capture range (~225kHz). If fault-tolerance to the loss of an externally applied SYNC clock is desired, the FREQUENCY_SWITCH command of a “sync slave” can be left at the nominal target switching frequency of the application, and not 0x0000 However, it is then still necessary to configure MFR_CONFIG_ ALL[4] = 1b. With this combination of configurations, the LTM4664A’s SYNC pin becomes a high impedance input and the module synchronizes its frequency to that of the externally applied clock, provided that the frequency of the externally applied clock exceeds ~½. of the target frequency (FREQUENCY_SWITCH). If the SYNC clock is absent, the module responds by operating at its target frequency, indefinitely. If and when the SYNC clock is restored, the module automatically phase-locks to the SYNC clock as normal. The only shortcoming of this approach is: the EEPROM must be configured per above guidance; resistor pin-strapping options on the FSWPH_CFG pin alone cannot provide fault-tolerance to the absence of the SYNC clock. The FREQUENCY_SWITCH register can be altered via I2C commands, but only when switching action is disengaged, i.e., the module’s outputs are turned off. The FREQUENCY_ SWITCH command takes on the value stored in NVM at VINS3 power-up, but is overridden according to a resistor pin-strap applied between the FSWPH_CFG pin and SGND only if the module is configured to respect resistor pin-strap settings (MFR_CONFIG_ALL[6] = 0b). Table 3 highlights available resistor pin-strap and corresponding FREQUENCY_SWITCH settings. The relative phasing of all active channels in a PolyPhase rail should be optimally phased. The relative phasing of each rail is 360°/n, where n is the number of phases in the rail. MFR_PWM_CONFIG[2:0] configures channel relative Rev. 0 For more information www.analog.com LTM4664A DUAL 25A/30A PSM APPLICATIONS INFORMATION phasing with respect to the SYNC pin. Phase relationship values are indicated with 0° corresponding to the falling edge of SYNC being coincident with the turn-on of the top MOSFETs, MTn. The MFR_PWM_CONFIG command can be altered via I2C commands, but only when switching action is disengaged, i.e., the module’s outputs are turned off. The MFR_PWM_CONFIG command takes on the value stored in NVM at SVIN power-up, but is overridden according to a resistor pin-strap applied between the FSWPH_CFG pin and SGND only if the module is configured to respect resistor pin-strap settings (MFR_CONFIG_ALL[6] = 0b). Table 3 highlights available resistor pin-strap and corresponding MFR_PWM_CONFIG[2:0] settings. Some combinations of FREQUENCY_SWITCH and MFR_PWM_CONFIG[2:0] are not available by resistor pin-strapping the FSWPH_CFG pin. All combinations of supported values for FREQUENCY_SWITCH and MFR_ PWM_CONFIG[2:0] can be configured by NVM programming—or, I2C transactions, provided switching action is disengaged, i.e., the module’s outputs are turned off. Care must be taken to minimize capacitance on SYNC to assure that the pull-up resistor versus the capacitor load has a low enough time constant for the application to form a “clean” clock. (See “Open-Drain Pins”, later in this section.) When an LTM4664A PSM is configured as a sync slave, it is permissible for external circuitry to drive the SYNC pin from a current-limited source (less than 10mA), rather than using a pull-up resistor. Any external circuitry must not drive high with arbitrarily low impedance at SVIN power-up, because the SYNC output can be low impedance until NVM contents have been downloaded to RAM. Recommended LTM4664A PSM switching frequencies of operation for many common VIN-to-VOUT applications are indicated below. When the two channels of an LTM4664A PSM are stepping input voltage(s) down to output voltages whose recommended switching frequencies below are significantly different, operation at the higher of the two recommended switching frequencies is preferable, but minimum on-time must be considered. (See Minimum On-Time Considerations section.) Table 9. Recommended PSM Switching Frequency for Various VIN-to-VOUT Step-Down Scenarios V 7.5VIN 10VIN 12VIN 14.5VIN 250kHz 250kHz 250kHz 250kHz 350kHz 350kHz 350kHz 350kHz 0.5 0.7 0.8 0.9 1.0 1.2 1.5 OUTPUT CURRENT LIMIT PROGRAMMING The cycle-by-cycle current limit (= VISENSE/DCR) is proportional to COMP_Cn, which can be programmed from 1.45V to 2.2V using the PMBus command IOUT_OC_ FAULT_LIMIT. The LTM4664A PSM uses only the sub-milliohm sensing to detect current levels. See page103. The LTM4664A PSM has two ranges of current limit programming. The value of MFR_PWM_MODE[2] is reserved and the MFR_PWM_MODE[7], and IOUT_OC_FAULT_LIMIT are used to set the current limit level, see the section of the PMBus commands, the device can regulate output voltage with the peak current under the value of IOUT_OC_ FAULT_LIMIT in normal operation. In case of output current exceeding that current limit, a OC fault will be issued. Each of the IOUT_OC_FAULT_LIMIT ranges will effects the loop gain, and subsequently effects the loop stability, so setting the range of current limiting is a part of loop design. The LTpowerCAD Design Tool can be used to look at the loop stability changes if current limit is adjusted. The LTM4664A PSM will automatically update the current limit as the inductor temperature changes. Keep in mind this operation is on a cycle-by-cycle basis and is only a function of the peak inductor current. The average inductor current is monitored by the ADC converter and can provide a warning if too much average output current is detected. The overcurrent fault is detected when the COMP_Cn voltage hits the maximum value. The digital processor within the LTM4664A PSM provides the ability to either ignore the fault, shut down and latch off or shut down and retry indefinitely (hiccup). Refer to the overcurrent portion of the Dual 25A/30A PSM Operation section for more detail. The READ_POUT can be used to readback calculated output power. Rev. 0 For more information www.analog.com 65 LTM4664A DUAL 25A/30A PSM APPLICATIONS INFORMATION MINIMUM ON-TIME CONSIDERATIONS Minimum on-time, tON(MIN), is the smallest time duration that the LTM4664A PSM is capable of turning on the top MOSFET. It is determined by internal timing delays and the gate charge required to turn on the top MOSFET. Low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: tON(MIN) < VOUTn VINn • fOSC If the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. The output voltage will continue to be regulated, but the ripple voltage and current will increase. The minimum on-time for the LTM4664A is 60ns. VARIABLE DELAY TIME, SOFT-START AND OUTPUT VOLTAGE RAMPING The LTM4664A PSM must enter its run state prior to softstart. The RUN_Cn pins are released after the part initializes, and VINS3 is greater than the VIN_ON threshold and Stage 2 PGood pin releases the RUN_Cn pins. If multiple LTM4664As are used in an application, they should be configured to share the same RUN_Cn pins. They all hold their respective RUN_Cn pins low until all devices initialize and VINS3 exceeds the VIN_ON threshold for all devices. The SHARE_CLK pin assures all the devices connected to the signal use the same time base. After the RUN_Cn pin releases, the controller waits for the user-specified turn-on delay (TON_DELAYn) prior to initiating an output voltage ramp. Multiple LTM4664As and other LTC parts can be configured to start with variable delay times. To work correctly, all devices use the same timing clock (SHARE_CLK) and all devices must share the RUN_Cn pin. This allows the relative delay of all parts to be synchronized. The actual variation in the delay will be dependent on the highest clock rate of the devices connected to the SHARE_CLK pin (all Analog Devices ICs are configured to allow the fastest SHARE_CLK signal to control the timing of all devices). The SHARE_CLK signal can be 66 ±10% in frequency, thus the actual time delays will have some variance. Soft-start is performed by actively regulating the load voltage while digitally ramping the target voltage from 0V to the commanded voltage set point. The rise time of the voltage ramp can be programmed using the TON_RISEn command to minimize inrush currents associated with the start-up voltage ramp. The soft-start feature is disabled by setting TON_RISEn to any value less than 0.250ms. The LTM4664A PSM performs the necessary math internally to assure the voltage ramp is controlled to the desired slope. However, the voltage slope can not be any faster than the VOUTn fundamental limits of the power stage. The number of tON(MIN) < steps in the ramp is equal to TON_RISE/0.1ms. Therefore, the shorter the TON_RISEn time setting, the more discrete steps in the soft-start ramp appear. The LTM4664A PSM PWM always operates in discontinuous mode during the TON_RISEn operation. In discontinuous mode, the bottom MOSFET (MBn) is turned off as soon as reverse current is detected in the inductor. This allows the regulator to start up into a prebiased load. There is no analog tracking feature in the LTM4664A PSM; however, two outputs can be given the same TON_RISEn and TON_DELAYn times to achieve ratiometric rail tracking. Because the RUNn pins are released at the same time and both units use the same time base (SHARE_CLK), the outputs track very closely. If the circuit is in a PolyPhase configuration, all timing parameters must be the same. DIGITAL SERVO MODE For maximum accuracy in the regulated output voltage, enable the digital servo loop by asserting bit 6 of the MFR_PWM_MODE command. In digital servo mode, the LTM4664A PSM will adjust the regulated output voltage based on the ADC voltage reading. Every 90ms the digital servo loop will step the LSB of the DAC (nominally 1.375mV or 0.6875mV depending on the voltage range bit) until the output is at the correct ADC reading. At power-up this mode engages after TON_MAX_FAULT_LIMIT unless the limit is set to 0 (infinite). If the TON_MAX_ FAULT_LIMIT is set to  0 (infinite), the servo begins after TON_RISE is complete and VOUT has exceeded the Rev. 0 For more information www.analog.com LTM4664A DUAL 25A/30A PSM APPLICATIONS INFORMATION VOUT_UV_FAULT_LIMIT. This same point in time is when the output changes from discontinuous to the programmed mode as indicated in MFR_PWM_MODE bit 0. Refer to Figure 29 for details on the VOUT waveform under time-based sequencing. If the TON_MAX_FAULT_LIMIT is set to a value greater than 0 and the TON_MAX_FAULT_ RESPONSE is set to ignore 0x00, the servo begins: 1. After the TON_RISE sequence is complete 2. After the TON_MAX_FAULT_LIMIT time is reached; and 3. After the VOUT_UV_FAULT_LIMIT has been exceeded or the IOUT_OC_FAULT_LIMIT is no longer active. If the TON_MAX_FAULT_LIMIT is set to a value greater than 0 and the TON_MAX_FAULT_RESPONSE is not set to ignore 0x00, the servo begins: 1. After the TON_RISE sequence is complete 2. After the TON_MAX_FAULT_LIMIT time has expired and both VOUT_UV_FAULT and IOUT_OC_FAULT are not present. The maximum rise time is limited to 1.3 seconds. In a PolyPhase configuration it is recommended only one of the control loops have the digital servo mode enabled. This will assure the various loops do not work against each other due to slight differences in the reference circuits. SOFT OFF (SEQUENCED OFF) In addition to a controlled start-up, the LTM4664A PSM also supports controlled turn-off. The TOFF_DELAY and TOFF_FALL functions are shown in Figure 30. TOFF_FALL is processed when the RUN pin goes low or if the part is commanded off. If the part faults off or FAULT_Cn is pulled low externally and the part is programmed to respond to this, the output will three-state rather than exhibiting a controlled ramp. The output will decay as a function of the load. The output voltage will operate as shown in Figure 30 as long as the part is in forced continuous mode and the TOFF_FALL time is sufficiently slow that the power stage can achieve the desired slope. The TOFF_FALL time can only be met if the power stage and controller can sink sufficient current to assure the output is at zero volts by the end of the fall time interval. If the TOFF_FALL time is set shorter than the time required to discharge the load capacitance, the output will not reach the desired zero volt state. At the end of TOFF_FALL, the controller will cease to sink current and VOUT will decay at the natural rate determined by the load impedance. If the controller is in discontinuous mode, the controller will not pull negative current and the output will be pulled low by the load, not the power stage. The maximum fall time is limited to 1.3 seconds. The shorter TOFF_FALL time is set, the larger the discrete steps in the TOFF_FALL ramp will appear. The number of steps in the ramp is equal to TOFF_FALL/0.1ms. DIGITAL SERVO MODE ENABLED FINAL OUTPUT VOLTAGE REACHED TON_MAX_FAULT_LIMIT DAC VOLTAGE ERROR (NOT TO SCALE) VOUT TON_DELAY TON_RISE TIME DELAY OF 200-400ms TIME VOUT TOFF_DELAY 4664A F29 Figure 29. Timing Controlled VOUT Rise TOFF_FALL TIME 4664A F30 Figure 30. TOFF_DELAY and TOFF_FALL Rev. 0 For more information www.analog.com 67 LTM4664A DUAL 25A/30A PSM APPLICATIONS INFORMATION UNDERVOLTAGE LOCKOUT The LTM4664A PSM is initialized by an internal threshold-based UVLO where VINS3 must be approximately 4V and INTVCC, VDD33, and VDD25 must be within approximately 20% of their regulated values. In addition, VDD33 must be within approximately 7% of the targeted value before the RUN_Cn pin is released. After the part has initialized, an additional comparator monitors VINS3. The VIN_ON threshold must be exceeded before the power sequencing can begin. When VINS3 drops below the VIN_ OFF threshold, the SHARE_CLK pin will be pulled low and VINS3 must increase above the VIN_ON threshold before the controller will restart. The normal start-up sequence will be allowed after the VIN_ON threshold is crossed. If FAULTB is held low when VINS3 is applied, ALERT will be asserted low even if the part is programmed to not assert ALERT when FAULTB is held low. If I2C communication occurs before the LTM4664A is out of reset and only a portion of the command is seen by the part, this can be interpreted as a CML fault. If a CML fault is detected, ALERT is asserted low. It is possible to program the contents of the NVM in the application if the VDD33 supply is externally driven directly to VDD33 or through EXTVCC. This will activate the digital portion of the LTM4664A PSM without engaging the high voltage sections. PMBus communications are valid in this supply configuration. If VINS3 has not been applied to the LTM4664A PSM, bit 3 (NVM Not Initialized) in MFR_COMMON will be asserted low. If this condition is detected, the part will only respond to addresses 5A and 5B. To initialize the part issue the following set of commands: global address 0x5B command 0xBD data 0x2B followed by global address 5B command 0xBD and data 0xC4. The part will now respond to the correct address. Configure the part as desired then issue a STORE_USER_ ALL. When VIN is applied a MFR_RESET command must be issued to allow the PWM to be enabled and valid ADC conversions to be read. pins can be pulled low by external sources indicating a fault in some other portion of the system. The fault response is configurable and allows the following options: Ignore n Shut Down Immediately—Latch Off n n Shut Down Immediately—Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY Refer to the PMBus section of the data sheet and the PMBus specification for more details. The OV response is automatic. If an OV condition is detected, TGn goes low and BGn is asserted. Fault logging is available on the LTM4664A PSM. The fault logging is configurable to automatically store data when a fault occurs that causes the unit to fault off. The header portion of the fault logging table contains peak values. It is possible to read these values at any time. This data will be useful while troubleshooting the fault. If the LTM4664A PSM internal temperature is in excess of 85°C, writes into the NVM (other than fault logging) are not recommended. The data will still be held in RAM, unless the 3.3V supply UVLO threshold is reached. If the die temperature exceeds 130°C all NVM communication is disabled until the die temperature drops below 120°C. OPEN-DRAIN PINS The LTM4664A PSM has the following open-drain pins: 3.3V Pins 1. FAULT_Cn 2. SYNC 3. SHARE_CLK 4. PGOOD_Cn 5V Pins (5V pins operate correctly when pulled to 3.3V.) 1. RUN_Cn FAULT DETECTION AND HANDLING 2. ALERT The LTM4664A FAULT_Cn pins are configurable to indicate a variety of faults including OV, UV, OC, OT, timing faults, and peak over current faults. In addition, the FAULT_Cn 3. SCL 68 4. SDA Rev. 0 For more information www.analog.com LTM4664A DUAL 25A/30A PSM APPLICATIONS INFORMATION All the above pins have on-chip pull-down transistors that can sink 3mA at 0.4V. The low threshold on the pins is 0.8V; thus, there is plenty of margin on the digital signals with 3mA of current. For 3.3V pins, 3mA of current is a 1.1k resistor. Unless there are transient speed issues associated with the RC time constant of the resistor pull-up and parasitic capacitance to ground, a 10k resistor or larger is generally recommended. For high speed signals such as the SDA, SCL and SYNC, a lower value resistor may be required. The RC time constant should be set to 1/3 to 1/5 the required rise time to avoid timing issues. For a 100pF load and a 400kHz PMBus communication rate, the rise time must be less than 300ns. The resistor pull-up on the SDA and SCL pins with the time constant set to 1/3 the rise time is: RPULLUP = tRISE =1k 3 •100pF The closest 1% resistor value is 1k. Be careful to minimize parasitic capacitance on the SDA and SCL pins to avoid communication problems. To estimate the loading capacitance, monitor the signal in question and measure how long it takes for the desired signal to reach approximately 63% of the output value. This is a one time constant. The SYNC pin has an on-chip pull-down transistor with the output held low for nominally 500ns. If the internal oscillator is set for 500kHz and the load is 100pF and a 3x time constant is required, the resistor calculation is as follows: RPULLUP = 2µs – 500ns = 5k 3 •100pF The closest 1% resistor is 4.99k. If timing errors are occurring or if the SYNC frequency is not as fast as desired, monitor the waveform and determine if the RC time constant is too long for the application. If possible reduce the parasitic capacitance. If not, reduce the pull-up resistor sufficiently to assure proper timing. The SHARE_CLK pull-up resistor has a similar equation with a period of 10µs and a pull-down time of 1µs. The RC time constant should be approximately 3µs or faster. PHASE-LOCKED LOOP AND FREQUENCY SYNCHRONIZATION The LTM4664A PSM has a phase-locked loop (PLL) comprised of an internal voltage-controlled oscillator (VCO) and a phase detector. The PLL is locked to the falling edge of the SYNC pin. The phase relationship between the PWM controller and the falling edge of SYNC is controlled by the lower 3 bits of the MFR_PWM_ CONFIG command. For PolyPhase applications, it is recommended that all the phases be spaced evenly. Thus for a 2-phase system the signals should be 180° out of phase and a 4-phase system should be spaced 90°. The phase detector is an edge-sensitive digital type that provides a known phase shift between the external and internal oscillators. This type of phase detector does not exhibit false lock to harmonics of the external clock. The output of the phase detector is a pair of complementary current sources that charge or discharge the internal filter network. The PLL lock range is guaranteed between 200kHz and 1MHz. Nominal parts will have a range beyond this; however, operation to a wider frequency range is not guaranteed. The PLL has a lock detection circuit. If the PLL should lose lock during operation, bit 4 of the STATUS_MFR_ SPECIFIC command is asserted and the ALERT pin is pulled low. The fault can be cleared by writing a 1 to the bit. If the user does not wish to see the ALERT pin assert if a PLL_FAULT occurs, the SMBALERT_MASK command can be used to prevent the alert. If the SYNC signal is not clocking in the application, the nominal programmed frequency will control the PWM circuitry. However, if multiple parts share the SYNC pins and the signal is not clocking, the parts will not be synchronized and excess voltage ripple on the output may be present. Bit 10 of MFR_PADS will be asserted low if this condition exists. If the PWM signal appears to be running at too high a frequency, monitor the SYNC pin. Extra transitions on the falling edge will result in the PLL trying to lock on to noise versus the intended signal. Review routing of digital control signals and minimize crosstalk to the SYNC signal Rev. 0 For more information www.analog.com 69 LTM4664A DUAL 25A/30A PSM APPLICATIONS INFORMATION to avoid this problem. Multiple LTM4664As PSM sections are required to share one SYNC pin in PolyPhase configurations. For other configurations, connecting the SYNC pins to form a single SYNC signal is optional. If the SYNC pin is shared between LTM4664As PSM sections, only one LTM4664A section can be programmed with a frequency output. All the other LTM4664As sections should be programmed to disable the SYNC output. However their frequency should be programmed to the nominal desired value. See application schematic in Figure 51. PROGRAMMABLE LOOP COMPENSATION INPUT CURRENT SENSE AMPLIFIER By adjusting the gm and RCOMP only, the LTM4664A PSM can provide a flexible Type II compensation network to optimize the loop over a wide range of output capacitors. Adjusting the gm will change the gain of the compensation over the whole frequency range without moving the pole and zero location, as shown in Figure 32. Ω There is an IR voltage drop from the supply to the VINS3 controller pin due to the current flowing into the VINS3 controller pin. To compensate for this voltage drop, the MFR_ RVIN will be automatically set to the 1Ω internal sense resistor in the Figure 2 Block Diagram. The LTM4664A PSM will multiply the MFR_READ_ICHIP measurement value by this 1Ω resistor and add this voltage to the measured voltage at the VINS3 controller pin. Therefore, READ_VIN = VIN_CNTLPIN + (MFR_READ_ICHIP • 1Ω) The MFR_READ_ICHIP command is used to measure the internal controller current. Using the READ_PIN command allows for reading calculated input power. Ω The LTM4664A input current sense amplifier can sense the supply current into the VINS3_Cn power stages pins using an external sense resistor as shown in the Figure 2 Block Diagram. The RSENSE value can be programmed using the MFR_IIN_CAL_GAIN command. Kelvin sensing is recommended across the RSENSE resistor to eliminate errors. The MFR_PWM_CONFIG [6:5] sets the input current sense amplifier gain. See the MFR_PWM_CONFIG section. The IIN_OC_WARN_LIMIT command sets the value of the input current measured by the ADC, in amperes, that causes a warning indicating the input current is high. The READ_IIN value will be used to determine if this limit has been exceeded. The READ_IIN command returns the input current, in Amperes, as measured across the input current sense resistor. The LTM4664A offers programmable loop compensation to optimize the transient response without any hardware change. The error amplifier gain gm varies from 1.0m to 5.73m , and the compensation resistor RCOMP varies from 0kΩ to 62kΩ inside the controller. Two compensation capacitors, COMP_na and COMP_nb, are required in the design and the typical ratio between COMP_na and COMP_nb is 10. Also see Figure 2 Block Diagram, and Figure 31. Adjusting the RCOMP will change the pole and zero location, as shown in Figure 33. It is recommended that the user determines the appropriate value for the gm and RCOMP using the LTpowerCAD tool. gm RCOMP + VREF – FB 4664A F31 COMP_na COMP_nb Figure 31. Programmable Loop Compensation TYPE II COMPENSATION GAIN INCREASE gm FREQUENCY 4664A F32 Figure 32. Error Amp gm Adjust 70 For more information www.analog.com Rev. 0 LTM4664A DUAL 25A/30A PSM APPLICATIONS INFORMATION TYPE II COMPENSATION GAIN INCREASE RCOMP FREQUENCY 4664A F33 Figure 33. RCOMP Adjust CHECKING TRANSIENT RESPONSE The regulator loop response can be checked by looking at the load current transient response. Switching regulators take several cycles to respond to a step in DC (resistive) load current. When a load step occurs, VOUT shifts by an amount equal to ∆ILOAD(ESR), where ESR is the effective series resistance of COUT. ∆ILOAD also begins to charge or discharge COUT generating the feedback error signal that forces the regulator to adapt to the current change and return VOUT to its steady-state value. During this recovery time VOUT can be monitored for excessive overshoot or ringing, which would indicate a stability problem. The availability of the COMP pin not only allows optimization of control loop behavior but also provides a DC-coupled and AC-filtered closed-loop response test point. The DC step, rise time and settling at this test point truly reflects the closed-loop response. Assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. The bandwidth can also be estimated by examining the rise time at the pin. The COMP_Cna external capacitor shown in the Typical Application circuit will provide an adequate starting point for most applications. The programmable parameters that affect loop gain are the voltage range, bit[1] of the MFR_PWM_CONFIG command, the current range bit[7] of the MFR_PWM_MODE command, the gm of the PWM channel amplifier bits [7:5] of MFR_PWM_COMP, and the internal RCOMP compensation resistor, bits[4:0] of MFR_PWM_COMP. Be sure to establish these settings prior to compensation calculation. The COMP_Cna series internal RCOMP and external CCOMP_Cna filter sets the dominant pole-zero loop compensation. The internal RCOMP value can be modified (from 0Ω to 62kΩ) using bits[4:0] of the MFR_PWM_ COMP command. Adjust the value of RCOMP to optimize transient response once the final PCB layout is done and the particular CCOMP_bn filter capacitor and output capacitor type and value have been determined. The output capacitors need to be selected because the various types and values determine the loop gain and phase. An output current pulse of 20% to 80% of full-load current having a rise time of 1µs to 10µs will produce output voltage and COMP pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. Placing a power MOSFET with a resistor to ground directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce to a load step. The MOSFET + RSERIES will produce output currents approximately equal to VOUT/RSERIES. RSERIES values from 0.1Ω to 2Ω are valid depending on the current limit settings and the programmed output voltage. The initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. This is why it is better to look at the COMP pin signal which is in the feedback loop and is the filtered and compensated control loop response. The gain of the loop will be increased by increasing RCOMP and the bandwidth of the loop will be increased by decreasing CCOMP_Cna. If RCOMP is increased by the same factor that CCOMP is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. The gain of the loop will be proportional to the transconductance of the error amplifier which is set using bits[7:5] of the MFR_PWM_COMP command. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. A second, more severe transient is caused by switching in loads with large (>1µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and Rev. 0 For more information www.analog.com 71 LTM4664A DUAL 25A/30A PSM APPLICATIONS INFORMATION it is driven quickly. If the ratio of CLOAD to COUT is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 • CLOAD. Thus a 10µF capacitor would require a 250µs rise time, limiting the charging current to about 200mA. PolyPhase® Configuration When configuring a PolyPhase rail with multiple LTM4664As, the user must share the SYNC, COMP_na, COMP_nb SHARE_CLK, FAULT_Cn, and ALERT pins of these parts. Be sure to use pull-up resistors on FAULT_ Cn, SHARE_CLK and ALERT. One of the part’s SYNC pins must be set to the desired switching frequency, and all other FREQUENCY_SWITCH commands must be set to External Clock. If an external oscillator is provided, set the FREQUENCY_SWITCH command to External Clock for all parts. The relative phasing of all the channels should be spaced equally. The MFR_RAIL_ ADDRESS of all the devices should be set to the same value. Multiple channels need to tie all the VOSNS+ pins together, and all the VOSNS– pins together COMP_na and COMP_ nb pins together as well. Do not assert bit[4] of MFR_ CONFIG_ALL except in a PolyPhase application. See application example Figure 50. CONNECTING THE USB TO I2C/SMBUS/PMBUS CONTROLLER TO THE LTM4664A IN-SYSTEM The LTC USB-to-I2C/SMBus/PMBus adapter (DC1613A or equivalent) can be interfaced to the LTM4664A PSM on the user’s board for programming, telemetry and system debug. The adapter, when used in conjunction with LTpowerPlay, provides a powerful way to debug an entire power system. Faults are quickly diagnosed using telemetry, fault status commands and the fault log. The final configuration can be quickly developed and stored to the LTM4664A PSM EEPROM. Figure 34 illustrates the application schematic for powering, programming and communication with one or more LTM4664As PSM via the LTC I2C/SMBus/PMBus adapter regardless of whether or not system power is present. If system power is not present, the dongle will power the LTM4664A PSM through the VDD33 supply pin. To initialize the part when VIN is not applied and the VDD33 pin is powered, use global address 0x5B command 0xBD data 0x2B followed by address 0x5B command 0xBD data 0xC4.The LTM4664A PSM can now communicate with, and the project file Figure 34. Controller Connection can be updated. To write the updated project file to the NVM issue a STORE_USER _ALL command. When VIN is applied, a MFR_RESET must be issued to allow the PWM POWER to be enabled and valid ADCs to be read. VIN LTC CONTROLLER HEADER ISOLATED 3.3V SDA 100k 100k VIN VDD33 TP0101K SCL 1µF 10k VDD25 1µF LTM4664A PSM SDA 10k SCL WP PGND/SGND TO LTC DC1613 USB TO I2C/SMBus/PMBus CONTROLLER VIN TP0101K VDD33 1µF VDD25 1µF LTM4664A PSM SDA VGS MAX ON THE TP0101K IS 8V IF VIN > 16V CHANGE THE RESISTOR DIVIDER ON THE PFET GATE SCL WP PGND/SGND 4664A F34 Figure 34. Controller Connection 72 Rev. 0 For more information www.analog.com LTM4664A DUAL 25A/30A PSM APPLICATIONS INFORMATION Because of the adapter’s limited current sourcing capability, only the LTM4664As, PSM their associated pull-up resistors and the I2C pull-up resistors should be powered from the ORed 3.3V supply. In addition any device sharing the I2C bus connections with the LTM4664A PSM should not have body diodes between the SDA/SCL pins and their respective VDD node because this will interfere with bus communication in the absence of system power. If VINS3 is applied, the DC1613A will not supply the power to the LTM4664As PSM on the board. It is recommended the RUN_Cn pins be held low or no voltage configuration resistors inserted to avoid providing power to the load until the part is fully configured. The LTM4664A PSM is fully isolated from the host PC’s ground by the DC1613A.The 3.3V from the adapter and the LTM4664A VDD33 pin must be driven to each LTM4664A with a separate PFET. If both VINS3 and EXTVCC are not applied, the VDD33 pins can be in parallel because the on-chip LDO is off. The controller 3.3V current limit is 100mA but typical VDD33 currents are under 15mA. The VDD33 does back drive the INTVCC/EXTVCC pin. Normally this is not an issue if VIN is open. LTpowerPlay: AN INTERACTIVE GUI FOR DIGITAL POWER LTpowerPlay (Figure 35) is a powerful Windows-based development environment that supports Analog Devices digital power system management ICs including the LTM4664A PSM section. The software supports a variety of different tasks. LTpowerPlay can be used to evaluate Analog Devices ICs by connecting to a demo board or the user application. LTpowerPlay can also be used in an off-line mode (with no hardware present) in order to build multiple IC configuration files that can be saved and reloaded at a later time. LTpowerPlay provides unprecedented diagnostic and debug features. It becomes a valuable diagnostic tool during board bring-up to program or tweak the power system or to diagnose power issues when bring up rails. LTpowerPlay utilizes Analog Devices’ USB-to-I2C/SMBus/PMBus adapter to communication with one of the many potential targets including the DC2165A demo board, the DC2298A socketed programming board, or a customer target system. The software also provides an automatic update feature to keep the revisions current with the latest set of device drivers and documentation. A great deal of context sensitive help is available with LTpowerPlay along with several tutorial demos. Complete information is available at: LTpowerPlay PMBus COMMUNICATION AND COMMAND PROCESSING The LTM4664A PSM has a one deep buffer to hold the last data written for each supported command prior to processing as shown in Figure 36, Write Command Data Processing. When the part receives a new command from the bus, it copies the data into the Write Command Data Buffer, indicates to the internal processor that this command data needs to be fetched, and converts the command to its internal format so that it can be executed. Two distinct parallel blocks manage command buffering and command processing (fetch, convert, and execute) to ensure the last data written to any command is never lost. Command data buffering handles incoming PMBus writes by storing the command data to the Write Command Data Buffer and marking these commands for future processing. The internal processor runs in parallel and handles the sometimes slower task of fetching, converting and executing commands marked for processing. Some computationally intensive commands (e.g., timing parameters, temperatures, voltages and currents) have internal processor execution times that may be long relative to PMBus timing. If the part is busy processing a command, and new command(s) arrive, execution may be delayed or processed in a different order than received. The part indicates when internal calculations are in process via bit 5 of MFR_COMMON (“calculations not pending”). When the part is busy calculating, bit 5 is cleared. When this bit is set, the part is ready for another command. An example polling loop is provided in Figure 37 which ensures that commands are processed in order while simplifying error handling routines. Rev. 0 For more information www.analog.com 73 LTM4664A DUAL 25A/30A PSM APPLICATIONS INFORMATION Figure 35. LTpowerPlay Screen Shot CMD PMBus WRITE WRITE COMMAND DATA BUFFER DECODER CMDS DATA MUX CALCULATIONS PENDING S R PAGE • • • VOUT_COMMAND 0x00 0x21 • • • MFR_RESET INTERNAL PROCESSOR FETCH, CONVERT DATA AND EXECUTE 0xFD x1 4664A F36 Figure 36. Write Command Data Processing 74 Rev. 0 For more information www.analog.com LTM4664A DUAL 25A/30A PSM APPLICATIONS INFORMATION When the part receives a new command while it is busy, it will communicate this condition using standard PMBus protocol. Depending on part configuration it may either NACK the command or return all ones (0xFF) for reads. It may also generate a BUSY fault and ALERT notification, or stretch the SCL clock low. For more information refer to PMBus Specification v1.1, Part II, Section 10.8.7 and SMBus v2.0 section 4.3.3. Clock stretching can be enabled by asserting bit 1 of MFR_CONFIG_ ALL. Clock stretching will only occur if enabled and the bus communication speed exceeds 100kHz. // wait until chip is not busy do { mfrCommonValue = PMBUS_READ_BYTE(0xEF); partReady = (mfrCommonValue & 0x68) == 0x68; }while(!partReady) // now the part is ready to receive the next command PMBUS_WRITE_WORD(0x21, 0x2000); //write VOUT_ COMMAND to 2V Figure 37. Example of a Command Write of VOUT_COMMAND PMBus busy protocols are well accepted standards, but can make writing system level software somewhat complex. The part provides three ‘hand shaking’ status bits which reduce complexity while enabling robust system level communication. The three hand shaking status bits are in the MFR_ COMMON register. When the part is busy executing an internal operation, it will clear bit 6 of MFR_COMMON (‘chip not busy’). When the part is busy specifically because it is in a transitional VOUT state (margining hi/lo, power off/on, moving to a new output voltage set point, etc.) it will clear bit 4 of MFR_COMMON (‘output not in transition’). When internal calculations are in process, the part will clear bit 5 of MFR_COMMON (‘calculations not pending’). These three status bits can be polled with a PMBus read byte of the MFR_COMMON register until all three bits are set. A command immediately following the status bits being set will be accepted without NACKing or generating a BUSY fault/ALERT notification. The part can NACK commands for other reasons, however, as required by the PMBus spec (for instance, an invalid command or data). An example of a robust command write algorithm for the VOUT_COMMAND register is provided in Figure 33. It is recommended that all command writes (write byte, write word, etc.) be preceded with a polling loop to avoid the extra complexity of dealing with busy behavior and unwanted ALERT notification. A simple way to achieve this is to create a SAFE_WRITE_BYTE() and SAFE_WRITE_ WORD() subroutine. The above polling mechanism allows your software to remain clean and simple while robustly communicating with the part. For a detailed discussion of these topics and other special cases please refer to the Analog Devices Application Notes. When communicating using bus speeds at or below 100kHz, the polling mechanism shown here provides a simple solution that ensures robust communication without clock stretching. At bus speeds in excess of 100kHz, it is strongly recommended that the part be configured to enable clock stretching. This requires a PMBus master that supports clock stretching. System software that detects and properly recovers from the standard PMBus NACK/ BUSY faults as described in the PMBus Specification v1.1, Par II, Section 10.8.7 is required to communicate The LTM4664A PSM is not recommended in applications with bus speeds in excess of 400kHz. THERMAL CONSIDERATIONS AND OUTPUT CURRENT DERATING The thermal resistances reported in the Pin Configuration section of this data sheet are consistent with those parameters defined by JESD51-12 and are intended for use with finite element analysis (FEA) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation performed on a µModule package mounted to a hardware test board defined by JESD51-9 (“Test Boards for Area Array Surface Mount Package Thermal Measurements”). The motivation for providing these thermal coefficients is found in JESD51-12 (“Guidelines for Reporting and Using Electronic Package Thermal Information”). Many designers may opt to use laboratory equipment and a test vehicle such as the demo board to predict the µModule regulator’s thermal performance in their application at various electrical and environmental operating conditions to compliment any FEA activities. Without FEA software, the thermal resistances reported in the Rev. 0 For more information www.analog.com 75 LTM4664A DUAL 25A/30A PSM APPLICATIONS INFORMATION Pin Configuration section are in-and-of themselves not relevant to providing guidance of thermal performance; instead, the derating curves provided later in this data sheet can be used in a manner that yields insight and guidance pertaining to one’s application-usage, and can be adapted to correlate thermal performance to one’s own application. The Pin Configuration section gives four thermal coefficients explicitly defined in JESD51-12; these coefficients are quoted or paraphrased below: 1. θJA, the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclosure. This environment is sometimes referred to as “still air” although natural convection causes the air to move. This value is determined with the part mounted to a JESD51-9 defined test board, which does not reflect an actual application or viable operating condition. 2. θJCbottom, the thermal resistance from junction to the bottom of the product case, is determined with all of the component power dissipation flowing through the bottom of the package. In the typical µModule regulator, the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient environment. As a result, this thermal resistance value may be useful for comparing packages but the test conditions don’t generally match the user’s application. 3. θJCtop, the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. As the electrical connections of the typical µModule regulator are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. As in the case of θJCbottom, this value may be useful for comparing packages but the test conditions don’t generally match the user’s application. 4. θJB, the thermal resistance from junction to the printed circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the µModule regulator and into the board, and is really the sum of the θJCbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. The board temperature is measured a specified distance from the package, using a two sided, two layer board. This board is described in JESD51-9. A graphical representation of the aforementioned thermal resistances is given in Figure 38; blue resistances are contained within the µModule regulator, whereas green resistances are external to the µModule package. As a practical matter, it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by JESD51-12 or provided in the Pin µModule DEVICE θJA JUNCTION-TO-AMBIENT RESISTANCE θJCTOP JUNCTION-TO-CASE (TOP) RESISTANCE CASE (TOP)-TO-AMBIENT RESISTANCE θJB JUNCTION-TO-BOARD RESISTANCE JUNCTION θJCBOTTOM JUNCTION-TO-CASE (BOTTOM) RESISTANCE CASE (BOTTOM)-TO-BOARD RESISTANCE AMBIENT BOARD-TO-AMBIENT RESISTANCE 4664A F38 Figure 38. Graphical Representation of JESD51-12 Thermal Coefficients 76 Rev. 0 For more information www.analog.com LTM4664A DUAL 25A/30A PSM APPLICATIONS INFORMATION Configuration section replicates or conveys normal operating conditions of a µModule regulator. For example, in normal board-mounted applications, never does 100% of the device’s total power loss (heat) thermally conduct exclusively through the top or exclusively through the bottom of the µModule package—as the standard defines for θJCtop and θJCbottom, respectively. In practice, power loss is thermally dissipated in both directions away from the package—granted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board. Within the LTM4664A, be aware there are multiple power devices and components dissipating power, with a consequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. To reconcile this complication without sacrificing modeling simplicity—but also, not ignoring practical realities—an approach has been taken using FEA software modeling along with laboratory testing in a controlled-environment chamber to reasonably define and correlate the thermal resistance values supplied in this data sheet: (1) Initially, FEA software is used to accurately build the mechanical geometry of the LTM4664A and the specified PCB with all of the correct material coefficients along with accurate power loss source definitions; (2) this model simulates a software-defined JEDEC environment consistent with JESD51-9 and JESD51-12 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the JEDEC-defined thermal resistance values; (3) the model and FEA software is used to evaluate the LTM4664A with heat sink and airflow; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled environment chamber while operating the device at the same power loss as that which was simulated. The outcome of this process and due diligence yields the set of derating curves provided in later sections of this data sheet, along with well-correlated JESD51-12defined θ values provided in the Pin Configuration section of this data sheet. The 1.0V and 1.5V power loss curves in Figure 39 and 40 respectively can be used in coordination with the load current derating curves in Figure 41 to 44 for calculating an approximate θJA thermal resistance for the LTM4664A with various heat sinking and airflow conditions. These thermal resistances represent demonstrated performance of the LTM4664A on hardware; a 8-layer FR4 PCB measuring 99mm × 145mm × 1.6mm using 2oz copper on all layers. The power loss curves are taken at room temperature, and are increased with multiplicative factors of 1.35 when the junction temperature reaches 125°C. The derating curves are plotted with the LTM4664A’s paralleled outputs initially sourcing up to 50A and the ambient temperature at 50°C. The output voltages are 1.0V and 1.5V. These are chosen to include the lower and higher output voltage ranges for correlating the thermal resistance. Thermal models are derived from several temperature measurements in a controlled temperature chamber along with thermal modeling analysis. The junction temperatures are monitored while ambient temperature is increased with and without airflow. The power loss increase with ambient temperature change is factored into the derating curves. The junctions are maintained at 125°C maximum while lowering output current or power while increasing ambient temperature. The decreased output current decreases the internal module loss as ambient temperature is increased. The monitored junction temperature of 120°C minus the ambient operating temperature specifies how much module temperature rise can be allowed. As an example in Figure 41, the load current is derated to ~30A at ~97°C ambient with no air or heat sink and the room temperature (25°C) power loss for this 48VIN to 1.0VOUT at 30AOUT condition is ~3.2W. A 4.32W loss is calculated by multiplying the ~3.2W room temperature loss from the 48VIN to 1.0VOUT power loss curve at 30A (Figure 41), with the 1.35 multiplying factor. If the 97°C ambient temperature is subtracted from the 120°C junction temperature, then the difference of 23°C divided by 4.32W yields a thermal resistance, θJA, of 5.3°C/W—in good agreement with Table 11. Table 10 and 11 provide equivalent thermal resistances for 1.0V and 1.5V outputs with and without airflow. The derived Rev. 0 For more information www.analog.com 77 LTM4664A DUAL 25A/30A PSM APPLICATIONS INFORMATION thermal resistances in Table 10 and Table 11 are for the various conditions can be multiplied by the calculated power loss as a function of ambient temperature to derive temperature rise above ambient, thus maximum junction temperature. Room temperature power loss can be derived from the efficiency curves in the Typical Performance Characteristics section and adjusted with the above ambient temperature multiplicative factors. Thermal performance expectations at up to 60A output (at up to 1.2VOUT) can be suitably approximated by studying this section's figures at analogous nearby output power conditions. For example: 1.2VOUT at 60A is 72W output. For thermal purposes, this operating point can be approximated by 1.5VOUT at 48A output (observe: also 72W output). The 1.5VOUT curves shown in this section can thus be utilized to infer thermal performance at currents higher than 25A, per channel (for output voltages up to 1.2VOUT). TABLE 10 AND TABLE 11: OUTPUT CURRENT DERATING (BASED ON DEMO BOARD) Table 10. 1.0V Output DERATING CURVE Figure 41, 42 Figure 41, 42 Figure 41, 42 VIN (V) 48, 54 48, 54 48, 54 POWER LOSS CURVE Figure 39, 40 Figure 39, 40 Figure 39, 40 AIRFLOW (LFM) 0 200 400 HEAT SINK None None None θJA (°C/W) 5.3 4.5 4.0 VIN (V) 48, 54 48, 54 48, 54 POWER LOSS CURVE Figure 39, 40 Figure 39, 40 Figure 39, 40 AIRFLOW (LFM) 0 200 400 HEAT SINK None None None θJA (°C/W) 5.3 4.5 4.0 Table 11. 1.5V Output DERATING CURVE Figure 43, 44 Figure 43, 44 Figure 43, 44 78 Rev. 0 For more information www.analog.com LTM4664A DUAL 25A/30A PSM APPLICATIONS INFORMATION Table 12. LTM4664A Dual 25A/30A PSM Output Capacitor Matrix All Below Parameters are Typical and Are Dependent on Board Layout Murata 220μF 6.3V GRM32ER60J227ME05 PANASONIC SP-CAP 470μF 2.5V EEFSX0E471E4 Taiyo Yuden 220μf 4V AMK325ABJ227MMHT PANASONIC POSCAP 470μF 2.5V ETPF470M5H Murata 100μF 6.3V GRM32ER60J107M PANASONIC POSCAP 1000μF 2.5V Murata 100μF 4V GRM21BR60G107ME15 PANASONIC POSCAP 1000μF 2.5V Taiyo Yuden 100μF 4V AMK325AD7MMHP Single 25A/30A Output ETCF1000M5H Programmed Values COUT2 VOUT (BULK) COMPna COMPnb EA-GM RCOMP LOW- VINS1 ILIM (μF) (kΩ) HI-RANGE RANGE (V) (pF) (pF) (ms) RECOVERY PEAKLOAD TIME(µs) TO-PEAK DROOP DEVIATION LTpowerCAD/ STEP FREQ. MEASURE (A/µs) (kHz) (mV) (mV) VOUT (V) COUT1 (CERAMIC) (μF) 0.9 5 × 100 2 × 470 2200 100 3.69 5 Yes Yes 48 (VINS1/4) or 12V 42.5 0.9 5 × 100 1 × 1000 3300 220 3.02 5 Yes Yes 48 (VINS1/4) or 12V 55.5 0.9 6 × 220 None 4700 100 3.69 4 Yes Yes 48 (VINS1/4) or 12V 75 1 5 × 100 2 × 470 2200 100 3.69 5 Yes Yes 48 (VINS1/4) or 12V 42.5 1 5 × 100 1 × 1000 3300 220 3.02 5 Yes Yes 48 (VINS1/4) or 12V 56 VINS3 C1, C2 85 36 12.5 250 111 40 12.5 250 150 50 12.5 250 85 36 12.5 250 112 40 12.5 250 1 6 × 220 None 4700 100 3.69 4 Yes Yes 48 (VINS1/4) or 12V 75 150 50 12.5 250 1.2 3 × 100 1 × 470 2200 220 3.69 3 Yes Yes 48 (VINS1/4) or 12V 67.5 135 27 12.5 350 1.2 3 × 100 1 × 470 2200 220 3.69 4 Yes Yes 48 (VINS1/4) or 12V 60 120 27 12.5 350 1.2 3 × 220 None 2200 220 1.68 5 Yes Yes 48 (VINS1/4) or 12V 85 170 20 12.5 350 1.2 1 × 100 1 × 470 2200 220 3.02 6 Yes Yes 48 (VINS1/4) or 12V 68 136 33 12.5 350 1.5 3 × 220 None 2200 220 1.68 5 Yes Yes 48 (VINS1/4) or 12V 115 230 30 12.5 350 1.5 1 × 100 1 × 470 2200 220 3.02 6 Yes Yes 48 (VINS1/4) or 12V 70 140 27 12.5 350 Rev. 0 For more information www.analog.com 79 LTM4664A DUAL 25A/30A PSM APPLICATIONS INFORMATION Table 13. LTM4664A Dual 25A/30A PSM Output Capacitor Matrix. All Below Parameters Are Typical and Are Dependent on Board Layout Murata 220µF 6.3V GRM32ER60J227ME05 PANASONIC SP-CAP 470µF 2.5V EEFSX0E471E4 Taiyo Yuden 220µF 4V AMK325ABJ227MMHT PANASONIC POSCAP 470µF 2.5V ETPF470M5H Murata 100µF 6.3V GRM32ER60J107M PANASONIC POSCAP 1000µF 2.5V ETPF1000M5H Murata 100µF 4V GRM21BR60G107ME15 PANASONIC POSCAP 1000µF 2.5V ETCF1000M5H Taiyo Yuden 100µF 4V AMK325AD7MMHP Dual Phase Single 50A/60A Output RECOVERY PEAKLOAD TIME(µs) TO-PEAK DROOP DEVIATION LTpowerCAD/ STEP FREQ. MEASURE (A/µs) (kHz) (mV) (mV) COUT1 VOUT (CERAMIC) (μF) (V) COUT2 (BULK) (μF) 0.9 8 × 100 4 × 470 3300 220 3.69 8 No Yes 48 (VINS1/4) or 12V 47.5 62/95 30 25 250 1 8 × 100 4 × 470 3300 220 3.69 8 No Yes 48 (VINS1/4) or 12V 47.5 62/95 30 25 250 35 64 35 25 250 70 100/140 35 25 350 VOUT LOW- VINS1 COMPna COMPnb EA-GM RCOMP ILIM (pF) (ms) (kΩ) HI-RANGE RANGE (V) (pF) VINS3 C1, C2 1.2 8 × 330 None 5600 100 3.02 5 No Yes 48 (VINS1/4) or 12V 1.2 4 × 100 2 × 470 3300 220 3.02 6 No Yes 48 (VINS1/4) or 12V 1.2 4 × 220 None 7500 220 3.02 5 No Yes 48 (VINS1/4) or 12V 63 126/- 25 25 350 1.5 4 × 220 None 7500 220 3.02 2.5 No Yes 48 (VINS1/4) or 12V 130 260 30 25 350 1.5 6 × 220 None 7500 220 3.69 3 No Yes 48 (VINS1/4) or 12V 100 200 30 25 350 1.5 4 × 100 2 × 470 3300 220 3.02 6 No Yes 48 (VINS1/4) or 12V 70 140 30 25 350 1.5 4 × 220 None 7500 220 3.02 5 No Yes 48 (VINS1/4) or 12V 63 126 25 25 350 80 Rev. 0 For more information www.analog.com LTM4664A DUAL 25A/30A PSM APPLICATIONS INFORMATION–DERATING CURVES 9 8 9 7 6 5 4 3 6 5 2 10 20 30 40 OUTPUT CURRENT (A) 1 50 10 0 10 20 30 40 OUTPUT CURRENT (A) 60 OLFM 200LFM 400LFM 30 20 10 10 10 60 TA (°C) 80 100 120 4664A F42 Figure 42. LTM4664A 54VIN 1VOUT Derating Curve No Heat Sink 0 100 120 30 20 40 80 40 20 20 60 TA (°C) OLFM 200LFM 400LFM 50 IOUT (A) IOUT (A) IOUT (A) 60 40 0 40 Figure 41. LTM4664A 48VIN 1VOUT Derating Curve No Heat Sink OLFM 200LFM 400LFM 50 40 0 20 4664A F41 Figure 40. 54V Input Power Loss 2-Phase 50A Output 30 0 4664A F40 Figure 39. 48V Input Power Loss 2-Phase 50A Output 50 0 50 4664A F39 60 30 20 4 1 0 40 7 3 OLFM 200LFM 400LFM 50 8 2 0 60 0.9V OUTPUT 1V OUTPUT 1.5V OUTPUT 1.2V OUTPUT 10 POWER LOSS (W) POWER LOSS (W) 11 0.9V OUTPUT 1V OUTPUT 1.5V OUTPUT 1.2V OUTPUT 10 IOUT (A) 11 0 20 40 60 TA (°C) 80 100 120 4664A F43 Figure 43. LTM4664A 48VIN 1.5VOUT 350kHz Derating Curve No Heat Sink 0 0 20 40 60 TA (°C) 80 100 120 4664A F44 Figure 44. LTM4664A 54VIN 1.5VOUT 350kHz Derating Curve No Heat Sink Rev. 0 For more information www.analog.com 81 LTM4664A DUAL 25A/30A PSM APPLICATIONS INFORMATION EMI PERFORMANCE The SW_Cn pin provides access to the midpoint of the power MOSFETs in LTM4664A’s power stages. Connecting an optional series RC network from SW_Cn to GND can dampen high frequency (~30MHz+) switch node ringing caused by parasitic inductances and capacitances in the switched-current paths. The RC network is called a snubber circuit because it dampens (or “snubs”) the resonance of the parasitics, at the expense of higher power loss. To use a snubber, choose first how much power to allocate to the task and how much PCB real estate is available to implement the snubber. For example, if PCB space allows a low inductance 0.5W resistor to be used then the capacitor in the snubber network (CSW) is computed by: CSW = PSNUB VINS3n (MAX) 2 • fSW where VIN3n(MAX) is the maximum input voltage that the input to the power stage (VINn) will see in the application, and fSW is the DC/DC converter’s switching frequency of operation. CSW should be NPO, C0G or X7R-type (or better) material. The snubber resistor (RSW) value is then given by: RSW = 5nH CSW A 2.2nF snubber capacitor is a good value to start with in series with the snubber resistor to ground. The no load input quiescent current can be monitored while selecting different RC series snubber components to get a increased power loss versus switch node ringing attenuation. SAFETY CONSIDERATIONS The LTM4664A modules do not provide galvanic isolation from VIN to VOUT. There is no internal fuse. If required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. The fuse or circuit breaker should be selected to limit the current to the regulator during overvoltage in case of an internal top MOSFET fault. If the internal top MOSFET fails, then turning it off will not resolve the overvoltage, thus the internal bottom MOSFET will turn on indefinitely trying to protect the load. Under this fault condition, the input voltage will source very large currents to ground through the failed internal top MOSFET and enabled internal bottom MOSFET. This can cause excessive heat and board damage depending on how much power the input voltage can deliver to this system. A fuse or circuit breaker can be used as a secondary fault protector in this situation. The device does support over current and overtemperature protection. The snubber resistor should be low ESL and capable of withstanding the pulsed currents present in snubber circuits. A value between 0.7Ω and 4.2Ω is normal. 82 Rev. 0 For more information www.analog.com LTM4664A DUAL 25A/30A PSM APPLICATIONS INFORMATION LAYOUT CHECKLIST/EXAMPLE n The high integration of LTM4664A makes the PCB board layout very simple and easy. However, to optimize its electrical and thermal performance, some layout considerations are still necessary. Use large PCB copper areas for high current paths, including VINn, GND and VOUTSn. It helps to minimize the PCB conduction loss and thermal stress. n n Place high frequency ceramic input and output capacitors next to the VINSn, GND and VOUTn pins to minimize high frequency noise. Place a dedicated power ground layer underneath the module. n n To minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. Do not put vias directly on pads, unless they are capped or plated over. Use a separate SGND copper plane for components connected to signal pins. Connect SGND to GND local to the LTM4664A. n Use Kelvin sense connections across the input RSENSE resistor if input current monitoring is used. n For parallel modules, tie the VOUTCn, ,VOSNS+_Cn/ VOSNS–_Cn voltage-sense differential pair lines, RUN_n, COMP_Cna, COMP_nb pin together. The user must share the SYNC, SHARE_CLK, FAULT, and ALERT pins of these parts. Be sure to use pull-up resistors on FAULT, SHARE_CLK and ALERT. n Bring out test points on the signal pins for monitoring. n Figure 45 gives a good example of the recommended layout. Reference DC2672A demo manual. TOP 3 (1210) FLYING CAPS 1ST STAGE BOTTOM 4 (1210) FLYING CAPS 1ST STAGE TOP LAYER LTM4664A 16 ×16 × 8mm 1ST STAGE INPUT CAP (1210) BOTTOM LAYER OUTPUT CAPS INPUT CAP TO 60A CORE (1206) 2ND STAGE INPUT CAP (1206) TOP 4 (1206) FLYING CAPS 2ND STAGE BOTTOM 3 (1206) FLYING CAPS 2ND STAGE 4664A F48 Figure 45. Recommended PCB Layout Package Top and Bottom View Rev. 0 For more information www.analog.com 83 LTM4664A TYPICAL APPLICATIONS 10µF ×2 50V VOUT1 1µF PGOODS2 EXTVCCS2 OVP_SET OVP_TRIP INSNSS1+ CIRCUIT BREAKER TRIP INTVCCS1 EXTVCCS1 GND PGOODS1 PGOODS2 1% 100k 1% 12.1k RUNS1 RUNS2 PGOOD_C0 VOUT2 IN+ 10µF 25V ×4 0.004Ω* INTVCC 4.7µF VDD33 VDD25 VDD33 10k VINS3_C0 SGND_C0_C1 VINS3_C1 VOSNS+ _C0 INTVCC VDD33 PGOOD_C1 VDD25 PINS NOT SHOWN: GL_C0 GL_C1 PHFLT_C0 PHFLT_C1 TWO PHASE PSM 60A SECTION PWMC1 PWMC0 PROGRAM EA-GM = 3.02ms VOUT RANGE = LOW RCOMP = 8k ILIM RANGE = LOW *OPTIONAL SENSE RESISTOR VDD25 100pF 3300pF FSWPH_CFG VOUTC1_CFG VOUTC0_CFG ALERT VTRIMC0_CFG SDA VTRIMC1_CFG VOSNS– _C1 SCL ASEL SHARE_CLK COMP_C1a VOSNS+ _C1 COMP_C0a SYNC COMP_C0b SDA ALERT FAULT_C1 COMP_C1b SCL 470µF ×3 VOSNS– 330µF 4V ×3 SGND_C0_C1 WP SYNC SHARE_CLK PGOODVCORE GND FAULT_C0 TSNS_C0b 10k + LOAD VOUTC1 RUN_C1 TSNS_C0a 10k VOSNS+ SWC1 TSNS_C1b 10k 0.9V/60A 330µF 4V ×2 VOSNS– _C0 TSNS_C1a 10k 10k PGOODVCORE GND PWM_C0 10k FAULT INTVCC 1% 36.5k VOUTC0 IN– PWM_C1 PGOODS2 ON/OFF SWC0 LTM4664A RUN_C0 10k 10k PGOODS1 FREQS1 UVS2 VOUT2 4.7µF 1µF FAULTS1 FREQS2 1% 60.4k 19.6k 7.5k VOUT2 GND FAULTS2 PGOODS1 VOUT2 MAIN BULK 5.1V OVP_SET VOUT2_SET INSNSS1– SW1 49.9k 100V 2.2µF 100V ×2 RSENSE 10mΩ VINS1 SW2 UVS1 VOUT1 VINS2F INSNS2+ SW3 VINS2 SW4 10µF ×8 50V 1% 6.04k INSNS2– INTVCCS2 10µF ×8 100k 50V HYS_PRGMS1 VOUT2 TIMERS1 GND HYS_PRGMS2 4:1 VOLTAGE DIVIDER 4.7µF 100k 0.068µF TIMERS2 0.068µF 48V 1% 100k EXTVCC 1% 14.7k 14.3k 1% 22.6k 1% 1.65k 1% 32.4k VOSNS+ VOSNS– 5V BIAS AT 50mA VDD25 4664A F46 Figure 46. 0.9V at 60A Output DC/DC µModule Regulator with I2C/SMBus/PMBus Serial Interface Including Hot Swap Front End with VOUT2 OVP Protection 84 Rev. 0 For more information www.analog.com LTM4664A TYPICAL APPLICATIONS CH1 18V PULSE ON VOUT2 20V/DIV, 500mS/DIV CH2 VIN HOT SWAP TURN OFF 50V/DIV CH3 CIRCUITBREAKERTRIP SIGNAL 10V/DIV CH4 1.5V VOUT PSM 500mV/DIV 4664A G46b Figure 46b. VOUT2 Overvoltage Protection THIS CIRCUIT CAN BE DUPLICATED AND CONNECTED TO ADDITIONAL LTM4664As USING EACH LTM4664A’S OVP CIRCUIT 20m 28V TO 58V, 60V MAX + 10nF 100k 562k UV=27V 10nF 28k 100nF 100V 10k 33k DRIVEN BY LTM4664A OVP CIRCUIT VOUT2 VIN BSC046N10NS3G 470µF 100V 100nF 100V 100k VCC MMBT3906 2M V 1µF GATE SNS U1 SHDN UV FLTB LT4363-1 GND OUT FB TMR ENOUT 10k CIRCUITBREAKERTRIP 1k OUT2SET 30k 4664A F46c NEXT DUPLICATE 10k VOUT2 OVP TRIP POINT AT 16.5V ON/OFF 47nF Figure 46c. Hot Swap Circuit Breaker Front End Rev. 0 For more information www.analog.com 85 LTM4664A TYPICAL APPLICATIONS VOUT1 VIN 30V–58V 1% 100k 4.7µF 1µF PGOODS2 EXTVCCS2 49.9k 100V OVP_SET INSNSS1+ VOUT2_SET INSNSS1– SW1 GND RUNS1 INTVCC 1% 36.5k SWC1 RUN_C0 VOUTC1 RUN_C1 GND SHARE_CLK *OPTIONAL SENSE RESISTOR CH0 PROGRAM EA-GM = 3.69ms RCOMP = 5k CH1 PROGRAM EA-GM = 3.69ms RCOMP = 3k VOSNS+ VOSNS– 2200pF 100pF 2200pF VDD25 1% 22.6k 1% 14.3k 1% 14.3k 1% 2.43k LOAD1 + 470µF ×1 4V +5V BIAS 50mA FSWPH_CFG VOUTC1_CFG VOUTC0_CFG VTRIMC0_CFG VTRIMC1_CFG PWMC0 220µF ×2 1.5V/25A 1% 14.5k PWMC1 100pF VOUT RANGE = LOW ILIM RANGE = LOW ASEL COMP_C1a COMP_C0a SDA 470µF ×2 4V VOSNS– 100µF ×3 4V EXTVCC SCL TWO PHASE PSM 25A/30A SECTION PGOODVCORE VOSNS–_C1 SYNC + LOAD0 VOSNS+_C1 FAULT_C1 ALERT 100µF + ×2 V OSNS 4V SGND_C0_C1 FAULT_C0 COMP_C0b ALERT PGOOD_C1 VDD25 COMP_C1b SCL SDA VDD33 WP SYNC SHARE_CLK 10k INTVCC VOSNS–_C0 TSNS_C0b FAULT VOSNS+_C0 TSNS_C0a 10k PGOODS2 VINS3_C1 TSNS_C1b 10k SGND_C0_C1 TSNS_C1a 10k 1V/30A VOUTC0 GND VINS3_C0 10k PGOODVCORE SWC0 LTM4664A – PWM_C0 4.7µF VDD33 VDD25 VDD33 PGOOD_C0 IN+ INTVCC PINS NOT SHOWN: GL_C0 GL_C1 PHFLT_C0 PHFLT_C1 ON/OFF FREQS1 VOUT2 IN 10k PGOODS1 FAULTS1 RUNS2 0.004* 4.7µF 1µF PGOODS1 PGOODS2 PWM_C1 1% 10µF 25V x4 10k VOUT2 GND UVS2 VOUT2 100k 10k INTVCCS1 7.5k 60.4k 1% 20k 10k 19.6k CIRCUIT BREAKER TRIP EXTVCCS1 FREQS2 1% VOUT2 VOUT2_SET FAULTS2 PGOODS1 MAIN BULK 5.1V RSENSE 10mΩ VINS1 SW2 UVS1 VOUT1 INSNS2+ VINS2 SW3 10µF ×8 50V 1% 10k INSNS2– INTVCCS2 HYS_PRGMS1 GND VOUT2 TIMERS1 TIMERS2 4:1 VOLTAGE DIVIDER HYS_PRGMS2 0.068µF SW4 0.068µF 10µF ×8 100k 50V VINS2F 100k 2.2µF ×2 100V OVP_TRIP 10µF ×2 VDD25 VDD25 1% 4.22k 22.6k 4664A F47 Figure 47. 54V to 1.0V at 30A and 1.5V Outputs at 25A With Providing I2C/SMBus/PMBus Serial Interface 86 Rev. 0 For more information www.analog.com LTM4664A TYPICAL APPLICATIONS VOUT1A VIN 40V–58V 1% 100k 1µF EXTVCCS2 OVP_SET INTVCCS1 1% 60.4k VOUT2A INTVCCA VDD33A VDD25A 10k VOUT2 VOSNS–_C0 VDD33 SWC1 VDD25A 1% 32.4k 100pF 6800pF 1µF PGOODS2A EXTVCCS2 OVP_TRIP OVP_SET VOUT2__SET INTVCCS1 EXTVCCS1 GND PGOODS1 PGOODS2 1% 12.1k VOUT2B RUNS1 RUNS2 PGOOD_C0 VOUT2 + VOSNS _C0 VOSNS–_C0 INTVCC VDD33 PGOOD_C1 VDD25 SYNC VOSNS– _C1 EXTVCC FSWPH_CFG VOUTC1_CFG VOUTC0_CFG VTRIMC0_CFG ASEL COMP_C1b COMP_C0b COMP_C0a COMP_C1a WP TSNS_C0b TSNS_C0a ALERT TSNS_C1b SCL VTRIMC1_CFG SHARE_CLK SDA PINS NOT SHOWN: GL_C0 PHFLT_C0 PHFLT_C1 GL_C1 PWMC0B COMPL COMPH 1% 22.6k + 220µF ×4 4V VOSNS– +5V BIAS ≥ 50mA VDD25B 1% 14.3k PWMC1B TWO PHASE PSM 60A SECTION VOSNS VOSNS+_C1 FAULT_C1 TSNS_C1a SDA ALERT VOSNS– SGND_C0_C1 FAULT_C0 PWM_C0 SCL 470µF ×2 4V PGOODVCORE VOUTC1 GND RUN_C1 PWM_C1 SYNC SHARE_CLK VOSNS+ SWC1 RUN_C0 FAULT 220µF ×4 4V SGND_C0_C1 VINS3_C1 PGOODS2A 1% 36.5k PGOODVCORE VOUTC0 GND VINS3_C0 INTVCCB ON/OFFB SWC0 LTM4664A (B) IN– 4.7µF VDD33B VDD25B 10k PGOODS1B FREQS1 IN+ 10µF ×4 25V 4.7µF 1µF FAULTS1 UVS2 1% 100k 7.5k VOUT2B GND FREQS2 1% 60.4k 19.6k CIRCUIT BREAKER TRIP FAULTS2 PGOODS1B VOUT2B MAIN BULK 5.1V OVP_SET INSNSS1+ INSNSS1– VINS1 RSENSE1 10mΩ SW1 SW2 VOUT1 UVS1 VINS2F INSNS2+ 49.9k 100V 2.2µF 100V ×2 10µF ×6 59V 1% 6.04k VINS2 SW3 SW4 VIN 40V–58V 1% 100k 10µF ×6 50V INSNS2– INTVCCS2 HYS_PRGMS1 VOUT2B 4.7µF HYS_PRGMS2 GND TIMERS1 4:1 VOLTAGE DIVIDER 100k VDD25A 32.4k COMPH COMPL 0.068µF TIMERS2 0.068µF +5V BIAS ≥ 50mA EXTVCC 1% 14.3k 10µF ×2 50V V OUT1B 100k VOSNS _C1 1% 14.3k 1% 1.65Ω VOSNS– – FSWPH_CFG VOUTC1_CFG VOUTC0_CFG ASEL ALERT COMP_C1b SDA PINS NOT SHOWN: PWMC1A GL_C0 TWO PHASE PSM 60A SECTION PWMC0A GL_C1 PHFLT_C0 VOUT RANGE = LOW PROGRAM EA-GM = 3.02ms PHFLT_C1 ILIM RANGE = LOW RCOMP = 4k ALL CHANNELS FOR ALL CHANNELS COMP_C0b SCL COMP_C0a ALERT VOSNS+ VOSNS+_C1 SYNC WP SCL SDA FAULT_C1 SHARE_CLK COMP_C1a SHARE_CLK 220µF ×4 4V SGND_C0_C1 FAULT_C0 TSNS_C0b SYNC 10k VOSNS– VOUTC1 GND RUN_C1 TSNS_C0a 10k LOAD PGOODVCORE PGOOD_C1 VDD25 TSNS_C1b 10k VOSNS+ VOSNS+_C0 INTVCC TSNS_C1a 10k 220µF ×4 4V SGND_C0_C1 PWM_C0 FAULT 0.9V/120A VOUTC0 GND VINS3_C0 VINS3_C1 PWM_C1 10k 10k 10k PGOODVCORE SWC0 LTM4664A (A) RUN_C0 PGOODS2A INTVCCA 1% 36.5k PGOOD_C0 IN– 4.7µF VDD33A ON/OFFA RUNS1 FREQS1 IN+ 10µF 25V ×4 10k PGOODS1A FAULTS1 RUNS2 UVS2 1% 100k 4.7µF 1µF PGOODS1 PGOODS2 7.5k VOUT2A GND FREQS2 1% 12.1k 19.6k EXTVCCS1 FAULTS2 PGOODS1A VOUT2A CIRCUIT BREAKER TRIP GND PGOODS2A MAIN BULK 5.1V OVP_SET INSNSS1+ INSNSS1– RSENSE 10mΩ SW1 SW2 UVS1 VOUT1 VINS2F INSNS2+ VINS2 SW4 INSNS2– INTVCCS2 49.9k 100V 2.2µF ×2 100V IOUT2_SET VOUT2A 4.7µF SW3 GND TIMERS1 TIMERS2 4:1 VOLTAGE DIVIDER HYS_PRGMS1 0.068µF HYS_PRGMS2 0.068µF 10µF ×6 50V 1% 6.04k VINS1 10µF ×6 100k 50V 100k OVP_TRIP 10µF ×2 50V 1% 1.65k 1% 1.65k 1% 14.3k 4664A F48 Figure 48. Two Paralleled LTM4664A Producing 54V to 0.9VOUT at 120A. Integrated Power System Management Features Accessible Over 2-Wire I2C/SMBus/PMBus Serial Interface Rev. 0 For more information www.analog.com 87 LTM4664A TYPICAL APPLICATIONS VIN 30V TO 58V VOUT1 1% 100k 1µF PGOODS2 EXTVCCS2 ENABLE INPUT OUTPUT 1% 1% 20k 100k VOUT2 PGOODS2 VIN/4 56µF 35V OTHER DC/DC REGS NO LOAD UNTIL ENABLED OVP_SET VOUT2_SET PGOODS2 INTVCC 10k PGOODS2 FAULT 10k 10k 10k 10k SGND_C0_C1 VINS3_C1 VOSNS+ _C0 INTVCC VOSNS– _C0 VDD33 SGND_C0_C1 FAULT_C1 VOSNS+_C1 470µF INTVCC 100µF ×6 + 470µF VOSNS–_C1 FSWPH_CFG VOUTC1_CFG VOUTC0_CFG VTRIMC0_CFG VTRIMC1_CFG ASEL COMP_C1b COMP_C0b COMP_C0a COMP_C1a WP TSNS_C0b TSNS_C0a TSNS_C1b TSNS_C1a PWM_C0 PWM_C1 PWMC1 PWMC0 + 1.2V/15A VOUTC1 GND FAULT_C0 CHANNEL 0 AND 1 EA-GM = 3.69ms RCOMP = 5k 10k SWC1 RUN_C1 TWO PHASE PSM SECTION 100µF ×6 PGOOD_C1 VDD25 SCL CHANNEL 0 AND 1 VOUT RANGE = LOW ILIM RANGE = LOW 1V/15A VOUTC0 GND VINS3_C0 10k PGOODVCORE SWC0 LTM4664A ALERT INTVCC 1% 36.5k PGOOD_C0 VOUT2 SHARE_CLK PINS NOT SHOWN: GL_C0 GL_C1 PHFLT_C0 PHFLT_C1 ON/OFF FREQS1 UVS2 SDA 10k PGOODS1 RUNS1 RUNS2 SYNC 10k 4.7µF 1µF FAULTS1 RUN_C0 10k 7.5k VOUT2 PGOODS1 IN– 4.7µF VDD33 VDD25 VDD33 INTVCCS1 GND IN+ 10µF 25V ×4 19.6k GND FREQS2 1% 60.4k ADDITIONAL 30W FROM VOUT2 VOUT2 CIRCUIT BREAKER TRIP EXTVCCS1 FAULTS2 PGOODS1 MAIN BULK 5.1V OVP_SET INSNSS1+ INSNSS1– SW1 RSENSE 10mΩ VINS1 SW2 UVS1 VOUT1 VINS2F INSNS2+ SW4 INSNS2– INTVCCS2 HYS_PRGMS1 VOUT2 4.7µF TIMERS1 GND HYS_PRGMS2 4:1 VOLTAGE DIVIDER 100k TIMERS2 0.068µF 49.9k 100V 2.2µF ×2 100V 10µF ×8 50V 1% 10k SW3 0.068µF 10µF ×8 50V VINS2 100k OVP_TRIP 10µF ×2 50V EXTVCC VDD25 1% 14.3k 100pF 2200pF 100pF 2200pF +5V 50mA 1% 22.6k 1% 2.43k 1% 32.4k 1% 22.6k 1% 14.3k 1% 14.3k 4664A F49 Figure 49. 30V – 58V to 1V and 1.2V at 15A, with Additional 30W from VOUT2. Integrated Power System Management Features Accessible Over 2-Wire I2C/SMBus/PMBus Serial Interface. For Evaluation and More Information, See Demo Boards DC2143 88 Rev. 0 For more information www.analog.com LTM4664A TYPICAL APPLICATIONS 10µF ×2 50V V OUT1A 1µF 10k EXTVCCS2 RSENSE1 10mΩ OVP_SET OVP_TRIP VOUT2_SET INTVCCS1 FAULTS1 1% 100k VOUT2A INTVCCA 4.7µF VDD33A VDD25A VDD33A 10k SGND_C0_C1 VINS3_C1 VOSNS+ _C0 INTVCC VOSNS– _C0 VDD33 PGOOD_C1 VDD25 VDD25A 1% 14.3k PWMC1A PWMC0A 10k 1% 32.4k 49.9k 100V OVP_TRIP OVP_SET VOUT2_SET INTVCCS1 PGOODS1 PGOODS2 RUNS1 ON/OFFB PGOOD_C0 VOUT2 VINS3_C0 SGND_C0_C1 VINS3_C1 VOSNS+ _C0 FAULT_C1 COMPH 0.9V CHANNELS GM = 3.69ms RCOMP = 3.4k VOSNS– 4700pF FSWPH_CFG VOUTC1_CFG VOUTC0_CFG VTRIMC0_CFG VOSNS– VOSNS– _C1 EXTVCC 1% 14.3k COMPL 100pF VTRIMC1_CFG ASEL COMP_C1a COMP_C0a COMP_C0b COMP_C1b WP TSNS_C0b TSNS_C0a TSNS_C1b SCL TSNS_C1a SHARE_CLK ALL CHANNELS HAVE VOUT RANGE = LOW ILIM RANGE = LOW 1.2V GM = 3.69ms CHANNEL RCOMP = 4k 470µF ×4 4V VOSNS+ VOSNS+ _C1 SYNC PWMC1B TWO PHASE PSM 60A SECTION PWM C0B PINS NOT SHOWN: GL_C0 GL_C1 PHFLT_C0 LOAD 220µF ×2 4V SGND_C0_C1 FAULT_C0 ALERT VOSNS+ VOSNS– VOUTC1 GND RUN_C1 SDA INTVCCB SWC1 PWM_C0 ALERT 220µF ×2 4V PGOOD_C1 PGOODVCORE PWM_C1 SCL SDA VOSNS+ VOSNS– _C0 RUN_C0 SYNC 10k 0.9V/90A VOUTC0 GND INTVCCB INTVCC 4.7µF VDD33B V DD33 VDD25B VDD25 SHARECLK 1% 36.5k PGOODVCORE SWC0 LTM4664A (B) IN– FAULT 10k PGOODS1B FREQS1 IN+ PGOODS2A 4.7µF 1µF FAULTS1 UVS2 10µF ×4 25V 7.5k VOUT2B SGNDS1 FREQS2 VOUT2B 19.6k EXTVCCS1 FAULTS2 1% 1% 12.1k 100k VOUT2B CIRCUIT BREAKER TRIP PGOODS1B RUNS2 1% 60.4k MAIN BULK 5.1V OVP_SET INSNSS1+ INSNSS1– VINS1 RSENSE2 10mΩ SW1 VOUT1 UVS1 VINS2F INSNS1+ SW2 10µF ×8 50V 1% 6.04k 2.2µF 100V ×2 GND PGOODS2A 1% 14.3k 1% 14.3k VIN 40V – 58V INSNS1 SW4 HYS_PRGMS1 EXTVCCS2 HYS_PRGMS2 VOUT2B 1µF TIMERS1 INTVCCS2 4.7µF TIMERS2 GND 100k 1.65k COMPL 1% 100k VINS2 0.068µF 1% 3.24k 1% 32.4 VOUT1B 10µF ×8 50V SW3 100k COMPH – 10µF ×2 50V 4:1 VOLTAGE DIVIDER 2200pF 220pF PINS NOT SHOWN: GL_C0 GL_C1 PHFLT_C0 PHFLT_C1 0.068µF VOSNS– +5V BIAS 50mA EXTVCC FSWPH_CFG VOUTC1_CFG VOUTC0_CFG VTRIMC0_CFG VTRIMC1_CFG ASEL ALERT COMP_C1a SDA COMP_C0a SCL DUAL 30A PSM SECTION 220µF ×2 4V VOSNS+ VOSNS– _C1 SHARE_CLK COMP_C0b SDA ALERT SYNC COMP_C1b SCL LOAD VOSNS+ _C1 FAULT_C1 WP CLK SHARE TSNS_C0b SYNC 10k TSNS_C0a 10k 470µF PGOODVCORE SGND_C0_C1 FAULT_C0 TSNS_C1b 10k + SWC1 TSNS_C1a 10k FAULT 100µF ×3 VOUTC1 GND RUN_C1 PWM_C0 10k 1.2V/30A VOUTC0 GND VINS3_C0 PWM_C1 10k 10k 10k PGOOD1P2V SWC0 LTM4664 (A) – RUN_C0 PGOODS2A 1% 36.5k PGOOD_C0 VOUT2 IN INTVCCA FREQS1 IN+ 10µF ×4 25V ON/OFFA RUNS1 RUNS2 UVS2 1% 12.1k 10k PGOODS1A PGOODS1 FREQS2 1% 60.4k 4.7µF 1µF SGNDS1 PGOODS2 7.5k VOUT2A EXTVCCS1 FAULTS2 PGOODS1A 19.6k CIRCUIT BREAKER TRIP GND PGOODS2A VOUT2A MAIN BULK 5.1V OVP_SET INSNSS1+ INSNSS1– SW1 VINS1 SW2 UVS1 VOUT1 VINS2F INSNS2+ SW3 SW4 INSNS2– INTVCCS2 HYS_PRGMS1 VOUT2A 4.7µF TIMERS1 GND HYS_PRGMS2 TIMERS2 4:1 VOLTAGE DIVIDER 100k 49.9k 100V 2.2µF ×2 100V 10µF ×8 50V 1% 6.04k VINS2 0.068µF 0.068µF VIN 40V – 58V 1% 100k 10µF ×8 50V 100k 1% 22.6k 1% 1.65k 1% 1.65k +5V BIAS 50mA VDD25B 1% 14.3k 4664A F50 Figure 50. 48V-58V Input, Converting 1.2V at 30A, and 0.9V at 90A. Power System Management Features Accessible Through LTM4664A Over 2-Wire I2C/SMBus/PMBus Serial Interface. Rev. 0 For more information www.analog.com 89 LTM4664A PMBus COMMAND DETAILS ADDRESSING AND WRITE PROTECT CMD CODE 0x00 0x05 0x06 COMMAND NAME PAGE PAGE_PLUS_WRITE PAGE_PLUS_READ DATA DEFAULT TYPE PAGED FORMAT UNITS NVM VALUE R/W Byte N Reg 0x00 W Block N Block N R/W R/W Byte N Reg Y 0x00 DESCRIPTION Provides integration with multi-page PMBus devices. Write a supported command directly to a PWM channel. Read a supported command directly from a PWM channel. 0x10 Level of protection provided by the device against accidental changes. 0xE6 Sets the 7-bit I2C address byte. 0xFA Common address for PolyPhase outputs to adjust common parameters. WRITE_PROTECT MFR_ADDRESS MFR_RAIL_ADDRESS R/W Byte R/W Byte N Y Reg Reg Y Y 0x4F 0x80 PAGE The PAGE command provides the ability to configure, control and monitor both PWM channels through only one physical address, either the MFR_ADDRESS or GLOBAL device address. Each PAGE contains the operating commands for one PWM channel. Pages 0x00 and 0x01 correspond to Channel 0 and Channel 1, respectively, in this device. Setting PAGE to 0xFF applies any following paged commands to both outputs. With PAGE set to 0xFF the LTM4664A will respond to read commands as if PAGE were set to 0x00 (Channel 0 results). This command has one data byte. PAGE_PLUS_WRITE The PAGE_PLUS_WRITE command provides a way to set the page within a device, send a command, and then send the data for the command, all in one communication packet. Commands allowed by the present write protection level may be sent with PAGE_PLUS_WRITE. The value stored in the PAGE command is not affected by PAGE_PLUS_WRITE. If PAGE_PLUS_WRITE is used to send a non-paged command, the Page Number byte is ignored. This command uses Write Block protocol. An example of the PAGE_PLUS_WRITE command with PEC sending a command that has two data bytes is shown in Figure 51. 1 7 S SLAVE ADDRESS 1 1 W PAGE_PLUS A A COMMAND CODE 8 8 LOWER DATA BYTE 1 8 BLOCK COUNT (= 4) 1 8 A PAGE NUMBER 1 8 1 8 1 1 A UPPER DATA BYTE A PEC BYTE A P 1 8 1 A COMMAND CODE A … 4664A F54 Figure 51. Example of PAGE_PLUS_WRITE PAGE_PLUS_READ The PAGE_PLUS_READ command provides the ability to set the page within a device, send a command, and then read the data returned by the command, all in one communication packet . 90 Rev. 0 For more information www.analog.com LTM4664A PMBus COMMAND DETAILS The value stored in the PAGE command is not affected by PAGE_PLUS_READ. If PAGE_PLUS_READ is used to access data from a non-paged command, the Page Number byte is ignored. This command uses the Process Call protocol. An example of the PAGE_PLUS_READ command with PEC is shown in Figure 52. 1 7 S SLAVE ADDRESS 1 7 Sr SLAVE ADDRESS 1 R 1 1 W PAGE_PLUS A A COMMAND CODE 8 1 8 A BLOCK COUNT (= 2) 1 8 BLOCK COUNT (= 2) 1 8 A LOWER DATA BYTE 1 8 A PAGE NUMBER 1 8 1 A COMMAND CODE A 1 8 1 8 A UPPER DATA BYTE A PEC BYTE 1 … 1 NA P 4664A F55 Figure 52. Example of PAGE_PLUS_READ Note: PAGE_PLUS commands cannot be nested. A PAGE_PLUS command cannot be used to read or write another PAGE_PLUS command. If this is attempted, the LTM4664A will NACK the entire PAGE_PLUS packet and issue a CML fault for Invalid/Unsupported Data. WRITE_PROTECT The WRITE_PROTECT command is used to control writing to the LTM4664A device. This command does not indicate the status of the WP pin which is defined in the MFR_COMMON command. The WP pin takes precedence over the value of this command. BYTE MEANING 0x80 Disable all writes except to the WRITE_PROTECT, PAGE, MFR_ EE_UNLOCK, and STORE_USER_ALL commands. 0x40 Disable all writes except to the WRITE_PROTECT, PAGE, MFR_EE_UNLOCK, MFR_CLEAR_PEAKS, STORE_USER_ALL, OPERATION and CLEAR_FAULTS command. Individual fault bits can be cleared by writing a 1 to the respective bits in the STATUS commands. 0x20 Disable all writes except to the WRITE_PROTECT, OPERATION, MFR_EE_UNLOCK, MFR_CLEAR_PEAKS, CLEAR_FAULTS, PAGE, ON_OFF_CONFIG, VOUT_COMMAND and STORE_USER_ ALL. Individual fault bits can be cleared by writing a 1 to the respective bits in the STATUS commands. 0x10 Reserved, must be 0 0x08 Reserved, must be 0 0x04 Reserved, must be 0 0x02 Reserved, must be 0 0x01 Reserved, must be 0 Enable writes to all commands when WRITE_PROTECT is set to 0x00. If WP pin is high, PAGE, OPERATION, MFR_CLEAR_PEAKS, MFR_EE_UNLOCK, WRITE_PROTECT and CLEAR_ FAULTS commands are supported. Individual fault bits can be cleared by writing a 1 to the respective bits in the STATUS commands. Rev. 0 For more information www.analog.com 91 LTM4664A PMBus COMMAND DETAILS MFR_ADDRESS The MFR_ADDRESS command byte sets the 7 bits of the PMBus slave address for this device. Setting this command to a value of 0x80 disables device addressing. The GLOBAL device address, 0x5A and 0x5B, cannot be deactivated. If RCONFIG is set to ignore, the ASEL pin is still used to determine the LSB of the channel address. If the ASEL pin is open, the LTM4664A will use the MFR_ADDRESS value stored in NVM to construct the effective address of the part. This command has one data byte. MFR_RAIL_ADDRESS The MFR_RAIL_ADDRESS command enables direct device address access to the PAGE activated channel. The value of this command should be common to all devices attached to a single power supply rail. The user should only perform command writes to this address. If a read is performed from this address and the rail devices do not respond with EXACTLY the same value, the LTM4664A will detect bus contention and may set a CML communications fault. Setting this command to a value of 0x80 disables rail device addressing for the channel. This command has one data byte. GENERAL CONFIGURATION COMMANDS COMMAND NAME CMD CODE DESCRIPTION TYPE DATA PAGED FORMAT UNITS NVM DEFAULT VALUE MFR_CHAN_CONFIG 0xD0 Configuration bits that are channel specific. R/W Byte Y Reg Y 0x10 MFR_CONFIG_ALL 0xD1 General configuration bits. R/W Byte N Reg Y 0x21 MFR_CHAN_CONFIG General purpose configuration command common to multiple LTC products. BIT MEANING 7 Reserved 6 Reserved 5 Reserved 4 Disable RUN Low. When asserted the RUN pin is not pulsed low if commanded OFF. 3 Enable short cycle recognition if this bit is set to a 1. 2 SHARE_CLOCK control. If SHARE_CLOCK is held low, the output is disabled. 1 No FAULT ALERT, ALERT is not pulled low if FAULT is pulled low externally. Assert this bit if either POWER_GOOD or VOUT_UVUF are propagated on FAULT. 0 Disables the VOUT decay value requirement for MFR_RETRY_TIME and tOFF(MIN) processing. When this bit is set to a 0, the output must decay to less than 12.5% of the programmed value for any action that turns off the rail including a fault, an OFF/ON command, or a toggle of RUN from high to low to high. This command has one data byte. 92 Rev. 0 For more information www.analog.com LTM4664A PMBus COMMAND DETAILS A short cycle event occurs whenever the PWM channel is commanded back ON, or reactivated, after the part has been commanded OFF and is processing either the TOFF_DELAY or the TOFF_FALL states. The PWM channel can be turned ON and OFF through either the RUN pin and or the PMBus OPERATION command. If the PWM channel is reactivated during the TOFF_DELAY, the part will perform the following: 1. Immediately tri-state the PWM channel output; 2. Start the retry delay timer as specified by the tOFF(MIN). 3. After the tOFF(MIN) value has expired, the PWM channel will proceed to the TON_DELAY state and the STATUS_ MFR_SPECIFIC bit #1 will assert. If the PWM channel is reactivated during the TOFF_FALL, the part will perform the following: 1. Stop ramping down the PWM channel output; 2. Immediately tri-state the PWM channel output; 3. Start the retry delay timer as specified by the tOFF(MIN). 4. After the tOFF(MIN) value has expired, the PWM channel will proceed to the TON_DELAY state and the STATUS_ MFR_SPEFIFIC bit #1 will assert. If the short cycle event occurs and the short cycle MFR_CHAN_CONFIG bit is not set, the PWM channel state machine will complete its TOFF_DELAY and TOFF_FALL operations as previously commanded by the user. MFR_CONFIG_ALL General purpose configuration command common to multiple LTC products. BIT MEANING 7 Enable Fault Logging 6 Ignore Resistor Configuration Pins 5 Mask PMBus, Part II, Section 10.9.1 Violations 4 Disable SYNC output 3 Enable 255ms PMBus timeout 2 A valid PEC required for PMBus writes to be accepted. If this bit is not set, the part will accept commands with invalid PEC. 1 Enable the use of PMBus clock stretching 0 Execute CLEAR_FAULTS on rising edge of either RUN pin. This command has one data byte. ON/OFF/MARGIN COMMAND NAME CMD CODE DESCRIPTION ON_OFF_CONFIG 0x02 OPERATION 0x01 MFR_RESET 0xFD TYPE PAGED RUN pin and PMBus bus on/off command configuration. R/W Byte Y Operating mode control. On/off, margin high and margin low. R/W Byte Y Commanded reset without requiring a power-down. Send Byte N DATA FORMAT UNITS NVM DEFAULT VALUE Reg Y 0x1E Reg Y 0x80 NA Rev. 0 For more information www.analog.com 93 LTM4664A PMBus COMMAND DETAILS ON_OFF_CONFIG The ON_OFF_CONFIG command specifies the combination of RUNn pin input state and PMBus commands needed to turn the PWM channel on and off. Supported Values: VALUE MEANING 0x1F OPERATION value and RUNn pin must both command the device to start/run. Device executes immediate off when commanded off. 0x1E OPERATION value and RUNn pin must both command the device to start/run. Device uses TOFF_ command values when commanded off. 0x17 RUNn pin control with immediate off when commanded off. OPERATION on/off control ignored. 0x16 RUNn pin control using TOFF_ command values when commanded off. OPERATION on/off control ignored. Programming an unsupported ON_OFF_CONFIG value will generate a CML fault and the command will be ignored. This command has one data byte. OPERATION The OPERATION command is used to turn the unit on and off in conjunction with the input from the RUNn pins. It is also used to cause the unit to set the output voltage to the upper or lower MARGIN VOLTAGEs. The unit stays in the commanded operating mode until a subsequent OPERATION command or change in the state of the RUNn pin instructs the device to change to another mode. If the part is stored in the MARGIN_LOW/HIGH state, the next RESET or POWER_ON cycle will ramp to that state. If the OPERATION command is modified, for example ON is changed to MARGIN_LOW, the output will move at a fixed slope set by the VOUT_TRANSITION_RATE. The default operation command is sequence off. If VIN is applied to a part with factory default programming and the VOUT_CONFIG resistor configuration pins are not installed, the outputs will be commanded off. The part defaults to the Sequence Off state. This command has one data byte. Supported Values: VALUE MEANING 0xA8 Margin high. 0x98 Margin low. 0x80 On (VOUT back to nominal even if bit 3 of ON_OFF_CONFIG is not set). 0x40* Soft off (with sequencing). 0x00* Immediate off (no sequencing). *Device does not respond to these commands if bit 3 of ON_OFF_CONFIG is not set. Programming an unsupported OPERATION value will generate a CML fault and the command will be ignored. This command has one data byte. MFR_RESET This command provides a means to reset the LTM4664A PSM from the serial bus. This forces the LTM4664A PSM to turn off both PWM channels, load the operating memory from internal EEPROM, clear all faults and then perform a soft-start of both PWM channels, if enabled. This write-only command has no data bytes. 94 Rev. 0 For more information www.analog.com LTM4664A PMBus COMMAND DETAILS PWM CONFIGURATION COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA DEFAULT FORMAT UNITS NVM VALUE MFR_PWM_COMP 0xD3 PWM loop compensation configuration R/W Byte Y Reg Y 0x28 MFR_PWM_MODE 0xD4 Configuration for the PWM engine. R/W Byte Y Reg Y 0xC7 MFR_PWM_CONFIG 0xF5 Set numerous parameters for the DC/DC controller including phasing. R/W Byte N Reg Y 0x10 FREQUENCY_SWITCH 0x33 Switching frequency of the controller. R/W Word N L11 Y 350kHz 0xFABC kHz MFR_PWM_MODE The MFR_PWM_MODE command sets important PWM controls for each channel. The MFR_PWM_MODE command allows the user to program the PWM controller to use discontinuous (pulse-skipping mode), or forced continuous conduction mode. BIT 7 0b 1b 6 5 MEANING Use High Range of ILIMIT Low Current Range High Current Range Enable Servo Mode External temperature sense: 0: ΔVBE measurement. [4:3] 2 1 1b 0b Bit[0] 0b 1b Now reserved, ΔVBE only supported. Reserved Reserved, always low DCR current sense VOUT Range The maximum output voltage is 2.75V The maximum output voltage is 3.6V Mode Discontinuous Forced Continuous Bit [7] of this command determines if the part is in high range or low range of the IOUT_OC_FAULT_LIMIT command. Changing this bit value changes the PWM loop gain and compensation. This bit value should not be changed when the channel output is active. Writing this bit when the channel is active will generate a CML fault. Bit [6] The LTM4664A PSM will not servo while the part is OFF, ramping on or ramping off. When set to a one, the output servo is enabled. The output set point DAC will be slowly adjusted to minimize the difference between the READ_VOUT_ADC and the VOUT_COMMAND (or the appropriate margined value). The LTM4664A PSM computes temperature in °C from ∆VBE measured by the ADC at the TSNSn pin as T = (G • ΔVBE • q/(K • ln(16))) – 273.15 + O Rev. 0 For more information www.analog.com 95 LTM4664A PMBus COMMAND DETAILS For both equations, G = MFR_TEMP_1_GAIN • 2–14, and O = MFR_TEMP_1_OFFSET Bit[2] is now reserved, and Ultra Low DCR mode is default. Bit[1] of this command determines if the part is in high range or low voltage range. Changing this bit value changes the PWM loop gain and compensation. This bit value should not be changed when the channel output is active. Writing this bit when the channel is active will generate a CML fault. Bit[0] determines if the PWM mode of operation is discontinuous (pulse-skipping mode), or forced continuous conduction mode. Whenever the channel is ramping on, the PWM mode will be discontinuous, regardless of the value of this bit. This command has one data byte. MFR_PWM_COMP The MFR_PWM_COMP command sets the gm of the PWM channel error amplifiers and the value of the internal RITHn compensation resistors. This command affects the loop gain of the PWM output which may require modifications to the external compensation network. BIT MEANING BIT [7:5] Error Amplifier GM Adjust (ms) 000b 1.00 001b 1.68 010b 2.35 011b 3.02 100b 3.69 101b 4.36 110b 5.04 111b 5.73 BIT [4:0] RCOMP (kΩ) 00000b 0 00001b 0.25 00010b 0.5 00011b 0.75 00100b 1 00101b 1.25 00110b 1.5 00111b 1.75 01000b 2 01001b 2.5 01010b 3 01011b 3.5 01100b 4 01101b 4.5 01110b 5 96 Rev. 0 For more information www.analog.com LTM4664A PMBus COMMAND DETAILS 01111b 5.5 10000b 6 10001b 7 10010b 8 10011b 9 10100b 11 10101b 13 10110b 15 10111b 17 11000b 20 11001b 24 11010b 28 11011b 32 11100b 38 11101b 46 11110b 54 11111b 62 This command has one data byte. MFR_PWM_CONFIG The MFR_PWM_CONFIG command sets the switching frequency phase offset with respect to the falling edge of the SYNC signal. The part must be in the OFF state to process this command. Either the RUN pins must be low or the channels must be commanded off. If either channel is in the RUN state and this command is written, the command will be NACK’d and a BUSY fault will be asserted. BIT MEANING 7 Reserved [6:5] 00b 01b 10b 11b 4 BIT [2:0] Input current sense gain. 2x gain. 0mV to 50mV range. 4x gain. 0mV to 20mV range. 8x gain. 0mV to 5mV range. Reserved Share Clock Enable : If this bit is 1, the SHARE_CLK pin will not be released until VIN > VIN_ON. The SHARE_CLK pin will be pulled low when VIN < VIN_OFF. If this bit is 0, the SHARE_ CLK pin will not be pulled low when VIN < VIN_OFF except for the initial application of VIN. CHANNEL 0 (DEGREES) CHANNEL 1 (DEGREES) 000b 0 180 001b 90 270 010b 0 240 011b 0 120 100b 120 240 101b 60 240 110b 120 300 Rev. 0 For more information www.analog.com 97 LTM4664A PMBus COMMAND DETAILS FREQUENCY_SWITCH The FREQUENCY_SWITCH command sets the switching frequency, in kHz, of the LTM4664A. Supported Frequencies: VALUE [15:0] 0x0000 0xF3E8 0xFABC 0xFB52 0xFBE8 0x023F 0x028A 0x02EE 0x03E8 RESULTING FREQUENCY (TYP) External Oscillator 250kHz 350kHz 425kHz 500kHz 575kHz 650kHz 750kHz 1000kHz The part must be in the OFF state to process this command. The RUN pin must be low or both channels must be commanded off. If the part is in the RUN state and this command is written, the command will be NACK'd and a BUSY fault will be asserted. When the part is commanded off and the frequency is changed, a PLL_UNLOCK status may be detected as the PLL locks onto the new frequency. This command has two data bytes and is formatted in Linear_5s_11s format. VOLTAGE Input Voltage and Limits COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM VIN_OV_FAULT_LIMIT 0x55 Input supply overvoltage fault limit. R/W Word N L11 V Y 15.5 0xD3E0 VIN_UV_WARN_LIMIT 0x58 Input supply undervoltage warning limit. R/W Word N L11 V Y 4.65 0xCA53 VIN_ON 0x35 Input voltage at which the unit should start power conversion. R/W Word N L11 V Y 4.75 0xCA60 VIN_OFF 0x36 Input voltage at which the unit should stop power conversion. R/W Word N L11 V Y 4.5 0xCA40 R Word N L11 mΩ N 1000 0x03E8 MFR_RVIN The resistance value of the VIN pin filter element in milliohms set at factory. DEFAULT VALUE VIN_OV_FAULT_LIMIT The VIN_OV_FAULT_LIMIT command sets the value of the input voltage measured by the ADC, in volts, that causes an input overvoltage fault. This command has two data bytes in Linear_5s_11s format. 98 Rev. 0 For more information www.analog.com LTM4664A PMBus COMMAND DETAILS VIN_UV_WARN_LIMIT The VIN_UV_WARN_LIMIT command sets the value of input voltage measured by the ADC that causes an input undervoltage warning. This warning is disabled until the input exceeds the input startup threshold value set by the VIN_ON command and the unit has been enabled. If the VIN Voltage drops below the VIN_OV_WARN_LIMIT the device: • Sets the INPUT Bit Is the STATUS_WORD • Sets the VIN Undervoltage Warning Bit in the STATUS_INPUT Command • Notifies the Host by Asserting ALERT, unless Masked VIN_ON The VIN_ON command sets the input voltage, in Volts, at which the unit starts power conversion. This command has two data bytes and is formatted in Linear_5s_11s format. VIN_OFF The VIN_OFF command sets the input voltage, in Volts, at which the unit stops power conversion. This command has two data bytes and is formatted in Linear_5s_11s format. MFR_RVIN The MFR_RVIN command is not available, MFR_RVIN is set at factory assembly with 1Ω. This command has two data bytes and is formatted in Linear_5s_11s format. Output Voltage and Limits COMMAND NAME VOUT_MODE VOUT_MAX VOUT_OV_FAULT_ LIMIT CMD CODE DESCRIPTION 0x20 Output voltage format and exponent (2–12). 0x24 Upper limit on the output voltage the unit can command regardless of any other commands. 0x40 Output overvoltage fault limit. VOUT_OV_WARN_ LIMIT 0x42 Output overvoltage warning limit. VOUT_MARGIN_HIGH 0x25 VOUT_COMMAND 0x21 Margin high output voltage set point. Must be greater than VOUT_COMMAND. Nominal output voltage set point. VOUT_MARGIN_LOW 0x26 VOUT_UV_WARN_ LIMIT 0x43 Margin low output voltage set point. Must be less than VOUT_COMMAND. Output undervoltage warning limit. VOUT_UV_FAULT_ LIMIT 0x44 Output undervoltage fault limit. MFR_VOUT_MAX 0xA5 Maximum allowed output voltage. TYPE R Byte PAGED Y DATA FORMAT Reg UNITS NVM R/W Word Y L16 V Y R/W Word R/W Word R/W Word Y L16 V Y Y L16 V Y Y L16 V Y R/W Word R/W Word Y L16 V Y Y L16 V Y R/W Word R/W Word R Word Y L16 V Y Y L16 V Y Y L16 V DEFAULT VALUE 2–12 0x14 1.8 0x2CCD 1.1 0x119A 1.075 0x1133 1.05 0x10CD 1.0 0x1000 0.95 0x0F33 0.925 0x0ECD 0.9 0x0E66 7.8 0x1CCD Rev. 0 For more information www.analog.com 99 LTM4664A PMBus COMMAND DETAILS VOUT_MODE The data byte for VOUT_MODE command, used for commanding and reading output voltage, consists of a 3-bit mode (only linear format is supported) and a 5-bit parameter representing the exponent used in output voltage Read/Write commands. This read-only command has one data byte. VOUT_MAX The VOUT_MAX command sets an upper limit on any voltage, including VOUT_MARGIN_HIGH, the unit can command regardless of any other commands or combinations. The maximum allowed value of this command is 3.6V. The maximum output voltage the LTM4664A PSM can produce is 1.8V including VOUT_MARGIN_HIGH. However, the VOUT_OV_FAULT_LIMIT can be commanded as high as 3.6V. This command has two data bytes and is formatted in Linear_16u format. VOUT_OV_FAULT_LIMIT The VOUT_OV_FAULT_LIMIT command sets the value of the output voltage measured by the OV supervisor comparator at the sense pins, in volts, which causes an output overvoltage fault. If the VOUT_OV_FAULT_LIMIT is modified and the part is in the RUN state, allow 10ms after the command is modified to assure the new value is being honored. The part indicates if it is busy making a calculation. Monitor bits 5 and 6 of MFR_COMMON. Either bit is low if the part is busy. If this wait time is not honored and the VOUT_COMMAND is modified above the old overvoltage limit, an OV condition might temporarily be detected resulting in undesirable behavior and possible damage to the switcher. If VOUT_OV_FAULT_RESPONSE is set to OV_PULLDOWN or 0x00, the FAULT pin will not assert if VOUT_OV_FAULT is propagated. The LTM4664A PSM will pull the TG low and assert the BG bit as soon as the overvoltage condition is detected. This command has two data bytes and is formatted in Linear_16u format. VOUT_OV_WARN_LIMIT The VOUT_OV_WARN_LIMIT command sets the value of the output voltage measured by the ADC at the sense pins, in volts, which causes an output voltage high warning. The MFR_VOUT_PEAK value can be used to determine if this limit has been exceeded. In response to the VOUT_OV_WARN_LIMIT being exceeded, the device: • Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE • Sets the VOUT bit in the STATUS_WORD • Sets the VOUT Overvoltage Warning bit in the STATUS_VOUT command • Notifies the host by asserting ALERT pin, unless masked This condition is detected by the ADC so the response time may be up to tCONVERT. This command has two data bytes and is formatted in Linear_16u format. 100 Rev. 0 For more information www.analog.com LTM4664A PMBus COMMAND DETAILS VOUT_MARGIN_HIGH The VOUT_MARGIN_HIGH command loads the unit with the voltage to which the output is to be changed, in Volts, when the OPERATION command is set to “Margin High”. The value should be greater than VOUT_COMMAND. The maximum guaranteed value on VOUT_MARGIN_HIGH is 3.6V. This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_ RATE will be used if this command is modified while the output is active and in a steady-state condition. This command has two data bytes and is formatted in Linear_16u format. VOUT_COMMAND The VOUT_COMMAND consists of two bytes and is used to set the output voltage, in volts. The maximum guaranteed value on VOUT is 3.6V. This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_ RATE will be used if this command is modified while the output is active and in a steady-state condition. This command has two data bytes and is formatted in Linear_16u format. VOUT_MARGIN_LOW The VOUT_MARGIN_LOW command loads the unit with the voltage to which the output is to be changed, in volts, when the OPERATION command is set to “Margin Low”. The value must be less than VOUT_COMMAND. This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_ RATE will be used if this command is modified while the output is active and in a steady-state condition. This command has two data bytes and is formatted in Linear_16u format. VOUT_UV_WARN_LIMIT The VOUT_UV_ WARN_LIMIT command reads the value of the output voltage measured by the ADC at the sense pins, in volts, which causes an output voltage low warning. In response to the VOUT_UV_WARN_LIMIT being exceeded, the device: • Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE • Sets the VOUT bit in the STATUS_WORD • Sets the VOUT Undervoltage Warning bit in the STATUS_VOUT command • Notifies the host by asserting ALERT pin, unless masked This command has two data bytes and is formatted in Linear_16u format. VOUT_UV_FAULT_LIMIT The VOUT_UV_FAULT_LIMIT command reads the value of the output voltage measured by the UV supervisor comparator at the sense pins, in volts, which causes an output undervoltage fault. This command has two data bytes and is formatted in Linear_16u format. Rev. 0 For more information www.analog.com 101 LTM4664A PMBus COMMAND DETAILS MFR_VOUT_MAX The MFR_VOUT_MAX command is the maximum output voltage in volts for each channel, including VOUT_OV_FAULT_ LIMIT. If the output voltages are set to high range (Bit 6 of MFR_PWM_CONFIG set to a 0) MFR_VOUT_MAX is 3.6V. If the output voltage is set to low range (Bit 6 of MFR_PWM_CONFIG set to a 1) the MFR_VOUT_MAX is 2.75V. Entering a VOUT_COMMAND value greater than this will result in a CML fault and the output voltage setting will be clamped to the maximum level. This will also result in Bit 3 VOUT_MAX_Warning in the STATUS_VOUT command being set. The maximum value to program is 1.8V and maximum operating is 1.5V. This read only command has 2 data bytes and is formatted in Linear_16u format. OUTPUT CURRENT AND LIMITS COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAULT VALUE R Word Y L11 mΩ Y 0.375 0xD018 Y 3900 0x0F3C MFR_IOUT_CAL_GAIN 0xDA The ratio of the voltage at the current sense pins to the sensed current. For devices using a fixed current sense resistor, it is the resistance value in mΩ. MFR_IOUT_CAL_GAIN_TC 0xF6 Temperature coefficient of the current R/W Word sensing element. Y CF IOUT_OC_FAULT_LIMIT 0x46 Output overcurrent fault limit. R/W Word Y L11 A Y 45.0 0xE2D0 IOUT_OC_WARN_LIMIT 0x4A Output overcurrent warning limit. R/W Word Y L11 A Y 34.0 0xE230 MFR_IOUT_CAL_GAIN The MFR_IOUT_CAL_GAIN command is used to set the resistance value of the current sense resistor in milliohms. (see also MFR_IOUT_CAL_GAIN_TC). This command has two data bytes and is formatted in Linear_5s_11s format. MFR_IOUT_CAL_GAIN_TC The MFR_IOUT_CAL_GAIN_TC command allows the user to program the temperature coefficient of the IOUT_CAL_ GAIN sense resistor or inductor DCR in ppm/°C. This command has two data bytes and is formatted in 16-bit 2’s complement integer ppm. N = –32768 to 32767 • 10–6. Nominal temperature is 27°C. The MFR_IOUT_CAL_GAIN is multiplied by: [1.0 + MFR_IOUT_CAL_GAIN_TC • (READ_TEMPERATURE_1‑27)]. DCR sensing will have a typical value of 3900. The MFR_IOUT_CAL_GAIN and MFR_IOUT_CAL_GAIN_TC impact all current parameters including: READ_IOUT, MFR_IOUT_PEAK, IOUT_OC_FAULT_LIMIT and IOUT_OC_WARN_LIMIT. 102 Rev. 0 For more information www.analog.com LTM4664A PMBus COMMAND DETAILS IOUT_OC_FAULT_LIMIT The IOUT_OC_FAULT_LIMIT command sets the value of the peak output current limit, in Amperes. When the controller is in current limit, the overcurrent detector will indicate an overcurrent fault condition. The following table lists the progammable peak output current limit value in mV between ISENSE+ and ISENSE–. The actual value of current limit is (ISENSE+ – ISENSE–)/MFR_IOUT_CAL_GAIN in Amperes. MFR_PWM_MODE[7] = 1b, High Current Range (mV) ILPEAK (A) IOUT (A) MFR_PWM_MODE[7] = 0b, Use ILIM Low Range Low Current Range (mV) ILPEAK (A) IOUT (A) 18.86 Not Needed Not Needed 10.48 29.9 23.9 20.42 Not Needed Not Needed 11.34 32.4 26.4 21.14 Not Needed Not Needed 11.74* 33.54 27.54 22.27 Not Needed Not Needed 12.37 35.3 29.3 23.41 Not Needed Not Needed 13.01** 37.1 31.1 24.55 Not Needed Not Needed 13.64 38.9 32.9 25.68 Not Needed Not Needed 14.27 40.8 34.8 26.82 Not Needed Not Needed 14.90 42.6 36.6 * = Recommended for 25A Current Limit Plus Some Headroom ** = Recommended for 30A Current Limit Plus Some Headroom for Up to 1.2V Output Note: This is the peak of the current waveform. The READ_IOUT command returns the average current. The peak output current limits are adjusted with temperature based on the MFR_IOUT_CAL_GAIN_TC using the equation: Peak Current Limit = MFR_IOUT_CAL_GAIN • (1 + MFR_IOUT_CAL_GAIN_TC • (READ_TEMPERTURE_1-27.0)). The LTM4664A automatically converts currents to the appropriate internal bit value. The IOUT range is set with bit 7 of the MFR_PWM_MODE command. The IOUT_OC_FAULT_LIMIT is ignored during TON_RISE and TOFF_FALL. If the IOUT_OC_FAULT_LIMIT is exceeded, the device: • Sets the IOUT bit in the STATUS word • Sets the IOUT Overcurrent fault bit in the STATUS_IOUT • Notifies the host by asserting ALERT, unless masked This command has two data bytes and is formatted in Linear_5s_11s format. **MFR_PWM_MODE[7]=1 is the high current range for ultra low DCR sensing. This range should be used since these current threshold values are too large for the LTM4664A. *Recommended for 35% up above 25A current limit Rev. 0 For more information www.analog.com 103 LTM4664A PMBus COMMAND DETAILS IOUT_OC_WARN_LIMIT This command sets the value of the output current measured by the ADC that causes an output overcurrent warning in Amperes. The READ_IOUT value will be used to determine if this limit has been exceeded. In response to the IOUT_OC_WARN_LIMIT being exceeded, the device: • Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE • Sets the IOUT bit in the STATUS_WORD • Sets the IOUT Overcurrent Warning bit in the STATUS_IOUT command, and • Notifies the host by asserting ALERT pin, unless masked The IOUT_OC_FAULT_LIMIT is ignored during TON_RISE and TOFF_FALL. This command has two data bytes and is formatted in Linear_5s_11s format Input Current and Limits COMMAND NAME MFR_IIN_CAL_GAIN CMD CODE DESCRIPTION 0xE8 The resistance value of the input current sense element in mΩ. TYPE R/W Word DATA FORMAT L11 UNITS mΩ NVM Y DEFAULT VALUE 2 0xC200 MFR_IIN_CAL_GAIN The MFR_IIN_CAL_GAIN command is used to set the resistance value of the input current sense resistor in milliohms. (see also READ_IIN). This command has two data bytes and is formatted in Linear_5s_11s format. COMMAND NAME IIN_OC_WARN_LIMIT TYPE PAGED DATA FORMAT UNITS NVM R/W Word N L11 A Y CMD CODE DESCRIPTION 0x5D Input overcurrent warning limit. DEFAULT VALUE 10.0 0xD280 IIN_OC_WARN_LIMIT The IIN_OC_WARN_LIMIT command sets the value of the input current measured by the ADC, in amperes, that causes a warning indicating the input current is high. The READ_IIN value will be used to determine if this limit has been exceeded. In response to the IIN_OC_WARN_LIMIT being exceeded, the device: • Sets the OTHER bit in the STATUS_BYTE • Sets the INPUT bit in the upper byte of the STATUS_WORD • Sets the IIN Overcurrent Warning bit[1] in the STATUS_INPUT command, and • Notifies the host by asserting ALERT pin This command has two data bytes and is formatted in Linear_5s_11s format. 104 Rev. 0 For more information www.analog.com LTM4664A PMBus COMMAND DETAILS TEMPERATURE External Temperature Calibration COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA DEFAULT FORMAT UNITS NVM VALUE MFR_TEMP_1_GAIN 0xF8 Sets the slope of the external temperature sensor. R/W Word Y CF MFR_TEMP_1_OFFSET 0xF9 Sets the offset of the external temperature sensor. R/W Word Y L11 C Y 0.995 0x3FAE Y 0.0 0x8000 MFR_TEMP_1_GAIN The MFR_TEMP_1_GAIN command will modify the slope of the external temperature sensor to account for nonidealities in the element and errors associated with the remote sensing of the temperature in the inductor. This command has two data bytes and is formatted in 16-bit 2’s complement integer. The effective gain adjustment is N • 2–14. The nominal value is 1. MFR_TEMP_1_OFFSET The MFR_TEMP_1_OFFSET command will modify the offset of the external temperature sensor to account for nonidealities in the element and errors associated with the remote sensing of the temperature in the inductor. This command has two data bytes and is formatted in Linear_5s_11s format. External Temperature Limits COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAULT VALUE OT_FAULT_LIMIT 0x4F Power stage overtemperature fault limit. R/W Word Y L11 C Y 128 0xF200 OT_WARN_LIMIT 0x51 Power stage overtemperature warning limit. R/W Word Y L11 C Y 125 0xEBE8 UT_FAULT_LIMIT 0x53 Power stage undertemperature fault limit. R/W Word Y L11 C Y –45 0xE530 OT_FAULT_LIMIT The OT_FAULT_LIMIT command sets the value of the external sense temperature measured by the ADC, in degrees Celsius, which causes an overtemperature fault. The READ_TEMPERATURE_1 value will be used to determine if this limit has been exceeded. This command has two data bytes and is formatted in Linear_5s_11s format. OT_WARN_LIMIT The OT_WARN_LIMIT command sets the value of the external sense temperature measured by the ADC, in degrees Celsius, which causes an overtemperature warning. The READ_TEMPERATURE_1 value will be used to determine if this limit has been exceeded. Rev. 0 For more information www.analog.com 105 LTM4664A PMBus COMMAND DETAILS In response to the OT_WARN_LIMIT being exceeded, the device: • Sets the TEMPERATURE bit in the STATUS_BYTE • Sets the Overtemperature Warning bit in the STATUS_TEMPERATURE command, and • Notifies the host by asserting ALERT pin, unless masked This command has two data bytes and is formatted in Linear_5s_11s format. UT_FAULT_LIMIT The UT_FAULT_LIMIT command sets the value of the power stage sense temperature measured by the ADC, in degrees Celsius, which causes an undertemperature fault. The READ_TEMPERATURE_1 value will be used to determine if this limit has been exceeded. Note: If the temp sensors are not installed, the UT_FAULT_LIMIT can be set to –275°C and UT_FAULT_LIMIT response set to ignore to avoid ALERT being asserted. This command has two data bytes and is formatted in Linear_5s_11s format. TIMING Timing—On Sequence/Ramp COMMAND NAME TON_DELAY CMD CODE DESCRIPTION 0x60 Time from RUN and/or Operation on to output rail turn-on. TON_RISE 0x61 Time from when the output starts to rise until the output voltage reaches the VOUT commanded value. TON_MAX_FAULT_LIMIT 0x62 Maximum time from the start of TON_RISE for VOUT to cross the VOUT_UV_FAULT_LIMIT. VOUT_TRANSITION_RATE 0x27 Rate the output changes when VOUT commanded to a new value. TYPE PAGED R/W Word Y DATA FORMAT L11 UNITS ms NVM Y DEFAULT VALUE 0.0 0x8000 3 0xC300 R/W Word Y L11 ms Y R/W Word Y L11 ms Y 5 0xCA80 R/W Word Y L11 V/ms Y 0.001 0x8042 TON_DELAY The TON_DELAY command sets the time, in milliseconds, from when a start condition is received until the output voltage starts to rise. Values from 0ms to 83 seconds are valid. The resulting turn-on delay will have a typical delay of 270µs for TON_DELAY = 0 and an uncertainty of ±50µs for all values of TON_DELAY. This command has two data bytes and is formatted in Linear_5s_11s format. TON_RISE The TON_RISE command sets the time, in milliseconds, from the time the output starts to rise to the time the output enters the regulation band. Values from 0 to 1.3 seconds are valid. The part will be in discontinuous mode during TON_RISE events. If TON_RISE is less than 0.25ms, the LTM4664A digital slope will be bypassed and the output voltage transition will only be controlled by the analog performance of the PWM switcher. The number of steps in TON_RISE is equal to TON_RISE (in ms)/0.1ms with an uncertainty of ±0.1ms. This command has two data bytes and is formatted in Linear_5s_11s format. 106 Rev. 0 For more information www.analog.com LTM4664A PMBus COMMAND DETAILS TON_MAX_FAULT_LIMIT The TON_MAX_FAULT_LIMIT command sets the value, in milliseconds, on how long the unit can attempt to power up the output without reaching the output undervoltage fault limit. A data value of 0ms means that there is no limit and that the unit can attempt to bring up the output voltage indefinitely. The maximum limit is 83 seconds. This command has two data bytes and is formatted in Linear_5s_11s format. VOUT_TRANSITION_RATE When a PMBus device receives either a VOUT_COMMAND or OPERATION (Margin High, Margin Low) that causes the output voltage to change this command set the rate in V/ms at which the output voltage changes. The commanded rate of change does not apply when the unit is commanded on or off. The maximum allowed slope is 4V/ms. This command has two data bytes and is formatted in Linear_5s_11s format. Timing—Off Sequence/Ramp COMMAND NAME TOFF_DELAY TOFF_FALL TOFF_MAX_WARN_LIMIT CMD CODE DESCRIPTION TYPE 0x64 Time from RUN and/or Operation off to R/W Word the start of TOFF_FALL ramp. Time from when the output starts to fall R/W Word 0x65 until the output reaches zero volts. Maximum allowed time, after TOFF_FALL R/W Word 0x66 completed, for the unit to decay below 12.5%. PAGED Y DATA FORMAT L11 UNITS ms NVM Y Y L11 ms Y Y L11 ms Y DEFAULT VALUE 0.0 0x8000 3 0xC300 0 0x8000 TOFF_DELAY The TOFF_DELAY command sets the time, in milliseconds, from when a stop condition is received until the output voltage starts to fall. Values from 0 to 83 seconds are valid. The resulting turn off delay will have a typical delay of 270µs for TOFF_DELAY = 0 and an uncertainty of ±50µs for all values of TOFF_DELAY. TOFF_DELAY is not applied when a fault event occurs This command has two data bytes and is formatted in Linear_5s_11s format. TOFF_FALL The TOFF_FALL command sets the time, in milliseconds, from the end of the turn-off delay time until the output voltage is commanded to zero. It is the ramp time of the VOUT DAC. When the VOUT DAC is zero, the PWM output will be set to high impedance state. The part will maintain the mode of operation programmed. For defined TOFF_FALL times, the user should set the part to continuous conduction mode. Loading the max value indicates the part will ramp down at the slowest possible rate. The minimum supported fall time is 0.25ms. A value less than 0.25ms will result in a 0.25ms ramp. The maximum fall time is 1.3 seconds. The number of steps in TOFF_FALL is equal to TOFF_FALL (in ms)/0.1ms with an uncertainty of ±0.1ms. In discontinuous conduction mode, the controller will not draw current from the load and the fall time will be set by the output capacitance and load current. This command has two data bytes and is formatted in Linear_5s_11s format. Rev. 0 For more information www.analog.com 107 LTM4664A PMBus COMMAND DETAILS TOFF_MAX_WARN_LIMIT The TOFF_MAX_WARN_LIMIT command sets the value, in milliseconds, on how long the output voltage exceeds 12.5% of the programmed voltage before a warning is asserted. The output is considered off when the VOUT voltage is less than 12.5% of the programmed VOUT_COMMAND value. The calculation begins after TOFF_FALL is complete. A data value of 0ms means that there is no limit and that the output voltage exceeds 12.5% of the programmed voltage indefinitely. Other than 0, values from 120ms to 524 seconds are valid. This command has two data bytes and is formatted in Linear_5s_11s format. Precondition for Restart COMMAND NAME CMD CODE DESCRIPTION MFR_RESTART_ DELAY 0xDC Minimum time the RUN pin is held low by the LTM4664A. TYPE PAGED DATA FORMAT UNITS NVM R/W Word Y L11 ms Y DEFAULT VALUE 150 0xF258 MFR_RESTART_DELAY This command specifies the minimum RUN off time in milliseconds. This device will pull the RUN pin low for this length of time once a falling edge of RUN has been detected. The minimum recommended value is 136ms. Note: The restart delay is different than the retry delay. The restart delay pulls RUN low for the specified time, after which a standard start-up sequence is initiated. The minimum restart delay should be equal to TOFF_DELAY + TOFF_ FALL + 136ms. Valid values are from 136ms to 65.52 seconds in 16ms increments. To assure a minimum off time, set the MFR_RESTART_DELAY 16ms longer than the desired time. The output rail can be off longer than the MFR_ RESTART_DELAY after the RUN pin is pulled high if the output decay bit 0 is enabled in MFR_CHAN_CONFIG and the output takes a long time to decay below 12.5% of the programmed value. This command has two data bytes and is formatted in Linear_5s_11s format. FAULT RESPONSE Fault Responses All Faults COMMAND NAME MFR_RETRY_ DELAY CMD CODE DESCRIPTION 0xDB Retry interval during FAULT retry mode. TYPE PAGED DATA FORMAT UNITS NVM R/W Word Y L11 ms Y DEFAULT VALUE 250 0xF3E8 MFR_RETRY_DELAY This command sets the time in milliseconds between retries if the fault response is to retry the controller at specified intervals. This command value is used for all fault responses that require retry. The retry time starts once the fault has been detected by the offending channel. Valid values are from 120ms to 83.88 seconds in 10µs increments. Note: The retry delay time is determined by the longer of the MFR_RETRY_DELAY command or the time required for the regulated output to decay below 12.5% of the programmed value. If the natural decay time of the output is too long, it is possible to remove the voltage requirement of the MFR_RETRY_DELAY command by asserting bit 0 of MFR_CHAN_CONFIG. This command has two data bytes and is formatted in Linear_5s_11s format. 108 Rev. 0 For more information www.analog.com LTM4664A PMBus COMMAND DETAILS Fault Responses Input Voltage COMMAND NAME VIN_OV_FAULT_RESPONSE CMD CODE DESCRIPTION 0x56 Action to be taken by the device when an input supply overvoltage fault is detected. TYPE R/W Byte DATA PAGED FORMAT Y UNITS Reg NVM DEFAULT VALUE Y 0x80 VIN_OV_FAULT_RESPONSE The VIN_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an input overvoltage fault. The data byte is in the format given in Table 17. The device also: • Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE • Set the INPUT bit in the upper byte of the STATUS_WORD • Sets the VIN Overvoltage Fault bit in the STATUS_INPUT command, and • Notifies the host by asserting ALERT pin, unless masked This command has one data byte. Fault Responses Output Voltage COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAULT VALUE VOUT_OV_FAULT_RESPONSE 0x41 Action to be taken by the device when an output overvoltage fault is detected. R/W Byte Y Reg Y 0xB8 VOUT_UV_FAULT_RESPONSE 0x45 Action to be taken by the device when an output undervoltage fault is detected. R/W Byte Y Reg Y 0xB8 TON_MAX_FAULT_ RESPONSE 0x63 Action to be taken by the device when a TON_MAX_FAULT event is detected. R/W Byte Y Reg Y 0xB8 VOUT_OV_FAULT_RESPONSE The VOUT_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an output overvoltage fault. The data byte is in the format given in Table 13. The device also: • Sets the VOUT_OV bit in the STATUS_BYTE • Sets the VOUT bit in the STATUS_WORD • Sets the VOUT Overvoltage Fault bit in the STATUS_VOUT command • Notifies the host by asserting ALERT pin, unless masked The only values recognized for this command are: 0x00–Part performs OV pull down only, or OV_PULLDOWN. 0x80–The device shuts down (disables the output) and the unit does not attempt to retry. (PMBus, Part II, Section 10.7). Rev. 0 For more information www.analog.com 109 LTM4664A PMBus COMMAND DETAILS 0xB8–The device shuts down (disables the output) and device attempts to retry continuously, without limitation, until it is commanded OFF (by the RUN pin or OPERATION command or both), bias power is removed, or another fault condition causes the unit to shut down. 0x4n The device shuts down and the unit does not attempt to retry. The output remains disabled until the part is commanded OFF then ON or the RUN pin is asserted low then high or RESET through the command or removal of VIN. The OV fault must remain active for a period of n • 10µs, where n is a value from 0 to 7. 0x78+n The device shuts down and the unit attempts to retry continuously until either the fault condition is cleared or the part is commanded OFF then ON or the RUN pin is asserted low then high or RESET through the command or removal of VIN. The OV fault must remain active for a period of n • 10µs, where n is a value from 0 to 7. Any other value will result in a CML fault and the write will be ignored. This command has one data byte. Table 14. VOUT_OV_FAULT_RESPONSE Data Byte Contents BITS 7:6 DESCRIPTION Response VALUE 00 For all values of bits [7:6], the LTM4664A: • Sets the corresponding fault bit in the status commands and • Notifies the host by asserting ALERT pin, unless masked. 01 The fault bit, once set, is cleared only when one or more of the following events occurs: • The device receives a CLEAR_FAULTS command. • The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin and OPERATION command, to turn off and then to turn back on, or 5:3 • Bias power is removed and reapplied to the LTM4664A. Retry Setting 2:0 Delay Time 10 11 MEANING Part performs OV pull down only or OV_PULLDOWN (i.e., turns off the top MOSFET and turns on lower MOSFET while VOUT is > VOUT_OV_FAULT). The PMBus device continues operation for the delay time specified by bits [2:0] and the delay time unit specified for that particular fault. If the fault condition is still present at the end of the delay time, the unit responds as programmed in the Retry Setting (bits [5:3]). The device shuts down immediately (disables the output) and responds according to the retry setting in bits [5:3]. Not supported. Writing this value will generate a CML fault. 000 The unit does not attempt to restart. The output remains disabled until the fault is cleared until the device is commanded OFF bias power is removed. 111 The PMBus device attempts to restart continuously, without limitation, until it is commanded OFF (by the RUN pin or OPERATION command or both), bias power is removed, or another fault condition causes the unit to shut down without retry. Note: The retry interval is set by the MFR_RETRY_DELAY command. 000-111 The delay time in 10µs increments. This delay time determines how long the controller continues operating after a fault is detected. Only valid for deglitched off state. VOUT_UV_FAULT_RESPONSE The VOUT_UV_FAULT_RESPONSE command instructs the device on what action to take in response to an output undervoltage fault. The data byte is in the format given in Table 8. The device also: • Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE • Sets the VOUT bit in the STATUS_WORD • Sets the VOUT undervoltage fault bit in the STATUS_VOUT command • Notifies the host by asserting ALERT pin, unless masked 110 Rev. 0 For more information www.analog.com LTM4664A PMBus COMMAND DETAILS The UV fault and warn are masked until the following criteria are achieved: 1) The TON_MAX_FAULT_LIMIT has been reached 2) The TON_DELAY sequence has completed 3) The TON_RISE sequence has completed 4) The VOUT_UV_FAULT_LIMIT threshold has been reached 5) The IOUT_OC_FAULT_LIMIT is not present The UV fault and warn are masked whenever the channel is not active. The UV fault and warn are masked during TON_RISE and TOFF_FALL sequencing. This command has one data byte. Table 15. VOUT_UV_FAULT_RESPONSE Data Byte Contents BITS 7:6 DESCRIPTION VALUE Response MEANING 00 The PMBus device continues operation without interruption. (Ignores the fault functionally) 01 The PMBus device continues operation for the delay time specified by bits [2:0] and the delay time unit specified for that particular fault. If the fault condition is still present at the end of the delay time, the unit responds as programmed in the Retry Setting (bits [5:3]). • The device receives a CLEAR_FAULTS command. 10 • The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin and OPERATION command, to turn off and then to turn back on, or The device shuts down (disables the output) and responds according to the retry setting in bits [5:3]. 11 Not supported. Writing this value will generate a CML fault. 000 The unit does not attempt to restart. The output remains disabled until the fault is cleared until the device is commanded OFF bias power is removed. 111 The PMBus device attempts to restart continuously, without limitation, until it is commanded OFF (by the RUN pin or OPERATION command or both), bias power is removed, or another fault condition causes the unit to shut down without retry. Note: The retry interval is set by the MFR_RETRY_DELAY command. For all values of bits [7:6], the LTM4664A: • Sets the corresponding fault bit in the status commands and • Notifies the host by asserting ALERT pin, unless masked. The fault bit, once set, is cleared only when one or more of the following events occurs: • The device receives a RESTORE_USER_ALL command. • The device receives a MFR_RESET command. • The device supply power is cycled. 5:3 2:0 Retry Setting Delay Time 000-111 The delay time in 10µs increments. This delay time determines how long the controller continues operating after a fault is detected. Only valid for deglitched off state. Rev. 0 For more information www.analog.com 111 LTM4664A PMBus COMMAND DETAILS TON_MAX_FAULT_RESPONSE The TON_MAX_FAULT_RESPONSE command instructs the device on what action to take in response to a TON_MAX fault. The data byte is in the format given in Table 13. The device also: • Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE • Sets the VOUT bit in the STATUS_WORD • Sets the TON_MAX_FAULT bit in the STATUS_VOUT command, and • Notifies the host by asserting ALERT pin, unless masked A value of 0 disables the TON_MAX_FAULT_RESPONSE. It is not recommended to use 0. Note: The PWM channel remains in discontinues mode until the TON_MAX_FAULT_LIMIT has been exceeded. This command has one data byte. Fault Responses Output Current COMMAND NAME IOUT_OC_FAULT_RESPONSE CMD CODE DESCRIPTION 0x47 Action to be taken by the device when an output overcurrent fault is detected. TYPE PAGED DATA FORMAT R/W Byte Y Reg UNITS NVM DEFAULT VALUE Y 0x00 IOUT_OC_FAULT_RESPONSE The IOUT_OC_FAULT_RESPONSE command instructs the device on what action to take in response to an output overcurrent fault. The data byte is in the format given in Table 9. The device also: • Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE • Sets the IOUT_OC bit in the STATUS_BYTE • Sets the IOUT bit in the STATUS_WORD • Sets the IOUT Overcurrent Fault bit in the STATUS_IOUT command, and • Notifies the host by asserting ALERT pin, unless masked This command has one data byte. 112 Rev. 0 For more information www.analog.com LTM4664A PMBus COMMAND DETAILS Table 16. IOUT_OC_FAULT_RESPONSE Data Byte Contents BITS 7:6 DESCRIPTION VALUE Response 00 The LTM4664A PSM continues to operate indefinitely while maintaining the output current at the value set by IOUT_OC_FAULT_LIMIT without regard to the output voltage (known as constant-current or brick-wall limiting). 01 Not supported. 10 The LTM4664A PSM continues to operate, maintaining the output current at the value set by IOUT_OC_FAULT_LIMIT without regard to the output voltage, for the delay time set by bits [2:0]. If the device is still operating in current limit at the end of the delay time, the device responds as programmed by the Retry Setting in bits [5:3]. 11 The LTM4664A PSM shuts down immediately and responds as programmed by the Retry Setting in bits [5:3]. 000 The unit does not attempt to restart. The output remains disabled until the fault is cleared by cycling the RUN pin or removing bias power. 111 The device attempts to restart continuously, without limitation, until it is commanded OFF (by the RUN pin or OPERATION command or both), bias power is removed, or another fault condition causes the unit to shut down. Note: The retry interval is set by the MFR_RETRY_DELAY command. For all values of bits [7:6], the LTM4664A: • Sets the corresponding fault bit in the status commands and • Notifies the host by asserting ALERT pin, unless masked. The fault bit, once set, is cleared only when one or more of the following events occurs: • The device receives a CLEAR_FAULTS command. • The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin and OPERATION command, to turn off and then to turn back on, or • The device receives a RESTORE_USER_ALL command. MEANING • The device receives a MFR_RESET command. • The device supply power is cycled. 5:3 2:0 Retry Setting Delay Time 000-111 The number of delay time units in 16ms increments. This delay time is used to determine the amount of time a unit is to continue operating after a fault is detected before shutting down. Only valid for deglitched off response. Fault Responses IC Temperature COMMAND NAME MFR_OT_FAULT_RESPONSE CMD CODE DESCRIPTION 0xD6 Action to be taken by the device when an internal overtemperature fault is detected. TYPE PAGED DATA FORMAT R Byte N Reg UNITS NVM DEFAULT VALUE 0xC0 MFR_OT_FAULT_RESPONSE The MFR_OT_FAULT_RESPONSE command byte instructs the device on what action to take in response to an internal overtemperature fault. The data byte is in the format given in Table 12. The LTM4664A also: • Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE • Sets the MFR bit in the STATUS_WORD, and • Sets the Overtemperature Fault bit in the STATUS_MFR_SPECIFIC command • Notifies the host by asserting ALERT pin, unless masked This command has one data byte. Rev. 0 For more information www.analog.com 113 LTM4664A PMBus COMMAND DETAILS Table 17. Data Byte Contents MFR_OT_FAULT_RESPONSE BITS 7:6 DESCRIPTION VALUE MEANING Response 00 Not supported. Writing this value will generate a CML fault. For all values of bits [7:6], the LTM4664A: 01 Not supported. Writing this value will generate a CML fault • Sets the corresponding fault bit in the status commands and 10 The device shuts down immediately (disables the output) and responds according to the retry setting in bits [5:3]. 11 The device’s output is disabled while the fault is present. Operation resumes and the output is enabled when the fault condition no longer exists. 000 The unit does not attempt to restart. The output remains disabled until the fault is cleared. • Notifies the host by asserting ALERT pin, unless masked. The fault bit, once set, is cleared only when one or more of the following events occurs: • The device receives a CLEAR_FAULTS command. • The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin and OPERATION command, to turn off and then to turn back on, or • Bias power is removed and reapplied to the LTM4664A. 5:3 Retry Setting 001-111 Not supported. Writing this value will generate CML fault. 2:0 Delay Time XXX Not supported. Value ignored Fault Responses External Temperature COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAULT VALUE OT_FAULT_ RESPONSE 0x50 Action to be taken by the device when an external overtemperature fault is detected, R/W Byte Y Reg Y 0xB8 UT_FAULT_ RESPONSE 0x54 Action to be taken by the device when an external undertemperature fault is detected. R/W Byte Y Reg Y 0xB8 OT_FAULT_RESPONSE The OT_FAULT_RESPONSE command instructs the device on what action to take in response to an external overtemperature fault on the external temp sensors. The data byte is in the format given in Table 8. The device also: • Sets the TEMPERATURE bit in the STATUS_BYTE • Sets the Overtemperature Fault bit in the STATUS_TEMPERATURE command, and • Notifies the host by asserting ALERT pin, unless masked This command has one data byte. UT_FAULT_RESPONSE The UT_FAULT_RESPONSE command instructs the device on what action to take in response to an external undertemperature fault on the external temp sensors. The data byte is in the format given in Table 13. The device also: • Sets the TEMPERATURE bit in the STATUS_BYTE • Sets the Undertemperature Fault bit in the STATUS_TEMPERATURE command, and • Notifies the host by asserting ALERT pin, unless masked 114 Rev. 0 For more information www.analog.com LTM4664A PMBus COMMAND DETAILS This condition is detected by the ADC so the response time may be up to tCONVERT. This command has one data byte. Table 18. Data Byte Contents: TON_MAX_FAULT_RESPONSE, VIN_OV_FAULT_RESPONSE, OT_FAULT_RESPONSE, UT_FAULT_RESPONSE BITS 7:6 DESCRIPTION VALUE MEANING Response 00 The PMBus device continues operation without interruption. For all values of bits [7:6], the LTM4664A: 01 Not supported. Writing this value will generate a CML fault. • Sets the corresponding fault bit in the status commands, and 10 The device shuts down immediately (disables the output) and responds according to the retry setting in bits [5:3]. 11 Not supported. Writing this value will generate a CML fault. 000 The unit does not attempt to restart. The output remains disabled until the fault is cleared until the device is commanded OFF bias power is removed. 111 The PMBus device attempts to restart continuously, without limitation, until it is commanded OFF (by the RUN pin or OPERATION command or both), bias power is removed, or another fault condition causes the unit to shut down without retry. Note: The retry interval is set by the MFR_RETRY_DELAY command. XXX Not supported. Values ignored • Notifies the host by asserting ALERT pin, unless masked. The fault bit, once set, is cleared only when one or more of the following events occurs: • The device receives a CLEAR_FAULTS command. • The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin and OPERATION command, to turn off and then to turn back on, or • The device receives a RESTORE_USER_ALL command. • The device receives a MFR_RESET command. • The device supply power is cycled. 5:3 2:0 Retry Setting Delay Time FAULT SHARING Fault Sharing Propagation COMMAND NAME MFR_FAULT_ PROPAGATE CMD CODE 0xD2 DESCRIPTION Configuration that determines which faults are propagated to the FAULT pins. TYPE PAGED DATA FORMAT R/W Word Y Reg UNITS NVM DEFAULT VALUE Y 0x6993 MFR_FAULT_PROPAGATE The MFR_FAULT_PROPAGATE command enables the faults that can cause the FAULTn pin to assert low. The command is formatted as shown in Table 15. Faults can only be propagated to the FAULTn pin if they are programmed to respond to faults. This command has two data bytes. Rev. 0 For more information www.analog.com 115 LTM4664A PMBus COMMAND DETAILS Table 19. FAULTn Propagate Fault Configuration The FAULT0 and FAULT1 pins are designed to provide electrical notification of selected events to the user. Some of these events are common to both output channels. Others are specific to an output channel. They can also be used to share faults between channels. BIT(S) B[15] SYMBOL VOUT disabled while not decayed. B[14] Mfr_fault_propagate_short_CMD_cycle OPERATION This is used in a PolyPhase configuration when bit 0 of the MFR_CHAN_CONFIG is a zero. If the channel is turned off, by toggling the RUN pin or commanding the part OFF, and then the RUN is reasserted or the part is commanded back on before the output has decayed, VOUT will not restart until the 12.5% decay is honored. The FAULT pin is asserted during this condition if bit 15 is asserted. 0: No action Mfr_fault_propagate_ton_max_fault 1: Asserts low if commanded off then on before the output has sequenced off. Re-asserts high tOFF(MIN) after sequence off. 0: No action if a TON_MAX_FAULT fault is asserted b[13] 1: Associated output will be asserted low if a TON_MAX_FAULT fault is asserted FAULT0 is associated with page 0 TON_MAX_FAULT faults FAULT1 is associated with page 1 TON_MAX_FAULT faults b[12] b[11] Reserved Mfr_fault0_propagate_int_ot, b[10] b[9] b[8] Mfr_fault1_propagate_int_ot Reserved Reserved Mfr_fault0_propagate_ut, 0: No action if the UT_FAULT_LIMIT fault is asserted Mfr_fault1_propagate_ut 1: Associated output will be asserted low if the UT_FAULT_LIMIT fault is asserted 0: No action if the MFR_OT_FAULT_LIMIT fault is asserted 1: Associated output will be asserted low if the MFR_OT_FAULT_LIMIT fault is asserted FAULT0 is associated with page 0 UT faults b[7] Mfr_fault0_propagate_ot, FAULT1 is associated with page 1 UT faults 0: No action if the OT_FAULT_LIMIT fault is asserted Mfr_fault1_propagate_ot 1: Associated output will be asserted low if the OT_FAULT_LIMIT fault is asserted FAULT0 is associated with page 0 OT faults FAULT1 is associated with page 1 OT faults b[6] b[5] b[4] Reserved Reserved Mfr_fault0_propagate_input_ov, b[3] b[2] Mfr_fault1_propagate_input_ov Reserved Mfr_fault0_propagate_iout_oc, 0: No action if the IOUT_OC_FAULT_LIMIT fault is asserted Mfr_fault1_propagate_iout_oc 1: Associated output will be asserted low if the IOUT_OC_FAULT_LIMIT fault is asserted 0: No action if the VIN_OV_FAULT_LIMIT fault is asserted 1: Associated output will be asserted low if the VIN_OV_FAULT_LIMIT fault is asserted FAULT0 is associated with page 0 OC faults b[1] Mfr_fault0_propagate_vout_uv, FAULT1 is associated with page 1 OC faults 0: No action if the VOUT_UV_FAULT_LIMIT fault is asserted Mfr_fault1_propagate_vout_uv 1: Associated output will be asserted low if the VOUT_UV_FAULT_LIMIT fault is asserted FAULT0 is associated with page 0 UV faults b[0] Mfr_fault0_propagate_vout_ov, FAULT1 is associated with page 1 UV faults 0: No action if the VOUT_OV_FAULT_LIMIT fault is asserted Mfr_fault1_propagate_vout_ov 1: Associated output will be asserted low if the VOUT_OV_FAULT_LIMIT fault is asserted FAULT0 is associated with page 0 OV faults FAULT1 is associated with page 1 OV faults 116 Rev. 0 For more information www.analog.com LTM4664A PMBus COMMAND DETAILS Fault Sharing Response COMMAND NAME CMD CODE DESCRIPTION MFR_FAULT_RESPONSE 0xD5 Action to be taken by the device when the FAULT pin is asserted low. TYPE R/W Byte PAGED Y DATA FORMAT Reg UNITS NVM Y DEFAULT VALUE 0xC0 MFR_FAULT_RESPONSE The MFR_FAULT_RESPONSE command instructs the device on what action to take in response to the FAULTn pin being pulled low by an external source. Supported Values: VALUE MEANING 0xC0 FAULT_INHIBIT The LTM4664A will three-state the output in response to the FAULT pin pulled low. 0x00 FAULT_IGNORE The LTM4664A continues operation without interruption. The device also: • Sets the MFR Bit in the STATUS_WORD. • Sets Bit 0 in the STATUS_MFR_SPECIFIC Command to Indicate FAULTn Is Being Pulled Low • Notifies the Host by Asserting ALERT, Unless Masked This command has one data byte. SCRATCHPAD COMMAND NAME USER_DATA_00 USER_DATA_01 USER_DATA_02 USER_DATA_03 USER_DATA_04 CMD CODE DESCRIPTION 0xB0 OEM reserved. Typically used for part serialization. 0xB1 Manufacturer reserved for LTpowerPlay. 0xB2 OEM reserved. Typically used for part serialization. 0xB3 A NVM word available for the user. 0xB4 A NVM word available for the user. TYPE R/W Word PAGED N DATA FORMAT Reg NVM Y DEFAULT VALUE NA R/W Word R/W Word Y N Reg Reg Y Y NA NA R/W Word R/W Word Y N Reg Reg Y Y 0x0000 0x0000 UNITS Rev. 0 For more information www.analog.com 117 LTM4664A PMBus COMMAND DETAILS USER_DATA_00   through USER_DATA_04 These commands are non-volatile memory locations for customer storage. The customer has the option to write any value to the USER_DATA_nn at any time. However, the LTpowerPlay software and contract manufacturers use some of these commands for inventory control. Modifying the reserved USER_DATA_nn commands may lead to undesirable inventory control and incompatibility with these products. These commands have 2 data bytes and are in register format. IDENTIFICATION COMMAND NAME PMBus_REVISION CAPABILITY MFR_ID MFR_MODEL MFR_SPECIAL_ID CMD CODE DESCRIPTION 0x98 PMBus revision supported by this device. Current revision is 1.2. 0x19 Summary of PMBus optional communication protocols supported by this device. 0x99 The manufacturer ID of the LTM4664A in ASCII. 0x9A Manufacturer part number in ASCII. 0xE7 Manufacturer code representing the LTM4664A. TYPE R Byte PAGED N DATA FORMAT Reg R Byte N Reg 0xB0 R String R String R Word N N N ASC ASC Reg LTC LTM4664 0x020X UNITS NVM FS DEFAULT VALUE 0x22 PMBus_REVISION The PMBUS_REVISION command indicates the revision of the PMBus to which the device is compliant. The LTM4664A is PMBus Version 1.2 compliant in both Part I and Part II. This read-only command has one data byte. CAPABILITY This command provides a way for a host system to determine some key capabilities of a PMBus device. The LTM4664A supports packet error checking, 400kHz bus speeds, and ALERT pin. This read-only command has one data byte. MFR_ID The MFR_ID command indicates the manufacturer ID of the LTM4664A using ASCII characters. This read-only command is in block format. MFR_MODEL The MFR_MODEL command indicates the manufacturer’s part number of the LTM4664A using ASCII characters. This read-only command is in block format. MFR_SPECIAL_ID The 16-bit word representing the part name and revision. 0x4C denotes the part is an LTM4664A, XX is adjustable by the manufacturer. This read-only command has two data bytes. 118 Rev. 0 For more information www.analog.com LTM4664A PMBus COMMAND DETAILS FAULT WARNING AND STATUS COMMAND NAME CLEAR_FAULTS SMBALERT_MASK CMD CODE DESCRIPTION 0x03 Clear any fault bits that have been set. 0x1B Mask activity. MFR_CLEAR_PEAKS STATUS_BYTE 0xE3 0x78 STATUS_WORD 0x79 STATUS_VOUT 0x7A STATUS_IOUT 0x7B STATUS_INPUT STATUS_ TEMPERATURE 0x7C 0x7D STATUS_CML 0x7E STATUS_MFR_ SPECIFIC 0x80 MFR_PADS MFR_COMMON 0xE5 0xEF TYPE Send Byte Block R/W Clears all peak values. Send Byte One byte summary of the unit’s fault R/W Byte condition. Two byte summary of the unit’s fault R/W Word condition. Output voltage fault and warning R/W Byte status. Output current fault and warning R/W Byte status. Input supply fault and warning status. R/W Byte External temperature fault and warning R/W Byte status for READ_TEMERATURE_1. Communication and memory fault and R/W Byte warning status. Manufacturer specific fault and state R/W Byte information. Digital status of the I/O pads. R Word Manufacturer status bits that are R Byte common across multiple LTC chips. Y Y Reg DEFAULT VALUE NA See CMD Details NA NA Y Reg NA Y Reg NA Y Reg NA N Y Reg Reg NA NA N Reg NA Y Reg NA N N Reg Reg NA NA PAGED N Y FORMAT Reg UNITS NVM Y CLEAR_FAULTS The CLEAR_FAULTS command is used to clear any fault bits that have been set. This command clears all bits in all status commands simultaneously. At the same time, the device negates (clears, releases) its ALERT pin signal output if the device is asserting the ALERT pin signal. If the fault is still present when the bit is cleared, the fault bit will remain set and the host notified by asserting the ALERT pin low. CLEAR_FAULTS can take up to 10µs to process. If a fault occurs within that time frame it may be cleared before the status register is set. This write-only command has no data bytes. The CLEAR_FAULTS does not cause a unit that has latched off for a fault condition to restart. Units that have shut down for a fault condition are restarted when: • The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin and OPERATION command, to turn off and then to turn back on, or • MFR_RESET command is issued. • Bias power is removed and reapplied to the integrated circuit SMBALERT_MASK The SMBALERT_MASK command can be used to prevent a particular status bit or bits from asserting ALERT as they are asserted. Figure 33 shows an example of the Write Word format used to set an ALERT mask, in this case without PEC. The bits in the mask byte align with bits in the specified status register. For example, if the STATUS_TEMPERATURE command code is sent in the first data byte, and the mask byte contains 0x40, then a subsequent External Overtemperature Warning Rev. 0 For more information www.analog.com 119 LTM4664A PMBus COMMAND DETAILS would still set bit 6 of STATUS_TEMPERATURE but not assert ALERT. All other supported STATUS_TEMPERATURE bits would continue to assert ALERT if set. Figure 50 shows an example of the Block Write – Block Read Process Call protocol used to read back the present state of any supported status register, again without PEC. SMBALERT_MASK cannot be applied to STATUS_BYTE, STATUS_WORD, MFR_COMMON or MFR_PADS. Factory default masking for applicable status registers is shown below. Providing an unsupported command code to SMBALERT_ MASK will generate a CML for Invalid/Unsupported Data. SMBALERT_MASK Default Setting: (Refer Also to Figure 2) STATUS RESISTER ALERT Mask Value MASKED BITS STATUS_VOUT STATUS_IOUT STATUS_TEMPERATURE STATUS_CML STATUS_INPUT STATUS_MFR_SPECIFIC 0x00 0x00 0x00 0x00 0x00 0x11 None None None None None Bit 4 (internal PLL unlocked), bit 0 (FAULT pulled low by external device) 1 7 S SLAVE ADDRESS 1 1 W A SMBALERT_MASK A COMMAND CODE 8 1 8 8 1 1 MASK BYTE A P 1 STATUS_x A COMMAND CODE 4664A F56 Figure 53. Example of Writing SMBALERT_MASK 1 7 S SLAVE ADDRESS 1 1 W A SMBALERT_MASK A COMMAND CODE 1 7 Sr SLAVE ADDRESS 8 1 R 1 8 1 BLOCK COUNT (= 1) A 8 1 STATUS_x A COMMAND CODE 1 8 1 8 A BLOCK COUNT (= 1) A MASK BYTE 1 … 1 NA P 4664A F57 Figure 54. Example of Reading SMBALERT_MASK MFR_CLEAR_PEAKS The MFR_CLEAR_PEAKS command clears the MFR_*_PEAK data values. A MFR_RESET command will also clear the MFR_*_PEAK data values. This write-only command has no data bytes. STATUS_BYTE The STATUS_BYTE command returns one byte of information with a summary of the most critical faults. This is the lower byte of the status word. 120 Rev. 0 For more information www.analog.com LTM4664A PMBus COMMAND DETAILS STATUS_BYTE Message Contents: BIT 7* 6 STATUS BIT NAME BUSY OFF 5 4 3 2 1 0* VOUT_OV IOUT_OC VIN_UV TEMPERATURE CML NONE OF THE ABOVE MEANING A fault was declared because the LTM4664A was unable to respond. This bit is set if the channel is not providing power to its output, regardless of the reason, including simply not being enabled. An output overvoltage fault has occurred. An output overcurrent fault has occurred. Not supported (LTM4664A returns 0). A temperature fault or warning has occurred. A communications, memory or logic fault has occurred. A fault Not listed in bits[7:1] has occurred. *ALERT can be asserted if either of these bits is set. They may be cleared by writing a 1 to their bit position in the STATUS_BYTE, in lieu of a CLEAR_ FAULTS command. This command has one data byte. STATUS_WORD The STATUS_WORD command returns a two-byte summary of the channel's fault condition. The low byte of the STATUS_WORD is the same as the STATUS_BYTE command. STATUS_WORD High Byte Message Contents: BIT STATUS BIT NAME MEANING 15 VOUT An output voltage fault or warning has occurred. 14 IOUT An output current fault or warning has occurred. 13 INPUT An input voltage fault or warning has occurred. 12 MFR_SPECIFIC A fault or warning specific to the LTM4664A has occurred. 11 POWER_GOOD# The POWER_GOOD state is false if this bit is set. 10 FANS Not supported (LTM4664A returns 0). 9 OTHER Not supported (LTM4664A returns 0). 8 UNKNOWN Not supported (LTM4664A returns 0). If any of the bits in the upper byte are set, NONE_OF_THE_ABOVE is asserted. This command has two data bytes. STATUS_VOUT The STATUS_VOUT command returns one byte of VOUT status information. STATUS_VOUT Message Contents: BIT 7 6 5 4 3 2 1 0 MEANING VOUT overvoltage fault. VOUT overvoltage warning. VOUT undervoltage warning. VOUT undervoltage fault. VOUT max warning. TON max fault. TOFF max fault. Not supported (LTM4664A returns 0). Rev. 0 For more information www.analog.com 121 LTM4664A PMBus COMMAND DETAILS The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear status by means other than using the CLEAR_FAULTS command. Any supported fault bit in this command will initiate an ALERT event. This command has one data byte. STATUS_IOUT The STATUS_IOUT command returns one byte of IOUT status information. STATUS_IOUT Message Contents: BIT MEANING 7 IOUT overcurrent fault. 6 Not supported (LTM4664A returns 0). 5 IOUT overcurrent warning. 4:0 Not supported (LTM4664A returns 0). The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear status by means other than using the CLEAR_FAULTS command. Any supported fault bit in this command will initiate an ALERT event. This command has one data byte. STATUS_INPUT The STATUS_INPUT command returns one byte of VIN (VINS3_C1) status information. STATUS_INPUT Message Contents: BIT 7 6 5 4 3 2 1 0 MEANING VIN overvoltage fault. Not supported (LTM4664A returns 0). VIN undervoltage warning. Not supported (LTM4664A returns 0). Unit off for insufficient VIN. Not supported (LTM4664A returns 0). IIN overcurrent warning. Not supported (LTM4664A returns 0). The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear status by means other than using the CLEAR_FAULTS command. Any supported fault bit in this command will initiate an ALERT event. Bit 3 of this command is not latched and will not generate an ALERT even if it is set. This command has one data byte. 122 Rev. 0 For more information www.analog.com LTM4664A PMBus COMMAND DETAILS STATUS_TEMPERATURE The STATUS_TEMPERATURE commands returns one byte with status information on temperature. This is a paged command and is related to the respective READ_TEMPERATURE_1 value. STATUS_TEMPERATURE Message Contents: BIT MEANING 7 External overtemperature fault. 6 External overtemperature warning. 5 Not supported (LTM4664A returns 0). 4 External undertemperature fault. 3:0 Not supported (LTM4664A returns 0). . The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear status by means other than using the CLEAR_FAULTS command. This command has one data byte. STATUS_CML The STATUS_CML command returns one byte of status information on received commands, internal memory and logic. STATUS_CML Message Contents: BIT MEANING 7 Invalid or unsupported command received. 6 Invalid or unsupported data received. 5 Packet error check failed. 4 Memory fault detected. 3 Processor fault detected. 2 Reserved (LTM4664A returns 0). 1 Other communication fault. 0 Other memory or logic fault. If either bit 3 or bit 4 of this command is set, a serious and significant internal error has been detected. Continued operation of the part is not recommended if these bits are continuously set. The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear status by means other than using the CLEAR_FAULTS command. Any supported fault bit in this command will initiate an ALERT event. This command has one data byte. Rev. 0 For more information www.analog.com 123 LTM4664A PMBus COMMAND DETAILS STATUS_MFR_SPECIFIC The STATUS_MFR_SPECIFIC commands returns one byte with the manufacturer specific status information. The format for this byte is: BIT MEANING 7 Internal Temperature Fault Limit Exceeded. 6 Internal Temperature Warn Limit Exceeded. 5 Factory Trim Area NVM CRC Fault. 4 PLL is Unlocked 3 Fault Log Present 2 VDD33 UV or OV Fault 1 Short-cycle Event Detected 0 FAULT Pin Asserted Low by External Device If any of these bits are set, the MFR bit in the STATUS_WORD will be set, and ALERT may be asserted. The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear status by means other than using the CLEAR_FAULTS command. However, the fault log present bit can only be cleared by issuing the MFR_FAULT_LOG_CLEAR command. Any supported fault bit in this command will initiate an ALERT event. This command has one data byte. MFR_PADS This command provides the user a means of directly reading the digital status of the I/O pins of the device. The bit assignments of this command are as follows: BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ASSIGNED DIGITAL PIN VDD33 OV Fault VDD33 UV Fault Reserved Reserved ADC Values Invalid, Occurs During Start-Up. May Occur Briefly on Current Measurement Channels During Normal Operation SYNC clocked by external device (when LTM4664A configured to drive SYNC pin) Channel 1 Power Good Channel 0 Power Good LTM4664A Driving RUN1 Low LTM4664A Driving RUN0 Low RUN1 Pin State RUN0 Pin State LTM4664A Driving FAULT1 Low LTM4664A Driving FAULT0 Low FAULT1 Pin State FAULT0 Pin State A 1 indicates the condition is true. This read-only command has two data bytes. 124 Rev. 0 For more information www.analog.com LTM4664A PMBus COMMAND DETAILS MFR_COMMON The MFR_COMMON command contains bits that are common to all LTC digital power and telemetry products. BIT MEANING 7 Chip Not Driving ALERT Low 6 LTM4664A Not Busy 5 Calculations Not Pending 4 LTM4664A Outputs Not in Transition 3 NVM Initialized 2 Reserved 1 SHARE_CLK Timeout 0 WP Pin Status This read-only command has one data byte. MFR_INFO The MFR_INFO command contains additional status bits that are LTC3884-specific and may be common to multiple ADI PSM products. MFR_INFO Data Contents: BIT 15:5 4 MEANING Reserved. EEPROM ECC status. 0: Corrections made in the EEPROM user space. 1: No corrections made in the EEPROM user space. 3:0 Reserved EEPROM ECC status is updated after each RESTORE_USER_ALL or RESET command, a power-on reset or an EEPROM bulk read operation. This read-only command has two data bytes. Rev. 0 For more information www.analog.com 125 LTM4664A PMBus COMMAND DETAILS TELEMETRY COMMAND NAME READ_VIN READ_IIN READ_VOUT READ_IOUT READ_TEMPERATURE_1 CMD CODE 0x88 0x89 0x8B 0x8C 0x8D READ_TEMPERATURE_2 0x8E READ_FREQUENCY READ_POUT READ_PIN MFR_PIN_ACCURACY MFR_IOUT_PEAK 0x95 0x96 0x97 0xAC 0xD7 MFR_VOUT_PEAK 0xDD MFR_VIN_PEAK 0xDE MFR_TEMPERATURE_1_PEAK 0xDF MFR_READ_IIN_PEAK 0xE1 MFR_READ_ICHIP MFR_TEMPERATURE_2_PEAK 0xE4 0xF4 MFR_ADC_CONTROL 0xD8 126 DESCRIPTION TYPE PAGED FORMAT UNITS Measured input supply voltage. R Word N L11 V Measured input supply current. R Word N L11 A Measured output voltage. R Word Y L16 V Measured output current. R Word Y L11 A Power stage diode junction temperature. This R Word Y L11 C is the value used for all temperature related processing, including MFR_IOUT_CAL_GAIN. Power stage junction temperature. Does not R Word N L11 C affect any other commands. Measured PWM switching frequency. R Word Y L11 Hz Calculated output power. R Word Y L11 W Calculated input power. R Word N L11 W Returns the accuracy of the READ_PIN command R Byte N % Report the maximum measured value of R Word Y L11 A READ_IOUT since last MFR_CLEAR_PEAKS. Maximum measured value of READ_VOUT R Word Y L16 V since last MFR_CLEAR_PEAKS. Maximum measured value of READ_VIN since R Word N L11 V last MFR_CLEAR_PEAKS. Maximum measured value of external R Word Y L11 C Temperature (READ_TEMPERATURE_1) since last MFR_CLEAR_PEAKS. Maximum measured value of READ_IIN R Word N L11 A command since last MFR_CLEAR_PEAKS. Measured current used by the LTM4664A. R Word N L11 A R Word N L11 C Peak internal die temperature since last MFR_CLEAR_PEAKS. ADC telemetry parameter selected for repeated R/W Byte N N Reg fast ADC read back. NVM DEFAULT VALUE NA NA NA NA NA NA NA NA NA 5.0% NA NA NA NA NA NA NA NA Rev. 0 For more information www.analog.com LTM4664A PMBus COMMAND DETAILS READ_VIN The READ_VIN command returns the measured VIN pin voltage, in volts added to READ_ICHIP • MFR_RVIN. This compensates for the IR voltage drop across the VIN filter element due to the supply current of the LTM4664A. This read-only command has two data bytes and is formatted in Linear_5s_11s format. READ_VOUT The READ_VOUT command returns the measured output voltage by the VOUT_MODE command. This read-only command has two data bytes and is formatted in Linear_16u format. READ_IIN The READ_IIN command returns the input current, in Amperes, as measured across the input current sense resistor (see also MFR_IIN_CAL_GAIN). This read-only command has two data bytes and is formatted in Linear_5s_11s format. READ_IOUT The READ_IOUT command returns the average output current in amperes. The IOUT value is a function of: a) the differential voltage measured across the ISENSE pins b) the MFR_IOUT_CAL_GAIN value c) the MFR_IOUT_CAL_GAIN_TC value, and d) READ_TEMPERATURE_1 value e) The MFR_TEMP_1_GAIN and the MFR_TEMP_1_OFFSET This read-only command has two data bytes and is formatted in Linear_5s_11s format. READ_TEMPERATURE_1 The READ_TEMPERATURE_1 command returns the temperature, in degrees Celsius, of the power stage sense element. This read-only command has two data bytes and is formatted in Linear_5s_11s format. READ_TEMPERATURE_2 The READ_TEMPERATURE_2 command returns the LTM4664A’s die temperature, in degrees Celsius, of the internal sense element. This read-only command has two data bytes and is formatted in Linear_5s_11s format. READ_FREQUENCY The READ_FREQUENCY command is a reading of the PWM switching frequency in kHz. This read-only command has 2 data bytes and is formatted in Linear_5s_11s format. READ_POUT The READ_POUT command is a reading of the DC/DC converter output power in Watts. POUT is calculated based on the most recent correlated output voltage and current reading. This read-only command has 2 data bytes and is formatted in Linear_5s_11s format. Rev. 0 For more information www.analog.com 127 LTM4664A PMBus COMMAND DETAILS READ_PIN The READ_PIN command is a reading of the DC/DC converter input power in Watts. PIN is calculated based on the most recent input voltage and current reading. This read-only command has 2 data bytes and is formatted in Linear_5s_11s format. MFR_PIN_ACCURACY The MFR_PIN_ACCURACY command returns the accuracy, in percent, of the value returned by the READ_PIN command. There is one data byte. The value is 0.1% per bit which gives a range of ±0.0% to ±25.5%. This read-only command has one data byte and is formatted as an unsigned integer. MFR_IOUT_PEAK The MFR_IOUT_PEAK command reports the highest current, in amperes, reported by the READ_IOUT measurement. This command is cleared using the MFR_CLEAR_PEAKS command. This read-only command has two data bytes and is formatted in Linear_5s_11s format. MFR_VOUT_PEAK The MFR_VOUT_PEAK command reports the highest voltage, in volts, reported by the READ_VOUT measurement. This command is cleared using the MFR_CLEAR_PEAKS command. This read-only command has two data bytes and is formatted in Linear_16u format. MFR_VIN_PEAK The MFR_VIN_PEAK command reports the highest voltage, in volts, reported by the READ_VIN measurement. This command is cleared using the MFR_CLEAR_PEAKS command. This read-only command has two data bytes and is formatted in Linear_5s_11s format. MFR_TEMPERATURE_1_PEAK The MFR_TEMPERATURE_1_PEAK command reports the highest temperature, in degrees Celsius, reported by the READ_TEMPERATURE_1 measurement. This command is cleared using the MFR_CLEAR_PEAKS command. This read-only command has two data bytes and is formatted in Linear_5s_11s format. MFR_READ_IIN_PEAK The MFR_READ_IIN_PEAK command reports the highest current, in Amperes, reported by the READ_IIN measurement. This command is cleared using the MFR_CLEAR_PEAKS command. This command has two data bytes and is formatted in Linear_5s_11s format. MFR_READ_ICHIP The MFR_READ_ICHIP command returns the measured input current, in Amperes, used by the LTM4664A. This command has two data bytes and is formatted in Linear_5s_11s format. 128 Rev. 0 For more information www.analog.com LTM4664A PMBus COMMAND DETAILS MFR_TEMPERATURE_2_PEAK The MFR_TEMPERATURE_2_PEAK command reports the highest temperature, in degrees Celsius, reported by the READ_TEMPERATURE_2 measurement. This command is cleared using the MFR_CLEAR_PEAKS command. This read-only command has two data bytes and is formatted in Linear_5s_11s format. MFR_ADC_CONTROL The MFR_ADC_CONTROL command determines the ADC read back selection. A default value of 0 in the command runs the standard telemetry loop with all parameters updated in a round robin fashion with a typical latency of tCONVERT. The user can command a non-zero value to monitored a single parameter with an approximate update rate of 8ms. This command has a latency of up to 2 ADC conversions or approximately 16ms (external temperature conversions may have a latency of up to 3 ADC conversion or approximately 24ms). It is recommended the part remain in standard telemetry mode except for special cases where fast ADC updates of a single parameter is required. The part should be commanded to monitor the desired parameter for a limited period of time (less then 1 second) then set the command back to standard round robin mode. If this command is set to any value except standard round robin telemetry (0) all warnings and faults associated with telemetry other than the selected parameter are effectively disabled and voltage servoing is disabled. When round robin is reasserted, all warnings and faults and servo mode are re-enabled. COMMANDED VALUE 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 TELEMETRY COMMAND NAME 0x01 0x00 READ_VIN READ_TEMPERATURE_1 READ_IOUT READ_VOUT READ_TEMPERATURE_1 READ_IOUT READ_VOUT READ_TEMPERATURE_2 READ_IIN MFR_READ_ICHIP DESCRIPTION Reserved Reserved Reserved Channel 1 external temperature Reserved Channel 1 measured output current Channel 1 measured output voltage Channel 0 external temperature Reserved Channel 0 measured output current Channel 0 measured output voltage Internal junction temperature Measured input supply current Measured supply current of the LTM4664A Measured input supply voltage Standard ADC Round Robin Telemetry If a reserved command value is entered, the telemetry will default to Internal IC Temperature and issue a CML fault. CML faults will continue to be issued by the LTM4664A until a valid command value is entered. The accuracy of the measured input supply voltage is only guaranteed if the MFR_ADC_CONTROL command is set to standard round robin telemetry. This write-only command has 1 data byte and is formatted in register format. Rev. 0 For more information www.analog.com 129 LTM4664A PMBus COMMAND DETAILS NVM MEMORY COMMANDS Store/Restore COMMAND NAME STORE_USER_ALL CMD CODE 0x15 RESTORE_USER_ALL 0x16 MFR_COMPARE_USER_ALL 0xF0 DESCRIPTION TYPE Store user operating memory to Send Byte EEPROM. Restore user operating memory from Send Byte EEPROM. Compares current command contents Send Byte with NVM. PAGED N FORMAT UNITS NVM DEFAULT VALUE NA N NA N NA STORE_USER_ALL The STORE_USER_ALL command instructs the PMBus device to copy the non-volatile user contents of the Operating Memory to the matching locations in the non-volatile User NVM memory. Executing this command if the die temperature exceeds 85°C or is below 0°C is not recommended and the data retention of 10 years cannot be guaranteed. If the die temperature exceeds 130°C, the STORE_USER_ALL command is disabled. The command is re-enabled when the IC temperature drops below 125°C. Communication with the LTM4664A and programming of the NVM can be initiated when EXTVCC or VDD33 is available and VIN is not applied. To enable the part in this state, using global address 0x5B write MFR_EE_UNLOCK to 0x2B followed by 0xC4. The LTM4664A will now communicate normally, and the project file can be updated. To write the updated project file to the NVM issue a STORE_USER_ALL command. When VIN is applied, a MFR_RESET must be issued to allow the PWM to be enabled and valid ADCs to be read. This write-only command has no data bytes. RESTORE_USER_ALL The RESTORE_USER_ALL command instructs the LTM4664A to copy the contents of the non-volatile User memory to the matching locations in the Operating Memory. The values in the Operating Memory are overwritten by the value retrieved from the User commands. The LTM4664A ensures both channels are off, loads the operating memory from the internal EEPROM, clears all faults, reads the resistor configuration pins, and then performs a soft-start of both PWM channels if applicable. STORE_USER_ALL, MFR_COMPARE_USER_ALL and RESTORE_USER_ALL commands are disabled if the die exceeds 130°C and are not re-enabled until the die temperature drops below 125°C. This write-only command has no data bytes. MFR_COMPARE_USER_ALL The MFR_COMPARE_USER_ALL command instructs the PMBus device to compare current command contents with what is stored in non-volatile memory. If the compare operation detects differences, a CML bit 0 fault will be generated. This write-only command has no data bytes. 130 Rev. 0 For more information www.analog.com LTM4664A PMBus COMMAND DETAILS Fault Logging COMMAND NAME MFR_FAULT_LOG MFR_FAULT_LOG_ STORE MFR_FAULT_LOG_CLEAR CMD CODE DESCRIPTION 0xEE Fault log data bytes. 0xEA Command a transfer of the fault log from RAM to EEPROM. 0xEC Initialize the EEPROM block reserved for fault logging. DATA TYPE PAGED FORMAT UNITS R Block N CF Send Byte N Send Byte N NVM Y DEFAULT VALUE NA NA NA MFR_FAULT_LOG The MFR_FAULT_LOG command allows the user to read the contents of the FAULT_LOG after the first fault occurrence since the last MFR_FAULT_LOG_CLEAR command was written. The contents of this command are stored in non-volatile memory, and are cleared by the MFR_FAULT_LOG_CLEAR command. The length and content of this command are listed in Table 15. If the user accesses the MFR_FAULT_LOG command and no fault log is present, the command will return a data length of 0. If a fault log is present, the MFR_FAULT_LOG will return a block of data 147 bytes long. If a fault occurs within the first second of applying power, some of the earlier pages in the fault log may not contain valid data. NOTE: The approximate transfer time for this command is 3.4ms using a 400kHz clock. This read-only command is in block format. MFR_FAULT_LOG_STORE The MFR_FAULT_LOG_STORE command forces the fault log operation to be written to NVM just as if a fault event occurred. This command will set bit 3 of the STATUS_MFR_SPECIFIC fault if bit 7 “Enable Fault Logging” is set in the MFR_CONFIG_ALL command. If the die temperature exceeds 130°C, the MFR_FAULT_LOG_STORE command is disabled until the IC temperature drops below 125°C. This write-only command has no data bytes. Rev. 0 For more information www.analog.com 131 LTM4664A PMBus COMMAND DETAILS Table 20. Fault Logging This table outlines the format of the block data from a read block data of the MFR_FAULT_LOG command. Data Format Definitions DATA Block Length LIN 11 = PMBus = Rev 1.2, Part 2, section 7.1 LIN 16 = PMBus Rev 1.2, Part 2, section 8. Mantissa portion only BYTE = 8 bits interpreted per definition of this command BITS DATA FORMAT BYTE BYTE NUM BLOCK READ COMMAND 147 The MFR_FAULT_LOG command is a fixed length of 147 bytes The block length will be zero if a data log event has not been captured HEADER INFORMATION Fault Log Preface MFR_VOUT_PEAK (PAGE 0) [7:0] [7:0] [15:8] [7:0] [7:0] [7:0] [15:8] [23:16] [31:24] [39:32] [47:40] [15:8] L16 0 1 2 3 4 5 6 7 8 9 10 11 MFR_VOUT_PEAK (PAGE 1) [7:0] [15:8] L16 12 13 MFR_IOUT_PEAK (PAGE 0) [7:0] [15:8] L11 14 15 MFR_IOUT_PEAK (PAGE 1) [7:0] [15:8] L11 16 17 Fault Source MFR_REAL_TIME MFR_VIN_PEAK READ_TEMPERATURE1 (PAGE 0) READ_TEMPERATURE1 (PAGE 1) READ_TEMPERATURE2 132 [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] ASC Reg Reg Reg L11 L11 L11 L11 18 19 20 21 22 23 24 25 26 Returns LTxx beginning at byte 0 if a partial or complete fault log exists. Word xx is a factory identifier that may vary part to part. Refer to Table 16. 48 bit share-clock counter value when fault occurred (200µs resolution). Peak READ_VOUT on Channel 0 since last power-on or CLEAR_PEAKS command. Peak READ_VOUT on Channel 1 since last power-on or CLEAR_PEAKS command. Peak READ_IOUT on Channel 0 since last power-on or CLEAR_PEAKS command. Peak READ_IOUT on Channel 1 since last power-on or CLEAR_PEAKS command. Peak READ_VIN since last power-on or CLEAR_PEAKS command. External temperature sensor 0 during last event. External temperature sensor 1 during last event. LTM4664A die temperature sensor during last event. Rev. 0 For more information www.analog.com LTM4664A PMBus COMMAND DETAILS CYCLICAL DATA EVENT n Event “n” represents one complete cycle of ADC reads through the MUX at time of fault. Example: If the fault occurs when the ADC is processing step 15, it will continue to take readings through step 25 and then store the header and all 6 event pages to EEPROM (Data at Which Fault Occurred; Most Recent Data) READ_VOUT (PAGE 0) READ_VOUT (PAGE 1) READ_IOUT (PAGE 0) READ_IOUT (PAGE 1) READ_VIN READ_IIN STATUS_VOUT (PAGE 0) STATUS_VOUT (PAGE 1) STATUS_WORD (PAGE 0) STATUS_WORD (PAGE 1) [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] STATUS_MFR_SPECIFIC (PAGE 0) STATUS_MFR_SPECIFIC (PAGE 1) EVENT n-1 (data measured before fault was detected) [15:8] READ_VOUT (PAGE 0) [7:0] READ_VOUT (PAGE 1) [15:8] [7:0] READ_IOUT (PAGE 0) [15:8] [7:0] READ_IOUT (PAGE 1) [15:8] [7:0] READ_VIN [15:8] [7:0] READ_IIN [15:8] [7:0] STATUS_VOUT (PAGE 0) STATUS_VOUT (PAGE 1) STATUS_WORD (PAGE 0) [15:8] [7:0] STATUS_WORD (PAGE 1) [15:8] [7:0] STATUS_MFR_SPECIFIC (PAGE 0) STATUS_MFR_SPECIFIC (PAGE 1) LIN 16 LIN 16 LIN 16 LIN 16 LIN 11 LIN 11 LIN 11 LIN 11 LIN 11 LIN 11 LIN 11 LIN 11 BYTE BYTE WORD WORD WORD WORD BYTE BYTE 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 LIN 16 LIN 16 LIN 16 LIN 16 LIN 11 LIN 11 LIN 11 LIN 11 LIN 11 LIN 11 LIN 11 LIN 11 BYTE BYTE WORD WORD WORD WORD BYTE BYTE 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 Rev. 0 For more information www.analog.com 133 LTM4664A PMBus COMMAND DETAILS EVENT n-5 (Oldest Recorded Data) READ_VOUT (PAGE 0) READ_VOUT (PAGE 1) READ_IOUT (PAGE 0) READ_IOUT (PAGE 1) READ_VIN READ_IIN STATUS_VOUT (PAGE 0) STATUS_VOUT (PAGE 1) STATUS_WORD (PAGE 0) STATUS_WORD (PAGE 1) [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] STATUS_MFR_SPECIFIC (PAGE 0) STATUS_MFR_SPECIFIC (PAGE 1) LIN 16 LIN 16 LIN 16 LIN 16 LIN 11 LIN 11 LIN 11 LIN 11 LIN 11 LIN 11 LIN 11 LIN 11 BYTE BYTE WORD WORD WORD WORD BYTE BYTE 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 Table 21. Explanation of Position_Fault Values POSITION_FAULT VALUE SOURCE OF FAULT LOG 0xFF MFR_FAULT_LOG_STORE 0x00 TON_MAX_FAULT 0x01 VOUT_OV_FAULT 0x02 VOUT_UV_FAULT 134 0x03 IOUT_OC_FAULT 0x05 TEMP_OT_FAULT 0x06 TEMP_UT_FAULT 0x07 VIN_OV_FAULT 0x0A MFR_TEMP_2_OT_FAULT Rev. 0 For more information www.analog.com LTM4664A PMBus COMMAND DETAILS MFR_INFO Contact the factory for details. MFR_IOUT_CAL_GAIN Contact the factory for details. MFR_FAULT_LOG_CLEAR The MFR_FAULT_LOG_CLEAR command will erase the fault log file stored values. It will also clear bit 3 in the STATUS_MFR_SPECIFIC command. After a clear is issued, the status can take up to 8ms to clear. This write-only command is send bytes. Block Memory Write/Read COMMAND NAME CMD CODE DESCRIPTION TYPE DATA PAGED FORMAT UNITS NVM DEFAULT VALUE MFR_EE_UNLOCK 0xBD Unlock user EEPROM for access by MFR_EE_ERASE and MFR_EE_DATA commands. R/W Byte N Reg NA MFR_EE_ERASE 0xBE Initialize user EEPROM for bulk programming by MFR_EE_DATA. R/W Byte N Reg NA MFR_EE_DATA 0xBF Data transferred to and from EEPROM using sequential PMBus word reads or writes. Supports bulk programming. R/W Word N Reg NA All the NVM commands are disabled if the die temperature exceeds 130°C. NVM commands are re-enabled when the die temperature drops below 125°C. MFR_EE_xxxx The MFR_EE_xxxx commands facilitate bulk programming of the LTM4664A internal EEPROM. Contact the factory for details. Rev. 0 For more information www.analog.com 135 136 GND VOUTC0 VOUTC0 VOUTC0 VOUTC0 VOUTC0 VOUTC0 VOUTC0 A9 A10 A11 A12 A13 A14 A15 A16 B9 B10 B11 B12 B13 B14 B15 B16 PIN ID B1 B2 B3 B4 B5 B6 B7 B8 GND VOUTC0 VOUTC0 VOUTC0 VOUTC0 GND GND GND FUNCTION GND GND GND VOUTC1 VOUTC1 VOUTC1 VOUTC1 GND C9 C10 C11 C12 C13 C14 C15 C16 PIN ID C1 C2 C3 C4 C5 C6 C7 C8 GND GND GND GND GND VOUT1 VOUT1 VOUT1 FUNCTION VINS2 VINS2 VINS2 GND GND GND GND GND D9 D10 D11 D12 D13 D14 D15 D16 PIN ID D1 D2 D3 D4 D5 D6 D7 D8 GND INTVCCS1 EXTVCCS1 PGOODS1 GND SW2 SW2 SW2 FUNCTION SW3 SW3 SW3 GND VINS2F INSNSS2– INSNSS2+ GND E9 E10 E11 E12 E13 E14 E15 E16 GND UVS1 FAULTS1 FREQS1 GND GND GND GND F9 F10 F11 F12 F13 F14 F15 F16 GND GND RUNS1 TIMERS1 G9 G10 G11 G12 G13 G14 G15 G16 PIN ID FUNCTION PIN ID FUNCTION PIN ID E1 GND F1 GND G1 E2 GND F2 GND G2 E3 GND F3 GND G3 E4 GND F4 GND G4 E5 HYS_PRGMS2 F5 TIMERS2 G5 E6 OVP_SET F6 VOUT2_SET G6 E7 OVP_TRIP F7 EXTVCCS2 G7 E8 GND F8 GND G8 PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID M1 VINS3_C1 N1 GND P1 GND R1 J1 GND K1 GND L1 VINS3 _C1 J2 GND K2 GND L2 VINS3 _C1 M2 VINS3_C1 N2 GND P2 GND R2 J3 GND K3 GND L3 GND M3 GND N3 GND P3 GND R3 J4 GND K4 GND L4 PWM_C1 M4 GND N4 GND P4 GND R4 PHFLT_C1 M5 GND N5 PGOOD_C1 P5 GL_C1 R5 J5 VTRIMC1_CFG K5 VTRIMC0_CFG L5 – + L6 VDD33 M6 COMP_1a N6 VOSNS _C1 P6 VOSNS _C1 R6 J6 VOUTC0_CFG K6 VDD25 J7 VOUTC1_CFG K7 WP L7 SHARE_CLK M7 COMP_1b N7 GND P7 GND R7 J8 ASEL K8 RUN_C1 L8 SDA M8 SYNC N8 SGND_C0_C1 P8 GND R8 J9 RUN_C0 K9 FAULT_C1 L9 SCL M9 SGND_C0_C1 N9 SGND_C0_C1 P9 GND R9 R10 J10 ALERT K10 FAULT_C0 L10 TSNS_C0a M10 TSNS_C1a N10 COMP_0b P10 IN– J11 GND K11 GND L11 GND M11 GND N11 GND P11 COMP_0a R11 M12 VINS3_C0 N12 GND P12 VOSNS–_C0 R12 J12 K12 L12 VINS3 _C0 K13 L13 VINS3 _C0 M13 VINS3_C0 N13 GND P13 GND R13 J13 INSNSS1– + K14 L14 GND M14 GND N14 GND P14 GND R14 J14 INSNSS1 K15 L15 GND M15 PWM_C0 N15 GND P15 GND R15 J15 VINS1 K16 L16 GND M16 PHFLT_C0 N16 GND P16 GL_C0 R16 J16 VINS1 FUNCTION VOUTC1 VOUTC1 VOUTC1 VOUTC1 VOUTC1 VOUTC1 VOUTC1 GND PIN ID A1 A2 A3 A4 A5 A6 A7 A8 Table 22. LTM4664AY Pin Out Array BGA PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY. FUNCTION GND GND GND GND GND GND INTVCC EXTVCC GND IN+ PGOOD_C0 VOSNS+_C0 GND GND GND GND PIN ID FUNCTION T1 TSNS_C1b T2 GND T3 GND T4 SWC1 T5 SWC1 T6 SWC1 T7 SWC1 T8 GND T9 GND T10 SWC0 T11 SWC0 T12 SWC0 T13 SWC0 T14 GND T15 GND T16 TSNS_C0b PIN ID FUNCTION H1 VOUT2 H2 VOUT2 H3 VOUT2 H4 GND H5 PGOODS2 H6 FAULTS2 H7 UVS2 H8 FSWPH_ CFG GND H9 GND GND H10 GND GND H11 GND HYS_PRGMS1 H12 H13 SW1 H14 SW1 H15 SW1 H16 FUNCTION SW4 SW4 SW4 GND FREQS2 RUNS2 INTVCCS2 GND LTM4664A PACKAGE DESCRIPTION Rev. 0 For more information www.analog.com X 15.65 0.500 ±0.025 Ø 240x Y E D 15.60 PACKAGE TOP VIEW 2.500 SUGGESTED PCB LAYOUT TOP VIEW 2.500 aaa Z 1.500 4 0.500 0.0000 0.500 // f f f Z Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license For is granted implication or otherwise under any patent or patent rights of Analog Devices. more by information www.analog.com 7.500 6.500 5.500 4.500 3.500 2.500 1.500 0.500 0.0000 0.500 1.500 2.500 3.500 4.500 5.500 6.500 7.500 DETAIL A SYMBOL A A1 A2 b b1 D E e F G H1 H2 H3 aaa bbb ccc ddd eee fff H2 MOLD CAP ccc Z b1 A2 e 14 b 13 12 11 10 9 G 8 7 6 e 5 4 3 2 DETAIL A 1 F E D C B A NOM 7.72 0.50 1.82 0.60 0.50 16.00 16.00 1.00 15.00 15.00 0.32 1.50 5.40 0.36 1.55 5.52 0.15 0.10 0.20 0.25 0.10 0.35 MAX 8.03 0.55 1.91 0.70 0.53 DIMENSIONS DETAIL B SUBSTRATE THK MOLD CAP HT INDUCTOR HT BALL DIMENSION PAD DIMENSION BALL HT NOTES DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE 4 TRAY PIN 1 BEVEL COMPONENT PIN “A1” 7 ! PACKAGE IN TRAY LOADING ORIENTATION LTMXXXX µModule 3 SEE NOTES PIN 1 7 SEE NOTES BGA 240 0617 REV B PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY 6. SOLDER BALL COMPOSITION CAN BE 96.5% Sn/3.0% Ag/0.5% Cu OR Sn Pb EUTECTIC 5. PRIMARY DATUM -Z- IS SEATING PLANE BALL DESIGNATION PER JESD MS-028 AND JEP95 3 2. ALL DIMENSIONS ARE IN MILLIMETERS NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 PACKAGE BOTTOM VIEW T R P N M L K J H 15 G F b 16 H1 PACKAGE SIDE VIEW A Z SUBSTRATE A1 TOTAL NUMBER OF BALLS: 240 0.28 1.45 5.28 MIN 7.41 0.45 1.73 0.50 0.47 ddd M Z X Y eee M Z DETAIL B Øb (240 PLACES) H3 INDUCTOR // bbb Z (Reference LTC DWG # 05-08-1567 Rev B) Z PIN “A1” CORNER 1.500 BGA Package 240-Lead (16mm × 16mm × 7.72mm) LTM4664A PACKAGE DESCRIPTION aaa Z Rev. 0 137 7.500 6.500 5.500 4.500 3.500 3.500 4.500 5.500 6.500 7.500 LTM4664A TYPICAL APPLICATIONS DESIGN RESOURCES SUBJECT DESCRIPTION Manufacturing: • Quick Start Guide • PCB Design, Assembly and Manufacturing Guidelines • Package and Board Level Reliability µModule Design and Manufacturing Resources Design: • Selector Guides • Demo Boards and Gerber Files • Free Simulation Tools µModule Regulator Products Search 1. Sort table of products by parameters and download the result as a spread sheet. 2. Search using the Quick Power Search parametric table. Digital Power System Management Analog Devices’ family of digital power supply management ICs are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature EEPROM for storing user configurations and fault logging. RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTM4664 54VIN Dual 25A or Single 50A µModule Regulator with PMBus Interface 30V ≤ VIN ≤ 58V, 0.5V ≤ VOUT ≤ 1.5V. 16mm × 16mm × 7.72mm BGA LTM4681 Quad 31.25A to Single 125A µModule Regulator with PMBus Interface Quad 31.25A to Single 125A µModule Regulator with PMBus Interface LTM4700 Dual 50A or Single 100A µModule Regulator with PMBus Interface 4.5V ≤ VIN ≤ 16V, 0.5V ≤ VOUT ≤ 1.8V. 15mm × 22mm × 7.82mm BGA LTM4680 Dual 30A or Single 60A µModule Regulator with PMBus Interface 4.5V ≤ VIN ≤ 16V, 0.5V ≤ VOUT ≤ 3.3V. 16mm × 16mm × 7.72mm BGA LTM4678 Dual 25A or Single 50A µModule Regulator with PMBus Interface 4.5V ≤ VIN ≤ 16V, 0.5V ≤ VOUT ≤ 3.3V. 16mm × 16mm × 5.86mm BGA LTM4686 Ultrathin Package, Dual 10A or Single 20A µModule Regulator with PMBus Interface 4.5V ≤ VIN ≤ 17V, 0.5V ≤ VOUT ≤ 2.75V. 11.9mm × 16mm × 1.82mm LGA LTM4650 Dual 50A or Single 100A µModule Regulator 4.5V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 1.8V. 16mm × 16mm × 5.01mm BGA LTM4650A Dual 50A or Single 100A µModule Regulator with High VOUT Range 4.5V ≤ VIN ≤ 16V, 0.6V ≤ VOUT ≤ 5.5V. 16mm × 16mm × 5.01mm BGA. 16mm × 16mm × 4.41mm LGA. LTC®2977 Octal Digital Power Supply Manager with EEPROM I²C/PMBus Interface, Configuration EEPROM, Fault Logging, 16-Bit ADC with ±0.25% TUE, 3.3V to 15V Operation LTC2974 Quad Digital Power Supply Manager with EEPROM I²C/PMBus Interface, Configuration EEPROM, Fault Logging, Per Channel Voltage, Current and Temperature Measurements 138 Rev. 0 12/21 www.analog.com For more information www.analog.com  ANALOG DEVICES, INC. 2021