LTM4668A
Quad DC/DC µModule Regulator
with Configurable 1.2A Output Array
FEATURES
DESCRIPTION
Quad Output Step-Down µModule Regulator with
1.2A per Output Channel
n Wide Input Voltage Range: 2.7V to 17V
n 0.6V to 5.5V Output Voltage
n 1.2A DC, Parallelable, Output Current Each Channel
n ±1.5% Total Output Voltage Regulation
n 100% Duty Cycle Operation
n Current Mode Control, Fast Transient Response
n External Frequency Synchronization
n Selectable Burst Mode® Operation
n Power Good Indicator
n Over Voltage, Current and Temperature Protection
n 6.25mm x 6.25mm x 2.1mm BGA Package
n Pin Compatible with LTM4668 (0.6V to 1.8V
Output, 1MHz).
The LTM®4668A is a quad DC/DC step-down µModule
(micromodule) regulator with 1.2A DC current per output. Outputs can be paralleled in an array for up to 4.8A
capability. Included in the package are the switching
controllers, power FETs, inductors and support components. Operating over an input voltage range of 2.7V to
17V, the LTM4668A supports an output voltage range of
0.6V to 5.5V. Only bulk input and output capacitors are
needed. The device supports frequency synchronization,
PolyPhase operation, selectable Burst Mode operation,
100% duty cycle and low IQ operation. Its high switching
frequency and a current mode architecture enables a very
fast transient response to line and load changes without
sacrificing stability.
n
APPLICATIONS
Telecom, Networking and Industrial Equipment
Multi-Rail Point of Load Regulation
n FPGAs, DSPs and ASICs Application
n
n
Fault protection features include overvoltage, overcurrent
and overtemperature protection. The power module is
offered in a space saving and thermally enhanced 6.25mm
× 6.25mm × 2.1mm BGA package. The LTM4668A is available with SnPb (BGA) or RoHS compliant terminal finish.
Configurable Output Array
1.2A
1.2A
1.2A
1.2A
All registered trademarks and trademarks are the property of their respective owners.
2.4A
3.6A
1.2A
1.2A
4.8A
1.2A
TYPICAL APPLICATION
5V to 17V Input, Quad 1.5V, 1.8V, 2.5V, 3.3V Output DC/DC µModule Regulator
22µF
×2
25V
VIN
VOUT1
VFB1
PGOOD1
1.5V/1.2A
40.2k
90
LTM4668A
VOUT2
VFB2
PGOOD2
RUN1
RUN2
RUN3
RUN4
VOUT3
VFB3
PGOOD3
2.5V/1.2A
19.1k
47µF
6.3V
3.3V/1.2A
13.3k
95
47µF
6.3V
47µF
6.3V
EFFICIENCY (%)
5V
to 17V
3.3V Output Efficiency (Each Channel)
100
85
80
75
70
65
60
VIN = 5V
VIN = 12V
55
INTVCC
MODE
GND
VOUT4
VFB4
PGOOD4
1.8V/1.2A
30.1k
47µF
6.3V
4668a TA01a
50
0.0
0.2
0.4
0.6
0.8
LOAD CURRENT (A)
1.0
1.2
4668a TA01b
Rev. A
Document Feedback
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1
LTM4668A
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
VIN.............................................................. –0.3V to 17V
VOUT (per Channel)....................................... –0.3V to 6V
RUN (per Channel)...................................... –0.3V to 17V
PGOOD (per Channel)................................... –0.3V to 6V
FB (per Channel).................................... –0.3V to INTVCC
MODE/SYNC.................................–0.3V to INTVCC+0.3V
Operating Junction Temperature (Note 2)... –40 to 125°C
Storage Temperature Range....................... –55 to 125°C
Peak Solder Reflow Body Temperature.................. 260°C
FB2
VOUT2
GND
PGOOD3
FB3
VOUT3
PGOOD2
7
6
GND
RUN3
RUN2
5
VIN
MODE/SYNC
VIN
RUN4
4
INTVCC
3
RUN1
PGOOD1
2
VOUT1
FB1
PGOOD4
VOUT4
FB4
1
A
B
C
D
E
F
G
BGA PACKAGE
49-LEAD (6.25mm × 6.25mm × 2.1mm)
TJMAX = 125°C, θJCtop = 17°C/W, θJCtop = 2.75°C/W,
θJB + θBA = 17°C/W, θJA = 10°C/W
Weight = 0.79g
θ VALUES DETERMINED PER JESD51-12
ORDER INFORMATION
PART MARKING*
PART NUMBER
LTM4668AEY#PBF
LTM4668AIY#PBF
PAD OR BALL FINISH
SAC305 (RoHS)
DEVICE
FINISH CODE
PACKAGE
TYPE
MSL
RATING
e1
BGA
4
LTM4668AY
LTM4668AY
• Device temperature grade is indicated by a label on the shipping container.
• Pad or ball finish code is per IPC/JEDEC J-STD-609.
• BGA Package and Tray Drawings
TEMPERATURE RANGE
(SEE NOTE 2)
–40°C to 125°C
• This product is not recommended for second side reflow.
This product is moisture sensitive. For more information, go
to Recommended BGA PCB Assembly and Manufacturing
Procedures.
Rev. A
2
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LTM4668A
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified internal
operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, per the typical application.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Switching Regulator Section: (Per Channel)
VIN
Input DC Voltage
l
2.7
17
V
VOUT(RANGE)
Output Voltage Range
VIN = 2.7V to 17V (Step-Down Only)
l
0.6
5.5
V
Output Voltage, Total Variation with
Line and Load
CIN = 10µF, COUT = 47µF Ceramic
RFB = 13.3k, MODE = INTVCC/2
VIN = 5V to 17V, IOUT = 0A to 1.2A
l
VOUT(DC)
3.25
3.30
3.35
V
VRUN
RUN Pin On Threshold
VRUN Rising
0.55
0.7
0.9
V
IQ(VIN)
Input Supply Bias Current
VIN = 12V, VOUT = 3.3V, MODE = INTVCC/2 (CCM)
VIN = 12V, VOUT = 3.3V, MODE = INTVCC (Burst)
VIN = 12V, VOUT = 3.3V, MODE = GND (PS)
Shutdown, RUN = 0, VIN = 12V
IS(VIN)
Input Supply Current
VIN = 12V, VOUT = 3.3V, IOUT = 1.2A
IOUT(DC)
Output Continuous Current Range
VIN = 12V, VOUT = 3.3V (Note 4)
ΔVOUT (Line)
VOUT
Line Regulation Accuracy
VOUT = 3.3V, VIN = 5V to 17V, IOUT = 0A
l
ΔVOUT (Load)
VOUT
Load Regulation Accuracy
VOUT = 3.3V, IOUT = 0A to 1.2A
l
VOUT(AC)
Output Ripple Voltage
IOUT = 0A, COUT = 47µF Ceramic
VIN = 12V, VOUT = 3.3V
8
mV
ΔVOUT(START)
Turn-On Overshoot
IOUT = 0A, COUT = 47µF Ceramic,
VIN = 12V, VOUT = 3.3V
30
mV
tSTART
Turn-On Time
COUT = 47µF Ceramic, VIN = 12V, VOUT = 3.3V,
No Load
0.8
ms
ΔVOUTLS
Peak Deviation for Dynamic Load
Load: 0% to 50% to 0% of Full Load
COUT = 47µF Ceramic, VIN = 12V, VOUT = 3.3V
70
mV
tSETTLE
Settling Time for Dynamic Load Step
Load: 0% to 50% to 0% of Full Load
COUT = 47µF Ceramic, VIN = 12V, VOUT = 3.3V
30
µs
IOUTPK
Output Current Limit
VIN = 12V, VOUT = 3.3V
2
A
VFB
Voltage at VFB Pin
IOUT = 0A, VOUT = 3.3V
IFB
Current at VFB Pin
(Note 3)
RFBHI
Resistor Between VOUT and VFB Pins
tON(MIN)
Minimum On-Time
75
0.5
200
1
390
0
l
0.591
60.05
(Note 5)
mA
mA
µA
µA
mA
1.2
A
0.01
0.1
%/V
0.1
0.75
%
0.60
60.40
60
0.609
V
±10
nA
60.75
kΩ
ns
Rev. A
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3
LTM4668A
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified internal
operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, per the typical application.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
VPGOOD
PGOOD Trip Level
VFB With Respect to Set Output
VFB Ramping Negative
VFB Ramping Positive
–11
–7.5
7.5
11
275
UNITS
%
%
RPGOOD
PGOOD Resistance
VINTVCC
Internal VCC Voltage
VIN = 6V to 17V
4.7
5
5.3
Ω
V
UVLO
Undervoltage Lockout
VIN Ramping Up
2.3
2.5
2.7
V
UVLO(HYS)
UVLO Hysteresis
250
mV
fOSC
Oscillator Frequency
2.25
MHz
SYNC
SYNC Capture Range
1500
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTM4668A is tested under pulsed load conditions such
that TJ ≈ TA. The LTM4668AE is guaranteed to meet performance
specifications over the 0°C to 125°C internal operating temperature
range. Specifications over the full –40°C to 125°C internal operating
temperature range are assured by design, characterization and correlation
3000
kHz
with statistical process controls. The LTM4668AI is guaranteed to meet
specifications over the full –40°C to 125°C internal operating temperature
range. Note that the maximum ambient temperature consistent with
these specifications is determined by specific operating conditions in
conjunction with board layout, the rated package thermal resistance and
other environmental factors.
Note 3: 100% tested at wafer level
Note 4: See output current derating curves for different VIN, VOUT and TA.
Note 5: Guaranteed by design.
Rev. A
4
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LTM4668A
TYPICAL PERFORMANCE CHARACTERISTICS
100
Efficiency vs Load Current at 12VIN
100
96
90
92
92
80
88
88
70
84
80
76
72
68
1.8VOUT
2.5VOUT
3.3VOUT
64
60
0
0.1 0.2 0.4 0.5 0.6 0.7 0.8 1.0 1.1 1.2
LOAD CURRENT (A)
EFFICIENCY (%)
96
EFFICIENCY (%)
EFFICIENCY (%)
100
Efficiency vs Load Current at 5VIN
84
80
76
72
1.8VOUT
2.5VOUT
3.3VOUT
5VOUT
68
64
60
0
0.1 0.2 0.4 0.5 0.6 0.7 0.8 1.0 1.1 1.2
LOAD CURRENT (A)
4668a G01
50
40
30
20
CCM
BURST MODE
PULSE-SKIP MODE
10
0
0.001
0.01
0.1
1
LOAD CURRENT (A)
VOUT
50mV/DIV
AC-COUPLED
LOAD STEP
CURRENT
0.2A/DIV
LOAD STEP
CURRENT
0.2A/DIV
4668a G06
50µs/DIV
VIN = 12V, VOUT = 2.5V, fS = 2.25MHz
COUT = 1× 47µF CERAMIC CAPACITOR
CFF = 150pF
0.3A LOAD STEP 10A/µA
4668a G07
5V Output Transient Response
3.3V Output Transient Response
VOUT
50mV/DIV
AC-COUPLED
VOUT
50mV/DIV
AC-COUPLED
LOAD STEP
CURRENT
0.2A/DIV
LOAD STEP
CURRENT
0.2A/DIV
4668a G08
10
4668a G03
2.5V Output Transient Response
VOUT
50mV/DIV
AC-COUPLED
50µs/DIV
VIN = 12V, VOUT = 3.3V, fS = 2.25MHz
COUT = 1× 47µF CERAMIC CAPACITOR
CFF = 150pF
0.3A LOAD STEP 10A/µA
60
4668a G02
1.8V Output Transient Response
50µs/DIV
VIN = 12V, VOUT = 1.8V, fS = 2.25MHz
COUT = 1× 47µF CERAMIC CAPACITOR
CFF = 150pF
0.3A LOAD STEP 10A/µA
CCM, Burst and Pulse Skip Mode
Efficiency VIN = 12V, VOUT = 3.3V
50µs/DIV
VIN = 12V, VOUT = 5V, fS = 2.25MHz
COUT = 1× 47µF CERAMIC CAPACITOR
CFF = 150pF
0.3A LOAD STEP 10A/µA
4668a G09
Rev. A
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5
LTM4668A
TYPICAL PERFORMANCE CHARACTERISTICS
Start-Up Waveform without
Load Current
INPUT
CURRENT
0.2A/DIV
INPUT
CURRENT
0.2A/DIV
RUN
10V/DIV
RUN
10V/DIV
VOUT
2V/DIV
VOUT
2V/DIV
500µs/DIV
VIN = 12V, VOUT = 3.3V, fS = 2.25MHz
COUT = 1× 47µF CERAMIC CAPACITOR
CFF = 150pF
Output Short-Circuit Waveform
without Load Applied
Start-Up Waveform with 1.2A
Load Current
4668a G10
INPUT
CURRENT
0.5A/DIV
VOUT
2V/DIV
500µs/DIV
VIN = 12V, VOUT = 3.3V, fS = 2.25MHz
COUT = 1× 47µF CERAMIC CAPACITOR
CFF = 150pF
Output Short-Circuit Waveform
with 1.2A Load Current Applied
4668a G11
VOUT
5mV/DIV
AC-COUPLED
RUN
10V/DIV
VOUT
2V/DIV
4668a G12
Steady-State Output
Voltage Ripple
Start-Up into Pre-Biased Output
INPUT
CURRENT
0.2A/DIV
INPUT
CURRENT
0.5A/DIV
20µs/DIV
VIN = 12V, VOUT = 3.3V, fS = 2.25MHz
COUT = 1× 47µF CERAMIC CAPACITOR
CFF = 150pF
VOUT
2V/DIV
20µs/DIV
VIN = 12V, VOUT = 3.3V, fS = 2.25MHz
COUT = 1× 47µF CERAMIC CAPACITOR
CFF = 150pF
4668a G13
500µs/DIV
VIN = 12V, VOUT = 3.3V, fS = 2.25MHz,
OUTPUT PREBIASED TO 1.5V
COUT = 1× 47µF CERAMIC CAPACITOR
CFF = 150pF
4668a G14
500ns/DIV
VIN = 12V, VOUT = 3.3V, fS = 2.25MHz
COUT = 1× 47µF CERAMIC CAPACITOR
CFF = 150pF
4668a G15
Rev. A
6
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LTM4668A
PIN FUNCTIONS
VIN (A4, B4, F4, G4): Power Input Pins connect to the
drain of the internal top MOSFET for each switching mode
regulator channel and the internal 5V regulator for the
control circuitry. Apply input voltages between these
pins and GND pins. Recommend placing input decoupling capacitance directly between each of VIN pins and
GND pins.
400mA peak current clamp. Tie MODE/SYNC to GND for
pulse-skipping operation, and tie MODE/SYNC to a voltage between 1V and INTVCC – 1.2V for forced continuous
mode. Furthermore, connecting this pin to an external
clock will synchronize the switch clock to the external
clock and put the part in forced continuous mode. Do
not float this pin.
VOUT1 (A1, B1), VOUT2 (A7, B7), VOUT3 (F7, G7), VOUT4
(F1, G1): Power Output Pins of each switching mode
regulator channel. Apply output load between these pins
and GND pins. Recommend placing output decoupling
capacitance directly between these pins and GND pins.
See the Applications Information section for paralleling
outputs.
INTVCC (C4): Internal 5V Regulator Output. The internal
power drivers and control circuits are powered from this
voltage. Decouple each pin to GND with a minimum of
2.2µF local low ESR ceramic capacitor. INTVCC only starts
up if at least one of the RUN pins is high.
GND (A2–A3, A5–A6, B2–B3, B5–B6, C2, C6, D3–D5,
E2, E6, F2–F3, F5–F6, G2–G3, G5–G6): Power Ground
Pins for both Input and Output Returns. Use large PCB
copper areas to connect all GND together.
PGOOD1 (D2), PGOOD2 (D6), PGOOD3 (D7), PGOOD4
(D1): Output Power Good with Open-Drain Logic of each
switching mode regulator channel. PGOOD is pulled to
ground when the voltage on the FB pin is not within ±7.5%
of the internal 0.6V reference.
MODE/SYNC (E4): Burst Mode Select and External Clock
Synchronization of the switching mode regulator. Tie
MODE/SYNC to INTVCC for Burst Mode operation with a
RUN1 (C3), RUN2 (C5), RUN3 (E5), RUN4 (E3): Run
Control Input of each switching mode regulator channel.
Enable regulator operation by tying the specific RUN pin
above 1V. Tying it below 0.35V shuts down the specific
regulator channel.
FB1 (C1), FB2 (C7), FB3 (E7), FB4 (E1): The Negative
Input of the Error Amplifier for each switching mode regulator channel. Internally, this pin is connected to VOUT of
each channel with a 60.4kΩ precision resistor. Different
output voltages can be programmed with an additional
resistor between FB and GND pins. In PolyPhase® operation, connect FB pins for all slave channels to INTVCC and
connect VOUT for all paralleled channels together. See the
Applications Information section for details.
Rev. A
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7
LTM4668A
BLOCK DIAGRAM
MODE/SYNC
PGOOD1
INTVCC
100k
VIN
2.2µF
0.1µF
1µH
RUN1
10µF
VOUT1
GND
60.4k
47µF
INTVCC
VIN
6V TO 17V
VOUT1
5V
1.2A
FB1
8.25k
PGOOD2
100k
VIN
VIN
0.1µF
1µH
RUN2
VOUT2
GND
60.4k
INTVCC
47µF
VOUT2
2.5V
1.2A
FB2
19.1k
POWER CONTROL
PGOOD3
100k
VIN
VIN
0.1µF
RUN3
1µH
VOUT3
GND
60.4k
INTVCC
47µF
VOUT3
3.3V
1.2A
FB3
13.3k
PGOOD4
100k
VIN
VIN
0.1µF
RUN4
1µH
VOUT4
GND
60.4k
INTVCC
47µF
VOUT4
1.8V
1.2A
FB4
30.1k
4668a BD
Rev. A
8
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LTM4668A
DECOUPLING REQUIREMENTS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Switching Regulator Section: (Per Channel)
CIN
External Input Capacitor Requirement
(VIN = 2.7V to 17V, VOUT = 1.5V)
IOUT = 1.2A
4.7
10
µF
COUT
External Output Capacitor Requirement
(VIN = 2.7V to 17V, VOUT = 1.5V)
IOUT = 1.2A
22
47
µF
OPERATION
The LTM4668A is a quad output standalone non-isolated
switch mode DC/DC power supply. It has built-in four
separate regulator channels and each of them can deliver
1.2A continuous output current with few external input
and output capacitors. Each regulator provides precisely
regulated output voltage programmable via a single external resistor over 2.7V to 17V input voltage range. The
LTM4688A supports output voltages of 0.6V to 5.5V. The
typical application schematic is shown in Figure 14.
Current mode control also provides cycle-by-cycle fast
overcurrent protection. An internal overvoltage and
undervoltage comparator pulls the open-drain PGOOD
output low if the output feedback voltage exits a ±7.5%
window around the regulation point. Furthermore, in an
overvoltage condition, internal top FET is turned off and
bottom FET is turned on and held on until the overvoltage
condition clears.
The LTM4668A uses a constant frequency, peak current
mode architecture and has integrated power MOSFETs,
inductors, and other supporting discrete components.
The typical switching frequency is set to 2.25MHz. For
switching noise-sensitive applications, the µModule can
be externally synchronized to a clock from 1.5MHz to
3MHz. See the Applications Information section.
Pulling the RUN pin below 0.35V forces the controller
into its shutdown state, turning off both power MOSFETs
and most of the internal control circuitry. At light load
currents, pulse-skipping mode or Burst Mode operation
can be enabled to achieve higher efficiency compared to
continuous mode (CCM) by setting MODE/SYNC pin to
GND or INTVCC accordingly. The LTM4668A has internal
800µs soft-start ramp on each output channel.
With current mode control and internal feedback loop
compensation, the LTM4668A module has sufficient stability margins and good transient performance with a wide
range of output capacitors, even with all ceramic output
capacitors.
The pin compatible part LTM4668 is recommended when
operating at a lower output voltage range of 0.6V to 1.8V
and has a typical switching frequency of 1MHz. The differences between LTM4668 and LTM4668A are shown
in Table 1.
Current mode control provides the flexibility of paralleling any of the separate regulator channels with accurate
current sharing. With a built-in clock interleaving between
each two regulator channels, the LTM4668A could easily
employ a 2+2, 3+1 or all 4 channels, parallel operation
which is more than flexible in a multi-rail POL application.
Table 1.
RECOMMENDED VOUT RANGE
SWITCHING FREQUENCY
LTM4668
0.6V to 1.8V
1MHz
LTM4668A
0.6V to 5.5V*
2.25MHz
*There are restrictions in the maximum VIN and VOUT step-down ratio. See
VIN to VOUT Step-Down Ratios section.
Rev. A
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9
LTM4668A
APPLICATIONS INFORMATION
The typical LTM4668A application circuit is shown in
Figure 14. External component selection is primarily determined by the input voltage, the output voltage and the
maximum load current. Refer to Table 8 for specific external capacitor requirements for a particular application.
VIN to VOUT Step-Down Ratios
There are restrictions in the maximum VIN and VOUT stepdown ratio that can be achieved for a given input voltage due to the minimum on-time limits of each regulator
channel. The minimum on-time limit imposes a minimum
duty cycle of the converter which can be calculated as:
DMIN = TON(MIN) • fSW
where TON(MIN) is the minimum on-time, 40ns typical for
LTM4668A.
In the cases where the minimum duty cycle is surpassed,
pulse-skipping mode (MODE/SYNC = GND) or Burst
Mode (MODE/SYNC = INTVCC) has to be implemented
instead of forced-continuous mode operation in order to
allow the LTM4668A to decrease switching frequency and
maintain output voltage in regulation. The pin compatible
module LTM4668 can also be used in high VIN, low VOUT
application to avoid minimum on time violation with its
1MHz default switching frequency.
The LTM4668A is able to run at 100% duty cycle operation. As the duty cycle approaches 100%, the LTM4668A
enters dropout operation. During dropout, the top PMOS
switch is turned on continuously, and all active circuitry
is kept alive.
Note that additional thermal derating may be applied. See
the Thermal Considerations and Output Current Derating
section in this data sheet.
Output Voltage Programming
The PWM controller has an internal 0.6V reference voltage. As shown in the Block Diagram, a 60.4k 0.5% internal
feedback resistor connects each regulator channel VOUT
and FB pin together. Adding a resistor RFB from FB pin to
GND programs the output voltage:
VOUT = 0.6V •
60.4k + RFB
RFB
Table 2. VFB Resistor Table vs Various Output Voltages
VOUT(V)
RFB(k)
0.6
1.0
1.2
1.5
1.8
2.5
3.3
5.0
OPEN
90.9
60.4
40.2
30.1
19.1
13.3
8.25
For parallel operation, a single resistor as determined by
the previous equation is used for RFB and is connected
from a master channel’s FB pin to GND. Tie the FB pins
of the slave channels to INTVCC and tie the VOUT pins and
the RUN pins together for all channels in parallel. See the
Multi-Channel Parallel Operation section.
Input Decoupling Capacitors
The LTM4668A module should be connected to a low
AC-impedance DC source. One piece of 4.7µF input
ceramic capacitor is required to be placed on each side of
the module for RMS ripple current decoupling. Bulk input
capacitor is only needed when the input source impedance is compromised by long inductive leads, traces or
not enough source capacitance. The bulk capacitor can be
an electrolytic aluminum capacitor and polymer capacitor.
Without considering the inductor current ripple, the RMS
current of the input capacitor can be estimated as:
ICIN(RMS) =
IOUT(MAX)
η%
• D • (1− D )
where η% is the estimated efficiency of the power module.
Output Decoupling Capacitors
With an optimized high frequency, high bandwidth design,
only single piece of low ESR output ceramic capacitor is
required for each regulator channel to achieve low output
voltage ripple and very good transient response. Additional
output filtering may be required by the system designer,
if further reduction of output ripples or dynamic transient
spikes is required. Table 8 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 0.3A (25%) load step
transient. Multiphase operation will reduce effective output
ripple as a function of the number of phases. Application
Note 77 discusses this noise reduction versus output ripple current cancellation, but the output capacitance will be
more a function of stability and transient response. The
LTpowerCAD® design tool is available to download online
Rev. A
10
For more information www.analog.com
LTM4668A
APPLICATIONS INFORMATION
for output ripple, stability and transient response analysis
and calculating the output ripple reduction as the number
of phases implemented increases by N times.
Burst Mode Operation
The LTM4668A is capable of Burst Mode operation in
which the power MOSFETs operate intermittently based
on load demand, thus saving quiescent current. For applications where maximizing the efficiency at very light loads
is a high priority, Burst Mode operation should be applied.
To enable Burst Mode operation, simply tie the MODE/
SYNC pin to INTVCC.
During Burst Mode operation, the peak current of the
inductor is set to approximately 400mA in normal operation even though the output of the error amplifier (COMP)
indicates a lower value. The COMP voltage drops when
the inductor’s average current is greater than the load
requirement. As the COMP voltage drops below 0.2V, the
burst comparator trips, causing the internal sleep line to
go high and turn off both power MOSFETs.
In sleep mode, the internal circuitry is partially turned
off, reducing the quiescent current. The load current is
now being supplied from the output capacitors. When the
output voltage drops, causing COMP voltage to rise, the
internal sleep line goes low, and the LTM4668A resumes
normal operation. The next oscillator cycle will turn on
the top power MOSFET and the switching cycle repeats.
When all channels are in sleep mode, the LTM4668A module draws only 8µA of quiescent current from VIN.
Pulse-Skipping Mode Operation
In applications where low output ripple and high efficiency
at intermediate currents are desired, pulse-skipping mode
should be used by grounding the MODE/SYNC pin. In
LTM4668A, pulse-skipping mode is implemented similarly to Burst Mode operation with the peak inductor current set to be at least 66mA. This results in lower ripple
than in Burst Mode operation with the trade-off of slightly
lower efficiency.
Both modes, Burst Mode operation and pulse-skipping
mode, automatically switch from continuous operation to
the selected mode when the load current is low.
Force Continuous Current Mode (CCM)
In applications where fixed frequency operation is more
critical than low current efficiency, and where the lowest output ripple is desired, forced continuous operation should be used. Forced continuous operation can
be enabled by tying the MODE pin to INTVCC/2. In this
mode, inductor current is allowed to reverse during low
output loads, the output of the error amplifier is in control
of the current comparator threshold throughout, and the
top MOSFET always turns on with each oscillator pulse.
During start-up, the module operates in pulse-skipped
mode regardless of the mode programmed on the MODE/
SYNC pin to prevent inductor current from reversing until
the LTM4668A’s output voltage is in regulation.
Operating Frequency
The operating frequency of the LTM4668A is optimized
to achieve the compact package size and the minimum
output ripple voltage while keeping high efficiency. The
default operating frequency is internally set to 2.25MHz.
In most applications, no additional frequency adjusting
is required.
If any operating frequency other than 2.25MHz is required
by application, the µModule can be externally synchronized to a clock from 1.5MHz to 3MHz.
Frequency Synchronization and Clock In
The power module has a phase-locked loop comprised
of an internal voltage controlled oscillator and a phase
detector. This allows all internal top MOSFET turn-on to
be locked to the rising edge of the same external clock.
The external clock frequency range must be within ±50%
around the 2.25MHz set frequency. A pulse detection circuit is used to detect a clock on the MODE/SYNC pin to
turn on the phase-locked loop. The pulse width of the
clock has to be at least 400ns. The clock high level must
be above 2V and clock low level below 0.3V. During the
start-up of the regulator, the phase-locked loop function
is disabled. And once engaged in frequency sync, the
LTM4668A runs in forced continuous mode at the external clock frequency.
Rev. A
For more information www.analog.com
11
LTM4668A
APPLICATIONS INFORMATION
Multi-Channel Parallel Operation
A multiphase power supply significantly reduces the
amount of ripple current in both the input and output
capacitors. The RMS input ripple current is reduced by,
and the effective ripple frequency is multiplied by, the
number of phases used (assuming that the input voltage is greater than the number of phases used times
the output voltage). The output ripple amplitude is also
reduced by the number of phases used when all of the
outputs are tied together to achieve a single high output
current design.
For the application that demands more than 1.5A of output current, the LTM4668A multiple regulator channels
can be easily paralleled to provide more output current
without increasing input and output voltage ripples. The
LTM4668A has preset built-in 180° phase shift between
channel 1, 2 and 3, 4 which is suitable to employ a 2+2,
3+1 or 4 channel parallel operation. Table 3 gives the
phase difference between regulator channels.
Table 3. Phase Difference Between Regulator Channels
CHANNEL
Phase Diff.
CH1
CH2
0°
CH3
The LTM4668A device is an inherently current mode controlled device, so parallel modules will have very good
current sharing. This will balance the thermals on the
design. When configuring the LTM4668A for parallel
operation, channels 1 and 4 serve as master channels
to slave channels 2 and 3, respectively. To configure a
channel as a slave, tie its FB pin to INTVCC to shut down
CH4
180°
0°
Figure 1 shows a 2+2 and a 4-channels parallel concept
schematics for clock phasing.
INTVCC
FB1
RUN1
CH1
(0°)
FB2
RUN2
FB3
CH2
(0°)
0°
VOUT1
INTVCC
RUN3
CH3
(180°)
VOUT2
FB4
0°
VOUT3
RUN4
CH4
(180°)
VOUT4
LTM4668A
2.4A
2.4A
INTVCC
INTVCC
FB1
RUN1
CH1
(0°)
VOUT1
FB2
0°
RUN2
CH2
(0°)
FB3
0°
VOUT2
INTVCC
RUN3
CH3
(0°)
FB4
0°
VOUT3
RUN4
CH4
(0°)
VOUT4
LTM4668A
4668a F01
4.8A
Figure 1. 2+2 and 4-Channel Parallel Concept Schematic
Rev. A
12
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LTM4668A
APPLICATIONS INFORMATION
its control circuitry. The master channel’s drive signal is
used instead to drive the slave channel’s power switches.
Then, to complete configuration, tie its VOUT to the master
channel VOUT and its RUN pin to the master channel’s
RUN pin. Channel 2 and 3 cannot be tied together to provide a dual channel single output. For a three-channel
single-output, or four-channel single-output, channel 1
is used as the master channel. Table 4 lists the recommended channel combinations for multi-channel parallel
operation. In parallel output application, use the master
channel’s PGOOD signal as the power good indicator. Do
not tie PGOOD pins together.
Table 4. Configuration of Multi-Channel Parallel Operation
NUMBER OF OUTPUT
VOLTAGE RAILS
PARALLELING
CHANNEL
MASTER
CHANNEL
PGOOD
INDICATOR
QUAD
1/2/3/4
TRIPLE
(1+2)/3/4
1
PGOOD1
DUAL
(1+2)/(3+4)
1, 4
PGOOD1, 4
DUAL
(1+2+4)/3
1
PGOOD1
SINGLE
(1+2+3+4)
1
PGOOD1
Input RMS Ripple Current Cancellation
Application Note 77 provides a detailed explanation of
multiphase operation. The input RMS ripple current cancellation mathematical derivations are presented, and
a graph is displayed representing the RMS ripple current reduction as a function of the number of interleaved
phases. Figure 2 shows this graph.
Soft-Start and Output Voltage Tracking
The LTM4668A has an internal 800µs soft-start ramp for
each channel. During soft-start operation, the switcher
operates in pulse-skipping mode regardless of the mode
programmed on the MODE/SYNC pin. Once the soft-start
period is complete, the part will transition into the desired
mode of operation.
Power Good
The PGOOD pins are open drain pins that can be used to
monitor valid output voltage regulation. This pin monitors
0.60
1-PHASE
2-PHASE
3-PHASE
4-PHASE
6-PHASE
0.55
0.50
RMS INPUT RIPPLE CURRENT
DC LOAD CURRENT
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0.1 0.15
0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
DUTY CYCLE (VOUT/VIN)
4668a F02
Figure 2. Input RMS Current Ratios to DC Load Current as a Function of Duty Cycle
Rev. A
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13
LTM4668A
APPLICATIONS INFORMATION
a ±7.5% window around the regulation point. A resistor
can be pulled up to a particular supply voltage for monitoring. To prevent unwanted PGOOD glitches during transients or dynamic VOUT changes, the LTM4668A’s PGOOD
falling edge includes a blanking delay of approximately 32
switching cycles.
Stability Compensation
The LTM4668A module internal compensation loop of
each regulator channel is designed and optimized for low
ESR ceramic output capacitors only application. Table 6
is provided for most application requirements. In cases
that require bulk output capacitors for output ripple or
dynamic transient spike reduction, an additional 10pF to
15pF phase boost cap is recommended between VOUT
and FB pins. The LTpowerCAD design tool is available to
download for control loop optimization.
Run Enable
Pulling the RUN pin of each regulator channel to ground
forces the regulator into its shutdown state, turning off
both power MOSFETs and most of its internal control circuitry. Bringing the RUN pin above 1V will turn on the
entire regulator channel.
VIN Overvoltage Protection
The LTM4668A module constantly monitors the VIN
pins for an overvoltage condition. When VIN rises above
19V, the corresponding regulator suspends operation by
shutting off both power MOSFETs. Once VIN drops below
18.7V, the regulator immediately resumes normal operation. The regulators execute soft-start function when exiting an overvoltage condition.
Thermal Considerations and Output Current Derating
The thermal resistances reported in the Pin Configuration
section of the data sheet are consistent with those parameters defined by JESD51-9 and are intended for use with
finite element analysis (FEA) software modeling tools that
leverage the outcome of thermal modeling, simulation
and correlation to hardware evaluation performed on a
µModule package mounted to a hardware test board—
also defined by JESD51-9 (“Test Boards for Area Array
Surface Mount Package Thermal Measurements”). The
motivation for providing these thermal coefficients in
found in JESD51-12 (“Guidelines for Reporting and Using
Electronic Package Thermal Information”).
Many designers may opt to use laboratory equipment and
a test vehicle such as the demo board to anticipate the
µModule regulator’s thermal performance in their application at various electrical and environmental operating
conditions to compliment any FEA activities. Without
FEA software, the thermal resistances reported in the
Pin Configuration section are in-and-of themselves not
relevant to providing guidance of thermal performance;
instead, the derating curves provided in the data sheet can
be used in a manner that yields insight and guidance pertaining to one’s application usage, and can be adapted to
correlate thermal performance to one’s own application.
The Pin Configuration section typically gives four thermal
coefficients explicitly defined in JESD51-12; these coefficients are quoted or paraphrased below:
1. θJA, the thermal resistance from junction to ambient,
is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed
enclosure. This environment is sometimes referred to
as “still air” although natural convection causes the
air to move. This value is determined with the part
mounted to a JESD51-9 defined test board, which
does not reflect an actual application or viable operating condition.
2. θJCbottom, the thermal resistance from junction to
ambient, is the natural convection junction-to-ambient
air thermal resistance measured in a one cubic foot
sealed enclosure. This environment is sometimes
referred to as “still air” although natural convection
causes the air to move. This value is determined with
the part mounted to a JESD51-9 defined test board,
which does not reflect an actual application or viable
operating condition.
3. θJCtop, the thermal resistance from junction to top of
the product case, is determined with nearly all of the
component power dissipation flowing through the top
of the package. As the electrical connections of the
typical µModule are on the bottom of the package, it
Rev. A
14
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LTM4668A
APPLICATIONS INFORMATION
JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-CASE (TOP)
RESISTANCE
JUNCTION
JUNCTION-TO-BOARD RESISTANCE
JUNCTION-TO-CASE
CASE (BOTTOM)-TO-BOARD
(BOTTOM) RESISTANCE
RESISTANCE
AMBIENT
BOARD-TO-AMBIENT
RESISTANCE
4668a F03
µMODULE DEVICE
Figure 3. Graphical Representation of JESD51-12 Thermal Coefficients
is rare for an application to operate such that most of
the heat flows from the junction to the top of the part.
As in the case of θJCbottom, this value may be useful
for comparing packages but the test conditions don’t
generally match the user’s application.
4. θJB, the thermal resistance from junction to the printed
circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the
bottom of the µModule and into the board, and is really
the sum of the θJCbottom and the thermal resistance of
the bottom of the part through the solder joints and
through a portion of the board. The board temperature is measured a specified distance from the package, using a two sided, two layer board. This board is
described in JESD51-9.
A graphical representation of the aforementioned thermal resistances is given in Figure 3; blue resistances are
contained within the μModule regulator, whereas green
resistances are external to the µModule.
As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD51-12 or provided in the
Pin Configuration section replicates or conveys normal
operating conditions of a μModule. For example, in normal board-mounted applications, never does 100% of
the device’s total power loss (heat) thermally conduct
exclusively through the top or exclusively through bottom
of the µModule—as the standard defines for θJCtop and
θJCbottom, respectively. In practice, power loss is thermally dissipated in both directions away from the package—granted, in the absence of a heat sink and airflow,
a majority of the heat flow is into the board.
Within a SIP (system-in-package) module, be aware there
are multiple power devices and components dissipating
power, with a consequence that the thermal resistances
relative to different junctions of components or die are not
exactly linear with respect to total package power loss. To
reconcile this complication without sacrificing modeling
simplicity—but also, not ignoring practical realities—an
approach has been taken using FEA software modeling
along with laboratory testing in a controlled-environment
chamber to reasonably define and correlate the thermal
resistance values supplied in this data sheet: (1) Initially,
FEA software is used to accurately build the mechanical
geometry of the µModule and the specified PCB with all
of the correct material coefficients along with accurate
power loss source definitions; (2) this model simulates
a software-defined JEDEC environment consistent with
JESD51-9 to predict power loss heat flow and temperature
readings at different interfaces that enable the calculation
of the JEDEC-defined thermal resistance values; (3) the
model and FEA software is used to evaluate the µModule
with heat sink and airflow; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled-environment
Rev. A
For more information www.analog.com
15
LTM4668A
APPLICATIONS INFORMATION
chamber while operating the device at the same power
loss as that which was simulated. An outcome of this
process and due-diligence yields a set of derating curves
provided in other sections of this data sheet. After these
laboratory test have been performed and correlated to
the µModule model, then the θJB and θBA are summed
together to correlate quite well with the µModule model
with no airflow or heat sinking in a properly define chamber. This θJB + θBA value is shown in the Pin Configuration
section and should accurately equal the θJA value because
approximately 100% of power loss flows from the junction through the board into ambient with no airflow or top
mounted heat sink.
The 1.8V, 3.3V and 5V power loss curves in Figures 4 to 6
can be used in coordination with the load current derating
curves in Figures 7 to 12 for calculating an approximate
θJA thermal resistance for the LTM4668A with various airflow conditions. The power loss curves are taken at room
temperature, and are increased with multiplicative factors
of 1.3 considering both MOSFET RDS(ON) and inductor
DCR increases at 120°C junction temperature when the
derating starts. The derating curves are plotted with the
output current starting at 4.8A with all 4 channels paralleled together and the ambient temperature at 40°C. The
output voltages are 1.8V, 3.3V and 5V. These are chosen
to include the lower and higher output voltage ranges for
correlating the thermal resistance. Thermal models are
derived from several temperature measurements in a controlled temperature chamber along with thermal modeling
analysis. The junction temperatures are monitored while
ambient temperature is increased with and without airflow. The power loss increase with ambient temperature
change is factored into the derating curves. The junctions
are maintained at 120°C maximum while lowering output
current or power with increasing ambient temperature.
The decreased output current will decrease the internal
module loss as ambient temperature is increased. The
monitored junction temperature of 120°C minus the ambient operating temperature specifies how much module
temperature rise can be allowed.
As an example, in Figure 11 the load current is derated to
~3.75A at ~80°C with no air or heat sink and the power
loss for the 12V to 3.3V at 3.75A output is about 2.6W. The
2.6W loss is calculated with the ~2W room temperature
loss from the 12V to 3.3V power loss curve at 3.75A, and
the 1.3 multiplying factor at 125°C junction. If the 80°C
ambient temperature is subtracted from the 120°C junction temperature, then the difference of 40°C divided by
2.6W equals a 15.3°C/W θJA thermal resistance. Table 5
specifies a 15°C/W value which is very close.
Table 5 to Table 7 provide equivalent thermal resistances
for 1.8V, 3.3V and 5V outputs with and without airflow.
The derived thermal resistances in Table 5 and Table 6
for the various conditions can be multiplied by the calculated power loss as a function of ambient temperature to
derive temperature rise above ambient, thus maximum
junction temperature. Room temperature power loss
can be derived from the efficiency curves in the Typical
Performance Characteristics section and adjusted with
the above ambient temperature multiplicative factors. The
printed circuit board is a 1.6mm thick six layer board with
two ounce copper for the two outer layers and one ounce
copper for the four inner layers. The PCB dimensions are
94mm × 100mm.
Rev. A
16
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LTM4668A
APPLICATIONS INFORMATION
2.5
2.0
1.5
1.0
0.5
0
1.5
1.0
0.5
1
0
2
3
LOAD CURRENT (A)
4
0
5
1.5
1.0
0.5
0
1
3
2
LOAD CURRENT (A)
4
0
5
5.0
4.5
4.5
4.0
4.0
4.0
3.5
3.5
3.5
1.0
0
30
40
3.0
2.5
2.0
1.5
1.0
0LFM
200LFM
400LFM
0.5
LOAD CURRENT (A)
5.0
1.5
0
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
30
40
2.0
1.5
0
Figure 8. 5V to 1.8V Derating
Curve, No Heat Sinking
4.5
4.5
4.0
4.0
4.0
3.5
3.5
3.5
1.0
0
30
40
3.0
2.5
2.0
1.5
1.0
0LFM
200LFM
400LFM
0.5
LOAD CURRENT (A)
4.5
LOAD CURRENT (A)
5.0
1.5
4668a F10
Figure 10. 5V to 3.3V Derating
Curve, No Heat Sinking
0
30
40
2.5
2.0
1.5
0LFM
200LFM
400LFM
0.5
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4668a F11
Figure 11. 12V to 3.3V Derating
Curve, No Heat Sinking
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
3.0
1.0
0LFM
200LFM
400LFM
0.5
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
40
Figure 9. 12V to 1.8V Derating
Curve, No Heat Sinking
5.0
2.0
30
4668a F09
5.0
2.5
0LFM
200LFM
400LFM
4668a F08
Figure 7. 3.3V to 1.8V Derating
Curve, No Heat Sinking
5
2.5
0.5
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4668a F07
4
3.0
1.0
0LFM
200LFM
400LFM
0.5
3.0
3
2
LOAD CURRENT (A)
Figure 6. 5V Output Power Loss
4.5
2.0
1
4668a F06
5.0
2.5
0
Figure 5. 3.3V Output Power Loss
LOAD CURRENT (A)
LOAD CURRENT (A)
2.0
4668a F05
Figure 4. 1.8V Output Power Loss
3.0
VIN = 12V
2.5
2.0
4668a F04
LOAD CURRENT (A)
3.0
VIN = 5V
VIN = 12V
2.5
POWER LOSS (A)
POWER LOSS (W)
3.0
VIN = 3.3V
VIN = 5V
VIN = 12V
POWER LOSS (A)
3.0
0
30
40
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4668a F12
Figure 12. 12V to 5V Derating
Curve, No Heat Sinking
Rev. A
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17
LTM4668A
APPLICATIONS INFORMATION
Table 5. 1.8V Output
DERATING CURVE
VIN (V)
POWER LOSS CURVE
AIR FLOW (LFM)
HEAT SINK
ΘJA (°C/W)
Figures 7, 8, 9
3.3, 5, 12
Figure 4
0
None
15
Figures 7, 8, 9
3.3, 5, 12
Figure 4
200
None
13
Figures 7, 8, 9
3.3, 5, 12
Figure 4
400
None
12
DERATING CURVE
VIN (V)
POWER LOSS CURVE
AIR FLOW (LFM)
HEAT SINK
ΘJA(°C/W)
Figures 10, 11
5, 12
Figure 5
0
None
15
Figures 10, 11
5, 12
Figure 5
200
None
13
Figures 10, 11
5, 12
Figure 5
400
None
12
DERATING CURVE
VIN (V)
POWER LOSS CURVE
AIR FLOW (LFM)
HEAT SINK
ΘJA(°C/W)
Figure 12
12
Figure 6
0
None
15
Figure 12
12
Figure 6
200
None
13
Figure 12
12
Figure 6
400
None
12
Table 6. 3.3V Output
Table 7. 5V Output
Table 8. Output Voltage Response vs Component Matrix (Refer to Figure 14) 0A to 0.3A Load Step Typical Measured Values
CIN CERAMIC VENDORS
VALUE
PART NUMBER
COUT CERAMIC VENDORS
VALUE
PART NUMBER
MURATA
22µF, 25V
GRM21BR61E226ME44L
MURATA
47µF, 6.3V
GRM21BR60J476ME15
TAIYO YUDEN
22µF, 25V
TMK316BBJ226ML-T
TAIYO YUDEN
47µF, 6.3V
JMK212BJ476MG-T
P-P
LOAD STEP
DROOP DERIVATION RECOVERY LOAD
SLEW RATE
(mV)
(mV)
TIME (µs) STEP (A)
(A/µs)
VOUT
(V)
CIN
(CERAMIC)
CIN
(BULK)
COUT1
(CERAMIC)
COUT2
(BULK)
CFF
(pF)
VIN
(V)
1.8
20µF
NA
47µF
NA
150
5, 12
0
56
30
0.3
10
30.1
2.5
20µF
NA
47µF
NA
150
5, 12
0
61
35
0.3
10
19.1
3.3
20µF
NA
47µF
NA
150
5, 12
0
68
40
0.3
10
13.3
5
20µF
NA
47µF
NA
150
12
0
92
50
0.3
10
8.25
1
20µF
NA
47µF
NA
150
5
0
48.2
13
0.3
10
90.9
1.2
20µF
NA
47µF
NA
150
5
0
48.9
15
0.3
10
60.4
1.5
20µF
NA
47µF
NA
150
5
0
51.5
20
0.3
10
40.2
RFB
(kΩ)
Rev. A
18
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LTM4668A
APPLICATIONS INFORMATION
Safety Considerations
The LTM4668A modules do not provide galvanic isolation
from VIN to VOUT. There is no internal fuse. If required,
a slow blow fuse with a rating twice the maximum input
current needs to be provided to protect each unit from
catastrophic failure. The device does support thermal
shutdown and overcurrent protection.
Layout Checklist/Example
The high integration of LTM4668A makes the PCB board
layout very simple and easy. However, to optimize its
electrical and thermal performance, some layout considerations are still necessary.
• Use large PCB copper areas for high current paths,
including VIN, GND, VOUT1 and VOUT2. It helps to minimize the PCB conduction loss and thermal stress.
• Place high frequency ceramic input and output capacitors next to the VIN, PGND and VOUT pins to minimize
high frequency noise.
• Place a dedicated power ground layer underneath
the unit.
• To minimize the via conduction loss and reduce module
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
• Do not put vias directly on the pad, unless they are
capped or plated over.
• Use a separated SGND ground copper area for components connected to signal pins. Connect the SGND
to GND underneath the unit.
• For parallel modules, tie the VOUT, VFB and COMP pins
together. Use an internal layer to closely connect these
pins together. The TRACK pin can be tied a common
capacitor for regulator soft-start.
• Bring out test points on the signal pins for monitoring.
Figure 13 gives a good example of the recommended
layout.
VOUT2
VOUT3
VIN
GND
VOUT1
VIN
GND
VOUT4
4668a F13
Figure 13. Recommended PCB Layout
Rev. A
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19
LTM4668A
TYPICAL APPLICATIONS
PGOOD1 PGOOD2 PGOOD3 PGOOD4
VIN
6V TO 17V
22µF
25V
VIN PGOOD1 PGOOD2 PGOOD3 PGOOD4 VOUT1
VFB1
13.3k
RUN1
RUN2
RUN3
RUN4
VOUT2
VFB2
VOUT1
3.3V/1.2A
47µF
6.3V
25.5k
47µF
6.3V
8.25k
47µF
6.3V
VOUT2
2V/1.2A
LTM4668A
VOUT3
VFB3
INTVCC
MODE/SYNC
VOUT4
VFB4
GND
30.1k
VOUT3
5V/1.2A
VOUT4
1.8V/1.2A
47µF
6.3V
4668a F14
Figure 14. 6V to 17V Input, 3.3V, 2V, 5V, 1.8V Output at 1.2A Design
PGOOD1 PGOOD2 PGOOD3 PGOOD4
VIN
5V TO 17V
22µF
25V
VIN PGOOD1 PGOOD2 PGOOD3 PGOOD4 VOUT1
VFB1
90.9k
RUN1
RUN2
RUN3
RUN4
INTVCC
47µF
6.3V
VOUT2
VFB2
INTVCC
VOUT3
VFB3
INTVCC
VOUT1
1.0V/2.4A
LTM4668A
INTVCC
MODE/SYNC
VOUT4
VFB4
GND
13.3k
47µF
6.3V
VOUT2
3.3V/2.4A
4668a F15
Figure 15. 5V to 17V Input, 1V and 3.3V Output at 2.4A Design with Pulse-Skipping Mode
PGOOD1 PGOOD2 PGOOD3 PGOOD4
VIN
2.7V TO 17V
22µF
25V
VIN PGOOD1 PGOOD2 PGOOD3 PGOOD4 VOUT1
VFB1
30.1k
RUN1
RUN2
RUN3
RUN4
INTVCC
VOUT2
VFB2
INTVCC
VOUT3
VFB3
INTVCC
VOUT4
VFB4
INTVCC
47µF
6.3V
×2
VOUT
1.8V/4.8A
LTM4668A
INTVCC
MODE/SYNC
GND
4668a F16
Figure 16. 2.7V to 17V Input, Four Phase Parallel Single Output 1.8V at 4.8A Design
Rev. A
20
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LTM4668A
PACKAGE DESCRIPTION
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
Table 9. LTM4668A Component BGA Pinout
PIN
NAME
PIN
NAME
PIN
NAME
PIN
NAME
PIN
NAME
PIN
NAME
PIN
NAME
A1
VOUT1
B1
VOUT1
C1
FB1
D1
PGOOD4
E1
FB4
F1
VOUT4
G1
VOUT4
A2
GND
B2
GND
C2
GND
D2
PGOOD1
E2
GND
F2
GND
G2
GND
A3
GND
B3
GND
C3
RUN1
D3
GND
E3
RUN4
F3
GND
G3
GND
A4
VIN
B4
VIN
C4
INTVCC
D4
GND
E4
MODE/SYNC
F4
VIN
G4
VIN
A5
GND
B5
GND
C5
RUN2
D5
GND
E5
RUN3
F5
GND
G5
GND
A6
GND
B6
GND
C6
GND
D6
PGOOD2
E6
GND
F6
GND
G6
GND
A7
VOUT2
B7
VOUT2
C7
FB2
D7
PGOOD3
E7
FB3
F7
VOUT3
G7
VOUT3
Rev. A
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PACKAGE TOP VIEW
E
0.8
1.6
SUGGESTED PCB LAYOUT
TOP VIEW
0.000
aaa Z
2×
0.40 ±0.025 Ø 49x
4
0.8
PIN “A1”
CORNER
1.6
X
2.4
1.6
0.8
0.000
0.8
1.6
2.4
Y
D
2×
aaa Z
SYMBOL
A
A1
A2
b
b1
D
E
e
F
G
H1
H2
aaa
bbb
ccc
ddd
eee
b1
DETAIL A
NOM
2.10
0.40
1.70
0.50
0.40
6.25
6.25
0.80
4.80
4.80
0.20
1.50
MAX
2.30
0.50
1.80
0.55
0.43
DIMENSIONS
A
A2
SUBSTRATE THK
MOLD CAP HT
BALL DIMENSION
PAD DIMENSION
BALL HT
NOTES
DETAIL B
PACKAGE SIDE VIEW
0.15
0.10
0.20
0.15
0.08
TOTAL NUMBER OF BALLS: 49
MIN
1.90
0.30
1.60
0.45
0.37
H1
SUBSTRATE
A1
ddd M Z X Y
eee M Z
DETAIL B
H2
MOLD
CAP
ccc Z
Øb (49 PLACES)
// bbb Z
(Reference LTC DWG# 05-08-1600 Rev Ø)
Z
22
Z
BGA Package
49-Lead (6.25mm × 6.25mm × 2.10mm)
e
5
G
4
3
e
2
1
DETAIL A
PACKAGE BOTTOM VIEW
b
6
G
F
E
D
C
B
A
PIN 1
6
SEE NOTES
DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
4
TRAY PIN 1
BEVEL
COMPONENT
PIN “A1”
6
!
BGA 49 0917 REV Ø
PACKAGE IN TRAY LOADING ORIENTATION
LTMXXXXXX
µModule
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
5. PRIMARY DATUM -Z- IS SEATING PLANE
BALL DESIGNATION PER JEP95
3
2. ALL DIMENSIONS ARE IN MILLIMETERS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
F
b
3
SEE NOTES
7
LTM4668A
PACKAGE DESCRIPTION
Rev. A
2.4
2.4
LTM4668A
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
02/20
Added ground symbol to Typical Application schematics.
1
MODE/SYNC pin description: Added “Do not float this pin”.
7
INTVCC pin description: Added “INTVCC only starts up if at least one of the RUN pins is high”.
7
Added clarification on VIN to VOUT step-down ratio on LTM466A.
9
Added clarification on PGOOD in multi-channel applications.
13
Table 5: Added 3 more lines for VOUT = 1V, 1.2V, 1.5V.
18
Edited Figure 14 and 15.
20
Edited Figure 16.
21
Rev. A
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Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
more by
information
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23
LTM4668A
PACKAGE PHOTO
DESIGN RESOURCES
SUBJECT
DESCRIPTION
µModule Design and Manufacturing Resources
Design:
• Selector Guides
• Demo Boards and Gerber Files
• Free Simulation Tools
µModule Regulator Products Search
1. Sort table of products by parameters and download the result as a spread sheet.
Manufacturing:
• Quick Start Guide
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability
2. Search using the Quick Power Search parametric table.
Digital Power System Management
Analog Devices’ family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.
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Ultrathin, Quad 3A Step-Down µModule Regulator
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