LTM4680
Dual 30A or Single 60A µModule Regulator
with Digital Power System Management
FEATURES
DESCRIPTION
Dual 30A or Single 60A Digitally Adjustable Analog
Loops with Digital Interface for Control and Monitoring
nn Wide Input Voltage Range: 4.5V to 16V
nn Output Voltage Range: 0.5V to 3.3V
nn 90% Full Load Efficiency from 12V to 1V
IN
OUT at 60A
nn ±0.5% Maximum DC Output Error Over Temperature
nn ±2.5% Current Readback Accuracy (25°C to 125°C)
nn Integrated Input Current Sense Amplifier
nn 400kHz PMBus-Compliant I2C Serial Interface
nn Supports Telemetry Polling Rates up to 125Hz
nn Constant Frequency Current Mode Control
nn Parallel and Current Share Multiple Modules
nn Pin Compatible with LTM4678
nn 16mm × 16mm × 7.82mm BGA Package
Readable Data:
nn Input and Output Voltages, Currents, and Temperatures
nn Running Peak Values, Uptime, Faults and Warnings
nn Onboard EEPROM Fault Log Record
Writable Data and Configurable Parameters:
nn Output Voltage, Voltage Sequencing and Margining
nn Digital Soft-Start/Stop Ramp, Program Analog Loop
nn OV/UV/OT, UVLO, Frequency and Phasing
The LTM®4680 is a dual 30A or single 60A step-down
µModule® (power module) DC/DC regulator featuring
remote configurability and telemetry-monitoring of power
management parameters over PMBus—an open standard I2C-based digital interface protocol. The LTM4680
is comprised of digitally programmable analog control
loops, precision mixed-signal circuitry, EEPROM, power
MOSFETs, inductors and supporting components.
nn
APPLICATIONS
nn
System Optimization, Characterization and Data Mining
in Prototype, Production and Field Environments
The LTM4680 product video is available on the website.
The LTM4680’s 2-wire serial interface allows outputs
to be margined, tuned and ramped up and down at programmable slew rates with sequencing delay times. True
input current sense, output currents and voltages, output
power, temperatures, uptime and peak values are readable. Custom configuration of the EEPROM contents is not
required. At start-up, output voltages, switching frequency,
and channel phase angle assignments can be set by pinstrapping resistors. The LTpowerPlay® GUI and DC1613
USB-to-PMBus converter and demo kits are available.
The LTM4680 is offered in a 16mm × 16mm × 7.82mm
BGA package available with SnPb or RoHS compliant terminal finish. Pin compatible with LTM4678.
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. Patents including 5408150, 5481178, 5705919, 5929620, 6144194, 6177787, 6580258,
7420359, 8163643. Licensed under U.S. Patent 7000125 and other related patents worldwide.
Click to view associated Video Design Idea.
TYPICAL APPLICATION
Dual 30A µModule Regulator with Digital Interface for Control and Monitoring*
22µF
×5
IN+
VOSNS0+
RSENSE
ON/OFF CONTROL
FAULT INTERRUPTS
SYNCHRONIZATION TIME-BASE
REGISTER WRITE PROTECTION
IN–
VIN1
VIN0
SVIN
RUN1
VOSNS0–
LTM4680
VOSNS1+
LOAD1
VOSNS1–
FAULT1
SYNC
SHARE_CLK
*FOR COMPLETE CIRCUIT, SEE FIGURE 46
LOAD0
VOUT1
RUN0
FAULT0
WP
VOUT0
ADJUSTABLE
UP TO 30A
VOUT0
SCL
SDA
ALERT
SGND GND
100µF
×8
VOUT1
ADJUSTABLE
UP TO 30A
100µF
×8
I2C/SMBus I/F WITH PMBus
COMMAND SET TO/FROM
IPMI OR OTHER BOARD
MANAGEMENT CONTROLLER
4680 TA01a
95
90
EFFICIENCY (%)
4.5V to 16V
(FROM
4.5V TO 5.75V,
CONNECT
VIN, SVIN
AND INTVCC
TOGETHER)
Efficiency vs Current at 12V Input
100
85
80
75
70
65
1.0V, 250kHz
1.5V, 425kHz
0
5
10
15
20
LOAD CURRENT (A)
25
30
4680 TA01b
Rev. B
Document Feedback
For more information www.analog.com
1
LTM4680
TABLE OF CONTENTS
Features...................................................... 1
Applications................................................. 1
Typical Application ......................................... 1
Description.................................................. 1
Table of Contents........................................... 2
Absolute Maximum Ratings............................... 4
Order Information........................................... 4
Pin Configuration........................................... 4
Electrical Characteristics.................................. 5
Typical Performance Characteristics................... 12
Pin Functions............................................... 15
Simplified Block Diagram................................ 19
Decoupling Requirements................................ 19
Functional Diagram....................................... 20
Test Circuits................................................ 21
Operation................................................... 23
Power Module Introduction ....................................23
Power Module Overview, Major Features.................23
EEPROM with ECC .................................................. 24
Power-Up and Initialization .....................................25
Soft-Start ................................................................26
Time-Based Sequencing .........................................26
Voltage-Based Sequencing .....................................26
Shutdown ............................................................... 27
Light-Load Current Operation ................................. 27
Switching Frequency and Phase.............................. 28
PWM Loop Compensation ...................................... 28
Output Voltage Sensing .......................................... 28
INTVCC/EXTVCC Power ........................................... 28
Output Current Sensing and Sub Milliohm
DCR Current Sensing ..............................................29
Input Current Sensing .............................................29
PolyPhase Load Sharing .........................................29
External/Internal Temperature Sense ......................30
RCONFIG (Resistor Configuration) Pins ..................30
Table 1. VOUTn_CFG Pin Strapping Look-Up Table for
the LTM4680’s Output Voltage, Coarse Setting (Not
Applicable if MFR_CONFIG_ALL[6] = 1b)..............31
Table 2. VTRIMn_CFG Pin Strapping Look-Up
Table for the LTM4680’s Output Voltage, Fine
Adjustment Setting (Not Applicable if MFR_
CONFIG_ALL[6] = 1b) ......................................... 31
2
Table 3. FSWPH_CFG Pin Strapping Look-Up Table
to Set the LTM4680’s Switching Frequency and
Channel Phase-Interleaving Angle (Not Applicable
if MFR_CONFIG_ALL[6] = 1b) ............................ 32
Table 4. ASEL Pin Strapping Look-Up Table to
Set the LTM4680’s Slave Address (Applicable
Regardless of MFR_CONFIG_ALL[6] Setting) .....33
Table 5. LTM4680 MFR_ADDRESS Command
Examples Expressed in 7- and 8-Bit Addressing ..... 33
Fault Detection and Handling ..................................33
Status Registers and ALERT Masking ...................34
Figure 5. LTM4680 Status Register Summary.......35
Mapping Faults to FAULT Pins ..............................36
Power Good Pins ..................................................36
CRC Protection .....................................................36
Serial Interface .......................................................36
Communication Protection ...................................36
Device Addressing ..................................................36
Responses to VOUT and IIN/IOUT Faults ................... 37
Output Overvoltage Fault Response ..................... 37
Output Undervoltage Response ............................38
Peak Output Overcurrent Fault Response .............38
Responses to Timing Faults ....................................38
Responses to VIN OV Faults ....................................38
Responses to OT/UT Faults .....................................38
Internal Overtemperature Fault Response ............38
External Overtemperature and
Undertemperature Fault Response .....................39
Responses to Input Overcurrent and Output
Undercurrent Faults ................................................39
Responses to External Faults .................................. 39
Fault Logging .......................................................... 39
Bus Timeout Protection .......................................... 39
Similarity Between PMBus, SMBus and I2C
2-Wire Interface ......................................................40
PMBus Serial Digital Interface ................................40
Table 6. Abbreviations of Supported Data Formats ....41
Figure 6. PMBus Timing Diagram.......................... 41
Figures 7 to 24 PMBus Protocols............................ 42
Rev. B
For more information www.analog.com
LTM4680
TABLE OF CONTENTS
PMBus Command Summary............................. 45
PMBus Commands .................................................45
Table 7. PMBus Commands Summary (Note:
The Data Format Abbreviations Are Detailed in
Table 8) ............................................................45
Table 8. Data Format Abbreviations ......................50
Applications Information................................. 51
VIN to VOUT Step-Down Ratios ................................ 51
Input Capacitors ..................................................... 51
Output Capacitors ................................................... 51
Light Load Current Operation.................................. 51
Switching Frequency and Phase ............................. 52
Output Current Limit Programming ........................53
Minimum On-Time Considerations .........................54
Variable Delay Time, Soft-Start and Output
Voltage Ramping ....................................................54
Digital Servo Mode .................................................54
Soft Off (Sequenced Off) ........................................55
Undervoltage Lockout .............................................56
Fault Detection and Handling ..................................56
Open-Drain Pins .....................................................56
Phase-Locked Loop and Frequency Synchronization .. 57
Input Current Sense Amplifier .................................58
Programmable Loop Compensation .......................58
Checking Transient Response ................................. 59
PolyPhase Configuration ......................................60
Connecting The USB to I2C/SMBus/PMBus
Controller to the LTM4680 In System .....................60
LTpowerPlay: An Interactive GUI for Digital Power........ 61
PMBus Communication and Command
Processing .............................................................. 61
Thermal Considerations and Output
Current Derating ...................................................63
Tables 10 thru 11: Output Current Derating............66
Table 12. Channel Output Voltage vs Capacitor
Selection, All Ceramic Configuration, 15A to 30A
Load Step with 15A/µs Slew Rate .......................66
Table 13. Channel Output Voltage vs Capacitor
Selection, Bulk and Ceramic Cap Configuration,
15A to 30A Load Step with 15A/µs Slew Rate .... 67
Table 14. Dual Phase Single Output Voltage vs
Capacitor Selection, Bulk and Ceramic Cap
Configuration, 30A to 60A Load Step with 30A/µs
Slew Rate ...........................................................68
Derating Curves.......................................................69
EMI Performance .................................................... 70
Safety Considerations ............................................. 70
Layout Checklist/Example ...................................... 70
Typical Applications....................................... 72
PMBus Command Details................................ 77
Addressing and Write Protect..................................77
General Configuration Commands........................... 79
On/Off/Margin.........................................................80
PWM Configuration................................................. 82
Voltage.....................................................................85
Input Voltage and Limits........................................85
Output Voltage and Limits.....................................86
Output Current and Limits.......................................89
Input Current and Limits ....................................... 91
Temperature.............................................................92
Power Stage DCR Temperature Calibration...........92
Timing.....................................................................93
Timing—On Sequence/Ramp................................93
Timing—Off Sequence/Ramp...............................94
Precondition for Restart........................................95
Fault Response........................................................95
Fault Responses All Faults.....................................95
Fault Responses Input Voltage..............................96
Fault Responses Output Voltage............................96
Fault Responses Output Current............................99
Fault Responses IC Temperature......................... 100
Fault Responses External Temperature................ 101
Fault Sharing.......................................................... 102
Fault Sharing Propagation................................... 102
Fault Sharing Response....................................... 104
Scratchpad............................................................ 104
Identification.......................................................... 105
Fault Warning and Status....................................... 106
Telemetry............................................................... 113
NVM Memory Commands..................................... 117
Store/Restore...................................................... 117
Fault Logging....................................................... 118
Block Memory Write/Read................................... 122
Package Description.................................... 123
Table 23. LTM4680 BGA Pinout........................... 123
Revision History......................................... 125
Package Photograph.................................... 126
Design Resources....................................... 126
Related Parts............................................. 126
Rev. B
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3
LTM4680
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
Terminal Voltages:
VINn (Note 4), SVIN, IIN+, IIN−....................... –0.3V to 18V
(SVIN – IIN+), (IIN+ – IIN−)............................ –0.3V to 0.3V
SW0, SW1................... −1V to 18V, −5V to 18V Transient
INTVCC, EXTVCC........................................... –0.3V to 6V
VOUTn......................................................... –0.3V to 3.6V
VOSNS0+, VOSNS1+.......................................... –0.3V to 6V
VOSNS0−, VOSNS1−....................................... –0.3V to 0.3V
RUNn, SDA, SCL, ALERT............................ –0.3V to 5.5V
FSWPH_CFG, VOUT0,1_CFG,
VTRIM0,1_CFG, ASEL.......................... –0.3V to 2.75V
FAULTn, SYNC, SHARE_CLK, WP,
PGOOD0, PGOOD1................................ −0.3V to 3.6V
COMPna, COMPnb, ................................... –0.3V to 2.7V
TSNS0a, TSNS1a....................................... –0.3V to 2.2V
TSNS0b, TSNS1b....................................... –0.3V to 0.8V
Temperatures
Internal Operating Temperature Range
(Notes 2, 13, 16, 17)............................... –40°C to 125°C
Storage Temperature Range................... –55°C to 125°C
Peak Solder Reflow Package Body Temperature.... 245°C
(Not recommended for upside down reflow.)
TOP VIEW
VOSNS1+ VOSNS1–
A
VOUT1
GND
SW1
B
VOUT1
COMP1b
C
D
VTRIM0_
CFG
SHARE
VDD25
TSNS1b PGOOD1 COMP1a CLK
GND
SVIN
WP
GND
INTVCC VDD33
E
VIN1
FSWPH_ VTRIM1_ VOUT0_ VOUT1_
CFG
CFG
EXTVCC
F
SGND
GND
G
VIN0
COMP0b SDA
CFG
CFG
RUN1
ASEL
FAULT1 RUN0
ALERT FAULT0
H
IIN+
PGOOD0 TSNS0b COMP0a TSNS1a TSNS0a
SCL
J
IIN–
GND
SYNC
K
VOUT0
GND
L
VOUT0
SW0
VOSNS0+ VOSNS0–
M
1
2
3
4
5
6
7
8
9
10
11
12
BGA PACKAGE
144-LEAD (16mm × 16mm × 7.82mm)
TJMAX = 125°C, θJCtop = 3.3°C/W, θJCbottom = 2°C/W, θJB = 2°C/W, θJA = 7°C/W
WEIGHT = 7.4 GRAMS
ORDER INFORMATION
PART MARKING*
PART NUMBER
LTM4680EY#PBF
LTM4680IY#PBF
LTM4680IY
PAD OR BALL FINISH
SAC305 (RoHS)
SnPb (63/37)
DEVICE
LTM4680Y
LTM4680Y
LTM4680Y
Contact the factory for parts specified with wider operating temperature
ranges. *Device temperature grade is indicated by a label on the shipping
container. Pad or ball finish code is per IPC/JEDEC J-STD-609.
4
FINISH CODE
PACKAGE
TYPE
MSL
RATING
BGA
4
e1
TEMPERATURE RANGE
(See Note 2)
–40°C to 125°C
e0
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures
• LGA and BGA Package and Tray Drawings
Rev. B
For more information www.analog.com
LTM4680
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2). n is specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUNn = 3.3V,
EXTVCC = 0, FREQUENCY_SWITCH = 350kHz and VOUTn commanded to 1.000V unless otherwise noted. Configured with factory-default
EEPROM settings and per Test Circuit 1, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
VIN
Input DC Voltage
Test Circuit 1
Test Circuit 2; VIN_OFF < VIN_ON = 4V
VOUTn
Range of Output Voltage Regulation
VOUTn Differentially Sensed on VOSNSn+/VOSNSn– Pin-Pair;
Commanded by Serial Bus or with Resistors Present at
Start-Up on VOUTn_CFG
VOUTn(DC)
Output Voltage, Total Variation with
Line and Load
Digital Servo Engaged (MFR_PWM_MODEn[6] = 1b)
Digital Servo Disengaged (MFR_PWM_MODEn[6] = 0b)
VOUTn Commanded to 1.000V, VOUTn Low Range
(MFR_PWM_MODEn[1] = 1b) (Note 5)
VUVLO
Undervoltage Lockout Threshold,
When VIN < 4.3V
VINTVCC Falling
VINTVCC Rising
MAX
UNITS
l
l
5.75
4.5
MIN
TYP
16
5.75
V
V
l
0.5
3.34
V
l 0.995 1.000 1.005
0.985 1.000 1.015
V
V
3.55
3.90
V
V
Input Specifications
IINRUSH(VIN)
Input Inrush Current at
Start-Up
Test Circuit 1, VOUTn =1V, VIN = 12V; No Load Besides
Capacitors; TON_RISEn = 3ms (Note 12)
IQ(SVIN)
Input Supply Bias Current
Forced Continuous Mode, MFR_PWM_MODEn[0] = 1b
RUNn = 3.3V
Shutdown, RUN0 = RUN1 = 0V
IS(VINn,DCM)
Input Supply Current in
Discontinuous Mode Operation
Discontinuous Mode, MFR_PWM_MODEn[0] = 0b,
IOUTn = 100mA
IS(VINn,FCM)
Input Supply Current in ForcedContinuous Mode Operation
Forced Continuous Mode, MFR_PWM_MODEn[0] = 1b
VINn = 12V, VOUTn = 1V
IOUTn = 30A
50
mA
37
25
mA
mA
20
mA
3.2
A
Output Specifications
IOUTn
Output Continuous Current Range
Utilizing MFR_PWM_MODE[7] = 1 for IOUT_OC_FAULT_
LIMIT, Page 90 (Note 6)
∆VOUTn(LINE)
Line Regulation Accuracy
Digital Servo Engaged (MFR_PWM_MODEn[6] = 1b)
Digital Servo Disengaged (MFR_PWM_MODEn[6] = 0b)
SVIN and VINn Electrically Shorted Together and INTVCC
Open Circuit; IOUTn = 0A, 5.75V ≤ VIN ≤ 16V, VOUT Low Range
(MFR_PWM_MODEn[1] = 1b), FREQUENCY_SWITCH =
350kHz (Note 5)
VOUTn
∆VOUTn(LOAD)
Load Regulation Accuracy
VOUTn
VOUTn(AC)
Digital Servo Engaged (MFR_PWM_MODEn[6] = 1b)
Digital Servo Disengaged (MFR_PWM_MODEn[6] = 0b)
0A ≤ IOUTn ≤ 30A, VOUTn Low Range, (MFR_PWM_
MODEn[1] = 1b) (Note 5)
0
30
A
l
0.03
0.03
±0.2
%/V
%/V
l
0.03
0.2
0.5
%
%
Output Voltage Ripple
10
fS (Each Channel) VOUTn Ripple Frequency
FREQUENCY_SWITCH Set to 350kHz (0xFABC)
∆VOUTn(START)
Turn-On Overshoot
TON_RISEn = 3ms (Note 12)
tSTART
Turn-On Start-Up Time
Time from VIN Toggling from 0V to 12V to Rising Edge
PGOODn. TON_DELAYn = 0ms, TON_RISEn = 3ms
l
tDELAY(0ms)
Turn-On Delay Time
Time from First Rising Edge of RUNn to Rising Edge of
PGOODn . TON_DELAYn = 0ms, TON_RISEn = 3ms,
VIN Having Been Established for at Least 70ms
l
∆VOUTn(LS)
Peak Output Voltage Deviation for
Dynamic Load Step
Load: 0A to 15A and 15A to 0A at 15A/µs,
VOUTn = 1V, VIN = 12V (Note 12) See Transient Graph
tSETTLE
Settling Time for Dynamic Load Step Load: 0A to 15A and 15A to 0A at 15A/µs,
VOUTn = 1V, VIN = 12V (Note 12) See Transient Graphs
l
320
2.75
350
mVP-P
370
kHz
8
mV
30
ms
3.1
3.8
ms
60
mV
50
µs
Rev. B
For more information www.analog.com
5
LTM4680
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2). n is specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUNn = 3.3V,
EXTVCC = 0, FREQUENCY_SWITCH = 350kHz and VOUTn commanded to 1.000V unless otherwise noted. Configured with factory-default
EEPROM settings and per Test Circuit 1, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
IOUTn(OCL_AVG)
Output Current Limit, Time
Averaged, Readback
Time-Averaged Output Inductor Current Limit Inception
Threshold, Commanded by IOUT_OC_FAULT_LIMITn
(Note 12)
Utilizing MFR_PWM_MODE[7] = 0, Using IL PEAK = 40A,
Page 90
VFBCMn
Feedback Input Common Mode
Range
VOSNSn– Valid Input Range (Referred to SGND)
VOSNSn+ Valid Input Range (Referred to SGND)
VOUT-RNGL
Full-Scale Command Voltage, Range VOUTn Commanded to 2.750V, MFR_PWM_MODEn[1] = 1b
Low (0.5V to 2.75V)
(Notes 7, 15)
Set Point Accuracy
Resolution
LSB Step Size
MIN
TYP
MAX
39
UNITS
A
Control Section
VOUT-RNGH
l
l
Full-Scale Command Voltage, Range VOUTn Commanded to 3.6V, MFR_PWM_MODEn[1] = 0b
High (0.5V to 3.6V)
Limit Design to 3.6V Operating for Module
Set Point Accuracy
(Notes 7, 15)
Resolution
LSB Step Size
–0.1
0.3
3.6
2.75
−0.5
12
0.688
V
0.5
3.6
–0.5
12
1.375
V
V
%
Bits
mV
V
0.5
%
Bits
mV
RVSNS0+
VOSNS0+ Impedance to SGND
0.05V ≤ VVOSNS0+ – VSGND ≤ 3.3V
50
kΩ
RVSNS1+
VOSNS1+ Impedance to SGND
0.05V ≤ VVOSNS1+ – VSGND ≤ 3.3V
50
kΩ
tON(MIN)
Minimum On-Time
(Note 8 )
60
ns
RCOMP0,1
Resolution
Compensation Resistor RTH(MAX)
Compensation Resistor RTH(MIN)
MFR_PWM_CONFIG[4:0] = 0 to 31 (See Figure 1)
5
62
0.5
Bits
kΩ
kΩ
gm0,1
Resolution
Error Amplifier gm(MAX)
Error Amplifier gm(MIN)
LSB Step Size
COMP0,1 = 1.35V, MFR_PWM_CONFIG[7:5] = 0 to 7
3
5.76
1
0.68
Bits
mmho
mmho
mmho
Analog OV/UV (Overvoltage/Undervoltage) Output Voltage Supervisor Comparators (VOUT_OV/UV_FAULT_LIMIT and VOUT_OV/UV_WARN_LIMIT Monitors)
NOV/UV_COMP
Resolution, Output Voltage
Supervisors
(Note 15)
VOV-RNG
Output OV Comparator Threshold
Detection Range
(Note 15)
High Range Scale, MFR_PWM_MODEn[1] = 0b
Low Range Scale, MFR_PWM_MODEn[1] = 1b
VOUSTP
Output OV and UV Comparator
Threshold Programming LSB Step
Size
(Note 15)
High Range Scale, MFR_PWM_MODEn[1] = 0b
Low Range Scale, MFR_PWM_MODEn[1] = 1b
VOUT-RNGH
Full-Scale Command Voltage, Range VOUTn Commanded to 3.6V, MFR_PWM_MODEn[1] = 0b
High (0.5V to 3.6V)
(Notes 7, 15)
Set Point Accuracy
Resolution
LSB Step Size
VOV-ACC-n
Output OV Comparator Threshold
Accuracy Channel 0 and 1
2V ≤ VVOSNSn+ – VVOSNSn– ≤ 3.6V, MFR_PWM_MODEn[1] = 0b l
0.5V ≤ VVOSNSn+ – VVOSNSn– < 2.7V, MFR_PWM_MODEn[1] = 1b l
(Note 14)
VUV-RNG
Output UV Comparator Threshold
Detection Range
High Range Scale, MFR_PWM_MODEn[1] = 0b
Low Range Scale, MFR_PWM_MODEn[1] = 1b
(Note 15)
6
9
1
0.5
Bits
3.6
2.7
11.2
5.6
3.5
–0.5
1
0.5
12
1.375
V
V
mV
mV
3.7
V
–0.5
%
Bits
mV
±1.5
±40
%
mV
3.6
2.7
V
V
Rev. B
For more information www.analog.com
LTM4680
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2). n is specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUNn = 3.3V,
EXTVCC = 0, FREQUENCY_SWITCH = 350kHz and VOUTn commanded to 1.000V unless otherwise noted. Configured with factory-default
EEPROM settings and per Test Circuit 1, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
VUV-ACC-n
Output UV Comparator Threshold
Accuracy
2V ≤ VVSNSn+ – VVSNSn– ≤ 3.6V, MFR_PWM_MODEn[1] = 0b
0.5V ≤ VVSNSn+ – VVSNSn– < 2.7V, MFR_PWM_MODEn[1] = 1b
tPROP-OV
Output OV Comparator Response
Times
tPROP-UV
Output UV Comparator Response
Times
MIN
TYP
MAX
UNITS
±1.5
±40
%
mV
Overdrive to 10% Above Programmed Threshold
100
µs
Under Drive to 10% Below Programmed Threshold
100
µs
l
l
(Note 14)
Analog OV/UV SVIN Input Voltage Supervisor Comparators (Threshold Detectors for VIN_ON and VIN_OFF)
NSVIN-OV/UV-COMP SVIN OV/UV Comparator ThresholdProgramming Resolution
(Notes 14, 15)
9
SVIN-OU-RANGE
SVIN OV/UV Comparator ThresholdProgramming Range
Limited to Abs Max = 18V for LTM4680 Module
SVIN-OU-STP
SVIN OV/UV Comparator ThresholdProgramming LSB Step Size
(Note 15)
SVIN-OU-ACC
SVIN OV/UV Comparator Threshold
Accuracy
4.5V < SVIN ≤ 16V
l
±350
mV
tPROP-SVIN-HIGH-VIN SVIN OV/UV Comparator Response
Time, High VIN Operating
Configuration
Test Circuit 1, and:
VIN_ON = 9V; SVIN Driven from 8.775V to 9.225V
VIN_OFF = 9V; SVIN Driven from 9.225V to 8.775V
l
l
100
100
µs
µs
tPROP-SVIN-LOW-VIN SVIN OV/UV Comparator Response
Time, Low VIN Operating
Configuration
Test Circuit 2, and:
VIN_ON = 4.5V; SVIN Driven from 4.225V to 4.725V
VIN_OFF = 4.5V; SVIN Driven from 4.725V to 4.225V
l
l
100
100
µs
µs
4.5
Bits
18
V
76
mV
Channels 0 and 1 Output Voltage Readback (READ_VOUTn)
NVO-RB
Output Voltage Readback Resolution (Note 15)
and LSB Step Size
VO-F/S
Output Voltage Full-Scale Digitizable
Range
VRUNn = 0V (Note 15), Limited to 3.6V Max Operating
VO-RB-ACC-n
Output Voltage Readback Accuracy
1V ≤ VVOSNSn+ – VVOSNSn– ≤ 3.3V
0.5V ≤ VVOSNSn+ – VVOSNSn– < 1V
tCONVERT-VO-RB
Output Voltage Readback Update
Rate
MFR_ADC_CONTROL = 0x00 (Notes 9, 15)
MFR_ADC_CONTROL = 0x01 through 0x0C (Notes 9, 15)
MFR_ADC_CONTROL Section
16
244
Bits
µV
8
l
l
V
Within ±0.5% of Reading
Within ±5mV of Reading
90
8
ms
ms
ms
10
15.625
Bits
mV
Input Voltage (SVIN) Readback (READ_VIN)
NSVIN-RB
Input Voltage Readback Resolution
and LSB Step Size
(Notes 11, 15) Limited to Abs Max = 18V for
LTM4680 Module
SVIN-F/S
Input Voltage Full-Scale Digitizable
Range
(Notes 11, 15)
SVIN-RB-ACC
Input Voltage Readback Accuracy
READ_VIN, 4.5V ≤ SVIN ≤ 16V
tCONVERT-SVIN-RB
Input Voltage Readback Update Rate MFR_ADC_CONTROL = 0x00 (Notes 9, 15)
MFR_ADC_CONTROL = 0x01 (Notes 9, 15)
43
l
V
Within ±2% of Reading
90
8
ms
ms
Channels 0 and 1 Output Current (READ_IOUTn), Duty Cycle (READ_DUTY_CYCLEn), and Computed Input Current (MFR_READ_IINn) Readback
NIO-RB
Output Current Readback Resolution (Note 15)
and LSB Step Size
IO-F/S
Output Current Full-Scale Digitizable
Range
(Note 15)
Utilizing MFR_PWM_MODE[7] = 0b,
Using IOUT_OC_FAULT_LIMIT = 40A, Page 90
10
34.1
30
Bits
mA
A
Rev. B
For more information www.analog.com
7
LTM4680
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2). n is specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUNn = 3.3V,
EXTVCC = 0, FREQUENCY_SWITCH = 350kHz and VOUTn commanded to 1.000V unless otherwise noted. Configured with factory-default
EEPROM settings and per Test Circuit 1, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
IO-RB-ACC
Output Current, Readback Accuracy
READ_IOUTn, Channels 0 and 1, 0 ≤ IOUTn ≤ 30A,
Forced-Continuous Mode, MFR_PWM_MODEn[0] = 1b
25°C to 125°C
l
–40°C to 125°C
See Histograms in Typical Performance Characteristic, (Note 12).
MIN
TYP
MAX
UNITS
Within 0.75A of Reading
Within 1.5A of Reading
IO-RB(30A)
Full Load Output Current Readback
IOUTn = 30A (Note 12). See Histograms in Typical
Performance Characteristics
30
A
tCONVERT-IO-RB
Output Current Readback Update
Rate
MFR_ADC_CONTROL = 0x00 (Notes 9, 15)
MFR_ADC_CONTROL = 0x06 (CH0 IOUT) or 0x0A (CH1 IOUT)
(Notes 9, 15) See MFR_ADC_CONTROL Section
90
8
ms
ms
Resolution
(Note 15)
10
Bits
VIINSTP
LSB Step Size Full-Scale Range = 16mV
LSB Step Size Full-Scale Range = 32mV
LSB Step Size Full-Scale Range = 64mV
15.26
30.52
61
µV
µV
µV
IIN_TUE
Total Unadjusted Error
Gain = 8, 0V ≤ |VIIN+ – VIIN–| ≤ 5mV
Gain = 4, 0V ≤ |VIIN+ – VIIN–| ≤ 20mV
Gain = 2, 0V ≤ |VIIN+ – VIIN–| ≤ 50mV
Gain = 8, 2.5mV ≤ |VIIN+ – VIIN–| (Note 14)
Gain = 4, 4mV ≤ |VIIN+ – VIIN–| (Note 14)
Gain = 2, 6mV ≤ |VIIN+ – VIIN–| (Note 14)
VOS
Zero-Code Offset Voltage
(Note 15)
tCONVERT
Update Rate
(Notes 9,15) See MFR_ADC_CONTROL Section for Faster
Update Rates
90
ms
Input Current Readback
N
±2
±1.3
±1.2
l
l
l
±50
%
%
%
µV
Supply Current Readback
N
Resolution
(Note 15)
10
Bits
VICHIPSTP
LSB Step Size Full-Scale Range =
256mV
Onboard 1Ω Resistor
244
µV
ICHIP_RB
ICHIP Readback
SVIN Current
±50
mA
tCONVERT
Update Rate
(Notes 9,15) See MFR_ADC_CONTROL Section for Faster
Update Rates
90
ms
0.25
°C
±2.5
°C
Temperature Readback (T0, T1)
TRES-RB
Temperature Readback Resolution
Channel 0, Channel 1, and Controller (Note 15)
T0_TUE
External Temperature Total
Unadjusted Readback Error
Supporting Only ΔVBE Sensing
T1_TUE
Internal TSNS TUE
VRUN0,1 = 0.0, fSYNC = 0kHz (Note 14)
±1
°C
tCONVERT
Update Rate
MFR_ADC_CONTROL = 0x00 (Notes 9, 15)
MFR_ADC_CONTROL = 0x04 or 0x0C (Notes 9, 15)
90
8
ms
ms
INTVCC Regulator/EXTVCC
VINTVCC
Internal VCC Voltage No Load
6V ≤ VIN ≤ 16V
VLDO_INT
INTVCC Load Regulation
ICC = 0mA to 20mA, 6V ≤ VIN ≤ 16V
VEXTVCC
EXTVCC Switchover Voltage
VIN ≥ 7V, EXTVCC Rising
VLDO_HYS
EXTVCC Hysteresis
VLDO_EXT
EXTVCC Voltage Drop
ICC = 20mA, VEXTVCC = 5.5V
70
VIN_THR
VIN Threshold to Enable EXTVCC
Switchover
VIN Rising
7
V
VIN_THF
VIN Threshold to Disable EXTVCC
Switchover
VIN Falling
6.5
V
8
5.25
4.5
5.5
5.75
V
0.5
±2
%
4.7
V
300
mV
120
mV
Rev. B
For more information www.analog.com
LTM4680
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2). n is specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUNn = 3.3V,
EXTVCC = 0, FREQUENCY_SWITCH = 350kHz and VOUTn commanded to 1.000V unless otherwise noted. Configured with factory-default
EEPROM settings and per Test Circuit 1, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
VVDD33
Internal VDD33 Voltage
4.5V < VINTVCC or 4.8V < VEXTVCC
3.2
ILIM
VDD33 Current Limit
VDD33 = GND, VIN = INTVCC = 4.5V
VVDD33_OV
VVDD33_UV
TYP
MAX
3.3
3.4
UNITS
VDD33 Regulator
V
100
mA
VDD33 Overvoltage Threshold
3.5
V
VDD33 Undervoltage Threshold
3.1
V
VDD25 Regulator
VVDD25
Internal VDD25 Voltage
ILIM
VDD25 Current Limit
VDD25 = GND, VIN = INTVCC = 4.5V
2.5
V
80
mA
Oscillator and Phase-Locked Loop (PLL)
fRANGE
PLL SYNC Range
Synchronized with Falling Edge of SYNC
l
fOSC
Oscillator Frequency Accuracy
Frequency Switch = 250.0 to 1000.0 kHz (Note 15)
l
300
1000
kHz
±7.5
%
VTH(SYNC)
SYNC Input Threshold
VSYNC Falling
VSYNC Rising
1
1.5
VOL(SYNC)
SYNC Low Output Voltage
ILOAD = 3mA
0.2
ILEAK(SYNC)
SYNC Leakage Current in Slave Mode 0V ≤ VPIN ≤ 3.6V
θSYNC-θ0
SYNC to Ch0 Phase Relationship
Based on the Falling Edge of Sync
and Rising Edge of TG0
MFR_PWM_CONFIG[2:0] = 0,2,3
MFR_PWM_CONFIG[2:0] = 5
MFR_PWM_CONFIG[2:0] = 1
MFR_PWM_CONFIG[2:0]= 4,6
0
60
90
120
Deg
Deg
Deg
Deg
θSYNC-θ1
SYNC to Ch1 Phase Relationship
Based on the Falling Edge of Sync
and Rising Edge of TG1
MFR_PWM_CONFIG[2:0] = 3
MFR_PWM_CONFIG[2:0] = 0
MFR_PWM_CONFIG[2:0] = 2,4,5
MFR_PWM_CONFIG[2:0] = 1
MFR_PWM_CONFIG[2:0] = 6
120
180
240
270
300
Deg
Deg
Deg
Deg
Deg
V
V
0.4
±5
V
µA
EEPROM Characteristics
Endurance
(Notes 13, 16)
0°C ≤ TJ ≤ 85°C During EEPROM Write Operations
l 10,000
Retention
(Notes 13, 16)
TJ < 125°C
l
Mass_Write
Mass Write Operation Time
STORE_USER_ALL, 0°C < TJ < 85°C
During EEPROM Write Operation
Cycles
10
Years
440
4100
ms
Leakage Current SDA, SCL, ALERT, RUN
IOL
Input Leakage Current
OV ≤ VPIN ≤ 5.5V
l
±5
µA
OV ≤ VPIN ≤ 3.6V
l
±2
µA
1.35
V
Leakage Current FAULTn, PGOODn, SHARE_CLK
IGL
Input Leakage Current
Digital Inputs SCL, SDA, RUNn, FAULTn
VIH
Input High Threshold Voltage
l
VIL
Input Low Threshold Voltage
l
VHYST
Input Hysteresis
CPIN
Input Capacitance
SCL, SDA
0.8
V
0.08
V
10
pF
Digital Input WP
IPUWP
Input Pull-Up Current
WP
10
µA
Open-Drain Outputs SCL, SDA, FAULTn, ALERT, RUNn, SHARE_CLK, PGOODn
VOL
Output Low Voltage
ISINK = 3mA
0.4
V
Rev. B
For more information www.analog.com
9
LTM4680
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2). n is specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUNn = 3.3V,
EXTVCC = 0, FREQUENCY_SWITCH = 350kHz and VOUTn commanded to 1.000V unless otherwise noted. Configured with factory-default
EEPROM settings and per Test Circuit 1, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
1.5
1.8
UNITS
Digital Inputs SHARE_CLK, WP
VIH
Input High Threshold Voltage
l
VIL
Input Low Threshold Voltage
l
0.6
V
1
V
3
µs
100
µs
10
µs
Digital Filtering of FAULTn
IFLTG
Input Digital Filtering FAULTn
Digital Filtering of PGOODn
IFLTG
Output Digital Filtering PGOODn
Digital Filtering of RUNn
IFLTG
Input Digital Filtering RUN
PMBus Interface Timing Characteristics
fSCL
Serial Bus Operating Frequency
l
10
tBUF
Bus Free Time Between Stop and
Start
l
1.3
µs
tHD(STA)
Hold Time After Repeated Start
Condition After This Period, the First
Clock is Generated
l
0.6
µs
tSU(STA)
Repeated Start Condition Setup Time
l
0.6
tSU(ST0)
Stop Condition Setup Time
l
0.6
tHD(DAT)
Date Hold Time
Receiving Data
Transmitting Data
l
l
0
0.3
tSU(DAT)
Data Setup Time
Receiving Data
tTIMEOUT_SMB
Stuck PMBus Timer Non-Block Reads Measured from the Last PMBus Start Event
Stuck PMBus Timer Block Reads
tLOW
Serial Clock Low Period
l
1.3
tHIGH
Serial Clock High Period
l
0.6
10000
kHz
µs
µs
0.9
0.1
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTM4680 is tested under pulsed-load conditions such that
TJ ≈ TA. The LTM4680E is guaranteed to meet performance specifications
over the 0°C to 125°C internal operating temperature range. Specifications
over the –40°C to 125°C internal operating temperature range are assured
by design, characterization and correlation with statistical process
10
400
µs
µs
µs
32
255
ms
10000
µs
µs
controls. The LTM4680I is guaranteed to meet specifications over the full
–40°C to 125°C internal operating temperature range. TJ is calculated from
the ambient temperature TA and the power dissipation PD according the
formula:
TJ = TA + (PD • θJA)
Note that the maximum ambient temperature consistent with these
specifications is determined by specific operating conditions in
conjunction with board layout, the rated package thermal resistance and
other environmental factors.
Rev. B
For more information www.analog.com
LTM4680
ELECTRICAL CHARACTERISTICS
Note 11: The absolute maximum rating for the SVIN pin is 18V. Input
voltage telemetry (READ_VIN) is obtained by digitizing a voltage scaled
down from the SVIN pin.
Note 12: These typical parameters are based on bench measurements and
are not production tested.
Note 13: EEPROM endurance and retention are guaranteed by wafer-level
testing for data retention. The minimum retention specification applies
for devices whose EEPROM has been cycled less than the minimum
endurance specification, and whose EEPROM data was written to at 0°C
≤ TJ ≤ 85°C. The RESTORE_USER_ALL or MFR_RESET is valid over
the entire operating temperature range and does not influence EEPROM
characteristics.
Note 14: Part tested with PWM disabled. Evaluation in application
demonstrates capability. TUE(%) = ADC Gain Error (%) + 100 (zero code
offset + ADC Linearity Error)/Actual Value.
Note 15: Tested at IC-level ATE.
Note 16: The LTM4680’s EEPROM temperature range for valid write
commands is 0°C to 85°C. To achieve guaranteed EEPROM data retention,
execution of the “STORE_USER_ALL” command—i.e., uploading RAM
contents to NVM—outside this temperature range is not recommended.
However, as long as the LTM4680’s EEPROM temperature is less than
130°C, the LTM4680 will obey the STORE_USER_ALL command. Only
when EEPROM temperature exceeds 130°C, the LTM4680 will not act
on any STORE_USER_ALL transactions: instead, the LTM4680 NACKs
the serial command and asserts its relevant CML (communications,
memory, logic) fault bits. EEPROM temperature can be queried prior
to commanding STORE_USER_ALL; see the Applications Information
section.
Note 17: The LTM4680 includes overtemperature protection that is
intended to protect the device during momentary overload conditions.
Junction temperature will exceed 125°C when overtemperature protection
is active. Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
62
56
50
43
RTH(kΩ)
Note 3: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified
Note 4: The two power inputs—VIN0 and VIN1—and their respective power
outputs—VOUT0 and VOUT1—are tested independently in production. A
shorthand notation is used in this document that allows these parameters
to be referred to by “VINn” and “VOUTn”, where n is permitted to take on
a value of 0 or 1. This italicized, subscripted “n ” notation and convention
is extended to encompass all such pin names, as well as register names
with channel-specific, i.e., paged data. For example, VOUT_COMMANDn
refers to the VOUT_COMMAND command code data located in Pages 0
and 1, which in turn relate to channel 0 (VOUT0) and channel 1 (VOUT1).
Registers containing non-page-specific data, i.e., whose data is “global” to
the module or applies to both of the module’s channels lack the italicized,
subscripted “n ”, e.g., FREQUENCY_SWITCH.
Note 5: VOUTn (DC) and line and load regulation tests are performed in
production with digital servo disengaged (MFR_PWM_MODEn[6] = 0b)
and low VOUTn range selected MFR_PWM_MODEn[1] = 1b. The digital
servo control loop is exercised in production (setting MFR_PWM_
MODEn[6] = 1b), but convergence of the output voltage to its final settling
value is not necessarily observed in final test—due to potentially long
time constants involved—and is instead guaranteed by the output voltage
readback accuracy specification. Evaluation in application demonstrates
capability; see the Typical Performance Characteristics section.
Note 6: See output current derating curves for different VIN, VOUT, and TA,
located in the Applications Information section.
Note 7: Even though VOUT0 and VOUT1 are specified for 6V absolute
maximum, the maximum recommended command voltage to regulate
output channels 0 and 1 is 3.6V with VOUT range-setting bit is set using
the MFR_PWM_MODEn[1] = 0b.
Note 8: Minimum on-time is tested at wafer sort.
Note 9: The data conversion is done by default in round robin fashion. All
inputs signals are continuously converted for a typical latency of 90ms.
Setting MFR_ADC_CONTRL value to be 0 to 12, LTM4680 can do fast
data conversion with only 8ms to 10ms. See section PMBus Command
for details.
Note 10: The following telemetry parameters are formatted in PMBusdefined “Linear Data Format”, in which each register contains a word
comprised of 5 most significant bits—representing a signed exponent, to
be raised to the power of 2—and 11 least significant bits—representing
a signed mantissa: input voltage (on SVIN), accessed via the READ_VIN
command code; output currents (IOUTn), accessed via the READ_IOUTn
command codes; module input current (IVIN0 + IVIN1 + ISVIN), accessed via
the READ_IIN command code; channel input currents (IVINn + 1/2 • ISVIN),
accessed via the MFR_READ_IINn command codes;and duty cycles of
channel 0 and channel 1 switching power stages, accessed via the
READ_DUTY_CYCLEn command codes. This data format limits the
resolution of telemetry readback data to 10 bits even though the internal
ADC is 16 bits and the LTM4680’s internal calculations use 32-bit words.
37
31
25
19
12
6
0
0
5
10
15
20
CODE
25
30
35
4680 F01
Figure 1. Programmable RCOMP
Rev. B
For more information www.analog.com
11
LTM4680
TYPICAL PERFORMANCE CHARACTERISTICS
100
100
95
95
90
90
EFFICIENCY (%)
EFFICIENCY (%)
Single Channel Efficiency,
5VIN, VIN = SVIN = EXTVCC = 5V
CCM Mode
85
80
0.9V, 250kHz
1.0V, 250kHz
1.2V, 350kHz
1.5V, 425kHz
1.8V, 500kHz
2.5V, 575kHz
3.3V, 650kHz
75
70
65
0
5
10
15
20
LOAD CURRENT (A)
25
TA = 25°C.
Single Channel Efficiency,
8VIN, VIN = SVIN = 8V,
EXTVCC = 5V, CCM Mode
85
80
0.9V, 250kHz
1.0V, 250kHz
1.2V, 350kHz
1.5V, 425kHz
1.8V, 500kHz
2.5V, 575kHz
3.3V, 650kHz
75
70
65
30
0
5
10
15
20
LOAD CURRENT (A)
25
4680 G01
4680 G02
Dual Channel Single Output
Efficiency, 12VIN, VIN = SVIN = 12V,
EXTVCC = 5V, VOUT0 and VOUT1
Paralleled CCM Mode
100
100
95
95
90
90
EFFICIENCY (%)
EFFICIENCY (%)
Single Channel Efficiency,
12VIN, VIN = SVIN = 12V,
EXTVCC = 5V CCM Mode
85
80
0.9V, 250kHz
1.0V, 250kHz
1.2V, 350kHz
1.5V, 425kHz
1.8V, 500kHz
2.5V, 575kHz
3.3V, 650kHz
75
70
65
0
5
10
15
20
LOAD CURRENT (A)
25
85
80
0.9V, 250kHz
1.0V, 250kHz
1.2V, 350kHz
1.5V, 425kHz
2.5V, 575kHz
3.3V, 650kHz
75
70
30
65
0
4680 G03
12
30
10
20
30
40
LOAD CURRENT (A)
50
60
4680 G04
Rev. B
For more information www.analog.com
LTM4680
TYPICAL PERFORMANCE CHARACTERISTICS
Single Channel Load Transient
Response 50% (15A) to 100% (30A)
Load Step, 15A/µs VIN = 12V,
VOUT = 0.9V, fSW = 250kHz
TA = 25°C, unless otherwise noted.
Single Channel Load Transient
Response 50% (15A) to 100% (30A)
Load Step, 15A/µs VIN = 12V,
VOUT = 1.2V, fSW = 350kHz
Single Channel Load Transient
Response 50% (15A) to 100% (30A)
Load Step, 15A/µs VIN = 12V,
VOUT = 1.8V, fSW = 500kHz
50mV/DIV
50mV/DIV
50mV/DIV
LOAD STEP
10A/DIV
LOAD STEP
10A/DIV
LOAD STEP
10A/DIV
4680 G06
100µs/DIV
FIGURE 46 CIRCUIT, 12V TO 1.2V, FREQ = 350kHz
COUT = 470µF ×2 POSCAP, 100µF ×4 CERAMIC
RCOMP = 17k, EA-GM = 3.69ms,
COMPna = 3.3nF, COMPnb = 68pF
ILIM LOW, VOUT RANGE LOW
4680 G05
100µs/DIV
FIGURE 46 CIRCUIT, 12V TO 0.9V, FREQ = 250kHz
COUT = 470µF ×3 POSCAP, 100µF ×4 CERAMIC
RCOMP = 17k, EA-GM = 3.69ms,
COMPna = 3.3nF, COMPnb = 68pF
ILIM LOW, VOUT RANGE LOW
Single Channel Load Transient
Response 50% (15A) to 100% (30A)
Load Step, 15A/µs VIN = 12V,
VOUT = 2.5V, fSW = 575kHz
Single Channel Load Transient
Response 50% (15A) to 100% (30A)
Load Step, 15A/µs VIN = 12V,
VOUT = 3.3V, fSW = 650kHz
Dual Output Concurrent Rail,
Start-Up/Shut Down
VOUT1, 1.8V
500mV/DIV
100mV/DIV
50mV/DIV
4680 G07
100µs/DIV
FIGURE 46 CIRCUIT, 12V TO 1.8V, FREQ = 500kHz
COUT = 470µF ×2 POSCAP, 100µF ×4 CERAMIC
RCOMP = 17k, EA-GM = 3.69ms,
COMPna = 3.3nF, COMPnb = 68pF
ILIM LOW, VOUT RANGE LOW
VOUT0, 1V
500mV/DIV
IOUT0, 18A
5A/DIV
LOAD STEP
10A/DIV
LOAD STEP
10A/DIV
RUN0, RUN1
4680 G08
100µs/DIV
FIGURE 46 CIRCUIT, 12V TO 2.5V, FREQ = 575kHz
COUT = 470µF ×2 POSCAP, 100µF ×4 CERAMIC
RCOMP = 20k, EA-GM = 1.68ms,
COMPna = 3.3nF, COMPnb = 68pF
ILIM LOW, VOUT RANGE LOW
4680 G09
100µs/DIV
FIGURE 46 CIRCUIT, 12V TO 3.3V, FREQ = 650kHz
COUT = 470µF ×2 POSCAP, 100µF ×4 CERAMIC
RCOMP = 20k, EA-Gm = 3.02ms,
COMPna = 3.3nF, COMPnb = 68pF
ILIM LOW, VOUT RANGE HIGH
Dual Output Concurrent Rail,
Start-Up/Shut Down, Pre-Bias
Single Phase Single Output
Short-Circuit Protection, No Load
VOUT1, 1.8V
500mV/DIV
2V/DIV
4680 G10
2ms/DIV
FIGURE 46 CIRCUIT, 12VIN, 30A LOAD ON VOUT0,
NO LOAD ON VOUT1
TON_DELAY0 = 0ms
TON_DELAY1 = 0ms
TON_RISE0 = 3ms
TON_RISE1 = 5.297ms
TOFF_DELAY0 = 2.43ms TOFF_DELAY1 = 0ms
TOFF_FALL0 = 3ms
TOFF_FALL1 = 5.328ms
ON_OFF CONFIGn = 0X1E
Single Phase Single Output
Short-Circuit Protection, 30A Load
VOUT0
500mV/DIV
VOUT0
500mV/DIV
IIN
2A/DIV
IIN
2A/DIV
VOUT0, 1V
500mV/DIV
IOUT0, 30A
10A/DIV
RUN0, RUN1
2V/DIV
4680 G11
2ms/DIV
FIGURE 46 CIRCUIT, 12VIN, 30A LOAD ON VOUT0,
NO LOAD ON VOUT1, VOUT1 IS PRE-BIASED TO
500mV THROUGH A DIODE
TON_DELAY0 = 0ms
TON_DELAY1 = 0ms
TON_RISE0 = 3ms
TON_RISE1 = 5.297ms
TOFF_DELAY0 = 2.43ms TOFF_DELAY1 = 0ms
TOFF_FALL0 = 3ms
TOFF_FALL1 = 5.328ms
ON_OFF CONFIGn = 0X1E
4680 G12
20µs/DIV
FIGURE 46 CIRCUIT, 12VIN, NO LOAD ON VOUT0
PRIOR TO APPLICATION OF SHORT-CIRCUIT
USE HIGH RANGE OF I LIMIT SYSTEM
SHORT-CIRCUIT USING LOW IMPEDANCE
COPPER ACROSS OUTPUT (HARD SHORT)
4680 G13
20µs/DIV
FIGURE 46 CIRCUIT, 12VIN, 30A LOAD ON VOUT0
PRIOR TO APPLICATION OF SHORT-CIRCUIT
USE HIGH RANGE OF I LIMIT SYSTEM
SHORT-CIRCUIT USING LOW IMPEDANCE
COPPER ACROSS OUTPUT (HARD SHORT)
Rev. B
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13
LTM4680
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs Load Current
Comparison, RSENSE = 3mΩ,
12V to 1.8VOUT, 500kHz
14
6
5
4
3
2
RSENSE
READBACK
4
RSENSE
READBACK
1
0
70
0
10
20
40
30
50
LOAD CURRENT (A)
60
READ_IOUT of 16 LTM4680
Channels 12VIN, 1VOUT, TJ = 25°C,
IOUTn = 30A, System Having
Reached Thermally Steady-State
Condition, No Airflow
3
3
30.6
30.3
30.3
30.3
30.2
30.2
30.1
30.0
30.0
29.9
0
29.9
1
READ_IOUT CHANNEL READBACK (A)
4680 G17
14
60
4680 G18
70
2
1
0
30.1
2
29.8
30.4
30.4
30.5
30.6
30.7
30.7
30.8
30.8
30.9
30.9
31.0
31.0
31.2
READ_IOUT CHANNEL READBACK (A)
NUMBER OF CHANNELS
3
NUMBER OF CHANNELS
4
0
20
40
30
50
LOAD CURRENT (A)
READ_IOUT of 16 LTM4680
Channels 12VIN, 1VOUT, TJ = 125°C,
IOUTn = 30A, System Having
Reached Thermally Steady-State
Condition, No Airflow
4
1
10
4680 G16
4
2
0
4680 G15
READ_IOUT of 16 LTM4680
Channels 12VIN, 1VOUT, TJ = –40°C,
IOUTn = 30A, System Having
Reached Thermally Steady-State
Condition, No Airflow
NUMBER OF CHANNELS
0
70
30.1
4680 G14
RSENSE
READBACK
2
30.0
60
6
29.9
30
50
20
40
LOAD CURRENT (A)
8
29.9
10
10
29.8
0
12
29.8
1
0
16
7
29.7
2
18
8
29.6
3
9
29.4
4
20
30.3
INPUT CURRENT (A)
INPUT CURRENT (A)
5
10
INPUT CURRENT (A)
6
Supply Current vs Load Current
Comparison, RSENSE = 3mΩ,
12V to 3.3VOUT, 650kHz
30.2
Supply Current vs Load Current
Comparison, RSENSE = 3mΩ,
12V to 1.0VOUT, 250kHz
TA = 25°C, 12VIN to 1VOUT, unless otherwise noted.
READ_IOUT CHANNEL READBACK (A)
4680 G19
Rev. B
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LTM4680
PIN FUNCTIONS
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
GND (A3-A6, B1, B3-B6, C1-C6, D2-D6, E5-E6, F5-F7,
G5-G8, H5-H8, J2-J6, K2-6, L1, L3-L6, M3-M6): Power
Ground of the LTM4680. Power return for VOUT0 and
VOUT1. Return input and output capacitors to this point .
VOUT0 (K7-K11, L7-L12, M7-M10): Channel 0 Output
Voltage. Place recommended output capacitors from this
shape to GND. See recommended layout.
VOSNS0+ (M11): Channel 0 Positive Differential Voltage
Sense Input. Together, VOSNS0+ and VOSNS0– serve to
kelvin-sense the VOUT0 output voltage at VOUT0’s point
of load (POL) and provide the differential feedback signal
directly to channel 0’s feedback loop. Command VOUT0’s
target regulation voltage by serial bus. Its initial command
value at SVIN power-up is dictated by NVM (non-volatile
memory) contents (factory default: 1.000V)—or, optionally, may be set by configuration resistors; see VOUT0_
CFG and the Applications Information section.
VOSNS0– (M12): Channel 0 Negative Differential Voltage
Sense Input. See VOSNS0+.
VOUT1 (A7-A10, B7-B12, C7-C9, D7): Channel 1 Output
Voltage. Place recommended output capacitors from this
shape to GND See recommended layout.
VOSNS1+ (A11): Channel 1 Positive Differential Voltage
Sense Input. Together, VOSNS1+ and VOSNS1– serve to
kelvin-sense the VOUT1 output voltage at VOUT1’s point
of load (POL) and provide the differential feedback signal
directly to channel 1’s feedback loop. Command VOUT1’s
target regulation voltage by serial bus. Its initial command
value at SVIN power-up is dictated by NVM (non-volatile
memory) contents (factory default: 1.000V)—or, optionally, may be set by configuration resistors; see VOUT1_
CFG and the Applications Information section.
VOSNS1– (A12): Channel 1 Negative Differential Voltage
Sense Input. See VOSNS1+.
SGND (F9-10, G9-10): SGND is the signal ground return
path of the LTM4680. SGND is not internally connected to
GND. Connect SGND to GND local to the LTM4680. See
recommended layout.
VIN0 (G1-G4, H1-H4): Positive Power Input to Channel
0 Switching Stage. Provide sufficient decoupling capacitance in the form of multilayer ceramic capacitors (MLCCs)
and low ESR electrolytic (or equivalent) to handle reflected
input current ripple from the step-down switching stage.
MLCCs should be placed as close to the LTM4680 as
physically possible. See Layout Recommendations in the
Applications Information section.
VIN1 (E1-E4, F1-F4): Positive Power Input to Channel 1
Switching Stage. Provide sufficient decoupling capacitance in the form of MLCCs and low ESR electrolytic (or
equivalent) to handle reflected input current ripple from
the step-down switching stage. MLCCs should be placed
as close to the LTM4680 as physically possible. See
Layout Recommendations in the Applications Information
section.
SW0 (L2, M1-M2): Switching Node of Channel 0 StepDown Converter Stage. Used for test purposes or EMIsnubbing. May be routed a short distance to a local test
point to monitor switching action of channel 0, if desired,
but do not route near any sensitive signals; otherwise,
leave electrically isolated (open).
SW1 (A1-A2, B2): Switching Node of Channel 1 StepDown Converter Stage. Used for test purposes or EMIsnubbing. May be routed a short distance to a local test
point to monitor switching action of channel 1, if desired,
but do not route near any sensitive signals; otherwise,
leave open.
SVIN (D1): Input Supply for LTM4680’s Internal Control IC.
In most applications, SVIN connects to VIN0 and/or VIN1.
SVIN can be operated from an auxiliary supply separate
from VIN0/VIN1 for powering the VIN0/VIN1 from a lower
supply like 3.3V. The SVIN pin has an onboard 1Ω and 1µF
decoupling capacitor. The 1Ω resistor is used to measure
the actual control chip current. See MFR_READ_ICHIP
Rev. B
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15
LTM4680
PIN FUNCTIONS
and MFR_ADC_CONTROL COMMAND section. When
operating from 4.5V to 5.75V with no auxiliary bias supply, then the main input supply should connect to SVIN
and INTVCC. See Test Circuit 2 for an example. In this
configuration, the ICHIP current will not be relevant since
INTVCC is connected to SVIN.
VDD25 (D12): Internally Generated 2.5V Power Supply
Output Pin. Do not load this pin with external current;
it is used strictly to bias internal logic and provides current for the internal pull-up resistors connected to the
configuration-programming pins. No external decoupling
is required.
IIN+ (J1): Positive Current Sense Amplifier Input. If the
input current sense amplifier is not used, this pin must
be shorted to the IIN– and SVIN pin. See Operation section
for detail about the input current sensing.
ASEL (F12): Serial Bus Address Configuration Pin. On
any given I2C/SMBus serial bus segment, every device
must have its own unique slave address. If this pin is left
open, the LTM4680 powers up to its default slave address
of 0x4F (hexadecimal), i.e., 1001111b (industry-standard
convention is used throughout this document: 7-bit slave
addressing). The lower four bits of the LTM4680’s slave
address can be altered from this default value by connecting a resistor from this pin to SGND. Minimize capacitance—especially when the pin is left open—to assure
accurate detection of the pin state. See Table 4.
IIN– (K1): Negative Current Sense Amplifier Input. If the
input current sense amplifier is not used, this pin must
be shorted to the IIN+ and SVIN pin. See Operation section
for detail about the input current sensing.
EXTVCC (F8): External Power Input to an Internal Switch
Connected to INTVCC. This switch closes and supplies
the IC power, bypassing the internal regulator whenever
EXTVCC is higher than 4.7V and VIN is higher than 7V.
EXTVCC also powers up VDD33 when EXTVCC is higher than
4.7V and INTVCC is lower than 3.8V. Do not exceed 6V
on this pin. Decouple this pin to PGND with a minimum
of 4.7µF low ESR tantalum or ceramic capacitor. If the
EXTVCC pin is not used to power INTVCC, the EXTVCC pin
must be tied GND.
INTVCC (E7) : Internal Regulator, 5.5V Output. When
operating the LTM4680 from 5.75V ≤ SVIN ≤ 16V, an
LDO generates INTVCC from SVIN to bias internal control
circuits and the MOSFET drivers of the LTM4680. An
external 2.2µF ceramic decoupling is required. INTVCC is
regulated regardless of the RUNn pin state. When operating the LTM4680 with 4.5V ≤ SVIN < 5.75V, INTVCC must
be electrically shorted to SVIN.
VDD33 (E8): Internally Generated 3.3V Power Supply
Output Pin. This pin should only be used to provide external current for the pull-up resistors required for FAULTn,
SHARE_CLK, and SYNC, and may be used to provide
external current for pull-up resistors on RUNn, SDA, SCL,
ALERT and PGOODn. No external decoupling is required.
16
FSWPH_CFG (E9): Switching Frequency, Channel
Phase-Interleaving Angle and Phase Relationship to
SYNC Configuration Pin. If this pin is left open—or, if the
LTM4680 is configured to ignore pin-strap (RCONFIG)
resistors, i.e., MFR_CONFIG_ALL[6] = 1b—then
LTM4680’s switching frequency (FREQUENCY_SWITCH)
and channel phase relationships (with respect to the SYNC
clock; MFR_PWM_CONFIG[2:0]) are dictated at SVIN
power-up according to the LTM4680’s NVM contents.
Default factory values are: 575kHz operation; channel 0
at 0°; and channel 1 at 180°C (convention throughout
this document: a phase angle of 0° means the channel’s switch node rises coincident with the falling edge
of the SYNC pulse). Connecting a resistor from this pin
to SGND (and using the factory-default NVM setting of
MFR_CONFIG_ALL[6] = 0b) allows a convenient way to
configure multiple LTM4680s with identical NVM contents
for different switching frequencies of operation and phase
interleaving angle settings of intra- and extra-moduleparalleled channels—all, without GUI intervention or the
need to “custom pre-program” module NVM contents.
(See the Operation section.) Minimize capacitance—especially when the pin is left open—to assure accurate detection of the pin state. See Table 3.
Rev. B
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LTM4680
PIN FUNCTIONS
VOUT0_CFG (E11): Output Voltage Select Pin for VOUT0,
Coarse Setting. If the VOUT0_CFG and VTRIM0_CFG pins
are both left open—or, if the LTM4680 is configured to
ignore pin-strap (RCONFIG) resistors, i.e., MFR_CONFIG_
ALL[6] = 1b—then the LTM4680s target VOUT0 output
voltage setting (VOUT_COMMAND0) and associated
power-good and OV/UV warning and fault thresholds are
dictated at SVIN power-up according to the LTM4680’s
NVM contents. A resistor connected from this pin to
SGND—in combination with resistor pin settings on
VTRIM0_CFG, and using the factory-default NVM setting
of MFR_CONFIG_ALL[6] = 0b—can be used to configure the LTM4680’s channel 0 output to power-up to a
VOUT_COMMAND value (and associated output voltage
monitoring and protection/fault-detection thresholds)
different from those of NVM contents. (See Table 1 in
the Operation section.) Connecting resistor(s) from
VOUT0_CFG to SGND and/or VTRIM0_CFG to SGND in
this manner allows a convenient way to configure multiple LTM4680s with identical NVM contents for different
output voltage settings all without GUI intervention or
the need to “custom-preprogram” module NVM contents.
Minimize capacitance especially when the pin is left open
to assure accurate detection of the pin state. Note that use
of RCONFIGs on VOUT0_CFG/VTRIM0_CFG can affect the
VOUT0 range setting (MFR_PWM_MODE0[1]) and loop
gain.
VTRIM1_CFG (E10): Output Voltage Select Pin for VOUT1,
Fine Setting. Works in combination with VOUT1_CFG to
affect the VOUT_COMMAND (and associated output voltage monitoring and protection/fault-detection thresholds)
of channel 1, at SVIN power-up. (See VOUT1_CFG and
the Operation section.) Minimize capacitance especially
when the pin is left open to assure accurate detection of
the pin state. Note that use of RCONFIGs on VOUT1_CFG/
VTRIM1_CFG can affect the VOUT1 range setting (MFR_
PWM_MODE1[1]) and loop gain.
VOUT1_CFG (E12): Output Voltage Select Pin for VOUT1,
Coarse Setting. If the VOUT1_CFG and VTRIM1_CFG
pins are both left open or, if the LTM4680 is configured to ignore pin-strap (RCONFIG) resistors, i.e.,
MFR_CONFIG_ALL[6] = 1b then the LTM4680’s target
VOUT1 output voltage setting (VOUT_COMMAND1) and
associated OV/UV warning and fault thresholds are dictated at SVIN power-up according to the LTM4680’s NVM
contents, in precisely the same fashion that the VOUT1_
CFG and VTRIM1_CFG pins affect the respective settings
of VOUT1/channel 1. (See VOUT1_CFG, VTRIM1_CFG and
the Operation section.) Minimize capacitance—especially
when the pin is left open—to assure accurate detection of
the pin state. Note that use of RCONFIGs on VOUT1_CFG/
VTRIM1_CFG can affect the VOUT1 range setting (MFR_
PWM_MODE1[1]) and loop gain.
VTRIM0_CFG (C12): Output Voltage Select Pin for VOUT0,
Fine Setting. Works in combination with VOUT0_CFG to
affect the VOUT_COMMAND (and associated output voltage monitoring and protection/fault-detection thresholds)
of channel 0, at SVIN power-up. (See VOUT0_CFG and
the Operation section.) Minimize capacitance—especially
when the pin is left open—to assure accurate detection of
the pin state. Note that use of RCONFIGs on VOUT0_CFG/
VTRIM0_CFG can affect the VOUT0 range setting (MFR_
PWM_MODE0[1]) and loop gain.
RUN0, RUN1 (G12, F11 Respectively): Enable Run Input
for Channels 0 and 1, Respectively. Open-drain input and
output. Logic high on these pins enables the respective
outputs of the LTM4680. These open-drain output pins
hold the pin low until the LTM4680 is out of reset and SVIN
is detected to exceed VIN_ON. A pull-up resistor to 3.3V is
required in the application. The LTM4680 pulls RUN0 and/
or RUN1 low, as appropriate, when a global fault and/or
channel-specific fault occurs whose fault response is
configured to latch off and cease regulation; issuing a
CLEAR_FAULTS command via I2C or power-cycling SVIN
is necessary to restart the module, in such cases. Do not
pull RUN logic high with a low impedance source.
PGOOD0/PGOOD1 (J7/D9): Power Good Indicator
Outputs. Open-drain logic output that is pulled to ground
when the output exceeds the UV and OV regulation window. The output is deglitch by an internal 100µs filter. A
pull-up resistor to 3.3V is required in the application.
Rev. B
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17
LTM4680
PIN FUNCTIONS
FAULT0/FAULT1 (H12/G11): Digital Programmable Fault
Inputs and Outputs. Open-drain output. A pull-up resistor
to 3.3V is required in the application.
COMP0b/COMP1b (H9/C10): Current Control Threshold
and Error Amplifier Compensation Nodes. Each associated channel’s current comparator tripping threshold
increases with its compensation voltage. Each channel
has a 6.8pF to SGND.
COMP0a/COMP1a (J9/D10): Loop Compensation Nodes.
The internal PWM loop compensation resistors RCOMPn
of the LTM4680 can be adjusted using bit[4:0] of the
MFR_PWM_COMP command. The transconductance of
the LTM4680 PWM error amplifier can be adjusted using
bit[7:5] of the MFR_PWM_COMP command. These two
loop compensation parameters can be programmed when
device is in operation. Refer to the Programmable Loop
Compensation subsection in the Applications Information
section for further details. See Figure 1.
SYNC (K12): External Clock Synchronization Input and
Open-Drain Output Pin. If an external clock is present at
this pin, the switching frequency will be synchronized to
the external clock. If clock master mode is enabled, this
pin will pull low at the switching frequency with a 500ns
pulse to ground. A resistor pull-up to 3.3V is required in
the application if the LTM4680 is the master.
SCL (J12): Serial Bus Clock Open-Drain Input (Can Be
an Input and Output, if Clock Stretching is Enabled). A
pull-up resistor to 3.3V is required in the application for
digital communication to the SMBus master(s) that nominally drive this clock. The LTM4680 will never encounter
scenarios where it would need to engage clock stretching
unless SCL communication speeds exceed 100kHz—and
even then, LTM4680 will not clock stretch unless clock
stretching is enabled by means of setting MFR_CONFIG_
ALL[1] = 1b. The factory-default NVM configuration setting has MFR_CONFIG_ALL[1] = 0b: clock stretching
disabled. If communication on the bus at clock speeds
above 100kHz is required, the user’s SMBus master(s)
needs to implement clock stretching support to assure
18
solid serial bus communications, and only then should
MFR_CONFIG_ALL[1] be set to 1b. When clock stretching is enabled, SCL becomes a bidirectional, open-drain
output pin on LTM4680.
SDA (H10): Serial Bus Data Open-Drain Input and Output.
A pull-up resistor to 3.3V is required in the application.
ALERT (H11): Open-Drain Digital Output. A pull-up resistor to 3.3V is required in the application only if SMBALERT
interrupt detection is implemented in one’s SMBus
system.
SHARE_CLK (D11): Share Clock, Bidirectional Open-Drain
Clock Sharing Pin. Nominally 100kHz. Used for synchronizing the time base between multiple LTM4680s (and any
other Analog Devices devices with a SHARE_ CLK pin)—
to realize well-defined rail sequencing and rail tracking.
Tie the SHARE_CLK pins of all such devices together; all
devices with a SHARE_CLK pin will synchronize to the
fastest clock. A pull-up resistor to 3.3V is only required
when synchronizing the time base between devices.
TSNS0a, TSNS0b (J11 and J8, Respectively): Channel 0
Temperature Excitation/Measurement and Thermal
Sensor Pins, Respectively. Connect TSNS0a to TSNS0b.
This allows the LTM4680 to monitor the power stage temperature of channel 0.
TSNS1a, TSNS1b (J10 and D8, Respectively): Channel 1
Temperature Excitation/Measurement and Thermal
Sensor Pins, Respectively. In most applications, connect
TSNS1a to TSNS1b. This allows the LTM4680 to monitor the power stage temperature of channel 1. See the
Operation section for information on how to use TSNS1a
to monitor an external temperature sensor.
WP (C11): Write Protect Pin, Active High. An internal 10µA current source pulls this pin to VDD33. If WP
is open circuit or logic high, only I2C writes to PAGE,
OPERATION, CLEAR_FAULTS, MFR_CLEAR_PEAKS and
MFR_EE_UNLOCK are supported. Additionally, Individual
faults can be cleared by writing 1b’s to bits of interest in
registers prefixed with “STATUS”. If WP is low, I2C writes
are unrestricted.
Rev. B
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LTM4680
SIMPLIFIED BLOCK DIAGRAM
+
RSENSE
CIN2
CIN1
2.2µF
IN+
IN–
SVIN
VIN0
+
–
1Ω
VOUT0 ADJ
TO 3.3V
UP TO 30A
COUT2
INTVCC
EXTVCC
VDD33
SW1
MT1
330nH
VOUT0
GND
1µF
INPUT CURRENT/ICHIP (READ_IIN,
MFR_READ_IIN_PEAK TO ANALOG
READBACK)
MT0
COUT1
VIN1
2.2µF
2.2µF
1µF
A=N
SW0
1µF
330nH
POWER CONTROL
ANALOG SECTION
2.2µF
MB0
2.2µF
GND
MB1
0.01µF
DIE TEMP SENSE
TSNS0b
0.01µF
TSNS0
IOUT0 CURRENT SENSE
TSNS0a
TO ANALOG
READBACK
TO ANALOG
READBACK
CLOAD0
TSNS1b
TSNS1a
TEMP MUX
VOSNS0–
X1
PROG GM
COMP0a
CCOMPL
+
–
10:1 MUX
EA0
6.8pF
X1
ALL ANALOG
READBACK SIGNALS
COMP0b
CCOMPH
VOSNS1+
+
REMOTE SENSE
PROG RCOMP
+
EA1
–
PROG GM
–
REMOTE SENSE
VOSNS1–
6.8pF
PROG RCOMP
ADC
PGOOD1
PGOOD0
SYNC
SCL
CCOMPH
COMP1a
SPI SLAVE
2.5V
SDA
CCOMPL
3.3V
TOLERANT PULL-UP
NOT SHOWN
VDD25
2.2µF
ALERT
WP
ROM
RUN0
RAM
SPI MASTER
DIGITAL ENGINE
RUN1
FAULT0
3.3V-TOLERANT
PULL-UP NOT
SHOWN
LOAD1
CLOAD1
COMP1b
POWER CONTROL DIGITAL SECTION
5.5V-TOLERANT
PULL-UP NOT
SHOWN
COUT4
COUT3
SGND
TSNS1
IOUT0 CURRENT SENSE
VOSNS0+
LOAD0
VOUT1 ADJ
TO 3.3V
UP TO 30A
VOUT1
SYNC DRIVER
ASEL
FSWPH_ CFG
32MHz OSC
VTRIM0_ CFG
VTRIM1_ CFG
EEPROM
FAULT1
VOUT0_CFG
SHARE_CLK
VOUT1_CFG
CONFIG RESISTORS
TO 2.5V SGND NOT SHOWN
4680 F02
Figure 2. Simplified LTM4680 Block Diagram
DECOUPLING REQUIREMENTS
TA = 25°C. Using Test Circuit 1 configuration.
SYMBOL
PARAMETER
CONDITIONS
CINH
External High Frequency Input Capacitor Requirement
(5.75V ≤ VIN ≤ 16V, VOUTn Commanded to 1.000V)
IOUT0 = 30A
IOUT1 = 30A
MIN
TYP
100
100
MAX
UNITS
µF
µF
COUTn
External High Frequency Output Capacitor Requirement
(5.75V ≤ VIN ≤ 16V, VOUTn Commanded to 1.000V)
IOUT0 = 30A
IOUT1 = 30A
800
800
µF
µF
Rev. B
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19
COUT2
COUT1
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CCOMPL
3.3V-TOLERANT
PULL-UP NOT
SHOWN
5.5V-TOLERANT
PULL-UP NOT
SHOWN
CCOMPH
CLOAD0
(VOUT0 TELEMETRY:
READ_VOUT0,
MFR_VOUT_PEAK,
READ_VOUT0)
LOAD0
VOUT0
ADJ
TO 3.6V
UP TO
30A
CSNUB0
RSNUB0
OPTIONAL
SNUBBER
X1
TSNS0
IOUT0 SENSE
MB0
PROG RCOMP
PROG GM
MFR_PWM_COMP
CHANNEL TIMING
MANAGEMENT
VDD33
I2C-BASED SMBus
INTERFACE WITH PMBus
COMMANDS (10kHZ
TO 400kHz COMPATIBLE)
UVLO
2µA
VBE SENSING
ROM
PROGRAM
RAM
2.2µF
INTVCC
EXTVCC
TEMP MUX
DIE TEMP SENSE
READ_TEMPERATURE0
32µA
EEPROM
1µF
SYNC DRIVER
+
EA1
–
DCR SENSE Z
330nH
CONFIG
DETECT
VDD33
X1
2.5V
ASEL
2.2µF
VDD25
SYNC
PGOOD1
COMP1a
6.8pF
COMP1b
VOSNS1–
VOSNS1+
TSNS1a
TSNS1b
SGND
GND
2.2µF
VOUT1
SW1
4680 F03
VOUT1_CFG
VOUT0_CFG
VTRIM1_ CFG
VTRIM0_ CFG
FSWPH_ CFG
14.3k
×6
REMOTE SENSE
TSNS1
PROG RCOMP
–
+
0.01µF
READ_TEMPERATURE1
CHANNEL 1 TEMP
(IOUT1 TELEMETRY:
READ_IOUT1,
MFR_IOUT_PEAK)
(MFR_PWM_MODE, MFR_PWM_CONFIG,
FREQUENCY_SWITCH)
PROG GM
MFR_PWM_COMP
CCM CH1 I SIGNAL
32MHz OSC
SETPOINT,
UV, OV, ILIM
DACs
SINC3
SPI MASTER
SPI SLAVE
ADC
10:1 MUX
MB1
MT1
VIN1
IOUT1 SENSE
2.2µF
VDD33
(CURRENT MODE PWM CNTL LOOPS,
POWER CONTROL ANALOG SECTION
LINEAR REGULATORS, DACs, ADC,
UV/OV MONITORS, VCO/PLL, MOSFET
DRIVERS AND POWER CNTL LOGIC)
DIGITAL ENGINE, MAIN CONTROL
VDD33
COMPARE
+
–
EA0
DCR SENSE Z
CCM CH0 I SIGNAL
330nH
POWER MANAGEMENT DIGITAL SECTION
6.8pF
REMOTE SENSE
SHARE_CLK
FAULT1
FAULT0
RUN1
RUN0
10µA
WP
ALERT
SDA
SCL
PGOOD0
COMP0a
COMP0b
VOSNS0–
VOSNS0+
TSNS0a
0.01µF
READ_TEMPERATURE1
CHANNEL 0 TEMP
2.2µF
(IOUT0 TELEMETRY:
READ_IOUT0,
MFR_IOUT_PEAK)
MT0
1µF SVIN TELEMETRY:
(MFR_READ_ICHIP,
READ_VIN, READ_VIN_PEAK)
INPUT CURRENT/ICHIP
(READIIN, MFRREADIINPEAK TO
ANALOG READBACK)
(MFR_PWM_MODE, MFR_PWM_CONFIG,
FREQUENCY_SWITCH)
TSNS0b
GND
VOUT0
SW0
A=N
IIN
1µF
VIN0
VIN
SVIN
1Ω
ICHIP
IN–
VOUT1
IN+
2.2µF
VOUT2
CIN2
IOUT1
CIN1
IOUT2
RSENSE
PWM0
+
TEMP
20
–
PWM1
+
CCOMPH
CONFIG RESISTORS
TO SGND NOT SHOWN
3.3V
TOLERANT PULL-UP
NOT SHOWN
CCOMPL
CLOAD1
LOAD1
VOUT1
ADJ
COUT4 TO 3.6V
UP TO
30A
CSNUB1
RSNUB1
(VOUT0 TELEMETRY:
READ_VOUT0,
MFR_VOUT_PEAK,
READ_POUT1)
COUT3
OPTIONAL
SNUBBER
LTM4680
FUNCTIONAL DIAGRAM
Figure 3. Functional LTM4680 Block Diagram
Rev. B
LTM4680
TEST CIRCUITS
Test Circuit 1. LTM4680 ATE High VIN Operating Range Configuration, 5.75V ≤ VIN ≤ 16V
150µF
TSNS1b
TSNS1a
TSNS0b
TSNS0a
PGOOD1
INTVCC
PGOOD0
5.75V TO 16V
EXTVCC
VIN
VDD25
VDD33
2.2µF
IN+
RSENSE
VOSNS0+
IN–
22µF
×5
–
VIN1
RUN1
VOSNS1+
LTM4680
RUN0
–
VOSNS1
FAULT0
FAULT1
SCL
SYNC
SDA
ALERT
SHARE_CLK
2200pF
COUT0* BULK
LOAD1
100µF
×4
VOUT1
1V, ADJUSTABLE
UP TO 3.6V AT 30A
COUT1* BULK
I2C/SMBus I/F WITH PMBus COMMAND SET
TO/FROM IPMI OR OTHER BOARD
MANAGEMENT CONTROLLER
*COUT0 AND COUT1 ARE
OPTIONAL FOR ATE TEST
(PULL-UP RESISTORS ON DIGITAL
I/O PINS NOT SHOWN)
4680 TC01
2200pF
100pF
SGND
ASEL
FSWPH_CFG
VOUT1_CFG
VOUT0_CFG
VTRIM0_CFG
COMP0b
VTRIM1_CFG
GND
WP
COMP0a
SYNCHRONIZATION
TIME-BASE
REGISTER WRITE
PROTECTION
VOUT1
COMP1b
FAULT INTERRUPTS
100µF
×4
VOUT0
1V, ADJUSTABLE
UP TO 3.6V AT 30A
SW1
SVIN
COMP1a
ON/OFF CONTROL
LOAD0
VOSNS0
VIN0
SVIN
SW0
VOUT0
100pF
Rev. B
For more information www.analog.com
21
LTM4680
TEST CIRCUITS
Test Circuit 2. LTM4680 ATE Low VIN Operating Range Configuration, 4.5V ≤ VIN ≤ 5.75V
1Ω
SVIN
TSNS1b
TSNS1a
TSNS0b
TSNS0a
PGOOD1
VOSNS0–
VIN0
SW1
SVIN
VOUT1
RUN1
–
VOSNS1
FAULT0
FAULT1
SCL
SYNC
SDA
ALERT
SHARE_CLK
2200pF
FSWPH_CFG
VOUT1_CFG
VOUT0_CFG
VTRIM0_CFG
GND
WP
SGND
LOAD1
100µF
×4
100µF
×4
VOUT0
1V, ADJUSTABLE
UP TO 3.6V AT 30A
COUT0* BULK
VOUT1
1V, ADJUSTABLE
UP TO 3.6V AT 30A
COUT1* BULK
I2C/SMBus I/F WITH PMBus COMMAND SET
TO/FROM IPMI OR OTHER BOARD
MANAGEMENT CONTROLLER
*COUT0 AND COUT1 ARE
OPTIONAL FOR ATE TEST
(PULL-UP RESISTORS ON DIGITAL
I/O PINS NOT SHOWN)
4680 TC02
2200pF
100pF
LOAD0
VOSNS1+
LTM4680
RUN0
COMP1a
SYNCHRONIZATION
TIME-BASE
REGISTER WRITE
PROTECTION
VIN1
VTRIM1_CFG
FAULT INTERRUPTS
VOSNS0+
COMP0b
ON/OFF CONTROL
IN–
COMP0a
SVIN
SW0
VOUT0
RSENSE
22µF
×5
22
EXTVCC
INTVCC
IN+
ASEL
150µF
PGOOD0
4.5V TO 5.75V
COMP1b
VIN
VDD25
VDD33
2.2µF
100pF
Rev. B
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LTM4680
OPERATION
POWER MODULE INTRODUCTION
Programmable Output Voltage
n
The LTM4680 is a highly configurable dual 30A output standalone nonisolated switching mode step-down
DC/DC power supply with built-in EEPROM NVM (nonvolatile memory) with ECC and I2C-based PMBus/ SMBus
2-wire serial communication interface capable of 400kHz
SCL bus speed. Two output voltages can be regulated
(VOUT0, VOUT1—collectively, VOUTn) with a few external input and output capacitors and pull-up resistors.
Readback telemetry data of input and output voltages and
input and output currents, and module temperatures are
continually digitized cyclically by an integrated 16-bit ADC
(analog-to-digital converter). Many fault thresholds and
responses are customizable. Data can be autonomously
saved to EEPROM when a fault occurs, and the resulting fault log can be retrieved over I2C at a later time, for
analysis. See Figures 2 and 3 for Block Diagrams.
Programmable Input Voltage On and Off Threshold
Voltage
n
Programmable Current Limit
n
Programmable Switching Frequency
n
Programmable OV and UV Threshold voltage
n
Programmable ON and Off Delay Times
n
Programmable Output Rise/Fall Times
n
Phase-Locked Loop for Synchronous PolyPhase
Operation (2, 3, 4 or 6 Phases)
n
Nonvolatile Configuration Memory with ECC
n
Optional External Configuration Resistors for Key
Operating Parameters
n
Optional Time Base Interconnect for Synchronization
Between Multiple Controllers
n
POWER MODULE OVERVIEW, MAJOR FEATURES
WP Pin to Protect Internal Configuration
n
Major Features Include:
Stand Along Operation After User Factory
Configuration
n
Dedicated Power Good Indicators
n
Direct Input and Chip Current Sensing
n
PMBus, Version 1.2, 400kHz Compliant Interface
n
Programmable Loop Compensation Parameters
n
TINIT Start-Up Time: 30ms
n
PWM Synchronization Circuit, (See Frequency and
Phasing Section for Details)
n
MFR_ADC_CONTROL for Fast ADC Sampling of One
Parameter (as Fast as 8ms) (See PMBus Command
for Details)
The PMBus interface provides access to important power
management data during system operation including:
Internal Controller Temperature
n
n
n
Fully Differential Output Sensing for Both Channels;
VOUT0/VOUT1 Both Programmable Up to 3.6V
n
Average Output Voltage
n
Average Input Voltage
n
Average Input Current
n
Power-Up and Program EEPROM with EXTVCC
n
Input Voltage Up to 16V
n
n
∆VBE Temperature Sensing
n
SYNC Contention Circuit (Refer to Frequency and
Phase Section for Details)
Fault Logging
n
Average Chip Input Current from VIN
Configurable, Latched and Unlatched Individual Fault
and Warning Status
n
n
Internal Power Channel Temperature Average
Output Current
Individual channels are accessed through the PMBus
using the PAGE command, i.e., PAGE 0 or 1.
Fault reporting and shutdown behavior are fully configurable. Two individual FAULT0, FAULT1 outputs are provided, both of which can be masked independently.
Rev. B
For more information www.analog.com
23
LTM4680
OPERATION
Three dedicated pins for ALERT, PGOOD0/PGOOD1 functions are provided. The shutdown operation also allows
all faults to be individually masked and can be operated
in either unlatched (hiccup) or latched modes.
Individual status commands enable fault reporting over
the serial bus to identify the specific fault event. Fault or
warning detection includes the following:
Output Undervoltage/Overvoltage
n
Input Undervoltage/Overvoltage
n
Input and Output Overcurrent
n
Internal Overtemperature
n
Communication, Memory or Logic (CML) Fault
n
EEPROM WITH ECC
The LTM4680 contains internal EEPROM with ECC (Error
Correction Coding) to store user configuration settings
and fault log information. EEPROM endurance retention and mass write operation time are specified in the
Electrical Characteristics and Absolute Maximum Ratings
sections. Write operations above TJ = 85°C are possible
although the Electrical Characteristics are not guaranteed
and the EEPROM will be degraded. Read operations performed at temperatures between –40°C and 125°C will not
degrade the EEPROM. Writing to the EEPROM above 85°C
will result in a degradation of retention characteristics.
The fault logging function, which is useful in debugging
system problems that may occur at high temperatures,
only writes to fault log EEPROM locations. If occasional
writes to these registers occur above 85°C, the slight degradation in the data retention characteristics of the fault
log will not take away from the usefulness of the function.
It is recommended that the EEPROM not be written when
the die temperature is greater than 85°C. If the die temperature exceeds 130°C, the LTM4680 will disable all
EEPROM write operations. All EEPROM write operations
will be re-enabled when the die temperature drops below
125°C. (The controller will also disable all the switching
when the die temperature exceeds the internal overtemperature fault limit 160°C with a 10°C hysteresis).
24
The degradation in EEPROM retention for temperatures
>125°C can be approximated by calculating the dimensionless acceleration factor using the following equation:
AF = e
⎡⎛ Ea ⎞ ⎛
⎞⎤
1
1
–
⎢⎜⎝ ⎟⎠ •⎜
⎟⎠ ⎥
+273
+273
T
T
k
⎝ USE
STRESS
⎦
⎣
where:
AF = acceleration factor
Ea = activation energy = 1.4eV
k = 8.617 • 10–5 eV/°K
TUSE = 125°C specified junction temperature
TSTRESS = actual junction temperature in °C
Example: Calculate the effect on retention when operating
at a junction temperature of 135°C for 10 hours.
TSTRESS = 130°C
TUSE = 125°C,
AF = e([(1.4/8.617 • 10
–5) • (1/398 – 1/403)] )
= 16.6
The equivalent operating time at 125°C = 16.6 hours.
Thus the overall retention of the EEPROM was degraded
by 16.6 hours as a result of operating at a junction temperature of 130°C for 10 hours. The effect of the overstress is negligible when compared to the overall EEPROM
retention rating of 87,600 hours at a maximum junction
temperature of 125°C.
The integrity of the entire onboard EEPROM is checked with
a CRC calculation each time its data is to be read, such as
after a power-on reset or execution of a RESTORE_USER_
ALL command. If a CRC error occurs, the CML bit is set in
the STATUS_BYTE and STATUS_WORD commands, the
EEPROM CRC Error bit in the STATUS_MFR_SPECIFIC
command is set, and the ALERT and RUN pins pulled
low (PWM channels off). At that point the device will only
respond at special address 0x7C, which is activated only
after an invalid CRC has been detected. The chip will also
respond at the global addresses 0x5A and 0x5B, but use
of these addresses when attempting to recover from a
CRC issue is not recommended. All power supply rails
associated with either PWM channel of a device reporting
an invalid CRC should remain disabled until the issue is
Rev. B
For more information www.analog.com
LTM4680
OPERATION
resolved. See the Applications Information section or contact the factory for details on efficient in-system EEPROM
programming, including bulk EEPROM Programming,
which the LTM4680 also supports.
The LTM4680 contains dual integrated constant frequency
current mode control buck regulators (channel 0 and
channel 1) whose built-in power MOSFETs are capable of
fast switching speed. The factory NVM-default switching
frequency clocks SYNC at 350kHz, to which the regulators synchronize their switching frequency. The default
phase-interleaving angle between the channels is 180°.
A pin-strapping resistor on FSWPH_CFG configures the
frequency of the SYNC clock (switching frequency) and
the channel phase relationship of the channels to each
other and with respect to the falling edge of the SYNC signal. (Most possible combinations of switching frequency
and phase-angle assignments are settleable by resistor
pin programming; see Table 3. Configure the LTM4680’s
NVM to implement settings not available by resistorpin strapping.) When a FSWPH_CFG pin-strap resistor
sets the channel phase relationship of the LTM4680’s
channels, the SYNC clock is not driven by the module;
instead, SYNC becomes strictly a high impedance input
and channel switching frequency is then synchronized to
SYNC provided by an externally-generated clock or sibling LTM4680 with pull-up resistor to VDD33. Switching
frequency and phase relationship can be altered via the
I2C interface, but only when switching action is off, i.e.,
when the module is not regulating either output. See the
Applications Information section for details.
Programmable analog feedback loop compensation for
channel 0 and channel 1 is accomplished with a capacitor connection from COMP0,1a to SGND, and a capacitor
from COMP0,1b to SGND. The COMP0,1b pin is for the
high frequency gain roll off and is the gm amplifier output that has a programmable range, and the COMP0,1a
pin has the programmable resistor range along with a
capacitor to SGND that sets the frequency compensation. See Programmable Loop Compensation section.
The LTM4680 module has sufficient stability margins and
good transient performance with a wide range of output
capacitors—even all-ceramic MLCCs. Table 12 through
Table 14 provide guidance on input and output capacitors
recommended for many common operating conditions
along with the programmable compensation settings. The
Analog Devices LTpowerCAD tool is available for transient
and stability analysis, and experienced users who prefer to adjust the module’s feedback loop compensation
parameters can use this tool.
POWER-UP AND INITIALIZATION
The LTM4680 is designed to provide standalone supply
sequencing and controlled turn-on and turn-off operation.
It operates from a single input supply (4.5V to 16V) while
three on-chip linear regulators generate internal 2.5V,
3.3V and 5.5V. If VIN does not exceed 6V, and the EXTVCC
pin is not driven by an external supply, the INTVCC and VIN
pins must be tied together. The controller configuration is
initialized by an internal threshold based UVLO where VIN
must be approximately 4V and the 5.5V, 3.3V and 2.5V
linear regulators must be within approximately 20% of
the regulated values. In addition to the power supply, a
PMBus RESTORE_USER_ALL or MFR_RESET command
can initialize the part too.
The EXTVCC pin is driven by an external regulator to
improve efficiency of the circuit and minimize power
loss on the LTM4680 when VIN is high. The EXTVCC pin
must exceed approximately 4.8V, and VIN must exceed 7V
before the INTVCC LDO operates from the EXTVCC pin. To
minimize application power, the EXTVCC pin can be supplied by a switching regulator.
During initialization, the external configuration resistors are identified and/or contents of the NVM are
read into the controller’s commands and the power
train is held off. The RUNn and FAULTn and PGOODn
are held low. The LTM4680 will use the contents of
Table 1 thru Table 4 to determine the resistor defined
parameters. See the Resistor Configuration section
for more details. The resistor configuration pins only
control some of the preset values of the controller. The
remaining values are programmed in NVM either at the
factory or by the user.
If the configuration resistors are not inserted or if the
ignore RCONFIG bit is asserted (bit 6 of the MFR_
CONFIG_ALL configuration command), the LTM4680
Rev. B
For more information www.analog.com
25
LTM4680
OPERATION
will use only the contents of NVM to determine the DC/
DC characteristics. The ASEL value read at power-up or
reset is always respected unless the pin is open. The ASEL
will set the bottom 4LSBs and the MSBs are set by NVM.
See the Applications Information section for more details.
After the part has initialized, an additional comparator
monitors VIN. The VIN_ON threshold must be exceeded
before the output power sequencing can begin. After VIN
is initially applied, the part will typically require 30ms to
initialize and begin the TON_DELAY timer. The readback
of voltages and currents may require an additional 0ms
to 90ms.
SOFT-START
The method of start-up sequencing described below is
time-based. The part must enter the run state prior to
soft-start. The run pins are released by the LTM4680 after
the part is initialized and VIN is greater than the VIN_ON
threshold. If multiple LTM4680s are used in an application, they all hold their respective run pins low until
all devices are initialized and VIN exceeds the VIN_ON
threshold for every device. The SHARE_CLK pin assures
all the devices connected to the signal use the same time
base. The SHARE_CLK pin is held low until the part has
been initialized after VIN is applied. The LTM4680 can be
set to turn-off (or remain off) if SHARE_CLK is low (set
bit 2 of MFR_CHAN_CONFIG to 1). This allows the user
to assure synchronization across numerous LTC® devices
even if the RUN pins cannot be connected together due to
board constraints. In general, if the user cares about synchronization between chips it is best not only to connect
all the respective RUN pins together but also to connect
all the respective SHARE_CLK pins together and pulled up
to VDD33 with a 10k resistor. This assures all chips begin
sequencing at the same time and use the same time base.
After the RUN pins release and prior to entering a constant output voltage regulation state, the LTM4680 performs a monotonic initial ramp or “soft-start”. Soft-start
is performed by actively regulating the load voltage while
digitally ramping the target voltage from 0V to the commanded voltage set-point. Once the LTM4680 is commanded to turn on (after power up and initialization),
the controller waits for the user specified turn-on delay
26
(TON_DELAY) prior to initiating this output voltage ramp.
The rise time of the voltage ramp can be programmed
using the TON_RISE command to minimize inrush currents associated with the start-up voltage ramp. The
soft-start feature is disabled by setting the value of TON_
RISE to any value less than 0.25ms. The LTM4680 PWM
always uses discontinuous mode during the TON_RISE
operation. In discontinuous mode, the bottom MOSFET
is turned off as soon as reverse current is detected in the
inductor. This will allow the regulator to start up into a
pre-biased load. When the TON_MAX_FAULT_LIMIT is
reached, the part transitions to continuous mode, if so
programmed. If TON_MAX_FAULT_LIMIT is set to zero,
there is no time limit and the part transitions to the desired
conduction mode after TON_RISE completes and VOUT
has exceeded the VOUT_UV_FAULT_LIMIT and IOUT_OC
is not present. However, setting TON_MAX_FAULT_LIMIT
to a value of 0 is not recommended.
TIME-BASED SEQUENCING
The default mode for sequencing the outputs on and off
is time-based. Each output is enabled after waiting TON_
DELAY amount of time following either a RUN pin going
high, a PMBus command to turn on or the VIN rising above
a preprogrammed voltage. Off sequencing is handled in a
similar way. To assure proper sequencing, make sure all
ICs connect the SHARE_CLK pin together and RUN pins
together. If the RUN pins cannot be connected together
for some reasons, set bit 2 of MFR_CHAN_ CONFIG to
1. This bit requires the SHARE_CLK pin to be clocking
before the power supply output can start. When the RUN
pin is pulled low, the LTM4680 will hold the pin low for the
MFR_ RESTART_DELAY. The minimum MFR_RESTART_
DELAY is TOFF_DELAY + TOFF_FALL + 136ms. This delay
assures proper sequencing of all rails. The LTM4680 calculates this delay internally and will not process a shorter
delay. However, a longer commanded MFR_RESTART_
DELAY can be used by the part. The maximum allowed
value is 65.52 seconds.
VOLTAGE-BASED SEQUENCING
The sequence can also be voltage-based. As shown
in Figure 4, The PGOODn pin is asserted when the UV
Rev. B
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LTM4680
OPERATION
threshold is exceeded for each output. It is possible to
feed the PGOOD pin from one LTM4680 into the RUN pin
of the next LTM4680 in the sequence, especially across
multiple LTM4680s. The PGOODn has a 100µs filter. If
the VOUT voltage bounces around the UV threshold for a
long period of time it is possible for the PGOODn output
to toggle more than once. To minimize this problem, set
the TON_RISE time under 100ms.
If a fault in the string of rails is detected, only the faulted
rail and downstream rails will fault off. The rails in the
string of devices in front of the faulted rail will remain on
unless commanded off.
START
PGOOD0
RUN 0
LTM4680
RUN 1
PGOOD1
RUN 0
PGOOD0
LTM4680
RUN 1
PGOOD1
There are two ways to respond to faults; which are retry
mode and latched off mode. In retry mode, the controller responds to a fault by shutting down and entering the inactive state for a programmable delay time
(MFR_RETRY_DELAY). This delay minimizes the duty
cycle associated with autonomous retries if the fault that
causes the shutdown disappears once the output is disabled. The retry delay time is determined by the longer of
the MFR_RETRY_ DELAY command or the time required
for the regulated output to decay below 12.5% of the
programmed value. If multiple outputs are controlled by
the same FAULTn pin, the decay time of the faulted output
determines the retry delay. If the natural decay time of
the output is too long, it is possible to remove the voltage requirement of the MFR_RETRY_DELAY command
by asserting bit 0 of MFR_CHAN_CONFIG. Alternatively,
latched off mode means the controller remains latched-off
following a fault and clearing requires user intervention
such as toggling RUNn or commanding the part OFF then
ON.
4680 F04
TO NEXT CHANNEL
IN THE SEQUENCE
Figure 4. Event (Voltage) Based Sequencing
SHUTDOWN
The LTM4680 supports two shutdown modes. The first
mode is closed-loop shutdown response, with user
defined turn-off delay (TOFF_DELAY) and ramp down rate
(TOFF_FALL). The controller will maintain the mode of
operation for TOFF_FALL. The second mode is discontinuous conduction mode, the controller will not draw current
from the load and the fall time will be set by the output
capacitance and load current, instead of TOFF_FALL.
The shutdown occurs in response to a fault condition
or loss of SHARE_CLK (if bit 2 of MFR_CHAN_ CONFIG
is set to a 1) or VIN falling below the VIN_OFF threshold or FAULT pulled low externally (if the MFR_FAULT_
RESPONSE is set to inhibit). Under these conditions, the
power stage is disabled in order to stop the transfer of
energy to the load as quickly as possible. The shutdown
state can be entered from the soft-start or active regulation states or through user intervention.
LIGHT-LOAD CURRENT OPERATION
The LTM4680 has two modes of operation: high efficiency
discontinuous conduction mode or forced continuous
conduction mode. Mode selection is done using the
MFR_PWM _MODE command (discontinuous conduction is always the start-up mode, forced continuous is the
default running mode).
If a controller is enabled for discontinuous operation, the
inductor current is not allowed to reverse. The reverse
current comparator’s output turns off the bottom MOSFET
just before the inductor current reaches zero, preventing
it from reversing and going negative.
In forced continuous operation, the inductor current is
allowed to reverse at light loads or under large transient
conditions. The peak inductor current is determined solely
by the voltage on the COMPn pins. In this mode, the efficiency at light loads is lower than in discontinuous mode
operation. However, continuous mode exhibits lower output ripple and less interference with audio circuitry, but
may result in reverse inductor current, which can cause
the input supply to boost. The VIN_OV_FAULT_LIMIT can
detect this and turn off the offending channel. However,
Rev. B
For more information www.analog.com
27
LTM4680
OPERATION
this fault is based on an ADC read and can take up to tCONVERT to detect. If there is a concern about the input supply
boosting, keep the part in discontinuous conduction mode.
PWM control pins will also apply. Both channels must be
off before the FREQUENCY_SWITCH and MFR_PWM_
CONFIG commands can be written to the LTM4680.
If the part is set to discontinuous mode operation, as
the inductor average current increases, the controller will
automatically modify the operation from discontinuous
mode to continuous mode.
The phase relationships and frequency options provide for
numerous application options. Multiple LTM4680 modules can be synchronized to realize a PolyPhase array.
In this case the phases should be separated by 360/n
degrees, where n is the number of phases driving the
output voltage rail.
SWITCHING FREQUENCY AND PHASE
The switching frequency of the PWM can be established
with an internal oscillator or an external time base. The
internal phase-locked loop (PLL) synchronizes the PWM
control to this timing reference with proper phase relation,
whether the clock is provided internally or externally. The
device can also be configured to provide the master clock
to other devices through PMBus command, NVM setting,
or external configuration resistors as outlined in Table 3.
As clock master, the LTM4680 will drive its open-drain
SYNC pin at the selected rate with a pulse width of 500ns.
An external pull-up resistor between SYNC and VDD33 is
required in this case. Only one device connected to SYNC
should be designated to drive the pin. The LTM4680 will
automatically revert to an external SYNC input, disabling
its own SYNC, as long as the external SYNC frequency is
greater than 80% of the programmed SYNC frequency.
The external SYNC input shall have a duty cycle between
20% and 80%.
Whether configured to drive SYNC or not, the LTM4680
can continue PWM operation using its own internal oscillator if an external clock signal is subsequently lost.
The device can also be programmed to always require an
external oscillator for PWM operation by setting bit 4 of
MFR_CONFIG_ALL. The status of the SYNC driver circuit
is indicated by bit 10 of MFR_PADS.
The MFR_PWM_CONFIG command can be used to configure the phase of each channel. Desired phase can also
be set from EEPROM or external configuration resistors
as outlined in Table 3. Designated phase is the relationship between the falling edge of SYNC and the internal
clock edge that sets the PWM latch to turn on the top
power switch. Additional small propagation delays to the
28
PWM LOOP COMPENSATION
The internal PWM loop compensation resistors RCOMPna
of the LTM4680 can be adjusted using bit[4:0] of the
MFR_PWM_COMP command.
The transconductance (gm) of the LTM4680 PWM error
amplifier can be adjusted using bit[7:5] of the MFR_
PWM_COMP command. These two loop compensation
parameters can be programmed when device is in operation. Refer to the Programmable Loop Compensation subsection in the Applications Information section for further
details.
OUTPUT VOLTAGE SENSING
Both channels in LTM4680 have differential amplifiers, which allow the remote sensing of the load voltage
between V+ and V– pins. The telemetry ADC is also fully
differential and makes measurements between VOSNSn+
and VOSNSn-voltages for both channels at the V+ and V–
pins, respectively. The maximum allowed 3.6V, but the
LTM4680 design is limited to 3.3V.
INTVCC/EXTVCC POWER
Power for the internal top and bottom MOSFET drivers and most other internal circuitry is derived from the
INTVCC pin. When the EXTVCC pin is shorted to GND or
tied to a voltage less than 4.7V, an internal 5.5V linear
regulator supplies INTVCC power from VIN. If EXTVCC is
taken above 4.8V and VIN is higher than 7.0V, the 5.5V
regulator is turned off and an internal switch is turned on,
connecting EXTVCC. Using the EXTVCC allows the INTVCC
power to be derived from a high efficiency external source
Rev. B
For more information www.analog.com
LTM4680
OPERATION
such as a switching regulator output. EXTVCC can provide
power to the internal 3.3V linear regulator even when VIN
is not present, which allows the LTM4680 to be initialized
and programmed even without main power being applied.
The INTVCC regulator is powered from the SVIN pin, the
power through the IC is equal to SVIN • IINTVCC. The gate
charge current is dependent on operating frequency. The
INTVCC regulator can supply up to 100mA, and the typical
INTVCC current for the LTM4680 is ~50mA. A 12V input
voltage would equate to a difference of 7V drop across
the internal controller, when multiplied by 50mA equals a
350mW power loss. This loss can be eliminated by providing an external 5V bias on the EXTVCC pin.
Do not tie INTVCC on the LTM4680 to an external supply
because INTVCC will attempt to pull the external supply
high and hit current limit, significantly increasing the die
temperature.
For applications where VIN is 5V, tie the VIN and INTVCC
pins together to the 5V input through a 1Ω or 2.2Ω resistor as shown in Test Circuit 2.
OUTPUT CURRENT SENSING AND SUB MILLIOHM
DCR CURRENT SENSING
The LTM4680 use a unique sub-milliohm inductor current sensing technique that provides a high level signal
to noise ratio while sensing very low signals in current
mode operation. This enables higher conversion efficiencies with the use of the internal sub-milliohm inductors in
heavy load applications. The current limit threshold can
be accurately set with the MFR_PWM_MODE[7] for High
and Low range (see page 90).
The internal DCR sensing network, thus current limit are
calculated based on the DCR of the inductor at room temperature. The DCR of the inductor has a large temperature
coefficient, approximately 3800ppm/°C. The temperature
coefficient of the inductor is written to the MFR_IOUT_
CAL_GAIN_TC register. The external temperature is sensed
near the inductor and used to modify the internal current
limit circuit to maintain an essentially constant current
limit with temperature. The current sensed is then digitized
by the LTM4680’s telemetry ADC with an input range of
±128mV, a noise floor of 7µVRMS, and a peak-peak noise of
approximately 46.5µV. The LTM4680 computes the inductor current using the DCR value stored in the IOUT_CAL_
GAIN command and the temperature coefficient stored in
command MFR_IOUT_CAL_GAIN_TC. The resulting current value is returned by the READ_IOUT command.
INPUT CURRENT SENSING
To sense the total input current consumed by the
LTM4680’s power stages , a sense resistor is placed
between the supply voltage and the drain of the top
N-channel MOSFET. The IIN+ and IIN– pins are connected
to the sense resistor. The filtered voltage is amplified by
the internal high side current sense amplifier and digitized
by the LTM4680’s telemetry ADC. The input current sense
amplifier has three gain settings of 2x, 4x, and 8x set by
the bits[6:5] of the MFR_PWM_CONFIG command. The
maximum input sense voltage for the three gain settings
is 50mV, 25mV, and 10mV respectively. The LTM4680
computes the input current using the internal RSENSE
value stored in the IIN_CAL_GAIN command. The resulting measured power stage current is returned by the
READ_IIN command.
The LTM4680 uses a 1Ω resistor to measure the SVIN pin
supply current being consumed by the LTM4680. This
value is returned by the MFR_READ_ICHIP command.
The chip current is calculated by using the 1Ω value
stored in the MFR_ICHIP_CAL_GAIN command. Refer
to the subsection titled Input Current Sense Amplifier in
the Applications Information section for further details.
PolyPhase LOAD SHARING
Multiple LTM4680s can be arrayed in order to provide a
balanced load-share solution by bussing the necessary
pins. Figure 47 illustrates a 4-Phase design sharing connections required for load sharing.
If an external oscillator is not provided, the SYNC pin
should only be enabled on one of the LTM4680s. The
other(s) should be programmed to disable SYNC using
bit 4 of MFR_CONFIG_ALL. If an external oscillator is
present, the chip with the SYNC pin enabled will detect
the presence of the external clock and disable its output.
Rev. B
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29
LTM4680
OPERATION
Multiple channels need to tie all the VOSNSn+ pins together,
and all the VOSNSn – pins together, COMPna and COMPnb
pins together as well. Do not assert bit[4] of MFR_
CONFIG_ALL except in a PolyPhase application.
The user must share the SYNC, SHARE_CLK, FAULT, and
ALERT pins of these parts. Be sure to use pull-up resistors
on SYNC, FAULT, SHARE_CLK and ALERT.
EXTERNAL/INTERNAL TEMPERATURE SENSE
Temperature is measured using the internal diodeconnected PNP transistors on either of the TSNS0b or
TSNS1b pins corresponding to channel 0 or 1. TSNSnb
pins should be connected to their respective TSNSna pins,
and these returns are directly connected to the LTM4680
SGND pin. Two different currents are applied to the diode
(nominally 2µA and 32µA) and the temperature is calculated from a ∆VBE measurement made with the internal
16-bit monitor ADC (see Figure 2 Block Diagram).
The LTM4680 will only implement ∆VBE temperature
sensing, therefore MFR_PWM_MODE bit[5] is reserved.
CH0 and CH1 temperatures can be linked to CH0 only for
adjusting the temperature compensated variables, and
internal temperature monitoring. This frees up TSNS1a
for an external/temperature sensing.
RCONFIG (RESISTOR CONFIGURATION) PINS
There are six input pins utilizing 1% resistors between
these pins and SGND to select key operating parameters.
The pins are ASEL, FSWPH_CFG, VOUT0_CFG, VOUT1_
CFG, VTRIM0_CFG, VTRIM1_CFG. If pins are floated, the
value stored in the corresponding NVM command is used.
If bit 6 of the MFR_CONFIG_ALL configuration command
is asserted in NVM, the resistor input is ignored upon
power-up except for ASEL which is always respected.
The resistor configuration pins are only measured during a power-up reset or after a MFR_RESET or after a
RESTORE_USER_ALL command is executed.
The VOUTn_CFG pin settings are described in Table 1.
These pins set the LTM4680 VOUT0 and VOUT1 output
voltage coarse settings. If the pin is open, the VOUT_
COMMAND command is loaded from NVM to determine
30
the output voltage. The default setting is to have the
switcher off unless the voltage configuration pins are
installed. The VTRIMn_CFG pins in Table 2 are used to set
the output voltage fine adjustment setting. Both combine
to offer several distinct output voltages.
The following parameters are set as a percentage of the
output voltage if the RCONFIG pins are used to determine
the output voltage:
n
n
n
n
n
n
VOUT_OV_FAULT_LIMIT.....................................+10%
VOUT_OV_WARN_LIMIT.....................................+7.5%
VOUT_MAX..........................................................+7.5%
VOUT_MARGIN_HIGH.........................................+5%
VOUT_MARGIN_LOW..........................................–5%
VOUT_UV_FAULT_LIMIT.....................................–7%
The FSWPH_CFG pin settings are described in Table 3.
This pin selects the switching frequency and phase of each
channel. The phase relationships between the two channels
and SYNC pin are determined in Table 3. To synchronize
to an external clock, the part should be put into external
clock mode (SYNC output disabled but frequency set to
the nominal value). If no external clock is supplied, the part
will clock at the programmed frequency. If the application
is multiphase and the SYNC signal between chips is lost,
the parts will not operate at the designed phase even if
they are programmed and trimmed to the same frequency.
This may increase the ripple voltage on the output, possibly produce undesirable operation. If the external SYNC
signal is being generated internally and external SYNC is
not selected, bit 10 of MFR_PADS will be asserted. If no
frequency is selected and the external SYNC frequency is
not present, a PLL_FAULT will occur. If the user does not
wish to see the ALERT from a PLL_FAULT even if there is
not a valid synchronization signal at power-up, the ALERT
mask for PLL_FAULT must be written. See the description
on SMBALERT_MASK for more details. If the SYNC pin is
connected between multiple ICs only one of the ICs should
have the SYNC pin enabled using the MFR_CONFIG_ALL[4]
=1, and all other ICs should be configured to have the SYNC
pin disabled with MFR_CONFIG_ALL[4] =0.
The ASEL pin settings are described in Table 4. ASEL
selects slave address for the LTM4680. For more detail,
refer to Table 5.
Rev. B
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LTM4680
OPERATION
NOTE: Per the PMBus specification, pin programmed
parameters can be overridden by commands from the
digital interface with the exception of ASEL which is
always honored. Do not set any part address to 0x5A or
0x5B because these are global addresses and all parts will
respond to them.
Table 1. VOUTn_CFG Pin Strapping Look-Up Table for the
LTM4680’s Output Voltage, Coarse Setting (Not Applicable if
MFR_CONFIG_ALL[6] = 1b)
Table 2. VTRIMn_CFG Pin Strapping Look-Up Table for the
LTM4680’s Output Voltage, Fine Adjustment Setting (Not
Applicable if MFR_CONFIG_ALL[6] = 1b)
RVTRIMn_CFG*
(kΩ)
VTRIM (mV) FINE ADJUSTMENT TO VOUTn
SETTING WHEN RESPECTIVE
Open
0
32.4
99
22.6
86.625
74.25
15.4
61.875
RVOUTn_CFG*
(kΩ)
VOUTn (V)
SETTING COARSE
MFR_PWM_
MODEn[1] BIT
18.0
Open
NVM
NVM
12.7
49.5
32.4
NVM
NVM
10.7
37.125
22.6
3.3
0
9.09
24.75
18.0
3.1
0
7.68
12.375
15.4
2.9
0
6.34
–12.375
12.7
2.7
0
5.23
–24.75
10.7
2.5
0, if VTRIMn > 0mV
1, if VTRIMn ≤ 0mV
4.22
–37.125
9.09
2.3
1
3.24
–49.5
7.68
2.1
1
2.43
–61.875
6.34
1.9
1
1.65
–74.25
5.23
1.7
1
0.787
–86.625
4.22
1.5
1
0
–99
3.24
1.3
1
2.43
1.1
1
1.65
0.9
1
0.787
0.7
1
0
0.5
1
*RVOUTn_CFG value indicated is nominal. Select RVOUTn_CFG from a
resistor vendor such that its value is always within 3% of the value
indicated in the table. Take into account resistor initial tolerance, T.C.R.
and resistor operating temperatures, soldering heat/IR reflow, and
endurance of the resistor over its lifetime. Thermal shock/cycling,
moisture (humidity) and other effects (depending on one’s specific
application) could also affect RVOUTn_CFG’s value over time. All such
effects must be taken into account in order for resistor pin strapping to
yield the expected result at every SVIN power-up and/or every execution
of MFR_RESET or RESTORE_ USER_ALL, over the lifetime of one’s
product.
*RVTRIMn_CFG value indicated is nominal. Select RVTRIMn_CFG from a
resistor vendor such that its value is always within 3% of the value
indicated in the table. Take into account resistor initial tolerance, T.C.R.
and resistor operating temperatures, soldering heat/IR reflow, and
endurance of the resistor over its lifetime. Thermal shock/cycling,
moisture (humidity) and other effects (depending on one’s specific
application) could also affect RVTRIMn_CFG’s value over time. All such
effects must be taken into account in order for resistor pin strapping to
yield the expected result at every SVIN power-up and/or every execution
of MFR_RESET, or RESTORE_USER_ALL over the lifetime of one’s
product.
Rev. B
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31
LTM4680
OPERATION
Table 3. FSWPH_CFG Pin Strapping Look-Up Table to Set the LTM4680’s Switching Frequency and Channel Phase-Interleaving Angle
(Not Applicable if MFR_CONFIG_ALL[6] = 1b)
RFSWPH_CFG*
(kΩ)
SWITCHING
FREQUENCY (kHz)
θSYNC TO θ0
θSYNC TO θ1
bits [2:0] of
MFR_PWM_CONFIG
bit [4] of
MFR_CONFIG_ALL
Open
NVM; LTM4680
Default = 500
NVM; LTM4680
Default = 0°
NVM; LTM4680
Default = 180°
NVM; LTM4680
Default = 000b
NVM; LTM4680
Default = 0b
32.4
250
0°
180°
000b
0b
22.6
350
0°
180°
000b
0b
18.0
425
0°
180°
000b
0b
15.4
575
0°
180°
000b
0b
12.7
650
0°
180°
000b
0b
10.7
750
0°
180°
000b
0b
7.68
500
120°
240°
100b
0b
6.34
500
90°
270°
001b
0b
5.23
External**
0°
240°
010b
1b
4.22
External**
0°
120°
011b
1b
3.24
External**
60°
240°
101b
1b
2.43
External**
120°
300°
110b
1b
1.65
External**
90°
270°
001b
1b
0.787
External**
0°
180°
000b
1b
0
External**
120°
240°
100b
1b
*RFSWPH_CFG value indicated is nominal. Select RFSWPH_CFG from a resistor vendor such that its value is always within 3% of the value indicated in the
table. Take into account resistor initial tolerance, T.C.R. and resistor operating temperatures, soldering heat/IR reflow, and endurance of the resistor over
its lifetime. Thermal shock/cycling, moisture (humidity) and other effects (depending on one’s specific application) could also affect RFSWPH_CFG’s value
over time. All such effects must be taken into account in order for resistor pin-strapping to yield the expected result at every SVIN power-up and/or every
execution of MFR_RESET or RESTORE_USER_ALL, over the lifetime of one’s product.
**External setting corresponds to FREQUENCY_SWITCH (Register 0x33) value set to 0x0000; the device synchronizes its switching frequency to that of
the clock provided on the SYNC pin, provided MFR_CONFIG_ALL[4] = 1b.
32
Rev. B
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LTM4680
OPERATION
Table 4. ASEL Pin Strapping Look-Up Table to Set the
LTM4680’s Slave Address (Applicable Regardless of
MFR_CONFIG_ALL[6] Setting)
Table 5. LTM4680 MFR_ADDRESS Command Examples
Expressed in 7- and 8-Bit Addressing
HEX DEVICE
ADDRESS
BIT
RASEL* (kΩ)
SLAVE ADDRESS
Open
100_1111_R/W
DESCRIPTION
7-BIT
8-BIT
7 6 5 4 3 2 1 0 R/W
100_1111_R/W
Rail4
0x5A
0xB4
0 1 0 1 1 0 1 0
0
22.6
100_1110_R/W
Global4
0x5B
0xB6
0 1 0 1 1 0 1 1
0
18.0
100_1101_R/W
Default
0x4F
0x9E
0 1 0 0 1 1 1 1
0
15.4
100_1100_R/W
Example 1
0x40
0x80
0 1 0 0 0 0 0 0
0
12.7
100_1011_R/W
Example 2
0x41
0x82
0 1 0 0 0 0 0 1
0
100_1010_R/W
Disabled2,3
1 0 0 0 0 0 0 0
0
9.09
100_1001_R/W
7.68
100_1000_R/W
Note 1: This table can be applied to the MFR_RAIL_ADDRESSn
commands, but not the MFR_ADDRESS command.
6.34
100_0111_R/W
5.23
100_0110_R/W
4.22
100_0101_R/W
3.24
100_0100_R/W
2.43
100_0011_R/W
1.65
100_0010_R/W
0.787
100_0001_R/W
0
100_0000_R/W
32.4
10.7
Where:
R/W = Read/Write bit in control byte
All PMBus device addresses listed in the specification are 7 bits wide
unless otherwise noted.
Note: The LTM4680 will always respond to slave address 0x5A and 0x5B
regardless of the NVM or ASEL resistor configuration values.
*RCFG value indicated is nominal. Select RCFG from a resistor vendor
such that its value is always within 3% of the value indicated in the table.
Take into account resistor initial tolerance, T.C.R. and resistor operating
temperatures, soldering heat/IR reflow, and endurance of the resistor
over its lifetime. Thermal shock cycling, moisture (humidity) and other
effects (depending on one’s specific application) could also affect RCFG’s
value over time. All such effects must be taken into account in order for
resistor pin-strapping to yield the expected result at every SVIN power-up
and/or every execution of MFR_RESET or RESTORE_USER_ALL, over the
lifetime of one’s product.
Note 2: A disabled value in one command does not disable the device,
nor does it disable the global address.
Note 3: A disabled value in one command does not inhibit the device
from responding to device addresses specified in other commands.
Note 4: It is not recommended to write the value 0x00, 0x0C (7-bit), 0x5A
(7-bit), 0x5B (7-bit) or 0x7C(7-bit) to the MFR_CHANNEL_ADDRESSn or
the MFR_RAIL_ADDRESSn commands.
FAULT DETECTION AND HANDLING
A variety of fault and warning reporting and handling
mechanisms are available. Fault and warning detection
capabilities include:
Input OV Fault Protection and UV Warning
n
Average Input OC Warning
n
Output OV/UV Fault and Warning Protection
n
Output OC Fault and Warning Protection
n
Internal Control Die and Internal Module
Overtemperature Fault and Warning Protection
n
Internal Undertemperature Fault and Warning
Protection
n
CML Fault (Communication, Memory or Logic)
n
External Fault Detection via the Bidirectional FAULTn
Pins
n
In addition, the LTM4680 can map any combination of
fault indicators to their respective FAULTn pin using the
propagate FAULTn response commands, MFR_FAULT_
PROPAGATE. Typical usage of a FAULTn pin is as a driver
for an external crowbar device, overtemperature alert,
Rev. B
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33
LTM4680
OPERATION
overvoltage alert or as an interrupt to cause a microcontroller to poll the fault commands. Alternatively, the
FAULTn pins can be used as inputs to detect external faults
downstream of the controller that require an immediate
response.
Any fault or warning event will always cause the ALERT
pin to assert low unless the fault or warning is masked by
the SMBALERT_MASK. The pin will remain asserted low
until the CLEAR_FAULTS command is issued, the fault bit
is written to a 1 or bias power is cycled or a MFR_RESET
command is issued, or the RUN pins are toggled OFF/
ON or the part is commanded OFF/ON via PMBus or an
ARA command operation is performed. The MFR_FAULT_
PROPAGATE command determines if the FAULT pins are
pulled low when a fault is detected.
Output and input fault event handling is controlled by
the corresponding fault response byte as specified in
Tables 14 thru 18. Shutdown recovery from these types
of faults can either be autonomous or latched. For autonomous recovery, the faults are not latched, so if the fault
conditions not present after the retry interval has elapsed,
a new soft-start is attempted.
If the fault persists, the controller will continue to retry.
The retry interval is specified by the MFR_RETRY_DELAY
command and prevents damage to the regulator components by repetitive power cycling, assuming the fault
condition itself is not immediately destructive. The MFR_
RETRY_DELAY must be greater than 120ms. It can not
exceed 83.88 seconds.
Status Registers and ALERT Masking
Figure 5 summarizes the internal LTM4680 status registers accessible by PMBus command. These contain indication of various faults, warnings and other important
operating conditions. As shown, the STATUS_BYTE and
STATUS_WORD commands also summarize contents of
other status registers. Refer to PMBus Command Details
for specific information.
NONE OF THE ABOVE in the STATUS_BYTE indicates that
one or more of the bits in the most-significant nibble of
STATUS_WORD are also set.
34
In general, any asserted bit in a STATUS_x register also
pulls the ALERT pin low. Once set, ALERT will remain low
until one of the following occurs.
A CLEAR_FAULTS or MFR_RESET Command Is
Issued
n
The Related Status Bit Is Written to a One
n
The Faulted Channel Is Properly Commanded Off and
Back On
n
The LTM4680 Successfully Transmits Its Address
During a PMBus ARA
n
Bias Power Is Cycled
n
With some exceptions, the SMBALERT_MASK command
can be used to prevent the LTM4680 from asserting
ALERT for bits in these registers on a bit-by-bit basis.
These mask settings are promoted to STATUS_WORD
and STATUS_BYTE in the same fashion as the status bits
themselves. For example, if ALERT is masked for all bits
in channel 0 STATUS_VOUT, then ALERT is effectively
masked for the VOUT bit in STATUS_WORD for PAGE 0.
The BUSY bit in STATUS_BYTE also asserts ALERT low
and cannot be masked. This bit can be set as a result of
various internal interactions with PMBus communication.
This fault occurs when a command is received that cannot
be safely executed with one or both channels enabled. As
discussed in the Application Information, BUSY faults can
be avoided by polling MFR_COMMON before executing
some commands.
If masked faults occur immediately after power up, ALERT
may still be pulled low because there has not been time
to retrieve all of the programmed masking information
from EEPROM.
Status information contained in MFR_COMMON and
MFR_PADS can be used to further debug or clarify the
contents of STATUS_BYTE or STATUS_WORD as shown,
but the contents of these registers do not affect the state
of the ALERT pin and may not directly influence bits in
STATUS_BYTE or STATUS_WORD.
Rev. B
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LTM4680
OPERATION
STATUS_WORD
STATUS_VOUT*
7
6
5
4
3
2
1
0
VOUT_OV Fault
VOUT_OV Warning
VOUT_UV Warning
VOUT_UV Fault
VOUT_MAX Warning
TON_MAX Fault
TOFF_MAX Warning
(reads 0)
15
14
13
12
11
10
9
8
VOUT
IOUT
INPUT
MFR_SPECIFIC
POWER_GOOD#
(reads 0)
(reads 0)
(reads 0)
7
6
5
4
3
2
1
0
BUSY
OFF
VOUT_OV
IOUT_OC
(reads 0)
TEMPERATURE
CML
NONE OF THE ABOVE
STATUS_BYTE
(PAGED)
STATUS_IOUT
7
6
5
4
3
2
1
0
IOUT_OC Fault
(reads 0)
IOUT_OC Warning
(reads 0)
(reads 0)
(reads 0)
(reads 0)
(reads 0)
MFR_COMMON
7
6
5
4
3
2
1
0
STATUS_TEMPERATURE
OT Fault
OT Warning
(reads 0)
UT Fault
(reads 0)
(reads 0)
(reads 0)
(reads 0)
(PAGED)
STATUS_CML
7
6
5
4
3
2
1
0
Chip Not Driving ALERT Low
Chip Not Busy
Internal Calculations Not Pending
Output Not In Transition
EEPROM Initialized
(reads 0)
SHARE_CLK_LOW
WP Pin High
Invalid/Unsupported Command
Invalid/Unsupported Data
Packet Error Check Failed
Memory Fault Detected
Processor Fault Detected
(reads 0)
Other Communication Fault
Other Memory or Logic Fault
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
EEPROM ECC Status
Reserved
Reserved
Reserved
Reserved
DESCRIPTION
7
6
5
4
3
2
1
0
Internal Temperature Fault
Internal Temperature Warning
EEPROM CRC Error
Internal PLL Unlocked
Fault Log Present
VDD33 UV or OV Fault
VOUT Short Cycled
FAULT Pulled Low By External Device
(PAGED)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VDD33 OV Fault
VDD33 UV Fault
(reads 0)
(reads 0)
Invalid ADC Result(s)
SYNC Clocked by External Source
Channel 1 is POWER_GOOD
Channel 0 is POWER_GOOD
LTM4680 Forcing RUN1 Low
LTM4680 Forcing RUN0 Low
RUN1 Pin State
RUN0 Pin State
LTM4680 Forcing FAULT1 Low
LTM4680 Forcing FAULT0 Low
FAULT1 Pin State
FAULT0 Pin State
MFR_PADS
MFR_INFO
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VIN_OV Fault
(reads 0)
VIN_UV Warning
(reads 0)
Unit Off for Insuffcient VIN
(reads 0)
IIN_OC Warning
(reads 0)
STATUS_MFR_SPECIFIC
(PAGED)
(PAGED)
7
6
5
4
3
2
1
0
STATUS_INPUT
7
6
5
4
3
2
1
0
4680 F05
MASKABLE GENERATES ALERT BIT CLEARABLE
General Fault or Warning Event
General Non-Maskable Event
Dynamic
Status Derived from Other Bits
Yes
No
No
No
Yes
Yes
No
Not Directly
Yes
Yes
No
No
Figure 5. LTM4680 Status Register Summary
Rev. B
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35
LTM4680
OPERATION
Mapping Faults to FAULT Pins
Channel-to-channel fault (including channels from multiple LTM4680s) dependencies can be created by connecting FAULTn pins together. In the event of an internal
fault, one or more of the channels is configured to pull
the bussed FAULTn pins low. The other channels are then
configured to shut down when the FAULTn pins are pulled
low. For autonomous group retry, the faulted channel is
configured to let go of the FAULTn pin(s) after a retry
interval, assuming the original fault has cleared. All the
channels in the group then begin a soft-start sequence. If
the fault response is LATCH_OFF, the FAULTn pin remains
asserted low until either the RUN pin is toggled OFF/ON or
the part is commanded OFF/ON. The toggling of the RUN
either by the pin or OFF/ON command will clear faults
associated with the channel. If it is desired to have all
faults cleared when either RUN pin is toggled or, set bit 0
of MFR_CONFIG_ALL to a 1.
The status of all faults and warnings is summarized in the
STATUS_WORD and STATUS_BYTE commands.
Additional fault detection and handling capabilities are:
Power Good Pins
The PGOODn pins of the LTM4680 are connected to the
open drains of internal MOSFETs. The MOSFETs turn on
and pull the PGOODn pins low when the channel output
voltage is not within the channel’s UV and OV voltage
thresholds. During TON_DELAY and TON_RISE sequencing, the PGOODn pin is held low. The PGOODn pin is
also pulled low when the respective RUNn pin is low. The
PGOODn pin response is deglitched by an internal 100µs
digital filter. The PGOODn pin and PGOOD status may be
different at times due to communication latency of up to
10µs.
CRC Protection
The integrity of the NVM memory is checked after a power
on reset. A CRC error will prevent the controller from leaving the inactive state. If a CRC error occurs, the CML bit is
set in the STATUS_BYTE and STATUS_WORD commands,
the appropriate bit is set in the STATUS_MFR_SPECIFIC
command, and the ALERT pin will be pulled low. NVM
36
repair can be attempted by writing the desired configuration to the controller and executing a STORE_USER_ALL
command followed by a CLEAR_FAULTS command.
The LTM4680 manufacturing section of the NVM is mirrored. If both copies are corrupted, the “NVM CRC Fault”
in the STATUS_MFR_SPECIFIC command is set. If this
bit remains set after being cleared by issuing a CLEAR_
FAULTS or writing a 1 to this bit, an irrecoverable internal
fault has occurred. The user is cautioned to disable both
output power supply rails associated with this specific
part. There are no provisions for field repair of NVM faults
in the manufacturing section.
SERIAL INTERFACE
The LTM4680 serial interface is a PMBus compliant slave
device and can operate at any frequency between 10kHz
and 400kHz. The address is configurable using either the
NVM or an external resistor. In addition the LTM4680
always responds to the global broadcast address of 0x5A
(7-bit) or 0x5B (7-bit).
The serial interface supports the following protocols
defined in the PMBus specifications: 1) send command,
2) write byte, 3) write word, 4) group, 5) read byte, 6) read
word and 7) read block. 8) write block. All read operations
will return a valid PEC if the PMBus master requests it. If
the PEC_REQUIRED bit is set in the MFR_CONFIG_ALL
command, the PMBus write operations will not be acted
upon until a valid PEC has been received by the LTM4680.
Communication Protection
PEC write errors (if PEC_REQUIRED is active), attempts
to access unsupported commands, or writing invalid data
to supported commands will result in a CML fault. The
CML bit is set in the STATUS_BYTE and STATUS_WORD
commands, the appropriate bit is set in the STATUS_CML
command, and the ALERT pin is pulled low.
DEVICE ADDRESSING
The LTM4680 offers five different types of addressing
over the PMBus interface, specifically: 1) global, 2) device,
3) rail addressing and 4) alert response address (ARA).
Rev. B
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LTM4680
OPERATION
Global addressing provides a means of the PMBus master
to address all LTM4680 devices on the bus. The LTM4680
global address is fixed 0x5A (7-bit) or 0xB4 (8-bit) and
cannot be disabled. Commands sent to the global address
act the same as if PAGE is set to a value of 0xFF. Commands
sent are written to both channels simultaneously. Global
command 0x5B (7-bit) or 0xB6 (8-bit) is paged and allows
channel specific command of all LTM4680 devices on the
bus. Other ADI device types may respond at one or both
of these global addresses. Reading from global addresses
is strongly discouraged.
The IIN and IOUT overcurrent monitors are performed by
ADC readings and calculations. Thus these values are
based on average currents and can have a time latency
of up to tCONVERT. The IOUT calculation accounts for the
DCR and their temperature coefficient. The input current is
equal to the voltage measured across the RSENSE resistor
divided by the resistors value as set with the MFR_RVIN
command. If this calculated input current exceeds the
IN_OC_WARN_LIMIT the ALERT pin is pulled low and
the IIN_OC_WARN bit is asserted in the STATUS_INPUT
command.
Device addressing provides the standard means of the
PMBus master communicating with a single instance
of an LTM4680. The value of the device address is set
by a combination of the ASEL configuration pin and the
MFR_ ADDRESS command. When this addressing means
is used, the PAGE command determines the channel being
acted upon. Device addressing can be disabled by writing
a value of 0x80 to the MFR_ADDRESS.
The digital processor within the LTM4680 provides the
ability to ignore the fault, shut down and latch off or shut
down and retry indefinitely (hiccup). The retry interval
is set in MFR_RETRY_ DELAY and can be from 120ms
to 83.88 seconds in 1ms increments. The shutdown for
OV/UV and OC can be done immediately or after a user
selectable deglitch time.
Rail addressing provides a means for the bus master to
simultaneously communicate with all channels connected
together to produce a single output voltage (PolyPhase).
While similar to global addressing, the rail address can
be dynamically assigned with the paged MFR_RAIL_
ADDRESS command, allowing for any logical grouping
of channels that might be required for reliable system
control. Reading from rail addresses is also strongly
discouraged.
All four means of PMBus addressing require the user to
employ disciplined planning to avoid addressing conflicts.
Communication to LTM4680 devices at global and rail
addresses should be limited to command write operations.
RESPONSES TO VOUT AND IIN/IOUT FAULTS
A programmable overvoltage comparator (OV) guards
against transient overshoots as well as long-term overvoltages at the output. In such cases, the top MOSFET
is turned off and the bottom MOSFET is turned on.
However, the reverse output current is monitored while
device is in OV fault. When it reaches the limit, both top
and bottom MOSFETs are turned off. The top and bottom MOSFETs will keep their state until the overvoltage
condition is cleared regardless of the PMBus VOUT_OV_
FAULT_RESPONSE command byte value. This hardware
level fault response delay is typically 2µs from the overvoltage condition to BG asserted high. Using the VOUT_
OV_FAULT_RESPONSE command, the user can select
any of the following behaviors:
OV Pull-Down Only (OV Cannot Be Ignored)
n
VOUT OV and UV conditions are monitored by comparators. The OV and UV limits are set in three ways:
As a Percentage of the VOUT if Using the Resistor
Configuration Pins
n
In NVM if Either Programmed at the Factory or
Through the GUI
n
Output Overvoltage Fault Response
n
Shut Down (Stop Switching) Immediately—Latch Off
Shut Down Immediately—Retry Indefinitely at the
Time Interval Specified in MFR_RETRY_DELAY
n
Either the Latch Off or Retry fault responses can be deglitched in increments of (0-7) • 10µs. See Table 15.
By PMBus Command
n
Rev. B
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37
LTM4680
OPERATION
Output Undervoltage Response
Ignore
FAULT_LIMIT is 10µs. If the VOUT_UV_FAULT _LIMIT
is not reached within the TON_MAX_FAULT_LIMIT time,
the response of this fault is determined by the value of
the TON_MAX_FAULT_RESPONSE command value. This
response may be one of the following:
Shut Down Immediately—Latch Off
n
The response to an undervoltage comparator output can
be the following:
n
Ignore
n
Shut Down Immediately—Retry Indefinitely at the
Time Interval Specified in MFR_RETRY_DELAY.
n
The UV responses can be deglitched. See Table 16.
Peak Output Overcurrent Fault Response
Due to the current mode control algorithm, peak output
current across the inductor is always limited on a cycleby-cycle basis. The value of the peak current limit is specified in Electrical Characteristics table. The current limit
circuit operates by limiting the COMPn maximum voltage.
Since internal DCR sensing is used, the COMPn maximum
voltage has a temperature dependency directly proportional to the TC of the DCR of the inductor. The LTM4680
automatically monitors the external temperature sensors
and modifies the maximum allowed COMPn to compensate for this term. The IOUT_OC_FAULT_LIMIT section
provides data points for IOUT Limiting on page 90.
The overcurrent fault processing circuitry can execute the
following behaviors:
n
Shut Down (Stop Switching) Immediately—Latch Off
Shut Down Immediately—Retry Indefinitely at the
Time Interval Specified in MFR_RETRY_DELAY.
n
This fault response is not deglitched. A value of 0 in
TON_MAX_FAULT_LIMIT means the fault is ignored. The
TON_MAX_FAULT_LIMIT should be set longer than the
TON_RISE time. It is recommended TON_MAX_FAULT_
LIMIT always be set to a non-zero value, otherwise the
output may never come up and no flag will be set to the
user. See Table 19.
RESPONSES TO VIN OV FAULTS
VIN overvoltage is measured with the ADC. The response
is naturally deglitched by the 100ms typical response time
of the ADC. The fault responses are:
Ignore
n
Shut Down Immediately—Latch Off
n
Shut Down Immediately—Retry Indefinitely at the
Time Interval Specified in MFR_RETRY_DELAY. See
Table 19.
n
Current Limit Indefinitely
n
Shut Down Immediately—Latch Off
n
Shut Down Immediately—Retry Indefinitely at the
Time Interval Specified in MFR_RETRY_DELAY.
n
The overcurrent responses can be deglitched in increments of (0-7) • 16ms. See Table 17.
RESPONSES TO TIMING FAULTS
TON_MAX_FAULT_LIMIT is the time allowed for VOUT to
rise and settle at start-up. The TON_MAX_FAULT_LIMIT
condition is predicated upon detection of the VOUT_UV_
FAULT_LIMIT as the output is undergoing a SOFT_START
sequence. The TON_MAX_ FAULT_LIMIT time is started
after TON_DELAY has been reached and a SOFT_START
sequence is started. The resolution of the TON_MAX_
38
RESPONSES TO OT/UT FAULTS
Internal Overtemperature Fault Response
An internal temperature sensor protects against NVM
damage. Above 85°C, no writes to NVM are recommended. Above 130°C, the internal overtemperature warn
threshold is exceeded and the part disables the NVM and
does not re-enable until the temperature has dropped to
125°C. When the die temperature exceed 160°C the internal temperature fault response is enabled and the PWM
is disabled until the die temperature drops below 150°C.
Temperature is measured by the ADC. Internal temperature faults cannot be ignored. Internal temperature limits
cannot be adjusted by the user. See Table 18.
Rev. B
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LTM4680
OPERATION
External Overtemperature and Undertemperature
Fault Response
Two internal temperature sensors are used to sense the
temperature of critical circuit elements like inductors
and power MOSFETs on each channel. The OT_FAULT_
RESPONSE and UT_FAULT_ RESPONSE commands are
used to determine the appropriate response to an overtemperature and under temperature condition, respectively. If no external sense elements are used (not recommended) set the UT_FAULT_ RESPONSE to ignore—and
set the UT_FAULT_LIMIT to 275°C. The fault responses
are:
Ignore
n
Shut Down Immediately—Latch Off
n
Shut Down Immediately—Retry Indefinitely at the Time
n
Interval Specified in MFR_RETRY_DELAY. See Table 19.
RESPONSES TO INPUT OVERCURRENT AND OUTPUT
UNDERCURRENT FAULTS
Input overcurrent and output undercurrent are measured
with the ADC. The fault responses are:
FAULT LOGGING
The LTM4680 has fault logging capability. Data is logged
into memory in the order shown in Table 19. The data is
stored in a continuously updated buffer in RAM. When a
fault event occurs, the fault log buffer is copied from the
RAM buffer into NVM. Fault logging is allowed at temperatures above 85°C; however, retention of 10 years is
not guaranteed. When the die temperature exceeds 130°C
the fault logging is delayed until the die temperature drops
below 125°C. The fault log data remains in NVM until a
MFR_FAULT _LOG_CLEAR command is issued. Issuing
this command re-enables the fault log feature. Before reenabling fault log, be sure no faults are present and a
CLEAR_FAULTS command has been issued.
When the LTM4680 powers-up or exits its reset state, it
checks the NVM for a valid fault log. If a valid fault log
exists in NVM, the “Valid Fault Log” bit in the STATUS_
MFR_SPECIFIC command will be set and an ALERT event
will be generated. Also, fault logging will be blocked until
the LTM4680 has received a MFR_FAULT_LOG_CLEAR
command before fault logging will be re-enabled.
Shut Down Immediately—Latch Off
The information is stored in EEPROM in the event of
any fault that disables the controller on either channel. A
FAULTn being externally pulled low will not trigger a fault
logging event.
Shut Down Immediately—Retry Indefinitely at the
Time Interval Specified in MFR_RETRY_DELAY.
BUS TIMEOUT PROTECTION
Ignore
n
n
n
RESPONSES TO EXTERNAL FAULTS
When either FAULTn pin is pulled low, the OTHER bit is
set in the STATUS_WORD command, the appropriate bit
is set in the STATUS_MFR_SPECIFIC command, and the
ALERT pin is pulled low. Responses are not deglitched.
Each channel can be configured to ignore or shut down
then retry in response to its FAULTn pin going low by
modifying the MFR_FAULT_RESPONSE command. To
avoid the ALERT pin asserting low when FAULT is pulled
low, assert bit 1 of MFR_CHAN_CONFIG, or mask the
ALERT using the SMBALERT_MASK command.
The LTM4680 implements a timeout feature to avoid
persistent faults on the serial interface. The data packet
timer begins at the first START event before the device
address write byte. Data packet information must be
completed within 30ms or the LTM4680 will three-state
the bus and ignore the given data packet. If more time
is required, assert bit 3 of MFR_CONFIG_ALL to allow
typical bus timeouts of 255ms. Data packet information
includes the device address byte write, command byte,
repeat start event (if a read operation), device address
byte read (if a read operation), all data bytes and the PEC
byte if applicable.
The LTM4680 allows longer PMBus timeouts for block
read data packets. This timeout is proportional to the
length of the block read. The additional block read timeout
Rev. B
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39
LTM4680
OPERATION
applies primarily to the MFR_FAULT_LOG command. The
timeout period defaults to 32ms.
The user is encouraged to use as high a clock rate as
possible to maintain efficient data packet transfer between
all devices sharing the serial bus interface. The LTM4680
supports the full PMBus frequency range from 10kHz
to 400kHz.
SIMILARITY BETWEEN PMBus, SMBus AND I2C
2-WIRE INTERFACE
The PMBus 2-wire interface is an incremental extension
of the SMBus. SMBus is built upon I2C with some minor
differences in timing, DC parameters and protocol. The
PMBus/SMBus protocols are more robust than simple I2C
byte commands because PMBus/SMBus provide timeouts to prevent persistent bus errors and optional packet
error checking (PEC) to ensure data integrity. In general, a
master device that can be configured for I2C communication can be used for PMBus communication with little or
no change to hardware or firmware. Repeat start (restart)
is not supported by all I2C controllers but is required for
SMBus/PMBus reads. If a general purpose I2C controller
is used, check that repeat start is supported.
The LTM4680 supports the maximum SMBus clock speed
of 100kHz and is compatible with the higher speed PMBus
specification (between 100kHz and 400kHz) if MFR_
COMMON polling or clock stretching is enabled. For
robust communication and operation refer to the Note
section in the PMBus command summary. Clock stretching is enabled by asserting bit 1 of MFR_CONFIG_ALL.
For a description of the minor extensions and exceptions
PMBus makes to SMBus, refer to PMBus Specification
Part 1 Revision 1.2: Paragraph 5: Transport.
For a description of the differences between SMBus
and I2C, refer to System Management Bus (SMBus)
Specification Version 2.0: Appendix B—Differences
Between SMBus and I2C.
40
PMBus SERIAL DIGITAL INTERFACE
The LTM4680 communicates with a host (master) using
the standard PMBus serial bus interface. The Timing
Diagram, Figure 6, shows the timing relationship of the
signals on the bus. The two-bus lines, SDA and SCL, must
be high when the bus is not in use. External pull-up resistors or current sources are required on these lines. The
LTM4680 is a slave device. The master can communicate
with the LTM4680 using the following formats:
Master Transmitter, Slave Receiver
n
Master Receiver, Slave Transmitter
n
The following PMBus protocols are supported:
Write Byte, Write Word, Send Byte
n
Read Byte, Read Word, Block Read, Block Write
n
Alert Response Address
n
Figures 7 to 24 illustrate the aforementioned PMBus
protocols. All transactions support PEC and GCP (group
command protocol). The Block Read supports 255 bytes
of returned data. For this reason, the PMBus timeout may
be extended when reading the fault log.
Figure 7 is a key to the protocol diagrams in this section.
PEC is optional.
A value shown below a field in the following figures is
mandatory value for that field.
The data formats implemented by PMBus are:
Master transmitter transmits to slave receiver. The
transfer direction in this case is not changed.
n
n
n
Master reads slave immediately after the first byte. At
the moment of the first acknowledgment (provided by
the slave receiver) the master transmitter becomes
a master receiver and the slave receiver becomes a
slave transmitter.
Combined format. During a change of direction within
a transfer, the master repeats both a start condition
and the slave address but with the R/W bit reversed.
In this case, the master receiver terminates the transfer by generating a NACK on the last byte of the transfer and a STOP condition.
Rev. B
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LTM4680
OPERATION
Refer to Figure 7 for a legend.
Handshaking features are included to ensure robust system communication. Please refer to the PMBus Communication
and Command Processing subsection of the Applications Information section for further details.
SDA
tf
tLOW
tr
tSU(DAT)
tHD(SDA)
tf
tSP
tr
tBUF
SCL
tHD(STA)
tHD(DAT)
tSU(STA)
tHIGH
tSU(STO)
4680 F06
START
CONDITION
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
Figure 6. PMBus Timing Diagram
Table 6. Abbreviations of Supported Data Formats
PMBus
TERMINOLOGY
SPECIFICATION
ADI
REFERENCE
TERMINOLOGY DEFINITION
EXAMPLE
Floating point 16-bit data: value = Y • 2N,
b[15:0] = 0x9807 = 10011_000_0000_0111
value = 7 • 2–13 = 854E-6
L11
Linear
Part II ¶7.1
Linear_5s_1s
L16
Linear
VOUT_MODE
Part II ¶8.2
Linear_16u
Floating point 16-bit data: value = Y • 2–12,
where Y = b[15:0], an unsigned integer
b[15:0] = 0x4C00 = 0100_1100_0000_0000
value = 19456 • 2–12 = 4.75
CF
DIRECT
Part II ¶7.2
Varies
16-bit data with a custom format defined in
the detailed PMBus command description
Often an unsigned or two’s compliment
integer
Reg
Register Bits
Part II ¶10.3
Reg
Per-bit meaning defined in detailed PMBus
command description
PMBus STATUS_BYTE command
ASC
Text Characters
Part II ¶22.2.1
ASCII
ISO/IEC 8859-1 [A05]
LTC (0x4C5443)
where N = b[15:11] and Y = b[10:0], both
two’s compliment binary integers
Rev. B
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41
LTM4680
OPERATION
FIGURES 7 TO 24 PMBus PROTOCOLS
S
START CONDITION
Sr
REPEATED START CONDITION
Rd
READ (BIT VALUE OF 1)
Wr
WRITE (BIT VALUE OF 0)
A
ACKNOWLEDGE (THIS BIT POSITION MAY BE 0
FOR AN ACK OR 1 FOR A NACK)
P
STOP CONDITION
PEC PACKET ERROR CODE
MASTER TO SLAVE
SLAVE TO MASTER
...
CONTINUATION OF PROTOCOL
4680 F07
Figure 7. PMBus Packet Protocol Diagram Element Key
1
7
S
1
1
SLAVE ADDRESS Rd/Wr A
1
P
4680 F08
Figure 8. Quick Command Protocol
1
7
S
1
1
8
1
1
SLAVE ADDRESS Wr A COMMAND CODE A
P
4680 F09
Figure 9. Send Byte Protocol
1
S
7
1
1
8
1
SLAVE ADDRESS Wr A COMMAND CODE A
8
1
1
PEC
A
P
4680 F10
Figure 10. Send Byte Protocol with PEC
1
S
7
1
1
8
1
SLAVE ADDRESS Wr A COMMAND CODE A
8
1
1
DATA BYTE
A
P
F11
Figure 11. Write Byte Protocol
1
S
7
1
1
8
1
SLAVE ADDRESS Wr A COMMAND CODE A
8
1
8
1
DATA BYTE
A
PEC
A
1
P
4680 F12
Figure 12. Write Byte Protocol with PEC
1
S
7
1
1
8
1
SLAVE ADDRESS Wr A COMMAND CODE A
8
1
8
1
1
DATA BYTE LOW
A
DATA BYTE HIGH
A
P
4680 F13
Figure 13. Write Word Protocol
1
S
7
1
1
8
1
SLAVE ADDRESS Wr A COMMAND CODE A
8
1
8
1
8
1
1
DATA BYTE LOW
A
DATA BYTE HIGH
A
PEC
A
P
4680 F14
Figure 14. Write Word Protocol with PEC
42
Rev. B
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LTM4680
OPERATION
1
7
S
1
1
8
1
1
1
7
1
SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A
8
1
1
DATA BYTE
A
P
4680 F15
Figure 15. Read Byte Protocol
1
S
7
1
1
8
1
1
7
1
8
1
DATA BYTE
A
1
SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A
PEC
1
1
A
P
4680 F16
Figure 16. Read Byte Protocol with PEC
1
S
7
1
1
8
1
1
SLAVE ADDRESS Wr A COMMAND CODE A
7
1
1
Sr SLAVE ADDRESS Rd A
8
1
DATA BYTE LOW
A
1
1
DATA BYTE HIGH A
8
P
4680 F17
Figure 17. Read Word Protocol
1
S
7
1
1
8
1
1
7
1
1
SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A
8
1
DATA BYTE LOW
A
8
1
DATA BYTE HIGH A
8
1
1
PEC
A
P
4680 F18
Figure 18. Read Word Protocol with PEC
1
S
7
1
1
8
1
1
7
1
1
SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A
8
1
BYTE COUNT = N A
8
1
8
1 …
8
1
DATA BYTE 1
A
DATA BYTE 2
A …
DATA BYTE N
A
…
1
P
4680 F19
Figure 19. Block Read Protocol
1
S
7
1
1
8
1
1
7
1
1
SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A
8
1
BYTE COUNT = N A
8
1
8
1 …
8
1
8
1
1
DATA BYTE 1
A
DATA BYTE 2
A …
DATA BYTE N
A
PEC
A
P
…
4680 F20
Figure 20. Block Read Protocol with PEC
Rev. B
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43
LTM4680
OPERATION
1
S
7
1
1
8
1
8
1
SLAVE ADDRESS Wr A COMMAND CODE A BYTE COUNT = M A
8
1
DATA BYTE 2
1
7
1
8
A …
1
Sr SLAVE ADDRESS Rd A
8
1
DATA BYTE 1
A
…
1
A …
DATA BYTE M
8
1
BYTE COUNT = N A
8
1
1
DATA BYTE 1
A
…
8
1 …
8
1
1
DATA BYTE 2
A …
DATA BYTE N
A
P
4680 F21
Figure 21. Block Write – Block Read Process Call
1
S
7
1
1
8
1
8
1
SLAVE ADDRESS Wr A COMMAND CODE A BYTE COUNT = M A
8
1
DATA BYTE 2
1
7
1
8
A …
1
Sr SLAVE ADDRESS Rd A
8
1
DATA BYTE 1
A
…
1
DATA BYTE M
8
A …
1
BYTE COUNT = N A
8
1
1
DATA BYTE 1
A
…
8
1 …
8
1
8
1
1
DATA BYTE 2
A …
DATA BYTE N
A
PEC
A
P
4680 F22
Figure 22. Block Write – Block Read Process Call with PEC
1
7
1
1
8
1
1
S ALERT RESPONSE Rd A DEVICE ADDRESS A
ADDRESS
P
4680 F23
Figure 23. Alert Response Address Protocol
1
7
1
1
8
1
S ALERT RESPONSE Rd A DEVICE ADDRESS A
ADDRESS
8
1
1
PEC
A
P
4680 F24
Figure 24. Alert Response Address Protocol with PEC
44
Rev. B
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LTM4680
PMBus COMMAND SUMMARY
PMBus COMMANDS
Table 7 lists supported PMBus commands and manufacturer specific commands. A complete description of
these commands can be found in the “PMBus Power
System Mgt Protocol Specification – Part II – Revision
1.2”. Users are encouraged to reference this specification. Exceptions or manufacturer specific implementations are listed in Table 7. Floating point values listed in
the “DEFAULT VALUE” column are either Linear 16-bit
Signed (PMBus Section 8.3.1) or Linear_5s_11s (PMBus
Section 7.1) format, whichever is appropriate for the command. All commands from 0xD0 through 0xFF not listed in
Table 7 are implicitly reserved by the manufacturer. Users
should avoid blind writes within this range of commands
to avoid undesired operation of the part. All commands
from 0x00 through 0xCF not listed in Table 7 are implicitly
not supported by the manufacturer. Attempting to access
non-supported or reserved commands may result in a
CML command fault event. All output voltage settings and
measurements are based on the VOUT_MODE setting of
0x14. This translates to an exponent of 2–12.
If PMBus commands are received faster than they are
being processed, the part may become too busy to handle
new commands. In these circumstances the part follows
the protocols defined in the PMBus Specification v1.2,
Part II, Section 10.8.7, to communicate that it is busy.
The part includes handshaking features to eliminate busy
errors and simplify error handling software while ensuring robust communication and system behavior. Please
refer to the subsection titled PMBus Communication and
Command Processing in the Applications Information
section for further details.
Table 7. PMBus Commands Summary (Note: The Data Format Abbreviations Are Detailed in Table 8)
COMMAND NAME
CMD
CODE DESCRIPTION
PAGE
0x00
Provides integration with multi-page
PMBus devices.
R/W Byte
N
Reg
OPERATION
0x01
Operating mode control. On/off, margin
high and margin low.
R/W Byte
Y
Reg
ON_OFF_CONFIG
0x02
RUN pin and PMBus bus on/off command
configuration.
R/W Byte
Y
Reg
CLEAR_FAULTS
0x03
Clear any fault bits that have been set.
Send Byte
N
PAGE_PLUS_WRITE
0x05
Write a command directly to a
specified page.
W Block
N
77
PAGE_PLUS_READ
0x06
Read a command directly from a
specified page.
Block R/W
N
77
WRITE_PROTECT
0x10
Level of protection provided by the device
against accidental changes.
R/W Byte
N
STORE_USER_ALL
0x15
Store user operating memory to EEPROM.
Send Byte
RESTORE_USER_ALL
0x16
Restore user operating memory from
EEPROM.
Send Byte
CAPABILITY
0x19
Summary of PMBus optional communication
protocols supported by this device.
R Byte
N
Reg
SMBALERT_MASK
0x1B
Mask ALERT activity
Block R/W
Y
Reg
VOUT_MODE
0x20
Output voltage format and exponent (2–12).
VOUT_COMMAND
0x21
VOUT_MAX
0x24
TYPE
DATA
PAGED FORMAT UNITS NVM
Reg
DEFAULT
VALUE
PAGE
0x00
77
Y
0x80
81
Y
0x1E
81
NA
106
Y
0x00
78
N
NA
117
N
NA
117
0xB0
105
See CMD
106
2–12
87
Y
R Byte
Y
Reg
Nominal output voltage set point.
R/W Word
Y
L16
V
Y
1.0
0x1000
88
Upper limit on the commanded output
voltage including VOUT_MARGIN_HI.
R/W Word
Y
L16
V
Y
3.6
0x399A
87
0x14
Rev. B
For more information www.analog.com
45
LTM4680
PMBus COMMAND SUMMARY
COMMAND NAME
CMD
CODE DESCRIPTION
VOUT_MARGIN_HIGH
0x25
Margin high output voltage set point. Must
be greater than VOUT_COMMAND.
R/W Word
Y
L16
V
Y
1.05
0x10CD
88
VOUT_MARGIN_LOW
0x26
Margin low output voltage set point. Must
be less than VOUT_COMMAND.
R/W Word
Y
L16
V
Y
0.95
0x0F33
88
VOUT_TRANSITION_ RATE
0X27
Rate the output changes when VOUT
commanded to a new value.
R/W Word
Y
L11
V/ms
Y
0.001
0x8042
94
FREQUENCY_SWITCH
0x33
Switching frequency of the controller.
R/W Word
N
L11
kHz
Y
350kHz
0xFABC
85
VIN_ON
0x35
Input voltage at which the unit should start R/W Word
power conversion.
N
L11
V
Y
4.75
0xD130
86
VIN_OFF
0x36
Input voltage at which the unit should stop
power conversion.
R/W Word
N
L11
V
Y
4.5
0xD120
86
VOUT_OV_FAULT_LIMIT
0x40
Output overvoltage fault limit.
R/W Word
Y
L16
V
Y
1.1
0x119A
87
VOUT_OV_FAULT_
RESPONSE
0x41
Action to be taken by the device when an
output overvoltage fault is detected.
R/W Byte
Y
Reg
Y
0xB8
96
VOUT_OV_WARN_LIMIT
0x42
Output overvoltage warning limit.
R/W Word
Y
L16
V
Y
1.075
0x1133
87
VOUT_UV_WARN_LIMIT
0x43
Output undervoltage warning limit.
R/W Word
Y
L16
V
Y
0.925
0x0ECD
88
VOUT_UV_FAULT_LIMIT
0x44
Output undervoltage fault limit.
R/W Word
Y
L16
V
Y
0.9
0x0E66
88
VOUT_UV_FAULT_
RESPONSE
0x45
Action to be taken by the device when an
output undervoltage fault is detected.
R/W Byte
Y
Reg
Y
0xB8
97
IOUT_OC_FAULT_LIMIT
0x46
Output overcurrent fault limit.
R/W Word
Y
L11
Y
40.00
0xE280
90
IOUT_OC_FAULT_ RESPONSE
0x47
Action to be taken by the device when an
output overcurrent fault is detected.
R/W Byte
Y
Reg
Y
0x00
99
IOUT_OC_WARN_LIMIT
0x4A
Output overcurrent warning limit.
R/W Word
Y
L11
A
Y
35.0
0xE230
91
OT_FAULT_LIMIT
0x4F
External overtemperature fault limit.
R/W Word
Y
L11
C
Y
128.0
0xF200
92
OT_FAULT_RESPONSE
0x50
Action to be taken by the device when an
external overtemperature fault is detected,
R/W Byte
Y
Reg
Y
0xB8
101
OT_WARN_LIMIT
0x51
External overtemperature warning limit.
R/W Word
Y
L11
C
Y
125.0
0xEBE8
92
UT_FAULT_LIMIT
0x53
External undertemperature fault limit.
R/W Word
Y
L11
C
Y
–45.0
0xE530
93
UT_FAULT_RESPONSE
0x54
Action to be taken by the device when
an external undertemperature fault is
detected.
R/W Byte
Y
Reg
Y
0xB8
101
VIN_OV_FAULT_LIMIT
0x55
Input supply overvoltage fault limit.
R/W Word
N
L11
Y
15.5
0xD3E0
85
VIN_OV_FAULT_ RESPONSE
0x56
Action to be taken by the device when an
input overvoltage fault is detected.
R/W Byte
Y
Reg
Y
0x80
96
VIN_UV_WARN_LIMIT
0x58
Input supply undervoltage warning limit.
R/W Word
N
L11
V
Y
4.65
0xD12A
86
IIN_OC_WARN_LIMIT
0x5D
Input supply overcurrent warning limit.
R/W Word
N
L11
A
Y
20.0
0xDA80
91
46
TYPE
DATA
PAGED FORMAT UNITS NVM
A
V
DEFAULT
VALUE
PAGE
Rev. B
For more information www.analog.com
LTM4680
PMBus COMMAND SUMMARY
COMMAND NAME
CMD
CODE DESCRIPTION
TON_DELAY
0x60
Time from RUN and/or Operation on to
output rail turn-on.
R/W Word
Y
L11
ms
Y
0.0
0x8000
93
TON_RISE
0x61
Time from when the output starts to rise
until the output voltage reaches the VOUT
commanded value.
R/W Word
Y
L11
ms
Y
3.0
0xC300
93
TON_MAX_FAULT_LIMIT
0x62
Maximum time from the start of
TON_RISE for VOUT to cross the
VOUT_UV_FAULT_LIMIT.
R/W Word
Y
L11
ms
Y
5.0
0xCA80
94
TON_MAX_FAULT_
RESPONSE
0x63
Action to be taken by the device when a
TON_ MAX_FAULT event is detected.
R/W Byte
Y
Reg
Y
0xB8
99
TOFF_DELAY
0x64
Time from RUN and/or Operation off to the R/W Word
start of TOFF_FALL ramp.
Y
L11
ms
Y
0.0
0x8000
94
TOFF_FALL
0x65
Time from when the output starts to fall
until the output reaches zero volts.
R/W Word
Y
L11
ms
Y
3.0
0xC300
94
TOFF_MAX_WARN_ LIMIT
0x66
Maximum allowed time, after TOFF_FALL
completed, for the unit to decay below
12.5%.
R/W Word
Y
L11
ms
Y
0
0x8000
95
STATUS_BYTE
0x78
One byte summary of the unit’s fault
condition.
R/W Byte
Y
Reg
NA
107
STATUS_WORD
0x79
Two byte summary of the unit’s fault
condition.
R/W Word
Y
Reg
NA
108
STATUS_VOUT
0x7A
Output voltage fault and warning status.
R/W Byte
Y
Reg
NA
109
STATUS_IOUT
0x7B
Output current fault and warning status.
R/W Byte
Y
Reg
NA
110
STATUS_INPUT
0x7C
Input supply fault and warning status.
R/W Byte
N
Reg
NA
110
STATUS_TEMPERATURE
0x7D
External temperature fault and warning
status for READ_TEMERATURE_1.
R/W Byte
Y
Reg
NA
110
STATUS_CML
0x7E
Communication and memory fault and
warning status.
R/W Byte
N
Reg
NA
111
STATUS_MFR_SPECIFIC
0x80
Manufacturer specific fault and state
information.
R/W Byte
Y
Reg
NA
111
READ_VIN
0x88
Measured input supply voltage.
R Word
N
L11
V
NA
113
READ_IIN
0x89
Measured input supply current.
R Word
N
L11
A
NA
114
READ_VOUT
0x8B
Measured output voltage.
R Word
Y
L16
V
NA
113
READ_IOUT
0x8C
Measured output current.
R Word
Y
L11
A
NA
114
READ_TEMPERATURE_1
0x8D
External temperature sensor temperature.
This is the value used for all temperature
related processing, including
IOUT_CAL_GAIN.
R Word
Y
L11
C
NA
114
READ_TEMPERATURE_2
0x8E
Internal die junction temperature. Does
not affect any other commands.
R Word
N
L11
C
NA
114
READ_FREQUENCY
0x95
Measured PWM switching frequency.
R Word
Y
L11
Hz
NA
114
READ_POUT
0x96
Measured output power
R Word
Y
L11
W
N/A
114
READ_PIN
0x97
Calculated input power
R Word
Y
L11
W
N/A
114
PMBus_REVISION
0x98
PMBus revision supported by this device.
Current revision is 1.2.
R Byte
N
Reg
0x22
105
MFR_ID
0x99
The manufacturer ID of the LTM4680 in
ASCII.
R String
N
ASC
ADI
105
MFR_MODEL
0x9A
Manufacturer part number in ASCII.
R String
N
ASC
LTM4680
105
TYPE
DATA
PAGED FORMAT UNITS NVM
DEFAULT
VALUE
PAGE
Rev. B
For more information www.analog.com
47
LTM4680
PMBus COMMAND SUMMARY
COMMAND NAME
CMD
CODE DESCRIPTION
MFR_VOUT_MAX
0xA5
Maximum allowed output voltage
including VOUT_OV_FAULT_LIMIT.
R Word
Y
L16
MFR_PIN_ACCURACY
0xAC
Returns the accuracy of the READ_PIN
command
R Byte
N
%
USER_DATA_00
0xB0
OEM RESERVED. Typically used for part
serialization.
R/W Word
N
Reg
USER_DATA_01
0xB1
Manufacturer reserved for LTpowerPlay.
R/W Word
Y
USER_DATA_02
0xB2
OEM RESERVED. Typically used for part
serialization
R/W Word
USER_DATA_03
0xB3
An NVM word available for the user.
USER_DATA_04
0xB4
An NVM word available for the user.
MFR_EE_UNLOCK
0xBD Contact factory.
122
MFR_EE_ERASE
0xBE
Contact factory.
122
MFR_EE_DATA
0xBF
Contact factory.
122
MFR_CHAN_CONFIG
0xD0
Configuration bits that are channel
specific.
MFR_CONFIG_ALL
0xD1
MFR_FAULT_ PROPAGATE
0xD2
MFR_PWM_COMP
MFR_PWM_MODE
TYPE
DATA
PAGED FORMAT UNITS NVM
V
DEFAULT
VALUE
PAGE
3.6
0x399A
89
5.0%
115
Y
NA
105
Reg
Y
NA
105
N
Reg
Y
NA
105
R/W Word
Y
Reg
Y
0x0000
105
R/W Word
N
Reg
Y
0x0000
105
R/W Byte
Y
Reg
Y
General configuration bits.
R/W Byte
N
Reg
Y
0x21
80
Configuration that determines which faults
are propagated to the FAULT pin.
R/W Word
Y
Reg
Y
0x6993
102
0xD3
PWM loop compensation configuration
R/W Byte
Y
Reg
Y
0x28
83
0xD4
Configuration for the PWM engine.
R/W Byte
Y
Reg
Y
0x47
82
MFR_FAULT_RESPONSE
0xD5
Action to be taken by the device when the
FAULT pin is externally asserted low.
R/W Byte
Y
Reg
Y
0xC0
104
MFR_OT_FAULT_ RESPONSE
0xD6
Action to be taken by the device when an
internal overtemperature fault is detected.
R Byte
N
Reg
0xC0
100
MFR_IOUT_PEAK
0xD7
Report the maximum measured
value of READ_ IOUT since last
MFR_CLEAR_PEAKS.
R Word
Y
L11
NA
115
MFR_ADC_CONTROL
0xD8
ADC telemetry parameter selected for
repeated fast ADC read back
R/W Byte
N
Reg
0x00
116
MFR_RETRY_DELAY
0xDB Retry interval during FAULT retry mode.
R/W Word
Y
L11
ms
Y
250.0
0xF3E8
95
MFR_RESTART_DELAY
0xDC Minimum time the RUN pin is held low by
the LTM4680.
R/W Word
Y
L11
ms
Y
150.0
0xF258
95
MFR_VOUT_PEAK
0xDD Maximum measured value of READ_VOUT
since last MFR_CLEAR_PEAKS.
R Word
Y
L16
V
NA
115
MFR_VIN_PEAK
0xDE
Maximum measured value of READ_VIN
since last MFR_CLEAR_PEAKS.
R Word
N
L11
V
NA
115
MFR_TEMPERATURE_1_ PEAK
0xDF
Maximum measured value of external
Temperature (READ_TEMPERATURE_1)
since last MFR_CLEAR_PEAKS.
R Word
Y
L11
C
NA
115
MFR_READ_IIN_PEAK
0xE1
Maximum measured value of READ_IIN
command since last MFR_CLEAR_PEAKS
R Word
N
L11
A
NA
115
MFR_CLEAR_PEAKS
0xE3
Clears all peak values.
Send Byte
N
NA
107
MFR_READ_ICHIP
0xE4
Measured supply current of the SVIN pin
R Word
N
L11
NA
115
MFR_PADS
0xE5
Digital status of the I/O pads.
R Word
N
Reg
NA
112
48
A
A
0x1D
79
Rev. B
For more information www.analog.com
LTM4680
PMBus COMMAND SUMMARY
COMMAND NAME
CMD
CODE DESCRIPTION
TYPE
MFR_ADDRESS
0xE6
Sets the 7-bit I2C address byte.
MFR_SPECIAL_ID
0xE7
Manufacturer code representing the
LTM4680 and revision
MFR_IIN_CAL_GAIN
0xE8
MFR_FAULT_LOG_ STORE
0xEA
MFR_INFO
0x
DATA
PAGED FORMAT UNITS NVM
R/W Byte
N
Reg
R Word
N
Reg
The resistance value of the input current
sense element in mΩ.
R/W Word
N
L11
Command a transfer of the fault log from
RAM to EEPROM.
Send Byte
N
R Word
Y
Send Byte
N
Y
mΩ
Y
DEFAULT
VALUE
PAGE
0x4F
79
0x414X
105
1.0
0xBA00
91
NA
118
Contact factory.
122
MFR_IOUT_CAL_GAIN
0xDA SET AT FACTORY
L11
MFR_FAULT_LOG_ CLEAR
0xEC
Initialize the EEPROM block reserved for
fault logging.
MFR_FAULT_LOG
0xEE
Fault log data bytes.
R Block
N
Reg
MFR_COMMON
0xEF
Manufacturer status bits that are common
across multiple ADI chips.
R Byte
N
Reg
MFR_COMPARE_USER_ ALL
0xF0
Compares current command contents
with NVM.
Send Byte
N
MFR_TEMPERATURE_2_ PEAK
0xF4
Peak internal die temperature since last
MFR_ CLEAR_PEAKS.
R Word
N
L11
MFR_PWM_CONFIG
0xF5
Set numerous parameters for the DC/DC
controller including phasing.
R/W Byte
N
Reg
MFR_IOUT_CAL_GAIN_ TC
0xF6
Temperature coefficient of the current
sensing element.
R/W Word
Y
CF
MFR_ICHIP_CAL_GAIN
0xF7
The resistance value of the VIN pin filter
element in mΩ.
R/W Word
N
L11
MFR_TEMP_1_GAIN
0xF8
Sets the slope of the external temperature
sensor.
R/W Word
Y
CF
MFR_TEMP_1_OFFSET
0xF9
Sets the offset of the external temperature
sensor with respect to –273.1°C
R/W Word
Y
L11
MFR_RAIL_ADDRESS
0xFA
Common address for PolyPhase outputs
to adjust common parameters.
R/W Byte
Y
Reg
MFR_REAL_TIME
0xFB
48-bit share-clock counter value.
R Block
N
CF
MFR_RESET
0xFD
Commanded reset without requiring a
power down.
Send Byte
N
mΩ
89
NA
122
NA
118
NA
112
NA
117
NA
116
Y
0x10
84
ppm/
˚C
Y
3800
0x0ED8
89
mΩ
Y
1000
0x03E8
86
Y
0.995
0x3FAE
92
Y
0.0
0x8000
92
Y
0x80
79
NA
66
NA
81
Y
C
C
Note 1: Commands indicated with Y in the NVM column indicate that these commands are stored and restored using the STORE_USER_ALL and
RESTORE_USER_ALL commands, respectively.
Note 2: Commands with a default value of NA indicate “not applicable”. Commands with a default value of FS indicate “factory set on a per part basis”.
Note 3: The LTM4680 contains additional commands not listed in Table 7. Reading these commands is harmless to the operation of the IC; however, the
contents and meaning of these commands can change without notice.
Note 4: Some of the unpublished commands are read-only and will generate a CML bit 6 fault if written.
Note 5: Writing to commands not published in Table 7 is not permitted.
Note 6: The user should not assume compatibility of commands between different parts based upon command names. Always refer to the manufacturer’s
data sheet for each part for a complete definition of a command’s function. ADI strives to keep command functionality compatible between all ADI
devices. Differences may occur to address specific product requirements.
Rev. B
For more information www.analog.com
49
LTM4680
PMBus COMMAND SUMMARY
Table 8. Data Format Abbreviations
L11
Linear_5s_11s
PMBus data field b[15:0]
Value = Y • 2N
where N = b[15:11] is a 5-bit two’s complement integer and Y = b[10:0] is an 11-bit two’s complement integer
Example:
For b[15:0] = 0x9807 = ‘b10011_000_0000_0111
Value = 7 • 2–13 = 854 • 10–6
From “PMBus Spec Part II: Paragraph 7.1”
L16
Linear_16u
PMBus data field b[15:0]
Value = Y • 2N
where Y = b[15:0] is an unsigned integer and N = VOUT_MODE_PARAMETER is a 5-bit two’s complement exponent that is
hardwired to –12 decimal
Example:
For b[15:0] = 0x9800 = ‘b1001_1000_0000_0000
Value = 19456 • 2–12 = 4.75 From “PMBus Spec Part II: Paragraph 8.2”
Reg
Register
PMBus data field b[15:0] or b[7:0].
Bit field meaning is defined in detailed PMBus Command Description.
L16
Integer Word
PMBus data field b[15:0]
Value = Y
where Y = b[15:0] is a 16-bit unsigned integer
Example:
For b[15:0] = 0x9807 = ‘b1001_1000_0000_0111
Value = 38919 (decimal)
CF
Custom Format
Value is defined in detailed PMBus Command Description.
This is often an unsigned or two’s complement integer scaled by an MFR specific constant.
ASC
ASCII Format
A variable length string of text characters conforming to ISO/IEC 8859-1 standard.
50
Rev. B
For more information www.analog.com
LTM4680
APPLICATIONS INFORMATION
VIN TO VOUT STEP-DOWN RATIOS
OUTPUT CAPACITORS
There are restrictions in the maximum VIN and VOUT stepdown ratio that can be achieved for a given input voltage.
Each output of the LTM4680 is capable of 95% duty cycle
at 500kHz, but the VIN to VOUT minimum dropout is still
a function of its load current and will limit output current
capability related to high duty cycle on the topside switch.
The LTM4680 is designed for low output voltage ripple
noise and good transient response. The bulk output
capacitors defined as COUT are chosen with low enough
effective series resistance (ESR) to meet the output voltage ripple and transient requirements. COUT can be a low
ESR tantalum capacitor, a low ESR polymer capacitor or
ceramic capacitor. The typical output capacitance range
for each output is from 400µF to 1000µF. Additional output filtering may be required by the system designer, if
further reduction of output ripple or dynamic transient
spikes is required. Table 13 shows a matrix of different
output voltages and output capacitors to minimize the
voltage droop and overshoot during a 15A to 30A step,
15A/µs transient each channel. Table 13 optimizes total
equivalent ESR and total bulk capacitance to optimize the
transient performance. Stability criteria are considered
in the Table 13 matrix, and the LTPowerCAD Design Tool
will be provided for stability analysis. Multiphase operation reduces effective output ripple as a function of the
number of phases. Application Note 77 discusses this
noise reduction versus output ripple current cancellation, but the output capacitance should be considered
carefully as a function of stability and transient response.
The LTPowerCAD Design Tool can calculate the output
ripple reduction as the number of implemented phases
increases by N times. A small value 10Ω resistor can be
placed in series from VOUTn to the VOSNS0+ pin to allow
for a bode plot analyzer to inject a signal into the control
loop and validate the regulator stability. The LTM4680’s
stability compensation can be adjusted using two external
capacitors, and the MFR_PWM_COMP commands.
Minimum on-time tON(MIN) is another consideration in
operating at a specified duty cycle while operating at a
certain frequency due to the fact that tON(MIN) < D/fSW,
where D is duty cycle and fSW is the switching frequency.
tON(MIN) is specified in the electrical parameters as 60ns.
See Note 6 in the Electrical Characteristics section for
output current guideline.
INPUT CAPACITORS
The LTM4680 module should be connected to a low AC
impedance DC source. For the regulator input, four 22µF
input ceramic capacitors are used to handle the RMS
ripple current. A 47µF to 150µF surface mount aluminum
electrolytic bulk capacitor can be used for more input
bulk capacitance. This bulk input capacitor is only needed
if the input source impedance is compromised by long
inductive leads, traces or not enough source capacitance.
If low impedance power planes are used, then this bulk
capacitor is not needed.
For a buck converter, the switching duty-cycle can be
estimated as:
Dn =
VOUTn
VINn
Without considering the inductor current ripple, for each
output, the RMS current of the input capacitor can be
estimated as:
ICINn (RMS) =
IOUTn (MAX)
η%
• Dn • (1− Dn )
In the above equation, η% is the estimated efficiency of the
power module. The bulk capacitor can be a switcher-rated
electrolytic aluminum capacitor, or a polymer capacitor.
LIGHT LOAD CURRENT OPERATION
The LTM4680 has two modes of operation including high
efficiency, discontinuous conduction mode or forced
continuous conduction mode. The mode of operation is
configured by bit 0 of the MFR_PWM_MODEn command
(discontinuous conduction is always the start-up mode,
forced continuous is the default running mode).
If a channel is enabled for discontinuous mode operation, the inductor current is not allowed to reverse. The
Rev. B
For more information www.analog.com
51
LTM4680
APPLICATIONS INFORMATION
reverse current comparator, IREV, turns off the bottom
MOSFET (MBn) just before the inductor current reaches
zero, preventing it from reversing and going negative.
Thus, the controller can operate in discontinuous (pulseskipping) operation. In forced continuous operation, the
inductor current is allowed to reverse at light loads or
under large transient conditions. The peak inductor current is determined solely by the voltage on the COMPna
pin. In this mode, the efficiency at light loads is lower than
in discontinuous mode operation. However, continuous
mode exhibits lower output ripple and less interference
with audio circuitry. Forced continuous conduction mode
may result in reverse inductor current, which can cause
the input supply to boost. The VIN_OV_FAULT_LIMIT can
detect this (if SVIN is connected to VIN0 and/or VIN1) and
turn off the offending channel. However, this fault is based
on an ADC read and can nominally take up to 100ms to
detect. If there is a concern about the input supply boosting, keep the part in discontinuous conduction operation.
SWITCHING FREQUENCY AND PHASE
The switching frequency of the LTM4680’s channels is
established by its analog phase-locked-loop (PLL) locking on to the clock present at the module’s SYNC pin. The
clock waveform on the SYNC pin can be generated by
the LTM4680’s internal circuitry when an external pull-up
resistor to 3.3V (e.g., VDD33) is provided, in combination
with the LTM4680 control IC’s FREQUENCY_SWITCH
command being set to one of the following supported values: 250kHz, 350kHz, 425kHz, 500kHz, 575kHz, 650kHz,
750kHz, 1000kHz. In this configuration, the module is
called a “sync master”: (using the factory-default setting
of MFR_ CONFIG_ALL[4] = 0b), SYNC becomes a bidirectional open-drain pin, and the LTM4680 pulls SYNC logic
low for nominally 500ns at a time, at the prescribed clock
rate. The SYNC signal can be bused to other LTM4680
modules (configured as “sync slaves”), for purposes of
synchronizing switching frequencies of multiple modules
within a system—but only one LTM4680 should be configured as a “sync master”; the other LTM4680(s) should
be configured as “sync slaves”.
The most straightforward way is to set its FREQUENCY_
SWITCH command to 0x0000 and MFR_CONFIG_
52
ALL[4] = 1b. This can be easily implemented with resistor
pin-strap settings on the FSWPH_CFG pin (see Table 3).
Using MFR_CONFIG_ALL[4] = 1b, the LTM4680s SYNC
pin becomes a high impedance input, only—i.e., it does
not drive SYNC low. The module synchronizes its frequency to that of the clock applied to its SYNC pin. The
only shortcoming of this approach is: in the absence of
an externally applied clock, the switching frequency of
the module will default to the low end of its frequencysynchronization capture range (~225kHz).
If fault-tolerance to the loss of an externally applied SYNC
clock is desired, the FREQUENCY_SWITCH command of
a “sync slave” can be left at the nominal target switching
frequency of the application, and not 0x0000 However,
it is then still necessary to configure MFR_CONFIG_
ALL[4] = 1b. With this combination of configurations,
the LTM4680’s SYNC pin becomes a high impedance
input and the module synchronizes its frequency to
that of the externally applied clock, provided that the
frequency of the externally applied clock exceeds ~½.
of the target frequency (FREQUENCY_SWITCH). If the
SYNC clock is absent, the module responds by operating
at its target frequency, indefinitely. If and when the SYNC
clock is restored, the module automatically phase-locks
to the SYNC clock as normal. The only shortcoming of
this approach is: the EEPROM must be configured per
above guidance; resistor pin-strapping options on the
FSWPH_CFG pin alone cannot provide fault-tolerance to
the absence of the SYNC clock.
The FREQUENCY_SWITCH register can be altered via I2C
commands, but only when switching action is disengaged,
i.e., the module’s outputs are turned off. The FREQUENCY_
SWITCH command takes on the value stored in NVM at
SVIN power-up, but is overridden according to a resistor pin-strap applied between the FSWPH_CFG pin and
SGND only if the module is configured to respect resistor
pin-strap settings (MFR_CONFIG_ALL[6] = 0b). Table 3
highlights available resistor pin-strap and corresponding
FREQUENCY_SWITCH settings.
The relative phasing of all active channels in a PolyPhase
rail should be optimally phased. The relative phasing of
each rail is 360°/n, where n is the number of phases in the
rail. MFR_PWM_CONFIG[2:0] configures channel relative
Rev. B
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phasing with respect to the SYNC pin. Phase relationship
values are indicated with 0° corresponding to the falling
edge of SYNC being coincident with the turn-on of the
top MOSFETs.
The MFR_PWM_CONFIG command can be altered via
I2C commands, but only when switching action is disengaged, i.e., the module’s outputs are turned off. The
MFR_PWM_CONFIG command takes on the value stored
in NVM at SVIN power-up, but is overridden according
to a resistor pin-strap applied between the FSWPH_CFG
pin and SGND only if the module is configured to respect
resistor pin-strap settings (MFR_CONFIG_ALL[6] = 0b).
Table 3 highlights available resistor pin-strap and corresponding MFR_PWM_CONFIG[2:0] settings.
Some combinations of FREQUENCY_SWITCH and
MFR_PWM_CONFIG[2:0] are not available by resistor
pin-strapping the FSWPH_CFG pin. All combinations of
supported values for FREQUENCY_SWITCH and MFR_
PWM_CONFIG[2:0] can be configured by NVM programming—or, I2C transactions, provided switching action is
disengaged, i.e., the module’s outputs are turned off.
Care must be taken to minimize capacitance on SYNC
to assure that the pull-up resistor versus the capacitor
load has a low enough time constant for the application
to form a “clean” clock. (See “Open-Drain Pins”, later in
this section.)
When an LTM4680 is configured as a sync slave, it is permissible for external circuitry to drive the SYNC pin from
a current-limited source (less than 10mA), rather than
using a pull-up resistor. Any external circuitry must not
drive high with arbitrarily low impedance at SVIN powerup, because the SYNC output can be low impedance until
NVM contents have been downloaded to RAM.
Recommended LTM4680 switching frequencies of operation for many common VIN-to-VOUT applications are
indicated below. When the two channels of an LTM4680
are stepping input voltage(s) down to output voltages
whose recommended switching frequencies below are
significantly different, operation at the higher of the two
recommended switching frequencies is preferable, but
minimum on-time must be considered. (See Minimum
On-Time Considerations section.)
Table 9. Recommended Switching Frequency for Various VINto-VOUT Step-Down Scenarios
5VIN
0.9VOUT
1.0VOUT
1.2VOUT
1.5VOUT
1.8VOUT
8VIN
12VIN
250kHz to 350kHz
350kHz to 500kHz
500kHz to 575kHz
2.5VOUT
575kHz to 750kHz
3.3VOUT
650kHz to 1000kHz
OUTPUT CURRENT LIMIT PROGRAMMING
The cycle-by-cycle current limit (= VISENSE/DCR) is proportional to COMPn, which can be programmed from 1.45V
to 2.2V using the PMBus command IOUT_OC_FAULT_
LIMIT. The LTM4680 uses only the sub-milliohm sensing
to detect current levels. See page 90. The LTM4680
has two ranges of current limit programming. The value
of MFR_PWM_MODE[2] is reserved and the MFR_PWM_
MODE[7], and IOUT_OC_FAULT_LIMIT are used to set
the current limit level, see the section of the PMBus commands, the device can regulate output voltage with the
peak current under the value of IOUT_OC_FAULT_LIMIT
in normal operation. In case of output current exceeding
that current limit, a OC fault will be issued. Each of the
IOUT_OC_FAULT_LIMIT ranges will affect the loop gain,
and subsequently affect the loop stability, so setting the
range of current limiting is a part of loop design.
The LTPowerCAD Design Tool can be used to look at the
loop stability changes if current limit is adjusted. The
LTM4680 will automatically update the current limit as the
inductor temperature changes. Keep in mind this operation is on a cycle-by-cycle basis and is only a function of
the peak inductor current. The average inductor current
is monitored by the ADC converter and can provide a
warning if too much average output current is detected.
The overcurrent fault is detected when the COMPn voltage
hits the maximum value. The digital processor within the
LTM4680 provides the ability to either ignore the fault,
shut down and latch off or shut down and retry indefinitely
(hiccup). Refer to the overcurrent portion of the Operation
section for more detail. The Read_POUT can be used to
readback calculated output power.
Rev. B
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LTM4680
APPLICATIONS INFORMATION
MINIMUM ON-TIME CONSIDERATIONS
Minimum on-time, tON(MIN), is the smallest time duration that the LTM4680 is capable of turning on the top
MOSFET. It is determined by internal timing delays and the
gate charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
tON(MIN) <
VOUTn
VINn • fOSC
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The minimum on-time for the LTM4680 is 60ns.
VARIABLE DELAY TIME, SOFT-START AND OUTPUT
VOLTAGE RAMPING
The LTM4680 must enter its run state prior to soft-start.
The RUNn pins are released after the part initializes and
SVIN is greater than the VIN_ON threshold. If multiple
LTM4680s are used in an application, they should be configured to share the same RUNn pins. They all hold their
respective RUNn pins low until all devices initialize and
SVIN exceeds the VIN_ON threshold for all devices. The
SHARE_CLK pin assures all the devices connected to the
signal use the same time base.
After the RUNn pin releases, the controller waits for the
user-specified turn-on delay (TON_DELAYn) prior to initiating an output voltage ramp. Multiple LTM4680s and
other ADI parts can be configured to start with variable
delay times. To work correctly, all devices use the same
timing clock (SHARE_CLK) and all devices must share
the RUNn pin.
This allows the relative delay of all parts to be synchronized. The actual variation in the delay will be dependent
on the highest clock rate of the devices connected to the
SHARE_CLK pin (all Analog Devices ICs are configured
to allow the fastest SHARE_CLK signal to control the timing of all devices). The SHARE_CLK signal can be ±10%
54
in frequency, thus the actual time delays will have some
variance.
Soft-start is performed by actively regulating the load
voltage while digitally ramping the target voltage from 0V
to the commanded voltage set point. The rise time of the
voltage ramp can be programmed using the TON_RISEn
command to minimize inrush currents associated with the
start-up voltage ramp. The soft-start feature is disabled
by setting TON_RISEn to any value less than 0.250ms.
The LTM4680 performs the necessary math internally to
assure the voltage ramp is controlled to the desired slope.
However, the voltage slope can not be any faster than the
VOUTn fundamental limits of the power stage. The number
of tON(MIN) steps in the ramp is equal to TON_RISE/0.1ms.
Therefore, the shorter the TON_RISEn time setting, the
more discrete steps in the soft-start ramp appear.
The LTM4680 PWM always operates in discontinuous
mode during the TON_RISEn operation. In discontinuous
mode, the bottom MOSFET (MBn) is turned off as soon
as reverse current is detected in the inductor. This allows
the regulator to start up into a pre-biased load.
There is no analog tracking feature in the LTM4680; however, two outputs can be given the same TON_RISEn and
TON_DELAYn times to achieve ratiometric rail tracking.
Because the RUNn pins are released at the same time and
both units use the same time base (SHARE_CLK), the
outputs track very closely. If the circuit is in a PolyPhase
configuration, all timing parameters must be the same.
DIGITAL SERVO MODE
For maximum accuracy in the regulated output voltage,
enable the digital servo loop by asserting bit 6 of the
MFR_PWM_MODE command. In digital servo mode, the
LTM4680 will adjust the regulated output voltage based
on the ADC voltage reading. Every 90ms the digital servo
loop will step the LSB of the DAC (nominally 1.375mV or
0.6875mV depending on the voltage range bit) until the
output is at the correct ADC reading. At power-up this
mode engages after TON_MAX_FAULT_LIMIT unless the
limit is set to 0 (infinite). If the TON_MAX_FAULT_LIMIT is
set to 0 (infinite), the servo begins after TON_RISE is complete and VOUT has exceeded the VOUT_UV_FAULT_LIMIT.
Rev. B
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This same point in time is when the output changes from
discontinuous to the programmed mode as indicated in
MFR_PWM_MODE bit 0. Refer to Figure 25 for details on
the VOUT waveform under time-based sequencing. If the
TON_MAX_FAULT_LIMIT is set to a value greater than 0
and the TON_MAX_FAULT_RESPONSE is set to ignore
0x00, the servo begins:
1. After the TON_RISE sequence is complete
2. After the TON_MAX_FAULT_LIMIT time is reached;
and
3. After the VOUT_UV_FAULT_LIMIT has been exceed
or the IOUT_OC_FAULT_LIMIT is no longer active.
If the TON_MAX_FAULT_LIMIT is set to a value greater
than 0 and the TON_MAX_FAULT_RESPONSE is not set
to ignore 0x00, the servo begins:
1. After the TON_RISE sequence is complete
2. After the TON_MAX_FAULT_LIMIT time has expired
and both VOUT_UV_FAULT and IOUT_OC_FAULT are
not present.
The maximum rise time is limited to 1.3 seconds.
In a PolyPhase configuration it is recommended only one
of the control loops have the digital servo mode enabled.
This will assure the various loops do not work against each
other due to slight differences in the reference circuits.
SOFT OFF (SEQUENCED OFF)
In addition to a controlled start-up, the LTM4680 also
supports controlled turn-off. The TOFF_DELAY and TOFF_
FALL functions are shown in Figure 26. TOFF_FALL is
processed when the RUN pin goes low or if the part is
commanded off. If the part faults off or FAULTn is pulled
low externally and the part is programmed to respond
to this, the output will three-state rather than exhibiting
a controlled ramp. The output will decay as a function
of the load. The output voltage will operate as shown
in Figure 26 as long as the part is in forced continuous mode and the TOFF_FALL time is sufficiently slow
that the power stage can achieve the desired slope. The
TOFF_FALL time can only be met if the power stage and
controller can sink sufficient current to assure the output
is at zero volts by the end of the fall time interval. If the
TOFF_FALL time is set shorter than the time required to
discharge the load capacitance, the output will not reach
the desired zero volt state. At the end of TOFF_FALL, the
controller will cease to sink current and VOUT will decay
at the natural rate determined by the load impedance. If
the controller is in discontinuous mode, the controller will
not pull negative current and the output will be pulled low
by the load, not the power stage. The maximum fall time
is limited to 1.3 seconds. The shorter TOFF_FALL time is
set, the larger the discrete steps in the TOFF_FALL ramp
will appear. The number of steps in the ramp is equal to
TOFF_FALL/0.1ms.
DIGITAL SERVO
MODE ENABLED FINAL OUTPUT
VOLTAGE REACHED
TON_MAX_FAULT_LIMIT
DAC VOLTAGE
ERROR (NOT
TO SCALE)
VOUT
TON_DELAY
TON_RISE
TIME DELAY OF
200-400ms
VOUT
TOFF_DELAY
TIME
TOFF_FALL
TIME
4680 F26
4680 F25
Figure 25. Timing Controlled VOUT Rise
Figure 26. TOFF_DELAY and TOFF_FALL
Rev. B
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LTM4680
APPLICATIONS INFORMATION
UNDERVOLTAGE LOCKOUT
The LTM4680 is initialized by an internal threshold-based
UVLO where VIN must be approximately 4V and INTVCC,
VDD33, and VDD25 must be within approximately 20% of
their regulated values. In addition, VDD33 must be within
approximately 7% of the targeted value before the RUN
pin is released. After the part has initialized, an additional
comparator monitors VIN. The VIN_ON threshold must be
exceeded before the power sequencing can begin. When
VIN drops below the VIN_OFF threshold, the SHARE_CLK
pin will be pulled low and VIN must increase above the
VIN_ON threshold before the controller will restart. The
normal start-up sequence will be allowed after the VIN_
ON threshold is crossed. If FAULTn is held low when VIN
is applied, ALERT will be asserted low even if the part is
programmed to not assert ALERT when FAULTn is held
low. If I2C communication occurs before the LTM4680 is
out of reset and only a portion of the command is seen by
the part, this can be interpreted as a CML fault. If a CML
fault is detected, ALERT is asserted low.
It is possible to program the contents of the NVM in
the application if the VDD33 supply is externally driven
directly to VDD33 or through EXTVCC. This will activate
the digital portion of the LTM4680 without engaging
the high voltage sections. PMBus communications are
valid in this supply configuration. If VIN has not been
applied to the LTM4680, bit 3 (NVM Not Initialized) in
MFR_COMMON will be asserted low. If this condition is
detected, the part will only respond to addresses 0x5A
and 0x5B. To initialize the part issue the following set of
commands: global address 0x5B command 0xBD data
0x2B followed by global address 0x5B command 0xBD
and data 0xC4. The part will now respond to the correct address. Configure the part as desired then issue a
STORE_USER_ALL. When VIN is applied a MFR_RESET
command must be issued to allow the PWM to be enabled
and valid ADC conversions to be read.
can be pulled low by external sources indicating a fault in
some other portion of the system. The fault response is
configurable and allows the following options:
Ignore
n
Shut Down Immediately—Latch Off
n
Shut Down Immediately—Retry Indefinitely at the
Time Interval Specified in MFR_RETRY_DELAY
n
Refer to the PMBus section of the data sheet and the
PMBus specification for more details.
The OV response is automatic. If an OV condition is
detected, TGn goes low and BGn is asserted.
Fault logging is available on the LTM4680. The fault logging is configurable to automatically store data when a
fault occurs that causes the unit to fault off. The header
portion of the fault logging table contains peak values. It
is possible to read these values at any time. This data will
be useful while troubleshooting the fault.
If the LTM4680 internal temperature is in excess of 85°C,
writes into the NVM (other than fault logging) are not
recommended. The data will still be held in RAM, unless
the 3.3V supply UVLO threshold is reached. If the die
temperature exceeds 130°C all NVM communication is
disabled until the die temperature drops below 120°C.
OPEN-DRAIN PINS
The LTM4680 has the following open-drain pins:
3.3V Pins
1. FAULTn
2. SYNC
3. SHARE_CLK
4. PGOODn
5V Pins (5V pins operate correctly when pulled to 3.3V.)
FAULT DETECTION AND HANDLING
1. RUNn
The LTM4680 FAULT pins are configurable to indicate a
variety of faults including OV, UV, OC, OT, timing faults,
and peak over current faults. In addition, the FAULT pins
3. SCL
56
2. ALERT
4. SDA
Rev. B
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All the above pins have on-chip pull-down transistors that
can sink 3mA at 0.4V. The low threshold on the pins is
0.8V; thus, there is plenty of margin on the digital signals
with 3mA of current. For 3.3V pins, 3mA of current is
a 1.1k resistor. Unless there are transient speed issues
associated with the RC time constant of the resistor pullup and parasitic capacitance to ground, a 10k resistor or
larger is generally recommended.
For high speed signals such as the SDA, SCL and SYNC,
a lower value resistor may be required. The RC time constant should be set to 1/3 to 1/5 the required rise time
to avoid timing issues. For a 100pF load and a 400kHz
PMBus communication rate, the rise time must be less
than 300ns. The resistor pull-up on the SDA and SCL pins
with the time constant set to 1/3 the rise time is:
RPULLUP =
tRISE
= 1k
3 •100pF
The closest 1% resistor value is 1k. Be careful to minimize
parasitic capacitance on the SDA and SCL pins to avoid
communication problems. To estimate the loading capacitance, monitor the signal in question and measure how
long it takes for the desired signal to reach approximately
63% of the output value. This is a one time constant. The
SYNC pin has an on-chip pull-down transistor with the
output held low for nominally 500ns. If the internal oscillator is set for 500kHz and the load is 100pF and a 3x time
constant is required, the resistor calculation is as follows:
RPULLUP =
2µs – 500ns
= 5k
3 •100pF
The closest 1% resistor is 4.99k.
If timing errors are occurring or if the SYNC frequency is
not as fast as desired, monitor the waveform and determine if the RC time constant is too long for the application. If possible reduce the parasitic capacitance. If not,
reduce the pull-up resistor sufficiently to assure proper
timing. The SHARE_CLK pull-up resistor has a similar
equation with a period of 10µs and a pull-down time of
1µs. The RC time constant should be approximately 3µs
or faster.
PHASE-LOCKED LOOP AND FREQUENCY
SYNCHRONIZATION
The LTM4680 has a phase-locked loop (PLL) comprised
of an internal voltage-controlled oscillator (VCO) and a
phase detector. The PLL is locked to the falling edge of
the SYNC pin. The phase relationship between the PWM
controller and the falling edge of SYNC is controlled by
the lower 3 bits of the MFR_PWM_ CONFIG command.
For PolyPhase applications, it is recommended that all
the phases be spaced evenly. Thus for a 2-phase system
the signals should be 180° out of phase and a 4-phase
system should be spaced 90°.
The phase detector is an edge-sensitive digital type that
provides a known phase shift between the external and
internal oscillators. This type of phase detector does not
exhibit false lock to harmonics of the external clock.
The output of the phase detector is a pair of complementary current sources that charge or discharge the internal
filter network. The PLL lock range is guaranteed between
200kHz and 1MHz. Nominal parts will have a range beyond
this; however, operation to a wider frequency range is not
guaranteed.
The PLL has a lock detection circuit. If the PLL should
lose lock during operation, bit 4 of the STATUS_MFR_
SPECIFIC command is asserted and the ALERT pin is
pulled low. The fault can be cleared by writing a 1 to the
bit. If the user does not wish to see the ALERT pin assert
if a PLL_FAULT occurs, the SMBALERT_MASK command
can be used to prevent the alert.
If the SYNC signal is not clocking in the application, the
nominal programmed frequency will control the PWM
circuitry. However, if multiple parts share the SYNC pins
and the signal is not clocking, the parts will not be synchronized and excess voltage ripple on the output may be
present. Bit 10 of MFR_PADS will be asserted low if this
condition exists.
If the PWM signal appears to be running at too high a
frequency, monitor the SYNC pin. Extra transitions on
the falling edge will result in the PLL trying to lock on to
noise versus the intended signal. Review routing of digital
control signals and minimize crosstalk to the SYNC signal
Rev. B
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57
LTM4680
APPLICATIONS INFORMATION
to avoid this problem. Multiple LTM4680s are required
to share one SYNC pin in PolyPhase configurations.
For other configurations, connecting the SYNC pins to
form a single SYNC signal is optional. If the SYNC pin
is shared between LTM4680s, only one LTM4680 can
be programmed with a frequency output. All the other
LTM4680s should be programmed to disable the SYNC
output. However their frequency should be programmed
to the nominal desired value.
INPUT CURRENT SENSE AMPLIFIER
The LTM4680 input current sense amplifier can sense the
supply current into the VIN0 and VIN1 power stages pins
using an external sense resistor as shown in the Figure 2
Block Diagram. The RSENSE value can be programmed
using the MFR_IIN_CAL_GAIN command. Kelvin sensing
is recommended across the RSENSE resistor to eliminate
errors. The MFR_PWM_CONFIG [6:5] sets the input current sense amplifier gain. See the MFR_PWM_CONFIG
section. The IIN_OC_WARN_LIMIT command sets the
value of the input current measured by the ADC, in
amperes, that causes a warning indicating the input current is high. The READ_IIN value will be used to determine
if this limit has been exceeded. The READ_IIN command
returns the input current, in Amperes, as measured across
the input current sense resistor.
There is an IR voltage drop from the supply to the SVIN
pin due to the current flowing into the SVIN pin. To compensate for this voltage drop, the MFR_RVIN will be
automatically set to the 1Ω internal sense resistor in the
Figure 2 Block Diagram. The LTM4680 will multiply the
MFR_READ_ICHIP measurement value by this 1Ω resistor and add this voltage to the measured voltage at the
SVIN pin. Therefore, READ_VIN = VSVIN_PIN + (MFR_
READ_ICHIP • 1Ω) The MFR_READ_ICHIP command is
used to measure the internal controller current. Using
the READ_PIN command allows for reading calculated
input power.
change. The error amplifier gain gm varies from 1.0mmho
to 5.73mmho, and the compensation resistor RCOMPn
varies from 0kΩ to 62kΩ inside the controller. Two compensation capacitors, COMPna and COMPnb, are required
in the design and the typical ratio between COMPna and
COMPnb is 10. Also see Figure 2 Block Diagram and
Figure 27.
By adjusting the gm and RCOMPn only, the LTM4680 can
provide a flexible Type II compensation network to optimize the loop over a wide range of output capacitors.
Adjusting the gm will change the gain of the compensation
over the whole frequency range without moving the pole
and zero location, as shown in Figure 28.
Adjusting the RCOMP will change the pole and zero location, as shown in Figure 29. It is recommended that the
user determines the appropriate value for the gm and
RCOMPn using the LTPowerCAD tool.
gm
RCOMPn
COMPna
COMPnb
CCOMPL
CCOMPH
+
VREF
–
FB
4680 F27
Figure 27. Programmable Loop Compensation
TYPE II COMPENSATION
GAIN
INCREASE gm
PROGRAMMABLE LOOP COMPENSATION
FREQUENCY
The LTM4680 offers programmable loop compensation
to optimize the transient response without any hardware
58
4680 F28
Figure 28. Error Amp gm Adjust
Rev. B
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TYPE II COMPENSATION
GAIN
INCREASE RCOMPn
FREQUENCY
4680 F29
Figure 29. RCOMP Adjust
CHECKING TRANSIENT RESPONSE
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, VOUT shifts by an
amount equal to ∆ILOAD(ESR), where ESR is the effective
series resistance of COUT. ∆ILOAD also begins to charge or
discharge COUT generating the feedback error signal that
forces the regulator to adapt to the current change and
return VOUT to its steady-state value. During this recovery time VOUT can be monitored for excessive overshoot
or ringing, which would indicate a stability problem. The
availability of the COMP pin not only allows optimization
of control loop behavior but also provides a DC-coupled
and AC-filtered closed-loop response test point. The DC
step, rise time and settling at this test point truly reflects
the closed-loop response. Assuming a predominantly
second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot
seen at this pin. The bandwidth can also be estimated by
examining the rise time at the pin. The COMPna external
capacitor shown in the Typical Application circuit will provide an adequate starting point for most applications. The
programmable parameters that affect loop gain are the
voltage range, bit[1] of the MFR_PWM_MODE command,
the current range bit[7] of the MFR_PWM_MODE command, the gm of the PWM channel amplifier bits [7:5] of
MFR_PWM_COMP, and the internal RCOMP compensation
resistor, bits[4:0] of MFR_PWM_COMP. Be sure to establish these settings prior to compensation calculation.
The COMPna series internal RCOMPn and external CCOMPna
filter sets the dominant pole-zero loop compensation.
The internal RCOMPn value can be modified (from 0Ω to
62kΩ) using bits[4:0] of the MFR_PWM_ COMP command. Adjust the value of RCOMPn to optimize transient
response once the final PCB layout is done and the particular CCOMPnb filter capacitor and output capacitor type
and value have been determined. The output capacitors
need to be selected because the various types and values
determine the loop gain and phase. An output current
pulse of 20% to 80% of full-load current having a rise
time of 1µs to 10µs will produce output voltage and COMP
pin waveforms that will give a sense of the overall loop
stability without breaking the feedback loop. Placing a
power MOSFET with a resistor to ground directly across
the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce to a
load step. The MOSFET + RSERIES will produce output currents approximately equal to VOUT/RSERIES. RSERIES values from 0.1Ω to 2Ω are valid depending on the current
limit settings and the programmed output voltage. The
initial output voltage step resulting from the step change
in output current may not be within the bandwidth of the
feedback loop, so this signal cannot be used to determine
phase margin. This is why it is better to look at the COMP
pin signal which is in the feedback loop and is the filtered
and compensated control loop response. The gain of the
loop will be increased by increasing RCOMP. If RCOMP is
increased by the same factor that CCOMPL is decreased,
the zero frequency will be kept the same, thereby keeping
the phase shift the same in the most critical frequency
range of the feedback loop. The gain of the loop will be
proportional to the transconductance of the error amplifier which is set using bits[7:5] of the MFR_PWM_COMP
command. The output voltage settling behavior is related
to the stability of the closed-loop system and will demonstrate the actual overall supply performance. A second,
more severe transient is caused by switching in loads with
large (>1µF) supply bypass capacitors. The discharged
bypass capacitors are effectively put in parallel with COUT,
causing a rapid drop in VOUT. No regulator can alter its
delivery of current quickly enough to prevent this sudden
step change in output voltage if the load switch resistance
is low and it is driven quickly. If the ratio of CLOAD to
Rev. B
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LTM4680
APPLICATIONS INFORMATION
COUT is greater than 1:50, the switch rise time should be
controlled so that the load rise time is limited to approximately 25 • CLOAD. Thus a 10µF capacitor would require
a 250µs rise time, limiting the charging current to about
200mA.
PolyPhase Configuration
When configuring a PolyPhase rail with multiple
LTM4680s, the user must share the SYNC, COMP, SHARE_
CLK, FAULT, and ALERT pins of these parts. Be sure to
use pull-up resistors on FAULT, SHARE_CLK and ALERT.
One of the part’s SYNC pins must be set to the desired
switching frequency, and all other FREQUENCY_SWITCH
commands must be set to External Clock. If an external
oscillator is provided, set the FREQUENCY_SWITCH command to External Clock for all parts. The relative phasing
of all the channels should be spaced equally. The MFR_
RAIL_ ADDRESS of all the devices should be set to the
same value.
Multiple channels need to tie all the VOSNSn+ pins
together, and all the VOSNSn– pins together, COMPna and
COMPnb pins together as well. Do not assert bit[4] of
MFR_CONFIG_ALL except in a PolyPhase application. See
application example Figure 47.
CONNECTING THE USB TO I2C/SMBUS/PMBUS
CONTROLLER TO THE LTM4680 IN SYSTEM
The ADI USB-to-I2C/SMBus/PMBus adapter (DC1613A or
equivalent) can be interfaced to the LTM4680 on the user’s
board for programming, telemetry and system debug.
The adapter, when used in conjunction with LTpowerPlay,
provides a powerful way to debug an entire power system. Faults are quickly diagnosed using telemetry, fault
status commands and the fault log. The final configuration can be quickly developed and stored to the LTM4680
EEPROM. Figure 30 illustrates the application schematic
for powering, programming and communication with
one or more LTM4680s via the ADI I2C/SMBus/PMBus
adapter regardless of whether or not system power is
present. If system power is not present, the dongle will
power the LTM4680 through the VDD33 supply pin. To
initialize the part when VIN is not applied and the VDD33
pin is powered, use global address 0x5B command 0xBD
data 0x2B followed by address 0x5B command 0xBD data
0xC4. The LTM4680 can now communicate with the internal EEPROM and read the project file. To write the updated
project file to the NVM issue a STORE_USER _ALL command. When VIN is applied, a MFR_RESET must be issued
to allow the PWM POWER to be enabled and valid ADCs
to be read.
VIN
LTC
CONTROLLER
HEADER
ISOLATED
3.3V
SDA
100k
100k
VIN
VDD33
TP0101K
SCL
1µF
10k
VDD25
1µF
LTM4680
SDA
10k
SCL
WP
PGND/SGND
TO LTC DC1613
USB TO I2C/SMBus/PMBus
CONTROLLER
VIN
TP0101K
VDD33
1µF
VDD25
1µF
LTM4680
SDA
VGS MAX ON THE TP0101K IS 8V IF VIN > 16V
CHANGE THE RESISTOR DIVIDER ON THE PFET GATE
SCL
WP
PGND/SGND
4680 F30
Figure 30. Controller Connection
60
Rev. B
For more information www.analog.com
LTM4680
APPLICATIONS INFORMATION
Because of the adapter’s limited current sourcing capability, only the LTM4680s, their associated pull-up resistors
and the I2C pull-up resistors should be powered from
the VDD33 3.3V supply. In addition any device sharing
the I2C bus connections with the LTM4680 should not
have body diodes between the SDA/SCL pins and their
respective VDD node because this will interfere with bus
communication in the absence of system power. If VIN is
applied, the DC1613A will not supply the power to the
LTM4680s on the board. It is recommended the RUNn
pins be held low or no voltage configuration resistors
inserted to avoid providing power to the load until the
part is fully configured.
The LTM4680 is fully isolated from the host PC’s ground
by the DC1613A.The 3.3V from the adapter and the
LTM4680 VDD33 pin must be driven to each LTM4680 with
a separate PFET. If both VIN and EXTVCC are not applied,
the VDD33 pins can be in parallel because the on-chip
LDO is off. The controller 3.3V current limit is 100mA but
typical VDD33 currents are under 15mA. The VDD33 does
back drive the INTVCC/EXTVCC pin. Normally this is not
an issue if VIN is open.
LTpowerPlay: AN INTERACTIVE GUI FOR DIGITAL
POWER
LTpowerPlay (Figure 31) is a powerful Windows-based
development environment that supports Analog Devices
digital power system management ICs including the
LTM4680. The software supports a variety of different tasks. LTpowerPlay can be used to evaluate Analog
Devices ICs by connecting to a demo board or the user
application. LTpowerPlay can also be used in an offline
mode (with no hardware present) in order to build multiple IC configuration files that can be saved and reloaded
at a later time. LTpowerPlay provides unprecedented diagnostic and debug features. It becomes a valuable diagnostic tool during board bring-up to program or tweak the
power system or to diagnose power issues when bring up
rails. LTpowerPlay utilizes Analog Devices’s USB-to-I2C/
SMBus/PMBus adapter to communication with one of
the many potential targets including the DC2844A demo
board, the DC2298A socketed programming board, or a
customer target system. The software also provides an
automatic update feature to keep the revisions current
with the latest set of device drivers and documentation.
A great deal of context sensitive help is available with
LTpowerPlay along with several tutorial demos. Complete
information is available at LTpowerPlay.
PMBus COMMUNICATION AND COMMAND
PROCESSING
The LTM4680 has a one deep buffer to hold the last data
written for each supported command prior to processing
as shown in Figure 32, Write Command Data Processing.
When the part receives a new command from the bus,
it copies the data into the Write Command Data Buffer,
indicates to the internal processor that this command data
needs to be fetched, and converts the command to its
internal format so that it can be executed. Two distinct
parallel blocks manage command buffering and command
processing (fetch, convert, and execute) to ensure the last
data written to any command is never lost. Command
data buffering handles incoming PMBus writes by storing the command data to the Write Command Data Buffer
and marking these commands for future processing. The
internal processor runs in parallel and handles the sometimes slower task of fetching, converting and executing
commands marked for processing. Some computationally intensive commands (e.g., timing parameters, temperatures, voltages and currents) have internal processor execution times that may be long relative to PMBus
timing. If the part is busy processing a command, and
new command(s) arrive, execution may be delayed or
processed in a different order than received. The part indicates when internal calculations are in process via bit 5 of
MFR_COMMON (“calculations not pending”). When the
part is busy calculating, bit 5 is cleared. When this bit is
set, the part is ready for another command. An example
polling loop is provided in Figure 33 which ensures that
commands are processed in order while simplifying error
handling routines.
When the part receives a new command while it is busy,
it will communicate this condition using standard PMBus
protocol. Depending on part configuration it may either
NACK the command or return all ones (0xFF) for reads. It
may also generate a BUSY fault and ALERT notification,
Rev. B
For more information www.analog.com
61
LTM4680
APPLICATIONS INFORMATION
Figure 31. LTpowerPlay Screen Shot
CMD
PMBus
WRITE
WRITE COMMAND
DATA BUFFER
DECODER
CMDS
DATA
MUX
CALCULATIONS
PENDING
S
R
PAGE
•
•
•
VOUT_COMMAND
0x00
0x21
•
•
•
MFR_RESET
INTERNAL
PROCESSOR
FETCH,
CONVERT
DATA
AND
EXECUTE
0xFD
x1
4680 F32
Figure 32. Write Command Data Processing
62
Rev. B
For more information www.analog.com
LTM4680
APPLICATIONS INFORMATION
or stretch the SCL clock low. For more information refer
to PMBus Specification v1.1, Part II, Section 10.8.7
and SMBus v2.0 section 4.3.3. Clock stretching can be
enabled by asserting bit 1 of MFR_CONFIG_ ALL. Clock
stretching will only occur if enabled and the bus communication speed exceeds 100kHz.
is to create a SAFE_WRITE_BYTE() and SAFE_WRITE_
WORD() subroutine. The above polling mechanism allows
your software to remain clean and simple while robustly
communicating with the part. For a detailed discussion of
these topics and other special cases please refer to Analog
Devices application notes.
// wait until chip is not busy
do
{
mfrCommonValue = PMBUS_READ_BYTE(0xEF);
partReady = (mfrCommonValue & 0x68) == 0x68;
}while(!partReady)
When communicating using bus speeds at or below
100kHz, the polling mechanism shown here provides a
simple solution that ensures robust communication without clock stretching. At bus speeds in excess of 100kHz,
it is strongly recommended that the part be configured to
enable clock stretching. This requires a PMBus master that
supports clock stretching. System software that detects
and properly recovers from the standard PMBus NACK/
BUSY faults as described in the PMBus Specification v1.1,
Par II, Section 10.8.7 is required to communicate The
LTM4680 is not recommended in applications with bus
speeds in excess of 400kHz.
// now the part is ready to receive the next
command
PMBUS_WRITE_WORD(0x21, 0x2000); //write VOUT_
COMMAND to 2V
Figure 33. Example of a Command Write of VOUT_COMMAND
PMBus busy protocols are well accepted standards, but
can make writing system level software somewhat complex. The part provides three ‘hand shaking’ status bits
which reduce complexity while enabling robust system
level communication.
The three hand shaking status bits are in the MFR_
COMMON register. When the part is busy executing an
internal operation, it will clear bit 6 of MFR_COMMON
(‘chip not busy’). When the part is busy specifically because
it is in a transitional VOUT state (margining hi/lo, power off/
on, moving to a new output voltage set point, etc.) it will
clear bit 4 of MFR_COMMON (‘output not in transition’).
When internal calculations are in process, the part will clear
bit 5 of MFR_COMMON (‘calculations not pending’). These
three status bits can be polled with a PMBus read byte of
the MFR_COMMON register until all three bits are set. A
command immediately following the status bits being set
will be accepted without NACKing or generating a BUSY
fault/ALERT notification. The part can NACK commands
for other reasons, however, as required by the PMBus spec
(for instance, an invalid command or data). An example of a
robust command write algorithm for the VOUT_COMMAND
register is provided in Figure 33.
It is recommended that all command writes (write byte,
write word, etc.) be preceded with a polling loop to avoid
the extra complexity of dealing with busy behavior and
unwanted ALERT notification. A simple way to achieve this
THERMAL CONSIDERATIONS AND OUTPUT
CURRENT DERATING
The thermal resistances reported in the Pin Configuration
section of this data sheet are consistent with those
parameters defined by JESD51-12 and are intended for
use with finite element analysis (FEA) software modeling tools that leverage the outcome of thermal modeling,
simulation, and correlation to hardware evaluation performed on a µModule package mounted to a hardware
test board defined by JESD51-9 (“Test Boards for Area
Array Surface Mount Package Thermal Measurements”).
The motivation for providing these thermal coefficients is
found in JESD51-12 (“Guidelines for Reporting and Using
Electronic Package Thermal Information”).
Many designers may opt to use laboratory equipment
and a test vehicle such as the demo board to predict the
µModule regulator’s thermal performance in their application at various electrical and environmental operating
conditions to compliment any FEA activities. Without
FEA software, the thermal resistances reported in the
Pin Configuration section are in-and-of themselves not
relevant to providing guidance of thermal performance;
instead, the derating curves provided later in this data sheet
Rev. B
For more information www.analog.com
63
LTM4680
APPLICATIONS INFORMATION
can be used in a manner that yields insight and guidance
pertaining to one’s application-usage, and can be adapted
to correlate thermal performance to one’s own application.
The Pin Configuration section gives four thermal coefficients explicitly defined in JESD51-12; these coefficients
are quoted or paraphrased below:
1. θJA, the thermal resistance from junction to ambient,
is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed
enclosure. This environment is sometimes referred to
as “still air” although natural convection causes the
air to move. This value is determined with the part
mounted to a JESD51-9 defined test board, which
does not reflect an actual application or viable operating condition.
2. θJCbottom, the thermal resistance from junction to the
bottom of the product case, is determined with all
of the component power dissipation flowing through
the bottom of the package. In the typical µModule
regulator, the bulk of the heat flows out the bottom
of the package, but there is always heat flow out into
the ambient environment. As a result, this thermal
resistance value may be useful for comparing packages but the test conditions don’t generally match the
user’s application.
3. θJCtop, the thermal resistance from junction to top of
the product case, is determined with nearly all of the
component power dissipation flowing through the top
of the package. As the electrical connections of the
typical µModule regulator are on the bottom of the
package, it is rare for an application to operate such
that most of the heat flows from the junction to the top
of the part. As in the case of θJCbottom, this value may
be useful for comparing packages but the test conditions don’t generally match the user’s application.
4 θJB, the thermal resistance from junction to the printed
circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the
bottom of the µModule regulator and into the board,
and is really the sum of the θJCbottom and the thermal
resistance of the bottom of the part through the solder
joints and through a portion of the board. The board
temperature is measured a specified distance from
the package, using a two sided, two layer board. This
board is described in JESD51-9.
A graphical representation of the aforementioned thermal
resistances is given in Figure 34; blue resistances are
contained within the µModule regulator, whereas green
resistances are external to the µModule package.
As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD51-12 or provided in the Pin
Configuration section replicates or conveys normal operating conditions of a µModule regulator. For example, in
normal board-mounted applications, never does 100%
of the device’s total power loss (heat) thermally conduct
exclusively through the top or exclusively through bottom of the µModule package—as the standard defines
JUNCTION-TO-AMBIENT THERMAL RESISTANCE COMPONENTS
JUNCTION-TO-CASE (TOP)
RESISTANCE
JUNCTION
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION-TO-CASE
CASE (BOTTOM)-TO-BOARD
(BOTTOM) RESISTANCE
RESISTANCE
AMBIENT
BOARD-TO-AMBIENT
RESISTANCE
4680 F33
µModule DEVICE
Figure 34. Graphical Representation of JESD51-12 Thermal Coefficients
64
For more information www.analog.com
Rev. B
LTM4680
APPLICATIONS INFORMATION
for θJCtop and θJCbottom, respectively. In practice, power
loss is thermally dissipated in both directions away from
the package—granted, in the absence of a heat sink and
airflow, a majority of the heat flow is into the board.
Within the LTM4680, be aware there are multiple power
devices and components dissipating power, with a consequence that the thermal resistances relative to different junctions of components or die are not exactly linear
with respect to total package power loss. To reconcile this
complication without sacrificing modeling simplicity—
but also, not ignoring practical realities—an approach
has been taken using FEA software modeling along with
laboratory testing in a controlled-environment chamber
to reasonably define and correlate the thermal resistance
values supplied in this data sheet: (1) Initially, FEA software is used to accurately build the mechanical geometry
of the LTM4680 and the specified PCB with all of the correct material coefficients along with accurate power loss
source definitions; (2) this model simulates a softwaredefined JEDEC environment consistent with JESD51-9
and JESD51-12 to predict power loss heat flow and
temperature readings at different interfaces that enable
the calculation of the JEDEC-defined thermal resistance
values; (3) the model and FEA software is used to evaluate
the LTM4680 with heat sink and airflow; (4) having solved
for and analyzed these thermal resistance values and
simulated various operating conditions in the software
model, a thorough laboratory evaluation replicates the
simulated conditions with thermocouples within a controlled environment chamber while operating the device
at the same power loss as that which was simulated. The
outcome of this process and due diligence yields the set
of derating curves provided in later sections of this data
sheet, along with well-correlated JESD51-12-defined θ
values provided in the Pin Configuration section of this
data sheet.
The 5V, 8V and 12V power loss curves in Figure 35,
Figure 36 and Figure 37 respectively can be used in coordination with the load current derating curves in Figure 38
to Figure 43 for calculating an approximate θJA thermal
resistance for the LTM4680 with various heat sinking and
airflow conditions. These thermal resistances represent
demonstrated performance of the LTM4680 on hardware;
a 6-layer FR4 PCB measuring 99mm × 130mm × 1.6mm
using 2oz copper on all layers. The power loss curves
are taken at room temperature, and are increased with
multiplicative factors of 1.35 when the junction temperature reaches 125°C. The derating curves are plotted with
the LTM4680’s paralleled outputs initially sourcing up to
60A and the ambient temperature at 25°C. The output
voltages are 0.9V and 1.8V. These are chosen to include
the lower and higher output voltage ranges for correlating
the thermal resistance. Thermal models are derived from
several temperature measurements in a controlled temperature chamber along with thermal modeling analysis.
The junction temperatures are monitored while ambient
temperature is increased with and without airflow.
The power loss increase with ambient temperature change
is factored into the derating curves. The junctions are
maintained at 125°C maximum while lowering output current or power while increasing ambient temperature. The
decreased output current decreases the internal module
loss as ambient temperature is increased. The monitored
junction temperature of 125°C minus the ambient operating temperature specifies how much module temperature
rise can be allowed. As an example in Figure 40, the load
current is derated to ~50A at ~75°C ambient with no air
or heat sink and the room temperature (25°C) power loss
for this 12VIN to 0.9VOUT at 50AOUT condition is ~5W. A
6.75W loss is calculated by multiplying the ~5W room
temperature loss from the 12VIN to 0.9VOUT power loss
curve at 50A (Figure 37), with the 1.35 multiplying factor. If the 75°C ambient temperature is subtracted from
the 125°C junction temperature, then the difference of
50°C divided by 6.75W yields a thermal resistance, θJA,
of 7.4°C/W—in good agreement with Table 10. Tables 10
and 11 provide equivalent thermal resistances for 0.9V
and 1.8V outputs with and without airflow. The derived
thermal resistances in Tables 10 and 11 for the various
conditions can be multiplied by the calculated power loss
as a function of ambient temperature to derive temperature rise above ambient, thus maximum junction temperature. Room temperature power loss can be derived
from the efficiency curves in the Typical Performance
Characteristics section and adjusted with the above ambient temperature multiplicative factors.
Rev. B
For more information www.analog.com
65
LTM4680
APPLICATIONS INFORMATION
Tables 10 thru 11: Output Current Derating
Table 10. 0.9V Output
DERATING CURVE
Figure 38 to Figure 40
Figure 38 to Figure 40
Figure 38 to Figure 40
VIN (V)
5, 8, 12
5, 8, 12
5, 8, 12
POWER LOSS CURVE
Figure 35 to Figure 37
Figure 35 to Figure 37
Figure 35 to Figure 37
AIRFLOW (LFM)
0
200
400
HEAT SINK
None
None
None
θJA (°C/W)
7
6
5
VIN (V)
5, 8, 12
5, 8, 12
5, 8, 12
POWER LOSS CURVE
Figure 35 to Figure 37
Figure 35 to Figure 37
Figure 35 to Figure 37
AIRFLOW (LFM)
0
200
400
HEAT SINK
None
None
None
θJA (°C/W)
7
6
5
Table 11. 1.8V Output
DERATING CURVE
Figure 41 to Figure 43
Figure 41 to Figure 43
Figure 41 to Figure 43
Table 12. Channel Output Voltage vs Capacitor Selection, All Ceramic Configuration, 15A to 30A Load Step with 15A/µs Slew Rate
VIN
(V)
VOUT VOUT
ILIM
COUT
(V) RANGE RANGE (CER CAP)
COUT
(BULK
CAP)
CCOMP B
(pF)
CCOMP A
(nF)
RCOMP
(kΩ)
EA-GM
(mS)
fSW
(kHz)
PK-PK
RECOVERY
LOAD STEP DEVIATION
TIME
(A)
(mV)
(μS)
5
0.9
Low
Low
*330µFX7
None
68
3.3
11
5.04
250
15 to 30
104
40
12
0.9
Low
Low
*330µFX7
None
68
3.3
11
5.04
250
15 to 30
104
40
15
0.9
Low
Low
*330µFX7
None
68
3.3
11
5.04
250
15 to 30
105
40
5
1
Low
Low
*330µFX7
None
68
3.3
11
5.04
250
15 to 30
104
40
12
1
Low
Low
*330µFX7
None
68
3.3
11
5.04
250
15 to 30
104
40
15
1
Low
Low
*330µFX7
None
68
3.3
11
5.04
250
15 to 30
105
40
5
0.9
Low
Low
*330µFX6
None
68
3.3
9
5.76
350
15 to 30
102
30
12
0.9
Low
Low
*330µFX6
None
68
3.3
9
5.76
350
15 to 30
99
30
15
0.9
Low
Low
*330µFX6
None
68
3.3
9
5.76
350
15 to 30
100
30
5
1
Low
Low
*330µFX6
None
68
3.3
9
5.76
350
15 to 30
102
30
12
1
Low
Low
*330µFX6
None
68
3.3
9
5.76
350
15 to 30
102
30
15
1
Low
Low
*330µFX6
None
68
3.3
9
5.76
350
15 to 30
99
30
6
1.2
Low
Low
*330µFX5
None
68
3.3
9
5.76
350
15 to 30
115
30
12
1.2
Low
Low
*330µFX5
None
68
3.3
9
5.76
350
15 to 30
112
30
15
1.2
Low
Low
*330µFX5
None
68
3.3
9
5.76
350
15 to 30
110
30
6
1.5
Low
Low
*330µFX5
None
68
3.3
9
5.76
425
15 to 30
115
30
12
1.5
Low
Low
*330µFX5
None
68
3.3
9
5.76
425
15 to 30
109
30
15
1.5
Low
Low
*330µFX5
None
68
3.3
9
5.76
425
15 to 30
110
30
6
1.8
Low
Low
*330µFX5
None
68
3.3
5
5.76
500
15 to 30
141
25
12
1.8
Low
Low
*330µFX5
None
68
3.3
5
5.76
500
15 to 30
132
25
15
1.8
Low
Low
*330µFX5
None
68
3.3
5
5.76
500
15 to 30
132
25
6
2.5
Low
Low
*330µFX5
None
68
3.3
5
5.04
575
15 to 30
176
25
12
2.5
Low
Low
*330µFX5
None
68
3.3
5
5.04
575
15 to 30
146
25
15
2.5
Low
Low
*330µFX5
None
68
3.3
5
5.04
575
15 to 30
146
25
8
3.3
High
Low
*330µFX5
None
68
3.3
9
5.76
650
15 to 30
191
40
12
3.3
High
Low
*330µFX5
None
68
3.3
9
5.76
650
15 to 30
166
40
15
3.3
High
Low
*330µFX5
None
68
3.3
9
5.76
650
15 to 30
166
40
* Murata GRM32ER60G337ME05L, 330μF, 4V, X5R
66
Rev. B
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LTM4680
APPLICATIONS INFORMATION
Table 13. Channel Output Voltage vs Capacitor Selection, Bulk and Ceramic Cap Configuration, 15A to 30A Load Step with 15A/µs
Slew Rate
VIN
(V)
VOUT VOUT
ILIM
(V) RANGE RANGE
COUT
(CER CAP)
COUT
(BULK CAP)
CCOMP B
(pF)
CCOMP A
(nF)
RCOMP
(kΩ)
EA-GM
(mS)
PK-PK RECOVERY
fSW LOAD STEP DEVIATION
TIME
(kHz)
(A)
(mV)
(μS)
5
0.9
Low
Low
*100µFX4
**470µFX3
68
3.3
17
3.69
250
15 to 30
99
50
12
0.9
Low
Low
*100µFX4
**470µFX3
68
3.3
17
3.69
250
15 to 30
97
50
15
0.9
Low
Low
*100µFX4
**470µFX3
68
3.3
17
3.69
250
15 to 30
99
50
5
1
Low
Low
*100µFX5
**470µFX2
68
3.3
17
3.69
250
15 to 30
114
50
12
1
Low
Low
*100µFX5
**470µFX2
68
3.3
17
3.69
250
15 to 30
115
50
15
1
Low
Low
*100µFX5
**470µFX2
68
3.3
17
3.69
250
15 to 30
114
50
5
0.9
Low
Low
*100µFX4
**470µFX2
68
3.3
17
3.69
350
15 to 30
102
50
12
0.9
Low
Low
*100µFX4
**470µFX2
68
3.3
17
3.69
350
15 to 30
100
50
15
0.9
Low
Low
*100µFX4
**470µFX2
68
3.3
17
3.69
350
15 to 30
102
50
5
1
Low
Low
*100µFX4
**470µFX2
68
3.3
17
3.69
350
15 to 30
105
50
12
1
Low
Low
*100µFX4
**470µFX2
68
3.3
17
3.69
350
15 to 30
104
50
15
1
Low
Low
*100µFX4
**470µFX2
68
3.3
17
3.69
350
15 to 30
104
50
5
1.2
Low
Low
*100µFX4
**470µFX2
68
3.3
17
3.69
350
15 to 30
107
50
12
1.2
Low
Low
*100µFX4
**470µFX2
68
3.3
17
3.69
350
15 to 30
102
50
15
1.2
Low
Low
*100µFX4
**470µFX2
68
3.3
17
3.69
350
15 to 30
104
50
5
1.5
Low
Low
*100µFX4
**470µFX2
68
3.3
17
3.69
425
15 to 30
105
50
12
1.5
Low
Low
*100µFX4
**470µFX2
68
3.3
17
3.69
425
15 to 30
97
50
15
1.5
Low
Low
*100µFX4
**470µFX2
68
3.3
17
3.69
425
15 to 30
97
50
6
1.8
Low
Low
*100µFX4
**470µFX2
68
3.3
17
3.69
500
15 to 30
100
50
12
1.8
Low
Low
*100µFX4
**470µFX2
68
3.3
17
3.69
500
15 to 30
94
50
15
1.8
Low
Low
*100µFX4
**470µFX2
68
3.3
17
3.69
500
15 to 30
95
50
6
2.5
Low
Low
*100µFX4
***470µFX2
68
3.3
20
1.68
575
15 to 30
156
80
12
2.5
Low
Low
*100µFX4
***470µFX2
68
3.3
20
1.68
575
15 to 30
136
80
15
2.5
Low
Low
*100µFX4
***470µFX2
68
3.3
20
1.68
575
15 to 30
136
80
6
3.3
High
Low
*100µFX4
***470µFX2
68
3.3
20
3.02
650
15 to 30
177
80
12
3.3
High
Low
*100µFX4
***470µFX2
68
3.3
20
3.02
650
15 to 30
144
80
15
3.3
High
Low
*100µFX4
***470µFX2
68
3.3
20
3.02
650
15 to 30
141
80
* Murata GRM32ER60G337ME05L, 330μF, 4V, X5R
** Panasonic EEFGX0D471R, 470µF, 2.0V, 3mΩ—Used on Up to 1.8V Output
*** Panasonic 4TPF470ML, 470µF, 4V, 10mΩ—Used on 2.5V and 3.3V Output
Rev. B
For more information www.analog.com
67
LTM4680
APPLICATIONS INFORMATION
Table 14. Dual Phase Single Output Voltage vs Capacitor Selection, Bulk and Ceramic Cap Configuration, 30A to 60A Load Step with
30A/µs Slew Rate
VIN
(V)
VOUT VOUT
ILIM
(V) RANGE RANGE
COUT
(CER CAP)
COUT
(BULK CAP)
CCOMP B
(pF)
CCOMP A
(nF)
RCOMP
(kΩ)
EA-GM
(mS)
PK-PK RECOVERY
fSW LOAD STEP DEVIATION
TIME
(kHz)
(A)
(mV)
(μS)
6
1
Low
Low
*100µFx8
**470µFx4
68
3.3
15
3.69
350
30 to 60
91.7
30
12
1
Low
Low
*100µFx8
**470µFx4
68
3.3
15
3.69
350
30 to 60
87.7
30
15
1
Low
Low
*100µFx8
**470µFx4
68
3.3
15
3.69
350
30 to 60
87
30
6
1.5
Low
Low
*100µFx8
**470µFx4
68
3.3
15
3.69
425
30 to 60
89
30
12
1.5
Low
Low
*100µFx8
**470µFx4
68
3.3
15
3.69
425
30 to 60
82.3
30
15
1.5
Low
Low
*100µFx8
**470µFx4
68
3.3
15
3.69
425
30 to 60
80.3
30
6
1.8
Low
Low
*100µFx8
**470µFx4
68
3.3
15
3.69
500
30 to 60
91
30
12
1.8
Low
Low
*100µFx8
**470µFx4
68
3.3
15
3.69
500
30 to 60
79
30
15
1.8
Low
Low
*100µFx8
**470µFx4
68
3.3
15
3.69
500
30 to 60
79.7
30
* Murata GRM32ER60G337ME05L, 330μF, 4V, X5R
** Panasonic EEFGX0D471R, 470µF, 2.0V, 3mΩ—Used on Up to 1.8V Output
68
Rev. B
For more information www.analog.com
LTM4680
APPLICATIONS INFORMATION-DERATING CURVES
DERATING CURVES
8
6
4
8
4
10
20
30
40
LOAD CURRENT (A)
50
0
60
0
10
20
30
40
LOAD CURRENT (A)
50
40
20
0LFM
200LFM
400LFM
0
25
50
75
100
125
AMBIENT TEMPERATURE (°C)
40
20
0LFM
200LFM
400LFM
0
25
50
75
100
125
AMBIENT TEMPERATURE (°C)
4680 F38
20
0
150
0
150
4680 F41
Figure 41. 5V to 1.8V Derating
Curve, No Heat Sink
0
25
50
75
100
125
AMBIENT TEMPERATURE (°C)
80
60
40
20
0
150
Figure 40. 12V to 0.9V Derating
Curve, No Heat Sink
MAXIMUM LOAD CURRENT (A)
MAXIMUM LOAD CURRENT (A)
25
50
75
100
125
AMBIENT TEMPERATURE (°C)
0LFM
200LFM
400LFM
4680 F40
80
0LFM
200LFM
400LFM
60
40
Figure 39. 8V to 0.9V Derating
Curve, No Heat Sink
80
20
50
60
4680 F39
Figure 38. 5V to 0.9V Derating
Curve, No Heat Sink
40
20
30
40
LOAD CURRENT (A)
80
60
0
150
60
10
Figure 37. 12VIN Power Loss Curve
MAXIMUM LOAD CURRENT (A)
60
0
4680 F37
80
MAXIMUM LOAD CURRENT (A)
MAXIMUM LOAD CURRENT (A)
0
60
Figure 36. 8VIN Power Loss Curve
80
MAXIMUM LOAD CURRENT (A)
4
4680 F36
Figure 35. 5VIN Power Loss Curve
0
6
2
4680 F35
0
8
2
0
0.9V, 250kHz
1.0V, 250kHz
1.2V, 350kHz
1.5V, 425kHz
1.8V, 500kHz
2.5V, 575kHz
3.3V, 650kHz
10
6
2
0
12
0.9V, 250kHz
1.0V, 250kHz
1.2V, 350kHz
1.5V, 425kHz
1.8V, 500kHz
2.5V, 575kHz
3.3V, 650kHz
10
POWER LOSS (W)
10
POWER LOSS (W)
12
0.9V, 250kHz
1.0V, 250kHz
1.2V, 350kHz
1.5V, 425kHz
1.8V, 500kHz
2.5V, 575kHz
3.3V, 650kHz
POWER LOSS (W)
12
0LFM
200LFM
400LFM
0
25
50
75
100
125
AMBIENT TEMPERATURE (°C)
150
4680 F42
Figure 42. 8V to 1.8V Derating
Curve, No Heat Sink
60
40
20
0
0LFM
200LFM
400LFM
0
25
50
75
100
125
AMBIENT TEMPERATURE (°C)
150
4680 F43
Figure 43. 12V to 1.8V Derating
Curve, No Heat Sink
Rev. B
For more information www.analog.com
69
LTM4680
APPLICATIONS INFORMATION
EMI PERFORMANCE
SAFETY CONSIDERATIONS
The SWn pin provides access to the midpoint of the power
MOSFETs in LTM4680’s power stages.
The LTM4680 modules do not provide galvanic isolation
from VIN to VOUT. There is no internal fuse. If required,
a slow blow fuse with a rating twice the maximum input
current needs to be provided to protect each unit from
catastrophic failure.
Connecting an optional series RC network from SWn to
GND can dampen high frequency (~30MHz+) switch node
ringing caused by parasitic inductances and capacitances
in the switched-current paths. The RC network is called a
snubber circuit because it dampens (or “snubs”) the resonance of the parasitics, at the expense of higher power
loss. To use a snubber, choose first how much power to
allocate to the task and how much PCB real estate is available to implement the snubber. For example, if PCB space
allows a low inductance 0.5W resistor to be used then the
capacitor in the snubber network (CSW) is computed by:
CSW =
PSNUB
VINn (MAX)2 • fSW
where VINn(MAX) is the maximum input voltage that the
input to the power stage (VINn) will see in the application,
and fSW is the DC/DC converter’s switching frequency
of operation. CSW should be NPO, C0G or X7R-type (or
better) material.
The snubber resistor (RSW) value is then given by:
RSW =
5nH
CSW
The fuse or circuit breaker should be selected to limit the
current to the regulator during overvoltage in case of an
internal top MOSFET fault. If the internal top MOSFET
fails, then turning it off will not resolve the overvoltage,
thus the internal bottom MOSFET will turn on indefinitely
trying to protect the load. Under this fault condition, the
input voltage will source very large currents to ground
through the failed internal top MOSFET and enabled
internal bottom MOSFET. This can cause excessive heat
and board damage depending on how much power the
input voltage can deliver to this system. A fuse or circuit
breaker can be used as a secondary fault protector in
this situation. The device does support over current and
overtemperature protection.
LAYOUT CHECKLIST/EXAMPLE
The high integration of LTM4680 makes the PCB board
layout very simple and easy. However, to optimize its
electrical and thermal performance, some layout considerations are still necessary.
Use large PCB copper areas for high current paths,
including VINn, GND and VOUTn. It helps to minimize
the PCB conduction loss and thermal stress.
n
The snubber resistor should be low ESL and capable of
withstanding the pulsed currents present in snubber circuits. A value between 0.7Ω and 4.2Ω is normal.
A 2.2nF snubber capacitor is a good value to start with in
series with the snubber resistor to ground. The no load
input quiescent current can be monitored while selecting
different RC series snubber components to get a increased
power loss versus switch node ringing attenuation.
n
n
n
70
Place high frequency ceramic input and output capacitors next to the VINn, GND and VOUTn pins to minimize
high frequency noise.
Place a dedicated power ground layer underneath the
module.
To minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers.
Rev. B
For more information www.analog.com
LTM4680
APPLICATIONS INFORMATION
Do not put vias directly on pads, unless they are
capped or plated over.
n
n
Use a separate SGND copper plane for components
connected to signal pins. Connect SGND to GND local
to the LTM4680.
n
n
Use Kelvin sense connections across the input RSENSE
resistor if input current monitoring is used.
GND
n
For parallel modules, tie the VOUTn, ,VOSNSn+/VOSNSn–
voltage-sense differential pair lines, RUNn, , COMPna,
COMPnb pin together. The user must share the SYNC,
SHARE_CLK, FAULT, and ALERT pins of these parts.
Be sure to use pull-up resistors on FAULT, SHARE_
CLK and ALERT.
Bring out test points on the signal pins for monitoring.
Figure 44 gives a good example of the recommended
layout.
GND
GND
VOUT1
VOUT0
GND
GND
VOUT1
VOUT0
GND
GND
GND
GND
VIN
OPTIONAL INPUT
CURRENT SENSE
VIN
VSUPPLY
GND
GND
4680 F44a
4680 F44b
(b) BOTTOM LAYER
(a) TOP LAYER
Figure 44. Recommended PCB Layout Package Top View
Rev. B
For more information www.analog.com
71
LTM4680
TYPICAL APPLICATIONS
VDD33
10k
2.2µF
150µF
TSNS1b
TSNS1a
TSNS0a
PGOOD1
PGOOD0
EXTVCC
INTVCC
IN+
VDD25
VDD33
VIN 5.75V TO 16V
TSNS0b
PGOOD
VDD33
SW0
VOUT0
1mΩ
100µF
×5
IN–
VIN0
4.99k
10k
10k
ON/OFFCONFIG
FAULT INTERRUPTS
LTM4680
RUN1
470µF
×2
LOAD
SCL
SDA
ALERT
GND
FAULT1
FSWPH_CFG
VOUT1_CFG
VOUT0_CFG
VTRIM1_CFG
COMP0b
COMP0a
COMP1b
SHARE_CLK
VTRIM0_CFG
SYNC
COMP1a
+
VOSNS1–
FAULT0
WP
100µF
×5
VOSNS1+
RUN0
470µF
×2
0.9V AT 60A
VOSNS0+
VOSNS0–
SW1
VOUT1
SVIN
VDD33
10k
VIN1
10k
SGND
100pF
825Ω
• SLAVE ADDRESS = 1001110_R/W (0X4E)
• 350kHz SWITCHING FREQUENCY
• NO GUI CONFIGURATION AND NO PART-SPECIFIC PROGRAMMING REQUIRED
EXCEPT: VIN_OFF < VIN_UV_WARN_LIMIT, VIN_ON
