LTM4693
Ultrathin Low VIN, 2A Buck-Boost
µModule Regulator
FEATURES
DESCRIPTION
Wide Input Voltage Range: 2.6V to 5.5V
n Adjustable Output Voltage Range: 1.8V to 5.5V
n 2A of Continuous Output Current with V ≥ V
IN
OUT
(Buck Mode and Buck-Boost Mode);
Minimum 1A Continuous Output Current
with VIN < VOUT (Boost Mode).
n Low Ripple Buck-Boost Architecture
n Programmable Soft-Start and V UVLO
IN
n Burst Mode I 15μA for High Efficiency at Light Loads
Q
n Ultrathin, Small Surface Mount Footprint
3.5mm × 4mm × 1.25mm LGA Package
The LTM®4693 is an ultrathin, highly efficient, 2A buckboost µModule® DC/DC converter that operates from
input voltages above, below or equal to the output voltage. Included in the package are the switching controller, power MOSFETs, inductor and support components.
The LTM4693’s advanced topology provides a continuous transfer through all operating modes. VIN operation
from 2.6V to 5.5V covers a wide variety of power sources
including typical 3.3V and 5V. Output voltage ranging
from 1.8V to 5.5V is set by an external resistor. Only a few
external components are needed for a typical application.
n
Selectable Burst Mode® operation reduces quiescent current to 15μA, ensuring high efficiency across the entire
load range. To optimize applications for highest efficiency,
the switching frequency can be programmed between
1MHz to 4MHz or synchronized to an external clock for
noise sensitive circuits.
APPLICATIONS
Telecom, Datacom (Optical Modules) and
Industrial Equipment
n Medical and Industrial Instruments
n Wireless RF Transmitter
n Battery Powered System
n
LTM4693 is available in ultrathin, 3.5mm × 4mm ×1.25mm
LGA Package. The LTM4693 is Pb-free and RoHS compliant.
All registered trademarks and trademarks are the property of their respective owners.
TYPICAL APPLICATION
3.3VOUT, 2A DC/DC µModule Regulator
22µF
0.1µF
VOUT
VIN
FB
SS
FREQ
LTM4693
MODE/SYNC
PINS NOT USED:
SW1, SW2
RUN/UVLO
VIN
26.2k
COMP
10k
GND
4693 TA01a
100
VOUT
3.3V/1.5A
22µF
(2A AT BUCK)
2.2nF
95
90
EFFICIENCY (%)
VIN
2.6V to 5.5V
Efficiency at 3.3VOUT
85
80
75
70
VIN = 2.6V, 1MHz
VIN = 3.3V, 1MHz
VIN = 4.2V, 1MHz
VIN = 5V, 1MHz
65
60
0
0.5
1
1.5
LOAD CURRENT (A)
2
4693 TA01a
Rev. 0
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1
LTM4693
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
Supply Voltages
VIN, VOUT.................................................. –0.3V to 6V
SW1, SW2 Voltage.................................... –0.3V to 6V
All Other Pins................................................ –0.3V to 6V
Operating Junction Temperature
(Note 2)................................................... –40°C to 125°C
Storage Temperature Range................... –55°C to 125°C
Peak Solder Reflow Body Temperature.................. 260°C
GND 5
COMP
VOUT
SW2 4
FB
SS
GND 3
FREQ
MODE/SYNC
SW1 2
VIN
GND 1
A
B
C
D
RUN/UVLO
E
LGA Package
25-LEAD (3.5mm × 4mm × 1.25mm)
TJMAX = 125°C, θJCtop = 34°C/W, θJCbottom = 6.5°C/W,
θJA = 38°C/W, WEIGHT = 39.4mg
ORDER INFORMATION
PART MARKING*
PART NUMBER
LTM4693EV#PBF
LTM4693IV#PBF
PAD OR BALL FINISH
DEVICE
FINISH CODE
JDEC
FINISH CODE
PACKAGE
TYPE
MSL
RATING
Au (RoHS)
4693
V
e4
LGA
3
• Contact the factory for parts specified with wider operating
temperature ranges. *Pad or ball finish code is per IPC/JEDEC
J-STD-609.
2
TEMPERATURE RANGE
(SEE NOTE 2)
–40°C to 125°C
• Recommended LGA and BGA PCB Assembly and Manufacturing Procedures
• LGA and BGA Package and Tray Drawings
Rev. 0
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LTM4693
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 3.8V, VOUT = 3.3V unless otherwise noted
PARAMETER
CONDITIONS
MIN
VIN Operating Voltage
TYP
MAX
UNITS
l
2.6
5.5
V
l
1.8
5.5
V
Feedback Pin Voltage
l
0.98
1.0
1.02
V
RUN/UVLO Pin Rising Threshold
l
1.16
1.2
1.24
V
RUN/UVLO Pin Falling Threshold
l
1.06
1.1
1.16
V
1
50
nA
0.45
0.60
V
1
2
µA
Output Voltage Range
VIN = 2.6V to 5.5V
Output DC Voltage
RFB = 26.2kΩ
RUN/UVLO Pin Input Leakage Current
3.3
RUN/UVLO = 5V
RUN/UVLO Pin Shutdown Threshold
l
0.27
V
Shutdown Current: VIN
RUN/UVLO = 0V
Input Supply Bias Current
MODE = VIN
20
mA
MODE = GND
15
µA
3.5
A
Output Current Limit
Line Regulation Accuracy
VIN = 2.6V to 5.5V, IOUT = 10mA
Load Regulation Accuracy
IOUT = 0A to 2A (Note 4)
Output Ripple Voltage
IOUT = 0A, COUT = 100µF Ceramic, fSW = 2.2MHz
Switching Frequency
External RT = 90.9kΩ
Oscillator Programmable Frequency Range
Programmed at FREQ, VIN = 2.9V
MODE/SYNC Applied Clock Frequency
VIN = 2.9V
Soft-Start Period
CSS = 2.7nF
External SS Regulation Voltage
Capacitor to GND Sets SS Time
l
0.06
0.06
0.15
0.7
l
0.1
1
5
2.2
l
1.9
1
4
MHz
l
1
4
MHz
2.5
MHz
ms
1
0
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTM4693 is tested under pulsed load conditions such
that TJ ≈ TA. The LTM4693E is guaranteed to meet performance
specifications over the 0°C to 85°C internal operating temperature
range. Specifications over the full –40°C to 125°C internal operating
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTM4693I is guaranteed to meet
specifications over the full –40°C to 125°C internal operating temperature
%
mV
2.2
Feedback Pin Input Current
%/V
%/V
V
50
nA
range. Note that the maximum ambient temperature consistent with
these specifications is determined by specific operating conditions in
conjunction with board layout, the rated package thermal resistance and
other environmental factors.
Note 3: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Continuous operation above the maximum operating junction temperature
may impair device reliability or permanently damage the device.
Note 4: See output current derating curves for different VIN, VOUT and
ambient temperature.
Rev. 0
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3
LTM4693
TYPICAL PERFORMANCE CHARACTERISTICS
1.8VOUT Efficiency,
1MHz, Burst Mode Operation
1.8VOUT Efficiency, 1MHz, CCM
2.5VOUT Efficiency, 1MHz,CCM
100
100
100
95
90
95
80
85
80
75
70
60
0
0.5
1
1.5
LOAD CURRENT (A)
60
50
40
30
VIN = 2.6V
VIN = 3.3V
VIN = 5V
10
0
0.0001
2
0.001
0.01
0.1
LOAD CURRENT (A)
100
100
90
95
30
VIN = 2.6V
VIN = 3.3V
VIN = 5V
10
0
0.0001
0.001
0.01
0.1
LOAD CURRENT (A)
1 2
80
75
VIN = 2.6V
VIN = 3.3V
VIN = 4.2V
VIN = 5V
0
0.5
1
1.5
LOAD CURRENT (A)
70
60
50
40
30
VIN = 2.6V
VIN = 3.3V
VIN = 4.2V
VIN = 5V
20
10
2
0
0.0001
0.001
0.01
0.1
LOAD CURRENT (A)
4693 G05
1 2
4693 G06
5VOUT Efficiency,
1MHz, Burst Mode Operation
5VOUT Efficiency, 1MHz, CCM
2
100
85
60
Output Ripple
100
90
80
EFFICIENCY (%)
90
EFFICIENCY (%)
1
1.5
LOAD CURRENT (A)
80
65
95
85
80
75
70
0
0.5
1
1.5
LOAD CURRENT (A)
VOUT
AC-COUPLED
20mV/DIV
70
60
50
40
30
500ns/DIV
20
VIN = 2.6V
VIN = 3.3V
VIN = 5V
65
VIN = 2.6V
VIN = 3.3V
VIN = 5V
10
2
4693 G07
4
0.5
90
4693 G04
60
0
3.3VOUT Efficiency,
1MHz, Burst Mode Operation
3.3VOUT Efficiency, 1MHz, CCM
70
20
VIN = 2.6V
VIN = 3.3V
VIN = 5V
4693 G03
EFFICIENCY (%)
40
100
60
90
EFFICIENCY (%)
EFFICIENCY (%)
80
50
75
4693 G02
2.5VOUT Efficiency, 1MHz, Burst
Mode Operation
60
80
65
1 2
4693 G01
70
85
70
20
VIN = 2.6V
VIN = 3.3V
VIN = 5V
65
90
70
EFFICIENCY (%)
EFFICIENCY (%)
EFFICIENCY (%)
90
0
0.0001
0.001
0.01
0.1
LOAD CURRENT (A)
4693 G09
VIN = 3.3V, VOUT = 3.3V, fSW = 2.2MHz
ILOAD = 0.8A, COUT = 22μF CERAMIC CAP
1 2
4693 G08
Rev. 0
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LTM4693
TYPICAL PERFORMANCE CHARACTERISTICS
Load Transient Response
2.6VIN to 5VOUT
Load Transient Response
3.3VIN to 1.8VOUT
Load Transient Response
3.3VIN to 3.3VOUT
VOUT
200mV/DIV
VOUT
100mV/DIV
VOUT
100mV/DIV
IOUT
0.5A/DIV
IOUT
0.5A/DIV
IOUT
0.5A/DIV
100µs/DIV
4693 G10
100µs/DIV
4693 G11
100µs/DIV
VIN = 2.6V, VOUT = 5V, fSW = 1MHz
COUT = 2× 22μF CERAMIC CAP
CTH = 2200pF, RTH = 10k
LOAD STEP 1A–1.5A
VIN = 3.3V, VOUT = 1.8V, fSW = 1MHz
COUT = 2× 22μF CERAMIC CAP
CTH = 2200pF, RTH = 10k
LOAD STEP 1A–2A
VIN = 3.3V, VOUT = 3.3V, fSW = 1MHz
COUT = 2× 22μF CERAMIC CAP
CTH = 2200pF, RTH = 10k
LOAD STEP 1A–2A
Load Transient Response
5VIN to 3.3VOUT
Load Transient Response
5VIN to 5VOUT
Start-Up with No Load
VOUT
100mV/DIV
VOUT
200mV/DIV
IOUT
0.5A/DIV
IOUT
0.5A/DIV
100µs/DIV
4693 G13
4693 G12
VOUT
2V/DIV
IOUT
1A/DIV
100µs/DIV
4693 G14
500µs/DIV
4693 G15
VIN = 5V, VOUT = 3.3V, fSW = 1MHz
COUT = 2× 22μF CERAMIC CAP
CTH = 2200pF, RTH = 10k
LOAD STEP 1A–2A
VIN = 5V, VOUT = 5V, fSW = 1MHz
COUT = 2× 22μF CERAMIC CAP
CTH = 2200pF, RTH = 10k
LOAD STEP 1A–2A
VIN = 3.3V, VOUT = 3.3V, fSW = 1MHz, 0A LOAD
COUT = 3× 22μF + 3× 2.2μF CERAMIC
SOFT-START CAPACITOR = 0.01μF
USE RUN PIN TO CONTROL START-UP
Start-Up with 2A Load
Short-Circuit with No Load
Short-Circuit with 2A Load
VOUT
2V/DIV
VOUT
2V/DIV
VOUT
2V/DIV
IOUT
1A/DIV
IIN
5A/DIV
1ms/DIV
IIN
2A/DIV
4693 G16
VIN = 3.3V, VOUT = 3.3V, fSW = 1MHz, 2A LOAD
COUT = 3× 22μF + 3× 2.2μF CERAMIC
SOFT-START CAPACITOR = 0.01μF
USE RUN PIN TO CONTROL START-UP
100µs/DIV
4693 G17
VIN = 3.3V, VOUT = 3.3V, fSW = 1MHz, 0A LOAD
COUT = 3× 22μF + 3× 2.2μF CERAMIC
100µs/DIV
4693 G18
VIN = 3.3V, VOUT = 3.3V, fSW = 1MHz, 2A LOAD
COUT = 3× 22μF + 3× 2.2μF CERAMIC
Rev. 0
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5
LTM4693
PIN FUNCTIONS
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
GND (Pins A1, B1, A3, B3, C3, A5, B5): Power Ground
Connection. These pins and exposed thermal pad must
make full connection to PCB ground plane to meet specific
thermal requirements.
SW1 (Pins A2, B2, C2): Buck-Boost Converter Switching
Node Pin 1.
MODE/SYNC (Pin E2): Mode Selection and Oscillator
Synchronization. Do not leave this pin floating.
MODE/SYNC = High (VIN). Disable Burst Mode operation and maintain low noise, constant frequency
PWM operation.
MODE/SYNC = Low (GND). The converter operates in
Burst Mode operation.
VIN (Pins C1, D1, D2): Power Input for Buck-Boost
Converter. Connect a minimum 22μF low ESR capacitor
to GND as close to the device as possible.
MODE/SYNC = External CLK. The internal oscillator is synchronized to the external CLK signal, Burst Mode operation is disabled. A clock pulse width between 75ns and
tperiod –75ns is required to synchronize the oscillator. An
external resistor must be connected between FREQ and
GND to program the oscillator 25% to 50% below the
desired synchronization frequency.
VOUT (Pins C5, D4, D5): Power Output for Buck-Boost
Converter. Connect a minimum 22μF low ESR capacitor
to GND as close to the device as possible. Capacitor value
may change depending on VOUT voltage and load current
requirements.
FREQ (Pin E3): Oscillator Frequency Programming Input.
Default switching frequency is 1MHz when this pin is left
floating. Connect an external RT resistor from FREQ to
GND to program the switching frequency from 1MHz to
4MHz according to Equation 2.
SW2 (Pins A4, B4, C4): Buck-Boost Converter Switching
Node Pin 2.
SS (Pin D3): External Soft-Start. Connect to VIN for 2ms
default soft-start period. Connect an external capacitor to
set soft-start period according to Equation 1.
tSS (ms) = 0.8 • CSS (nF)
(1)
RUN/UVLO (Pin E1): Input to Enable the IC. Connect
RUN to VIN to enable the LTM4693 at the 2.6V minimum
operating voltage. Connect to an external divider from VIN
to provide a programmable accurate VIN undervoltage
threshold, see application information for details.
6
RT (kΩ) =
fSW
110
(MHz) – 1
(2)
FB (Pin E4): Feedback Input to Error Amplifier. The resistor connected to this pin sets the converter output voltage
(Equation 3).
VOUT = 1.0V •
RFB + 60.4k
RFB
(3)
COMP (Pin E5): The output of the voltage error amplifier used to program average inductor current inside the
module. An R-C from this pin to ground sets the voltage
loop compensation.
Rev. 0
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LTM4693
BLOCK DIAGRAM
SW1
VIN
VIN
2.6V TO 5.5V
Q1
SW2
L
0.47µH
Q2
Q3
Q4
VOUT
22μF
VOUT
3.3V/2A
22μF
60.4k
FB
RUN/UVLO
26.2k
MODE/SYNC
4 SWITCH BUCK-BOOST CONTROLLER
SS
0.1μF
FREQ
COMP
110k
22pF
10k
2.2nF
GND
4693 BD
Rev. 0
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7
LTM4693
OPERATION
The LTM4693 is a standalone nonisolated buck-boost
switching DC/DC power supply. The buck-boost topology
allows the LTM4693 to regulate its output voltage above
or below the input voltage, and the maximum output current depends upon the input voltage. In buck and buckboost region, the converter can source 2A output current,
while in boost region, the converter can source at least
1A output current. The low RDS(ON), low gate charge synchronous switches and low DCR inductor inside provide
highly efficient power module with a tiny 3.5mm × 4mm
× 1.25mm size. The LTM4693 utilizes a proprietary low
noise switching algorithm to provide a seamless transition between operating modes. These advantages result
in increased efficiency and stability in comparison to the
traditional buck-boost converter. A simplified block diagram is given on the previous page.
The LTM4693 provides a precisely regulated output voltage programmable from 1.8V to 5.5V via an external
resistor connecting from the FB pin to GND. The input
voltage range is from 2.6V to 5.5V.
The LTM4693 utilizes average current mode control
for its pulse width modulator. Current mode control,
both average and the better known peak method, provide some benefits compared to other control methods
including: simplified loop compensation, rapid response
to load transients and inherent line voltage rejection. The
8
switching frequency is set by connecting the appropriate
resistor value from the FREQ pin to GND. The LTM4693
default frequency is 1MHz, and it can be configured to
operate over a wide range of switching frequencies, from
1MHz to 4MHz, allowing applications to be optimized for
broad area and efficiency. Driving the MODE/SYNC pin will
synchronize the LTM4693 to an external clock.
Burst Mode operation is available in the LTM4693 and is
user-selected via the MODE/SYNC input pin. In Burst Mode
operation, the LTM4693 provides exceptional efficiency at
light output loads by operating the converter only when
necessary to maintain voltage regulation. The typical
quiescent current in Burst Mode operation is only 15μA
at no load. At higher loads, the LTM4693 automatically
transitions to fixed frequency PWM operation. Continuous
PWM mode can also be selected via the MODE/SYNC pin
for low switching ripple and low noise operation.
The LTM4693 features an accurate, resistor programmable RUN/UVLO comparator which allows the buck-boost
DC/DC converter to turn on and off at user-selected voltage thresholds depending on the power source. Besides,
the soft-start period is also programmable by an appropriate capacitor connecting from SS to GND.
Rev. 0
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LTM4693
APPLICATIONS INFORMATION
The front page shows a typical LTM4693 application
circuit. This Applications Information section serves as
a guideline of selecting external components for typical applications. The examples and equations in this
section assume continuous conduction mode unless
otherwise specified.
VIN UVLO THRESHOLD
The VIN threshold is internally set to a typical value of
1.7V for turn-on and 1.6V for turn-off when RUN/UVLO
is connected to VIN. The VIN UVLO can be adjusted to a
higher threshold voltage with a resistor network on RUN/
UVLO according to Equation 4 and Equation 5.
VTURN(ON) = 1.2V •(1+R1/R2)
(4)
The accurate RUN/UVLO pin threshold has 100mV of hysteresis provided internally.
(5)
V
= 1.1V •(1+R1/R2)
TURN(OFF)
LTM4693
VIN
R1
RUN/UVLO
R2
4693 F01
Figure 1. Circuit to Set VIN UVLO
OUTPUT VOLTAGE PROGRAMMING
The PWM controller has an internal 1V reference voltage.
As shown in the Block Diagram, a 60.4k internal feedback
resistor connects from VFB to VOUT. Adding a resistor
RFB from FB pin to GND pin programs the output voltage
(Equation 6).
VOUT = 1.0V •
60.4k +RFB
RFB
(6)
SETTING THE SWITCHING FREQUENCY
The operating frequency of the LTM4693 is optimized
to achieve the compact package size and the minimum
output ripple voltage while keeping high efficiency. The
default operating frequency is internally set to 1MHz by
an internal resistor. In most applications, no additional
frequency adjusting is required.
If any operating frequency higher than 1MHz is required
by application, the operating frequency can be adjusted
by adding a resistor RT between FREQ pin and GND. The
RT resistor required to set a specific switching frequency
can be calculated with Equation 7.
R T (kΩ) =
110
fSW (MHz)− 1
(7)
The programmable operating frequency range is from
1MHz to 4MHz. The typical value of RT and the switching
frequency is shown as Table 1.
Table 1. RT Value for Common Switching Frequencies
fSW
RT
1.0MHz
OPEN
2.0MHz
110kΩ
3.0MHz
55kΩ
4.0MHz
36.5kΩ
The LTM4693 can be synchronized to an external clock
applied to the MODE/SYNC pin. The frequency of the
external clock must be higher than the internal oscillator
frequency as set by the FREQ pin. In order to accommodate the ±20% possible variation in the oscillator frequency, the RT resistor should be chosen to set the internal oscillator frequency between 25% to 50% below the
synchronization frequency. For example, to synchronize
to an external 2.5MHz clock, RT should be selected to set
the internal oscillator at 1.9MHz or lower.
Rev. 0
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9
LTM4693
APPLICATIONS INFORMATION
SOFT-START
The soft‑start circuit linearly ramps the average inductor current during the soft‑start period (tSS). An internal
soft‑start interval of approximately 2ms can be selected
by connecting SS to VIN. For applications requiring a longer soft‑start period, an external capacitor CSS on SS sets
soft‑start period according to Equation 8. The total softstart time can be calculated as:
tSS (ms) = 0.8 • CSS (nF)
SS
CSS
PROGRAMMABLE
SOFT-START
VIN
(8)
DEFAULT 2ms
SOFT-START
VIN
SS
4693 F02
Figure 2. Circuit to Set Soft-Start Time
where CSS is the capacitance on the SS pin.
The soft‑start circuit slowly ramps the error amplifier
output at VC. In doing so, the current command of the
IC is slowly increased, starting from zero. The soft‑start
period is defined as the time it takes the SS capacitor to
ramp to 0.9V, allowing VC to command full rated current.
In most situations, VOUT comes into regulation without
needing full inductor current, resulting in power up times
at a fraction of the soft-start period. After initial power up,
soft-start can be reset by VIN UVLO asserting, thermal
shutdown, or a VOUT short-circuit.
OUTPUT CAPACITORS
A low effective series resistance (ESR) output capacitor
should be connected at the output of the buck‑boost converter in order to minimize output voltage ripple. Multilayer
ceramic capacitor is an excellent option as it has low ESR
and is available in small footprint. The capacitor value
should be chosen large enough to reduce the output
voltage ripple to acceptable levels. The output voltage
ripple increases with load current and is generally higher
in boost mode than in buck mode. Both output voltage
ripple generated across the output capacitance, and output voltage ripple produced across the internal resistance
10
of the output capacitor need to be considered. In most
LTM4693 applications, an output capacitor between 68µF
and 220µF from VOUT to GND will work well. An additional
low value ceramic capacitor such as 4.7µF can be placed
between VOUT to GND to reduce switching noise to the
control circuitry. The LTpowerCAD® design tool is available to download online to perform ripple analysis based
on certain number and type of the capacitors.
INPUT DECOUPLING CAPACITORS
The VIN pin carries the full inductor current, provides
power to internal switches and drivers, and powers control circuits in the IC. To minimize input voltage ripple
and ensure proper operation of the IC, a low ESR bypass
capacitor with a value of at least 22µF should be located as
close to VIN as possible. The traces connecting this capacitor to VIN and the ground plane (GND) should be made as
short as possible. An additional low value ceramic capacitor such as 4.7µF can be placed between VIN and GND to
reduce switching noise to the control circuitry.
RECOMMENDED INPUT AND OUTPUT CAPACITORS
The capacitors used to filter the input and output of the
LTM4693 must have low ESR and must be rated to handle
the large AC currents generated by the switching converters. While there are many capacitor types for these
applications (including low ESR tantalum, OSCON and
POSCAP), ceramic capacitors are often utilized in switching converter applications due to their small size, low ESR
and low leakage currents. The major providers of ceramic
capacitors are AVX, Kemet, Murata, Taiyo Yuden and TDK.
Many ceramic capacitors intended for power applications experience a significant loss in capacitance from
their rated value as the DC bias voltage on the capacitor
increases. It is not uncommon for a small surface mount
capacitor to lose more than 50% of its rated capacitance
when operated near its maximum rated voltage. This
effect is generally reduced as the case size is increased
for the same nominal value capacitor. As a result, it is
often necessary to use a larger value capacitance or a
higher voltage rated capacitor than would ordinarily be
required to actually realize the intended capacitance at
Rev. 0
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LTM4693
APPLICATIONS INFORMATION
the operating voltage of the application. X5R, X6S or X7R
dielectric types are recommended as they exhibit the best
performance over the wide operating and temperature
ranges. To verify that the intended capacitance is achieved
in the application circuit, be sure to consult the capacitor
vendor’s curve of capacitance vs DC bias voltage.
FORCED CONTINUOUS MODE (FCM)
If the MODE/SYNC pin is high or if the load current on the
converter is high enough to enter forced continuous mode
operation, the LTM4693 operates at a fixed frequency programmed by the FREQ pin. FCM minimizes output voltage
ripple and yields a low noise switching frequency spectrum. A proprietary switching algorithm provides seamless transitions between operating modes and eliminates
discontinuities in the average inductor current, inductor
ripple current and loop transfer function throughout all
modes of operation. These advantages result in increased
efficiency, improved loop stability, and lower output voltage ripple. In response to the internal control loop command, an internal pulse width modulator generates the
appropriate switch duty cycle to maintain regulation of
the output voltage.
Burst Mode OPERATION
When the MODE/SYNC pin is held low, the LTM4693 is
configured for Burst Mode operation. As a result, the
buck‑boost DC/DC converter will operate with normal
continuous PWM switching above a predetermined average inductor current and will automatically transition to
power saving Burst Mode operation below this level. With
MODE/SYNC low, at light output loads, the LTM4693 will
go into a standby or sleep state when the output voltage
achieves its nominal regulation level. The sleep state halts
PWM switching and powers down all non‑essential functions of the IC, significantly reducing the quiescent current of the LTM4693. This greatly improves overall power
conversion efficiency when the output load is light. Since
the converter is not operating in sleep, the output voltage
will slowly decay at a rate determined by the output load
resistance and the output capacitor value. When the output voltage has decayed by a small amount, typically less
than 1%, the LTM4693 will wake up and resume normal
switching operation until the voltage on VOUT is restored
to the previous level. If the load is very light, the LTM4693
may only need to switch for a few cycles to restore VOUT
and may sleep for extended periods of time, significantly
improving efficiency.
AVERAGE CURRENT MODE CONTROL AND STABILITY
COMPENSATION
The LTM4693 utilizes average current mode control for
the pulse width modulator as shown in Figure 3. Current
mode control, both average and the better known peak
methods, enjoy some benefits compared to other control methods including: simplified loop compensation,
rapid response to load transients and inherent line
voltage rejection.
Referring to Figure 3, an internal high gain transconductance error amplifier labeled VAMP monitors VOUT through
a voltage divider connected to the FB node and generates
an output, VC, used by the current mode control loop
to command the appropriate inductor current level. To
ensure stability, external frequency compensation components (RC and CC) must be installed between VC and
GND and CHF is optional.
VC is internally connected to the non‑inverting input of
a second amplifier, referred to in Figure 3 as IAMP. The
inverting input of the average current amplifier is connected to the inductor current sense resistor RCS with a
200mV offset. IAMP contains an internal averaging filter
and frequency compensation network to stabilize operation of the internal current loop. The average current
amplifier’s output (ICOMP) provides the cycle‑by‑cycle
Rev. 0
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11
LTM4693
APPLICATIONS INFORMATION
CURRENT SENSE
INDUCTOR
IL
SW2
SW1
RCS
VOUT
IAMP
–
+
R3
1V
R4
INTERNAL
CURRENT
AMPLIFIER
–
+
ICOMP
PWM RAMPS/
OSCILLATOR
VAMP
FB
PWM
VC
CLAMP
0.9V
TO
SWITCHES
DRIVE
LOGIC
4693 F03
RC
CHF
CC
Figure 3. Average Current Mode Control Loop
duty cycle command into the buck‑boost PWM circuitry.
The inductor current sensing circuitry alternately measures the current through the power switches. The output
of the sensing circuitry produces a voltage across resistor RCS that resembles the inductor current waveform
transformed to a voltage. If there is an increase in the
power converter load on VOUT, the instantaneous level
of VOUT will drop slightly, which will increase the voltage
level on VC by the inverting action of the voltage error
amplifier. When the increase on VC first occurs, the output
of the current averaging amplifier, ICOMP, will increase
momentarily to command a larger duty cycle. This duty
cycle increase will result in a higher inductor current level,
ultimately raising the average voltage across RCS. Once
the average value of the voltage on RCS is equivalent to
the VC level, the voltage on ICOMP will revert very closely to
its previous level into the PWM and force the correct duty
cycle to maintain voltage regulation at this new higher
inductor current level. The average current amplifier is
configured, so in steady state, the average value of the
voltage applied to its inverting input (voltage across RCS)
will be equivalent to the voltage on its non‑inverting input
VC. As a result, the average value of the inductor current
is controlled in order to maintain voltage regulation. The
entire current amplifier and PWM can be simplified as a
12
voltage controlled current source, with the driving voltage coming from VC. The voltage error amplifier monitors VOUT through a voltage divider and makes adjustments to the current command as necessary to maintain
regulation. The voltage error amplifier therefore controls
the outer voltage regulation loop. The average current
amplifier makes adjustments to the inductor current as
directed by the voltage error amplifier output via VC and is
commonly referred to as the inner current loop amplifier.
The average current mode control technique is similar to
peak current mode control except that the average current amplifier controls average current instead of the peak
current. This difference eliminates the peak to average
current error inherent to peak current mode control, while
maintaining most of the advantages inherent to peak current mode control. The inner loop compensation components are fixed internally on the LTM4693 to simplify the
loop design and provide the highest possible bandwidth
over a wide operating range. However, the compensation
of the voltage loop is external for the LTM4693 which
allows the overall loop characteristics to be customized
depending on the programmed output voltage, oscillator
frequency, output capacitance and equivalent ESR of the
output capacitors.
Rev. 0
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LTM4693
APPLICATIONS INFORMATION
The average current mode control used in the LTM4693
can be conceptualized as a voltage controlled current
source (VCCS), driving the output load formed primarily
by RLOAD and COUT, as shown in Figure 4.
The voltage error amplifier output (VC), provides a command input to the VCCS. As with peak current mode control,
the inner average current control loop effectively turns the
inductor into a current source over the frequency range of
interest, resulting in a frequency response from the power
stage that exhibits a single pole (–20dB/decade) roll‑off.
The output capacitor (COUT) and load resistance (RLOAD)
form a dominant low frequency pole, where the effective
series resistance of the output capacitor and its capacitance form a zero, usually at a high enough frequency to
be ignored, if ceramic capacitors are employed.
A potentially troublesome Right Half Plane Zero (RHPZ)
is also encountered if the converter is operated in boost
mode. The RHPZ causes an increase in gain, like a zero,
but a decrease in phase, like a pole. This can ultimately
limit the maximum converter bandwidth that can be
achieved with the LTM4693. The RHPZ is not present
when operating in buck mode.
gm VIN > VOUT: 10A/V
VIN > VOUT: (10A/V) • (VIN/VOUT)
VC
VCCS
VOUT
RESR
RLOAD
R3
1V
FB
COUT
0.9V
R4
+
–
VOLTAGE
ERROR
AMPLIFIER
gm = 110µA/V
VC
RC
CHF
CC
4693 F04
Figure 4. Simplified Representation of Average Current
Mode Control Loop Small Signal Model
The voltage amplifier’s frequency response is designed to
optimize the response for the overall loop. Measurement
of the power stage gain over line, load, component variation, and frequency is strongly recommended prior to
loop design. The design parameters for compensation
design will focus on the series resistor and capacitors
connected from VC to GND (RC, CC and CHF (Optional)).
Being a buck‑boost converter, the target loop crossover
frequency for the compensation design will be dictated
by the highest boost ratio and load current as this will
result in the lowest RHPZ frequency. The general goal
is to set the crossover frequency and provide sufficient
phase boost using the external compensation network.
The LTpowerCAD design tool is available to download
online to perform loop compensation and transient
optimization.
Table 5 is provided for most application requirements.
Thermal Considerations and Output Current Derating
The thermal resistances reported in the Pin Configuration
section of the data sheet are consistent with those parameters defined by JESD51-12 and are intended for use with
finite element analysis (FEA) software modeling tools that
leverage the outcome of thermal modeling, simulation,
and correlation to hardware evaluation performed on a
µModule package mounted to a hardware test board. The
motivation for providing these thermal coefficients can be
found in JESD51-12 (“Guidelines for Reporting and Using
Electronic Package Thermal Information”).
Many designers may opt to use laboratory equipment and
a test vehicle such as the demo board to anticipate the
µModule regulator’s thermal performance in their application at various electrical and environmental operating
conditions to compliment any FEA activities. Without
FEA software, the thermal resistances reported in the
Pin Configuration section are, in-and-of themselves, not
relevant to providing guidance of thermal performance;
instead, the derating curves provided in the data sheet
can be used in a manner that yields insight and guidance
Rev. 0
For more information www.analog.com
13
LTM4693
APPLICATIONS INFORMATION
pertaining to one’s application usage, and can be adapted
to correlate thermal performance to one’s own application.
The Pin Configuration section typically gives three thermal
coefficients explicitly defined in JESD 51-12; these coefficients are quoted or paraphrased below:
1. θJA, the thermal resistance from junction to ambient,
is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed
enclosure. This environment is sometimes referred
to as “still air” although natural convection causes
the air to move. This value is determined with the
part mounted to a four-layer demo circuit DC3016A.
2. θJCbottom, the thermal resistance from junction to
bottom of the product case, is determined with all of
the component power dissipation flowing through the
bottom of the package. In the typical module regulator, the bulk of the heat flows out the bottom of
the package, but there is always heat flow out into
the ambient environment. As a result, this thermal
resistance value may be useful for comparing packages but the test conditions don’t generally match the
user’s application.
3. θJCtop, the thermal resistance from junction to top of
the product case, is determined with nearly all of the
component power dissipation flowing through the top
of the package. As the electrical connections of the
typical µModule are on the bottom of the package, it
is rare for an application to operate such that most of
the heat flows from the junction to the top of the part.
As in the case of θJCbottom, this value may be useful
for comparing packages but the test conditions don’t
generally match the user’s application.
A graphical representation of the aforementioned thermal resistances is given in Figure 5; blue resistances are
contained within the μModule regulator, whereas green
resistances are external to the µModule.
As a practical matter, it should be clear to the reader that
no individual or subgroup of the three thermal resistance
parameters defined by JESD 51-12 or provided in the
Pin Configuration section replicates or conveys normal operating conditions of a μModule. For example, in
14
normal board-mounted applications, never does 100%
of the device’s total power loss (heat) thermally conduct
exclusively through the top or exclusively through bottom
of the µModule—as the standard defines for θJCtop and
θJCbottom, respectively. In practice, power loss is thermally dissipated in both directions away from the package—granted, in the absence of a heat sink and airflow,
a majority of the heat flow is into the board.
Within the LTM4693 module, be aware there are multiple
power devices and components dissipating power, with
a consequence that the thermal resistances relative to
different junctions of components or die are not exactly
linear with respect to total package power loss. To reconcile this complication without sacrificing modeling
simplicity—but also, not ignoring practical realities—an
approach has been taken using FEA software modeling
along with laboratory testing in a controlled environment
chamber to reasonably define and correlate the thermal
resistance values supplied in this data sheet: (1) Initially,
FEA software is used to accurately build the mechanical
geometry of the µModule and the specified PCB with all
of the correct material coefficients along with accurate
power loss source definitions; (2) this model simulates
a software defined JEDEC environment consistent with
JSED51-12 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the JEDEC-defined thermal resistance values;
(3) the model and FEA software is used to evaluate the
LTM4693 with heat sink and airflow; (4) having solved for
and analyzed these thermal resistance values and simulated various operating conditions in the software model,
a thorough laboratory evaluation replicates the simulated
conditions with thermocouples within a controlled environment chamber while operating the device at the same
power loss as simulated. An outcome of this process and
due-diligence yields a set of derating curves shown in
this data sheet.
After these laboratory test have been performed and
correlated to LTM4693 model, then the θJA is provided
assuming approximately 100% of the power loss flows
from the junction through the board into ambient with no
airflow or top mounted heat sink.
Rev. 0
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LTM4693
APPLICATIONS INFORMATION
µModule DEVICE
θJA JUNCTION-TO-AMBIENT RESISTANCE
θJCtop JUNCTION-TO-CASE
(TOP) RESISTANCE
CASE (TOP)-TO-AMBIENT
RESISTANCE
AMBIENT
JUNCTION
θJCbot JUNCTION-TO-CASE
(BOTTOM) RESISTANCE
CASE (BOTTOM)-TO-BOARD
RESISTANCE
BOARD-TO-AMBIENT
RESISTANCE
4693 F05
Figure 5. Graphical Representation of JESD51-12 Thermal Coefficients, Including JESD 51-12 Terms
The 1.8V, 3.3V and 5V power loss curves in Figure 6 to
Figure 8 can be used in coordination with the load current
derating curves in Figure 9 to Figure 14 for calculating
an approximate θJA thermal resistance for the LTM4693
with various heat sinking and airflow conditions. The
power loss curves are taken at room temperature, and
are increased with multiplicative factors according to the
junction temperature. This approximate factor is: 1.2 for
120°C at junction temperature. Maximum load current is
achievable while increasing ambient temperature as long
as the junction temperature is less than 120°C, which is
5°C guard band from maximum junction temperature of
125°C. When the ambient temperature reaches a point
where the junction temperature is 120°C, then the load
current is lowered to maintain the junction at 120°C while
increasing ambient temperature up to 120°C. The derating
curves are plotted with the output current starting at 2A
and the ambient temperature at 30°C. The output voltages
are 1.8V, 3.3V and 5V. These are chosen to include the
lower and higher output voltage ranges for correlating
the thermal resistance. Thermal models are derived from
several temperature measurements in a controlled temperature chamber along with thermal modeling analysis.
The junction temperatures are monitored while ambient
temperature is increased with and without airflow. The
power loss increase with ambient temperature change
is factored into the derating curves. The junctions are
maintained at 120°C maximum while lowering output current or power with increasing ambient temperature. The
decreased output current will decrease the internal module
loss as ambient temperature is increased. The monitored
junction temperature of 120°C minus the ambient operating temperature specifies how much module temperature
rise can be allowed. As an example in Figure 9, the load
current is derated to 1.5A at ~ 105°C with no air or heat
sink and the power loss for the 3.3V to 1.8V at 1.5A output
is about 0.323W. The 0.388W loss is calculated with the
~ 0.323W room temperature loss from the 3.3V to 1.8V
power loss curve at 1.5A, and the 1.2 multiplying factor.
If the 105°C ambient temperature is subtracted from the
120°C junction temperature, then the difference of 15°C
divided by 0.388W equals a 38.7°C/W θJA thermal resistance. Table 2 specifies a 38°C/W which is very close.
Table 2 to Table 4 provide equivalent thermal resistances
for 1.8V, 3.3V and 5V outputs with and without airflow.
The derived thermal resistances in Table 2 to Table 4 for
the various conditions can be multiplied by the calculated power loss as a function of ambient temperature to
derive temperature rise above ambient, thus maximum
junction temperature. Room temperature power loss
can be derived from the efficiency curves in the Typical
Performance Characteristics section and adjusted with
the above ambient temperature multiplicative factors. The
printed circuit board is a 1.6mm thick four layer board
with two ounce copper for the two outer layers and one
ounce copper for the two inner layers. The PCB dimensions are 76mm × 76mm.
Rev. 0
For more information www.analog.com
15
LTM4693
APPLICATIONS INFORMATION
0.7
0.6
0.5
0.4
0.3
0.3
0.1
0.1
0
0
0.5
1
1.5
LOAD CURRENT (A)
2
0.8
0.4
0.2
0.5
0.4
0.3
0.1
0
0.5
1
1.5
LOAD CURRENT (A)
0
2
3.0
2.5
2.5
2.5
0LFM
200LFM
400LFM
0.5
0
25
50
LOAD CURRENT (A)
3.0
1.0
2.0
1.5
1.0
0LFM
200LFM
400LFM
0.5
75
TAMB (°C)
100
0
125
25
50
4693 F09
Figure 9. 3.3V to 1.8V Derating
Curve, No Heat Sink
1.0
100
0
125
2.5
0
25
50
2.0
1.5
1.0
0LFM
200LFM
400LFM
0.5
75
TAMB (°C)
100
125
4693 F12
Figure 12. 5V to 1.8V Derating
Curve, No Heat Sink
16
LOAD CURRENT (A)
2.5
LOAD CURRENT (A)
2.5
0LFM
200LFM
400LFM
0
25
50
75
TAMB (°C)
100
125
4693 F11
2.0
1.5
1.0
0LFM
200LFM
400LFM
0.5
75
TAMB (°C)
50
Figure 11. 3.3V to 5V Derating
Curve, No Heat Sink
3.0
0.5
25
4693 F10
3.0
1.0
0LFM
200LFM
400LFM
0.5
75
TAMB (°C)
2
1.5
3.0
1.5
1
1.5
LOAD CURRENT (A)
2.0
Figure 10. 3.3V to 3.3V
Derating Curve, No Heat Sink
2.0
0.5
Figure 8. Power Loss at 5V Output
and 1MHz Switching Frequency
3.0
1.5
0
4693 F08
Figure 7. Power Loss at 3.3V Output
and 1MHz Switching Frequency
LOAD CURRENT (A)
LOAD CURRENT (A)
0.6
4693 F07
Figure 6. Power Loss at 1.8V Output
and 1MHz Switching Frequency
LOAD CURRENT (A)
0.7
0.2
4693 F06
2.0
VIN = 2.6V
VIN = 3.3V
VIN = 5V
0.9
0.5
0.2
0
1.0
VIN = 2.6V
VIN = 3.3V
VIN = 5V
0.7
POWER LOSS (W)
0.6
POWER LOSS (W)
0.8
VIN = 2.6V
VIN = 3.3V
VIN = 5V
POWER LOSS (W)
0.8
100
125
4693 F13
Figure 13. 5V to 3.3V Derating
Curve, No Heat Sink
0
25
50
75
TAMB (°C)
100
125
4693 F14
Figure 14. 5V to 5V Derating
Curve, No Heat Sink
Rev. 0
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LTM4693
APPLICATIONS INFORMATION
SAFETY CONSIDERATIONS
LAYOUT CHECKLIST/EXAMPLE
The LTM4693 modules do not provide galvanic isolation
from VIN to VOUT. There is no internal fuse. If required,
a slow blow fuse with a rating twice the maximum input
current needs to be provided to protect each unit from
catastrophic failure. The device does support thermal
shutdown and short-circuit protection.
The high integration of LTM4693 makes the PCB board
layout very simple and easy. However, to optimize its
electrical and thermal performance, some layout considerations are still necessary.
Table 2. 1.8V Output
DERATING CURVE
VIN (V)
POWER LOSS CURVE
AIR FLOW (LFM)
HEAT SINK
θJA (°C/W)
Figure 9, Figure 12
3.3, 5
Figure 6
0
None
38
Figure 9, Figure 12
3.3, 5
Figure 6
200
None
34
Figure 9, Figure 12
3.3, 5
Figure 6
400
None
34
Table 3. 3.3V Output
DERATING CURVE
VIN (V)
POWER LOSS CURVE
AIR FLOW (LFM)
HEAT SINK
θJA (°C/W)
Figure 10, Figure 13
3.3, 5
Figure 7
0
None
38
Figure 10, Figure 13
3.3, 5
Figure 7
200
None
34
Figure 10, Figure 13
3.3, 5
Figure 7
400
None
34
Table 4. 5V Output
DERATING CURVE
VIN (V)
POWER LOSS CURVE
AIR FLOW (LFM)
HEAT SINK
θJA (°C/W)
Figure 11 ,Figure 14
3.3, 5
Figure 8
0
None
38
Figure 11 ,Figure 14
3.3, 5
Figure 8
200
None
34
Figure 11 ,Figure 14
3.3, 5
Figure 8
400
None
34
Rev. 0
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17
LTM4693
APPLICATIONS INFORMATION
Table 5. Output Voltage Response vs Component Matrix
COUT
VALUE
PART NUMBER
MURATA
22µF ×2, 25V, 1210, X5R
GRM32ER61E226ME15L
COMPENSATION
LOAD STEP
(A)
LOAD STEP
SLEW RATE
(A/µs)
P-P
DERIVATION
(mV)
RECOVERY
TIME
(µs)
22µF ×2
CTH = 2.2nF, RTH = 10k
1A – 1.5A
0.5
500
200
22µF ×2
CTH = 2.2nF, RTH = 10k
1A – 2A
1
180
70
VOUT
(V)
fSW
(MHz)
COUT
(CERAMIC)
2.6
5
1
3.3
1.8
1
VIN
(V)
3.3
3.3
1
22µF ×2
CTH = 2.2nF, RTH = 10k
1A – 2A
1
310
95
5
3.3
1
22µF ×2
CTH = 2.2nF, RTH = 10k
1A – 2A
1
270
95
5
5
1
22µF ×2
CTH = 2.2nF, RTH = 10k
1A – 2A
1
500
170
18
Rev. 0
For more information www.analog.com
LTM4693
APPLICATIONS INFORMATION
• Use large PCB copper areas for high current paths,
including VIN, GND and VOUT. It helps to minimize the
PCB conduction loss and thermal stress.
• Do not put via directly on the pad, unless they are
capped or plated over.
• Bring out test points on the signal pins for monitoring.
• Place high frequency ceramic input and output capacitors next to the VIN, GND and VOUT pins to minimize
high frequency noise.
Figure 15 gives a good example of the recommended layout.
• Place a dedicated power ground layer underneath
the unit.
• To minimize the via conduction loss and reduce module
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
GND
CIN1
COUT1 COUT2
CIN2
VOUT
VIN
GND
4693 Fxx
Figure 15. Recommended PCB Layout
Rev. 0
For more information www.analog.com
19
LTM4693
TYPICAL APPLICATIONS
SW1 SW1 SW1 SW2 SW2 SW2
VIN
2.6V to 5.5V
CIN
22µF
VIN
VOUT
VIN
VOUT
VIN
VOUT
SS
COUT
22µF
LTM4693
FREQ
VOUT
3.3V/1.5A
(2A AT BUCK)
26.2k
FB
MODE/SYNC
RUN/UVLO
COMP
10k
GND GND GND GND GND GND GND
2.2nF
4693 TA02
Figure 16. 2.6V to 5.5V Input, 3.3V Output with Minimum Components (Default 2ms Soft-Start Time and 1MHz Switching Frequency)
SW1 SW1 SW1 SW2 SW2 SW2
VIN
2.6V to 5.5V
CIN
22µF
VIN
VOUT
VIN
VOUT
VIN
VOUT
SS
0.1µF
75.5k
FB
MODE/SYNC
RUN/UVLO
VIN
COUT
100µF
LTM4693
FREQ
110k
VOUT
1.8V/2A
COMP
10k
GND GND GND GND GND GND GND
2.2nF
4693 TA03
Figure 17. 2.6V to 5.5V Input, 1.8V Output with Adjustable SS Time and 2MHz Switching Frequency
PACKAGE DESCRIPTION
LTM4693 LGA Pinout
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
A1
GND
A2
SW1
A3
GND
A4
SW2
A5
GND
B1
GND
B2
SW1
B3
GND
B4
SW2
B5
GND
C1
VIN
C2
SW1
C3
GND
C4
SW2
C5
VOUT
D1
VIN
D2
VIN
D3
SS
D4
VOUT
D5
VOUT
E1
RUN/UVLO
E2
MODE/SYNC
E3
FREQ
E4
FB
E5
COMP
20
Rev. 0
For more information www.analog.com
0.35 REF Ø 25x
PACKAGE TOP VIEW
1.30
SUGGESTED PCB LAYOUT
TOP VIEW
0.65
aaa Z
2×
E
0.000
4
0.65
PIN 1
CORNER
1.30
X
1.30
0.65
0.000
0.65
1.30
Y
D
aaa Z
SYMBOL
A
A1
b
D
E
e
F
G
H1
H2
aaa
bbb
ccc
ddd
eee
DETAIL B
H2
MOLD
CAP
DETAIL C
A1
NOM
1.25
0.35
4.00
3.50
0.65
2.60
2.60
0.25 REF
1.00 REF
MIN
1.15
0.32
0.15
0.10
0.10
0.15
0.08
MAX
1.35
0.03
0.38
DIMENSIONS
H1
DETAIL C
SUBSTRATE
b
ddd M Z X Y
eee M Z
SUBSTRATE THK
MOLD CAP HT
PAD DIMENSION
NOTES
DETAIL A
Øb (25 PLACES)
DETAIL B
PACKAGE SIDE VIEW
A
(Reference LTC DWG# 05-08-7014 Rev Ø)
ccc I Z
Z
2×
// bbb Z
LGA Package
25-Lead (3.5mm × 4mm × 1.25mm)
e
b
G
3
2
e
1
DETAIL A
PACKAGE BOTTOM VIEW
b
4
E
D
C
B
A
PIN 1
6
SEE NOTES
DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PIN 1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
4
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Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
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TRAY PIN 1
BEVEL
COMPONENT
PIN 1
6
!
LGA 25 0819 REV Ø
PACKAGE IN TRAY LOADING ORIENTATION
LTMXXXX
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
5. PRIMARY DATUM -Z- IS SEATING PLANE
LAND DESIGNATION PER JEP95
3
2. ALL DIMENSIONS ARE IN MILLIMETERS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
F
3
SEE NOTES
5
LTM4693
PACKAGE DESCRIPTION
Rev. 0
21
LTM4693
PACKAGE PHOTO
DESIGN RESOURCES
SUBJECT
DESCRIPTION
µModule Design and Manufacturing Resources
Design:
• Selector Guides
• Demo Boards and Gerber Files
• Free Simulation Tools
µModule Regulator Products Search
1. Sort table of products by parameters and download the result as a spread sheet.
Manufacturing:
• Quick Start Guide
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability
2. Search using the Quick Power Search parametric table.
Digital Power System Management
Analog Devices’ family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTM8083
36VIN, 36VOUT, 1.5A Buck-Boost µModule Regulator
3V ≤ VIN ≤ 36V, 1V ≤ VOUT ≤ 36V, 6.25mm × 6.25mm × 2.22mm BGA
LTM8054
36VIN, 36VOUT, 5.4A Buck-Boost µModule Regulator
5V ≤ VIN ≤ 36V, 1.2V ≤ VOUT ≤ 36V, 11.25mm × 15mm × 3.42mm BGA
LTM8055
36VIN, 36VOUT, 8.5A Buck-Boost µModule Regulator
5V ≤ VIN ≤ 36V, 1.2V ≤ VOUT ≤ 36V, 15mm × 15mm × 4.92mm BGA
LTM8056
58VIN, 48VOUT, 5.5A Buck-Boost µModule Regulator
5V ≤ VIN ≤ 58V, 1.2V ≤ VOUT ≤ 48V, 15mm × 15mm × 4.92mm BGA
LTM8045
Single, Inverting or SEPIC µModule DC/DC Convertor
2.8V ≤ VIN ≤ 18V. ±2.5V ≤ VOUT ≤ ±15V, 6.25mm × 11.25mm × 4.92mm BGA
LTM8049
Dual Outputs, SEPIC and/or Inverting µModule Regulator
2.6V ≤ VIN ≤ 20V. ±2.5V ≤ VOUT ≤ ±25V, 9mm × 15mm × 2.42mm BGA
22
Rev. 0
09/21
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For more information www.analog.com
ANALOG DEVICES, INC. 2021
