LTM8053/LTM8053-1
40VIN, 3.5A Step-Down
Silent Switcher µModule Regulator
FEATURES
DESCRIPTION
Complete Step-Down Switch Mode Power Supply
nn Low Noise Silent Switcher® Architecture
nn Wide Input Voltage Range: 3.4V to 40V
nn Wide Output Voltage Range: 0.97V to 15V
nn 3.5A Continuous Output Current at 12V , 5V
IN
OUT,
TA = 85°C
nn 6A Peak Output Current
nn Parallelable for Increased Output Current
nn Selectable Switching Frequency: 200kHz to 3MHz
nn Tiny, Low Profile 6.25mm × 9mm × 3.32mm RoHS
Compliant BGA Package
The LTM®8053 is a 40VIN, 3.5A continuous, 6A peak stepdown µModule® (power module) regulator. Included in
the package are the switching controller, power switches,
inductor, and all support components. Operating over an
input voltage range of 3.4V to 40V, the LTM8053/LTM80531 supports an output voltage range of 0.97V to 15V and a
switching frequency range of 200kHz to 3MHz, each set
by a single resistor. Only the input and output filter capacitors are needed to finish the design. The LTM8053-1 can
operate in forced continuous mode.
nn
The low profile package enables utilization of unused
space on the bottom of PC boards for high density point
of load regulation. The LTM8053/LTM8053-1 is packaged
in a thermally enhanced, compact over-molded ball grid
array (BGA) package suitable for automated assembly
by standard surface mount equipment. The LTM8053/
LTM8053-1 is RoHS compliant.
APPLICATIONS
Automotive Battery Regulation
Power for Portable Products
nn Distributed Supply Regulation
nn Industrial Supplies
nn Wall Transformer Regulation
nn
nn
All registered trademarks and trademarks are the property of their respective owners.
TYPICAL APPLICATION
5VOUT from 7VIN to 40VIN Step-Down Converter
Efficiency, VOUT = 5V
95
LTM8053
BIAS
AUX
RUN
4.7µF
85
VOUT
5V
3.5A
VOUT
RT
40.2k
1MHz
GND
SYNC
FB
60.4k
100µF
EFFICIENCY (%)
VIN
VIN
7V TO 40V
8053 TA01a
75
65
PINS NOT USED IN THIS CIRCUIT: TR/SS, PG, SHARE
55
12VIN
0
1
2
3
LOAD CURRENT (A)
4
8053 TA01
Rev D
Document Feedback
For more information www.analog.com
1
LTM8053/LTM8053-1
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
VIN, RUN, PG Voltage.................................................42V
AUX, VOUT, BIAS Voltage...........................................19V
FB, TR/SS Voltage.......................................................4V
SYNC Voltage...............................................................6V
Maximum Internal Temperature............................. 125°C
Storage Temperature.............................. –50°C to 125°C
Peak Reflow Solder Body Temperature.................. 250°C
TOP VIEW
BANK 2
VIN
RUN
GND
6
5
4
AUX
BIAS
RT TR/SS
SHARE SYNC
3
2
1
BANK 1
BANK 3
GND
VOUT
PG
GND FB
A
B
C
D
E
F
G
H
48-LEAD (9mm × 6.25mm × 3.32mm) BGA PACKAGE
TJMAX = 125°C, θJA = 24.3°C/W, θJCbottom = 5.8°C/W,
θJCtop = 16.8°C/W, θJB = 5.9°C/W, WEIGHT = 0.5g
θ VALUES DETERMINED PER JEDEC 51-9, 51-12
ORDER INFORMATION
PART MARKING*
PART NUMBER
LTM8053EY#PBF
LTM8053IY#PBF
LTM8053EY-1#PBF
LTM8053IY-1#PBF
TERMINAL FINISH
DEVICE
FINISH CODE
PACKAGE
TYPE
MSL
RATING
SAC305 (RoHS)
LTM8053
e1
BGA
3
–40°C to 125°C
SAC305 (RoHS)
LTM8053-1
e1
BGA
3
–40°C to 125°C
• Consult Marketing for parts specified with wider operating temperature
ranges. *Device temperature grade is indicated by a label on the shipping
container. Pad or ball finish code is per IPC/JEDEC J-STD-609.
2
TEMPERATURE RANGE
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures
• LGA and BGA Package and Tray Drawings
Rev D
For more information www.analog.com
LTM8053/LTM8053-1
ELECTRICAL
CHARACTERISTICS
The
l denotes the specifications which apply over the specified internal
operating temperature range, otherwise specifications are at TJ = 25°C. VIN = 12V, RUN = 2V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
Minimum Input Voltage
VIN Rising
Output DC Voltage
RFB Open
RFB = 16.9kΩ, VIN = 40V
Peak Output DC Current
VOUT = 3.3V, fSW = 1MHz
Quiescent Current Into VIN
RUN = 0V
BIAS = 0V, No Load, SYNC = 0V, Not Switching
3
300
µA
µA
Quiescent Current Into BIAS
BIAS = 5V, RUN = 0V
BIAS = 5V, No Load, SYNC = 0V, Not Switching
BIAS = 5V, VOUT = 3.3V, IOUT = 3.5A, fSW = 1MHz
1
275
12
µA
µA
mA
Line Regulation
5.5V < VIN < 36V, IOUT = 1A
0.5
%
Load Regulation
0.1A < IOUT < 3.5A
0.5
%
Output Voltage Ripple
IOUT = 3.5A
10
mV
Switching Frequency
RT = 232kΩ
RT = 41.2kΩ
RT = 10.7kΩ
200
0.95
3
kHz
MHz
MHz
3.4
RUN Threshold Voltage
950
970
0.9
RUN Current
TR/SS Pull-Down
PG Threshold Voltage at FB (Upper)
V
V
V
A
(Note 5)
TR/SS = 0V
UNITS
6
l
TR/SS Current
MAX
0.97
15
Voltage at FB
Minimum BIAS Voltage
TYP
l
980
mV
3.2
V
1.06
V
1
µA
2
µA
TR/SS = 0.1V
200
Ω
FB Falling (Note 6)
1.05
V
PG Threshold Voltage at FB (Lower)
FB Rising (Note 6)
0.89
PG Leakage Current
PG = 42V
PG Sink Current
PG = 0.1V
V
1
µA
150
µA
SYNC Threshold Voltage
Synchronization
0.4
1.5
V
SYNC Voltage
To Enable Spread Spectrum
2.9
4.2
V
SYNC Current
SYNC = 0V
35
µA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Unless otherwise noted, the absolute minimum voltage is zero.
Note 3: The LTM8053E/LTM8053E-1 is guaranteed to meet performance
specifications from 0°C to 125°C internal. Specifications over the full
–40°C to 125°C internal operating temperature range are assured by
design, characterization and correlation with statistical process controls.
The LTM8053I/LTM8053I-1 is guaranteed to meet specifications over
the full –40°C to 125°C internal operating temperature range. Note that
the maximum internal temperature is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
resistance and other environmental factors.
Note 4: The LTM8053/LTM8053-1 contains overtemperature protection
that is intended to protect the device during momentary overload
conditions. The internal temperature exceeds the maximum operating
junction temperature when the overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 5. Below this specified voltage, internal circuitry will draw power
from VIN.
Note 6. PG transitions from low to high.
Rev D
For more information www.analog.com
3
LTM8053/LTM8053-1
TYPICAL PERFORMANCE CHARACTERISTICS
90
65
55
45
70
0
1
2
3
LOAD CURRENT (A)
50
4
12VIN
24VIN
36VIN
0
1
2
3
LOAD CURRENT (A)
90
60
LTM8053 Efficiency vs Load
Current, VOUT = 2V, BIAS = 5V
1
2
3
LOAD CURRENT (A)
EFFICIENCY (%)
70
50
4
95
0
1
55
0
1
2
3
LOAD CURRENT (A)
4
8053 G07
4
2
3
LOAD CURRENT (A)
LTM8053 Efficiency vs Load
Current, VOUT = 2.5V, BIAS = 5V
70
55
4
12VIN
24VIN
36VIN
0
1
2
3
LOAD CURRENT (A)
4
8053 G06
LTM8053 Efficiency vs Load
Current, VOUT = 5V, BIAS = 5V
95
EFFICIENCY (%)
75
55
LTM8053 Efficiency vs Load
Current, VOUT = 8V, BIAS = 5V
85
65
12VIN
24VIN
36VIN
4
60
12VIN
24VIN
36VIN
85
EFFICIENCY (%)
EFFICIENCY (%)
85
65
2
3
LOAD CURRENT (A)
8053 G05
LTM8053 Efficiency vs Load
Current, VOUT = 3.3V, BIAS = 5V
75
1
80
8053 G04
95
90
60
12VIN
24VIN
36VIN
0
0
8053 G03
80
EFFICIENCY (%)
EFFICIENCY (%)
80
50
50
4
12VIN
24VIN
36VIN
8053 G02
LTM8053 Efficiency vs Load
Current, VOUT = 1.8V, BIAS = 5V
70
70
60
60
12VIN
24VIN
36VIN
LTM8053 Efficiency vs Load
Current, VOUT = 1.5V, BIAS = 5V
80
8053 G01
90
90
80
EFFICIENCY (%)
EFFICIENCY (%)
75
LTM8053 Efficiency vs Load
Current, VOUT = 1.2V, BIAS = 5V
EFFICIENCY (%)
85
LTM8053 Efficiency vs Load
Current, VOUT = 0.97V, BIAS = 5V
TA = 25°C, unless otherwise noted.
75
65
12VIN
24VIN
36VIN
0
1
2
3
LOAD CURRENT (A)
4
8053 G08
55
12VIN
24VIN
36VIN
0
1
2
3
LOAD CURRENT (A)
4
8053 G09
Rev D
For more information www.analog.com
LTM8053/LTM8053-1
TYPICAL PERFORMANCE CHARACTERISTICS
100
90
85
90
80
75
55
EFFICIENCY (%)
95
65
80
70
24VIN
36VIN
0
1
2
3
LOAD CURRENT (A)
60
4
24VIN
36VIN
0
1
2
3
LOAD CURRENT (A)
50
4
80
80
80
1
70
60
5VIN
12VIN
24VIN
36VIN
0
EFFICIENCY (%)
90
EFFICIENCY (%)
90
50
2
3
LOAD CURRENT (A)
50
4
0
1
2
3
LOAD CURRENT (A)
0.6
12VIN
24VIN
0
0.5
1
1.5
LOAD CURRENT (A)
2
2.5
5VIN
12VIN
24VIN
0
1.00
12VIN
24VIN
36VIN
0.2
0
2
4
LOAD CURRENT (A)
8053 G16
3
LTM8053 Input vs Load Current
VOUT = 1.2V, BIAS = 5V
0.4
0
1
2
LOAD CURRENT (A)
8053 G15
INPUT CURRENT (A)
80
INPUT CURRENT (A)
0.8
50
50
4
LTM8053 Input vs Load Current
VOUT = 0.97V, BIAS = 5V
90
4
70
8053 G14
LTM8053 Efficiency vs Load
Current, VOUT = –15V, BIAS Tied
to LTM8053 GND
60
2
3
LOAD CURRENT (A)
60
5VIN
12VIN
24VIN
8053 G13
70
1
LTM8053 Efficiency vs Load
Current, VOUT = –12V, BIAS Tied
to LTM8053 GND
90
60
0
8053 G12
LTM8053 Efficiency vs Load
Current, VOUT = –8V, BIAS Tied to
LTM8053 GND
70
5VIN
12VIN
24VIN
36VIN
8053 G11
LTM8053 Efficiency vs Load
Current, VOUT = –5V, BIAS Tied to
LTM8053 GND
EFFICIENCY (%)
70
60
8053 G10
EFFICIENCY (%)
LTM8053 Efficiency vs Load
Current, VOUT = –3.3V, BIAS Tied
to LTM8053 GND
LTM8053 Efficiency vs Load
Current, VOUT = 15V, BIAS = 5V
EFFICIENCY (%)
EFFICIENCY (%)
LTM8053 Efficiency vs Load
Current, VOUT = 12V, BIAS = 5V
TA = 25°C, unless otherwise noted.
6
8053 G17
12VIN
24VIN
36VIN
0.75
0.50
0.25
0
0
2
4
LOAD CURRENT (A)
6
8053 G18
Rev D
For more information www.analog.com
5
LTM8053/LTM8053-1
TYPICAL PERFORMANCE CHARACTERISTICS
1.25
12VIN
24VIN
36VIN
0.3
0.75
0.50
0.25
0
2
4
LOAD CURRENT (A)
0
6
0
2
4
LOAD CURRENT (A)
0.4
2
4
LOAD CURRENT (A)
1.0
0
6
0
2
4
LOAD CURRENT (A)
2
4
LOAD CURRENT (A)
6
8053 G25
6
0
6
0
2
4
LOAD CURRENT (A)
4
LTM8053 Input vs Load Current
VOUT = 15V, BIAS = 5V
24VIN
36VIN
3
2
1
0
0
2
4
LOAD CURRENT (A)
6
8053 G24
INPUT CURRENT (A)
INPUT CURRENT (A)
INPUT CURRENT (A)
1
0
0.75
24VIN
36VIN
2
0
12VIN
24VIN
36VIN
1.50
4
12VIN
24VIN
36VIN
6
LTM8053 Input vs Load Current
VOUT = 5V, BIAS = 5V
2.25
LTM8053 Input vs Load Current
VOUT = 12V, BIAS = 5V
3
2
4
LOAD CURRENT (A)
8053 G23
LTM8053 Input vs Load Current
VOUT = 8V, BIAS = 5V
4
0
8053 G21
INPUT CURRENT (A)
1.5
8053 G22
5
0
3.00
0.5
0
0.6
6
12VIN
24VIN
36VIN
2.0
INPUT CURRENT (A)
INPUT CURRENT (A)
2.5
0.8
0.9
0.3
LTM8053 Input vs Load Current
VOUT = 3.3V, BIAS = 5V
12VIN
24VIN
36VIN
1.2
12VIN
24VIN
36VIN
8053 G20
LTM8053 Input vs Load Current
VOUT = 2.5V, BIAS = 5V
1.6
LTM8053 Input vs Load Current
VOUT = 2V, BIAS = 5V
1.2
8053 G19
0
1.5
12VIN
24VIN
36VIN
1.00
0.6
0
LTM8053 Input vs Load Current
VOUT = 1.8V, BIAS = 5V
INPUT CURRENT (A)
0.9
INPUT CURRENT (A)
INPUT CURRENT (A)
1.2
LTM8053 Input vs Load Current
VOUT = 1.5V, BIAS = 5V
TA = 25°C, unless otherwise noted.
6
8053 G26
3
2
1
0
0
2
4
LOAD CURRENT (A)
6
8053 G27
Rev D
For more information www.analog.com
LTM8053/LTM8053-1
TYPICAL PERFORMANCE CHARACTERISTICS
LTM8053 Input vs Load Current
VOUT = –3.3V, BIAS tied to
LTM8053 GND
3
12VIN
24VIN
36VIN
INPUT CURRENT (A)
2.0
INPUT CURRENT (A)
LTM8053 Input vs Load Current
VOUT = –5V, BIAS Tied to
LTM8053 GND
1.5
1.0
LTM8053 Input vs Load Current
VOUT = –8V, BIAS Tied to
LTM8053 GND
4
12VIN
24VIN
36VIN
INPUT CURRENT (A)
2.5
TA = 25°C, unless otherwise noted.
2
1
0.5
0
0
2
4
LOAD CURRENT (A)
0
6
0
2
4
LOAD CURRENT (A)
4
4
2
1
2
1
5.5
0
0.5
1
1.5
LOAD CURRENT (A)
3.0
LTM8053 BIAS Current vs Load
CurrentVOUT = 1.5V, BIAS = 5V
0
2
4
LOAD CURRENT (A)
6
12VIN
24VIN
36VIN
0
2
4
LOAD CURRENT (A)
5.5
4.5
4.0
3.0
6
LTM8053 BIAS Current vs Load
Current VOUT = 1.8V, BIAS = 5V
5.0
3.5
12VIN
24VIN
36VIN
3.0
8053 G33
BIAS CURRENT (mA)
3.5
3.5
2.0
2
5.0
BIAS CURRENT (mA)
BIAS CURRENT (mA)
5.0
4
LTM8053 BIAS Current vs Load
Current VOUT = 0.97V, BIAS = 5V
8053 G32
LTM8053 BIAS Current vs Load
Current VOUT = 1.2V, BIAS = 5V
4.0
2
3
LOAD CURRENT (A)
2.5
8053 G31
4.5
1
4.0
3
0
3
4.5
BIAS CURRENT (mA)
INPUT CURRENT (A)
INPUT CURRENT (A)
3
0
8053 G30
12VIN
24VIN
12VIN
24VIN
1
2
LOAD CURRENT (A)
1
LTM8053 Input vs Load Current
VOUT = –15V, BIAS Tied to
LTM8053 GND
LTM8053 Input vs Load Current
VOUT = –12V, BIAS tied to
LTM8053 GND
0
2
8053 G29
8053 G28
0
3
0
6
12VIN
24VIN
2
4
LOAD CURRENT (A)
6
8053 G35
8053 G34
4.0
3.5
12VIN
24VIN
36VIN
0
4.5
3.0
12VIN
24VIN
36VIN
0
2
4
LOAD CURRENT (A)
6
8053 G36
Rev D
For more information www.analog.com
7
LTM8053/LTM8053-1
TYPICAL PERFORMANCE CHARACTERISTICS
6.5
BIAS CURRENT (mA)
BIAS CURRENT (mA)
5.0
4.5
4.0
7.0
2
4
LOAD CURRENT (A)
5.5
5.0
4.5
12VIN
24VIN
36VIN
0
6.5
4.0
6
6
5
12VIN
24VIN
36VIN
0
2
4
LOAD CURRENT (A)
0
2
4
LOAD CURRENT (A)
4.5
6
12VIN
24VIN
36VIN
0
12
LTM8053 BIAS Current vs Load
Current, VOUT = 12V, BIAS = 5V
8
7
2
4
LOAD CURRENT (A)
9
8
12VIN
24VIN
36VIN
0
10
7
6
24VIN
36VIN
0
2
4
LOAD CURRENT (A)
8053 G41
LTM8053 BIAS Current vs Load
Current, VOUT = 15V, BIAS = 5V
900
LTM8053 Dropout Voltage vs Load
Current, VOUT = 5V, BIAS = 5V
2250
8
7
6
24VIN
36VIN
0
2
4
LOAD CURRENT (A)
6
INPUT CURRENT (mA)
DROPOUT VOLTAGE (mV)
BIAS CURRENT (mA)
9
600
300
0
0
2
4
LOAD CURRENT (A)
8053 G43
8
6
8053 G44
6
8053 G42
LTM8053 Input Current vs VIN
VOUT Short-Circuited
SYNC Grounded
SYNC Floating
11
10
6
11
9
6
6
2
4
LOAD CURRENT (A)
8053 G39
LTM8053 BIAS Current vs Load
Current, VOUT = 8V, BIAS = 5V
8053 G40
12
5.0
BIAS CURRENT (mA)
BIAS CURRENT (mA)
BIAS CURRENT (mA)
10
7
5.5
8053 G38
LTM8053 BIAS Current vs Load
Current, VOUT = 5V, BIAS = 5V
8
6.0
12VIN
24VIN
36VIN
8053 G37
9
LTM8053 BIAS Current vs Load
Current, VOUT = 3.3V, BIAS = 5V
6.0
5.5
3.5
LTM8053 BIAS Current vs Load
Current, VOUT = 2.5V, BIAS = 5V
BIAS CURRENT (mA)
6.0
LTM8053 BIAS Current vs Load
Current, VOUT = 2V, BIAS = 5V
TA = 25°C, unless otherwise noted.
1500
750
0
3
16
28
VIN (V)
40
8053 G45
Rev D
For more information www.analog.com
LTM8053/LTM8053-1
TYPICAL PERFORMANCE CHARACTERISTICS
LTM8053 Maximum Load Current
vs VIN, BIAS Open
LTM8053 Maximum Load Current
vs VIN, BIAS Open
7
2
–3.3VOUT
–5VOUT
–8VOUT
1
0
10
20
30
INPUT VOLTAGE (V)
40
MAXIMUM LOAD CURRENT (A)
3
2.0
1.5
1.0
0.5
–12VOUT
–15VOUT
0
8053 G46
7
MAXIMUM LOAD CURRENT (A)
MAXIMUM LOAD CURRENT (A)
5
4
3
2
12VIN
24VIN
36VIN
1
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
6
5
4
3
2
12VIN
24VIN
36VIN
1
0
125
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
3
2
12VIN
24VIN
36VIN
1
0
7
MAXIMUM LOAD CURRENT (A)
MAXIMUM LOAD CURRENT (A)
4
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
125
12VIN
24VIN
36VIN
1
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
7
0 LFM
6
5
4
3
2
12VIN
24VIN
36VIN
1
0
125
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
5
4
3
2
12VIN
24VIN
36VIN
1
0
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
125
8053 G53
8053 G52
125
8053 G51
LTM8053 Derating, VOUT = 3.3V,
BIAS = 5V, DC1934A Demo Board
7
0 LFM
6
125
LTM8053 Derating, VOUT = 1.8V,
BIAS = 5V, DC1934A Demo Board
LTM8053 Derating, VOUT = 2.5V,
BIAS = 5V, DC1934A Demo Board
0 LFM
5
2
8053 G50
LTM8053 Derating, VOUT = 2V,
BIAS = 5V, DC1934A Demo Board
6
3
8053 G48
0 LFM
8053 G49
7
4
LTM8053 Derating, VOUT = 1.5V,
BIAS = 5V, DC1934A Demo Board
0 LFM
6
5
0
30
0 LFM
6
8053 G47
LTM8053 Derating, VOUT = 1.2V,
BIAS = 5V, DC1934A Demo Board
7
10
20
INPUT VOLTAGE (V)
MAXIMUM LOAD CURRENT (A)
4
2.5
MAXIMUM LOAD CURRENT (A)
5
0
LTM8053 Derating, VOUT = 0.97V,
BIAS = 5V, DC1934A Demo Board
3.0
MAXIMUM LOAD CURRENT (A)
MAXIMUM LOAD CURRENT (A)
6
0
TA = 25°C, unless otherwise noted.
0 LFM
6
5
4
3
2
12VIN
24VIN
36VIN
1
0
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
125
8053 G54
Rev D
For more information www.analog.com
9
LTM8053/LTM8053-1
TYPICAL PERFORMANCE CHARACTERISTICS
LTM8053 Derating, VOUT = 5V,
BIAS = 5V, DC1934A Demo Board
3
2
12VIN
24VIN
36VIN
1
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
125
5
4
3
2
12VIN
24VIN
36VIN
1
0
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
8053 G55
4
3
2
24VIN
36VIN
0
4
3
2
1
0
24VIN
36VIN
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
25
50
75
100
AMBIENT TEMPERATURE (°C)
5
4
3
2
12VIN
24VIN
36VIN
1
0
125
0 LFM
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
LTM8053 Derating, VOUT = –5V,
BIAS Tied to LTM8053 GND,
DC1934A Demo Board
4
3
2
0
4
MAXIMUM LOAD CURRENT (A)
MAXIMUM LOAD CURRENT (A)
LTM8053 Derating, VOUT = –8V,
BIAS Tied to LTM8053 GND,
DC1934A Demo Board
0 LFM
1
12VIN
24VIN
36VIN
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
125
0 LFM
3
2
1
0
12VIN
24VIN
0
8053 G60
10
125
8053 G59
8053 G58
5
125
8053 G57
6
MAXIMUM LOAD CURRENT (A)
MAXIMUM LOAD CURRENT (A)
5
0
5
LTM8053 Derating, VOUT = –3.3V,
BIAS Tied to LTM8053 GND,
DC1934A Demo Board
0 LFM
1
125
0 LFM
8053 G56
LTM8053 Derating, VOUT = 15V,
BIAS = 5V, DC1934A Demo Board
6
6
0 LFM
MAXIMUM LOAD CURRENT (A)
4
0
6
0 LFM
5
LTM8053 Derating, VOUT = 12V,
BIAS = 5V, DC1934A Demo Board
LTM8053 Derating, VOUT = 8V,
BIAS = 5V, DC1934A Demo Board
MAXIMUM LOAD CURRENT (A)
MAXIMUM LOAD CURRENT (A)
6
TA = 25°C, unless otherwise noted.
25
50
75
100
AMBIENT TEMPERATURE (°C)
125
8053 G61
Rev D
For more information www.analog.com
LTM8053/LTM8053-1
TYPICAL PERFORMANCE CHARACTERISTICS
LTM8053 Derating, VOUT = –12V,
BIAS Tied to LTM8053 GND,
DC1934A Demo Board
12VIN
24VIN
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
125
8053 G62
55
0 LFM
5VOUT, 3.5A Load
14VIN, fSW = 1MHz
45
1.5
AMPLITUDE (dBuV/m)
1
0
2.0
0 LFM
2
LTM8053 CISPR32 Class B Emissions
DC1934A Demo Board, No EMI Filter
(C10 = 0.1µF, Short L1, Open C7)
LTM8053 Derating, VOUT = –15V,
BIAS Tied to LTM8053 GND,
DC1934A Demo Board
MAXIMUM LOAD CURRENT (A)
MAXIMUM LOAD CURRENT (A)
3
TA = 25°C, unless otherwise noted.
1.0
0.5
0
25
15
5
12VIN
24VIN
0
Class B Limit
35
25
50
75
100
AMBIENT TEMPERATURE (°C)
125
8053 G63
–5
0
200
400
600
FREQUENCY (MHz)
800
1000
8053 G64
Rev D
For more information www.analog.com
11
LTM8053/LTM8053-1
PIN FUNCTIONS
GND (Bank 1, A1, A6, B3): Tie these GND pins to a local
ground plane below the LTM8053/LTM8053-1 and the
circuit components. In most applications, the bulk of the
heat flow out of the LTM8053/LTM8053-1 is through these
pads, so the printed circuit design has a large impact on
the thermal performance of the part. See the PCB Layout
and Thermal Considerations sections for more details.
VIN (Bank 2): VIN supplies current to the LTM8053/
LTM8053-1’s internal regulator and to the internal power
switch. These pins must be locally bypassed with an external, low ESR capacitor; see Table 2 for recommended
values.
VOUT (Bank 3): Power Output Pins. Apply the output
filter capacitor and the output load between these pins
and GND pins.
BIAS (Pin A2): The BIAS pin connects to the internal power
bus. Connect to a power source greater than 3.2V. If VOUT
is greater than 3.2V, connect this pin to AUX. Decouple
this pin with at least 1µF if the voltage source for BIAS is
remote. If unused or when generating a negative output,
connect BIAS to LTM8053/LTM8053-1 GND.
PG (Pin A3): The PG pin is the open-collector output
of an internal comparator. PG remains low until the FB
pin voltage is between 0.89V and 1.05V typical. The PG
signal is valid when VIN is above 3.4V. If VIN is above
3.4V and RUN is low, PG will drive low. If this function
is not used, leave this pin floating.
SHARE (Pin A4, LTM8053 only): Tie this to the SHARE
pin of another LTM8053 to load share. Otherwise leave
floating. Do not drive this pin.
VC (Pin A4, LTM8053-1 only): Error Amplifier Output.
The LTM8053-1 has internal compensation, so this pin
is normally not used. In some cases, it may be beneficial to connect an RC network to this pin to modify the
LTM8053-1 behavior.
RT (Pin A5): The RT pin is used to program the switching frequency of the LTM8053/LTM8053-1 by connecting a resistor from this pin to ground. The Applications
Information section of the data sheet includes a table
to determine the resistance value based on the desired
12
switching frequency. Minimize capacitance at this pin.
Do not drive this pin.
FB (Pin B1): The LTM8053/LTM8053-1 regulates its
FB pin to 0.97V. Connect the adjust resistor from this
pin to ground. The value of RFB is given by the equation
RFB = 241.53/(VOUT – 0.97), where RFB is in kΩ.
AUX (Pin B2): Low Current Voltage Source for BIAS.
In many designs, the BIAS pin is simply connected to
VOUT. The AUX pin is internally connected to VOUT and
is placed adjacent to the BIAS pin to ease printed circuit
board routing. Also, some applications require a feedforward capacitor; it can be connected from AUX to FB
for convenient PCB routing. Although this pin is internally
connected to VOUT, it is not intended to deliver a high
current, so do not draw current from this pin to the load.
SYNC (Pin B4, LTM8053 only): External Clock Synchronization Input and Operational Mode. This pin programs
four different operating modes: 1) Burst Mode® operation.
Tie this pin to ground for Burst Mode operation at low
output loads—this will result in low quiescent current.
2) Pulse-skipping mode. Float this pin for pulse-skipping
mode. This mode offers full frequency operation down
to low output loads before pulse-skipping mode occurs.
3) Spread spectrum mode. Tie this pin high (between
2.9V and 4.2V) for pulse-skipping mode with spread
spectrum modulation. 4) Synchronization mode. Drive
this pin with a clock source to synchronize to an external
frequency. During synchronization the part will operate
in pulse-skipping mode.
SYNC (Pin B4, LTM8053-1 only): External Clock Synchronization Input and Operational Mode. This pin programs
four different operating modes: 1) Burst Mode operation.
Tie this pin to ground for Burst Mode operation at low
output loads—this will result in low quiescent current.
2) Forced continuous mode (FCM). This mode offers full
frequency operation over a wide load range. Float this
pin for FCM. 3) Spread spectrum mode. Tie this pin high
(between 2.9V and 4.2V) for FCM with spread spectrum
modulation. 4) Synchronization mode. Drive this pin with
a clock source to synchronize to an external frequency.
During synchronization the part will operate in FCM.
Rev D
For more information www.analog.com
LTM8053/LTM8053-1
TR/SS (Pin B5): The TR/SS pin is used to provide a
soft-start or tracking function. The internal 2μA pull-up
current in combination with an external capacitor tied
to this pin creates a voltage ramp. If TR/SS is less than
0.97V, the FB voltage tracks to this value. For tracking, tie
a resistor divider to this pin from the tracked output. This
pin is pulled to ground with an internal MOSFET during
shutdown and fault conditions; use a series resistor if
driving from a low impedance output. This pin may be
left floating if the tracking function is not needed.
RUN (Pin B6): Pull the RUN pin below 0.9V to shut down
the LTM8053/LTM8053-1. Tie to 1.06V or more for normal
operation. If the shutdown feature is not used, tie this
pin to the VIN pin.
Table 1. LTM8053 Switching Modes
LTM8053
LTM8053-1
Burst Mode
Operation
Burst Mode
Operation
Operation when SYNC floating
DCM
FCM
Operation when SYNC
DCM
FCM
FCM with
Spread Spectrum
FCM with
Spread Spectrum
Operation when SYNC = 0V
Operation when SYNC between
2.9VDC and 4.2VDC
BLOCK DIAGRAM
LTM8053/LTM8053-1
BIAS
VIN
AUX
0.2µF
CURRENT
MODE
CONTROLLER
VOUT
249k
10pF
0.1µF
GND
FB
RUN
SHARE (LTM8053 ONLY)
VC (LTM8053-1 ONLY)
TR/SS
SYNC
RT
PG
8053 BD
Rev D
For more information www.analog.com
13
LTM8053/LTM8053-1
OPERATION
The LTM8053/LTM8053-1 is a stand-alone non-isolated
step-down switching DC/DC power supply that can deliver
up to 6A. The continuous current is determined by the
internal operating temperature. It provides a precisely
regulated output voltage programmable via one external
resistor from 0.97V to 15V. The input voltage range is
3.4V to 40V. Given that the LTM8053/LTM8053-1 is a
step-down converter, make sure that the input voltage is
high enough to support the desired output voltage and
load current. A simplified Block Diagram is given on the
previous page.
The LTM8053/LTM8053-1 contains a current mode controller, power switching elements, power inductor and
a modest amount of input and output capacitance. The
LTM8053/LTM8053-1 is a fixed frequency PWM regulator.
The switching frequency is set by simply connecting the
appropriate resistor value from the RT pin to GND.
An internal regulator provides power to the control circuitry. This bias regulator normally draws power from the
VIN pin, but if the BIAS pin is connected to an external
voltage higher than 3.2V, bias power is drawn from the
external source (typically the regulated output voltage).
This improves efficiency. The RUN pin is used to place
the LTM8053/LTM8053-1 in shutdown, disconnecting the
output and reducing the input current to a few μA.
To enhance efficiency, the LTM8053/LTM8053-1 automatically switches to Burst Mode operation in light or no load
situations. Between bursts, all circuitry associated with
controlling the output switch is shut down reducing the
input supply current.
The oscillator reduces the LTM8053/LTM8053-1’s operating frequency when the voltage at the FB pin is low. This
frequency foldback helps to control the output current
during start-up and overload.
14
If SYNC is grounded, both the LTM8053 and LTM8053-1
will operate in burst mode. If SYNC is floated or driven
high less than 4.2V, LTM8053 will operate in discontinuous
mode, while LTM8053-1 will operate in FCM.
The TR/SS node acts as an auxiliary input to the error
amplifier. The voltage at FB servos to the TR/SS voltage
until TR/SS goes about 0.97V. Soft-start is implemented
by generating a voltage ramp at the TR/SS pin using an
external capacitor which is charged by an internal constant
current. Alternatively, driving the TR/SS pin with a signal
source or resistive network provides a tracking function.
Do not drive the TR/SS pin with a low impedance voltage source. See the Applications Information section for
more details.
The LTM8053/LTM8053-1 contains a power good comparator which trips when the FB pin is between 0.89V and
1.05V, typical. The PG output is an open-drain transistor
that is off when the output is in regulation, allowing an
external resistor to pull the PG pin high. The PG signal
is valid when VIN is above 3.4V. If VIN is above 3.4V and
RUN is low, PG will drive low.
The LTM8053/LTM8053-1 is equipped with a thermal
shutdown that inhibits power switching at high junction
temperatures. The activation threshold of this function is
above 125°C to avoid interfering with normal operation,
so prolonged or repetitive operation under a condition in
which the thermal shutdown activates may damage or
impair the reliability of the device.
Two or more LTM8053s may be operated in parallel to
produce higher currents. The LTM8053-1 is not designed
for parallel operation.
Rev D
For more information www.analog.com
LTM8053/LTM8053-1
APPLICATIONS INFORMATION
For most applications, the design process is straightforward, summarized as follows:
1. Look at Table 2 and find the row that has the desired
input range and output voltage.
2. Apply the recommended CIN, COUT, RFB and RT values.
3. Apply the CFF (from AUX to FB) or CSHARE (from SHARE
to GND) capacitors as required.
4. Connect BIAS as indicated.
While these component combinations have been tested for
proper operation, it is incumbent upon the user to verify
proper operation over the intended system’s line, load and
environmental conditions. Bear in mind that the maximum
output current is limited by junction temperature, the
relationship between the input and output voltage magnitude and polarity and other factors. Please refer to the
graphs in the Typical Performance Characteristics section
for guidance.
The maximum frequency (and attendant RT value) at which
the LTM8053/LTM8053-1 should be allowed to switch
is given in Table 2 in the Maximum fSW column, while
the recommended frequency (and RT value) for optimal
efficiency over the given input condition is given in the
fSW column. There are additional conditions that must be
satisfied if the synchronization function is used. Please
refer to the Synchronization section for details.
Table 2. Recommended Component Values and Configuration (TA = 25°C)
RFB
CIN2
COUT
CFF
3.4V to 40V
0.97V
3.4V to 40V
1.2V
3.4V to 40V
1.5V
3.4V to 40V
1.8V
3.4V to 40V
2V
4V to 40V1
2.5V
5V to 40V1
3.3V
1
7V to 40V
5V
11V to 40V1
8V
16V to 40V1
12V
19.5V to 40V1 15V
4.5V to 25V1
–15V
Open
1.05M
464k
294k
237k
158k
102k
60.4k
34k
21.5k
16.9k
16.9k
4.7µF 50V 1206 X5R
4.7µF 50V 1206 X5R
4.7µF 50V 1206 X5R
4.7µF 50V 1206 X5R
4.7µF 50V 1206 X5R
4.7µF 50V 1206 X5R
4.7µF 50V 1206 X5R
4.7µF 50V 1206 X5R
4.7µF 50V 1206 X5R
4.7µF 50V 1206 X5R
4.7µF 50V 1206 X5R
4.7µF 50V 1206 X5R
2x 100µF 4V 0805 X5R
2x 100µF 4V 0805 X5R
100µF 4V 0805 X5R
100µF 4V 0805 X5R
100µF 4V 0805 X5R
100µF 4V 0805 X5R
100µF 4V 0805 X5R
100µF 6.3V 1206 X5R
47µF 10V 1210 X7R
22µF 16V 1210 X5S
22µF 16V 1210 X5S
22µF 16V 1210 X5S
47pF
47pF
27pF
10pF
3.4V to 28V1
–12V
21.5k
4.7µF 50V 1206 X5R 22µF 16V 1210 X5S
3.4V to 32V1
–8V
34k
4.7µF 50V 1206 X5R 47µF 10V 1210 X7R
3.4V to 35V1
–5V
60.4k
4.7µF 50V 1206 X5R 100µF 6.3V 1206 X5R
3.4V to 36V1
–3.3
102k
4.7µF 50V 1206 X5R 100µF 4V 0805 X5R
VIN
VOUT
CSHARE
47pF
47pF
BIAS
fSW
RT
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
LTM8053/
LTM8053-1
GND
LTM8053/
LTM8053-1
GND
LTM8053/
LTM8053-1
GND
LTM8053/
LTM8053-1
GND
LTM8053/
LTM8053-1
GND
450kHz
550kHz
600kHz
600kHz
650kHz
750kHz
850kHz
1MHz
1.2MHz
1.5MHz
1.5MHz
1.5MHz
100k
78.7k
71.5k
71.5k
64.9k
56.2k
48.7k
40.2k
33.2k
25.5k
25.5k
25.5k
MAX fSW MINRT
675kHz
850kHz
1.1MHz
1.3MHz
1.4MHz
1.8MHz
2.3MHz
3MHz
3MHz
3MHz
3MHz
3MHz
63.4k
49.9k
36.5k
30.9k
28k
20.5k
14.7k
10.7k
10.7k
10.7k
10.7k
10.7k
1.5MHz 25.5k
3MHz
10.7k
1.2MHz 33.2k
3MHz
10.7k
1MHz
40.2k
3MHz
10.7k
850kHz
48.7k
2.3MHz
14.7k
Note 1: The LTM8053/LTM8053-1 may be capable of lower input voltages but may skip switching cycles.
Note 2: An input bulk capacitor is required.
Rev D
For more information www.analog.com
15
LTM8053/LTM8053-1
APPLICATIONS INFORMATION
Capacitor Selection Considerations
Frequency Selection
The CIN and COUT capacitor values in Table 2 are the
minimum recommended values for the associated operating conditions. Applying capacitor values below those
indicated in Table 2 is not recommended, and may result
in undesirable operation. Using larger values is generally
acceptable, and can yield improved dynamic response, if
it is necessary. Again, it is incumbent upon the user to
verify proper operation over the intended system’s line,
load and environmental conditions.
The LTM8053/LTM8053-1 uses a constant frequency
PWM architecture that can be programmed to switch from
200kHz to 3MHz by using a resistor tied from the RT pin
to ground. Table 2 provides a list of RT resistor values and
their resultant frequencies.
Table 3. SW Frequency vs RT Value
fSW (MHz)
RT (kΩ)
0.2
232
0.3
150
Ceramic capacitors are small, robust and have very low
ESR. However, not all ceramic capacitors are suitable.
X5R and X7R types are stable over temperature and applied voltage and give dependable service. Other types,
including Y5V and Z5U have very large temperature and
voltage coefficients of capacitance. In an application circuit they may have only a small fraction of their nominal
capacitance resulting in much higher output voltage ripple
than expected.
Ceramic capacitors are also piezoelectric. In Burst Mode
operation, the LTM8053/LTM8053-1’s switching frequency
depends on the load current, and can excite a ceramic
capacitor at audio frequencies, generating audible noise.
Since the LTM8053/LTM8053-1 operates at a lower current
limit during Burst Mode operation, the noise is typically
very quiet to a casual ear.
If this audible noise is unacceptable, use a high performance electrolytic capacitor at the output. It may also be
a parallel combination of a ceramic capacitor and a low
cost electrolytic capacitor.
A final precaution regarding ceramic capacitors concerns
the maximum input voltage rating of the LTM8053/
LTM8053-1. A ceramic input capacitor combined with
trace or cable inductance forms a high-Q (underdamped)
tank circuit. If the LTM8053/LTM8053-1 circuit is plugged
into a live supply, the input voltage can ring to twice its
nominal value, possibly exceeding the device’s rating.
This situation is easily avoided; see the Hot-Plugging
Safely section.
16
0.4
110
0.5
88.7
0.6
71.5
0.7
60.4
0.8
52.3
1.0
40.2
1.2
33.2
1.4
28.0
1.6
23.7
1.8
20.5
2.0
18.2
2.2
15.8
3.0
10.7
Operating Frequency Trade-Offs
It is recommended that the user apply the optimal RT
value given in Table 2 for the input and output operating
condition. System level or other considerations, however,
may necessitate another operating frequency. While the
LTM8053/LTM8053-1 is flexible enough to accommodate
a wide range of operating frequencies, a haphazardly
chosen one may result in undesirable operation under
certain operating or fault conditions. A frequency that is
too high can reduce efficiency, generate excessive heat
or even damage the LTM8053/LTM8053-1 if the output
is overloaded or short-circuited. A frequency that is too
low can result in a final design that has too much output
ripple or too large of an output capacitor.
Rev D
For more information www.analog.com
LTM8053/LTM8053-1
APPLICATIONS INFORMATION
BIAS Pin Considerations
Load Sharing
The BIAS pin is used to provide drive power for the internal power switching stage and operate other internal
circuitry. For proper operation, it must be powered by at
least 3.2V. If the output voltage is programmed to 3.2V
or higher, BIAS may be simply tied to AUX. If VOUT is less
than 3.2V, BIAS can be tied to VIN or some other voltage
source. If the BIAS pin voltage is too high, the efficiency
of the LTM8053/LTM8053-1 may suffer. The optimum
BIAS voltage is dependent upon many factors, such as
load current, input voltage, output voltage and switching
frequency. In all cases, ensure that the maximum voltage
at the BIAS pin is less than 19V. If BIAS power is applied
from a remote or noisy voltage source, it may be necessary
to apply a decoupling capacitor locally to the pin. A 1µF
ceramic capacitor works well. The BIAS pin may also be
left open at the cost of a small degradation in efficiency.
If unused or when generating a negative output, connect
BIAS to LTM8053/LTM8053-1 GND.
Two or more LTM8053s may be paralleled to produce higher currents. To do this, tie the VIN, VOUT and
SHARE pins of all the paralleled LTM8053s together.
To ensure that paralleled modules start up together, the
TR/SS pins may be tied together, as well. If it is inconvenient
to tie the TR/SS pins together, make sure that the same
valued soft-start capacitors are used for each µModule
regulator. An example of two LTM8053s configured for
load sharing is given in the Typical Applications section.
Maximum Load
The maximum practical continuous load that the LTM8053
can drive, while rated at 3.5A, actually depends upon both
the internal current limit and the internal temperature.
The internal current limit is designed to prevent damage
to the LTM8053 in the case of overload or short-circuit.
The internal temperature of the LTM8053 depends upon
operating conditions such as the ambient temperature,
the power delivered, and the heat sinking capability of
the system. For example, if the LTM8053 is configured
to regulate at 1.2V, it may continuously deliver 5A from
12VIN if the ambient temperature is controlled to less than
60°C; this is quite a bit higher than the 3.5A continuous
rating. Please see the derating curve for VOUT = 1.2V in
the Typical Performance Characteristics section. Similarly,
if the output voltage is 15V and the ambient temperature
is 85°C, the LTM8053 will deliver at most 2A from 24VIN,
which is less than the 3.5A continuous rating. Furthermore,
the maximum output current of the LTM8053-1 can be
less than that of the LTM8053, especially above 8VOUT.
For closer load sharing, synchronize the LTM8053s to an
external clock source. When load sharing among n units
and using a single RFB resistor, the value of the resistor is:
R FB =
241.53
n ( VOUT – 0.97 )
where RFB is in kΩ.
Do not parallel LTM8053-1s. The LTM8053-1 is not designed for parallel operation.
Burst Mode Operation
To enhance efficiency at light loads, the LTM8053/
LTM8053-1 automatically switches to Burst Mode operation which keeps the output capacitor charged to the
proper voltage while minimizing the input quiescent current.
During Burst Mode operation, the LTM8053/LTM8053-1
delivers single cycle bursts of current to the output capacitor followed by sleep periods where most of the internal
circuitry is powered off and energy is delivered to the load
by the output capacitor. During the sleep time, VIN and
BIAS quiescent currents are greatly reduced, so, as the
load current decreases towards a no load condition, the
percentage of time that the LTM8053/LTM8053-1 operates
in sleep mode increases and the average input current is
greatly reduced, resulting in higher light load efficiency.
Burst Mode operation is enabled by tying SYNC to GND.
Rev D
For more information www.analog.com
17
LTM8053/LTM8053-1
APPLICATIONS INFORMATION
Minimum Input Voltage
The LTM8053/LTM8053-1 is a step-down converter, so
a minimum amount of headroom is required to keep the
output in regulation. Keep the input above 3.4V to ensure
proper operation. Voltage transients or ripple valleys
that cause the input to fall below 3.4V may turn off the
LTM8053/LTM8053-1.
Output Voltage Tracking and Soft-Start
The LTM8053/LTM8053-1 allows the user to program its
output voltage ramp rate by means of the TR/SS pin. An
internal 2μA pulls up the TR/SS pin to about 2.4V. Putting
an external capacitor on TR/SS enables soft starting the
output to reduce current surges on the input supply. During
the soft-start ramp the output voltage will proportionally
track the TR/SS pin voltage. For output tracking applications, TR/SS can be externally driven by another voltage
source. From 0V to 0.97V, the TR/SS voltage will override
the internal 0.97V reference input to the error amplifier,
thus regulating the FB pin voltage to that of the TR/SS
pin. When TR/SS is above 0.97V, tracking is disabled and
the feedback voltage will regulate to the internal reference
voltage. The TR/SS pin may be left floating if the function
is not needed.
An active pull-down circuit is connected to the TR/SS pin
which will discharge the external soft-start capacitor in
the case of fault conditions and restart the ramp when the
faults are cleared. Fault conditions that clear the soft-start
capacitor are the RUN pin transitioning low, VIN voltage
falling too low, or thermal shutdown.
Prebiased Output
As discussed in the Output Voltage Tracking and Soft-Start
section, the LTM8053/LTM8053-1 regulates the output to
the FB voltage determined by the TR/SS pin whenever TR/
SS is less than 0.97V. If the LTM8053/LTM8053-1 output
is higher than the target output voltage, the LTM8053/
LTM8053-1 will attempt to regulate the output to the target
voltage by returning a small amount of energy back to the
input supply. If there is nothing loading the input supply,
its voltage may rise. Take care that it does not rise so high
that the input voltage exceeds the absolute maximum rating
of the LTM8053/LTM8053-1. The LTM8053-1 is designed
18
to attempt to protect itself as the rising VIN approaches its
absolute maximum rating by disabling FCM.
Frequency Foldback
The LTM8053/LTM8053-1 is equipped with frequency
foldback which acts to reduce the thermal and energy
stress on the internal power elements during a short-circuit
or output overload condition. If the LTM8053/LTM8053-1
detects that the output has fallen out of regulation, the
switching frequency is reduced as a function of how far the
output is below the target voltage. This in turn limits the
amount of energy that can be delivered to the load under
fault. During the start-up time, frequency foldback is also
active to limit the energy delivered to the potentially large
output capacitance of the load. When a clock is applied
to the SYNC pin, the SYNC pin is floated or held high, the
frequency foldback is disabled and the switching frequency
will slow down only during overcurrent conditions.
Synchronization
To select low ripple Burst Mode operation, tie the SYNC
pin below about 0.4V (this can be ground or a logic low
output). To synchronize the LTM8053/LTM8053-1 oscillator to an external frequency connect a square wave (with
about 20% to 80% duty cycle) to the SYNC pin. The square
wave amplitude should have valleys that are below 0.4V
and peaks above 1.5V.
The LTM8053 will not enter Burst Mode operation at low
output loads while synchronized to an external clock, but
instead will pulse skip to maintain regulation. The LTM8053
may be synchronized over a 200kHz to 3MHz range. The RT
resistor should be chosen to set the LTM8053 switching
frequency equal to or below the lowest synchronization
input. For example, if the synchronization signal will be
500kHz and higher, the RT should be selected for 500kHz.
For some applications it is desirable for the LTM8053 to
operate in pulse-skipping mode, offering two major differences from Burst Mode operation. The first is that the
clock stays awake at all times and all switching cycles
are aligned to the clock. Second is that full switching frequency is reached at lower output load than in Burst Mode
operation. These two differences come at the expense of
Rev D
For more information www.analog.com
LTM8053/LTM8053-1
APPLICATIONS INFORMATION
increased quiescent current. To enable pulse-skipping
mode, the SYNC pin is floated.
VIN
VIN
The LTM8053-1 does not operate in discontinuous mode.
Instead, it operates in Burst Mode when SYNC is grounded,
and in forced continuous mode when SYNC is floated or
driven high and less than 4.2V. When an external SYNC
clock signal is applied, the LTM8053-1 operates in FCM.
VOUT
LTM8053
GND
NEGATIVE
OUTPUT VOLTAGE
8053 F01a
The LTM8053/LTM8053-1 features spread spectrum
operation to further reduce EMI/EMC emissions. To enable spread spectrum operation, apply between 2.9V and
4.2V to the SYNC pin. In this mode, triangular frequency
modulation is used to vary the switching frequency between
the value programmed by RT to about 20% higher than
that value. The modulation frequency is about 3kHz. For
example, when the LTM8053/LTM8053-1 is programmed
to 2MHz, the frequency will vary from 2MHz to 2.4MHz at
a 3kHz rate. When spread spectrum operation is selected,
Burst Mode operation is disabled, and the part will run in
pulse-skipping mode.
The LTM8053 does not operate in forced continuous mode
regardless of SYNC signal.
Figure 1a. The LTM8053/LTM8053-1 Can Be Used to
Generate a Negative Voltage
VIN
VIN
VOUT
LTM8053
GND
FAST LOAD
TRANSIENT
OUTPUT
TRANSIENT
RESPONSE
8053 F01b
Figure 1b. Any Output Voltage Transient Appears on
LTM8053/LTM8053-1 GND
FAST VIN
TRANSIENT
Negative Output
The LTM8053/LTM8053-1 is capable of generating a
negative output voltage by connected its VOUT to system
GND and the LTM8053/LTM8053-1 GND to the negative
voltage rail. An example of this is shown in the Typical
Applications section. The most versatile way to generate
a negative output is to use a dedicated regulator that
was designed to generate a negative voltage, but using a
buck regulator like the LTM8053/LTM8053-1 to generate
a negative voltage is a simple and cost effective solution,
as long as certain restrictions are kept in mind.
Figure 1a shows a typical negative output voltage application. Note that LTM8053/LTM8053-1 VOUT is tied to system
GND and input power is applied from VIN to LTM8053/
LTM8053-1 VOUT. As a result, the LTM8053/LTM8053-1
is not behaving as a true buck regulator, and the maximum
output current is depends upon the input voltage. In the
example shown in the Typical Applications section, there
is an attending graph that shows how much current the
LTM8053/LTM8053-1 deliver for given input voltages.
OUTPUT EXPERIENCES
A POSITIVE TRANSIENT
VIN
VIN
CIN
VOUT
LTM8053
COUT
GND
AC DIVIDER
OPTIONAL
SCHOTTKY
DIODE
8053 F01c
Figure 1c. A Schottky Diode Can Limit the Transient
Caused by a Fast Rising VIN to Safe Levels
Note that this configuration requires that any load current
transient will directly impress the transient voltage onto
the LTM8053/LTM8053-1 GND, as shown in Figure 1b, so
fast load transients can disrupt the LTM8053/LTM8053-1’s
operation or even cause damage. Carefully evaluate
whether the negative buck configuration is suitable for
the application.
The CIN and COUT capacitors in Figure 1c form an AC divider
at the negative output voltage node. If VIN is hot-plugged
Rev D
For more information www.analog.com
19
LTM8053/LTM8053-1
APPLICATIONS INFORMATION
or rises quickly, the resultant VOUT will be a positive transient, which may be unhealthy for the application load.
An antiparallel Schottky diode may be able to prevent this
positive transient from damaging the load. The location of
this Schottky diode is important. For example, in a system
where the LTM8053/LTM8053-1 is far away from the load,
placing the Schottky diode closest to the most sensitive
load component may be the best design choice. Carefully
evaluate whether the negative buck configuration is suitable
for the application. When generating a negative output,
connect BIAS to LTM8053/LTM8053-1 GND.
Shorted Input Protection
Care needs to be taken in systems where the output is
held high when the input to the LTM8053/LTM8053-1 is
absent. This may occur in battery charging applications or
in battery backup systems where a battery or some other
supply is diode OR-ed with the LTM8053/LTM8053-1’s
output. If the VIN pin is allowed to float and the RUN pin
is held high (either by a logic signal or because it is tied
to VIN), then the LTM8053/LTM8053-1’s internal circuitry
pulls its quiescent current through its internal power switch.
This is fine if your system can tolerate a few milliamps
in this state. If you ground the RUN pin, the internal current drops to essentially zero. However, if the VIN pin is
grounded while the output is held high, parasitic diodes
inside the LTM8053/LTM8053-1 can pull large currents
from the output through the VIN pin. Figure 2 shows a
circuit that runs only when the input voltage is present and
that protects against a shorted or reversed input.
VIN
VIN
LTM8053
RUN
8053 F02
Figure 2. The Input Diode Prevents a Shorted Input from
Discharging a Backup Battery Tied to the Output. It Also Protects
the Circuit from a Reversed Input. The LTM8053 Runs Only
When the Input Is Present.
20
PCB Layout
Most of the headaches associated with PCB layout have
been alleviated or even eliminated by the high level of
integration of the LTM8053/LTM8053-1. The LTM8053/
LTM8053-1 is nevertheless a switching power supply, and
care must be taken to minimize EMI and ensure proper
operation. Even with the high level of integration, you may
fail to achieve specified operation with a haphazard or poor
layout. See Figure 3 for a suggested layout. Ensure that
the grounding and heat sinking are acceptable.
A few rules to keep in mind are:
1. Place CFF, CSHARE, RFB and RT as close as possible to
their respective pins.
2. Place the CIN capacitor as close as possible to the VIN
and GND connection of the LTM8053/LTM8053-1.
3. Place the COUT capacitor as close as possible to the
VOUT and GND connection of the LTM8053/LTM8053-1.
4. Place the CIN and COUT capacitors such that their ground
current flow directly adjacent to or underneath the
LTM8053/LTM8053-1.
5. Connect all of the GND connections to as large a copper
pour or plane area as possible on the top layer. Avoid
breaking the ground connection between the external
components and the LTM8053/LTM8053-1.
6. Use vias to connect the GND copper area to the board’s
internal ground planes. Liberally distribute these GND
vias to provide both a good ground connection and
thermal path to the internal planes of the printed circuit
board. Pay attention to the location and density of the
thermal vias in Figure 3. The LTM8053/LTM8053-1
can benefit from the heat-sinking afforded by vias that
connect to internal GND planes at these locations, due
to their proximity to internal power handling components. The optimum number of thermal vias depends
upon the printed circuit board design. For example, a
board might use very small via holes. It should employ
more thermal vias than a board that uses larger holes.
Rev D
For more information www.analog.com
LTM8053/LTM8053-1
APPLICATIONS INFORMATION
improve the efficiency of the circuit, though it is likely to
be the largest component in the circuit.
VIN
CIN
GND
GND
Thermal Considerations
RUN
RT
RT TR/SS
SHARE SYNC
PC
BIAS AUX
FB
RFB
GND
COUT
VOUT
GND/THERMAL VIAS
8053 F03
Figure 3. Layout Showing Suggested External Components, GND
Plane and Thermal Vias
Hot-Plugging Safely
The small size, robustness and low impedance of ceramic
capacitors make them an attractive option for the input
bypass capacitor of LTM8053/LTM8053-1. However, these
capacitors can cause problems if the LTM8053/LTM8053-1
is plugged into a live supply (see Linear Technology Application Note 88 for a complete discussion). The low
loss ceramic capacitor combined with stray inductance
in series with the power source forms an underdamped
tank circuit, and the voltage at the VIN pin of the LTM8053/
LTM8053-1 can ring to more than twice the nominal input
voltage, possibly exceeding the LTM8053/LTM8053-1’s
rating and damaging the part. If the input supply is poorly
controlled or the LTM8053/LTM8053-1 is hot-plugged into
an energized supply, the input network should be designed
to prevent this overshoot. This can be accomplished by
installing a small resistor in series to VIN, but the most
popular method of controlling input voltage overshoot is
add an electrolytic bulk cap to the VIN net. This capacitor’s
relatively high equivalent series resistance damps the circuit
and eliminates the voltage overshoot. The extra capacitor
improves low frequency ripple filtering and can slightly
The LTM8053/LTM8053-1 output current may need to
be derated if it is required to operate in a high ambient
temperature. The amount of current derating is dependent upon the input voltage, output power and ambient
temperature. The derating curves given in the Typical
Performance Characteristics section can be used as a
guide. These curves were generated by the LTM8053/
LTM8053-1 mounted to a 58cm2 4-layer FR4 printed circuit
board. Boards of other sizes and layer count can exhibit
different thermal behavior, so it is incumbent upon the user
to verify proper operation over the intended system’s line,
load and environmental operating conditions.
For increased accuracy and fidelity to the actual application, many designers use FEA (finite element analysis) to
predict thermal performance. To that end, Page 2 of the
data sheet typically gives four thermal coefficients:
θJA – Thermal resistance from junction to ambient
θJCbottom – Thermal resistance from junction to the bottom
of the product case
θJCtop – Thermal resistance from junction to top of the
product case
θJB – Thermal resistance from junction to the printed
circuit board.
While the meaning of each of these coefficients may seem
to be intuitive, JEDEC has defined each to avoid confusion
and inconsistency. These definitions are given in JESD
51-12, and are quoted or paraphrased below:
θJA is the natural convection junction-to-ambient air
thermal resistance measured in a one cubic foot sealed
enclosure. This environment is sometimes referred to as
still air although natural convection causes the air to move.
This value is determined with the part mounted to a JESD
51-9 defined test board, which does not reflect an actual
application or viable operating condition.
Rev D
For more information www.analog.com
21
LTM8053/LTM8053-1
APPLICATIONS INFORMATION
θJCbottom is the junction-to-board thermal resistance with
all of the component power dissipation flowing through the
bottom of the package. In the typical µModule regulator,
the bulk of the heat flows out the bottom of the package,
but there is always heat flow out into the ambient environment. As a result, this thermal resistance value may
be useful for comparing packages but the test conditions
don’t generally match the user’s application.
θJCtop is determined with nearly all of the component power
dissipation flowing through the top of the package. As the
electrical connections of the typical µModule regulator are
on the bottom of the package, it is rare for an application
to operate such that most of the heat flows from the junction to the top of the part. As in the case of θJCbottom, this
value may be useful for comparing packages but the test
conditions don’t generally match the user’s application.
θJB is the junction-to-board thermal resistance where
almost all of the heat flows through the bottom of the
µModule regulator and into the board, and is often just
the sum of the θJCbottom and the thermal resistance of the
bottom of the part through the solder joints and through a
portion of the board. The board temperature is measured
a specified distance from the package, using a two sided,
two layer board. This board is described in JESD 51-9.
Given these definitions, it should now be apparent that none
of these thermal coefficients reflects an actual physical
operating condition of a µModule regulator. Thus, none
of them can be individually used to accurately predict the
thermal performance of the product. Likewise, it would
be inappropriate to attempt to use any one coefficient to
correlate to the junction temperature vs load graphs given
in the product’s data sheet. The only appropriate way to
use the coefficients is when running a detailed thermal
analysis, such as FEA, which considers all of the thermal
resistances simultaneously.
A graphical representation of these thermal resistances
is given in Figure 4. The blue resistances are contained
within the µModule regulator, and the green are outside.
The die temperature of the LTM8053/LTM8053-1 must be
lower than the maximum rating of 125°C, so care should
be taken in the layout of the circuit to ensure good heat
sinking of the LTM8053/LTM8053-1. The bulk of the heat
flow out of the LTM8053/LTM8053-1 is through the bottom of the package and the pads into the printed circuit
board. Consequently a poor printed circuit board design
can cause excessive heating, resulting in impaired performance or reliability. Please refer to the PCB Layout section
for printed circuit board design suggestions.
JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)
JUNCTION-TO-CASE (TOP)
RESISTANCE
JUNCTION
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION-TO-CASE
CASE (BOTTOM)-TO-BOARD
(BOTTOM) RESISTANCE
RESISTANCE
AMBIENT
BOARD-TO-AMBIENT
RESISTANCE
8053 F04
µMODULE REGULATOR
Figure 4. Graphical Representation of the Thermal Resistances Between the Device Junction and Ambient
22
Rev D
For more information www.analog.com
LTM8053/LTM8053-1
TYPICAL APPLICATIONS
15VOUT from 19.5VIN to 40VIN Step-Down Converter. BIAS Is Tied to AUX
LTM8053
VIN
VIN
19.5V TO 40V
BIAS
AUX
RUN
4.7µF
VOUT
15V
2A
VOUT
RT
25.5k
1.5MHz
FB
GND
SHARE
22µF
SYNC
16.9k
47pF
8053 TA02
PINS NOT USED IN THIS CIRCUIT: TR/SS, PG
1.2VOUT from 3.4VIN to 40VIN Step-Down Converter. BIAS Is Tied to an External 3.3V Source
LTM8053
VIN
VIN
3.4V TO 40V
RUN
4.7µF
VOUT
AUX
BIAS
EXT 3.3V
RT
47pf
GND
SYNC
100µF
×2
VOUT
1.2V
4A
1.05M
FB
78.7k
550kHz
PINS NOT USED IN THIS CIRCUIT: TR/SS, PG, SHARE
8053 TA03
2.5VOUT from 4VIN to 15VIN Step-Down Converter. BIAS Is Tied to VIN
LTM8053
VIN
VIN
4V TO 15V
RUN
BIAS
VOUT
4.7µF
100µF
RT
56.2k
750kHz
GND
SYNC
FB
VOUT
2.5V
3.5A
158k
PINS NOT USED IN THIS CIRCUIT: TR/SS, PG, SHARE, AUX
8053 TA04
Rev D
For more information www.analog.com
23
LTM8053/LTM8053-1
TYPICAL APPLICATIONS
–5VOUT from 5VIN to 35VIN Positive to Negative Converter. BIAS Is Tied to LTM8053 GND
Maximum Load Current vs VIN. BIAS Open
INPUT BULK CAP
5
VIN
MAXIMUM LOAD CURRENT (A)
+
VIN
5V TO 35V
LTM8053
RUN
4.7µF
40.2k
1MHz
OPTIONAL
SCHOTTKY
DIODE
VOUT
RT
FB
BIAS
GND
100µF
60.4k
SYNC
VOUT
–5V
PINS NOT USED IN THIS CIRCUIT: TR/SS, PG, SHARE, BIAS, AUX
4
3
2
1
0
8053 TA05a
0
10
20
30
INPUT VOLTAGE (V)
40
8053 TA05b
Use Two LTM8053s Powered from the Same Input Source to Get More Output Current
Do not operate LTM8053-1 devices in parallel.
VIN
VIN
7V TO 40V
LTM8053
BIAS
AUX
RUN
4.7µF
VOUT
5V
7A
VOUT
RT
40.2k
1MHz
100µF
FB
TR/SS
GND
SYNC SHARE
60.4k
OPTIONAL
SYNC
TR/SS
VIN
LTM8053
SHARE
BIAS
AUX
RUN
4.7µF
VOUT
RT
40.2k
1MHz
100µF
FB
GND
SYNC
60.4k
OPTIONAL
SYNC
PIN NOT USED IN THIS CIRCUIT: PG
24
8053 TA06
Rev D
For more information www.analog.com
LTM8053/LTM8053-1
PACKAGE DESCRIPTION
Table 3. LTM8053 Pinout (Sorted by Pin Number)
PIN
NAME
PIN
NAME
PIN
NAME
PIN
NAME
PIN
NAME
PIN
NAME
PIN
NAME
PIN
NAME
A1
GND
B1
FB
C1
GND
D1
GND
E1
GND
F1
GND
G1
VOUT
H1
VOUT
A2
BIAS
B2
AUX
C2
GND
D2
GND
E2
GND
F2
GND
G2
VOUT
H2
VOUT
A3
PG
B3
GND
C3
VIN
D3
GND
E3
GND
F3
GND
G3
VOUT
H3
VOUT
A4
SHARE
B4
SYNC
C4
VIN
D4
GND
E4
GND
F4
GND
G4
VOUT
H4
VOUT
A5
RT
B5
TR/SS
C5
VIN
D5
GND
E5
GND
F5
GND
G5
VOUT
H5
VOUT
A6
GND
B6
RUN
C6
VIN
D6
GND
E6
GND
F6
GND
G6
VOUT
H6
VOUT
PACKAGE PHOTOS
Rev D
For more information www.analog.com
25
For more information www.analog.com
aaa Z
0.50 ±0.025 Ø 48x
4
2.5
0.000
1.5
2.5
SUGGESTED PCB LAYOUT
TOP VIEW
0.5
PACKAGE TOP VIEW
E
0.5
PIN “A1”
CORNER
1.5
Y
3.5
2.5
1.5
0.5
0.000
0.5
1.5
2.5
3.5
X
D
aaa Z
// bbb Z
NOM
3.32
0.50
2.82
0.60
0.50
9.00
6.25
1.00
7.00
5.00
0.32
2.50
MAX
3.52
0.60
2.92
0.70
0.53
DIMENSIONS
BALL DIMENSION
PAD DIMENSION
BALL HT
NOTES
DETAIL B
PACKAGE SIDE VIEW
A2
A
SUBSTRATE THK
0.37
MOLD CAP HT
2.55
0.15
0.10
0.20
0.25
0.10
TOTAL NUMBER OF BALLS: 48
0.27
2.45
MIN
3.12
0.40
2.72
0.50
0.47
H1
SUBSTRATE
ddd M Z X Y
eee M Z
DETAIL A
Øb (48 PLACES)
SYMBOL
A
A1
A2
b
b1
D
E
e
F
G
H1
H2
aaa
bbb
ccc
ddd
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b1
DETAIL B
H2
MOLD
CAP
ccc Z
A1
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e
b
6
4
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2
PACKAGE BOTTOM VIEW
b
5
1
DETAIL A
PIN 1
3
SEE NOTES
H
G
F
E
D
C
B
A
6
SEE NOTES
DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
BALL DESIGNATION PER JEP95
6
TRAY PIN 1
BEVEL
!
BGA 48 0517 REV B
PACKAGE IN TRAY LOADING ORIENTATION
LTMXXXXXX
µModule
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
5. PRIMARY DATUM -Z- IS SEATING PLANE
4
3
2. ALL DIMENSIONS ARE IN MILLIMETERS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
COMPONENT
PIN “A1”
(Reference LTC DWG # 05-08-1999 Rev B)
Z
26
Z
BGA Package
48-Lead (9mm × 6.25mm × 3.32mm)
LTM8053/LTM8053-1
PACKAGE DESCRIPTION
Rev D
LTM8053/LTM8053-1
REVISION HISTORY
REV
DATE
DESCRIPTION
A
11/16
Added “Silent Switcher” to product description and features.
B
07/17
Changed recommended BIAS pin connection from Open to GND for the negative voltage output application.
C
12/17
Changed Peak Reflow Solder Body Temperature from 260°C to 250°C
D
06/18
Added LTM8053-1
Added EMI performance graph.
PAGE NUMBER
1
11
5, 7, 10, 11, 12,
15, 17, 19, 24
2
1-3, 12-22, 24
Rev D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
more by
information
www.analog.com
27
LTM8053/LTM8053-1
TYPICAL APPLICATION
0.97VOUT from 3.4VIN to 40VIN Step-Down Converter with Spread Spectrum. BIAS Is Tied to an External 3.3V Source
LTM8053
VIN
VIN
3.4V TO 40V
RUN
4.7µF
EXT 3.3V
VOUT
BIAS
SYNC
AUX
47pF
GND
PINS NOT USED IN THIS CIRCUIT: TR/SS, PG, SHARE
FB
RT
100µF
×2
VOUT
0.97V
4A
8053 TA07
100k
450kHz
DESIGN RESOURCES
SUBJECT
DESCRIPTION
µModule Design and Manufacturing Resources
Design:
• Selector Guides
• Demo Boards and Gerber Files
• Free Simulation Tools
µModule Regulator Products Search
1. Sort table of products by parameters and download the result as a spread sheet.
Manufacturing:
• Quick Start Guide
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability
2. Search using the Quick Power Search parametric table.
Digital Power System Management
Analog Devices’ family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
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FMEA Compliant Pinout
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BGA Package
LTM8021
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LTM8032
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3.6V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 10V, EN55022B Compliant
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Regulator
6V ≤ VIN ≤ 36V, 1.2V ≤ VOUT ≤ 24V, Constant Voltage Constant Current Operation
LTM4613
36V, 8A Low EMI Step-Down µModule
Regulator
5V ≤ VIN ≤ 36V, 3.3V ≤ VOUT ≤ 15V, EN55022B Compliant
LTM8027
60V, 4A Step-Down µModule Regulator
4.5V ≤ VIN ≤ 60V, 2.5V ≤ VOUT ≤ 24V
LTM8050
58V, 2A Step-Down µModule Regulator
3.6V ≤ VIN ≤ 58V, 0.8V ≤ VOUT ≤ 24V
28
Rev D
D17071-0-6/18(0)
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