LTM8065
40VIN, 2.5A Silent Switcher
µModule Regulator
FEATURES
DESCRIPTION
Complete Step-Down Switch Mode Power Supply
nn Low Noise Silent Switcher® Architecture
nn Wide Input Voltage Range: 3.4V to 40V
nn Wide Output Voltage Range: 0.97V to 18V
nn 2.5A Continuous Output Current, 3.5A Peak
nn Selectable Switching Frequency: 200kHz to 3MHz
nn External Synchronization
nn Programmable Soft-Start
nn Tiny, Low Profile 6.25mm × 6.25mm × 2.32mm
RoHS Compliant BGA Package
The LTM®8065 is a 40VIN, 3.5A peak, 2.5A continuous
step-down µModule® (power module) regulator. Included in
the package are the switching controller, power switches,
inductor and all support components. Operating over an
input voltage range of 3.4V to 40V, the LTM8065 supports
an output voltage range of 0.97V to 18V and a switching
frequency range of 200kHz to 3MHz, each set by a single
resistor. Only the input and output filter capacitors are
needed to finish the design.
nn
APPLICATIONS
Automotive Battery Regulation
Power for Portable Products
nn Distributed Supply Regulation
nn Industrial Supplies
nn Wall Transformer Regulation
nn
nn
The low profile package enables utilization of unused
space on the bottom of PC boards for high density point of
load regulation. The LTM8065 is packaged in a thermally
enhanced, compact over-molded ball grid array (BGA) package suitable for automated assembly by standard surface
mount equipment. The LTM8065 is RoHS compliant.
All registered trademarks and trademarks are the property of their respective owners.
TYPICAL APPLICATION
Efficiency vs Load Current
95
VIN
VIN
7V TO 40V
RUN
LTM8065
2.2µF
BIAS
AUX
VOUT
RT
41.2k
1MHz
GND
SYNC
FB
60.4k
22µF
VOUT
5V
2.5A
3.5A PEAK
EFFICIENCY (%)
5VOUT from 7VIN to 40VIN Step-Down Converter
VIN = 12V
90
85
8065 TA01a
PINS NOT USED IN THIS CIRCUIT: TR/SS, PG
80
0
1
2
LOAD CURRENT (A)
3
8065 TA01b
Rev.B
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1
LTM8065
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
VIN, RUN, PG Voltage ............................................... 42V
AUX, VOUT, BIAS Voltage ......................................... 19V
FB, TR/SS Voltage ..................................................... 4V
SYNC Voltage ............................................................. 6V
Maximum Internal Temperature ........................... 125°C
Storage Temperature ............................ –55°C to 125°C
Peak Reflow Solder Body Temperature ................ 260°C
TOP VIEW
GND
BIAS
PG
GND
RT
GND
A
FB
AUX
SYNC TR/SS
RUN
B
BANK 2
VIN
C
D
BANK 1
GND
E
F
BANK 3 VOUT
1
2
3
4
5
6
BGA PACKAGE
36-LEAD (6.25mm × 6.25mm × 2.32mm) BGA PACKAGE
TJMAX = 125°C, θJA = 21°C/W, θJCbottom = 5.9°C/W
θJCtop = 36.5°C/W, θJB = 6.3°C/W, WEIGHT = 0.5g
θ VALUES DETERMINED PER JEDEC51-9, 51-12
ORDER INFORMATION
PART MARKING*
PART NUMBER
LTM8065EY#PBF
LTM8065IY#PBF
TERMINAL FINISH
DEVICE
FINISH CODE
PACKAGE
TYPE
MSL
RATING
SAC305 (RoHS)
LTM8065
e1
BGA
3
• Contact the factory for parts specified with wider operating temperature
ranges. *Pad or ball finish code is per IPC/JEDEC J-STD-609.
TEMPERATURE RANGE
–40°C to 125°C
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures
• LGA and BGA Package and Tray Drawings
Rev.B
2
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LTM8065
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
temperature range, otherwise specifications are at TJ = 25°C. VIN = 12V, RUN = 2V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
Minimum Input Voltage
VIN Rising
Output DC Voltage
RFB Open
RFB = 14.3kΩ, VIN = 40V
MAX
Peak Output DC Current
VOUT = 3.3V, fSW = 1MHz
Quiescent Current into VIN
RUN = 0V
BIAS = 0V, No Load, SYNC = 0V, Not Switching
3
8
µA
µA
Quiescent Current into BIAS
BIAS = 5V, RUN = 0V
BIAS = 5V, No Load, SYNC = 0V, Not Switching
BIAS = 5V, VOUT = 3.3V, IOUT = 2.5A, fSW = 1MHz
1
5
12
µA
µA
mA
3.4
l
0.97
18
UNITS
V
V
V
3.5
A
Line Regulation
5.5V < VIN < 36V, IOUT = 1A
0.5
%
Load Regulation
0.1A < IOUT < 2.5A
0.5
%
Output Voltage Ripple
IOUT = 2.5A
10
mV
Switching Frequency
RT = 232kΩ
RT = 41.2kΩ
RT = 10.7kΩ
200
1
3
kHz
MHz
MHz
Voltage at FB
Minimum BIAS Voltage
l
950
970
(Note 5)
RUN Threshold Voltage
0.9
RUN Current
TR/SS Current
TR/SS = 0V
TR/SS Pull Down
TR/SS = 0.1V
980
mV
3.2
V
1.06
V
1
µA
2
µA
200
Ω
PG Threshold Voltage at FB (Upper)
FB Falling (Note 6)
1.05
V
PG Threshold Voltage at FB (Lower)
FB Rising (Note 6)
0.89
V
PG Leakage Current
PG = 42V
1
PG Sink Current
PG = 0.1V
SYNC Threshold Voltage
Synchronization
0.4
1.5
SYNC Voltage
To Enable Spread Spectrum
2.9
4.2
V
SYNC Current
SYNC = 0V
35
µA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Unless otherwise noted, the absolute minimum voltage is zero.
Note 3: The LTM8065E is guaranteed to meet performance specifications
from 0°C to 125°C internal. Specifications over the full –40°C to
125°C internal operating temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTM8065I is guaranteed to meet specifications over the full –40°C to
125°C internal operating temperature range. Note that the maximum
internal temperature is determined by specific operating conditions in
conjunction with board layout, the rated package thermal resistance and
other environmental factors.
150
µA
µA
V
Note 4: The LTM8065 contains overtemperature protection that is
intended to protect the device during momentary overload conditions. The
internal temperature exceeds the maximum operating junction temperature
when the overtemperature protection is active. Continuous operation
above the specified maximum operating junction temperature may impair
device reliability.
Note 5: Below this specified voltage, internal circuitry will draw power
from VIN.
Note 6: PG transitions from low to high.
Rev.B
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3
LTM8065
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency, VOUT = 1.2V,
BIAS = 5V
90
75
75
80
65
45
1
2
LOAD CURRENT (A)
65
45
3
12VIN
24VIN
36VIN
0
8065 G01
1
2
LOAD CURRENT (A)
50
3
80
80
80
EFFICIENCY (%)
90
EFFICIENCY (%)
90
50
70
60
12VIN
24VIN
36VIN
0
1
2
LOAD CURRENT (A)
50
3
0
1
2
LOAD CURRENT (A)
50
3
85
85
90
55
EFFICIENCY (%)
100
EFFICIENCY (%)
95
75
65
0
1
2
LOAD CURRENT (A)
3
55
3
1
2
LOAD CURRENT (A)
8065 G07
80
70
12VIN
24VIN
36VIN
0
1
2
LOAD CURRENT (A)
Efficiency, VOUT = 8V,
BIAS = 5V
95
12VIN
24VIN
36VIN
0
8065 G06
Efficiency, VOUT = 5V,
BIAS = 5V
65
12VIN
24VIN
36VIN
8065 G05
Efficiency, VOUT = 3.3V,
BIAS = 5V
3
70
60
12VIN
24VIN
36VIN
8065 G04
75
1
2
LOAD CURRENT (A)
Efficiency, VOUT = 2.5V,
BIAS = 5V
90
60
0
8065 G03
Efficiency, VOUT = 2V,
BIAS = 5V
70
12VIN
24VIN
36VIN
8065 G02
Efficiency, VOUT = 1.8V,
BIAS = 5V
EFFICIENCY (%)
70
60
55
12VIN
24VIN
36VIN
0
EFFICIENCY (%)
85
55
EFFICIENCY (%)
Efficiency, VOUT = 1.5V,
BIAS = 5V
85
EFFICIENCY (%)
EFFICIENCY (%)
Efficiency, VOUT = 0.97V,
BIAS = 5V
TA = 25°C, unless otherwise noted.
3
8065 G08
60
12VIN
24VIN
36VIN
0
1
2
LOAD CURRENT (A)
3
8065 G09
Rev.B
4
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LTM8065
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency, VOUT = 12V,
BIAS = 5V
TA = 25°C, unless otherwise noted.
Efficiency, VOUT = 15V,
BIAS = 5V
Efficiency, VOUT = 18V,
BIAS = 5V
90
90
90
80
70
60
EFFICIENCY (%)
100
EFFICIENCY (%)
100
EFFICIENCY (%)
100
80
70
24VIN
36VIN
0
1
2
LOAD CURRENT (A)
60
3
70
24VIN
36VIN
0
1
2
LOAD CURRENT (A)
EFFICIENCY (%)
EFFICIENCY (%)
80
90
90
80
80
70
1
2
LOAD CURRENT (A)
50
3
12VIN
24VIN
0
8065 G13
50
3
0
0.5
1
1.5
LOAD CURRENT (A)
2
3
80
EFFICIENCY (%)
EFFICIENCY (%)
12VIN
24VIN
1
2
LOAD CURRENT (A)
85
70
60
65
0
Efficiency, VOUT = –18V, BIAS tied
to LTM8065 GND
80
70
12VIN
24VIN
8065 G15
90
80
EFFICIENCY (%)
1
2
LOAD CURRENT (A)
Efficiency, VOUT = –15V, BIAS tied
to LTM8065 GND
85
60
70
8065 G14
Efficiency, VOUT = –12V, BIAS tied
to LTM8065 GND
75
3
60
60
12VIN
24VIN
35VIN
0
1
2
LOAD CURRENT (A)
Efficiency, VOUT = –8V,
BIAS tied to LTM8065 GND
EFFICIENCY (%)
85
70
0
8065 G12
Efficiency, VOUT = –5V,
BIAS tied to LTM8065 GND
75
24VIN
36VIN
8002 G11
Efficiency, VOUT = –3.3V,
BIAS tied to LTM8065 GND
60
60
3
8065 G10
65
80
50
75
70
65
12VIN
24VIN
0
0.5
1
LOAD CURRENT (A)
8065 G16
1.5
8065 G17
60
12VIN
0
0.25
0.50
0.75
LOAD CURRENT (A)
1
1.25
8065 G18
Rev.B
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5
LTM8065
TYPICAL PERFORMANCE CHARACTERISTICS
Input vs Load Current
VOUT = 0.97V
Input vs Load Current
VOUT = 1.2V
0.6
0.4
0.2
0
0
0.5
1
1.5
2
2.5
LOAD CURRENT (A)
3
0.6
12VIN
24VIN
36VIN
0.4
0.2
0
3.5
Input vs Load Current
VOUT = 1.5V
INPUT CURRENT (A)
12VIN
24VIN
36VIN
INPUT CURRENT (A)
INPUT CURRENT (A)
0.6
TA = 25°C, unless otherwise noted.
0
0.5
1
1.5
2
2.5
LOAD CURRENT (A)
3
8065 G19
0.2
0
0
0.5
1
1.5
2
2.5
LOAD CURRENT (A)
3
0.3
0
0.5
2.0
1
1.5
2
2.5
LOAD CURRENT (A)
3
0.5
1
1.5
2
2.5
LOAD CURRENT (A)
0
3.5
3
3.5
Input vs Load Current
VOUT = 2.5V
12VIN
24VIN
36VIN
0
0.5
1
1.5
2
2.5
LOAD CURRENT (A)
3
Input vs Load Current
VOUT = 8V
3
1.0
0.5
0
0
0.5
1
1.5
2
2.5
LOAD CURRENT (A)
3.5
8065 G24
12VIN
24VIN
36VIN
1.5
3.5
0.4
INPUT CURRENT (A)
12VIN
24VIN
36VIN
0
3
0.8
Input vs Load Current
VOUT = 5V
INPUT CURRENT (A)
INPUT CURRENT (A)
0
1
1.5
2
2.5
LOAD CURRENT (A)
8065 G23
Input vs Load Current
VOUT = 3.3V
0.5
0.5
8065 G21
1.2
0.6
0
3.5
1.0
0
12VIN
24VIN
36VIN
8065 G22
1.5
0
INPUT CURRENT (A)
INPUT CURRENT (A)
INPUT CURRENT (A)
0.9
0.4
0.2
3.5
Input vs Load Current
VOUT = 2V
12VIN
24VIN
36VIN
0.6
0.4
8065 G20
Input vs Load Current
VOUT = 1.8V
0.8
12VIN
24VIN
36VIN
3
8065 G25
3.5
8065 G26
12VIN
24VIN
36VIN
2
1
0
0
0.5
1
1.5
2
2.5
LOAD CURRENT (A)
3
3.5
8065 G27
Rev.B
6
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LTM8065
TYPICAL PERFORMANCE CHARACTERISTICS
1.5
1.0
0.5
0
0
0.5
1
1.5
2
2.5
LOAD CURRENT (A)
3
3
24VIN
36VIN
2
1
0
3.5
Input vs Load Current
VOUT = 15V
INPUT CURRENT (A)
3
24VIN
36VIN
INPUT CURRENT (A)
INPUT CURRENT (A)
2.0
Input vs Load Current
VOUT = 12V
TA = 25°C, unless otherwise noted.
0
0.5
1
1.5
2
2.5
LOAD CURRENT (A)
3
Input vs Load Current
VOUT = –3.3V
0
1
2
3
LOAD CURRENT (A)
1.5
1.0
0.5
0
4
2.0
12VIN
24VIN
0
1
2
3
LOAD CURRENT (A)
2.5
0
1.5
1.0
0.5
0.5
0
0.5
1
1.5
LOAD CURRENT (A)
2
8065 G34
0.5
0
1
2
LOAD CURRENT (A)
0
3
Input vs Load Current
VOUT = –18V
12VIN
2.0
INPUT CURRENT (A)
1.0
1.0
2.5
12VIN
24VIN
2.0
INPUT CURRENT (A)
INPUT CURRENT (A)
2.0
3.5
8065 G33
Input vs Load Current
VOUT = –15V
12VIN
24VIN
3
12VIN
24VIN
8065 G32
Input vs Load Current
VOUT = –12V
1.5
1
1.5
2
2.5
LOAD CURRENT (A)
1.5
0
4
8065 G31
2.5
0.5
Input vs Load Current
VOUT = –8V
INPUT CURRENT (A)
INPUT CURRENT (A)
INPUT CURRENT (A)
2.0
12VIN
24VIN
36VIN
0.5
0
8065 G30
Input vs Load Current
VOUT = –5V
1.0
0
1
8065 G29
8065 G28
1.5
24VIN
36VIN
2
0
3.5
Input vs Load Current
VOUT = 18V
1.5
1.0
0.5
0
0.5
1
LOAD CURRENT (A)
1.5
8065 G35
0
0
0.5
1
LOAD CURRENT (A)
1.5
8065 G36
Rev.B
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7
LTM8065
TYPICAL PERFORMANCE CHARACTERISTICS
Maximum Load Current vs VIN
BIAS tied to LTM8065 GND
Maximum Load Current vs VIN
BIAS tied to LTM8065 GND
3
2
–3.3VOUT
–5VOUT
–8VOUT
0
10
20
30
INPUT VOLTAGE (V)
1.5
1.0
0.5
0
40
–12VOUT
–15VOUT
–18VOUT
0
10
20
INPUT VOLTAGE (V)
8065 G37
4
1
12VIN
24VIN
36VIN
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
3
2
1
0
125
12VIN
24VIN
36VIN
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
MAXIMUM LOAD CURRENT (A)
MAXIMUM LOAD CURRENT (A)
0
4
0 LFM
1
12VIN
24VIN
36VIN
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
4
125
0 LFM
2
1
0
125
12VIN
24VIN
36VIN
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
2
1
0
12VIN
24VIN
36VIN
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
8065 G43
125
8065 G44
125
8065 G42
Derating, VOUT = 3.3V, BIAS = 5V,
DC2251A Demo Board
4
0 LFM
3
125
3
Derating, VOUT = 2.5V, BIAS = 5V,
DC2251A Demo Board
2
25
50
75
100
AMBIENT TEMPERATURE (°C)
8065 G41
Derating, VOUT = 2V, BIAS = 5V,
DC2251A Demo Board
3
0
Derating, VOUT = 1.8V, BIAS = 5V,
DC2251A Demo Board
0 LFM
8065 G40
4
12VIN
24VIN
36VIN
8065 G39
MAXIMUM LOAD CURRENT (A)
MAXIMUM LOAD CURRENT (A)
MAXIMUM LOAD CURRENT (A)
2
1
Derating, VOUT = 1.5V, BIAS = 5V,
DC2251A Demo Board
0 LFM
3
2
8065 G38
Derating, VOUT = 1.2V, BIAS = 5V,
DC2251A Demo Board
4
0 LFM
3
0
30
MAXIMUM LOAD CURRENT (A)
1
4
MAXIMUM LOAD CURRENT (A)
4
0
Derating, VOUT = 0.97V BIAS = 5V,
DC2251A Demo Board
2.0
MAXIMUM LOAD CURRENT (A)
MAXIMUM LOAD CURRENT (A)
5
0
TA = 25°C, unless otherwise noted.
0 LFM
3
2
1
0
12VIN
24VIN
36VIN
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
125
8065 G45
Rev.B
8
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LTM8065
TYPICAL PERFORMANCE CHARACTERISTICS
3
2
12VIN
24VIN
36VIN
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
3
2
1
0
125
12VIN
24VIN
36VIN
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
12VIN
24VIN
36VIN
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
2
1
0
125
0
24VIN
36VIN
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
MAXIMUM LOAD CURRENT (A)
3
MAXIMUM LOAD CURRENT (A)
24VIN
36VIN
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
125
25
50
75
100
AMBIENT TEMPERATURE (°C)
125
3
1
0
125
0 LFM
2
24VIN
36VIN
0
1
0
12VIN
24VIN
36VIN
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
8065 G52
125
8065 G53
125
Derating, VOUT = –5V, BIAS tied
to LTM8065 GND, DC2251A Demo
Board
3
0 LFM
2
25
50
75
100
AMBIENT TEMPERATURE (°C)
8065 G51
Derating, VOUT = –3.3V, BIAS tied
to LTM8065 GND, DC2251A Demo
Board
0 LFM
1
0
8065 G50
Derating, VOUT = 18V, BIAS = 5V,
DC2251A Demo Board
2
12VIN
24VIN
36VIN
Derating, VOUT = 15V, BIAS = 5V,
DC2251A Demo Board
0 LFM
8065 G49
3
1
8065 G48
MAXIMUM LOAD CURRENT (A)
MAXIMUM LOAD CURRENT (A)
MAXIMUM LOAD CURRENT (A)
0
3
0 LFM
1
2
Derating, VOUT = 12V, BIAS = 5V,
DC2251A Demo Board
2
0 LFM
fSW = 2MHz
8065 G47
Derating, VOUT = 8V, BIAS = 5V,
DC2251A Demo Board
3
Derating, VOUT = 5V, BIAS = 5V,
DC2251A Demo Board
3
0
125
8065 G46
4
4
0 LFM
MAXIMUM LOAD CURRENT (A)
1
0
4
0 LFM
f = 2MHz
MAXIMUM LOAD CURRENT (A)
MAXIMUM LOAD CURRENT (A)
4
Derating, VOUT = 5V, BIAS = 5V,
DC2251A Demo Board
MAXIMUM LOAD CURRENT (A)
Derating, VOUT = 3.3V, BIAS = 5V,
DC2251A Demo Board
TA = 25°C, unless otherwise noted.
0 LFM
2
1
0
12VIN
24VIN
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
125
8065 G54
Rev.B
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9
LTM8065
TYPICAL PERFORMANCE CHARACTERISTICS
Derating, VOUT = –8V, BIAS tied
to LTM8065 GND, DC2251A Demo
Board
1.00
1.0
0.5
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
0.50
0.25
0
125
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
0.50
0.25
0
125
12VIN
24VIN
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
CISPR22 Class B Radiated DC2251A
Demo Board, VOUT = 5V No Filter
(FB1, L1 short, C6, C7 open)
Dropout Voltage vs Load Current,
VOUT = 5V, BIAS = 5V
800
0 LFM
125
8065 G57
8065 G56
Derating, VOUT = –18V, BIAS tied
to LTM8065 GND, DC2251A Demo
Board
50
fSW = 1MHz, VIN = 14V, I OUT = 2.5A
40
0.50
0.25
600
AMPLITUDE (dBµV/m)
0.75
DROPOUT VOLTAGE (mV)
MAXIMUM LOAD CURRENT (A)
0 LFM
0.75
12VIN
24VIN
8065 G55
1.00
1.00
0 LFM
0.75
12VIN
24VIN
Derating, VOUT = –15V, BIAS tied
to LTM8065 GND, DC2251A Demo
Board
MAXIMUM LOAD CURRENT (A)
0 LFM
1.5
0
Derating, VOUT = –12V, BIAS tied
to LTM8065 GND, DC2251A Demo
Board
MAXIMUM LOAD CURRENT (A)
MAXIMUM LOAD CURRENT (A)
2.0
TA = 25°C, unless otherwise noted.
400
200
30
20
10
CLASS B LIMIT
HORIZONTAL
VERTICAL
0
0
12VIN
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
125
8065 G58
0
0
1
2
3
LOAD CURRENT (A)
4
8065 G59
–10
0
200
400
600
FREQUENCY (MHz)
800
1000
8065 G60
Rev.B
10
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LTM8065
PIN FUNCTIONS
GND (Bank 1, A1, A4, A6): Tie these GND pins to a local
ground plane below the LTM8065 and the circuit components. In most applications, the bulk of the heat flow out of
the LTM8065 is through these pads, so the printed circuit
design has a large impact on the thermal performance of
the part. See the PCB Layout and Thermal Considerations
sections for more details.
VIN (Bank 2): VIN supplies current to the LTM8065’s internal regulator and to the internal power switches. These
pins must be locally bypassed with an external, low ESR
capacitor; see Table 1 for recommended values.
VOUT (Bank 3): Power Output Pins. Apply the output filter
capacitor and the output load between these pins and
GND pins.
BIAS (Pin A2): The BIAS pin connects to the internal power
bus. Connect to a power source greater than 3.2V. If VOUT
is greater than 3.2V, connect this pin to AUX. If the output
voltage is less, connect this to a voltage source greater
than 3.2V. Decouple this pin with at least 1µF if the voltage
source for BIAS is remote. If unused, tie this pin to GND.
PG (Pin A3): The PG pin is the open-collector output of
an internal comparator. PG remains low until the FB pin
voltage is within about 10% of the final regulation voltage. The PG signal is valid when VIN is above 3.4V. If VIN
is above 3.4V and RUN is low, PG will drive low. If this
function is not used, leave this pin floating.
RT (Pin A5): The RT pin is used to program the switching
frequency of the LTM8065 by connecting a resistor from
this pin to ground. The Applications Information section of
the data sheet includes a table to determine the resistance
value based on the desired switching frequency. Minimize
capacitance at this pin. Do not drive this pin.
FB (Pin B1): The LTM8065 regulates its FB pin to 0.97V.
Connect the adjust resistor from this pin to ground.
The value of RFB is given by the equation RFB = 241.53/
(VOUT – 0.97), where RFB is in kΩ.
AUX (Pin B2): Low Current Voltage Source for BIAS. In
many designs, the BIAS pin is simply connected to VOUT.
The AUX pin is internally connected to VOUT and is placed
adjacent to the BIAS pin to ease printed circuit board routing.
Also, some applications require a feedforward capacitor;
it can be connected from AUX to FB for convenient PCB
routing. Although this pin is internally connected to VOUT,
it is not intended to deliver a high current, so do not draw
current from this pin to the load.
SYNC (Pin B4): External clock synchronization input
and operational mode. This pin programs four different
operating modes:
1. Burst Mode® Operation. Tie this pin to ground for Burst
Mode operation at low output loads—this will result in
ultralow quiescent current.
2. Pulse-skipping mode. Float this pin for pulse-skipping
mode. This mode offers full frequency operation down
to low output loads before pulse skipping occurs.
3. Spread spectrum mode. Tie this pin high (between
2.9V and 4.2V) for pulse-skipping mode with spread
spectrum modulation.
4. Synchronization mode. Drive this pin with a clock source
to synchronize to an external frequency. During synchronization the part will operate in pulse-skipping mode.
TR/SS (Pin B5): The TR/SS pin is used to provide a softstart or tracking function. The internal 2μA pull-up current
in combination with an external capacitor tied to this pin
creates a voltage ramp. If TR/SS is less than 0.97V, the
FB voltage tracks to this value. The soft-start ramp time
is approximated by the equation t = 0.485 • C where C is
in μF. For tracking, tie a resistor divider to this pin from the
tracked output. This pin is pulled to ground with an internal
MOSFET during shutdown and fault conditions; use a series
resistor if driving from a low impedance output. This pin
may be left floating if the tracking function is not needed.
RUN (Pin B6): Pull the RUN pin below 0.9V to shut down
the LTM8065. Tie to 1.06V or more for normal operation. If
the shutdown feature is not used, tie this pin to the VIN pin.
Rev.B
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11
LTM8065
BLOCK DIAGRAM
LTM8065 Block Diagram
BIAS
VIN
AUX
0.2µF
1.5µH
CURRENT
MODE
CONTROLLER
VOUT
249k
10pF
0.1µF
GND
FB
RUN
TR/SS
SYNC
RT
PG
8065 BD01
Rev.B
12
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LTM8065
OPERATION
The LTM8065 is a stand-alone non-isolated step-down
switching DC/DC power supply that can deliver up to
3.5A. The continuous current is determined by the internal
operating temperature. It provides a precisely regulated
output voltage programmable via one external resistor
from 0.97V to 18V. The input voltage range is 3.4V to 40V.
Given that the LTM8065 is a step-down converter, make
sure that the input voltage is high enough to support the
desired output voltage and load current. A simplified Block
Diagram is given on the previous page.
The LTM8065 contains a current mode controller, power
switching elements, power inductor and a modest amount
of input and output capacitance. The LTM8065 is a fixed
frequency PWM regulator. The switching frequency is set
by simply connecting the appropriate resistor value from
the RT pin to GND.
An internal regulator provides power to the control circuitry. This bias regulator normally draws power from the
VIN pin, but if the BIAS pin is connected to an external
voltage higher than 3.2V, bias power is drawn from the
external source (typically the regulated output voltage).
This improves efficiency. If BIAS is unused, tie this pin
to GND. The RUN pin is used to place the LTM8065 in
shutdown, disconnecting the output and reducing the
input current to a few µA.
To enhance efficiency, the LTM8065 automatically switches
to Burst Mode operation in light or no load situations.
Between bursts, all circuitry associated with controlling
the output switch is shut down reducing the input supply
current to just a few µA.
The oscillator reduces the LTM8065’s operating frequency
when the voltage at the FB pin is low. This frequency foldback helps to control the output current during start-up
and overload.
The TR/SS node acts as an auxiliary input to the error
amplifier. The voltage at FB servos to the TR/SS voltage
until TR/SS goes above 0.97V. Soft-start is implemented
by generating a voltage ramp at the TR/SS pin using an
external capacitor which is charged by an internal constant
current. Alternatively, driving the TR/SS pin with a signal
source or resistive network provides a tracking function.
Do not drive the TR/SS pin with a low impedance voltage source. See the Applications Information section for
more details.
The LTM8065 contains a power good comparator which
trips when the FB pin is at about 90% to 110% of its
regulated value. The PG output is an open-drain transistor
that is off when the output is in regulation, allowing an
external resistor to pull the PG pin high. The PG signal
is valid when VIN is above 3.4V. If VIN is above 3.4V and
RUN is low, PG will drive low.
The LTM8065 is equipped with a thermal shutdown that
inhibits power switching at high junction temperatures.
The activation threshold of this function is above the maximum temperature rating to avoid interfering with normal
operation, so prolonged or repetitive operation under a
condition in which the thermal shutdown activates may
damage or impair the reliability of the device.
Rev.B
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13
LTM8065
APPLICATIONS INFORMATION
For most applications, the design process is straightforward, summarized as follows:
1. Look at Table 1 and find the row that has the desired
input range and output voltage.
2. Apply the recommended, CIN, COUT, RFB and RT values.
3. Apply the CFF (from AUX to FB) as required.
4. Connect BIAS as indicated.
While these component combinations have been tested
for proper operation, it is incumbent upon the user to
verify proper operation over the intended system’s line,
load and environmental conditions. Bear in mind that the
maximum output current is limited by junction temperature, the relationship between the input and output voltage
magnitude and polarity and other factors. Please refer to
the graphs in the Typical Performance Characteristics
section for guidance.
The maximum frequency (and attendant RT value) at
which the LTM8065 should be allowed to switch is given
in Table 1 in the Maximum fSW column, while the recommended frequency (and RT value) for optimal efficiency
over the given input condition is given in the fSW column.
There are additional conditions that must be satisfied if
the synchronization function is used. Please refer to the
Synchronization section for details.
Capacitor Selection Considerations
The CIN and COUT capacitor values in Table 1 are the
minimum recommended values for the associated operating conditions. Applying capacitor values below those
indicated in Table 1 is not recommended and may result
in undesirable operation. Using larger values is generally
acceptable, and can yield improved dynamic response, if
it is necessary. Again, it is incumbent upon the user to
Table 1. Recommended Component Values and Configuration (TA = 25°C)
VIN
VOUT
RFB
CIN2
COUT
CFF
BIAS
fSW
RT
MAX fSW
MIN RT
3.4V to 40V
0.97V
open
2.2µF 50V 0805
100µF 4V 0805
47pF
3.2-19V
450kHz
100k
660kHz
63.4k
3.4V to 40V
1.2V
1.05M
2.2µF 50V 0805
100µF 4V 0805
47pF
3.2-19V
550kHz
78.7k
900kHz
45.3k
3.4V to 40V
1.5V
464k
2.2µF 50V 0805
100µF 4V 0805
27pF
3.2-19V
650kHz
64.9k
1MHz
41.2k
3.4V to 40V
1.8V
294k
2.2µF 50V 0805
100µF 4V 0805
10pF
3.2-19V
700kHz
60.4k
1.3MHz
28.7k
3.4V to 40V
2V
237k
2.2µF 50V 0805
100µF 4V 0805
3.2-19V
850kHz
51.5k
1.4MHz
28.0k
3.5V to 40V1
2.5V
158k
2.2µF 50V 0805
47µF 4V 0805
3.2-19V
900kHz
45.3k
1.7MHz
21.5k
4.5V to 40V1
3.3V
102k
2.2µF 50V 0805
47µF 4V 0805
3.2-19V
900kHz
45.3k
2.2MHz
15.8k
6.5V to 40V1
5V
60.4k
2.2µF 50V 0805
22µF 6.3V 0805
3.2-19V
1MHz
41.2k
3MHz
10.7k
10V to 40V1
8V
34k
2.2µF 50V 0805
22µF 10V 1206
3.2-19V
1.3MHz
28.7k
3MHz
10.7k
14.5V to 40V1
12V
21.5k
4.7µF 50V 0805
10µF 16V 0805
3.2-19V
1.3MHz
28.7k
3MHz
10.7k
19.5V to 40V1
15V
16.9k
4.7µF 50V 0805
10µF 16V 0805
3.2-19V
1.5MHz
25.5k
3MHz
10.7k
23V to 40V1
18V
14k
4.7µF 50V 0805
10µF 25V 1206
3.2-19V
1.8MHz
20.5k
3MHz
10.7k
3.4V to 36V1
–3.3V
102k
2.2µF 50V 0805
47µF 4V 0805
LTM8065 GND
900kHz
45.3k
2.2MHz
15.8k
3.4V to 35V1
–5V
59k
2.2µF 50V 0805
22µF 6.3V 0805
LTM8065 GND
1MHz
41.2k
3MHz
10.7k
3.4V to 32V1
–8V
34k
2.2µF 50V 0805
22µF 10V 1206
LTM8065 GND
1.3MHz
28.7k
3MHz
10.7k
3.4V to 28V1
–12V
21.5k
4.7µF 50V 0805
10µF 16V 0805
LTM8065 GND
1.3MHz
28.7k
3MHz
10.7k
3.4V to 25V1
–15V
16.9k
4.7µF 50V 0805
10µF 16V 0805
LTM8065 GND
1.5MHz
25.5k
3MHz
10.7k
3.4V to 22V1
–18V
14k
4.7µF 50V 0805
10µF 25V 1206
LTM8065 GND
1.8MHz
20.5k
3MHz
10.7k
1. The LTM8065 may be capable of lower input voltages but may skip off cycles.
2. An input bulk capacitor is required
Rev.B
14
For more information www.analog.com
LTM8065
APPLICATIONS INFORMATION
verify proper operation over the intended system’s line,
load and environmental conditions.
Table 2. SW Frequency vs RT Value
fSW (MHz)
RT (kΩ)
0.2
232
0.3
150
0.4
110
0.5
88.7
0.6
73.2
0.7
60.4
0.8
52.3
1.0
41.2
1.2
33.2
1.4
28.0
1.6
23.7
1.8
20.5
2.0
18.2
2.2
15.8
3.0
10.7
Ceramic capacitors are small, robust and have very low
ESR. However, not all ceramic capacitors are suitable.
X5R and X7R types are stable over temperature and applied voltage and give dependable service. Other types,
including Y5V and Z5U have very large temperature and
voltage coefficients of capacitance. In an application circuit they may have only a small fraction of their nominal
capacitance resulting in much higher output voltage ripple
than expected.
Ceramic capacitors are also piezoelectric. In Burst Mode
operation, the LTM8065’s switching frequency depends
on the load current, and can excite a ceramic capacitor
at audio frequencies, generating audible noise. Since the
LTM8065 operates at a lower current limit during Burst
Mode operation, the noise is typically very quiet to a
casual ear.
If this audible noise is unacceptable, use a high performance electrolytic capacitor at the output. It may also be
a parallel combination of a ceramic capacitor and a low
cost electrolytic capacitor.
A final precaution regarding ceramic capacitors concerns
the maximum input voltage rating of the LTM8065. A
ceramic input capacitor combined with trace or cable
inductance forms a high-Q (underdamped) tank circuit.
If the LTM8065 circuit is plugged into a live supply, the
input voltage can ring to twice its nominal value, possibly exceeding the device’s rating. This situation is easily
avoided; see the Hot-Plugging Safely section.
Frequency Selection
The LTM8065 uses a constant frequency PWM architecture that can be programmed to switch from 200kHz to
3MHz by using a resistor tied from the RT pin to ground.
Table 2 provides a list of RT resistor values and their
resultant frequencies.
Operating Frequency Trade-Offs
It is recommended that the user apply the optimal RT
value given in Table 1 for the input and output operating
condition. System level or other considerations, however,
may necessitate another operating frequency. While the
LTM8065 is flexible enough to accommodate a wide
range of operating frequencies, a haphazardly chosen
one may result in undesirable operation under certain
operating or fault conditions. A frequency that is too
high can reduce efficiency, generate excessive heat or
even damage the LTM8065 if the output is overloaded
or short-circuited. A frequency that is too low can result
in a final design that has too much output ripple or too
large of an output capacitor.
BIAS Pin Considerations
The BIAS pin is used to provide drive power for the internal
power switching stage and operate other internal circuitry.
For proper operation, it must be powered by at least 3.2V.
If the output voltage is programmed to 3.2V or higher, BIAS
may be simply tied to VOUT. If VOUT is less than 3.2V, BIAS
can be tied to VIN or some other voltage source. If the BIAS
pin voltage is too high, the efficiency of the LTM8065 may
suffer. The optimum BIAS voltage is dependent upon many
factors, such as load current, input voltage, output voltage and switching frequency. In all cases, ensure that the
Rev.B
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15
LTM8065
APPLICATIONS INFORMATION
maximum voltage at the BIAS pin is less than 19V. If BIAS
power is applied from a remote or noisy voltage source, it
may be necessary to apply a decoupling capacitor locally
to the pin. A 1µF ceramic capacitor works well. If BIAS is
unused, tie this pin to GND.
Maximum Load
The maximum practical continuous load that the LTM8065
can drive, while rated at 2.5A, actually depends upon both
the internal current limit and the internal temperature.
The internal current limit is designed to prevent damage
to the LTM8065 in the case of overload or short-circuit.
The internal temperature of the LTM8065 depends upon
operating conditions such as the ambient temperature,
the power delivered, and the heat sinking capability of
the system. For example, if the LTM8065 is configured
to regulate at 1.2V, it may continuously deliver 3.5A from
12VIN if the ambient temperature is controlled to less than
55°C. This is quite a bit higher than the 2.5A continuous
rating. Please see the “Derating, VOUT = 1.2V” curve in
the Typical Performance Characteristics section. Similarly,
if the output voltage is 18V and the ambient temperature
is 100°C, the LTM8065 will deliver at most 0.15A from
36VIN, which is less than the 2.5A continuous rating.
Load Sharing
The LTM8065 is not designed to load share.
Burst Mode Operation
To enhance efficiency at light loads, the LTM8065 automatically switches to Burst Mode operation which keeps
the output capacitor charged to the proper voltage while
minimizing the input quiescent current. During Burst
Mode operation, the LTM8065 delivers single cycle bursts
of current to the output capacitor followed by sleep periods
where most of the internal circuitry is powered off and
energy is delivered to the load by the output capacitor.
During the sleep time, VIN and BIAS quiescent currents
are greatly reduced, so, as the load current decreases
towards a no load condition, the percentage of time that
the LTM8065 operates in sleep mode increases and the
average input current is greatly reduced, resulting in
higher light load efficiency.
Burst Mode operation is enabled by tying SYNC to GND.
Minimum Input Voltage
The LTM8065 is a step-down converter, so a minimum
amount of headroom is required to keep the output in
regulation. Keep the input above 3.4V to ensure proper
operation. Voltage transients or ripple valleys that cause
the input to fall below 3.4V may turn off the LTM8065.
Output Voltage Tracking and Soft-Start
The LTM8065 allows the user to adjust its output voltage
ramp rate by means of the TR/SS pin. An internal 2μA pulls
up the TR/SS pin to about 2.4V. Putting an external capacitor on TR/SS enables soft starting the output to reduce
current surges on the input supply. During the soft-start
ramp the output voltage will proportionally track the TR/
SS pin voltage. For output tracking applications, TR/SS
can be externally driven by another voltage source. From
0V to 0.97V, the TR/SS voltage will override the internal
0.97V reference input to the error amplifier, thus regulating the FB pin voltage to that of the TR/SS pin. When TR/
SS is above 0.97V, tracking is disabled and the feedback
voltage will regulate to the internal reference voltage. The
TR/SS pin may be left floating if the function is not needed.
An active pull-down circuit is connected to the TR/SS pin
which will discharge the external soft-start capacitor in
the case of fault conditions and restart the ramp when the
faults are cleared. Fault conditions that clear the soft-start
capacitor are the RUN pin transitioning low, VIN voltage
falling too low, or thermal shutdown.
Pre-Biased Output
As discussed in the Output Voltage Tracking and SoftStart section, the LTM8065 regulates the output to the
FB voltage determined by the TR/SS pin whenever TR/
SS is less than 0.97V. If the LTM8065 output is higher
than the target output voltage, the LTM8065 will attempt
to regulate the output to the target voltage by returning a
small amount of energy back to the input supply. If there
is nothing loading the input supply, its voltage may rise.
Take care that it does not rise so high that the input voltage
exceeds the absolute maximum rating of the LTM8065.
Rev.B
16
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LTM8065
APPLICATIONS INFORMATION
Frequency Foldback
The LTM8065 is equipped with frequency foldback which
acts to reduce the thermal and energy stress on the internal
power elements during a short circuit or output overload
condition. If the LTM8065 detects that the output has
fallen out of regulation, the switching frequency is reduced
as a function of how far the output is below the target
voltage. This in turn limits the amount of energy that can
be delivered to the load under fault. During the start-up
time, frequency foldback is also active to limit the energy
delivered to the potentially large output capacitance of
the load. When a clock is applied to the SYNC pin, the
SYNC pin is floated or held high, the frequency foldback
is disabled, and the switching frequency will slow down
only during overcurrent conditions.
Synchronization
To select low ripple Burst Mode operation, tie the SYNC
pin below about 0.4V (this can be ground or a logic low
output). To synchronize the LTM8065 oscillator to an
external frequency, connect a square wave (with about
20% to 80% duty cycle) to the SYNC pin. The square
wave amplitude should have valleys that are below 0.4V
and peaks above 1.5V.
The LTM8065 will not enter Burst Mode operation at low
output loads while synchronized to an external clock, but
instead will pulse skip to maintain regulation. The LTM8065
may be synchronized over a 200kHz to 3MHz range. The RT
resistor should be chosen to set the switching frequency
equal to or below the lowest synchronization input. For
example, if the synchronization signal will be 500kHz and
higher, the RT should be selected for 500kHz.
For some applications it is desirable for the LTM8065 to
operate in pulse-skipping mode, offering two major differences from Burst Mode operation. The first is that the
clock stays awake at all times and all switching cycles
are aligned to the clock. The second is that full switching
frequency is reached at lower output load than in Burst
Mode operation. These two differences come at the expense
of increased quiescent current. To enable pulse-skipping
mode, the SYNC pin is floated.
The LTM8065 features spread spectrum operation to
further reduce EMI/EMC emissions. To enable spread
spectrum operation, apply between 2.9V and 4.2V to the
SYNC pin. In this mode, triangular frequency modulation
is used to vary the switching frequency between the value
programmed by RT to about 20% higher than that value.
The modulation frequency is about 3kHz. For example, when
the LTM8065 is programmed to 2MHz, the frequency will
vary from 2MHz to 2.4MHz at a 3kHz rate. When spread
spectrum operation is selected, Burst Mode operation is
disabled, and the part will run in pulse-skipping mode.
The LTM8065 does not operate in forced continuous mode
regardless of SYNC signal.
Negative Output
The LTM8065 is capable of generating a negative output
voltage by connecting its VOUT to system GND and the
LTM8065 GND to the negative voltage rail. An example
of this is shown in the Typical Applications section. The
most versatile way to generate a negative output is to
use a dedicated regulator that was designed to generate
a negative voltage, but using a buck regulator like the
LTM8065 to generate a negative voltage is a simple and
cost effective solution, as long as certain restrictions are
kept in mind.
Figure 1 shows a typical negative output voltage application.
Note that LTM8065 VOUT is tied to system GND and input
power is applied from VIN to LTM8065 VOUT. As a result,
the LTM8065 is not behaving as a true buck regulator,
and the maximum output current depends upon the input
voltage. In the example shown in the Typical Applications
section, there is an attending graph that shows how much
current the LTM8065 can deliver for given input voltages.
Note that this configuration requires that any load current
transient will directly impress the transient voltage onto
VIN
VIN
VOUT
LTM8065
GND
NEGATIVE
OUTPUT VOLTAGE
8065 F01
Figure 1. The LTM8065 Can Be Used to Generate a Negative Voltage
Rev.B
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17
LTM8065
APPLICATIONS INFORMATION
the LTM8065 GND, as shown in Figure 2, so fast load
transients can disrupt the LTM8065’s operation or even
cause damage.
VIN
VIN
VOUT
LTM8065
GND
FAST LOAD
TRANSIENT
OUTPUT TRANSIENT
RESPONSE
8065 F02
Figure 2. Any Output Voltage Transient Appears on LTM8065 GND
The CIN and COUT capacitors in Figure 3 form an AC divider
at the negative output voltage node. If VIN is hot-plugged
or rises quickly, the resultant VOUT will be a positive transient, which may be unhealthy for the application load.
An anti-parallel Schottky diode may be able to prevent
this positive transient from damaging the load. The location of this Schottky diode is important. For example, in
a system where the LTM8065 is far away from the load,
placing the Schottky diode closest to the most sensitive
load component may be the best design choice. Carefully
evaluate whether the negative buck configuration is suitable
for the application. For negative outputs, connect BIAS to
LTM8065 GND.
FAST VIN
TRANSIENT
OUTPUT EXPERIENCES
A POSITIVE TRANSIENT
VIN
VIN
CIN
VOUT
LTM8065
COUT
GND
AC DIVIDER
OPTIONAL
SCHOTTKY
DIODE
8065 F03
Figure 3. A Schottky Diode Can Limit the Transient
Caused by a Fast Rising VIN to Safe Levels
Shorted Input Protection
Care needs to be taken in systems where the output is held
high when the input to the LTM8065 is absent. This may
occur in battery charging applications or in battery backup
systems where a battery or some other supply is diode
ORed with the LTM8065’s output. If the VIN pin is allowed
to float and the RUN pin is held high (either by a logic signal
or because it is tied to VIN), then the LTM8065’s internal
circuitry pulls its quiescent current through its internal
power switch. This is fine if your system can tolerate a
few milliamps in this state. If you ground the RUN pin, the
internal current drops to essentially zero. However, if the
VIN pin is grounded while the output is held high, parasitic
diodes inside the LTM8065 can pull large currents from
the output through the VIN pin. Figure 4 shows a circuit
that runs only when the input voltage is present and that
protects against a shorted or reversed input.
VIN
VIN
LTM8065
RUN
8065 F04
Figure 4. The Input Diode Prevents a Shorted Input from
Discharging a Backup Battery Tied to the Output. It Also
Protects the Circuit from a Reversed Input. The LTM8065
Runs Only When the Input Is Present
PCB Layout
Most of the headaches associated with PCB layout have
been alleviated or even eliminated by the high level of
integration of the LTM8065. The LTM8065 is nevertheless a switching power supply, and care must be taken to
minimize EMI and ensure proper operation. Even with the
high level of integration, you may fail to achieve specified
operation with a haphazard or poor layout. See Figure 5
for a suggested layout. Ensure that the grounding and
heat sinking are acceptable.
A few rules to keep in mind are:
1. Place CFF, RFB and RT as close as possible to their
respective pins.
2. Place the CIN capacitor as close as possible to the VIN
and GND connection of the LTM8065.
3. Place the COUT capacitor as close as possible to the
VOUT and GND connection of the LTM8065.
Rev.B
18
For more information www.analog.com
LTM8065
APPLICATIONS INFORMATION
4. Place the CIN and COUT capacitors such that their
ground current flow directly adjacent to or underneath
the LTM8065.
5. Connect all of the GND connections to as large a copper
pour or plane area as possible on the top layer. Avoid
breaking the ground connection between the external
components and the LTM8065.
6. Use vias to connect the GND copper area to the board’s
internal ground planes. Liberally distribute these GND vias
to provide both a good ground connection and thermal
path to the internal planes of the printed circuit board. Pay
attention to the location and density of the thermal vias in
Figure 5. The LTM8065 can benefit from the heat-sinking
afforded by vias that connect to internal GND planes at
these locations, due to their proximity to internal power
handling components. The optimum number of thermal
vias depends upon the printed circuit board design. For
example, a board might use very small via holes. It should
employ more thermal vias than a board that uses larger
holes.
VIN
GND
GND
CIN
RUN
RT
PG
BIAS AUX
FB
RFB
GND/THERMAL VIAS
The small size, robustness and low impedance of ceramic
capacitors make them an attractive option for the input
bypass capacitor of LTM8065. However, these capacitors
can cause problems if the LTM8065 is plugged into a live
supply (see Linear Technology Application Note 88 for a
complete discussion). The low loss ceramic capacitor
combined with stray inductance in series with the power
source forms an underdamped tank circuit, and the voltage at the VIN pin of the LTM8065 can ring to more than
twice the nominal input voltage, possibly exceeding the
LTM8065’s rating and damaging the part. If the input supply
is poorly controlled or the LTM8065 is hot-plugged into an
energized supply, the input network should be designed
to prevent this overshoot. This can be accomplished by
installing a small resistor in series to VIN, but the most
popular method of controlling input voltage overshoot is
add an electrolytic bulk cap to the VIN net. This capacitor’s
relatively high equivalent series resistance damps the circuit
and eliminates the voltage overshoot. The extra capacitor
improves low frequency ripple filtering and can slightly
improve the efficiency of the circuit, though it is likely to
be the largest component in the circuit.
Thermal Considerations
RT TR/SS
SYNC
GND
Hot-Plugging Safely
GND
COUT
VOUT
8065 F05
Figure 5. Layout Showing Suggested External
Components, GND Plane and Thermal Vias
The LTM8065 output current may need to be derated if it
is required to operate in a high ambient temperature. The
amount of current derating is dependent upon the input
voltage, output power and ambient temperature. The
derating curves given in the Typical Performance Characteristics section can be used as a guide. These curves
were generated by the LTM8065 mounted to a 58cm2
4-layer FR4 printed circuit board. Boards of other sizes
and layer count can exhibit different thermal behavior, so
it is incumbent upon the user to verify proper operation
over the intended system’s line, load and environmental
operating conditions.
Rev.B
For more information www.analog.com
19
LTM8065
APPLICATIONS INFORMATION
For increased accuracy and fidelity to the actual application, many designers use FEA (Finite Element Analysis)
to predict thermal performance. To that end, Page 2 of
the data sheet typically gives four thermal coefficients:
to operate such that most of the heat flows from the junction to the top of the part. As in the case of θJCbottom, this
value may be useful for comparing packages but the test
conditions don’t generally match the user’s application.
θJA – Thermal resistance from junction to ambient
θJB is the junction-to-board thermal resistance where
almost all of the heat flows through the bottom of the
µModule regulator and into the board, and is really the
sum of the θJCbottom and the thermal resistance of the
bottom of the part through the solder joints and through a
portion of the board. The board temperature is measured
a specified distance from the package, using a two sided,
two layer board. This board is described in JESD 51-9.
θJCbottom – Thermal resistance from junction to the
bottom of the product case
θJCtop – Thermal resistance from junction to top of the
product case
θJB – Thermal resistance from junction to the printed
circuit board.
While the meaning of each of these coefficients may
seem to be intuitive, JEDEC has defined each to avoid
confusion and inconsistency. These definitions are given
in JESD 51-12, and are quoted or paraphrased below:
θJA is the natural convection junction-to-ambient air
thermal resistance measured in a one cubic foot sealed
enclosure. This environment is sometimes referred to as
“still air” although natural convection causes the air to
move. This value is determined with the part mounted to
a JESD 51-9 defined test board, which does not reflect an
actual application or viable operating condition.
θJCbottom is the junction-to-board thermal resistance with
all of the component power dissipation flowing through the
bottom of the package. In the typical µModule regulator,
the bulk of the heat flows out the bottom of the package,
but there is always heat flow out into the ambient environment. As a result, this thermal resistance value may
be useful for comparing packages but the test conditions
don’t generally match the user’s application.
θJCtop is determined with nearly all of the component power
dissipation flowing through the top of the package. As the
electrical connections of the typical µModule regulator are
on the bottom of the package, it is rare for an application
Given these definitions, it should now be apparent that none
of these thermal coefficients reflects an actual physical
operating condition of a µModule regulator. Thus, none
of them can be individually used to accurately predict the
thermal performance of the product. Likewise, it would
be inappropriate to attempt to use any one coefficient to
correlate to the junction temperature vs load graphs given
in the product’s data sheet. The only appropriate way to
use the coefficients is when running a detailed thermal
analysis, such as FEA, which considers all of the thermal
resistances simultaneously.
A simplified graphical representation of these thermal
resistances is given in Figure 6. The blue resistances are
contained within the µModule regulator, and the green
are outside.
The die temperature of the LTM8065 must be lower than
the maximum rating, so care should be taken in the layout
of the circuit to ensure good heat sinking of the LTM8065.
The bulk of the heat flow out of the LTM8065 is through
the bottom of the package and the pads into the printed
circuit board. Consequently a poor printed circuit board
design can cause excessive heating, resulting in impaired
performance or reliability. Please refer to the PCB Layout
section for printed circuit board design suggestions.
Rev.B
20
For more information www.analog.com
LTM8065
APPLICATIONS INFORMATION
JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)
JUNCTION-TO-CASE (TOP)
RESISTANCE
JUNCTION
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION-TO-CASE
CASE (BOTTOM)-TO-BOARD
(BOTTOM) RESISTANCE
RESISTANCE
AMBIENT
BOARD-TO-AMBIENT
RESISTANCE
8065 F06
µMODULE DEVICE
Figure 6. Simplified Graphical Representation of the Thermal Resistance Between the Device Junction and Ambient
Rev.B
For more information www.analog.com
21
LTM8065
TYPICAL APPLICATIONS
1.2VOUT from 3.4VIN to 40VIN Step-Down Converter. BIAS Is Tied to an External 3.3V Source
VIN
VIN
3.4V TO 40V
LTM8065
RUN
BIAS
2.2µF
3.3V
VOUT
1.2V
100µF 2.5A
VOUT
47pF
RT
78.7k
550kHz
GND
SYNC
FB
1.05M
8065 TA02
PINS NOT USED IN THIS CIRCUIT: TR/SS, PG
2.5VOUT from 5.5VIN to 15VIN Step-Down Converter. BIAS Is Tied to VIN
VIN
VIN
5.5V TO 15V
LTM8065
BIAS
RUN
VOUT
2.2µF
RT
45.3k
900kHz
GND
SYNC
FB
47µF
158k
VOUT
2.5V
2.5A
8065 TA03
PINS NOT USED IN THIS CIRCUIT: TR/SS, PG
–5VOUT from 3.4VIN to 35VIN Positive to Negative Converter
Maximum Load Current vs VIN,
BIAS tied to LTM8065 GND
INPUT BULK CAP
4
VIN
LTM8065
RUN
41.2k
1MHz
OPTIONAL
SCHOTTKY
DIODE
VOUT
2.2µF
RT
FB
GND
SYNC
BIAS
60.4k
22µF
8065 TA04a
VOUT
–5V
PINS NOT USED IN THIS CIRCUIT:
TR/SS, PG, AUX
MAXIMUM LOAD CURRENT (A)
+
VIN
3.4V TO 35V
3
2
1
0
INPUT BULK CAP: PLACE THE INPUT BULK CAP BETWEEN VIN AND VOUT (SYSTEM GROUND)
TO MITIGATE THE OUTPUT POSITIVE TRANSIENT WHEN VIN RISES QUICKLY.
0
10
20
30
INPUT VOLTAGE (V)
40
8065 TA04b
Rev.B
22
For more information www.analog.com
LTM8065
PACKAGE PHOTO
PACKAGE DESCRIPTION
Table 3. LTM8065 Pinout (Sorted by Pin Number)
PIN
PIN NAME
PIN
PIN NAME
PIN
PIN NAME
PIN
PIN NAME
PIN
PIN NAME
PIN
PIN NAME
A
1
GND
B
1
FB
C
1
GND
D
1
GND
E
1
GND
F
1
VOUT
A
2
BIAS
B
2
AUX
C
2
GND
D
2
GND
E
2
GND
F
2
VOUT
A
3
PG
B
3
GND
C
3
VIN
D
3
GND
E
3
GND
F
3
VOUT
A
4
GND
B
4
SYNC
C
4
VIN
D
4
GND
E
4
GND
F
4
VOUT
A
5
RT
B
5
TR/SS
C
5
VIN
D
5
GND
E
5
GND
F
5
VOUT
A
6
GND
B
6
RUN
C
6
VIN
D
6
GND
E
6
GND
F
6
VOUT
Rev.B
For more information www.analog.com
23
aaa Z
0.50 ±0.025 Ø 36x
E
2.5
2.5
SUGGESTED PCB LAYOUT
TOP VIEW
0.000
PACKAGE TOP VIEW
1.5
For more information www.analog.com
0.5
4
0.5
PIN “A1”
CORNER
1.5
Y
2.5
1.5
0.5
0.000
0.5
1.5
2.5
X
D
aaa Z
// bbb Z
MAX
2.52
0.60
1.92
0.70
0.53
DIMENSIONS
NOM
2.32
0.50
1.82
0.60
0.50
6.25
6.25
1.00
5.00
5.00
0.32
1.50
BALL DIMENSION
PAD DIMENSION
BALL HT
NOTES
DETAIL B
PACKAGE SIDE VIEW
A2
A
SUBSTRATE THK
0.37
MOLD CAP HT
1.55
0.15
0.10
0.20
0.25
0.10
TOTAL NUMBER OF BALLS: 36
0.27
1.45
MIN
2.12
0.40
1.72
0.50
0.47
H1
SUBSTRATE
ddd M Z X Y
eee M Z
DETAIL A
Øb (36 PLACES)
SYMBOL
A
A1
A2
b
b1
D
E
e
F
G
H1
H2
aaa
bbb
ccc
ddd
eee
b1
DETAIL B
H2
MOLD
CAP
ccc Z
A1
F
e
b
6
4
G
3
e
2
PACKAGE BOTTOM VIEW
b
5
1
DETAIL A
6
3
SEE NOTES
F
E
D
C
B
A
PIN 1
SEE NOTES
DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
4
6
TRAY PIN 1
BEVEL
!
PACKAGE IN TRAY LOADING ORIENTATION
LTMXXXXXX
µModule
BGA 36 0517 REV A
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
5. PRIMARY DATUM -Z- IS SEATING PLANE
BALL DESIGNATION PER JEP95
3
2. ALL DIMENSIONS ARE IN MILLIMETERS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
COMPONENT
PIN “A1”
(Reference LTC DWG # 05-08-1998 Rev A)
Z
24
Z
BGA Package
36-Lead (6.25mm × 6.25mm × 2.32mm)
LTM8065
PACKAGE DESCRIPTION
Rev.B
LTM8065
REVISION HISTORY
REV
DATE
DESCRIPTION
A
01/18
Added note on Positive to Negative Converter Application Circuit
PAGE NUMBER
22
B
09/18
Updated package thermal resistance
2
θJA = 20°C/W to 21°C/W, θJCbottom 5.3°C/W to 5.9°C/W
θJCtop = 24.5°C/W to 36.5°C/W, θJB 5.0°C/W to 6.3°C/W
Added clarification of BIAS Pin: If unused, tie BIAS Pin to GND
Updated BIAS Pin condition = 5V to (3.2V to 19V)
11,13,16
14
(Table 1)
Rev.B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
morebyinformation
subject to change without notice. No license isFor
granted
implication orwww.analog.com
otherwise under any patent or patent rights of Analog Devices.
25
LTM8065
TYPICAL APPLICATION
0.97VOUT from 3.4VIN to 40VIN Step Down Converter with Spread Spectrum. BIAS is Tied to an External 3.3V Source
VIN
VIN
3.4V TO 40V
LTM8065
RUN
2.2µF
VOUT
0.97V
2.5A
VOUT
47pF
RT
100k
450kHz
100µF
FB
GND
SYNC BIAS
8065 TA05
EXTERNAL
3.3V
PINS NOT USED IN THIS CIRCUIT: TR/SS, PG, AUX
DESIGN RESOURCES
SUBJECT
DESCRIPTION
µModule Design and Manufacturing Resources
Design:
• Selector Guides
• Demo Boards and Gerber Files
• Free Simulation Tools
µModule Regulator Products Search
1. Sort table of products by parameters and download the result as a spread sheet.
Manufacturing:
• Quick Start Guide
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability
2. Search using the Quick Power Search parametric table.
TechClip Videos
Quick videos detailing how to bench test electrical and thermal performance of µModule products.
Digital Power System Management
Linear Technology’s family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTM8053
40V, 3.5A Step-Down µModule Regulator
3.4V ≤ VIN ≤ 40V. 0.97V ≤ VOUT ≤ 15V. 6.25mm x 9mm x 3.32mm BGA Package.
LTM8032
36V, 2A Low EMI Step-Down µModule Regulator
3.6V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 10V. EN55022B Compliant.
LTM8033
36V, 3A Low EMI Step-Down µModule Regulator
3.6V ≤ VIN ≤ 36V. 0.8V ≤ VOUT ≤ 24V. EN55022B Compliant.
LTM8026
36V, 5A CVCC Step-Down µModule Regulator
6V ≤ VIN ≤ 36V. 1.2V ≤ VOUT ≤ 24V. Constant Voltage Constant Current Operation.
LTM4613
36V, 8A Low EMI Step-Down µModule Regulator
5V ≤ VIN ≤ 36V. 3.3V ≤ VOUT ≤ 15V. EN55022B Compliant.
LTM8027
60V, 4A Step-Down µModule Regulator
4.5V ≤ VIN ≤ 60V, 2.5V ≤ VOUT ≤ 24V.
LTM8050
58V, 2A Step-Down µModule Regulator
3.6V ≤ VIN ≤ 58V, 0.8V ≤ VOUT ≤ 24V.
LTM8003
3.5A Version of LTM8002, 40V, 3.5A, IQ = 25µA
FMEA Compliant
3.4V ≤ VIN ≤ 40V, 0.97V ≤ VOUT ≤ 18V, 6.25mm × 9mm × 3.32 BGA Package.
LTM8002
FMEA Compliant Pinout, 40A, 2.5A Step-Down
µModule Regulator
3.4V ≤ VIN ≤ 40V, 0.97V ≤ VOUT ≤ 18V, 6.25mm × 6.25mm × 2.32mm BGA Package.
Rev.B
26
09/18
For more information www.analog.com
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