MAT03

a FEATURES Dual Matched PNP Transistor Low Offset Voltage: 100 V max Low Noise: 1 nV/ √Hz @ 1 kHz max High Gain: 100 min High Gain Bandwidth: 190 MHz typ Tight Gain Matching: 3% max Excellent Logarithmic Conformance: rBE Available in Die Form Low Noise, Matched Dual PNP Transistor MAT03 PIN CONNECTION TO-78 (H Suffix) 0.3 typ GENERAL DESCRIPTION The MAT03 dual monolithic PNP transistor offers excellent parametric matching and high frequency performance. Low noise characteristics (1 nV/√Hz max @ 1 kHz), high bandwidth (190 MHz typical), and low offset voltage (100 µV max), makes the MAT03 an excellent choice for demanding preamplifier applications. Tight current gain matching (3% max mismatch) and high current gain (100 min), over a wide range of collector current, makes the MAT03 an excellent choice for current mirrors. A low value of bulk resistance (typically 0.3 Ω) also makes the MAT03 an ideal component for applications requiring accurate logarithmic conformance. Each transistor is individually tested to data sheet specifications. Device performance is guaranteed at 25°C and over the extended industrial and military temperature ranges. To insure the longterm stability of the matching parameters, internal protection diodes across the base-emitter junction clamp any reverse baseemitter junction potential. This prevents a base-emitter breakdown condition which can result in degradation of gain and matching performance due to excessive breakdown current. R EV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 MAT03–SPECIFICATIONS ELECTRICAL CHARACTERISTICS Parameter Current Gain 1 (@ TA = +25 C, unless otherwise noted.) MAT03A MAT03E Min Typ Max Min Typ Max 165 150 120 0.5 40 11 11 12 12 0.3 0.3 6 50 0.8 0.7 0.7 0.7 100 90 80 3 100 150 150 50 50 0.75 0.75 35 200 2 1 1 1 165 150 120 0.5 40 11 11 12 12 0.3 0.3 6 50 0.8 0.7 0.7 0.7 0.025 0.1 MAT03F Min Typ Max 80 70 60 3 100 150 150 50 50 0.75 0.75 35 200 165 150 120 0.5 40 11 11 12 12 0.3 0.3 6 50 0.8 0.7 0.7 0.7 0.025 0.1 Units Symbol hFE Conditions Current Gain Matching 2 Offset Voltage3 Offset Voltage Change vs. Collector Voltage Offset Voltage Change vs. Collector Current Bulk Resistance Offset Current Collector-Base Leakage Current Noise Voltage Density 4 DhFE VOS DVOS/DVCB DVOS/DIC rBE IOS ICB0 eN VCB = 0 V, –36 V 100 IC = 1 mA 90 IC = 100 µA 80 IC = 10 µA IC = 100 µA,VCB = 0 V VCB = 0 V, IC = 100 µA IC = 100 µA VCB1 = 0 V VCB2 = –36 V VCB = 0 V IC1 = 10 µA, IC2 = 1 mA VCB = 0 V 10 µA ≤ IC ≤ 1 mA IC = 100 µA, VCB = 0 V VCB = –36 V = VMAX IC = 1 mA, VCB = 0 fO = 10 Hz fO = 100 Hz fO = 1 kHz fO = 10 kHz IC = 1 mA, IB = 100 µA 6 200 200 200 75 75 0.75 0.75 45 400 % µV µV µV µV µV Ω Ω nA pA nV/÷ Hz nV/÷ Hz nV/÷ Hz nV/÷ Hz V Collector Saturation Voltage VCE(SAT) 0.025 0.1 ELECTRICAL CHARACTERISTICS (at –55 C ≤ T ≤ +125 C, unless otherwise noted.) A Parameter Current Gain Symbol hFE Conditions VCB = 0 V, –36 V I C = 1 mA IC = 100 µA IC = 10 µA IC = 100 µA, VCB = 0 V IC = 100 µA, VCB = 0 V IC = 100 µA, VCB = 0 V Min 70 60 50 MAT03A Typ 110 100 85 40 0.3 15 54 Max Units Offset Voltage Offset Voltage Drift5 Offset Current Breakdown Voltage VOS TCVOS IOS BVCEO 150 0.5 85 36 µV µV/°C nA V ELECTRICAL CHARACTERISTICS (at –40 C ≤ T ≤ +85 C, unless otherwise noted.) A Parameter Symbol Conditions MAT03E Min Typ Max MAT03F Min Typ Max Units Current Gain hFE Offset Voltage Offset Voltage Drift5 Offset Current Breakdown Voltage VOS TCVOS IOS BVCEO VCB = 0 V, –36 V IC = 1 m A IC = 100 µA IC = 10 µA IC = 100 µA, VCB = 0 V IC = 100 µA, VCB = 0 V IC = 100 µA, VCB = 0 V 70 60 50 120 105 90 30 135 0.3 0.5 10 85 60 50 40 120 105 90 30 265 0.3 1.0 10 200 36 36 µV µV/°C nA V NOTES 1 Current gain is measured at collector-base voltages (V CB) swept from 0 to V MAX at indicated collector current. Typicals are measured at V CB = 0 V. 2Current 3Offset gain matching ( ∆hFE) is defined as: ∆hFE = 100 ( ∆I B ) hFE (min ) IC . KT q In voltage is defined as: V OS = VBE1 – VBE2, where VOS is the differential voltage for I C1 = IC2: VOS = VBE1 – VBE2 = 4 Sample tested. Noise tested and specified as equivalent input voltage for each transistor. 5 Guaranteed by V OS test (TCVOS = VOS/T for VOS VBE) where T = 298°K for TA = 25°C. Specifications subject to change without notice.  I C1  I .  C2  –2– REV. B MAT03 WAFER TEST LIMITS (at 25 C, unless otherwise noted.) Parameter Symbol Conditions MAT03N Limits Units Breakdown Voltage Offset Voltage Current Gain Current Gain Match Offset Voltage Change vs. VCB Offset Voltage Change vs. Collector Current Bulk Resistance Collector Saturation Voltage BVCEO VOS hFE ∆hFE ∆VOS/∆VCB ∆VOS/∆IC rBE VCE (SAT) IC = 100 µA, VCB = 0 V 10 µA ≤ IC ≤ 1 mA IC = 1 mA, VCB = 0 V, –36 V IC = 10 µA, VCB = 0 V, –36 V IC = 100 µA, VCB = 0 V VCB1 = 0 V, IC = 100 µA VCB2 = –36 V VCB = 0 IC1 = 10 µA, IC2 = 1 mA 10 µA ≤ IC ≤ 1 mA IC = 1 mA, IB = 100 µA 36 200 200 80 60 6 200 200 75 75 0.75 0.1 V min µV max µV max min min % max µV max µV max µV max µV max Ω max V max NOTE: Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing. DICE CHARACTERISTICS 1. COLLECTOR (1 ) 2. BASE (1 ) 3. EMITTER (1 ) 4. COLLECTOR (2) 5. BASE (2) 6. EMITTER (2 ) SUBSTRATE CAN BE CONNECTED TO V– OR FLOATED ABSOLUTE MAXIMUM RATINGS 1 ORDERING GUIDE1 Model VOS max Temperature (TA = +25 C) Range –55°C to +125°C –40°C to +85°C –40°C to +85°C Package Option TO-78 TO-78 TO-78 Collector-Base Voltage (BVCBO) . . . . . . . . . . . . . . . . . . . . 36 V Collector-Emitter Voltage (BVCEO) . . . . . . . . . . . . . . . . . . 36 V Collector-Collector Voltage (BVCC) . . . . . . . . . . . . . . . . . . 36 V Emitter-Emitter Voltage (BVEE) . . . . . . . . . . . . . . . . . . . . . 36 V Collector Current (IC) . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Emitter Current (IE) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Total Power Dissipation Ambient Temperature ≤ 70°C2 . . . . . . . . . . . . . . . . 500 mW Operating Temperature Range MAT03A . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C MAT03E/F . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Operating Junction Temperature . . . . . . . . . . –55°C to +150°C Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . +300°C Junction Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C NOTES 1 Absolute maximum ratings apply to both DICE and packaged devices. 2 Rating applies to TO-78 not using a heat sink, and LCC; devices in free air only. For TO-78, derate linearly at 6.3 mW/ °C above 70 °C ambient temperature; for LCC, derate at 7.8 mW/ °C. MAT03AH2 100 µV MAT03EH 100 µV MAT03FH 200 µV NOTES 1 Burn-in is available on industrial temperature range parts. 2 For devices processed in total compliance to MIL-STD-883, add/883 after part number. Consult factory for 883 data sheet. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the MAT03 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. B –3– MAT03 Figure 1. Current Gain vs. Collector Current Figure 2. Current Gain vs. Temperature Figure 3. Gain Bandwidth vs. Collector Current Figure 4. Base-Emitter Voltage vs. Collector Current Figure 5. Small-Signal Input Resistance (hie) vs. Collector Current Figure 6. Small Signal Output Conductance (hoe) vs. Collector Current – 4– REV. B MAT03 Figure 7. Saturation Voltage vs. Collector Current Figure 8. Noise Voltage Density vs. Frequency Figure 9. Noise Voltage Density Figure 10. Total Noise vs. Collector Current Figure 11. Collector-Base Capacitance vs. VCB REV. B –5– MAT03 Figure 12. SPICE or SABER Model APPLICATIONS INFORMATION MAT03 MODELS MAT03 NOISE MEASUREMENT The MAT03 model (Figure 12) includes parasitic diodes D3 through D6. D1 and D2 are internal protection diodes which prevent zenering of the base-emitter junctions. The analysis programs, SPICE and SABER, are primarily used in evaluating the functional performance of systems. The models are provided only as an aid in utilizing these simulation programs. All resistive components (Johnson noise, en2 = 4kTBR, or en = 0.13√R nV/√Hz, where R is in kΩ) and semiconductor junctions (Shot noise, caused by current flowing through a junction, produces voltage noise in series impedances such as transistorcollector load resistors, In = 0.566 √I pA/√Hz where I is in µA) contribute to the system input noise. Figure 13 illustrates a technique for measuring the equivalent input noise voltage of the MAT03. 1 mA of stage current is used Figure 13. MAT03 Voltage Noise Measurement Circuit – 6– REV. B MAT03 to bias each side of the differential pair. The 5 kΩ collector resistors noise contribution is insignificant compared to the voltage noise of the MAT03. Since noise in the signal path is referred back to the input, this voltage noise is attenuated by the gain of the circuit. Consequently, the noise contribution of the collector load resistors is only 0.048 nV/√Hz. This is considerably less than the typical 0.8 nV/√Hz input noise voltage of the MAT03 transistor. The noise contribution of the OP27 gain stages is also negligible due to the gain in the signal path. The op amp stages amplify the input referred noise of the transistors to increase the signal strength to allow the noise spectral density (ein × 10000) to be measured with a spectrum analyzer. And, since we assume equal noise contributions from each transistor in the MAT03, the output is divided by √2 to determine a single transistor’s input noise. Air currents cause small temperature changes that can appear as low frequency noise. To eliminate this noise source, the measurement circuit must be thermally isolated. Effects of extraneous noise sources must also be eliminated by totally shielding the circuit. SUPER LOW NOISE AMPLIFIER The circuit in Figure 14a is a super low noise amplifier with equivalent input voltage noise of 0.32 nV/√Hz. By paralleling three MAT03 matched pairs, a further reduction of amplifier noise is attained by a reduction of the base spreading resistance by a factor of 3, and consequently the noise by √3. Additionally, the shot noise contribution is reduced by maintaining a high collector current (2 mA/device) which reduces the dynamic emitter resistance and decreases voltage noise. The voltage noise is inversely proportional to the square root of the stage current, and current noise increases proportionally to the square root of the stage current. Accordingly, this amplifier capitalizes on voltage noise reduction techniques at the expense of increasing the current noise. However, high current noise is not usually important when dealing with low impedance sources. Figure 14a. Super Low Noise Amplifier REV. B –7– MAT03 This amplifier exhibits excellent full power ac performance, 0.08% THD into a 600 Ω load, making it suitable for exacting audio applications (see Figure 14b). and the VBE of a silicon transistor is predictable and constant (to a few percent) over a wide temperature range. The voltage difference, approximately 1 V, is dropped across the 250 Ω resistor which produces a temperature stabilized emitter current. CURRENT SOURCES A fundamental requirement for accurate current mirrors and active load stages is matched transistor components. Due to the excellent VBE matching (the voltage difference between VBE’s required to equalize collector current) and gain matching, the MAT03 can be used to implement a variety of standard current mirrors that can source current into a load such as an amplifier stage. The advantages of current loads in amplifiers versus resistors is an increase of voltage gain due to higher impedances, larger signal range, and in many applications a wider signal bandwidth. Figure 16 illustrates a cascode current mirror consisting of two MAT03 transistor pairs. Figure 14b. Super Low Noise Amplifier—Total Harmonic Distortion LOW NOISE MICROPHONE PREAMPLIFIER Figure 15 shows a microphone preamplifier that consists of a MAT03 and a low noise op amp. The input stage operates at a relatively high quiescent current of 2 mA per side, which reduces the MAT03 transistor’s voltage noise. The 1/ƒ corner is less than 1 Hz. Total harmonic distortion is under 0.005% for a 10 V p-p signal from 20 Hz to 20 kHz. The preamp gain is 100, but can be modified by varying R5 or R6 (VOUT/VIN = R5/R6 + 1). A total input stage emitter current of 4 mA is provided by Q2. The constant current in Q2 is set by using the forward voltage of a GaAsP LED as a reference. The difference between this voltage The cascode current source has a common base transistor in series with the output which causes an increase in output impedance of the current source since VCE stays relatively constant. High frequency characteristics are improved due to a reduction of Miller capacitance. The small-signal output impedance can be determined by consulting “hOF vs. Collector Current” typical graph. Typical output impedance levels approach the performance of a perfect current source. Considering a typical collector current of 100 µA, we have: roQ3 = 1.0 µMHOS = 1 MΩ 1 Figure 15. Low Noise Microphone Preamplifier – 8– REV. B MAT03 Q2 and Q3 are in series and operate at the same current levels so the total output impedance is: RO = hFE roQ3 @ (160)(1 MΩ) = 160 MΩ. Since Q2 buffers Q3, both transistors in the MAT03, Q1 and Q3, maintain the same collector current. D2 and D3 form a Baker clamp which prevents Q2 from turning off, thereby improving the switching speed of the current mirror. The feedback serves to increase the output impedance and improves accuracy by reducing the base-width modulation which occurs with varying collector-emitter voltages. Accuracy and linearity performance of the current pump is summarized in Figure 19. Figure 16. Cascode Current Source Figure 17a. Current Matching Circuit CURRENT MATCHING The objective of current source or mirror design is generation of currents that are either matched or must maintain a constant ratio. However, mismatch of base-emitter voltages cause output current errors. Consider the example of Figure 17a. If the resistors and transistors are equal and the collector voltages are the same, the collector currents will match precisely. Investigating the current-matching errors resulting from a nonzero VOS, we define ∆IC as the current error between the two transistors. Graph 17b describes the relationship of current matching errors versus offset voltage for a specified average current IC. Note that since the relative error between the currents is exponentially proportional to the offset voltage, tight matching is required to design high accuracy current sources. For example, if the offset voltage is 5 mV at 100 µA collector current, the current matching error would be 20%. Additionally, temperature effects such as offset drift (3 µV/°C per mV of VOS) will degrade performance if Q1 and Q2 are not well matched. DIGITALLY PROGRAMMABLE BIPOLAR CURRENT PUMP Figure 17b. Current Matching Accuracy % vs. Offset Voltage The circuit of Figure 18 is a digitally programmable current pump. The current pump incorporates a DAC08, and a fast Wilson current source using the MAT03. Examining Figure 18, the DAC08 is set for 2 mA full-scale range so that bipolar current operation of ± 2 mA is achieved. The Wilson current mirror maintains linearity within the LSB range of the 8-bit DAC08 (± 2 mA/256 = 15.6 µA resolution) as seen in Figure 19. A negative feedback path established by Q2 regulates the collector current so that it matches the reference current programmed by the DAC08. Collector-emitter voltages across both Q1 and Q3 are matched by D1, with Q3’s collector-emitter voltage remaining constant, independent of the voltage across the current source output. Figure 18. Digitally Programmable Bipolar Current Pump REV. B –9– MAT03 The full-scale output of the DAC08, IOUT, is a linear function of IREF IFR = 256 256 × IREF, and IOUT + IOUT = IREF 256 256 The current mirror output is IOUT – IOUT = 1, so that if IREF = 2 mA: I = 2 IOUT – 1.992 mA  Input Code  = 2  256  (2 mA) – 1.992 mA.   DIGITAL CURRENT PUMP CODING Figure 19. Digitally Programmable Current Pump—INL Error as Digital Code Digital Input B1 . . . B8 FULL RANGE HALF-RANGE ZERO-SCALE 1111 1111 1000 0000 0000 0000 Output Current I = 1.992 mA I = 0.008 mA I = –1.992 mA – 10– REV. B MAT03 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). TO-78 Metal Can REFERENCE PLANE 0.185 (4.70) 0.165 (4.19) 0.750 (19.05) 0.500 (12.70) 0.250 (6.35) MIN 0.050 (1.27) MAX 4 0.100 (2.54) BSC 0.160 (4.06) 0.110 (2.79) 5 0.200 (5.08) BSC 3 2 0.019 (0.48) 0.016 (0.41) 0.040 (1.02) MAX 0.045 (1.14) 0.010 (0.25) 0.021 (0.53) 0.016 (0.41) BASE & SEATING PLANE 0.100 (2.54) BSC 1 0.034 (0.86) 0.027 (0.69) 45° BSC 6 0.370 (9.40) 0.335 (8.51) 0.335 (8.51) 0.305 (7.75) 0.045 (1.14) 0.027 (0.69) REV. B –11– – 12– 000000000 PRINTED IN U.S.A.